drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #define SWSMU_CODE_LAYER_L1
  24
  25 #include <linux/firmware.h>
  26 #include <linux/pci.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_smu.h"
  30 #include "smu_internal.h"
  31 #include "atom.h"
  32 #include "arcturus_ppt.h"
  33 #include "navi10_ppt.h"
  34 #include "sienna_cichlid_ppt.h"
  35 #include "renoir_ppt.h"
  36 #include "amd_pcie.h"
  37
  38 /*
  39  * DO NOT use these for err/warn/info/debug messages.
  40  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  41  * They are more MGPU friendly.
  42  */
  43 #undef pr_err
  44 #undef pr_warn
  45 #undef pr_info
  46 #undef pr_debug
  47
  48 size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
  49 {
  50         size_t size = 0;
  51
  52         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
  53                 return -EOPNOTSUPP;
  54
  55         mutex_lock(&smu->mutex);
  56
  57         size = smu_get_pp_feature_mask(smu, buf);
  58
  59         mutex_unlock(&smu->mutex);
  60
  61         return size;
  62 }
  63
  64 int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask)
  65 {
  66         int ret = 0;
  67
  68         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
  69                 return -EOPNOTSUPP;
  70
  71         mutex_lock(&smu->mutex);
  72
  73         ret = smu_set_pp_feature_mask(smu, new_mask);
  74
  75         mutex_unlock(&smu->mutex);
  76
  77         return ret;
  78 }
  79
  80 int smu_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value)
  81 {
  82         int ret = 0;
  83         struct smu_context *smu = &adev->smu;
  84
  85         if (is_support_sw_smu(adev) && smu->ppt_funcs->get_gfx_off_status)
  86                 *value = smu_get_gfx_off_status(smu);
  87         else
  88                 ret = -EINVAL;
  89
  90         return ret;
  91 }
  92
  93 int smu_set_soft_freq_range(struct smu_context *smu,
  94                             enum smu_clk_type clk_type,
  95                             uint32_t min,
  96                             uint32_t max)
  97 {
  98         int ret = 0;
  99
 100         mutex_lock(&smu->mutex);
 101
 102         if (smu->ppt_funcs->set_soft_freq_limited_range)
 103                 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu,
 104                                                                   clk_type,
 105                                                                   min,
 106                                                                   max);
 107
 108         mutex_unlock(&smu->mutex);
 109
 110         return ret;
 111 }
 112
 113 int smu_get_dpm_freq_range(struct smu_context *smu,
 114                            enum smu_clk_type clk_type,
 115                            uint32_t *min,
 116                            uint32_t *max)
 117 {
 118         int ret = 0;
 119
 120         if (!min && !max)
 121                 return -EINVAL;
 122
 123         mutex_lock(&smu->mutex);
 124
 125         if (smu->ppt_funcs->get_dpm_ultimate_freq)
 126                 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu,
 127                                                             clk_type,
 128                                                             min,
 129                                                             max);
 130
 131         mutex_unlock(&smu->mutex);
 132
 133         return ret;
 134 }
 135
 136 static int smu_dpm_set_vcn_enable_locked(struct smu_context *smu,
 137                                          bool enable)
 138 {
 139         struct smu_power_context *smu_power = &smu->smu_power;
 140         struct smu_power_gate *power_gate = &smu_power->power_gate;
 141         int ret = 0;
 142
 143         if (!smu->ppt_funcs->dpm_set_vcn_enable)
 144                 return 0;
 145
 146         if (atomic_read(&power_gate->vcn_gated) ^ enable)
 147                 return 0;
 148
 149         ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable);
 150         if (!ret)
 151                 atomic_set(&power_gate->vcn_gated, !enable);
 152
 153         return ret;
 154 }
 155
 156 static int smu_dpm_set_vcn_enable(struct smu_context *smu,
 157                                   bool enable)
 158 {
 159         struct smu_power_context *smu_power = &smu->smu_power;
 160         struct smu_power_gate *power_gate = &smu_power->power_gate;
 161         int ret = 0;
 162
 163         mutex_lock(&power_gate->vcn_gate_lock);
 164
 165         ret = smu_dpm_set_vcn_enable_locked(smu, enable);
 166
 167         mutex_unlock(&power_gate->vcn_gate_lock);
 168
 169         return ret;
 170 }
 171
 172 static int smu_dpm_set_jpeg_enable_locked(struct smu_context *smu,
 173                                           bool enable)
 174 {
 175         struct smu_power_context *smu_power = &smu->smu_power;
 176         struct smu_power_gate *power_gate = &smu_power->power_gate;
 177         int ret = 0;
 178
 179         if (!smu->ppt_funcs->dpm_set_jpeg_enable)
 180                 return 0;
 181
 182         if (atomic_read(&power_gate->jpeg_gated) ^ enable)
 183                 return 0;
 184
 185         ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable);
 186         if (!ret)
 187                 atomic_set(&power_gate->jpeg_gated, !enable);
 188
 189         return ret;
 190 }
 191
 192 static int smu_dpm_set_jpeg_enable(struct smu_context *smu,
 193                                    bool enable)
 194 {
 195         struct smu_power_context *smu_power = &smu->smu_power;
 196         struct smu_power_gate *power_gate = &smu_power->power_gate;
 197         int ret = 0;
 198
 199         mutex_lock(&power_gate->jpeg_gate_lock);
 200
 201         ret = smu_dpm_set_jpeg_enable_locked(smu, enable);
 202
 203         mutex_unlock(&power_gate->jpeg_gate_lock);
 204
 205         return ret;
 206 }
 207
 208 /**
 209  * smu_dpm_set_power_gate - power gate/ungate the specific IP block
 210  *
 211  * @smu:        smu_context pointer
 212  * @block_type: the IP block to power gate/ungate
 213  * @gate:       to power gate if true, ungate otherwise
 214  *
 215  * This API uses no smu->mutex lock protection due to:
 216  * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce).
 217  *    This is guarded to be race condition free by the caller.
 218  * 2. Or get called on user setting request of power_dpm_force_performance_level.
 219  *    Under this case, the smu->mutex lock protection is already enforced on
 220  *    the parent API smu_force_performance_level of the call path.
 221  */
 222 int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
 223                            bool gate)
 224 {
 225         int ret = 0;
 226
 227         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
 228                 return -EOPNOTSUPP;
 229
 230         switch (block_type) {
 231         /*
 232          * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses
 233          * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept.
 234          */
 235         case AMD_IP_BLOCK_TYPE_UVD:
 236         case AMD_IP_BLOCK_TYPE_VCN:
 237                 ret = smu_dpm_set_vcn_enable(smu, !gate);
 238                 if (ret)
 239                         dev_err(smu->adev->dev, "Failed to power %s VCN!\n",
 240                                 gate ? "gate" : "ungate");
 241                 break;
 242         case AMD_IP_BLOCK_TYPE_GFX:
 243                 ret = smu_gfx_off_control(smu, gate);
 244                 if (ret)
 245                         dev_err(smu->adev->dev, "Failed to %s gfxoff!\n",
 246                                 gate ? "enable" : "disable");
 247                 break;
 248         case AMD_IP_BLOCK_TYPE_SDMA:
 249                 ret = smu_powergate_sdma(smu, gate);
 250                 if (ret)
 251                         dev_err(smu->adev->dev, "Failed to power %s SDMA!\n",
 252                                 gate ? "gate" : "ungate");
 253                 break;
 254         case AMD_IP_BLOCK_TYPE_JPEG:
 255                 ret = smu_dpm_set_jpeg_enable(smu, !gate);
 256                 if (ret)
 257                         dev_err(smu->adev->dev, "Failed to power %s JPEG!\n",
 258                                 gate ? "gate" : "ungate");
 259                 break;
 260         default:
 261                 dev_err(smu->adev->dev, "Unsupported block type!\n");
 262                 return -EINVAL;
 263         }
 264
 265         return ret;
 266 }
 267
 268 int smu_get_power_num_states(struct smu_context *smu,
 269                              struct pp_states_info *state_info)
 270 {
 271         if (!state_info)
 272                 return -EINVAL;
 273
 274         /* not support power state */
 275         memset(state_info, 0, sizeof(struct pp_states_info));
 276         state_info->nums = 1;
 277         state_info->states[0] = POWER_STATE_TYPE_DEFAULT;
 278
 279         return 0;
 280 }
 281
 282 bool is_support_sw_smu(struct amdgpu_device *adev)
 283 {
 284         if (adev->asic_type >= CHIP_ARCTURUS)
 285                 return true;
 286
 287         return false;
 288 }
 289
 290 int smu_sys_get_pp_table(struct smu_context *smu, void **table)
 291 {
 292         struct smu_table_context *smu_table = &smu->smu_table;
 293         uint32_t powerplay_table_size;
 294
 295         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
 296                 return -EOPNOTSUPP;
 297
 298         if (!smu_table->power_play_table && !smu_table->hardcode_pptable)
 299                 return -EINVAL;
 300
 301         mutex_lock(&smu->mutex);
 302
 303         if (smu_table->hardcode_pptable)
 304                 *table = smu_table->hardcode_pptable;
 305         else
 306                 *table = smu_table->power_play_table;
 307
 308         powerplay_table_size = smu_table->power_play_table_size;
 309
 310         mutex_unlock(&smu->mutex);
 311
 312         return powerplay_table_size;
 313 }
 314
 315 int smu_sys_set_pp_table(struct smu_context *smu,  void *buf, size_t size)
 316 {
 317         struct smu_table_context *smu_table = &smu->smu_table;
 318         ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf;
 319         int ret = 0;
 320
 321         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
 322                 return -EOPNOTSUPP;
 323
 324         if (header->usStructureSize != size) {
 325                 dev_err(smu->adev->dev, "pp table size not matched !\n");
 326                 return -EIO;
 327         }
 328
 329         mutex_lock(&smu->mutex);
 330         if (!smu_table->hardcode_pptable)
 331                 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL);
 332         if (!smu_table->hardcode_pptable) {
 333                 ret = -ENOMEM;
 334                 goto failed;
 335         }
 336
 337         memcpy(smu_table->hardcode_pptable, buf, size);
 338         smu_table->power_play_table = smu_table->hardcode_pptable;
 339         smu_table->power_play_table_size = size;
 340
 341         /*
 342          * Special hw_fini action(for Navi1x, the DPMs disablement will be
 343          * skipped) may be needed for custom pptable uploading.
 344          */
 345         smu->uploading_custom_pp_table = true;
 346
 347         ret = smu_reset(smu);
 348         if (ret)
 349                 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret);
 350
 351         smu->uploading_custom_pp_table = false;
 352
 353 failed:
 354         mutex_unlock(&smu->mutex);
 355         return ret;
 356 }
 357
 358 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu)
 359 {
 360         struct smu_feature *feature = &smu->smu_feature;
 361         int ret = 0;
 362         uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32];
 363
 364         mutex_lock(&feature->mutex);
 365         bitmap_zero(feature->allowed, SMU_FEATURE_MAX);
 366         mutex_unlock(&feature->mutex);
 367
 368         ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask,
 369                                              SMU_FEATURE_MAX/32);
 370         if (ret)
 371                 return ret;
 372
 373         mutex_lock(&feature->mutex);
 374         bitmap_or(feature->allowed, feature->allowed,
 375                       (unsigned long *)allowed_feature_mask,
 376                       feature->feature_num);
 377         mutex_unlock(&feature->mutex);
 378
 379         return ret;
 380 }
 381
 382 static int smu_set_funcs(struct amdgpu_device *adev)
 383 {
 384         struct smu_context *smu = &adev->smu;
 385
 386         if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
 387                 smu->od_enabled = true;
 388
 389         switch (adev->asic_type) {
 390         case CHIP_NAVI10:
 391         case CHIP_NAVI14:
 392         case CHIP_NAVI12:
 393                 navi10_set_ppt_funcs(smu);
 394                 break;
 395         case CHIP_ARCTURUS:
 396                 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
 397                 arcturus_set_ppt_funcs(smu);
 398                 /* OD is not supported on Arcturus */
 399                 smu->od_enabled =false;
 400                 break;
 401         case CHIP_SIENNA_CICHLID:
 402         case CHIP_NAVY_FLOUNDER:
 403                 sienna_cichlid_set_ppt_funcs(smu);
 404                 break;
 405         case CHIP_RENOIR:
 406                 renoir_set_ppt_funcs(smu);
 407                 break;
 408         default:
 409                 return -EINVAL;
 410         }
 411
 412         return 0;
 413 }
 414
 415 static int smu_early_init(void *handle)
 416 {
 417         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 418         struct smu_context *smu = &adev->smu;
 419
 420         smu->adev = adev;
 421         smu->pm_enabled = !!amdgpu_dpm;
 422         smu->is_apu = false;
 423         mutex_init(&smu->mutex);
 424
 425         return smu_set_funcs(adev);
 426 }
 427
 428 static int smu_set_default_dpm_table(struct smu_context *smu)
 429 {
 430         struct smu_power_context *smu_power = &smu->smu_power;
 431         struct smu_power_gate *power_gate = &smu_power->power_gate;
 432         int vcn_gate, jpeg_gate;
 433         int ret = 0;
 434
 435         if (!smu->ppt_funcs->set_default_dpm_table)
 436                 return 0;
 437
 438         mutex_lock(&power_gate->vcn_gate_lock);
 439         mutex_lock(&power_gate->jpeg_gate_lock);
 440
 441         vcn_gate = atomic_read(&power_gate->vcn_gated);
 442         jpeg_gate = atomic_read(&power_gate->jpeg_gated);
 443
 444         ret = smu_dpm_set_vcn_enable_locked(smu, true);
 445         if (ret)
 446                 goto err0_out;
 447
 448         ret = smu_dpm_set_jpeg_enable_locked(smu, true);
 449         if (ret)
 450                 goto err1_out;
 451
 452         ret = smu->ppt_funcs->set_default_dpm_table(smu);
 453         if (ret)
 454                 dev_err(smu->adev->dev,
 455                         "Failed to setup default dpm clock tables!\n");
 456
 457         smu_dpm_set_jpeg_enable_locked(smu, !jpeg_gate);
 458 err1_out:
 459         smu_dpm_set_vcn_enable_locked(smu, !vcn_gate);
 460 err0_out:
 461         mutex_unlock(&power_gate->jpeg_gate_lock);
 462         mutex_unlock(&power_gate->vcn_gate_lock);
 463
 464         return ret;
 465 }
 466
 467 static int smu_late_init(void *handle)
 468 {
 469         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 470         struct smu_context *smu = &adev->smu;
 471         int ret = 0;
 472
 473         if (!smu->pm_enabled)
 474                 return 0;
 475
 476         ret = smu_set_default_od_settings(smu);
 477         if (ret) {
 478                 dev_err(adev->dev, "Failed to setup default OD settings!\n");
 479                 return ret;
 480         }
 481
 482         /*
 483          * Set initialized values (get from vbios) to dpm tables context such as
 484          * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each
 485          * type of clks.
 486          */
 487         ret = smu_set_default_dpm_table(smu);
 488         if (ret) {
 489                 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n");
 490                 return ret;
 491         }
 492
 493         ret = smu_populate_umd_state_clk(smu);
 494         if (ret) {
 495                 dev_err(adev->dev, "Failed to populate UMD state clocks!\n");
 496                 return ret;
 497         }
 498
 499         ret = smu_get_asic_power_limits(smu);
 500         if (ret) {
 501                 dev_err(adev->dev, "Failed to get asic power limits!\n");
 502                 return ret;
 503         }
 504
 505         smu_get_unique_id(smu);
 506
 507         smu_handle_task(&adev->smu,
 508                         smu->smu_dpm.dpm_level,
 509                         AMD_PP_TASK_COMPLETE_INIT,
 510                         false);
 511
 512         return 0;
 513 }
 514
 515 static int smu_init_fb_allocations(struct smu_context *smu)
 516 {
 517         struct amdgpu_device *adev = smu->adev;
 518         struct smu_table_context *smu_table = &smu->smu_table;
 519         struct smu_table *tables = smu_table->tables;
 520         struct smu_table *driver_table = &(smu_table->driver_table);
 521         uint32_t max_table_size = 0;
 522         int ret, i;
 523
 524         /* VRAM allocation for tool table */
 525         if (tables[SMU_TABLE_PMSTATUSLOG].size) {
 526                 ret = amdgpu_bo_create_kernel(adev,
 527                                               tables[SMU_TABLE_PMSTATUSLOG].size,
 528                                               tables[SMU_TABLE_PMSTATUSLOG].align,
 529                                               tables[SMU_TABLE_PMSTATUSLOG].domain,
 530                                               &tables[SMU_TABLE_PMSTATUSLOG].bo,
 531                                               &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
 532                                               &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
 533                 if (ret) {
 534                         dev_err(adev->dev, "VRAM allocation for tool table failed!\n");
 535                         return ret;
 536                 }
 537         }
 538
 539         /* VRAM allocation for driver table */
 540         for (i = 0; i < SMU_TABLE_COUNT; i++) {
 541                 if (tables[i].size == 0)
 542                         continue;
 543
 544                 if (i == SMU_TABLE_PMSTATUSLOG)
 545                         continue;
 546
 547                 if (max_table_size < tables[i].size)
 548                         max_table_size = tables[i].size;
 549         }
 550
 551         driver_table->size = max_table_size;
 552         driver_table->align = PAGE_SIZE;
 553         driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM;
 554
 555         ret = amdgpu_bo_create_kernel(adev,
 556                                       driver_table->size,
 557                                       driver_table->align,
 558                                       driver_table->domain,
 559                                       &driver_table->bo,
 560                                       &driver_table->mc_address,
 561                                       &driver_table->cpu_addr);
 562         if (ret) {
 563                 dev_err(adev->dev, "VRAM allocation for driver table failed!\n");
 564                 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
 565                         amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
 566                                               &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
 567                                               &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
 568         }
 569
 570         return ret;
 571 }
 572
 573 static int smu_fini_fb_allocations(struct smu_context *smu)
 574 {
 575         struct smu_table_context *smu_table = &smu->smu_table;
 576         struct smu_table *tables = smu_table->tables;
 577         struct smu_table *driver_table = &(smu_table->driver_table);
 578
 579         if (!tables)
 580                 return 0;
 581
 582         if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
 583                 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
 584                                       &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
 585                                       &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
 586
 587         amdgpu_bo_free_kernel(&driver_table->bo,
 588                               &driver_table->mc_address,
 589                               &driver_table->cpu_addr);
 590
 591         return 0;
 592 }
 593
 594 /**
 595  * smu_alloc_memory_pool - allocate memory pool in the system memory
 596  *
 597  * @smu: amdgpu_device pointer
 598  *
 599  * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr
 600  * and DramLogSetDramAddr can notify it changed.
 601  *
 602  * Returns 0 on success, error on failure.
 603  */
 604 static int smu_alloc_memory_pool(struct smu_context *smu)
 605 {
 606         struct amdgpu_device *adev = smu->adev;
 607         struct smu_table_context *smu_table = &smu->smu_table;
 608         struct smu_table *memory_pool = &smu_table->memory_pool;
 609         uint64_t pool_size = smu->pool_size;
 610         int ret = 0;
 611
 612         if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO)
 613                 return ret;
 614
 615         memory_pool->size = pool_size;
 616         memory_pool->align = PAGE_SIZE;
 617         memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT;
 618
 619         switch (pool_size) {
 620         case SMU_MEMORY_POOL_SIZE_256_MB:
 621         case SMU_MEMORY_POOL_SIZE_512_MB:
 622         case SMU_MEMORY_POOL_SIZE_1_GB:
 623         case SMU_MEMORY_POOL_SIZE_2_GB:
 624                 ret = amdgpu_bo_create_kernel(adev,
 625                                               memory_pool->size,
 626                                               memory_pool->align,
 627                                               memory_pool->domain,
 628                                               &memory_pool->bo,
 629                                               &memory_pool->mc_address,
 630                                               &memory_pool->cpu_addr);
 631                 if (ret)
 632                         dev_err(adev->dev, "VRAM allocation for dramlog failed!\n");
 633                 break;
 634         default:
 635                 break;
 636         }
 637
 638         return ret;
 639 }
 640
 641 static int smu_free_memory_pool(struct smu_context *smu)
 642 {
 643         struct smu_table_context *smu_table = &smu->smu_table;
 644         struct smu_table *memory_pool = &smu_table->memory_pool;
 645
 646         if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO)
 647                 return 0;
 648
 649         amdgpu_bo_free_kernel(&memory_pool->bo,
 650                               &memory_pool->mc_address,
 651                               &memory_pool->cpu_addr);
 652
 653         memset(memory_pool, 0, sizeof(struct smu_table));
 654
 655         return 0;
 656 }
 657
 658 static int smu_smc_table_sw_init(struct smu_context *smu)
 659 {
 660         int ret;
 661
 662         /**
 663          * Create smu_table structure, and init smc tables such as
 664          * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc.
 665          */
 666         ret = smu_init_smc_tables(smu);
 667         if (ret) {
 668                 dev_err(smu->adev->dev, "Failed to init smc tables!\n");
 669                 return ret;
 670         }
 671
 672         /**
 673          * Create smu_power_context structure, and allocate smu_dpm_context and
 674          * context size to fill the smu_power_context data.
 675          */
 676         ret = smu_init_power(smu);
 677         if (ret) {
 678                 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n");
 679                 return ret;
 680         }
 681
 682         /*
 683          * allocate vram bos to store smc table contents.
 684          */
 685         ret = smu_init_fb_allocations(smu);
 686         if (ret)
 687                 return ret;
 688
 689         ret = smu_alloc_memory_pool(smu);
 690         if (ret)
 691                 return ret;
 692
 693         ret = smu_i2c_init(smu, &smu->adev->pm.smu_i2c);
 694         if (ret)
 695                 return ret;
 696
 697         return 0;
 698 }
 699
 700 static int smu_smc_table_sw_fini(struct smu_context *smu)
 701 {
 702         int ret;
 703
 704         smu_i2c_fini(smu, &smu->adev->pm.smu_i2c);
 705
 706         ret = smu_free_memory_pool(smu);
 707         if (ret)
 708                 return ret;
 709
 710         ret = smu_fini_fb_allocations(smu);
 711         if (ret)
 712                 return ret;
 713
 714         ret = smu_fini_power(smu);
 715         if (ret) {
 716                 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n");
 717                 return ret;
 718         }
 719
 720         ret = smu_fini_smc_tables(smu);
 721         if (ret) {
 722                 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n");
 723                 return ret;
 724         }
 725
 726         return 0;
 727 }
 728
 729 static void smu_throttling_logging_work_fn(struct work_struct *work)
 730 {
 731         struct smu_context *smu = container_of(work, struct smu_context,
 732                                                throttling_logging_work);
 733
 734         smu_log_thermal_throttling(smu);
 735 }
 736
 737 static int smu_sw_init(void *handle)
 738 {
 739         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 740         struct smu_context *smu = &adev->smu;
 741         int ret;
 742
 743         smu->pool_size = adev->pm.smu_prv_buffer_size;
 744         smu->smu_feature.feature_num = SMU_FEATURE_MAX;
 745         mutex_init(&smu->smu_feature.mutex);
 746         bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX);
 747         bitmap_zero(smu->smu_feature.enabled, SMU_FEATURE_MAX);
 748         bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX);
 749
 750         mutex_init(&smu->smu_baco.mutex);
 751         smu->smu_baco.state = SMU_BACO_STATE_EXIT;
 752         smu->smu_baco.platform_support = false;
 753
 754         mutex_init(&smu->sensor_lock);
 755         mutex_init(&smu->metrics_lock);
 756         mutex_init(&smu->message_lock);
 757
 758         INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn);
 759         atomic64_set(&smu->throttle_int_counter, 0);
 760         smu->watermarks_bitmap = 0;
 761         smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 762         smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 763
 764         atomic_set(&smu->smu_power.power_gate.vcn_gated, 1);
 765         atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1);
 766         mutex_init(&smu->smu_power.power_gate.vcn_gate_lock);
 767         mutex_init(&smu->smu_power.power_gate.jpeg_gate_lock);
 768
 769         smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
 770         smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
 771         smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;
 772         smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2;
 773         smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3;
 774         smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4;
 775         smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5;
 776         smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6;
 777
 778         smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 779         smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
 780         smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING;
 781         smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO;
 782         smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR;
 783         smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE;
 784         smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM;
 785         smu->display_config = &adev->pm.pm_display_cfg;
 786
 787         smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
 788         smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
 789         ret = smu_init_microcode(smu);
 790         if (ret) {
 791                 dev_err(adev->dev, "Failed to load smu firmware!\n");
 792                 return ret;
 793         }
 794
 795         ret = smu_smc_table_sw_init(smu);
 796         if (ret) {
 797                 dev_err(adev->dev, "Failed to sw init smc table!\n");
 798                 return ret;
 799         }
 800
 801         ret = smu_register_irq_handler(smu);
 802         if (ret) {
 803                 dev_err(adev->dev, "Failed to register smc irq handler!\n");
 804                 return ret;
 805         }
 806
 807         return 0;
 808 }
 809
 810 static int smu_sw_fini(void *handle)
 811 {
 812         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 813         struct smu_context *smu = &adev->smu;
 814         int ret;
 815
 816         ret = smu_smc_table_sw_fini(smu);
 817         if (ret) {
 818                 dev_err(adev->dev, "Failed to sw fini smc table!\n");
 819                 return ret;
 820         }
 821
 822         smu_fini_microcode(smu);
 823
 824         return 0;
 825 }
 826
 827 static int smu_get_thermal_temperature_range(struct smu_context *smu)
 828 {
 829         struct amdgpu_device *adev = smu->adev;
 830         struct smu_temperature_range *range =
 831                                 &smu->thermal_range;
 832         int ret = 0;
 833
 834         if (!smu->ppt_funcs->get_thermal_temperature_range)
 835                 return 0;
 836
 837         ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range);
 838         if (ret)
 839                 return ret;
 840
 841         adev->pm.dpm.thermal.min_temp = range->min;
 842         adev->pm.dpm.thermal.max_temp = range->max;
 843         adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max;
 844         adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min;
 845         adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max;
 846         adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max;
 847         adev->pm.dpm.thermal.min_mem_temp = range->mem_min;
 848         adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max;
 849         adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max;
 850
 851         return ret;
 852 }
 853
 854 static int smu_smc_hw_setup(struct smu_context *smu)
 855 {
 856         struct amdgpu_device *adev = smu->adev;
 857         uint32_t pcie_gen = 0, pcie_width = 0;
 858         int ret;
 859
 860         if (adev->in_suspend && smu_is_dpm_running(smu)) {
 861                 dev_info(adev->dev, "dpm has been enabled\n");
 862                 return 0;
 863         }
 864
 865         ret = smu_init_display_count(smu, 0);
 866         if (ret) {
 867                 dev_info(adev->dev, "Failed to pre-set display count as 0!\n");
 868                 return ret;
 869         }
 870
 871         ret = smu_set_driver_table_location(smu);
 872         if (ret) {
 873                 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n");
 874                 return ret;
 875         }
 876
 877         /*
 878          * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools.
 879          */
 880         ret = smu_set_tool_table_location(smu);
 881         if (ret) {
 882                 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n");
 883                 return ret;
 884         }
 885
 886         /*
 887          * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify
 888          * pool location.
 889          */
 890         ret = smu_notify_memory_pool_location(smu);
 891         if (ret) {
 892                 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n");
 893                 return ret;
 894         }
 895
 896         /* smu_dump_pptable(smu); */
 897         /*
 898          * Copy pptable bo in the vram to smc with SMU MSGs such as
 899          * SetDriverDramAddr and TransferTableDram2Smu.
 900          */
 901         ret = smu_write_pptable(smu);
 902         if (ret) {
 903                 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n");
 904                 return ret;
 905         }
 906
 907         /* issue Run*Btc msg */
 908         ret = smu_run_btc(smu);
 909         if (ret)
 910                 return ret;
 911
 912         ret = smu_feature_set_allowed_mask(smu);
 913         if (ret) {
 914                 dev_err(adev->dev, "Failed to set driver allowed features mask!\n");
 915                 return ret;
 916         }
 917
 918         ret = smu_system_features_control(smu, true);
 919         if (ret) {
 920                 dev_err(adev->dev, "Failed to enable requested dpm features!\n");
 921                 return ret;
 922         }
 923
 924         if (!smu_is_dpm_running(smu))
 925                 dev_info(adev->dev, "dpm has been disabled\n");
 926
 927         if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
 928                 pcie_gen = 3;
 929         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
 930                 pcie_gen = 2;
 931         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
 932                 pcie_gen = 1;
 933         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
 934                 pcie_gen = 0;
 935
 936         /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
 937          * Bit 15:8:  PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
 938          * Bit 7:0:   PCIE lane width, 1 to 7 corresponds is x1 to x32
 939          */
 940         if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
 941                 pcie_width = 6;
 942         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
 943                 pcie_width = 5;
 944         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
 945                 pcie_width = 4;
 946         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
 947                 pcie_width = 3;
 948         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
 949                 pcie_width = 2;
 950         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
 951                 pcie_width = 1;
 952         ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width);
 953         if (ret) {
 954                 dev_err(adev->dev, "Attempt to override pcie params failed!\n");
 955                 return ret;
 956         }
 957
 958         ret = smu_get_thermal_temperature_range(smu);
 959         if (ret) {
 960                 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n");
 961                 return ret;
 962         }
 963
 964         ret = smu_enable_thermal_alert(smu);
 965         if (ret) {
 966                 dev_err(adev->dev, "Failed to enable thermal alert!\n");
 967                 return ret;
 968         }
 969
 970         ret = smu_disable_umc_cdr_12gbps_workaround(smu);
 971         if (ret) {
 972                 dev_err(adev->dev, "Workaround failed to disable UMC CDR feature on 12Gbps SKU!\n");
 973                 return ret;
 974         }
 975
 976         /*
 977          * For Navi1X, manually switch it to AC mode as PMFW
 978          * may boot it with DC mode.
 979          */
 980         ret = smu_set_power_source(smu,
 981                                    adev->pm.ac_power ? SMU_POWER_SOURCE_AC :
 982                                    SMU_POWER_SOURCE_DC);
 983         if (ret) {
 984                 dev_err(adev->dev, "Failed to switch to %s mode!\n", adev->pm.ac_power ? "AC" : "DC");
 985                 return ret;
 986         }
 987
 988         ret = smu_notify_display_change(smu);
 989         if (ret)
 990                 return ret;
 991
 992         /*
 993          * Set min deep sleep dce fclk with bootup value from vbios via
 994          * SetMinDeepSleepDcefclk MSG.
 995          */
 996         ret = smu_set_min_dcef_deep_sleep(smu,
 997                                           smu->smu_table.boot_values.dcefclk / 100);
 998         if (ret)
 999                 return ret;
1000
1001         return ret;
1002 }
1003
1004 static int smu_start_smc_engine(struct smu_context *smu)
1005 {
1006         struct amdgpu_device *adev = smu->adev;
1007         int ret = 0;
1008
1009         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1010                 if (adev->asic_type < CHIP_NAVI10) {
1011                         if (smu->ppt_funcs->load_microcode) {
1012                                 ret = smu->ppt_funcs->load_microcode(smu);
1013                                 if (ret)
1014                                         return ret;
1015                         }
1016                 }
1017         }
1018
1019         if (smu->ppt_funcs->check_fw_status) {
1020                 ret = smu->ppt_funcs->check_fw_status(smu);
1021                 if (ret) {
1022                         dev_err(adev->dev, "SMC is not ready\n");
1023                         return ret;
1024                 }
1025         }
1026
1027         /*
1028          * Send msg GetDriverIfVersion to check if the return value is equal
1029          * with DRIVER_IF_VERSION of smc header.
1030          */
1031         ret = smu_check_fw_version(smu);
1032         if (ret)
1033                 return ret;
1034
1035         return ret;
1036 }
1037
1038 static int smu_hw_init(void *handle)
1039 {
1040         int ret;
1041         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1042         struct smu_context *smu = &adev->smu;
1043
1044         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) {
1045                 smu->pm_enabled = false;
1046                 return 0;
1047         }
1048
1049         ret = smu_start_smc_engine(smu);
1050         if (ret) {
1051                 dev_err(adev->dev, "SMC engine is not correctly up!\n");
1052                 return ret;
1053         }
1054
1055         if (smu->is_apu) {
1056                 smu_powergate_sdma(&adev->smu, false);
1057                 smu_dpm_set_vcn_enable(smu, true);
1058                 smu_dpm_set_jpeg_enable(smu, true);
1059                 smu_set_gfx_cgpg(&adev->smu, true);
1060         }
1061
1062         if (!smu->pm_enabled)
1063                 return 0;
1064
1065         /* get boot_values from vbios to set revision, gfxclk, and etc. */
1066         ret = smu_get_vbios_bootup_values(smu);
1067         if (ret) {
1068                 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n");
1069                 return ret;
1070         }
1071
1072         ret = smu_setup_pptable(smu);
1073         if (ret) {
1074                 dev_err(adev->dev, "Failed to setup pptable!\n");
1075                 return ret;
1076         }
1077
1078         ret = smu_get_driver_allowed_feature_mask(smu);
1079         if (ret)
1080                 return ret;
1081
1082         ret = smu_smc_hw_setup(smu);
1083         if (ret) {
1084                 dev_err(adev->dev, "Failed to setup smc hw!\n");
1085                 return ret;
1086         }
1087
1088         /*
1089          * Move maximum sustainable clock retrieving here considering
1090          * 1. It is not needed on resume(from S3).
1091          * 2. DAL settings come between .hw_init and .late_init of SMU.
1092          *    And DAL needs to know the maximum sustainable clocks. Thus
1093          *    it cannot be put in .late_init().
1094          */
1095         ret = smu_init_max_sustainable_clocks(smu);
1096         if (ret) {
1097                 dev_err(adev->dev, "Failed to init max sustainable clocks!\n");
1098                 return ret;
1099         }
1100
1101         adev->pm.dpm_enabled = true;
1102
1103         dev_info(adev->dev, "SMU is initialized successfully!\n");
1104
1105         return 0;
1106 }
1107
1108 static int smu_disable_dpms(struct smu_context *smu)
1109 {
1110         struct amdgpu_device *adev = smu->adev;
1111         int ret = 0;
1112         bool use_baco = !smu->is_apu &&
1113                 ((adev->in_gpu_reset &&
1114                   (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) ||
1115                  ((adev->in_runpm || adev->in_hibernate) && amdgpu_asic_supports_baco(adev)));
1116
1117         /*
1118          * For custom pptable uploading, skip the DPM features
1119          * disable process on Navi1x ASICs.
1120          *   - As the gfx related features are under control of
1121          *     RLC on those ASICs. RLC reinitialization will be
1122          *     needed to reenable them. That will cost much more
1123          *     efforts.
1124          *
1125          *   - SMU firmware can handle the DPM reenablement
1126          *     properly.
1127          */
1128         if (smu->uploading_custom_pp_table &&
1129             (adev->asic_type >= CHIP_NAVI10) &&
1130             (adev->asic_type <= CHIP_NAVI12))
1131                 return 0;
1132
1133         /*
1134          * For Sienna_Cichlid, PMFW will handle the features disablement properly
1135          * on BACO in. Driver involvement is unnecessary.
1136          */
1137         if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
1138              use_baco)
1139                 return 0;
1140
1141         /*
1142          * For gpu reset, runpm and hibernation through BACO,
1143          * BACO feature has to be kept enabled.
1144          */
1145         if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) {
1146                 ret = smu_disable_all_features_with_exception(smu,
1147                                                               SMU_FEATURE_BACO_BIT);
1148                 if (ret)
1149                         dev_err(adev->dev, "Failed to disable smu features except BACO.\n");
1150         } else {
1151                 ret = smu_system_features_control(smu, false);
1152                 if (ret)
1153                         dev_err(adev->dev, "Failed to disable smu features.\n");
1154         }
1155
1156         if (adev->asic_type >= CHIP_NAVI10 &&
1157             adev->gfx.rlc.funcs->stop)
1158                 adev->gfx.rlc.funcs->stop(adev);
1159
1160         return ret;
1161 }
1162
1163 static int smu_smc_hw_cleanup(struct smu_context *smu)
1164 {
1165         struct amdgpu_device *adev = smu->adev;
1166         int ret = 0;
1167
1168         cancel_work_sync(&smu->throttling_logging_work);
1169
1170         ret = smu_disable_thermal_alert(smu);
1171         if (ret) {
1172                 dev_err(adev->dev, "Fail to disable thermal alert!\n");
1173                 return ret;
1174         }
1175
1176         ret = smu_disable_dpms(smu);
1177         if (ret) {
1178                 dev_err(adev->dev, "Fail to disable dpm features!\n");
1179                 return ret;
1180         }
1181
1182         return 0;
1183 }
1184
1185 static int smu_hw_fini(void *handle)
1186 {
1187         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1188         struct smu_context *smu = &adev->smu;
1189         int ret = 0;
1190
1191         if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1192                 return 0;
1193
1194         if (smu->is_apu) {
1195                 smu_powergate_sdma(&adev->smu, true);
1196                 smu_dpm_set_vcn_enable(smu, false);
1197                 smu_dpm_set_jpeg_enable(smu, false);
1198         }
1199
1200         if (!smu->pm_enabled)
1201                 return 0;
1202
1203         adev->pm.dpm_enabled = false;
1204
1205         ret = smu_smc_hw_cleanup(smu);
1206         if (ret)
1207                 return ret;
1208
1209         return 0;
1210 }
1211
1212 int smu_reset(struct smu_context *smu)
1213 {
1214         struct amdgpu_device *adev = smu->adev;
1215         int ret = 0;
1216
1217         ret = smu_hw_fini(adev);
1218         if (ret)
1219                 return ret;
1220
1221         ret = smu_hw_init(adev);
1222         if (ret)
1223                 return ret;
1224
1225         ret = smu_late_init(adev);
1226
1227         return ret;
1228 }
1229
1230 static int smu_suspend(void *handle)
1231 {
1232         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1233         struct smu_context *smu = &adev->smu;
1234         int ret;
1235
1236         if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1237                 return 0;
1238
1239         if (!smu->pm_enabled)
1240                 return 0;
1241
1242         adev->pm.dpm_enabled = false;
1243
1244         ret = smu_smc_hw_cleanup(smu);
1245         if (ret)
1246                 return ret;
1247
1248         smu->watermarks_bitmap &= ~(WATERMARKS_LOADED);
1249
1250         if (smu->is_apu)
1251                 smu_set_gfx_cgpg(&adev->smu, false);
1252
1253         return 0;
1254 }
1255
1256 static int smu_resume(void *handle)
1257 {
1258         int ret;
1259         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1260         struct smu_context *smu = &adev->smu;
1261
1262         if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1263                 return 0;
1264
1265         if (!smu->pm_enabled)
1266                 return 0;
1267
1268         dev_info(adev->dev, "SMU is resuming...\n");
1269
1270         ret = smu_start_smc_engine(smu);
1271         if (ret) {
1272                 dev_err(adev->dev, "SMC engine is not correctly up!\n");
1273                 return ret;
1274         }
1275
1276         ret = smu_smc_hw_setup(smu);
1277         if (ret) {
1278                 dev_err(adev->dev, "Failed to setup smc hw!\n");
1279                 return ret;
1280         }
1281
1282         if (smu->is_apu)
1283                 smu_set_gfx_cgpg(&adev->smu, true);
1284
1285         smu->disable_uclk_switch = 0;
1286
1287         adev->pm.dpm_enabled = true;
1288
1289         dev_info(adev->dev, "SMU is resumed successfully!\n");
1290
1291         return 0;
1292 }
1293
1294 int smu_display_configuration_change(struct smu_context *smu,
1295                                      const struct amd_pp_display_configuration *display_config)
1296 {
1297         int index = 0;
1298         int num_of_active_display = 0;
1299
1300         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1301                 return -EOPNOTSUPP;
1302
1303         if (!display_config)
1304                 return -EINVAL;
1305
1306         mutex_lock(&smu->mutex);
1307
1308         smu_set_min_dcef_deep_sleep(smu,
1309                                     display_config->min_dcef_deep_sleep_set_clk / 100);
1310
1311         for (index = 0; index < display_config->num_path_including_non_display; index++) {
1312                 if (display_config->displays[index].controller_id != 0)
1313                         num_of_active_display++;
1314         }
1315
1316         smu_set_active_display_count(smu, num_of_active_display);
1317
1318         smu_store_cc6_data(smu, display_config->cpu_pstate_separation_time,
1319                            display_config->cpu_cc6_disable,
1320                            display_config->cpu_pstate_disable,
1321                            display_config->nb_pstate_switch_disable);
1322
1323         mutex_unlock(&smu->mutex);
1324
1325         return 0;
1326 }
1327
1328 static int smu_get_clock_info(struct smu_context *smu,
1329                               struct smu_clock_info *clk_info,
1330                               enum smu_perf_level_designation designation)
1331 {
1332         int ret;
1333         struct smu_performance_level level = {0};
1334
1335         if (!clk_info)
1336                 return -EINVAL;
1337
1338         ret = smu_get_perf_level(smu, PERF_LEVEL_ACTIVITY, &level);
1339         if (ret)
1340                 return -EINVAL;
1341
1342         clk_info->min_mem_clk = level.memory_clock;
1343         clk_info->min_eng_clk = level.core_clock;
1344         clk_info->min_bus_bandwidth = level.non_local_mem_freq * level.non_local_mem_width;
1345
1346         ret = smu_get_perf_level(smu, designation, &level);
1347         if (ret)
1348                 return -EINVAL;
1349
1350         clk_info->min_mem_clk = level.memory_clock;
1351         clk_info->min_eng_clk = level.core_clock;
1352         clk_info->min_bus_bandwidth = level.non_local_mem_freq * level.non_local_mem_width;
1353
1354         return 0;
1355 }
1356
1357 int smu_get_current_clocks(struct smu_context *smu,
1358                            struct amd_pp_clock_info *clocks)
1359 {
1360         struct amd_pp_simple_clock_info simple_clocks = {0};
1361         struct smu_clock_info hw_clocks;
1362         int ret = 0;
1363
1364         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1365                 return -EOPNOTSUPP;
1366
1367         mutex_lock(&smu->mutex);
1368
1369         smu_get_dal_power_level(smu, &simple_clocks);
1370
1371         if (smu->support_power_containment)
1372                 ret = smu_get_clock_info(smu, &hw_clocks,
1373                                          PERF_LEVEL_POWER_CONTAINMENT);
1374         else
1375                 ret = smu_get_clock_info(smu, &hw_clocks, PERF_LEVEL_ACTIVITY);
1376
1377         if (ret) {
1378                 dev_err(smu->adev->dev, "Error in smu_get_clock_info\n");
1379                 goto failed;
1380         }
1381
1382         clocks->min_engine_clock = hw_clocks.min_eng_clk;
1383         clocks->max_engine_clock = hw_clocks.max_eng_clk;
1384         clocks->min_memory_clock = hw_clocks.min_mem_clk;
1385         clocks->max_memory_clock = hw_clocks.max_mem_clk;
1386         clocks->min_bus_bandwidth = hw_clocks.min_bus_bandwidth;
1387         clocks->max_bus_bandwidth = hw_clocks.max_bus_bandwidth;
1388         clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1389         clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1390
1391         if (simple_clocks.level == 0)
1392                 clocks->max_clocks_state = PP_DAL_POWERLEVEL_7;
1393         else
1394                 clocks->max_clocks_state = simple_clocks.level;
1395
1396         if (!smu_get_current_shallow_sleep_clocks(smu, &hw_clocks)) {
1397                 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1398                 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1399         }
1400
1401 failed:
1402         mutex_unlock(&smu->mutex);
1403         return ret;
1404 }
1405
1406 static int smu_set_clockgating_state(void *handle,
1407                                      enum amd_clockgating_state state)
1408 {
1409         return 0;
1410 }
1411
1412 static int smu_set_powergating_state(void *handle,
1413                                      enum amd_powergating_state state)
1414 {
1415         return 0;
1416 }
1417
1418 static int smu_enable_umd_pstate(void *handle,
1419                       enum amd_dpm_forced_level *level)
1420 {
1421         uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
1422                                         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
1423                                         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
1424                                         AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
1425
1426         struct smu_context *smu = (struct smu_context*)(handle);
1427         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1428
1429         if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1430                 return -EINVAL;
1431
1432         if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) {
1433                 /* enter umd pstate, save current level, disable gfx cg*/
1434                 if (*level & profile_mode_mask) {
1435                         smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
1436                         smu_dpm_ctx->enable_umd_pstate = true;
1437                         amdgpu_device_ip_set_powergating_state(smu->adev,
1438                                                                AMD_IP_BLOCK_TYPE_GFX,
1439                                                                AMD_PG_STATE_UNGATE);
1440                         amdgpu_device_ip_set_clockgating_state(smu->adev,
1441                                                                AMD_IP_BLOCK_TYPE_GFX,
1442                                                                AMD_CG_STATE_UNGATE);
1443                         smu_gfx_ulv_control(smu, false);
1444                         smu_deep_sleep_control(smu, false);
1445                 }
1446         } else {
1447                 /* exit umd pstate, restore level, enable gfx cg*/
1448                 if (!(*level & profile_mode_mask)) {
1449                         if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
1450                                 *level = smu_dpm_ctx->saved_dpm_level;
1451                         smu_dpm_ctx->enable_umd_pstate = false;
1452                         smu_deep_sleep_control(smu, true);
1453                         smu_gfx_ulv_control(smu, true);
1454                         amdgpu_device_ip_set_clockgating_state(smu->adev,
1455                                                                AMD_IP_BLOCK_TYPE_GFX,
1456                                                                AMD_CG_STATE_GATE);
1457                         amdgpu_device_ip_set_powergating_state(smu->adev,
1458                                                                AMD_IP_BLOCK_TYPE_GFX,
1459                                                                AMD_PG_STATE_GATE);
1460                 }
1461         }
1462
1463         return 0;
1464 }
1465
1466 static int smu_adjust_power_state_dynamic(struct smu_context *smu,
1467                                    enum amd_dpm_forced_level level,
1468                                    bool skip_display_settings)
1469 {
1470         int ret = 0;
1471         int index = 0;
1472         long workload;
1473         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1474
1475         if (!skip_display_settings) {
1476                 ret = smu_display_config_changed(smu);
1477                 if (ret) {
1478                         dev_err(smu->adev->dev, "Failed to change display config!");
1479                         return ret;
1480                 }
1481         }
1482
1483         ret = smu_apply_clocks_adjust_rules(smu);
1484         if (ret) {
1485                 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!");
1486                 return ret;
1487         }
1488
1489         if (!skip_display_settings) {
1490                 ret = smu_notify_smc_display_config(smu);
1491                 if (ret) {
1492                         dev_err(smu->adev->dev, "Failed to notify smc display config!");
1493                         return ret;
1494                 }
1495         }
1496
1497         if (smu_dpm_ctx->dpm_level != level) {
1498                 ret = smu_asic_set_performance_level(smu, level);
1499                 if (ret) {
1500                         dev_err(smu->adev->dev, "Failed to set performance level!");
1501                         return ret;
1502                 }
1503
1504                 /* update the saved copy */
1505                 smu_dpm_ctx->dpm_level = level;
1506         }
1507
1508         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1509                 index = fls(smu->workload_mask);
1510                 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1511                 workload = smu->workload_setting[index];
1512
1513                 if (smu->power_profile_mode != workload)
1514                         smu_set_power_profile_mode(smu, &workload, 0, false);
1515         }
1516
1517         return ret;
1518 }
1519
1520 int smu_handle_task(struct smu_context *smu,
1521                     enum amd_dpm_forced_level level,
1522                     enum amd_pp_task task_id,
1523                     bool lock_needed)
1524 {
1525         int ret = 0;
1526
1527         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1528                 return -EOPNOTSUPP;
1529
1530         if (lock_needed)
1531                 mutex_lock(&smu->mutex);
1532
1533         switch (task_id) {
1534         case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
1535                 ret = smu_pre_display_config_changed(smu);
1536                 if (ret)
1537                         goto out;
1538                 ret = smu_set_cpu_power_state(smu);
1539                 if (ret)
1540                         goto out;
1541                 ret = smu_adjust_power_state_dynamic(smu, level, false);
1542                 break;
1543         case AMD_PP_TASK_COMPLETE_INIT:
1544         case AMD_PP_TASK_READJUST_POWER_STATE:
1545                 ret = smu_adjust_power_state_dynamic(smu, level, true);
1546                 break;
1547         default:
1548                 break;
1549         }
1550
1551 out:
1552         if (lock_needed)
1553                 mutex_unlock(&smu->mutex);
1554
1555         return ret;
1556 }
1557
1558 int smu_switch_power_profile(struct smu_context *smu,
1559                              enum PP_SMC_POWER_PROFILE type,
1560                              bool en)
1561 {
1562         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1563         long workload;
1564         uint32_t index;
1565
1566         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1567                 return -EOPNOTSUPP;
1568
1569         if (!(type < PP_SMC_POWER_PROFILE_CUSTOM))
1570                 return -EINVAL;
1571
1572         mutex_lock(&smu->mutex);
1573
1574         if (!en) {
1575                 smu->workload_mask &= ~(1 << smu->workload_prority[type]);
1576                 index = fls(smu->workload_mask);
1577                 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1578                 workload = smu->workload_setting[index];
1579         } else {
1580                 smu->workload_mask |= (1 << smu->workload_prority[type]);
1581                 index = fls(smu->workload_mask);
1582                 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1583                 workload = smu->workload_setting[index];
1584         }
1585
1586         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
1587                 smu_set_power_profile_mode(smu, &workload, 0, false);
1588
1589         mutex_unlock(&smu->mutex);
1590
1591         return 0;
1592 }
1593
1594 enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu)
1595 {
1596         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1597         enum amd_dpm_forced_level level;
1598
1599         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1600                 return -EOPNOTSUPP;
1601
1602         if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1603                 return -EINVAL;
1604
1605         mutex_lock(&(smu->mutex));
1606         level = smu_dpm_ctx->dpm_level;
1607         mutex_unlock(&(smu->mutex));
1608
1609         return level;
1610 }
1611
1612 int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
1613 {
1614         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1615         int ret = 0;
1616
1617         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1618                 return -EOPNOTSUPP;
1619
1620         if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1621                 return -EINVAL;
1622
1623         mutex_lock(&smu->mutex);
1624
1625         ret = smu_enable_umd_pstate(smu, &level);
1626         if (ret) {
1627                 mutex_unlock(&smu->mutex);
1628                 return ret;
1629         }
1630
1631         ret = smu_handle_task(smu, level,
1632                               AMD_PP_TASK_READJUST_POWER_STATE,
1633                               false);
1634
1635         mutex_unlock(&smu->mutex);
1636
1637         return ret;
1638 }
1639
1640 int smu_set_display_count(struct smu_context *smu, uint32_t count)
1641 {
1642         int ret = 0;
1643
1644         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1645                 return -EOPNOTSUPP;
1646
1647         mutex_lock(&smu->mutex);
1648         ret = smu_init_display_count(smu, count);
1649         mutex_unlock(&smu->mutex);
1650
1651         return ret;
1652 }
1653
1654 int smu_force_clk_levels(struct smu_context *smu,
1655                          enum smu_clk_type clk_type,
1656                          uint32_t mask)
1657 {
1658         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1659         int ret = 0;
1660
1661         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1662                 return -EOPNOTSUPP;
1663
1664         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1665                 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n");
1666                 return -EINVAL;
1667         }
1668
1669         mutex_lock(&smu->mutex);
1670
1671         if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels)
1672                 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask);
1673
1674         mutex_unlock(&smu->mutex);
1675
1676         return ret;
1677 }
1678
1679 /*
1680  * On system suspending or resetting, the dpm_enabled
1681  * flag will be cleared. So that those SMU services which
1682  * are not supported will be gated.
1683  * However, the mp1 state setting should still be granted
1684  * even if the dpm_enabled cleared.
1685  */
1686 int smu_set_mp1_state(struct smu_context *smu,
1687                       enum pp_mp1_state mp1_state)
1688 {
1689         uint16_t msg;
1690         int ret;
1691
1692         if (!smu->pm_enabled)
1693                 return -EOPNOTSUPP;
1694
1695         mutex_lock(&smu->mutex);
1696
1697         switch (mp1_state) {
1698         case PP_MP1_STATE_SHUTDOWN:
1699                 msg = SMU_MSG_PrepareMp1ForShutdown;
1700                 break;
1701         case PP_MP1_STATE_UNLOAD:
1702                 msg = SMU_MSG_PrepareMp1ForUnload;
1703                 break;
1704         case PP_MP1_STATE_RESET:
1705                 msg = SMU_MSG_PrepareMp1ForReset;
1706                 break;
1707         case PP_MP1_STATE_NONE:
1708         default:
1709                 mutex_unlock(&smu->mutex);
1710                 return 0;
1711         }
1712
1713         ret = smu_send_smc_msg(smu, msg, NULL);
1714         /* some asics may not support those messages */
1715         if (ret == -EINVAL)
1716                 ret = 0;
1717         if (ret)
1718                 dev_err(smu->adev->dev, "[PrepareMp1] Failed!\n");
1719
1720         mutex_unlock(&smu->mutex);
1721
1722         return ret;
1723 }
1724
1725 int smu_set_df_cstate(struct smu_context *smu,
1726                       enum pp_df_cstate state)
1727 {
1728         int ret = 0;
1729
1730         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1731                 return -EOPNOTSUPP;
1732
1733         if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate)
1734                 return 0;
1735
1736         mutex_lock(&smu->mutex);
1737
1738         ret = smu->ppt_funcs->set_df_cstate(smu, state);
1739         if (ret)
1740                 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n");
1741
1742         mutex_unlock(&smu->mutex);
1743
1744         return ret;
1745 }
1746
1747 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en)
1748 {
1749         int ret = 0;
1750
1751         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1752                 return -EOPNOTSUPP;
1753
1754         if (!smu->ppt_funcs || !smu->ppt_funcs->allow_xgmi_power_down)
1755                 return 0;
1756
1757         mutex_lock(&smu->mutex);
1758
1759         ret = smu->ppt_funcs->allow_xgmi_power_down(smu, en);
1760         if (ret)
1761                 dev_err(smu->adev->dev, "[AllowXgmiPowerDown] failed!\n");
1762
1763         mutex_unlock(&smu->mutex);
1764
1765         return ret;
1766 }
1767
1768 int smu_write_watermarks_table(struct smu_context *smu)
1769 {
1770         int ret = 0;
1771
1772         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1773                 return -EOPNOTSUPP;
1774
1775         mutex_lock(&smu->mutex);
1776
1777         ret = smu_set_watermarks_table(smu, NULL);
1778
1779         mutex_unlock(&smu->mutex);
1780
1781         return ret;
1782 }
1783
1784 int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
1785                 struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges)
1786 {
1787         int ret = 0;
1788
1789         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1790                 return -EOPNOTSUPP;
1791
1792         mutex_lock(&smu->mutex);
1793
1794         if (!smu->disable_watermark &&
1795                         smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1796                         smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1797                 ret = smu_set_watermarks_table(smu, clock_ranges);
1798
1799                 if (!(smu->watermarks_bitmap & WATERMARKS_EXIST)) {
1800                         smu->watermarks_bitmap |= WATERMARKS_EXIST;
1801                         smu->watermarks_bitmap &= ~WATERMARKS_LOADED;
1802                 }
1803         }
1804
1805         mutex_unlock(&smu->mutex);
1806
1807         return ret;
1808 }
1809
1810 int smu_set_ac_dc(struct smu_context *smu)
1811 {
1812         int ret = 0;
1813
1814         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1815                 return -EOPNOTSUPP;
1816
1817         /* controlled by firmware */
1818         if (smu->dc_controlled_by_gpio)
1819                 return 0;
1820
1821         mutex_lock(&smu->mutex);
1822         ret = smu_set_power_source(smu,
1823                                    smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC :
1824                                    SMU_POWER_SOURCE_DC);
1825         if (ret)
1826                 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n",
1827                        smu->adev->pm.ac_power ? "AC" : "DC");
1828         mutex_unlock(&smu->mutex);
1829
1830         return ret;
1831 }
1832
1833 const struct amd_ip_funcs smu_ip_funcs = {
1834         .name = "smu",
1835         .early_init = smu_early_init,
1836         .late_init = smu_late_init,
1837         .sw_init = smu_sw_init,
1838         .sw_fini = smu_sw_fini,
1839         .hw_init = smu_hw_init,
1840         .hw_fini = smu_hw_fini,
1841         .suspend = smu_suspend,
1842         .resume = smu_resume,
1843         .is_idle = NULL,
1844         .check_soft_reset = NULL,
1845         .wait_for_idle = NULL,
1846         .soft_reset = NULL,
1847         .set_clockgating_state = smu_set_clockgating_state,
1848         .set_powergating_state = smu_set_powergating_state,
1849         .enable_umd_pstate = smu_enable_umd_pstate,
1850 };
1851
1852 const struct amdgpu_ip_block_version smu_v11_0_ip_block =
1853 {
1854         .type = AMD_IP_BLOCK_TYPE_SMC,
1855         .major = 11,
1856         .minor = 0,
1857         .rev = 0,
1858         .funcs = &smu_ip_funcs,
1859 };
1860
1861 const struct amdgpu_ip_block_version smu_v12_0_ip_block =
1862 {
1863         .type = AMD_IP_BLOCK_TYPE_SMC,
1864         .major = 12,
1865         .minor = 0,
1866         .rev = 0,
1867         .funcs = &smu_ip_funcs,
1868 };
1869
1870 int smu_load_microcode(struct smu_context *smu)
1871 {
1872         int ret = 0;
1873
1874         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1875                 return -EOPNOTSUPP;
1876
1877         mutex_lock(&smu->mutex);
1878
1879         if (smu->ppt_funcs->load_microcode)
1880                 ret = smu->ppt_funcs->load_microcode(smu);
1881
1882         mutex_unlock(&smu->mutex);
1883
1884         return ret;
1885 }
1886
1887 int smu_check_fw_status(struct smu_context *smu)
1888 {
1889         int ret = 0;
1890
1891         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1892                 return -EOPNOTSUPP;
1893
1894         mutex_lock(&smu->mutex);
1895
1896         if (smu->ppt_funcs->check_fw_status)
1897                 ret = smu->ppt_funcs->check_fw_status(smu);
1898
1899         mutex_unlock(&smu->mutex);
1900
1901         return ret;
1902 }
1903
1904 int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled)
1905 {
1906         int ret = 0;
1907
1908         mutex_lock(&smu->mutex);
1909
1910         if (smu->ppt_funcs->set_gfx_cgpg)
1911                 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled);
1912
1913         mutex_unlock(&smu->mutex);
1914
1915         return ret;
1916 }
1917
1918 int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed)
1919 {
1920         int ret = 0;
1921
1922         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1923                 return -EOPNOTSUPP;
1924
1925         mutex_lock(&smu->mutex);
1926
1927         if (smu->ppt_funcs->set_fan_speed_rpm)
1928                 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed);
1929
1930         mutex_unlock(&smu->mutex);
1931
1932         return ret;
1933 }
1934
1935 int smu_get_power_limit(struct smu_context *smu,
1936                         uint32_t *limit,
1937                         bool max_setting)
1938 {
1939         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1940                 return -EOPNOTSUPP;
1941
1942         mutex_lock(&smu->mutex);
1943
1944         *limit = (max_setting ? smu->max_power_limit : smu->current_power_limit);
1945
1946         mutex_unlock(&smu->mutex);
1947
1948         return 0;
1949 }
1950
1951 int smu_set_power_limit(struct smu_context *smu, uint32_t limit)
1952 {
1953         int ret = 0;
1954
1955         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1956                 return -EOPNOTSUPP;
1957
1958         mutex_lock(&smu->mutex);
1959
1960         if (limit > smu->max_power_limit) {
1961                 dev_err(smu->adev->dev,
1962                         "New power limit (%d) is over the max allowed %d\n",
1963                         limit, smu->max_power_limit);
1964                 goto out;
1965         }
1966
1967         if (!limit)
1968                 limit = smu->current_power_limit;
1969
1970         if (smu->ppt_funcs->set_power_limit)
1971                 ret = smu->ppt_funcs->set_power_limit(smu, limit);
1972
1973 out:
1974         mutex_unlock(&smu->mutex);
1975
1976         return ret;
1977 }
1978
1979 int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf)
1980 {
1981         int ret = 0;
1982
1983         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1984                 return -EOPNOTSUPP;
1985
1986         mutex_lock(&smu->mutex);
1987
1988         if (smu->ppt_funcs->print_clk_levels)
1989                 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf);
1990
1991         mutex_unlock(&smu->mutex);
1992
1993         return ret;
1994 }
1995
1996 int smu_get_od_percentage(struct smu_context *smu, enum smu_clk_type type)
1997 {
1998         int ret = 0;
1999
2000         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2001                 return -EOPNOTSUPP;
2002
2003         mutex_lock(&smu->mutex);
2004
2005         if (smu->ppt_funcs->get_od_percentage)
2006                 ret = smu->ppt_funcs->get_od_percentage(smu, type);
2007
2008         mutex_unlock(&smu->mutex);
2009
2010         return ret;
2011 }
2012
2013 int smu_set_od_percentage(struct smu_context *smu, enum smu_clk_type type, uint32_t value)
2014 {
2015         int ret = 0;
2016
2017         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2018                 return -EOPNOTSUPP;
2019
2020         mutex_lock(&smu->mutex);
2021
2022         if (smu->ppt_funcs->set_od_percentage)
2023                 ret = smu->ppt_funcs->set_od_percentage(smu, type, value);
2024
2025         mutex_unlock(&smu->mutex);
2026
2027         return ret;
2028 }
2029
2030 int smu_od_edit_dpm_table(struct smu_context *smu,
2031                           enum PP_OD_DPM_TABLE_COMMAND type,
2032                           long *input, uint32_t size)
2033 {
2034         int ret = 0;
2035
2036         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2037                 return -EOPNOTSUPP;
2038
2039         mutex_lock(&smu->mutex);
2040
2041         if (smu->ppt_funcs->od_edit_dpm_table) {
2042                 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size);
2043                 if (!ret && (type == PP_OD_COMMIT_DPM_TABLE))
2044                         ret = smu_handle_task(smu,
2045                                               smu->smu_dpm.dpm_level,
2046                                               AMD_PP_TASK_READJUST_POWER_STATE,
2047                                               false);
2048         }
2049
2050         mutex_unlock(&smu->mutex);
2051
2052         return ret;
2053 }
2054
2055 int smu_read_sensor(struct smu_context *smu,
2056                     enum amd_pp_sensors sensor,
2057                     void *data, uint32_t *size)
2058 {
2059         struct smu_umd_pstate_table *pstate_table =
2060                                 &smu->pstate_table;
2061         int ret = 0;
2062
2063         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2064                 return -EOPNOTSUPP;
2065
2066         if (!data || !size)
2067                 return -EINVAL;
2068
2069         mutex_lock(&smu->mutex);
2070
2071         if (smu->ppt_funcs->read_sensor)
2072                 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size))
2073                         goto unlock;
2074
2075         switch (sensor) {
2076         case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
2077                 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100;
2078                 *size = 4;
2079                 break;
2080         case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
2081                 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100;
2082                 *size = 4;
2083                 break;
2084         case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
2085                 ret = smu_feature_get_enabled_mask(smu, (uint32_t *)data, 2);
2086                 *size = 8;
2087                 break;
2088         case AMDGPU_PP_SENSOR_UVD_POWER:
2089                 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0;
2090                 *size = 4;
2091                 break;
2092         case AMDGPU_PP_SENSOR_VCE_POWER:
2093                 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0;
2094                 *size = 4;
2095                 break;
2096         case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
2097                 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0: 1;
2098                 *size = 4;
2099                 break;
2100         case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
2101                 *(uint32_t *)data = 0;
2102                 *size = 4;
2103                 break;
2104         default:
2105                 *size = 0;
2106                 ret = -EOPNOTSUPP;
2107                 break;
2108         }
2109
2110 unlock:
2111         mutex_unlock(&smu->mutex);
2112
2113         return ret;
2114 }
2115
2116 int smu_get_power_profile_mode(struct smu_context *smu, char *buf)
2117 {
2118         int ret = 0;
2119
2120         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2121                 return -EOPNOTSUPP;
2122
2123         mutex_lock(&smu->mutex);
2124
2125         if (smu->ppt_funcs->get_power_profile_mode)
2126                 ret = smu->ppt_funcs->get_power_profile_mode(smu, buf);
2127
2128         mutex_unlock(&smu->mutex);
2129
2130         return ret;
2131 }
2132
2133 int smu_set_power_profile_mode(struct smu_context *smu,
2134                                long *param,
2135                                uint32_t param_size,
2136                                bool lock_needed)
2137 {
2138         int ret = 0;
2139
2140         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2141                 return -EOPNOTSUPP;
2142
2143         if (lock_needed)
2144                 mutex_lock(&smu->mutex);
2145
2146         if (smu->ppt_funcs->set_power_profile_mode)
2147                 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size);
2148
2149         if (lock_needed)
2150                 mutex_unlock(&smu->mutex);
2151
2152         return ret;
2153 }
2154
2155
2156 int smu_get_fan_control_mode(struct smu_context *smu)
2157 {
2158         int ret = 0;
2159
2160         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2161                 return -EOPNOTSUPP;
2162
2163         mutex_lock(&smu->mutex);
2164
2165         if (smu->ppt_funcs->get_fan_control_mode)
2166                 ret = smu->ppt_funcs->get_fan_control_mode(smu);
2167
2168         mutex_unlock(&smu->mutex);
2169
2170         return ret;
2171 }
2172
2173 int smu_set_fan_control_mode(struct smu_context *smu, int value)
2174 {
2175         int ret = 0;
2176
2177         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2178                 return -EOPNOTSUPP;
2179
2180         mutex_lock(&smu->mutex);
2181
2182         if (smu->ppt_funcs->set_fan_control_mode)
2183                 ret = smu->ppt_funcs->set_fan_control_mode(smu, value);
2184
2185         mutex_unlock(&smu->mutex);
2186
2187         return ret;
2188 }
2189
2190 int smu_get_fan_speed_percent(struct smu_context *smu, uint32_t *speed)
2191 {
2192         int ret = 0;
2193
2194         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2195                 return -EOPNOTSUPP;
2196
2197         mutex_lock(&smu->mutex);
2198
2199         if (smu->ppt_funcs->get_fan_speed_percent)
2200                 ret = smu->ppt_funcs->get_fan_speed_percent(smu, speed);
2201
2202         mutex_unlock(&smu->mutex);
2203
2204         return ret;
2205 }
2206
2207 int smu_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
2208 {
2209         int ret = 0;
2210
2211         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2212                 return -EOPNOTSUPP;
2213
2214         mutex_lock(&smu->mutex);
2215
2216         if (smu->ppt_funcs->set_fan_speed_percent)
2217                 ret = smu->ppt_funcs->set_fan_speed_percent(smu, speed);
2218
2219         mutex_unlock(&smu->mutex);
2220
2221         return ret;
2222 }
2223
2224 int smu_get_fan_speed_rpm(struct smu_context *smu, uint32_t *speed)
2225 {
2226         int ret = 0;
2227
2228         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2229                 return -EOPNOTSUPP;
2230
2231         mutex_lock(&smu->mutex);
2232
2233         if (smu->ppt_funcs->get_fan_speed_rpm)
2234                 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed);
2235
2236         mutex_unlock(&smu->mutex);
2237
2238         return ret;
2239 }
2240
2241 int smu_set_deep_sleep_dcefclk(struct smu_context *smu, int clk)
2242 {
2243         int ret = 0;
2244
2245         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2246                 return -EOPNOTSUPP;
2247
2248         mutex_lock(&smu->mutex);
2249
2250         ret = smu_set_min_dcef_deep_sleep(smu, clk);
2251
2252         mutex_unlock(&smu->mutex);
2253
2254         return ret;
2255 }
2256
2257 int smu_set_active_display_count(struct smu_context *smu, uint32_t count)
2258 {
2259         int ret = 0;
2260
2261         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2262                 return -EOPNOTSUPP;
2263
2264         if (smu->ppt_funcs->set_active_display_count)
2265                 ret = smu->ppt_funcs->set_active_display_count(smu, count);
2266
2267         return ret;
2268 }
2269
2270 int smu_get_clock_by_type(struct smu_context *smu,
2271                           enum amd_pp_clock_type type,
2272                           struct amd_pp_clocks *clocks)
2273 {
2274         int ret = 0;
2275
2276         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2277                 return -EOPNOTSUPP;
2278
2279         mutex_lock(&smu->mutex);
2280
2281         if (smu->ppt_funcs->get_clock_by_type)
2282                 ret = smu->ppt_funcs->get_clock_by_type(smu, type, clocks);
2283
2284         mutex_unlock(&smu->mutex);
2285
2286         return ret;
2287 }
2288
2289 int smu_get_max_high_clocks(struct smu_context *smu,
2290                             struct amd_pp_simple_clock_info *clocks)
2291 {
2292         int ret = 0;
2293
2294         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2295                 return -EOPNOTSUPP;
2296
2297         mutex_lock(&smu->mutex);
2298
2299         if (smu->ppt_funcs->get_max_high_clocks)
2300                 ret = smu->ppt_funcs->get_max_high_clocks(smu, clocks);
2301
2302         mutex_unlock(&smu->mutex);
2303
2304         return ret;
2305 }
2306
2307 int smu_get_clock_by_type_with_latency(struct smu_context *smu,
2308                                        enum smu_clk_type clk_type,
2309                                        struct pp_clock_levels_with_latency *clocks)
2310 {
2311         int ret = 0;
2312
2313         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2314                 return -EOPNOTSUPP;
2315
2316         mutex_lock(&smu->mutex);
2317
2318         if (smu->ppt_funcs->get_clock_by_type_with_latency)
2319                 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks);
2320
2321         mutex_unlock(&smu->mutex);
2322
2323         return ret;
2324 }
2325
2326 int smu_get_clock_by_type_with_voltage(struct smu_context *smu,
2327                                        enum amd_pp_clock_type type,
2328                                        struct pp_clock_levels_with_voltage *clocks)
2329 {
2330         int ret = 0;
2331
2332         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2333                 return -EOPNOTSUPP;
2334
2335         mutex_lock(&smu->mutex);
2336
2337         if (smu->ppt_funcs->get_clock_by_type_with_voltage)
2338                 ret = smu->ppt_funcs->get_clock_by_type_with_voltage(smu, type, clocks);
2339
2340         mutex_unlock(&smu->mutex);
2341
2342         return ret;
2343 }
2344
2345
2346 int smu_display_clock_voltage_request(struct smu_context *smu,
2347                                       struct pp_display_clock_request *clock_req)
2348 {
2349         int ret = 0;
2350
2351         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2352                 return -EOPNOTSUPP;
2353
2354         mutex_lock(&smu->mutex);
2355
2356         if (smu->ppt_funcs->display_clock_voltage_request)
2357                 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req);
2358
2359         mutex_unlock(&smu->mutex);
2360
2361         return ret;
2362 }
2363
2364
2365 int smu_display_disable_memory_clock_switch(struct smu_context *smu, bool disable_memory_clock_switch)
2366 {
2367         int ret = -EINVAL;
2368
2369         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2370                 return -EOPNOTSUPP;
2371
2372         mutex_lock(&smu->mutex);
2373
2374         if (smu->ppt_funcs->display_disable_memory_clock_switch)
2375                 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch);
2376
2377         mutex_unlock(&smu->mutex);
2378
2379         return ret;
2380 }
2381
2382 int smu_notify_smu_enable_pwe(struct smu_context *smu)
2383 {
2384         int ret = 0;
2385
2386         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2387                 return -EOPNOTSUPP;
2388
2389         mutex_lock(&smu->mutex);
2390
2391         if (smu->ppt_funcs->notify_smu_enable_pwe)
2392                 ret = smu->ppt_funcs->notify_smu_enable_pwe(smu);
2393
2394         mutex_unlock(&smu->mutex);
2395
2396         return ret;
2397 }
2398
2399 int smu_set_xgmi_pstate(struct smu_context *smu,
2400                         uint32_t pstate)
2401 {
2402         int ret = 0;
2403
2404         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2405                 return -EOPNOTSUPP;
2406
2407         mutex_lock(&smu->mutex);
2408
2409         if (smu->ppt_funcs->set_xgmi_pstate)
2410                 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate);
2411
2412         mutex_unlock(&smu->mutex);
2413
2414         if(ret)
2415                 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n");
2416
2417         return ret;
2418 }
2419
2420 int smu_set_azalia_d3_pme(struct smu_context *smu)
2421 {
2422         int ret = 0;
2423
2424         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2425                 return -EOPNOTSUPP;
2426
2427         mutex_lock(&smu->mutex);
2428
2429         if (smu->ppt_funcs->set_azalia_d3_pme)
2430                 ret = smu->ppt_funcs->set_azalia_d3_pme(smu);
2431
2432         mutex_unlock(&smu->mutex);
2433
2434         return ret;
2435 }
2436
2437 /*
2438  * On system suspending or resetting, the dpm_enabled
2439  * flag will be cleared. So that those SMU services which
2440  * are not supported will be gated.
2441  *
2442  * However, the baco/mode1 reset should still be granted
2443  * as they are still supported and necessary.
2444  */
2445 bool smu_baco_is_support(struct smu_context *smu)
2446 {
2447         bool ret = false;
2448
2449         if (!smu->pm_enabled)
2450                 return false;
2451
2452         mutex_lock(&smu->mutex);
2453
2454         if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support)
2455                 ret = smu->ppt_funcs->baco_is_support(smu);
2456
2457         mutex_unlock(&smu->mutex);
2458
2459         return ret;
2460 }
2461
2462 int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state)
2463 {
2464         if (smu->ppt_funcs->baco_get_state)
2465                 return -EINVAL;
2466
2467         mutex_lock(&smu->mutex);
2468         *state = smu->ppt_funcs->baco_get_state(smu);
2469         mutex_unlock(&smu->mutex);
2470
2471         return 0;
2472 }
2473
2474 int smu_baco_enter(struct smu_context *smu)
2475 {
2476         int ret = 0;
2477
2478         if (!smu->pm_enabled)
2479                 return -EOPNOTSUPP;
2480
2481         mutex_lock(&smu->mutex);
2482
2483         if (smu->ppt_funcs->baco_enter)
2484                 ret = smu->ppt_funcs->baco_enter(smu);
2485
2486         mutex_unlock(&smu->mutex);
2487
2488         if (ret)
2489                 dev_err(smu->adev->dev, "Failed to enter BACO state!\n");
2490
2491         return ret;
2492 }
2493
2494 int smu_baco_exit(struct smu_context *smu)
2495 {
2496         int ret = 0;
2497
2498         if (!smu->pm_enabled)
2499                 return -EOPNOTSUPP;
2500
2501         mutex_lock(&smu->mutex);
2502
2503         if (smu->ppt_funcs->baco_exit)
2504                 ret = smu->ppt_funcs->baco_exit(smu);
2505
2506         mutex_unlock(&smu->mutex);
2507
2508         if (ret)
2509                 dev_err(smu->adev->dev, "Failed to exit BACO state!\n");
2510
2511         return ret;
2512 }
2513
2514 bool smu_mode1_reset_is_support(struct smu_context *smu)
2515 {
2516         bool ret = false;
2517
2518         if (!smu->pm_enabled)
2519                 return false;
2520
2521         mutex_lock(&smu->mutex);
2522
2523         if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support)
2524                 ret = smu->ppt_funcs->mode1_reset_is_support(smu);
2525
2526         mutex_unlock(&smu->mutex);
2527
2528         return ret;
2529 }
2530
2531 int smu_mode1_reset(struct smu_context *smu)
2532 {
2533         int ret = 0;
2534
2535         if (!smu->pm_enabled)
2536                 return -EOPNOTSUPP;
2537
2538         mutex_lock(&smu->mutex);
2539
2540         if (smu->ppt_funcs->mode1_reset)
2541                 ret = smu->ppt_funcs->mode1_reset(smu);
2542
2543         mutex_unlock(&smu->mutex);
2544
2545         return ret;
2546 }
2547
2548 int smu_mode2_reset(struct smu_context *smu)
2549 {
2550         int ret = 0;
2551
2552         if (!smu->pm_enabled)
2553                 return -EOPNOTSUPP;
2554
2555         mutex_lock(&smu->mutex);
2556
2557         if (smu->ppt_funcs->mode2_reset)
2558                 ret = smu->ppt_funcs->mode2_reset(smu);
2559
2560         mutex_unlock(&smu->mutex);
2561
2562         if (ret)
2563                 dev_err(smu->adev->dev, "Mode2 reset failed!\n");
2564
2565         return ret;
2566 }
2567
2568 int smu_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
2569                                          struct pp_smu_nv_clock_table *max_clocks)
2570 {
2571         int ret = 0;
2572
2573         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2574                 return -EOPNOTSUPP;
2575
2576         mutex_lock(&smu->mutex);
2577
2578         if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc)
2579                 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks);
2580
2581         mutex_unlock(&smu->mutex);
2582
2583         return ret;
2584 }
2585
2586 int smu_get_uclk_dpm_states(struct smu_context *smu,
2587                             unsigned int *clock_values_in_khz,
2588                             unsigned int *num_states)
2589 {
2590         int ret = 0;
2591
2592         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2593                 return -EOPNOTSUPP;
2594
2595         mutex_lock(&smu->mutex);
2596
2597         if (smu->ppt_funcs->get_uclk_dpm_states)
2598                 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states);
2599
2600         mutex_unlock(&smu->mutex);
2601
2602         return ret;
2603 }
2604
2605 enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu)
2606 {
2607         enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT;
2608
2609         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2610                 return -EOPNOTSUPP;
2611
2612         mutex_lock(&smu->mutex);
2613
2614         if (smu->ppt_funcs->get_current_power_state)
2615                 pm_state = smu->ppt_funcs->get_current_power_state(smu);
2616
2617         mutex_unlock(&smu->mutex);
2618
2619         return pm_state;
2620 }
2621
2622 int smu_get_dpm_clock_table(struct smu_context *smu,
2623                             struct dpm_clocks *clock_table)
2624 {
2625         int ret = 0;
2626
2627         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2628                 return -EOPNOTSUPP;
2629
2630         mutex_lock(&smu->mutex);
2631
2632         if (smu->ppt_funcs->get_dpm_clock_table)
2633                 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table);
2634
2635         mutex_unlock(&smu->mutex);
2636
2637         return ret;
2638 }
2639
2640 ssize_t smu_sys_get_gpu_metrics(struct smu_context *smu,
2641                                 void **table)
2642 {
2643         ssize_t size;
2644
2645         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2646                 return -EOPNOTSUPP;
2647
2648         if (!smu->ppt_funcs->get_gpu_metrics)
2649                 return -EOPNOTSUPP;
2650
2651         mutex_lock(&smu->mutex);
2652
2653         size = smu->ppt_funcs->get_gpu_metrics(smu, table);
2654
2655         mutex_unlock(&smu->mutex);
2656
2657         return size;
2658 }
2659
2660 int smu_enable_mgpu_fan_boost(struct smu_context *smu)
2661 {
2662         int ret = 0;
2663
2664         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2665                 return -EOPNOTSUPP;
2666
2667         mutex_lock(&smu->mutex);
2668
2669         if (smu->ppt_funcs->enable_mgpu_fan_boost)
2670                 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu);
2671
2672         mutex_unlock(&smu->mutex);
2673
2674         return ret;
2675 }