drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #define SWSMU_CODE_LAYER_L1
  24
  25 #include <linux/firmware.h>
  26 #include <linux/pci.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_smu.h"
  30 #include "smu_internal.h"
  31 #include "atom.h"
  32 #include "arcturus_ppt.h"
  33 #include "navi10_ppt.h"
  34 #include "sienna_cichlid_ppt.h"
  35 #include "renoir_ppt.h"
  36 #include "amd_pcie.h"
  37
  38 /*
  39  * DO NOT use these for err/warn/info/debug messages.
  40  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  41  * They are more MGPU friendly.
  42  */
  43 #undef pr_err
  44 #undef pr_warn
  45 #undef pr_info
  46 #undef pr_debug
  47
  48 size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
  49 {
  50         size_t size = 0;
  51
  52         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
  53                 return -EOPNOTSUPP;
  54
  55         mutex_lock(&smu->mutex);
  56
  57         size = smu_get_pp_feature_mask(smu, buf);
  58
  59         mutex_unlock(&smu->mutex);
  60
  61         return size;
  62 }
  63
  64 int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask)
  65 {
  66         int ret = 0;
  67
  68         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
  69                 return -EOPNOTSUPP;
  70
  71         mutex_lock(&smu->mutex);
  72
  73         ret = smu_set_pp_feature_mask(smu, new_mask);
  74
  75         mutex_unlock(&smu->mutex);
  76
  77         return ret;
  78 }
  79
  80 int smu_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value)
  81 {
  82         int ret = 0;
  83         struct smu_context *smu = &adev->smu;
  84
  85         if (is_support_sw_smu(adev) && smu->ppt_funcs->get_gfx_off_status)
  86                 *value = smu_get_gfx_off_status(smu);
  87         else
  88                 ret = -EINVAL;
  89
  90         return ret;
  91 }
  92
  93 int smu_set_soft_freq_range(struct smu_context *smu,
  94                             enum smu_clk_type clk_type,
  95                             uint32_t min,
  96                             uint32_t max)
  97 {
  98         int ret = 0;
  99
 100         mutex_lock(&smu->mutex);
 101
 102         if (smu->ppt_funcs->set_soft_freq_limited_range)
 103                 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu,
 104                                                                   clk_type,
 105                                                                   min,
 106                                                                   max);
 107
 108         mutex_unlock(&smu->mutex);
 109
 110         return ret;
 111 }
 112
 113 int smu_get_dpm_freq_range(struct smu_context *smu,
 114                            enum smu_clk_type clk_type,
 115                            uint32_t *min,
 116                            uint32_t *max)
 117 {
 118         int ret = 0;
 119
 120         if (!min && !max)
 121                 return -EINVAL;
 122
 123         mutex_lock(&smu->mutex);
 124
 125         if (smu->ppt_funcs->get_dpm_ultimate_freq)
 126                 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu,
 127                                                             clk_type,
 128                                                             min,
 129                                                             max);
 130
 131         mutex_unlock(&smu->mutex);
 132
 133         return ret;
 134 }
 135
 136 static int smu_dpm_set_vcn_enable_locked(struct smu_context *smu,
 137                                          bool enable)
 138 {
 139         struct smu_power_context *smu_power = &smu->smu_power;
 140         struct smu_power_gate *power_gate = &smu_power->power_gate;
 141         int ret = 0;
 142
 143         if (!smu->ppt_funcs->dpm_set_vcn_enable)
 144                 return 0;
 145
 146         if (atomic_read(&power_gate->vcn_gated) ^ enable)
 147                 return 0;
 148
 149         ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable);
 150         if (!ret)
 151                 atomic_set(&power_gate->vcn_gated, !enable);
 152
 153         return ret;
 154 }
 155
 156 static int smu_dpm_set_vcn_enable(struct smu_context *smu,
 157                                   bool enable)
 158 {
 159         struct smu_power_context *smu_power = &smu->smu_power;
 160         struct smu_power_gate *power_gate = &smu_power->power_gate;
 161         int ret = 0;
 162
 163         mutex_lock(&power_gate->vcn_gate_lock);
 164
 165         ret = smu_dpm_set_vcn_enable_locked(smu, enable);
 166
 167         mutex_unlock(&power_gate->vcn_gate_lock);
 168
 169         return ret;
 170 }
 171
 172 static int smu_dpm_set_jpeg_enable_locked(struct smu_context *smu,
 173                                           bool enable)
 174 {
 175         struct smu_power_context *smu_power = &smu->smu_power;
 176         struct smu_power_gate *power_gate = &smu_power->power_gate;
 177         int ret = 0;
 178
 179         if (!smu->ppt_funcs->dpm_set_jpeg_enable)
 180                 return 0;
 181
 182         if (atomic_read(&power_gate->jpeg_gated) ^ enable)
 183                 return 0;
 184
 185         ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable);
 186         if (!ret)
 187                 atomic_set(&power_gate->jpeg_gated, !enable);
 188
 189         return ret;
 190 }
 191
 192 static int smu_dpm_set_jpeg_enable(struct smu_context *smu,
 193                                    bool enable)
 194 {
 195         struct smu_power_context *smu_power = &smu->smu_power;
 196         struct smu_power_gate *power_gate = &smu_power->power_gate;
 197         int ret = 0;
 198
 199         mutex_lock(&power_gate->jpeg_gate_lock);
 200
 201         ret = smu_dpm_set_jpeg_enable_locked(smu, enable);
 202
 203         mutex_unlock(&power_gate->jpeg_gate_lock);
 204
 205         return ret;
 206 }
 207
 208 /**
 209  * smu_dpm_set_power_gate - power gate/ungate the specific IP block
 210  *
 211  * @smu:        smu_context pointer
 212  * @block_type: the IP block to power gate/ungate
 213  * @gate:       to power gate if true, ungate otherwise
 214  *
 215  * This API uses no smu->mutex lock protection due to:
 216  * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce).
 217  *    This is guarded to be race condition free by the caller.
 218  * 2. Or get called on user setting request of power_dpm_force_performance_level.
 219  *    Under this case, the smu->mutex lock protection is already enforced on
 220  *    the parent API smu_force_performance_level of the call path.
 221  */
 222 int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
 223                            bool gate)
 224 {
 225         int ret = 0;
 226
 227         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
 228                 return -EOPNOTSUPP;
 229
 230         switch (block_type) {
 231         /*
 232          * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses
 233          * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept.
 234          */
 235         case AMD_IP_BLOCK_TYPE_UVD:
 236         case AMD_IP_BLOCK_TYPE_VCN:
 237                 ret = smu_dpm_set_vcn_enable(smu, !gate);
 238                 if (ret)
 239                         dev_err(smu->adev->dev, "Failed to power %s VCN!\n",
 240                                 gate ? "gate" : "ungate");
 241                 break;
 242         case AMD_IP_BLOCK_TYPE_GFX:
 243                 ret = smu_gfx_off_control(smu, gate);
 244                 if (ret)
 245                         dev_err(smu->adev->dev, "Failed to %s gfxoff!\n",
 246                                 gate ? "enable" : "disable");
 247                 break;
 248         case AMD_IP_BLOCK_TYPE_SDMA:
 249                 ret = smu_powergate_sdma(smu, gate);
 250                 if (ret)
 251                         dev_err(smu->adev->dev, "Failed to power %s SDMA!\n",
 252                                 gate ? "gate" : "ungate");
 253                 break;
 254         case AMD_IP_BLOCK_TYPE_JPEG:
 255                 ret = smu_dpm_set_jpeg_enable(smu, !gate);
 256                 if (ret)
 257                         dev_err(smu->adev->dev, "Failed to power %s JPEG!\n",
 258                                 gate ? "gate" : "ungate");
 259                 break;
 260         default:
 261                 dev_err(smu->adev->dev, "Unsupported block type!\n");
 262                 return -EINVAL;
 263         }
 264
 265         return ret;
 266 }
 267
 268 int smu_get_power_num_states(struct smu_context *smu,
 269                              struct pp_states_info *state_info)
 270 {
 271         if (!state_info)
 272                 return -EINVAL;
 273
 274         /* not support power state */
 275         memset(state_info, 0, sizeof(struct pp_states_info));
 276         state_info->nums = 1;
 277         state_info->states[0] = POWER_STATE_TYPE_DEFAULT;
 278
 279         return 0;
 280 }
 281
 282 bool is_support_sw_smu(struct amdgpu_device *adev)
 283 {
 284         if (adev->asic_type >= CHIP_ARCTURUS)
 285                 return true;
 286
 287         return false;
 288 }
 289
 290 int smu_sys_get_pp_table(struct smu_context *smu, void **table)
 291 {
 292         struct smu_table_context *smu_table = &smu->smu_table;
 293         uint32_t powerplay_table_size;
 294
 295         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
 296                 return -EOPNOTSUPP;
 297
 298         if (!smu_table->power_play_table && !smu_table->hardcode_pptable)
 299                 return -EINVAL;
 300
 301         mutex_lock(&smu->mutex);
 302
 303         if (smu_table->hardcode_pptable)
 304                 *table = smu_table->hardcode_pptable;
 305         else
 306                 *table = smu_table->power_play_table;
 307
 308         powerplay_table_size = smu_table->power_play_table_size;
 309
 310         mutex_unlock(&smu->mutex);
 311
 312         return powerplay_table_size;
 313 }
 314
 315 int smu_sys_set_pp_table(struct smu_context *smu,  void *buf, size_t size)
 316 {
 317         struct smu_table_context *smu_table = &smu->smu_table;
 318         ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf;
 319         int ret = 0;
 320
 321         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
 322                 return -EOPNOTSUPP;
 323
 324         if (header->usStructureSize != size) {
 325                 dev_err(smu->adev->dev, "pp table size not matched !\n");
 326                 return -EIO;
 327         }
 328
 329         mutex_lock(&smu->mutex);
 330         if (!smu_table->hardcode_pptable)
 331                 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL);
 332         if (!smu_table->hardcode_pptable) {
 333                 ret = -ENOMEM;
 334                 goto failed;
 335         }
 336
 337         memcpy(smu_table->hardcode_pptable, buf, size);
 338         smu_table->power_play_table = smu_table->hardcode_pptable;
 339         smu_table->power_play_table_size = size;
 340
 341         /*
 342          * Special hw_fini action(for Navi1x, the DPMs disablement will be
 343          * skipped) may be needed for custom pptable uploading.
 344          */
 345         smu->uploading_custom_pp_table = true;
 346
 347         ret = smu_reset(smu);
 348         if (ret)
 349                 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret);
 350
 351         smu->uploading_custom_pp_table = false;
 352
 353 failed:
 354         mutex_unlock(&smu->mutex);
 355         return ret;
 356 }
 357
 358 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu)
 359 {
 360         struct smu_feature *feature = &smu->smu_feature;
 361         int ret = 0;
 362         uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32];
 363
 364         bitmap_zero(feature->allowed, SMU_FEATURE_MAX);
 365
 366         ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask,
 367                                              SMU_FEATURE_MAX/32);
 368         if (ret)
 369                 return ret;
 370
 371         bitmap_or(feature->allowed, feature->allowed,
 372                       (unsigned long *)allowed_feature_mask,
 373                       feature->feature_num);
 374
 375         return ret;
 376 }
 377
 378 static int smu_set_funcs(struct amdgpu_device *adev)
 379 {
 380         struct smu_context *smu = &adev->smu;
 381
 382         if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
 383                 smu->od_enabled = true;
 384
 385         switch (adev->asic_type) {
 386         case CHIP_NAVI10:
 387         case CHIP_NAVI14:
 388         case CHIP_NAVI12:
 389                 navi10_set_ppt_funcs(smu);
 390                 break;
 391         case CHIP_ARCTURUS:
 392                 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
 393                 arcturus_set_ppt_funcs(smu);
 394                 /* OD is not supported on Arcturus */
 395                 smu->od_enabled =false;
 396                 break;
 397         case CHIP_SIENNA_CICHLID:
 398         case CHIP_NAVY_FLOUNDER:
 399                 sienna_cichlid_set_ppt_funcs(smu);
 400                 break;
 401         case CHIP_RENOIR:
 402                 renoir_set_ppt_funcs(smu);
 403                 break;
 404         default:
 405                 return -EINVAL;
 406         }
 407
 408         return 0;
 409 }
 410
 411 static int smu_early_init(void *handle)
 412 {
 413         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 414         struct smu_context *smu = &adev->smu;
 415
 416         smu->adev = adev;
 417         smu->pm_enabled = !!amdgpu_dpm;
 418         smu->is_apu = false;
 419         mutex_init(&smu->mutex);
 420
 421         return smu_set_funcs(adev);
 422 }
 423
 424 static int smu_set_default_dpm_table(struct smu_context *smu)
 425 {
 426         struct smu_power_context *smu_power = &smu->smu_power;
 427         struct smu_power_gate *power_gate = &smu_power->power_gate;
 428         int vcn_gate, jpeg_gate;
 429         int ret = 0;
 430
 431         if (!smu->ppt_funcs->set_default_dpm_table)
 432                 return 0;
 433
 434         mutex_lock(&power_gate->vcn_gate_lock);
 435         mutex_lock(&power_gate->jpeg_gate_lock);
 436
 437         vcn_gate = atomic_read(&power_gate->vcn_gated);
 438         jpeg_gate = atomic_read(&power_gate->jpeg_gated);
 439
 440         ret = smu_dpm_set_vcn_enable_locked(smu, true);
 441         if (ret)
 442                 goto err0_out;
 443
 444         ret = smu_dpm_set_jpeg_enable_locked(smu, true);
 445         if (ret)
 446                 goto err1_out;
 447
 448         ret = smu->ppt_funcs->set_default_dpm_table(smu);
 449         if (ret)
 450                 dev_err(smu->adev->dev,
 451                         "Failed to setup default dpm clock tables!\n");
 452
 453         smu_dpm_set_jpeg_enable_locked(smu, !jpeg_gate);
 454 err1_out:
 455         smu_dpm_set_vcn_enable_locked(smu, !vcn_gate);
 456 err0_out:
 457         mutex_unlock(&power_gate->jpeg_gate_lock);
 458         mutex_unlock(&power_gate->vcn_gate_lock);
 459
 460         return ret;
 461 }
 462
 463 static int smu_late_init(void *handle)
 464 {
 465         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 466         struct smu_context *smu = &adev->smu;
 467         int ret = 0;
 468
 469         if (!smu->pm_enabled)
 470                 return 0;
 471
 472         ret = smu_post_init(smu);
 473         if (ret) {
 474                 dev_err(adev->dev, "Failed to post smu init!\n");
 475                 return ret;
 476         }
 477
 478         ret = smu_set_default_od_settings(smu);
 479         if (ret) {
 480                 dev_err(adev->dev, "Failed to setup default OD settings!\n");
 481                 return ret;
 482         }
 483
 484         /*
 485          * Set initialized values (get from vbios) to dpm tables context such as
 486          * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each
 487          * type of clks.
 488          */
 489         ret = smu_set_default_dpm_table(smu);
 490         if (ret) {
 491                 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n");
 492                 return ret;
 493         }
 494
 495         ret = smu_populate_umd_state_clk(smu);
 496         if (ret) {
 497                 dev_err(adev->dev, "Failed to populate UMD state clocks!\n");
 498                 return ret;
 499         }
 500
 501         ret = smu_get_asic_power_limits(smu);
 502         if (ret) {
 503                 dev_err(adev->dev, "Failed to get asic power limits!\n");
 504                 return ret;
 505         }
 506
 507         smu_get_unique_id(smu);
 508
 509         smu_get_fan_parameters(smu);
 510
 511         smu_handle_task(&adev->smu,
 512                         smu->smu_dpm.dpm_level,
 513                         AMD_PP_TASK_COMPLETE_INIT,
 514                         false);
 515
 516         return 0;
 517 }
 518
 519 static int smu_init_fb_allocations(struct smu_context *smu)
 520 {
 521         struct amdgpu_device *adev = smu->adev;
 522         struct smu_table_context *smu_table = &smu->smu_table;
 523         struct smu_table *tables = smu_table->tables;
 524         struct smu_table *driver_table = &(smu_table->driver_table);
 525         uint32_t max_table_size = 0;
 526         int ret, i;
 527
 528         /* VRAM allocation for tool table */
 529         if (tables[SMU_TABLE_PMSTATUSLOG].size) {
 530                 ret = amdgpu_bo_create_kernel(adev,
 531                                               tables[SMU_TABLE_PMSTATUSLOG].size,
 532                                               tables[SMU_TABLE_PMSTATUSLOG].align,
 533                                               tables[SMU_TABLE_PMSTATUSLOG].domain,
 534                                               &tables[SMU_TABLE_PMSTATUSLOG].bo,
 535                                               &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
 536                                               &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
 537                 if (ret) {
 538                         dev_err(adev->dev, "VRAM allocation for tool table failed!\n");
 539                         return ret;
 540                 }
 541         }
 542
 543         /* VRAM allocation for driver table */
 544         for (i = 0; i < SMU_TABLE_COUNT; i++) {
 545                 if (tables[i].size == 0)
 546                         continue;
 547
 548                 if (i == SMU_TABLE_PMSTATUSLOG)
 549                         continue;
 550
 551                 if (max_table_size < tables[i].size)
 552                         max_table_size = tables[i].size;
 553         }
 554
 555         driver_table->size = max_table_size;
 556         driver_table->align = PAGE_SIZE;
 557         driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM;
 558
 559         ret = amdgpu_bo_create_kernel(adev,
 560                                       driver_table->size,
 561                                       driver_table->align,
 562                                       driver_table->domain,
 563                                       &driver_table->bo,
 564                                       &driver_table->mc_address,
 565                                       &driver_table->cpu_addr);
 566         if (ret) {
 567                 dev_err(adev->dev, "VRAM allocation for driver table failed!\n");
 568                 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
 569                         amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
 570                                               &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
 571                                               &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
 572         }
 573
 574         return ret;
 575 }
 576
 577 static int smu_fini_fb_allocations(struct smu_context *smu)
 578 {
 579         struct smu_table_context *smu_table = &smu->smu_table;
 580         struct smu_table *tables = smu_table->tables;
 581         struct smu_table *driver_table = &(smu_table->driver_table);
 582
 583         if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
 584                 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
 585                                       &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
 586                                       &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
 587
 588         amdgpu_bo_free_kernel(&driver_table->bo,
 589                               &driver_table->mc_address,
 590                               &driver_table->cpu_addr);
 591
 592         return 0;
 593 }
 594
 595 /**
 596  * smu_alloc_memory_pool - allocate memory pool in the system memory
 597  *
 598  * @smu: amdgpu_device pointer
 599  *
 600  * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr
 601  * and DramLogSetDramAddr can notify it changed.
 602  *
 603  * Returns 0 on success, error on failure.
 604  */
 605 static int smu_alloc_memory_pool(struct smu_context *smu)
 606 {
 607         struct amdgpu_device *adev = smu->adev;
 608         struct smu_table_context *smu_table = &smu->smu_table;
 609         struct smu_table *memory_pool = &smu_table->memory_pool;
 610         uint64_t pool_size = smu->pool_size;
 611         int ret = 0;
 612
 613         if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO)
 614                 return ret;
 615
 616         memory_pool->size = pool_size;
 617         memory_pool->align = PAGE_SIZE;
 618         memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT;
 619
 620         switch (pool_size) {
 621         case SMU_MEMORY_POOL_SIZE_256_MB:
 622         case SMU_MEMORY_POOL_SIZE_512_MB:
 623         case SMU_MEMORY_POOL_SIZE_1_GB:
 624         case SMU_MEMORY_POOL_SIZE_2_GB:
 625                 ret = amdgpu_bo_create_kernel(adev,
 626                                               memory_pool->size,
 627                                               memory_pool->align,
 628                                               memory_pool->domain,
 629                                               &memory_pool->bo,
 630                                               &memory_pool->mc_address,
 631                                               &memory_pool->cpu_addr);
 632                 if (ret)
 633                         dev_err(adev->dev, "VRAM allocation for dramlog failed!\n");
 634                 break;
 635         default:
 636                 break;
 637         }
 638
 639         return ret;
 640 }
 641
 642 static int smu_free_memory_pool(struct smu_context *smu)
 643 {
 644         struct smu_table_context *smu_table = &smu->smu_table;
 645         struct smu_table *memory_pool = &smu_table->memory_pool;
 646
 647         if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO)
 648                 return 0;
 649
 650         amdgpu_bo_free_kernel(&memory_pool->bo,
 651                               &memory_pool->mc_address,
 652                               &memory_pool->cpu_addr);
 653
 654         memset(memory_pool, 0, sizeof(struct smu_table));
 655
 656         return 0;
 657 }
 658
 659 static int smu_alloc_dummy_read_table(struct smu_context *smu)
 660 {
 661         struct smu_table_context *smu_table = &smu->smu_table;
 662         struct smu_table *dummy_read_1_table =
 663                         &smu_table->dummy_read_1_table;
 664         struct amdgpu_device *adev = smu->adev;
 665         int ret = 0;
 666
 667         dummy_read_1_table->size = 0x40000;
 668         dummy_read_1_table->align = PAGE_SIZE;
 669         dummy_read_1_table->domain = AMDGPU_GEM_DOMAIN_VRAM;
 670
 671         ret = amdgpu_bo_create_kernel(adev,
 672                                       dummy_read_1_table->size,
 673                                       dummy_read_1_table->align,
 674                                       dummy_read_1_table->domain,
 675                                       &dummy_read_1_table->bo,
 676                                       &dummy_read_1_table->mc_address,
 677                                       &dummy_read_1_table->cpu_addr);
 678         if (ret)
 679                 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n");
 680
 681         return ret;
 682 }
 683
 684 static void smu_free_dummy_read_table(struct smu_context *smu)
 685 {
 686         struct smu_table_context *smu_table = &smu->smu_table;
 687         struct smu_table *dummy_read_1_table =
 688                         &smu_table->dummy_read_1_table;
 689
 690
 691         amdgpu_bo_free_kernel(&dummy_read_1_table->bo,
 692                               &dummy_read_1_table->mc_address,
 693                               &dummy_read_1_table->cpu_addr);
 694
 695         memset(dummy_read_1_table, 0, sizeof(struct smu_table));
 696 }
 697
 698 static int smu_smc_table_sw_init(struct smu_context *smu)
 699 {
 700         int ret;
 701
 702         /**
 703          * Create smu_table structure, and init smc tables such as
 704          * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc.
 705          */
 706         ret = smu_init_smc_tables(smu);
 707         if (ret) {
 708                 dev_err(smu->adev->dev, "Failed to init smc tables!\n");
 709                 return ret;
 710         }
 711
 712         /**
 713          * Create smu_power_context structure, and allocate smu_dpm_context and
 714          * context size to fill the smu_power_context data.
 715          */
 716         ret = smu_init_power(smu);
 717         if (ret) {
 718                 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n");
 719                 return ret;
 720         }
 721
 722         /*
 723          * allocate vram bos to store smc table contents.
 724          */
 725         ret = smu_init_fb_allocations(smu);
 726         if (ret)
 727                 return ret;
 728
 729         ret = smu_alloc_memory_pool(smu);
 730         if (ret)
 731                 return ret;
 732
 733         ret = smu_alloc_dummy_read_table(smu);
 734         if (ret)
 735                 return ret;
 736
 737         ret = smu_i2c_init(smu, &smu->adev->pm.smu_i2c);
 738         if (ret)
 739                 return ret;
 740
 741         return 0;
 742 }
 743
 744 static int smu_smc_table_sw_fini(struct smu_context *smu)
 745 {
 746         int ret;
 747
 748         smu_i2c_fini(smu, &smu->adev->pm.smu_i2c);
 749
 750         smu_free_dummy_read_table(smu);
 751
 752         ret = smu_free_memory_pool(smu);
 753         if (ret)
 754                 return ret;
 755
 756         ret = smu_fini_fb_allocations(smu);
 757         if (ret)
 758                 return ret;
 759
 760         ret = smu_fini_power(smu);
 761         if (ret) {
 762                 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n");
 763                 return ret;
 764         }
 765
 766         ret = smu_fini_smc_tables(smu);
 767         if (ret) {
 768                 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n");
 769                 return ret;
 770         }
 771
 772         return 0;
 773 }
 774
 775 static void smu_throttling_logging_work_fn(struct work_struct *work)
 776 {
 777         struct smu_context *smu = container_of(work, struct smu_context,
 778                                                throttling_logging_work);
 779
 780         smu_log_thermal_throttling(smu);
 781 }
 782
 783 static int smu_sw_init(void *handle)
 784 {
 785         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 786         struct smu_context *smu = &adev->smu;
 787         int ret;
 788
 789         smu->pool_size = adev->pm.smu_prv_buffer_size;
 790         smu->smu_feature.feature_num = SMU_FEATURE_MAX;
 791         mutex_init(&smu->smu_feature.mutex);
 792         bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX);
 793         bitmap_zero(smu->smu_feature.enabled, SMU_FEATURE_MAX);
 794         bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX);
 795
 796         mutex_init(&smu->smu_baco.mutex);
 797         smu->smu_baco.state = SMU_BACO_STATE_EXIT;
 798         smu->smu_baco.platform_support = false;
 799
 800         mutex_init(&smu->sensor_lock);
 801         mutex_init(&smu->metrics_lock);
 802         mutex_init(&smu->message_lock);
 803
 804         INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn);
 805         atomic64_set(&smu->throttle_int_counter, 0);
 806         smu->watermarks_bitmap = 0;
 807         smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 808         smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 809
 810         atomic_set(&smu->smu_power.power_gate.vcn_gated, 1);
 811         atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1);
 812         mutex_init(&smu->smu_power.power_gate.vcn_gate_lock);
 813         mutex_init(&smu->smu_power.power_gate.jpeg_gate_lock);
 814
 815         smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
 816         smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
 817         smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;
 818         smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2;
 819         smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3;
 820         smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4;
 821         smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5;
 822         smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6;
 823
 824         smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 825         smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
 826         smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING;
 827         smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO;
 828         smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR;
 829         smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE;
 830         smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM;
 831         smu->display_config = &adev->pm.pm_display_cfg;
 832
 833         smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
 834         smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
 835         ret = smu_init_microcode(smu);
 836         if (ret) {
 837                 dev_err(adev->dev, "Failed to load smu firmware!\n");
 838                 return ret;
 839         }
 840
 841         ret = smu_smc_table_sw_init(smu);
 842         if (ret) {
 843                 dev_err(adev->dev, "Failed to sw init smc table!\n");
 844                 return ret;
 845         }
 846
 847         ret = smu_register_irq_handler(smu);
 848         if (ret) {
 849                 dev_err(adev->dev, "Failed to register smc irq handler!\n");
 850                 return ret;
 851         }
 852
 853         return 0;
 854 }
 855
 856 static int smu_sw_fini(void *handle)
 857 {
 858         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 859         struct smu_context *smu = &adev->smu;
 860         int ret;
 861
 862         ret = smu_smc_table_sw_fini(smu);
 863         if (ret) {
 864                 dev_err(adev->dev, "Failed to sw fini smc table!\n");
 865                 return ret;
 866         }
 867
 868         smu_fini_microcode(smu);
 869
 870         return 0;
 871 }
 872
 873 static int smu_get_thermal_temperature_range(struct smu_context *smu)
 874 {
 875         struct amdgpu_device *adev = smu->adev;
 876         struct smu_temperature_range *range =
 877                                 &smu->thermal_range;
 878         int ret = 0;
 879
 880         if (!smu->ppt_funcs->get_thermal_temperature_range)
 881                 return 0;
 882
 883         ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range);
 884         if (ret)
 885                 return ret;
 886
 887         adev->pm.dpm.thermal.min_temp = range->min;
 888         adev->pm.dpm.thermal.max_temp = range->max;
 889         adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max;
 890         adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min;
 891         adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max;
 892         adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max;
 893         adev->pm.dpm.thermal.min_mem_temp = range->mem_min;
 894         adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max;
 895         adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max;
 896
 897         return ret;
 898 }
 899
 900 static int smu_smc_hw_setup(struct smu_context *smu)
 901 {
 902         struct amdgpu_device *adev = smu->adev;
 903         uint32_t pcie_gen = 0, pcie_width = 0;
 904         int ret;
 905
 906         if (adev->in_suspend && smu_is_dpm_running(smu)) {
 907                 dev_info(adev->dev, "dpm has been enabled\n");
 908                 return 0;
 909         }
 910
 911         ret = smu_init_display_count(smu, 0);
 912         if (ret) {
 913                 dev_info(adev->dev, "Failed to pre-set display count as 0!\n");
 914                 return ret;
 915         }
 916
 917         ret = smu_set_driver_table_location(smu);
 918         if (ret) {
 919                 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n");
 920                 return ret;
 921         }
 922
 923         /*
 924          * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools.
 925          */
 926         ret = smu_set_tool_table_location(smu);
 927         if (ret) {
 928                 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n");
 929                 return ret;
 930         }
 931
 932         /*
 933          * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify
 934          * pool location.
 935          */
 936         ret = smu_notify_memory_pool_location(smu);
 937         if (ret) {
 938                 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n");
 939                 return ret;
 940         }
 941
 942         /* smu_dump_pptable(smu); */
 943         /*
 944          * Copy pptable bo in the vram to smc with SMU MSGs such as
 945          * SetDriverDramAddr and TransferTableDram2Smu.
 946          */
 947         ret = smu_write_pptable(smu);
 948         if (ret) {
 949                 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n");
 950                 return ret;
 951         }
 952
 953         /* issue Run*Btc msg */
 954         ret = smu_run_btc(smu);
 955         if (ret)
 956                 return ret;
 957
 958         ret = smu_feature_set_allowed_mask(smu);
 959         if (ret) {
 960                 dev_err(adev->dev, "Failed to set driver allowed features mask!\n");
 961                 return ret;
 962         }
 963
 964         ret = smu_system_features_control(smu, true);
 965         if (ret) {
 966                 dev_err(adev->dev, "Failed to enable requested dpm features!\n");
 967                 return ret;
 968         }
 969
 970         if (!smu_is_dpm_running(smu))
 971                 dev_info(adev->dev, "dpm has been disabled\n");
 972
 973         if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
 974                 pcie_gen = 3;
 975         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
 976                 pcie_gen = 2;
 977         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
 978                 pcie_gen = 1;
 979         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
 980                 pcie_gen = 0;
 981
 982         /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
 983          * Bit 15:8:  PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
 984          * Bit 7:0:   PCIE lane width, 1 to 7 corresponds is x1 to x32
 985          */
 986         if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
 987                 pcie_width = 6;
 988         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
 989                 pcie_width = 5;
 990         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
 991                 pcie_width = 4;
 992         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
 993                 pcie_width = 3;
 994         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
 995                 pcie_width = 2;
 996         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
 997                 pcie_width = 1;
 998         ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width);
 999         if (ret) {
1000                 dev_err(adev->dev, "Attempt to override pcie params failed!\n");
1001                 return ret;
1002         }
1003
1004         ret = smu_get_thermal_temperature_range(smu);
1005         if (ret) {
1006                 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n");
1007                 return ret;
1008         }
1009
1010         ret = smu_enable_thermal_alert(smu);
1011         if (ret) {
1012                 dev_err(adev->dev, "Failed to enable thermal alert!\n");
1013                 return ret;
1014         }
1015
1016         ret = smu_notify_display_change(smu);
1017         if (ret)
1018                 return ret;
1019
1020         /*
1021          * Set min deep sleep dce fclk with bootup value from vbios via
1022          * SetMinDeepSleepDcefclk MSG.
1023          */
1024         ret = smu_set_min_dcef_deep_sleep(smu,
1025                                           smu->smu_table.boot_values.dcefclk / 100);
1026         if (ret)
1027                 return ret;
1028
1029         return ret;
1030 }
1031
1032 static int smu_start_smc_engine(struct smu_context *smu)
1033 {
1034         struct amdgpu_device *adev = smu->adev;
1035         int ret = 0;
1036
1037         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1038                 if (adev->asic_type < CHIP_NAVI10) {
1039                         if (smu->ppt_funcs->load_microcode) {
1040                                 ret = smu->ppt_funcs->load_microcode(smu);
1041                                 if (ret)
1042                                         return ret;
1043                         }
1044                 }
1045         }
1046
1047         if (smu->ppt_funcs->check_fw_status) {
1048                 ret = smu->ppt_funcs->check_fw_status(smu);
1049                 if (ret) {
1050                         dev_err(adev->dev, "SMC is not ready\n");
1051                         return ret;
1052                 }
1053         }
1054
1055         /*
1056          * Send msg GetDriverIfVersion to check if the return value is equal
1057          * with DRIVER_IF_VERSION of smc header.
1058          */
1059         ret = smu_check_fw_version(smu);
1060         if (ret)
1061                 return ret;
1062
1063         return ret;
1064 }
1065
1066 static int smu_hw_init(void *handle)
1067 {
1068         int ret;
1069         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1070         struct smu_context *smu = &adev->smu;
1071
1072         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) {
1073                 smu->pm_enabled = false;
1074                 return 0;
1075         }
1076
1077         ret = smu_start_smc_engine(smu);
1078         if (ret) {
1079                 dev_err(adev->dev, "SMC engine is not correctly up!\n");
1080                 return ret;
1081         }
1082
1083         if (smu->is_apu) {
1084                 smu_powergate_sdma(&adev->smu, false);
1085                 smu_dpm_set_vcn_enable(smu, true);
1086                 smu_dpm_set_jpeg_enable(smu, true);
1087                 smu_set_gfx_cgpg(&adev->smu, true);
1088         }
1089
1090         if (!smu->pm_enabled)
1091                 return 0;
1092
1093         /* get boot_values from vbios to set revision, gfxclk, and etc. */
1094         ret = smu_get_vbios_bootup_values(smu);
1095         if (ret) {
1096                 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n");
1097                 return ret;
1098         }
1099
1100         ret = smu_setup_pptable(smu);
1101         if (ret) {
1102                 dev_err(adev->dev, "Failed to setup pptable!\n");
1103                 return ret;
1104         }
1105
1106         ret = smu_get_driver_allowed_feature_mask(smu);
1107         if (ret)
1108                 return ret;
1109
1110         ret = smu_smc_hw_setup(smu);
1111         if (ret) {
1112                 dev_err(adev->dev, "Failed to setup smc hw!\n");
1113                 return ret;
1114         }
1115
1116         /*
1117          * Move maximum sustainable clock retrieving here considering
1118          * 1. It is not needed on resume(from S3).
1119          * 2. DAL settings come between .hw_init and .late_init of SMU.
1120          *    And DAL needs to know the maximum sustainable clocks. Thus
1121          *    it cannot be put in .late_init().
1122          */
1123         ret = smu_init_max_sustainable_clocks(smu);
1124         if (ret) {
1125                 dev_err(adev->dev, "Failed to init max sustainable clocks!\n");
1126                 return ret;
1127         }
1128
1129         adev->pm.dpm_enabled = true;
1130
1131         dev_info(adev->dev, "SMU is initialized successfully!\n");
1132
1133         return 0;
1134 }
1135
1136 static int smu_disable_dpms(struct smu_context *smu)
1137 {
1138         struct amdgpu_device *adev = smu->adev;
1139         int ret = 0;
1140         bool use_baco = !smu->is_apu &&
1141                 ((amdgpu_in_reset(adev) &&
1142                   (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) ||
1143                  ((adev->in_runpm || adev->in_hibernate) && amdgpu_asic_supports_baco(adev)));
1144
1145         /*
1146          * For custom pptable uploading, skip the DPM features
1147          * disable process on Navi1x ASICs.
1148          *   - As the gfx related features are under control of
1149          *     RLC on those ASICs. RLC reinitialization will be
1150          *     needed to reenable them. That will cost much more
1151          *     efforts.
1152          *
1153          *   - SMU firmware can handle the DPM reenablement
1154          *     properly.
1155          */
1156         if (smu->uploading_custom_pp_table &&
1157             (adev->asic_type >= CHIP_NAVI10) &&
1158             (adev->asic_type <= CHIP_NAVY_FLOUNDER))
1159                 return 0;
1160
1161         /*
1162          * For Sienna_Cichlid, PMFW will handle the features disablement properly
1163          * on BACO in. Driver involvement is unnecessary.
1164          */
1165         if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
1166              use_baco)
1167                 return 0;
1168
1169         /*
1170          * For gpu reset, runpm and hibernation through BACO,
1171          * BACO feature has to be kept enabled.
1172          */
1173         if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) {
1174                 ret = smu_disable_all_features_with_exception(smu,
1175                                                               SMU_FEATURE_BACO_BIT);
1176                 if (ret)
1177                         dev_err(adev->dev, "Failed to disable smu features except BACO.\n");
1178         } else {
1179                 ret = smu_system_features_control(smu, false);
1180                 if (ret)
1181                         dev_err(adev->dev, "Failed to disable smu features.\n");
1182         }
1183
1184         if (adev->asic_type >= CHIP_NAVI10 &&
1185             adev->gfx.rlc.funcs->stop)
1186                 adev->gfx.rlc.funcs->stop(adev);
1187
1188         return ret;
1189 }
1190
1191 static int smu_smc_hw_cleanup(struct smu_context *smu)
1192 {
1193         struct amdgpu_device *adev = smu->adev;
1194         int ret = 0;
1195
1196         cancel_work_sync(&smu->throttling_logging_work);
1197
1198         ret = smu_disable_thermal_alert(smu);
1199         if (ret) {
1200                 dev_err(adev->dev, "Fail to disable thermal alert!\n");
1201                 return ret;
1202         }
1203
1204         ret = smu_disable_dpms(smu);
1205         if (ret) {
1206                 dev_err(adev->dev, "Fail to disable dpm features!\n");
1207                 return ret;
1208         }
1209
1210         return 0;
1211 }
1212
1213 static int smu_hw_fini(void *handle)
1214 {
1215         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1216         struct smu_context *smu = &adev->smu;
1217         int ret = 0;
1218
1219         if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1220                 return 0;
1221
1222         if (smu->is_apu) {
1223                 smu_powergate_sdma(&adev->smu, true);
1224                 smu_dpm_set_vcn_enable(smu, false);
1225                 smu_dpm_set_jpeg_enable(smu, false);
1226         }
1227
1228         if (!smu->pm_enabled)
1229                 return 0;
1230
1231         adev->pm.dpm_enabled = false;
1232
1233         ret = smu_smc_hw_cleanup(smu);
1234         if (ret)
1235                 return ret;
1236
1237         return 0;
1238 }
1239
1240 int smu_reset(struct smu_context *smu)
1241 {
1242         struct amdgpu_device *adev = smu->adev;
1243         int ret;
1244
1245         amdgpu_gfx_off_ctrl(smu->adev, false);
1246
1247         ret = smu_hw_fini(adev);
1248         if (ret)
1249                 return ret;
1250
1251         ret = smu_hw_init(adev);
1252         if (ret)
1253                 return ret;
1254
1255         ret = smu_late_init(adev);
1256         if (ret)
1257                 return ret;
1258
1259         amdgpu_gfx_off_ctrl(smu->adev, true);
1260
1261         return 0;
1262 }
1263
1264 static int smu_suspend(void *handle)
1265 {
1266         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1267         struct smu_context *smu = &adev->smu;
1268         int ret;
1269
1270         if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1271                 return 0;
1272
1273         if (!smu->pm_enabled)
1274                 return 0;
1275
1276         adev->pm.dpm_enabled = false;
1277
1278         ret = smu_smc_hw_cleanup(smu);
1279         if (ret)
1280                 return ret;
1281
1282         smu->watermarks_bitmap &= ~(WATERMARKS_LOADED);
1283
1284         if (smu->is_apu)
1285                 smu_set_gfx_cgpg(&adev->smu, false);
1286
1287         return 0;
1288 }
1289
1290 static int smu_resume(void *handle)
1291 {
1292         int ret;
1293         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1294         struct smu_context *smu = &adev->smu;
1295
1296         if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1297                 return 0;
1298
1299         if (!smu->pm_enabled)
1300                 return 0;
1301
1302         dev_info(adev->dev, "SMU is resuming...\n");
1303
1304         ret = smu_start_smc_engine(smu);
1305         if (ret) {
1306                 dev_err(adev->dev, "SMC engine is not correctly up!\n");
1307                 return ret;
1308         }
1309
1310         ret = smu_smc_hw_setup(smu);
1311         if (ret) {
1312                 dev_err(adev->dev, "Failed to setup smc hw!\n");
1313                 return ret;
1314         }
1315
1316         if (smu->is_apu)
1317                 smu_set_gfx_cgpg(&adev->smu, true);
1318
1319         smu->disable_uclk_switch = 0;
1320
1321         adev->pm.dpm_enabled = true;
1322
1323         dev_info(adev->dev, "SMU is resumed successfully!\n");
1324
1325         return 0;
1326 }
1327
1328 int smu_display_configuration_change(struct smu_context *smu,
1329                                      const struct amd_pp_display_configuration *display_config)
1330 {
1331         int index = 0;
1332         int num_of_active_display = 0;
1333
1334         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1335                 return -EOPNOTSUPP;
1336
1337         if (!display_config)
1338                 return -EINVAL;
1339
1340         mutex_lock(&smu->mutex);
1341
1342         smu_set_min_dcef_deep_sleep(smu,
1343                                     display_config->min_dcef_deep_sleep_set_clk / 100);
1344
1345         for (index = 0; index < display_config->num_path_including_non_display; index++) {
1346                 if (display_config->displays[index].controller_id != 0)
1347                         num_of_active_display++;
1348         }
1349
1350         smu_set_active_display_count(smu, num_of_active_display);
1351
1352         smu_store_cc6_data(smu, display_config->cpu_pstate_separation_time,
1353                            display_config->cpu_cc6_disable,
1354                            display_config->cpu_pstate_disable,
1355                            display_config->nb_pstate_switch_disable);
1356
1357         mutex_unlock(&smu->mutex);
1358
1359         return 0;
1360 }
1361
1362 static int smu_get_clock_info(struct smu_context *smu,
1363                               struct smu_clock_info *clk_info,
1364                               enum smu_perf_level_designation designation)
1365 {
1366         int ret;
1367         struct smu_performance_level level = {0};
1368
1369         if (!clk_info)
1370                 return -EINVAL;
1371
1372         ret = smu_get_perf_level(smu, PERF_LEVEL_ACTIVITY, &level);
1373         if (ret)
1374                 return -EINVAL;
1375
1376         clk_info->min_mem_clk = level.memory_clock;
1377         clk_info->min_eng_clk = level.core_clock;
1378         clk_info->min_bus_bandwidth = level.non_local_mem_freq * level.non_local_mem_width;
1379
1380         ret = smu_get_perf_level(smu, designation, &level);
1381         if (ret)
1382                 return -EINVAL;
1383
1384         clk_info->min_mem_clk = level.memory_clock;
1385         clk_info->min_eng_clk = level.core_clock;
1386         clk_info->min_bus_bandwidth = level.non_local_mem_freq * level.non_local_mem_width;
1387
1388         return 0;
1389 }
1390
1391 int smu_get_current_clocks(struct smu_context *smu,
1392                            struct amd_pp_clock_info *clocks)
1393 {
1394         struct amd_pp_simple_clock_info simple_clocks = {0};
1395         struct smu_clock_info hw_clocks;
1396         int ret = 0;
1397
1398         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1399                 return -EOPNOTSUPP;
1400
1401         mutex_lock(&smu->mutex);
1402
1403         smu_get_dal_power_level(smu, &simple_clocks);
1404
1405         if (smu->support_power_containment)
1406                 ret = smu_get_clock_info(smu, &hw_clocks,
1407                                          PERF_LEVEL_POWER_CONTAINMENT);
1408         else
1409                 ret = smu_get_clock_info(smu, &hw_clocks, PERF_LEVEL_ACTIVITY);
1410
1411         if (ret) {
1412                 dev_err(smu->adev->dev, "Error in smu_get_clock_info\n");
1413                 goto failed;
1414         }
1415
1416         clocks->min_engine_clock = hw_clocks.min_eng_clk;
1417         clocks->max_engine_clock = hw_clocks.max_eng_clk;
1418         clocks->min_memory_clock = hw_clocks.min_mem_clk;
1419         clocks->max_memory_clock = hw_clocks.max_mem_clk;
1420         clocks->min_bus_bandwidth = hw_clocks.min_bus_bandwidth;
1421         clocks->max_bus_bandwidth = hw_clocks.max_bus_bandwidth;
1422         clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1423         clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1424
1425         if (simple_clocks.level == 0)
1426                 clocks->max_clocks_state = PP_DAL_POWERLEVEL_7;
1427         else
1428                 clocks->max_clocks_state = simple_clocks.level;
1429
1430         if (!smu_get_current_shallow_sleep_clocks(smu, &hw_clocks)) {
1431                 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1432                 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1433         }
1434
1435 failed:
1436         mutex_unlock(&smu->mutex);
1437         return ret;
1438 }
1439
1440 static int smu_set_clockgating_state(void *handle,
1441                                      enum amd_clockgating_state state)
1442 {
1443         return 0;
1444 }
1445
1446 static int smu_set_powergating_state(void *handle,
1447                                      enum amd_powergating_state state)
1448 {
1449         return 0;
1450 }
1451
1452 static int smu_enable_umd_pstate(void *handle,
1453                       enum amd_dpm_forced_level *level)
1454 {
1455         uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
1456                                         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
1457                                         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
1458                                         AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
1459
1460         struct smu_context *smu = (struct smu_context*)(handle);
1461         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1462
1463         if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1464                 return -EINVAL;
1465
1466         if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) {
1467                 /* enter umd pstate, save current level, disable gfx cg*/
1468                 if (*level & profile_mode_mask) {
1469                         smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
1470                         smu_dpm_ctx->enable_umd_pstate = true;
1471                         amdgpu_device_ip_set_powergating_state(smu->adev,
1472                                                                AMD_IP_BLOCK_TYPE_GFX,
1473                                                                AMD_PG_STATE_UNGATE);
1474                         amdgpu_device_ip_set_clockgating_state(smu->adev,
1475                                                                AMD_IP_BLOCK_TYPE_GFX,
1476                                                                AMD_CG_STATE_UNGATE);
1477                         smu_gfx_ulv_control(smu, false);
1478                         smu_deep_sleep_control(smu, false);
1479                 }
1480         } else {
1481                 /* exit umd pstate, restore level, enable gfx cg*/
1482                 if (!(*level & profile_mode_mask)) {
1483                         if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
1484                                 *level = smu_dpm_ctx->saved_dpm_level;
1485                         smu_dpm_ctx->enable_umd_pstate = false;
1486                         smu_deep_sleep_control(smu, true);
1487                         smu_gfx_ulv_control(smu, true);
1488                         amdgpu_device_ip_set_clockgating_state(smu->adev,
1489                                                                AMD_IP_BLOCK_TYPE_GFX,
1490                                                                AMD_CG_STATE_GATE);
1491                         amdgpu_device_ip_set_powergating_state(smu->adev,
1492                                                                AMD_IP_BLOCK_TYPE_GFX,
1493                                                                AMD_PG_STATE_GATE);
1494                 }
1495         }
1496
1497         return 0;
1498 }
1499
1500 static int smu_adjust_power_state_dynamic(struct smu_context *smu,
1501                                    enum amd_dpm_forced_level level,
1502                                    bool skip_display_settings)
1503 {
1504         int ret = 0;
1505         int index = 0;
1506         long workload;
1507         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1508
1509         if (!skip_display_settings) {
1510                 ret = smu_display_config_changed(smu);
1511                 if (ret) {
1512                         dev_err(smu->adev->dev, "Failed to change display config!");
1513                         return ret;
1514                 }
1515         }
1516
1517         ret = smu_apply_clocks_adjust_rules(smu);
1518         if (ret) {
1519                 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!");
1520                 return ret;
1521         }
1522
1523         if (!skip_display_settings) {
1524                 ret = smu_notify_smc_display_config(smu);
1525                 if (ret) {
1526                         dev_err(smu->adev->dev, "Failed to notify smc display config!");
1527                         return ret;
1528                 }
1529         }
1530
1531         if (smu_dpm_ctx->dpm_level != level) {
1532                 ret = smu_asic_set_performance_level(smu, level);
1533                 if (ret) {
1534                         dev_err(smu->adev->dev, "Failed to set performance level!");
1535                         return ret;
1536                 }
1537
1538                 /* update the saved copy */
1539                 smu_dpm_ctx->dpm_level = level;
1540         }
1541
1542         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1543                 index = fls(smu->workload_mask);
1544                 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1545                 workload = smu->workload_setting[index];
1546
1547                 if (smu->power_profile_mode != workload)
1548                         smu_set_power_profile_mode(smu, &workload, 0, false);
1549         }
1550
1551         return ret;
1552 }
1553
1554 int smu_handle_task(struct smu_context *smu,
1555                     enum amd_dpm_forced_level level,
1556                     enum amd_pp_task task_id,
1557                     bool lock_needed)
1558 {
1559         int ret = 0;
1560
1561         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1562                 return -EOPNOTSUPP;
1563
1564         if (lock_needed)
1565                 mutex_lock(&smu->mutex);
1566
1567         switch (task_id) {
1568         case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
1569                 ret = smu_pre_display_config_changed(smu);
1570                 if (ret)
1571                         goto out;
1572                 ret = smu_set_cpu_power_state(smu);
1573                 if (ret)
1574                         goto out;
1575                 ret = smu_adjust_power_state_dynamic(smu, level, false);
1576                 break;
1577         case AMD_PP_TASK_COMPLETE_INIT:
1578         case AMD_PP_TASK_READJUST_POWER_STATE:
1579                 ret = smu_adjust_power_state_dynamic(smu, level, true);
1580                 break;
1581         default:
1582                 break;
1583         }
1584
1585 out:
1586         if (lock_needed)
1587                 mutex_unlock(&smu->mutex);
1588
1589         return ret;
1590 }
1591
1592 int smu_switch_power_profile(struct smu_context *smu,
1593                              enum PP_SMC_POWER_PROFILE type,
1594                              bool en)
1595 {
1596         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1597         long workload;
1598         uint32_t index;
1599
1600         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1601                 return -EOPNOTSUPP;
1602
1603         if (!(type < PP_SMC_POWER_PROFILE_CUSTOM))
1604                 return -EINVAL;
1605
1606         mutex_lock(&smu->mutex);
1607
1608         if (!en) {
1609                 smu->workload_mask &= ~(1 << smu->workload_prority[type]);
1610                 index = fls(smu->workload_mask);
1611                 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1612                 workload = smu->workload_setting[index];
1613         } else {
1614                 smu->workload_mask |= (1 << smu->workload_prority[type]);
1615                 index = fls(smu->workload_mask);
1616                 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1617                 workload = smu->workload_setting[index];
1618         }
1619
1620         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
1621                 smu_set_power_profile_mode(smu, &workload, 0, false);
1622
1623         mutex_unlock(&smu->mutex);
1624
1625         return 0;
1626 }
1627
1628 enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu)
1629 {
1630         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1631         enum amd_dpm_forced_level level;
1632
1633         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1634                 return -EOPNOTSUPP;
1635
1636         if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1637                 return -EINVAL;
1638
1639         mutex_lock(&(smu->mutex));
1640         level = smu_dpm_ctx->dpm_level;
1641         mutex_unlock(&(smu->mutex));
1642
1643         return level;
1644 }
1645
1646 int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
1647 {
1648         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1649         int ret = 0;
1650
1651         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1652                 return -EOPNOTSUPP;
1653
1654         if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1655                 return -EINVAL;
1656
1657         mutex_lock(&smu->mutex);
1658
1659         ret = smu_enable_umd_pstate(smu, &level);
1660         if (ret) {
1661                 mutex_unlock(&smu->mutex);
1662                 return ret;
1663         }
1664
1665         ret = smu_handle_task(smu, level,
1666                               AMD_PP_TASK_READJUST_POWER_STATE,
1667                               false);
1668
1669         mutex_unlock(&smu->mutex);
1670
1671         return ret;
1672 }
1673
1674 int smu_set_display_count(struct smu_context *smu, uint32_t count)
1675 {
1676         int ret = 0;
1677
1678         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1679                 return -EOPNOTSUPP;
1680
1681         mutex_lock(&smu->mutex);
1682         ret = smu_init_display_count(smu, count);
1683         mutex_unlock(&smu->mutex);
1684
1685         return ret;
1686 }
1687
1688 int smu_force_clk_levels(struct smu_context *smu,
1689                          enum smu_clk_type clk_type,
1690                          uint32_t mask)
1691 {
1692         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1693         int ret = 0;
1694
1695         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1696                 return -EOPNOTSUPP;
1697
1698         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1699                 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n");
1700                 return -EINVAL;
1701         }
1702
1703         mutex_lock(&smu->mutex);
1704
1705         if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels)
1706                 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask);
1707
1708         mutex_unlock(&smu->mutex);
1709
1710         return ret;
1711 }
1712
1713 /*
1714  * On system suspending or resetting, the dpm_enabled
1715  * flag will be cleared. So that those SMU services which
1716  * are not supported will be gated.
1717  * However, the mp1 state setting should still be granted
1718  * even if the dpm_enabled cleared.
1719  */
1720 int smu_set_mp1_state(struct smu_context *smu,
1721                       enum pp_mp1_state mp1_state)
1722 {
1723         uint16_t msg;
1724         int ret;
1725
1726         if (!smu->pm_enabled)
1727                 return -EOPNOTSUPP;
1728
1729         mutex_lock(&smu->mutex);
1730
1731         switch (mp1_state) {
1732         case PP_MP1_STATE_SHUTDOWN:
1733                 msg = SMU_MSG_PrepareMp1ForShutdown;
1734                 break;
1735         case PP_MP1_STATE_UNLOAD:
1736                 msg = SMU_MSG_PrepareMp1ForUnload;
1737                 break;
1738         case PP_MP1_STATE_RESET:
1739                 msg = SMU_MSG_PrepareMp1ForReset;
1740                 break;
1741         case PP_MP1_STATE_NONE:
1742         default:
1743                 mutex_unlock(&smu->mutex);
1744                 return 0;
1745         }
1746
1747         ret = smu_send_smc_msg(smu, msg, NULL);
1748         /* some asics may not support those messages */
1749         if (ret == -EINVAL)
1750                 ret = 0;
1751         if (ret)
1752                 dev_err(smu->adev->dev, "[PrepareMp1] Failed!\n");
1753
1754         mutex_unlock(&smu->mutex);
1755
1756         return ret;
1757 }
1758
1759 int smu_set_df_cstate(struct smu_context *smu,
1760                       enum pp_df_cstate state)
1761 {
1762         int ret = 0;
1763
1764         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1765                 return -EOPNOTSUPP;
1766
1767         if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate)
1768                 return 0;
1769
1770         mutex_lock(&smu->mutex);
1771
1772         ret = smu->ppt_funcs->set_df_cstate(smu, state);
1773         if (ret)
1774                 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n");
1775
1776         mutex_unlock(&smu->mutex);
1777
1778         return ret;
1779 }
1780
1781 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en)
1782 {
1783         int ret = 0;
1784
1785         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1786                 return -EOPNOTSUPP;
1787
1788         if (!smu->ppt_funcs || !smu->ppt_funcs->allow_xgmi_power_down)
1789                 return 0;
1790
1791         mutex_lock(&smu->mutex);
1792
1793         ret = smu->ppt_funcs->allow_xgmi_power_down(smu, en);
1794         if (ret)
1795                 dev_err(smu->adev->dev, "[AllowXgmiPowerDown] failed!\n");
1796
1797         mutex_unlock(&smu->mutex);
1798
1799         return ret;
1800 }
1801
1802 int smu_write_watermarks_table(struct smu_context *smu)
1803 {
1804         int ret = 0;
1805
1806         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1807                 return -EOPNOTSUPP;
1808
1809         mutex_lock(&smu->mutex);
1810
1811         ret = smu_set_watermarks_table(smu, NULL);
1812
1813         mutex_unlock(&smu->mutex);
1814
1815         return ret;
1816 }
1817
1818 int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
1819                 struct pp_smu_wm_range_sets *clock_ranges)
1820 {
1821         int ret = 0;
1822
1823         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1824                 return -EOPNOTSUPP;
1825
1826         mutex_lock(&smu->mutex);
1827
1828         if (!smu->disable_watermark &&
1829                         smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1830                         smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1831                 ret = smu_set_watermarks_table(smu, clock_ranges);
1832
1833                 if (!(smu->watermarks_bitmap & WATERMARKS_EXIST)) {
1834                         smu->watermarks_bitmap |= WATERMARKS_EXIST;
1835                         smu->watermarks_bitmap &= ~WATERMARKS_LOADED;
1836                 }
1837         }
1838
1839         mutex_unlock(&smu->mutex);
1840
1841         return ret;
1842 }
1843
1844 int smu_set_ac_dc(struct smu_context *smu)
1845 {
1846         int ret = 0;
1847
1848         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1849                 return -EOPNOTSUPP;
1850
1851         /* controlled by firmware */
1852         if (smu->dc_controlled_by_gpio)
1853                 return 0;
1854
1855         mutex_lock(&smu->mutex);
1856         ret = smu_set_power_source(smu,
1857                                    smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC :
1858                                    SMU_POWER_SOURCE_DC);
1859         if (ret)
1860                 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n",
1861                        smu->adev->pm.ac_power ? "AC" : "DC");
1862         mutex_unlock(&smu->mutex);
1863
1864         return ret;
1865 }
1866
1867 const struct amd_ip_funcs smu_ip_funcs = {
1868         .name = "smu",
1869         .early_init = smu_early_init,
1870         .late_init = smu_late_init,
1871         .sw_init = smu_sw_init,
1872         .sw_fini = smu_sw_fini,
1873         .hw_init = smu_hw_init,
1874         .hw_fini = smu_hw_fini,
1875         .suspend = smu_suspend,
1876         .resume = smu_resume,
1877         .is_idle = NULL,
1878         .check_soft_reset = NULL,
1879         .wait_for_idle = NULL,
1880         .soft_reset = NULL,
1881         .set_clockgating_state = smu_set_clockgating_state,
1882         .set_powergating_state = smu_set_powergating_state,
1883         .enable_umd_pstate = smu_enable_umd_pstate,
1884 };
1885
1886 const struct amdgpu_ip_block_version smu_v11_0_ip_block =
1887 {
1888         .type = AMD_IP_BLOCK_TYPE_SMC,
1889         .major = 11,
1890         .minor = 0,
1891         .rev = 0,
1892         .funcs = &smu_ip_funcs,
1893 };
1894
1895 const struct amdgpu_ip_block_version smu_v12_0_ip_block =
1896 {
1897         .type = AMD_IP_BLOCK_TYPE_SMC,
1898         .major = 12,
1899         .minor = 0,
1900         .rev = 0,
1901         .funcs = &smu_ip_funcs,
1902 };
1903
1904 int smu_load_microcode(struct smu_context *smu)
1905 {
1906         int ret = 0;
1907
1908         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1909                 return -EOPNOTSUPP;
1910
1911         mutex_lock(&smu->mutex);
1912
1913         if (smu->ppt_funcs->load_microcode)
1914                 ret = smu->ppt_funcs->load_microcode(smu);
1915
1916         mutex_unlock(&smu->mutex);
1917
1918         return ret;
1919 }
1920
1921 int smu_check_fw_status(struct smu_context *smu)
1922 {
1923         int ret = 0;
1924
1925         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1926                 return -EOPNOTSUPP;
1927
1928         mutex_lock(&smu->mutex);
1929
1930         if (smu->ppt_funcs->check_fw_status)
1931                 ret = smu->ppt_funcs->check_fw_status(smu);
1932
1933         mutex_unlock(&smu->mutex);
1934
1935         return ret;
1936 }
1937
1938 int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled)
1939 {
1940         int ret = 0;
1941
1942         mutex_lock(&smu->mutex);
1943
1944         if (smu->ppt_funcs->set_gfx_cgpg)
1945                 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled);
1946
1947         mutex_unlock(&smu->mutex);
1948
1949         return ret;
1950 }
1951
1952 int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed)
1953 {
1954         int ret = 0;
1955
1956         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1957                 return -EOPNOTSUPP;
1958
1959         mutex_lock(&smu->mutex);
1960
1961         if (smu->ppt_funcs->set_fan_speed_rpm)
1962                 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed);
1963
1964         mutex_unlock(&smu->mutex);
1965
1966         return ret;
1967 }
1968
1969 int smu_get_power_limit(struct smu_context *smu,
1970                         uint32_t *limit,
1971                         bool max_setting)
1972 {
1973         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1974                 return -EOPNOTSUPP;
1975
1976         mutex_lock(&smu->mutex);
1977
1978         *limit = (max_setting ? smu->max_power_limit : smu->current_power_limit);
1979
1980         mutex_unlock(&smu->mutex);
1981
1982         return 0;
1983 }
1984
1985 int smu_set_power_limit(struct smu_context *smu, uint32_t limit)
1986 {
1987         int ret = 0;
1988
1989         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1990                 return -EOPNOTSUPP;
1991
1992         mutex_lock(&smu->mutex);
1993
1994         if (limit > smu->max_power_limit) {
1995                 dev_err(smu->adev->dev,
1996                         "New power limit (%d) is over the max allowed %d\n",
1997                         limit, smu->max_power_limit);
1998                 goto out;
1999         }
2000
2001         if (!limit)
2002                 limit = smu->current_power_limit;
2003
2004         if (smu->ppt_funcs->set_power_limit)
2005                 ret = smu->ppt_funcs->set_power_limit(smu, limit);
2006
2007 out:
2008         mutex_unlock(&smu->mutex);
2009
2010         return ret;
2011 }
2012
2013 int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf)
2014 {
2015         int ret = 0;
2016
2017         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2018                 return -EOPNOTSUPP;
2019
2020         mutex_lock(&smu->mutex);
2021
2022         if (smu->ppt_funcs->print_clk_levels)
2023                 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf);
2024
2025         mutex_unlock(&smu->mutex);
2026
2027         return ret;
2028 }
2029
2030 int smu_get_od_percentage(struct smu_context *smu, enum smu_clk_type type)
2031 {
2032         int ret = 0;
2033
2034         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2035                 return -EOPNOTSUPP;
2036
2037         mutex_lock(&smu->mutex);
2038
2039         if (smu->ppt_funcs->get_od_percentage)
2040                 ret = smu->ppt_funcs->get_od_percentage(smu, type);
2041
2042         mutex_unlock(&smu->mutex);
2043
2044         return ret;
2045 }
2046
2047 int smu_set_od_percentage(struct smu_context *smu, enum smu_clk_type type, uint32_t value)
2048 {
2049         int ret = 0;
2050
2051         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2052                 return -EOPNOTSUPP;
2053
2054         mutex_lock(&smu->mutex);
2055
2056         if (smu->ppt_funcs->set_od_percentage)
2057                 ret = smu->ppt_funcs->set_od_percentage(smu, type, value);
2058
2059         mutex_unlock(&smu->mutex);
2060
2061         return ret;
2062 }
2063
2064 int smu_od_edit_dpm_table(struct smu_context *smu,
2065                           enum PP_OD_DPM_TABLE_COMMAND type,
2066                           long *input, uint32_t size)
2067 {
2068         int ret = 0;
2069
2070         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2071                 return -EOPNOTSUPP;
2072
2073         mutex_lock(&smu->mutex);
2074
2075         if (smu->ppt_funcs->od_edit_dpm_table) {
2076                 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size);
2077                 if (!ret && (type == PP_OD_COMMIT_DPM_TABLE))
2078                         ret = smu_handle_task(smu,
2079                                               smu->smu_dpm.dpm_level,
2080                                               AMD_PP_TASK_READJUST_POWER_STATE,
2081                                               false);
2082         }
2083
2084         mutex_unlock(&smu->mutex);
2085
2086         return ret;
2087 }
2088
2089 int smu_read_sensor(struct smu_context *smu,
2090                     enum amd_pp_sensors sensor,
2091                     void *data, uint32_t *size)
2092 {
2093         struct smu_umd_pstate_table *pstate_table =
2094                                 &smu->pstate_table;
2095         int ret = 0;
2096
2097         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2098                 return -EOPNOTSUPP;
2099
2100         if (!data || !size)
2101                 return -EINVAL;
2102
2103         mutex_lock(&smu->mutex);
2104
2105         if (smu->ppt_funcs->read_sensor)
2106                 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size))
2107                         goto unlock;
2108
2109         switch (sensor) {
2110         case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
2111                 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100;
2112                 *size = 4;
2113                 break;
2114         case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
2115                 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100;
2116                 *size = 4;
2117                 break;
2118         case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
2119                 ret = smu_feature_get_enabled_mask(smu, (uint32_t *)data, 2);
2120                 *size = 8;
2121                 break;
2122         case AMDGPU_PP_SENSOR_UVD_POWER:
2123                 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0;
2124                 *size = 4;
2125                 break;
2126         case AMDGPU_PP_SENSOR_VCE_POWER:
2127                 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0;
2128                 *size = 4;
2129                 break;
2130         case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
2131                 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0: 1;
2132                 *size = 4;
2133                 break;
2134         case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
2135                 *(uint32_t *)data = 0;
2136                 *size = 4;
2137                 break;
2138         default:
2139                 *size = 0;
2140                 ret = -EOPNOTSUPP;
2141                 break;
2142         }
2143
2144 unlock:
2145         mutex_unlock(&smu->mutex);
2146
2147         return ret;
2148 }
2149
2150 int smu_get_power_profile_mode(struct smu_context *smu, char *buf)
2151 {
2152         int ret = 0;
2153
2154         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2155                 return -EOPNOTSUPP;
2156
2157         mutex_lock(&smu->mutex);
2158
2159         if (smu->ppt_funcs->get_power_profile_mode)
2160                 ret = smu->ppt_funcs->get_power_profile_mode(smu, buf);
2161
2162         mutex_unlock(&smu->mutex);
2163
2164         return ret;
2165 }
2166
2167 int smu_set_power_profile_mode(struct smu_context *smu,
2168                                long *param,
2169                                uint32_t param_size,
2170                                bool lock_needed)
2171 {
2172         int ret = 0;
2173
2174         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2175                 return -EOPNOTSUPP;
2176
2177         if (lock_needed)
2178                 mutex_lock(&smu->mutex);
2179
2180         if (smu->ppt_funcs->set_power_profile_mode)
2181                 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size);
2182
2183         if (lock_needed)
2184                 mutex_unlock(&smu->mutex);
2185
2186         return ret;
2187 }
2188
2189
2190 int smu_get_fan_control_mode(struct smu_context *smu)
2191 {
2192         int ret = 0;
2193
2194         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2195                 return -EOPNOTSUPP;
2196
2197         mutex_lock(&smu->mutex);
2198
2199         if (smu->ppt_funcs->get_fan_control_mode)
2200                 ret = smu->ppt_funcs->get_fan_control_mode(smu);
2201
2202         mutex_unlock(&smu->mutex);
2203
2204         return ret;
2205 }
2206
2207 int smu_set_fan_control_mode(struct smu_context *smu, int value)
2208 {
2209         int ret = 0;
2210
2211         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2212                 return -EOPNOTSUPP;
2213
2214         mutex_lock(&smu->mutex);
2215
2216         if (smu->ppt_funcs->set_fan_control_mode)
2217                 ret = smu->ppt_funcs->set_fan_control_mode(smu, value);
2218
2219         mutex_unlock(&smu->mutex);
2220
2221         return ret;
2222 }
2223
2224 int smu_get_fan_speed_percent(struct smu_context *smu, uint32_t *speed)
2225 {
2226         int ret = 0;
2227         uint32_t percent;
2228         uint32_t current_rpm;
2229
2230         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2231                 return -EOPNOTSUPP;
2232
2233         mutex_lock(&smu->mutex);
2234
2235         if (smu->ppt_funcs->get_fan_speed_rpm) {
2236                 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, &current_rpm);
2237                 if (!ret) {
2238                         percent = current_rpm * 100 / smu->fan_max_rpm;
2239                         *speed = percent > 100 ? 100 : percent;
2240                 }
2241         }
2242
2243         mutex_unlock(&smu->mutex);
2244
2245
2246         return ret;
2247 }
2248
2249 int smu_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
2250 {
2251         int ret = 0;
2252         uint32_t rpm;
2253
2254         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2255                 return -EOPNOTSUPP;
2256
2257         mutex_lock(&smu->mutex);
2258
2259         if (smu->ppt_funcs->set_fan_speed_rpm) {
2260                 if (speed > 100)
2261                         speed = 100;
2262                 rpm = speed * smu->fan_max_rpm / 100;
2263                 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, rpm);
2264         }
2265
2266         mutex_unlock(&smu->mutex);
2267
2268         return ret;
2269 }
2270
2271 int smu_get_fan_speed_rpm(struct smu_context *smu, uint32_t *speed)
2272 {
2273         int ret = 0;
2274
2275         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2276                 return -EOPNOTSUPP;
2277
2278         mutex_lock(&smu->mutex);
2279
2280         if (smu->ppt_funcs->get_fan_speed_rpm)
2281                 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed);
2282
2283         mutex_unlock(&smu->mutex);
2284
2285         return ret;
2286 }
2287
2288 int smu_set_deep_sleep_dcefclk(struct smu_context *smu, int clk)
2289 {
2290         int ret = 0;
2291
2292         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2293                 return -EOPNOTSUPP;
2294
2295         mutex_lock(&smu->mutex);
2296
2297         ret = smu_set_min_dcef_deep_sleep(smu, clk);
2298
2299         mutex_unlock(&smu->mutex);
2300
2301         return ret;
2302 }
2303
2304 int smu_get_clock_by_type(struct smu_context *smu,
2305                           enum amd_pp_clock_type type,
2306                           struct amd_pp_clocks *clocks)
2307 {
2308         int ret = 0;
2309
2310         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2311                 return -EOPNOTSUPP;
2312
2313         mutex_lock(&smu->mutex);
2314
2315         if (smu->ppt_funcs->get_clock_by_type)
2316                 ret = smu->ppt_funcs->get_clock_by_type(smu, type, clocks);
2317
2318         mutex_unlock(&smu->mutex);
2319
2320         return ret;
2321 }
2322
2323 int smu_get_max_high_clocks(struct smu_context *smu,
2324                             struct amd_pp_simple_clock_info *clocks)
2325 {
2326         int ret = 0;
2327
2328         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2329                 return -EOPNOTSUPP;
2330
2331         mutex_lock(&smu->mutex);
2332
2333         if (smu->ppt_funcs->get_max_high_clocks)
2334                 ret = smu->ppt_funcs->get_max_high_clocks(smu, clocks);
2335
2336         mutex_unlock(&smu->mutex);
2337
2338         return ret;
2339 }
2340
2341 int smu_get_clock_by_type_with_latency(struct smu_context *smu,
2342                                        enum smu_clk_type clk_type,
2343                                        struct pp_clock_levels_with_latency *clocks)
2344 {
2345         int ret = 0;
2346
2347         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2348                 return -EOPNOTSUPP;
2349
2350         mutex_lock(&smu->mutex);
2351
2352         if (smu->ppt_funcs->get_clock_by_type_with_latency)
2353                 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks);
2354
2355         mutex_unlock(&smu->mutex);
2356
2357         return ret;
2358 }
2359
2360 int smu_get_clock_by_type_with_voltage(struct smu_context *smu,
2361                                        enum amd_pp_clock_type type,
2362                                        struct pp_clock_levels_with_voltage *clocks)
2363 {
2364         int ret = 0;
2365
2366         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2367                 return -EOPNOTSUPP;
2368
2369         mutex_lock(&smu->mutex);
2370
2371         if (smu->ppt_funcs->get_clock_by_type_with_voltage)
2372                 ret = smu->ppt_funcs->get_clock_by_type_with_voltage(smu, type, clocks);
2373
2374         mutex_unlock(&smu->mutex);
2375
2376         return ret;
2377 }
2378
2379
2380 int smu_display_clock_voltage_request(struct smu_context *smu,
2381                                       struct pp_display_clock_request *clock_req)
2382 {
2383         int ret = 0;
2384
2385         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2386                 return -EOPNOTSUPP;
2387
2388         mutex_lock(&smu->mutex);
2389
2390         if (smu->ppt_funcs->display_clock_voltage_request)
2391                 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req);
2392
2393         mutex_unlock(&smu->mutex);
2394
2395         return ret;
2396 }
2397
2398
2399 int smu_display_disable_memory_clock_switch(struct smu_context *smu, bool disable_memory_clock_switch)
2400 {
2401         int ret = -EINVAL;
2402
2403         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2404                 return -EOPNOTSUPP;
2405
2406         mutex_lock(&smu->mutex);
2407
2408         if (smu->ppt_funcs->display_disable_memory_clock_switch)
2409                 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch);
2410
2411         mutex_unlock(&smu->mutex);
2412
2413         return ret;
2414 }
2415
2416 int smu_notify_smu_enable_pwe(struct smu_context *smu)
2417 {
2418         int ret = 0;
2419
2420         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2421                 return -EOPNOTSUPP;
2422
2423         mutex_lock(&smu->mutex);
2424
2425         if (smu->ppt_funcs->notify_smu_enable_pwe)
2426                 ret = smu->ppt_funcs->notify_smu_enable_pwe(smu);
2427
2428         mutex_unlock(&smu->mutex);
2429
2430         return ret;
2431 }
2432
2433 int smu_set_xgmi_pstate(struct smu_context *smu,
2434                         uint32_t pstate)
2435 {
2436         int ret = 0;
2437
2438         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2439                 return -EOPNOTSUPP;
2440
2441         mutex_lock(&smu->mutex);
2442
2443         if (smu->ppt_funcs->set_xgmi_pstate)
2444                 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate);
2445
2446         mutex_unlock(&smu->mutex);
2447
2448         if(ret)
2449                 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n");
2450
2451         return ret;
2452 }
2453
2454 int smu_set_azalia_d3_pme(struct smu_context *smu)
2455 {
2456         int ret = 0;
2457
2458         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2459                 return -EOPNOTSUPP;
2460
2461         mutex_lock(&smu->mutex);
2462
2463         if (smu->ppt_funcs->set_azalia_d3_pme)
2464                 ret = smu->ppt_funcs->set_azalia_d3_pme(smu);
2465
2466         mutex_unlock(&smu->mutex);
2467
2468         return ret;
2469 }
2470
2471 /*
2472  * On system suspending or resetting, the dpm_enabled
2473  * flag will be cleared. So that those SMU services which
2474  * are not supported will be gated.
2475  *
2476  * However, the baco/mode1 reset should still be granted
2477  * as they are still supported and necessary.
2478  */
2479 bool smu_baco_is_support(struct smu_context *smu)
2480 {
2481         bool ret = false;
2482
2483         if (!smu->pm_enabled)
2484                 return false;
2485
2486         mutex_lock(&smu->mutex);
2487
2488         if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support)
2489                 ret = smu->ppt_funcs->baco_is_support(smu);
2490
2491         mutex_unlock(&smu->mutex);
2492
2493         return ret;
2494 }
2495
2496 int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state)
2497 {
2498         if (smu->ppt_funcs->baco_get_state)
2499                 return -EINVAL;
2500
2501         mutex_lock(&smu->mutex);
2502         *state = smu->ppt_funcs->baco_get_state(smu);
2503         mutex_unlock(&smu->mutex);
2504
2505         return 0;
2506 }
2507
2508 int smu_baco_enter(struct smu_context *smu)
2509 {
2510         int ret = 0;
2511
2512         if (!smu->pm_enabled)
2513                 return -EOPNOTSUPP;
2514
2515         mutex_lock(&smu->mutex);
2516
2517         if (smu->ppt_funcs->baco_enter)
2518                 ret = smu->ppt_funcs->baco_enter(smu);
2519
2520         mutex_unlock(&smu->mutex);
2521
2522         if (ret)
2523                 dev_err(smu->adev->dev, "Failed to enter BACO state!\n");
2524
2525         return ret;
2526 }
2527
2528 int smu_baco_exit(struct smu_context *smu)
2529 {
2530         int ret = 0;
2531
2532         if (!smu->pm_enabled)
2533                 return -EOPNOTSUPP;
2534
2535         mutex_lock(&smu->mutex);
2536
2537         if (smu->ppt_funcs->baco_exit)
2538                 ret = smu->ppt_funcs->baco_exit(smu);
2539
2540         mutex_unlock(&smu->mutex);
2541
2542         if (ret)
2543                 dev_err(smu->adev->dev, "Failed to exit BACO state!\n");
2544
2545         return ret;
2546 }
2547
2548 bool smu_mode1_reset_is_support(struct smu_context *smu)
2549 {
2550         bool ret = false;
2551
2552         if (!smu->pm_enabled)
2553                 return false;
2554
2555         mutex_lock(&smu->mutex);
2556
2557         if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support)
2558                 ret = smu->ppt_funcs->mode1_reset_is_support(smu);
2559
2560         mutex_unlock(&smu->mutex);
2561
2562         return ret;
2563 }
2564
2565 int smu_mode1_reset(struct smu_context *smu)
2566 {
2567         int ret = 0;
2568
2569         if (!smu->pm_enabled)
2570                 return -EOPNOTSUPP;
2571
2572         mutex_lock(&smu->mutex);
2573
2574         if (smu->ppt_funcs->mode1_reset)
2575                 ret = smu->ppt_funcs->mode1_reset(smu);
2576
2577         mutex_unlock(&smu->mutex);
2578
2579         return ret;
2580 }
2581
2582 int smu_mode2_reset(struct smu_context *smu)
2583 {
2584         int ret = 0;
2585
2586         if (!smu->pm_enabled)
2587                 return -EOPNOTSUPP;
2588
2589         mutex_lock(&smu->mutex);
2590
2591         if (smu->ppt_funcs->mode2_reset)
2592                 ret = smu->ppt_funcs->mode2_reset(smu);
2593
2594         mutex_unlock(&smu->mutex);
2595
2596         if (ret)
2597                 dev_err(smu->adev->dev, "Mode2 reset failed!\n");
2598
2599         return ret;
2600 }
2601
2602 int smu_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
2603                                          struct pp_smu_nv_clock_table *max_clocks)
2604 {
2605         int ret = 0;
2606
2607         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2608                 return -EOPNOTSUPP;
2609
2610         mutex_lock(&smu->mutex);
2611
2612         if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc)
2613                 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks);
2614
2615         mutex_unlock(&smu->mutex);
2616
2617         return ret;
2618 }
2619
2620 int smu_get_uclk_dpm_states(struct smu_context *smu,
2621                             unsigned int *clock_values_in_khz,
2622                             unsigned int *num_states)
2623 {
2624         int ret = 0;
2625
2626         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2627                 return -EOPNOTSUPP;
2628
2629         mutex_lock(&smu->mutex);
2630
2631         if (smu->ppt_funcs->get_uclk_dpm_states)
2632                 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states);
2633
2634         mutex_unlock(&smu->mutex);
2635
2636         return ret;
2637 }
2638
2639 enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu)
2640 {
2641         enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT;
2642
2643         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2644                 return -EOPNOTSUPP;
2645
2646         mutex_lock(&smu->mutex);
2647
2648         if (smu->ppt_funcs->get_current_power_state)
2649                 pm_state = smu->ppt_funcs->get_current_power_state(smu);
2650
2651         mutex_unlock(&smu->mutex);
2652
2653         return pm_state;
2654 }
2655
2656 int smu_get_dpm_clock_table(struct smu_context *smu,
2657                             struct dpm_clocks *clock_table)
2658 {
2659         int ret = 0;
2660
2661         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2662                 return -EOPNOTSUPP;
2663
2664         mutex_lock(&smu->mutex);
2665
2666         if (smu->ppt_funcs->get_dpm_clock_table)
2667                 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table);
2668
2669         mutex_unlock(&smu->mutex);
2670
2671         return ret;
2672 }
2673
2674 ssize_t smu_sys_get_gpu_metrics(struct smu_context *smu,
2675                                 void **table)
2676 {
2677         ssize_t size;
2678
2679         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2680                 return -EOPNOTSUPP;
2681
2682         if (!smu->ppt_funcs->get_gpu_metrics)
2683                 return -EOPNOTSUPP;
2684
2685         mutex_lock(&smu->mutex);
2686
2687         size = smu->ppt_funcs->get_gpu_metrics(smu, table);
2688
2689         mutex_unlock(&smu->mutex);
2690
2691         return size;
2692 }
2693
2694 int smu_enable_mgpu_fan_boost(struct smu_context *smu)
2695 {
2696         int ret = 0;
2697
2698         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2699                 return -EOPNOTSUPP;
2700
2701         mutex_lock(&smu->mutex);
2702
2703         if (smu->ppt_funcs->enable_mgpu_fan_boost)
2704                 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu);
2705
2706         mutex_unlock(&smu->mutex);
2707
2708         return ret;
2709 }