drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #define SWSMU_CODE_LAYER_L1
  24
  25 #include <linux/firmware.h>
  26 #include <linux/pci.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_smu.h"
  30 #include "smu_internal.h"
  31 #include "atom.h"
  32 #include "arcturus_ppt.h"
  33 #include "navi10_ppt.h"
  34 #include "sienna_cichlid_ppt.h"
  35 #include "renoir_ppt.h"
  36 #include "amd_pcie.h"
  37
  38 /*
  39  * DO NOT use these for err/warn/info/debug messages.
  40  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  41  * They are more MGPU friendly.
  42  */
  43 #undef pr_err
  44 #undef pr_warn
  45 #undef pr_info
  46 #undef pr_debug
  47
  48 size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
  49 {
  50         size_t size = 0;
  51
  52         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
  53                 return -EOPNOTSUPP;
  54
  55         mutex_lock(&smu->mutex);
  56
  57         size = smu_get_pp_feature_mask(smu, buf);
  58
  59         mutex_unlock(&smu->mutex);
  60
  61         return size;
  62 }
  63
  64 int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask)
  65 {
  66         int ret = 0;
  67
  68         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
  69                 return -EOPNOTSUPP;
  70
  71         mutex_lock(&smu->mutex);
  72
  73         ret = smu_set_pp_feature_mask(smu, new_mask);
  74
  75         mutex_unlock(&smu->mutex);
  76
  77         return ret;
  78 }
  79
  80 int smu_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value)
  81 {
  82         int ret = 0;
  83         struct smu_context *smu = &adev->smu;
  84
  85         if (is_support_sw_smu(adev) && smu->ppt_funcs->get_gfx_off_status)
  86                 *value = smu_get_gfx_off_status(smu);
  87         else
  88                 ret = -EINVAL;
  89
  90         return ret;
  91 }
  92
  93 int smu_set_soft_freq_range(struct smu_context *smu,
  94                             enum smu_clk_type clk_type,
  95                             uint32_t min,
  96                             uint32_t max)
  97 {
  98         int ret = 0;
  99
 100         mutex_lock(&smu->mutex);
 101
 102         if (smu->ppt_funcs->set_soft_freq_limited_range)
 103                 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu,
 104                                                                   clk_type,
 105                                                                   min,
 106                                                                   max);
 107
 108         mutex_unlock(&smu->mutex);
 109
 110         return ret;
 111 }
 112
 113 int smu_get_dpm_freq_range(struct smu_context *smu,
 114                            enum smu_clk_type clk_type,
 115                            uint32_t *min,
 116                            uint32_t *max)
 117 {
 118         int ret = 0;
 119
 120         if (!min && !max)
 121                 return -EINVAL;
 122
 123         mutex_lock(&smu->mutex);
 124
 125         if (smu->ppt_funcs->get_dpm_ultimate_freq)
 126                 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu,
 127                                                             clk_type,
 128                                                             min,
 129                                                             max);
 130
 131         mutex_unlock(&smu->mutex);
 132
 133         return ret;
 134 }
 135
 136 static int smu_dpm_set_vcn_enable_locked(struct smu_context *smu,
 137                                          bool enable)
 138 {
 139         struct smu_power_context *smu_power = &smu->smu_power;
 140         struct smu_power_gate *power_gate = &smu_power->power_gate;
 141         int ret = 0;
 142
 143         if (!smu->ppt_funcs->dpm_set_vcn_enable)
 144                 return 0;
 145
 146         if (atomic_read(&power_gate->vcn_gated) ^ enable)
 147                 return 0;
 148
 149         ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable);
 150         if (!ret)
 151                 atomic_set(&power_gate->vcn_gated, !enable);
 152
 153         return ret;
 154 }
 155
 156 static int smu_dpm_set_vcn_enable(struct smu_context *smu,
 157                                   bool enable)
 158 {
 159         struct smu_power_context *smu_power = &smu->smu_power;
 160         struct smu_power_gate *power_gate = &smu_power->power_gate;
 161         int ret = 0;
 162
 163         mutex_lock(&power_gate->vcn_gate_lock);
 164
 165         ret = smu_dpm_set_vcn_enable_locked(smu, enable);
 166
 167         mutex_unlock(&power_gate->vcn_gate_lock);
 168
 169         return ret;
 170 }
 171
 172 static int smu_dpm_set_jpeg_enable_locked(struct smu_context *smu,
 173                                           bool enable)
 174 {
 175         struct smu_power_context *smu_power = &smu->smu_power;
 176         struct smu_power_gate *power_gate = &smu_power->power_gate;
 177         int ret = 0;
 178
 179         if (!smu->ppt_funcs->dpm_set_jpeg_enable)
 180                 return 0;
 181
 182         if (atomic_read(&power_gate->jpeg_gated) ^ enable)
 183                 return 0;
 184
 185         ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable);
 186         if (!ret)
 187                 atomic_set(&power_gate->jpeg_gated, !enable);
 188
 189         return ret;
 190 }
 191
 192 static int smu_dpm_set_jpeg_enable(struct smu_context *smu,
 193                                    bool enable)
 194 {
 195         struct smu_power_context *smu_power = &smu->smu_power;
 196         struct smu_power_gate *power_gate = &smu_power->power_gate;
 197         int ret = 0;
 198
 199         mutex_lock(&power_gate->jpeg_gate_lock);
 200
 201         ret = smu_dpm_set_jpeg_enable_locked(smu, enable);
 202
 203         mutex_unlock(&power_gate->jpeg_gate_lock);
 204
 205         return ret;
 206 }
 207
 208 /**
 209  * smu_dpm_set_power_gate - power gate/ungate the specific IP block
 210  *
 211  * @smu:        smu_context pointer
 212  * @block_type: the IP block to power gate/ungate
 213  * @gate:       to power gate if true, ungate otherwise
 214  *
 215  * This API uses no smu->mutex lock protection due to:
 216  * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce).
 217  *    This is guarded to be race condition free by the caller.
 218  * 2. Or get called on user setting request of power_dpm_force_performance_level.
 219  *    Under this case, the smu->mutex lock protection is already enforced on
 220  *    the parent API smu_force_performance_level of the call path.
 221  */
 222 int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
 223                            bool gate)
 224 {
 225         int ret = 0;
 226
 227         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
 228                 return -EOPNOTSUPP;
 229
 230         switch (block_type) {
 231         /*
 232          * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses
 233          * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept.
 234          */
 235         case AMD_IP_BLOCK_TYPE_UVD:
 236         case AMD_IP_BLOCK_TYPE_VCN:
 237                 ret = smu_dpm_set_vcn_enable(smu, !gate);
 238                 if (ret)
 239                         dev_err(smu->adev->dev, "Failed to power %s VCN!\n",
 240                                 gate ? "gate" : "ungate");
 241                 break;
 242         case AMD_IP_BLOCK_TYPE_GFX:
 243                 ret = smu_gfx_off_control(smu, gate);
 244                 if (ret)
 245                         dev_err(smu->adev->dev, "Failed to %s gfxoff!\n",
 246                                 gate ? "enable" : "disable");
 247                 break;
 248         case AMD_IP_BLOCK_TYPE_SDMA:
 249                 ret = smu_powergate_sdma(smu, gate);
 250                 if (ret)
 251                         dev_err(smu->adev->dev, "Failed to power %s SDMA!\n",
 252                                 gate ? "gate" : "ungate");
 253                 break;
 254         case AMD_IP_BLOCK_TYPE_JPEG:
 255                 ret = smu_dpm_set_jpeg_enable(smu, !gate);
 256                 if (ret)
 257                         dev_err(smu->adev->dev, "Failed to power %s JPEG!\n",
 258                                 gate ? "gate" : "ungate");
 259                 break;
 260         default:
 261                 dev_err(smu->adev->dev, "Unsupported block type!\n");
 262                 return -EINVAL;
 263         }
 264
 265         return ret;
 266 }
 267
 268 int smu_get_power_num_states(struct smu_context *smu,
 269                              struct pp_states_info *state_info)
 270 {
 271         if (!state_info)
 272                 return -EINVAL;
 273
 274         /* not support power state */
 275         memset(state_info, 0, sizeof(struct pp_states_info));
 276         state_info->nums = 1;
 277         state_info->states[0] = POWER_STATE_TYPE_DEFAULT;
 278
 279         return 0;
 280 }
 281
 282 bool is_support_sw_smu(struct amdgpu_device *adev)
 283 {
 284         if (adev->asic_type >= CHIP_ARCTURUS)
 285                 return true;
 286
 287         return false;
 288 }
 289
 290 int smu_sys_get_pp_table(struct smu_context *smu, void **table)
 291 {
 292         struct smu_table_context *smu_table = &smu->smu_table;
 293         uint32_t powerplay_table_size;
 294
 295         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
 296                 return -EOPNOTSUPP;
 297
 298         if (!smu_table->power_play_table && !smu_table->hardcode_pptable)
 299                 return -EINVAL;
 300
 301         mutex_lock(&smu->mutex);
 302
 303         if (smu_table->hardcode_pptable)
 304                 *table = smu_table->hardcode_pptable;
 305         else
 306                 *table = smu_table->power_play_table;
 307
 308         powerplay_table_size = smu_table->power_play_table_size;
 309
 310         mutex_unlock(&smu->mutex);
 311
 312         return powerplay_table_size;
 313 }
 314
 315 int smu_sys_set_pp_table(struct smu_context *smu,  void *buf, size_t size)
 316 {
 317         struct smu_table_context *smu_table = &smu->smu_table;
 318         ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf;
 319         int ret = 0;
 320
 321         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
 322                 return -EOPNOTSUPP;
 323
 324         if (header->usStructureSize != size) {
 325                 dev_err(smu->adev->dev, "pp table size not matched !\n");
 326                 return -EIO;
 327         }
 328
 329         mutex_lock(&smu->mutex);
 330         if (!smu_table->hardcode_pptable)
 331                 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL);
 332         if (!smu_table->hardcode_pptable) {
 333                 ret = -ENOMEM;
 334                 goto failed;
 335         }
 336
 337         memcpy(smu_table->hardcode_pptable, buf, size);
 338         smu_table->power_play_table = smu_table->hardcode_pptable;
 339         smu_table->power_play_table_size = size;
 340
 341         /*
 342          * Special hw_fini action(for Navi1x, the DPMs disablement will be
 343          * skipped) may be needed for custom pptable uploading.
 344          */
 345         smu->uploading_custom_pp_table = true;
 346
 347         ret = smu_reset(smu);
 348         if (ret)
 349                 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret);
 350
 351         smu->uploading_custom_pp_table = false;
 352
 353 failed:
 354         mutex_unlock(&smu->mutex);
 355         return ret;
 356 }
 357
 358 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu)
 359 {
 360         struct smu_feature *feature = &smu->smu_feature;
 361         int ret = 0;
 362         uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32];
 363
 364         bitmap_zero(feature->allowed, SMU_FEATURE_MAX);
 365
 366         ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask,
 367                                              SMU_FEATURE_MAX/32);
 368         if (ret)
 369                 return ret;
 370
 371         bitmap_or(feature->allowed, feature->allowed,
 372                       (unsigned long *)allowed_feature_mask,
 373                       feature->feature_num);
 374
 375         return ret;
 376 }
 377
 378 static int smu_set_funcs(struct amdgpu_device *adev)
 379 {
 380         struct smu_context *smu = &adev->smu;
 381
 382         if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
 383                 smu->od_enabled = true;
 384
 385         switch (adev->asic_type) {
 386         case CHIP_NAVI10:
 387         case CHIP_NAVI14:
 388         case CHIP_NAVI12:
 389                 navi10_set_ppt_funcs(smu);
 390                 break;
 391         case CHIP_ARCTURUS:
 392                 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
 393                 arcturus_set_ppt_funcs(smu);
 394                 /* OD is not supported on Arcturus */
 395                 smu->od_enabled =false;
 396                 break;
 397         case CHIP_SIENNA_CICHLID:
 398         case CHIP_NAVY_FLOUNDER:
 399                 sienna_cichlid_set_ppt_funcs(smu);
 400                 break;
 401         case CHIP_RENOIR:
 402                 renoir_set_ppt_funcs(smu);
 403                 break;
 404         default:
 405                 return -EINVAL;
 406         }
 407
 408         return 0;
 409 }
 410
 411 static int smu_early_init(void *handle)
 412 {
 413         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 414         struct smu_context *smu = &adev->smu;
 415
 416         smu->adev = adev;
 417         smu->pm_enabled = !!amdgpu_dpm;
 418         smu->is_apu = false;
 419         mutex_init(&smu->mutex);
 420
 421         return smu_set_funcs(adev);
 422 }
 423
 424 static int smu_set_default_dpm_table(struct smu_context *smu)
 425 {
 426         struct smu_power_context *smu_power = &smu->smu_power;
 427         struct smu_power_gate *power_gate = &smu_power->power_gate;
 428         int vcn_gate, jpeg_gate;
 429         int ret = 0;
 430
 431         if (!smu->ppt_funcs->set_default_dpm_table)
 432                 return 0;
 433
 434         mutex_lock(&power_gate->vcn_gate_lock);
 435         mutex_lock(&power_gate->jpeg_gate_lock);
 436
 437         vcn_gate = atomic_read(&power_gate->vcn_gated);
 438         jpeg_gate = atomic_read(&power_gate->jpeg_gated);
 439
 440         ret = smu_dpm_set_vcn_enable_locked(smu, true);
 441         if (ret)
 442                 goto err0_out;
 443
 444         ret = smu_dpm_set_jpeg_enable_locked(smu, true);
 445         if (ret)
 446                 goto err1_out;
 447
 448         ret = smu->ppt_funcs->set_default_dpm_table(smu);
 449         if (ret)
 450                 dev_err(smu->adev->dev,
 451                         "Failed to setup default dpm clock tables!\n");
 452
 453         smu_dpm_set_jpeg_enable_locked(smu, !jpeg_gate);
 454 err1_out:
 455         smu_dpm_set_vcn_enable_locked(smu, !vcn_gate);
 456 err0_out:
 457         mutex_unlock(&power_gate->jpeg_gate_lock);
 458         mutex_unlock(&power_gate->vcn_gate_lock);
 459
 460         return ret;
 461 }
 462
 463 static int smu_late_init(void *handle)
 464 {
 465         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 466         struct smu_context *smu = &adev->smu;
 467         int ret = 0;
 468
 469         if (!smu->pm_enabled)
 470                 return 0;
 471
 472         ret = smu_post_init(smu);
 473         if (ret) {
 474                 dev_err(adev->dev, "Failed to post smu init!\n");
 475                 return ret;
 476         }
 477
 478         ret = smu_set_default_od_settings(smu);
 479         if (ret) {
 480                 dev_err(adev->dev, "Failed to setup default OD settings!\n");
 481                 return ret;
 482         }
 483
 484         /*
 485          * Set initialized values (get from vbios) to dpm tables context such as
 486          * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each
 487          * type of clks.
 488          */
 489         ret = smu_set_default_dpm_table(smu);
 490         if (ret) {
 491                 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n");
 492                 return ret;
 493         }
 494
 495         ret = smu_populate_umd_state_clk(smu);
 496         if (ret) {
 497                 dev_err(adev->dev, "Failed to populate UMD state clocks!\n");
 498                 return ret;
 499         }
 500
 501         ret = smu_get_asic_power_limits(smu);
 502         if (ret) {
 503                 dev_err(adev->dev, "Failed to get asic power limits!\n");
 504                 return ret;
 505         }
 506
 507         smu_get_unique_id(smu);
 508
 509         smu_get_fan_parameters(smu);
 510
 511         smu_handle_task(&adev->smu,
 512                         smu->smu_dpm.dpm_level,
 513                         AMD_PP_TASK_COMPLETE_INIT,
 514                         false);
 515
 516         return 0;
 517 }
 518
 519 static int smu_init_fb_allocations(struct smu_context *smu)
 520 {
 521         struct amdgpu_device *adev = smu->adev;
 522         struct smu_table_context *smu_table = &smu->smu_table;
 523         struct smu_table *tables = smu_table->tables;
 524         struct smu_table *driver_table = &(smu_table->driver_table);
 525         uint32_t max_table_size = 0;
 526         int ret, i;
 527
 528         /* VRAM allocation for tool table */
 529         if (tables[SMU_TABLE_PMSTATUSLOG].size) {
 530                 ret = amdgpu_bo_create_kernel(adev,
 531                                               tables[SMU_TABLE_PMSTATUSLOG].size,
 532                                               tables[SMU_TABLE_PMSTATUSLOG].align,
 533                                               tables[SMU_TABLE_PMSTATUSLOG].domain,
 534                                               &tables[SMU_TABLE_PMSTATUSLOG].bo,
 535                                               &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
 536                                               &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
 537                 if (ret) {
 538                         dev_err(adev->dev, "VRAM allocation for tool table failed!\n");
 539                         return ret;
 540                 }
 541         }
 542
 543         /* VRAM allocation for driver table */
 544         for (i = 0; i < SMU_TABLE_COUNT; i++) {
 545                 if (tables[i].size == 0)
 546                         continue;
 547
 548                 if (i == SMU_TABLE_PMSTATUSLOG)
 549                         continue;
 550
 551                 if (max_table_size < tables[i].size)
 552                         max_table_size = tables[i].size;
 553         }
 554
 555         driver_table->size = max_table_size;
 556         driver_table->align = PAGE_SIZE;
 557         driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM;
 558
 559         ret = amdgpu_bo_create_kernel(adev,
 560                                       driver_table->size,
 561                                       driver_table->align,
 562                                       driver_table->domain,
 563                                       &driver_table->bo,
 564                                       &driver_table->mc_address,
 565                                       &driver_table->cpu_addr);
 566         if (ret) {
 567                 dev_err(adev->dev, "VRAM allocation for driver table failed!\n");
 568                 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
 569                         amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
 570                                               &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
 571                                               &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
 572         }
 573
 574         return ret;
 575 }
 576
 577 static int smu_fini_fb_allocations(struct smu_context *smu)
 578 {
 579         struct smu_table_context *smu_table = &smu->smu_table;
 580         struct smu_table *tables = smu_table->tables;
 581         struct smu_table *driver_table = &(smu_table->driver_table);
 582
 583         if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
 584                 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
 585                                       &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
 586                                       &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
 587
 588         amdgpu_bo_free_kernel(&driver_table->bo,
 589                               &driver_table->mc_address,
 590                               &driver_table->cpu_addr);
 591
 592         return 0;
 593 }
 594
 595 /**
 596  * smu_alloc_memory_pool - allocate memory pool in the system memory
 597  *
 598  * @smu: amdgpu_device pointer
 599  *
 600  * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr
 601  * and DramLogSetDramAddr can notify it changed.
 602  *
 603  * Returns 0 on success, error on failure.
 604  */
 605 static int smu_alloc_memory_pool(struct smu_context *smu)
 606 {
 607         struct amdgpu_device *adev = smu->adev;
 608         struct smu_table_context *smu_table = &smu->smu_table;
 609         struct smu_table *memory_pool = &smu_table->memory_pool;
 610         uint64_t pool_size = smu->pool_size;
 611         int ret = 0;
 612
 613         if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO)
 614                 return ret;
 615
 616         memory_pool->size = pool_size;
 617         memory_pool->align = PAGE_SIZE;
 618         memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT;
 619
 620         switch (pool_size) {
 621         case SMU_MEMORY_POOL_SIZE_256_MB:
 622         case SMU_MEMORY_POOL_SIZE_512_MB:
 623         case SMU_MEMORY_POOL_SIZE_1_GB:
 624         case SMU_MEMORY_POOL_SIZE_2_GB:
 625                 ret = amdgpu_bo_create_kernel(adev,
 626                                               memory_pool->size,
 627                                               memory_pool->align,
 628                                               memory_pool->domain,
 629                                               &memory_pool->bo,
 630                                               &memory_pool->mc_address,
 631                                               &memory_pool->cpu_addr);
 632                 if (ret)
 633                         dev_err(adev->dev, "VRAM allocation for dramlog failed!\n");
 634                 break;
 635         default:
 636                 break;
 637         }
 638
 639         return ret;
 640 }
 641
 642 static int smu_free_memory_pool(struct smu_context *smu)
 643 {
 644         struct smu_table_context *smu_table = &smu->smu_table;
 645         struct smu_table *memory_pool = &smu_table->memory_pool;
 646
 647         if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO)
 648                 return 0;
 649
 650         amdgpu_bo_free_kernel(&memory_pool->bo,
 651                               &memory_pool->mc_address,
 652                               &memory_pool->cpu_addr);
 653
 654         memset(memory_pool, 0, sizeof(struct smu_table));
 655
 656         return 0;
 657 }
 658
 659 static int smu_alloc_dummy_read_table(struct smu_context *smu)
 660 {
 661         struct smu_table_context *smu_table = &smu->smu_table;
 662         struct smu_table *dummy_read_1_table =
 663                         &smu_table->dummy_read_1_table;
 664         struct amdgpu_device *adev = smu->adev;
 665         int ret = 0;
 666
 667         dummy_read_1_table->size = 0x40000;
 668         dummy_read_1_table->align = PAGE_SIZE;
 669         dummy_read_1_table->domain = AMDGPU_GEM_DOMAIN_VRAM;
 670
 671         ret = amdgpu_bo_create_kernel(adev,
 672                                       dummy_read_1_table->size,
 673                                       dummy_read_1_table->align,
 674                                       dummy_read_1_table->domain,
 675                                       &dummy_read_1_table->bo,
 676                                       &dummy_read_1_table->mc_address,
 677                                       &dummy_read_1_table->cpu_addr);
 678         if (ret)
 679                 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n");
 680
 681         return ret;
 682 }
 683
 684 static void smu_free_dummy_read_table(struct smu_context *smu)
 685 {
 686         struct smu_table_context *smu_table = &smu->smu_table;
 687         struct smu_table *dummy_read_1_table =
 688                         &smu_table->dummy_read_1_table;
 689
 690
 691         amdgpu_bo_free_kernel(&dummy_read_1_table->bo,
 692                               &dummy_read_1_table->mc_address,
 693                               &dummy_read_1_table->cpu_addr);
 694
 695         memset(dummy_read_1_table, 0, sizeof(struct smu_table));
 696 }
 697
 698 static int smu_smc_table_sw_init(struct smu_context *smu)
 699 {
 700         int ret;
 701
 702         /**
 703          * Create smu_table structure, and init smc tables such as
 704          * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc.
 705          */
 706         ret = smu_init_smc_tables(smu);
 707         if (ret) {
 708                 dev_err(smu->adev->dev, "Failed to init smc tables!\n");
 709                 return ret;
 710         }
 711
 712         /**
 713          * Create smu_power_context structure, and allocate smu_dpm_context and
 714          * context size to fill the smu_power_context data.
 715          */
 716         ret = smu_init_power(smu);
 717         if (ret) {
 718                 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n");
 719                 return ret;
 720         }
 721
 722         /*
 723          * allocate vram bos to store smc table contents.
 724          */
 725         ret = smu_init_fb_allocations(smu);
 726         if (ret)
 727                 return ret;
 728
 729         ret = smu_alloc_memory_pool(smu);
 730         if (ret)
 731                 return ret;
 732
 733         ret = smu_alloc_dummy_read_table(smu);
 734         if (ret)
 735                 return ret;
 736
 737         ret = smu_i2c_init(smu, &smu->adev->pm.smu_i2c);
 738         if (ret)
 739                 return ret;
 740
 741         return 0;
 742 }
 743
 744 static int smu_smc_table_sw_fini(struct smu_context *smu)
 745 {
 746         int ret;
 747
 748         smu_i2c_fini(smu, &smu->adev->pm.smu_i2c);
 749
 750         smu_free_dummy_read_table(smu);
 751
 752         ret = smu_free_memory_pool(smu);
 753         if (ret)
 754                 return ret;
 755
 756         ret = smu_fini_fb_allocations(smu);
 757         if (ret)
 758                 return ret;
 759
 760         ret = smu_fini_power(smu);
 761         if (ret) {
 762                 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n");
 763                 return ret;
 764         }
 765
 766         ret = smu_fini_smc_tables(smu);
 767         if (ret) {
 768                 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n");
 769                 return ret;
 770         }
 771
 772         return 0;
 773 }
 774
 775 static void smu_throttling_logging_work_fn(struct work_struct *work)
 776 {
 777         struct smu_context *smu = container_of(work, struct smu_context,
 778                                                throttling_logging_work);
 779
 780         smu_log_thermal_throttling(smu);
 781 }
 782
 783 static int smu_sw_init(void *handle)
 784 {
 785         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 786         struct smu_context *smu = &adev->smu;
 787         int ret;
 788
 789         smu->pool_size = adev->pm.smu_prv_buffer_size;
 790         smu->smu_feature.feature_num = SMU_FEATURE_MAX;
 791         mutex_init(&smu->smu_feature.mutex);
 792         bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX);
 793         bitmap_zero(smu->smu_feature.enabled, SMU_FEATURE_MAX);
 794         bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX);
 795
 796         mutex_init(&smu->smu_baco.mutex);
 797         smu->smu_baco.state = SMU_BACO_STATE_EXIT;
 798         smu->smu_baco.platform_support = false;
 799
 800         mutex_init(&smu->sensor_lock);
 801         mutex_init(&smu->metrics_lock);
 802         mutex_init(&smu->message_lock);
 803
 804         INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn);
 805         atomic64_set(&smu->throttle_int_counter, 0);
 806         smu->watermarks_bitmap = 0;
 807         smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 808         smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 809
 810         atomic_set(&smu->smu_power.power_gate.vcn_gated, 1);
 811         atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1);
 812         mutex_init(&smu->smu_power.power_gate.vcn_gate_lock);
 813         mutex_init(&smu->smu_power.power_gate.jpeg_gate_lock);
 814
 815         smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
 816         smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
 817         smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;
 818         smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2;
 819         smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3;
 820         smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4;
 821         smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5;
 822         smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6;
 823
 824         smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 825         smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
 826         smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING;
 827         smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO;
 828         smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR;
 829         smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE;
 830         smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM;
 831         smu->display_config = &adev->pm.pm_display_cfg;
 832
 833         smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
 834         smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
 835         ret = smu_init_microcode(smu);
 836         if (ret) {
 837                 dev_err(adev->dev, "Failed to load smu firmware!\n");
 838                 return ret;
 839         }
 840
 841         ret = smu_smc_table_sw_init(smu);
 842         if (ret) {
 843                 dev_err(adev->dev, "Failed to sw init smc table!\n");
 844                 return ret;
 845         }
 846
 847         ret = smu_register_irq_handler(smu);
 848         if (ret) {
 849                 dev_err(adev->dev, "Failed to register smc irq handler!\n");
 850                 return ret;
 851         }
 852
 853         return 0;
 854 }
 855
 856 static int smu_sw_fini(void *handle)
 857 {
 858         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 859         struct smu_context *smu = &adev->smu;
 860         int ret;
 861
 862         ret = smu_smc_table_sw_fini(smu);
 863         if (ret) {
 864                 dev_err(adev->dev, "Failed to sw fini smc table!\n");
 865                 return ret;
 866         }
 867
 868         smu_fini_microcode(smu);
 869
 870         return 0;
 871 }
 872
 873 static int smu_get_thermal_temperature_range(struct smu_context *smu)
 874 {
 875         struct amdgpu_device *adev = smu->adev;
 876         struct smu_temperature_range *range =
 877                                 &smu->thermal_range;
 878         int ret = 0;
 879
 880         if (!smu->ppt_funcs->get_thermal_temperature_range)
 881                 return 0;
 882
 883         ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range);
 884         if (ret)
 885                 return ret;
 886
 887         adev->pm.dpm.thermal.min_temp = range->min;
 888         adev->pm.dpm.thermal.max_temp = range->max;
 889         adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max;
 890         adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min;
 891         adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max;
 892         adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max;
 893         adev->pm.dpm.thermal.min_mem_temp = range->mem_min;
 894         adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max;
 895         adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max;
 896
 897         return ret;
 898 }
 899
 900 static int smu_smc_hw_setup(struct smu_context *smu)
 901 {
 902         struct amdgpu_device *adev = smu->adev;
 903         uint32_t pcie_gen = 0, pcie_width = 0;
 904         int ret;
 905
 906         if (adev->in_suspend && smu_is_dpm_running(smu)) {
 907                 dev_info(adev->dev, "dpm has been enabled\n");
 908                 return 0;
 909         }
 910
 911         ret = smu_init_display_count(smu, 0);
 912         if (ret) {
 913                 dev_info(adev->dev, "Failed to pre-set display count as 0!\n");
 914                 return ret;
 915         }
 916
 917         ret = smu_set_driver_table_location(smu);
 918         if (ret) {
 919                 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n");
 920                 return ret;
 921         }
 922
 923         /*
 924          * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools.
 925          */
 926         ret = smu_set_tool_table_location(smu);
 927         if (ret) {
 928                 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n");
 929                 return ret;
 930         }
 931
 932         /*
 933          * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify
 934          * pool location.
 935          */
 936         ret = smu_notify_memory_pool_location(smu);
 937         if (ret) {
 938                 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n");
 939                 return ret;
 940         }
 941
 942         /* smu_dump_pptable(smu); */
 943         /*
 944          * Copy pptable bo in the vram to smc with SMU MSGs such as
 945          * SetDriverDramAddr and TransferTableDram2Smu.
 946          */
 947         ret = smu_write_pptable(smu);
 948         if (ret) {
 949                 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n");
 950                 return ret;
 951         }
 952
 953         /* issue Run*Btc msg */
 954         ret = smu_run_btc(smu);
 955         if (ret)
 956                 return ret;
 957
 958         ret = smu_feature_set_allowed_mask(smu);
 959         if (ret) {
 960                 dev_err(adev->dev, "Failed to set driver allowed features mask!\n");
 961                 return ret;
 962         }
 963
 964         ret = smu_system_features_control(smu, true);
 965         if (ret) {
 966                 dev_err(adev->dev, "Failed to enable requested dpm features!\n");
 967                 return ret;
 968         }
 969
 970         if (!smu_is_dpm_running(smu))
 971                 dev_info(adev->dev, "dpm has been disabled\n");
 972
 973         if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
 974                 pcie_gen = 3;
 975         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
 976                 pcie_gen = 2;
 977         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
 978                 pcie_gen = 1;
 979         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
 980                 pcie_gen = 0;
 981
 982         /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
 983          * Bit 15:8:  PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
 984          * Bit 7:0:   PCIE lane width, 1 to 7 corresponds is x1 to x32
 985          */
 986         if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
 987                 pcie_width = 6;
 988         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
 989                 pcie_width = 5;
 990         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
 991                 pcie_width = 4;
 992         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
 993                 pcie_width = 3;
 994         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
 995                 pcie_width = 2;
 996         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
 997                 pcie_width = 1;
 998         ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width);
 999         if (ret) {
1000                 dev_err(adev->dev, "Attempt to override pcie params failed!\n");
1001                 return ret;
1002         }
1003
1004         ret = smu_get_thermal_temperature_range(smu);
1005         if (ret) {
1006                 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n");
1007                 return ret;
1008         }
1009
1010         ret = smu_enable_thermal_alert(smu);
1011         if (ret) {
1012                 dev_err(adev->dev, "Failed to enable thermal alert!\n");
1013                 return ret;
1014         }
1015
1016         /*
1017          * For Navi1X, manually switch it to AC mode as PMFW
1018          * may boot it with DC mode.
1019          */
1020         ret = smu_set_power_source(smu,
1021                                    adev->pm.ac_power ? SMU_POWER_SOURCE_AC :
1022                                    SMU_POWER_SOURCE_DC);
1023         if (ret) {
1024                 dev_err(adev->dev, "Failed to switch to %s mode!\n", adev->pm.ac_power ? "AC" : "DC");
1025                 return ret;
1026         }
1027
1028         ret = smu_notify_display_change(smu);
1029         if (ret)
1030                 return ret;
1031
1032         /*
1033          * Set min deep sleep dce fclk with bootup value from vbios via
1034          * SetMinDeepSleepDcefclk MSG.
1035          */
1036         ret = smu_set_min_dcef_deep_sleep(smu,
1037                                           smu->smu_table.boot_values.dcefclk / 100);
1038         if (ret)
1039                 return ret;
1040
1041         return ret;
1042 }
1043
1044 static int smu_start_smc_engine(struct smu_context *smu)
1045 {
1046         struct amdgpu_device *adev = smu->adev;
1047         int ret = 0;
1048
1049         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1050                 if (adev->asic_type < CHIP_NAVI10) {
1051                         if (smu->ppt_funcs->load_microcode) {
1052                                 ret = smu->ppt_funcs->load_microcode(smu);
1053                                 if (ret)
1054                                         return ret;
1055                         }
1056                 }
1057         }
1058
1059         if (smu->ppt_funcs->check_fw_status) {
1060                 ret = smu->ppt_funcs->check_fw_status(smu);
1061                 if (ret) {
1062                         dev_err(adev->dev, "SMC is not ready\n");
1063                         return ret;
1064                 }
1065         }
1066
1067         /*
1068          * Send msg GetDriverIfVersion to check if the return value is equal
1069          * with DRIVER_IF_VERSION of smc header.
1070          */
1071         ret = smu_check_fw_version(smu);
1072         if (ret)
1073                 return ret;
1074
1075         return ret;
1076 }
1077
1078 static int smu_hw_init(void *handle)
1079 {
1080         int ret;
1081         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1082         struct smu_context *smu = &adev->smu;
1083
1084         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) {
1085                 smu->pm_enabled = false;
1086                 return 0;
1087         }
1088
1089         ret = smu_start_smc_engine(smu);
1090         if (ret) {
1091                 dev_err(adev->dev, "SMC engine is not correctly up!\n");
1092                 return ret;
1093         }
1094
1095         if (smu->is_apu) {
1096                 smu_powergate_sdma(&adev->smu, false);
1097                 smu_dpm_set_vcn_enable(smu, true);
1098                 smu_dpm_set_jpeg_enable(smu, true);
1099                 smu_set_gfx_cgpg(&adev->smu, true);
1100         }
1101
1102         if (!smu->pm_enabled)
1103                 return 0;
1104
1105         /* get boot_values from vbios to set revision, gfxclk, and etc. */
1106         ret = smu_get_vbios_bootup_values(smu);
1107         if (ret) {
1108                 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n");
1109                 return ret;
1110         }
1111
1112         ret = smu_setup_pptable(smu);
1113         if (ret) {
1114                 dev_err(adev->dev, "Failed to setup pptable!\n");
1115                 return ret;
1116         }
1117
1118         ret = smu_get_driver_allowed_feature_mask(smu);
1119         if (ret)
1120                 return ret;
1121
1122         ret = smu_smc_hw_setup(smu);
1123         if (ret) {
1124                 dev_err(adev->dev, "Failed to setup smc hw!\n");
1125                 return ret;
1126         }
1127
1128         /*
1129          * Move maximum sustainable clock retrieving here considering
1130          * 1. It is not needed on resume(from S3).
1131          * 2. DAL settings come between .hw_init and .late_init of SMU.
1132          *    And DAL needs to know the maximum sustainable clocks. Thus
1133          *    it cannot be put in .late_init().
1134          */
1135         ret = smu_init_max_sustainable_clocks(smu);
1136         if (ret) {
1137                 dev_err(adev->dev, "Failed to init max sustainable clocks!\n");
1138                 return ret;
1139         }
1140
1141         adev->pm.dpm_enabled = true;
1142
1143         dev_info(adev->dev, "SMU is initialized successfully!\n");
1144
1145         return 0;
1146 }
1147
1148 static int smu_disable_dpms(struct smu_context *smu)
1149 {
1150         struct amdgpu_device *adev = smu->adev;
1151         int ret = 0;
1152         bool use_baco = !smu->is_apu &&
1153                 ((amdgpu_in_reset(adev) &&
1154                   (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) ||
1155                  ((adev->in_runpm || adev->in_hibernate) && amdgpu_asic_supports_baco(adev)));
1156
1157         /*
1158          * For custom pptable uploading, skip the DPM features
1159          * disable process on Navi1x ASICs.
1160          *   - As the gfx related features are under control of
1161          *     RLC on those ASICs. RLC reinitialization will be
1162          *     needed to reenable them. That will cost much more
1163          *     efforts.
1164          *
1165          *   - SMU firmware can handle the DPM reenablement
1166          *     properly.
1167          */
1168         if (smu->uploading_custom_pp_table &&
1169             (adev->asic_type >= CHIP_NAVI10) &&
1170             (adev->asic_type <= CHIP_NAVY_FLOUNDER))
1171                 return 0;
1172
1173         /*
1174          * For Sienna_Cichlid, PMFW will handle the features disablement properly
1175          * on BACO in. Driver involvement is unnecessary.
1176          */
1177         if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
1178              use_baco)
1179                 return 0;
1180
1181         /*
1182          * For gpu reset, runpm and hibernation through BACO,
1183          * BACO feature has to be kept enabled.
1184          */
1185         if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) {
1186                 ret = smu_disable_all_features_with_exception(smu,
1187                                                               SMU_FEATURE_BACO_BIT);
1188                 if (ret)
1189                         dev_err(adev->dev, "Failed to disable smu features except BACO.\n");
1190         } else {
1191                 ret = smu_system_features_control(smu, false);
1192                 if (ret)
1193                         dev_err(adev->dev, "Failed to disable smu features.\n");
1194         }
1195
1196         if (adev->asic_type >= CHIP_NAVI10 &&
1197             adev->gfx.rlc.funcs->stop)
1198                 adev->gfx.rlc.funcs->stop(adev);
1199
1200         return ret;
1201 }
1202
1203 static int smu_smc_hw_cleanup(struct smu_context *smu)
1204 {
1205         struct amdgpu_device *adev = smu->adev;
1206         int ret = 0;
1207
1208         cancel_work_sync(&smu->throttling_logging_work);
1209
1210         ret = smu_disable_thermal_alert(smu);
1211         if (ret) {
1212                 dev_err(adev->dev, "Fail to disable thermal alert!\n");
1213                 return ret;
1214         }
1215
1216         ret = smu_disable_dpms(smu);
1217         if (ret) {
1218                 dev_err(adev->dev, "Fail to disable dpm features!\n");
1219                 return ret;
1220         }
1221
1222         return 0;
1223 }
1224
1225 static int smu_hw_fini(void *handle)
1226 {
1227         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1228         struct smu_context *smu = &adev->smu;
1229         int ret = 0;
1230
1231         if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1232                 return 0;
1233
1234         if (smu->is_apu) {
1235                 smu_powergate_sdma(&adev->smu, true);
1236                 smu_dpm_set_vcn_enable(smu, false);
1237                 smu_dpm_set_jpeg_enable(smu, false);
1238         }
1239
1240         if (!smu->pm_enabled)
1241                 return 0;
1242
1243         adev->pm.dpm_enabled = false;
1244
1245         ret = smu_smc_hw_cleanup(smu);
1246         if (ret)
1247                 return ret;
1248
1249         return 0;
1250 }
1251
1252 int smu_reset(struct smu_context *smu)
1253 {
1254         struct amdgpu_device *adev = smu->adev;
1255         int ret;
1256
1257         amdgpu_gfx_off_ctrl(smu->adev, false);
1258
1259         ret = smu_hw_fini(adev);
1260         if (ret)
1261                 return ret;
1262
1263         ret = smu_hw_init(adev);
1264         if (ret)
1265                 return ret;
1266
1267         ret = smu_late_init(adev);
1268         if (ret)
1269                 return ret;
1270
1271         amdgpu_gfx_off_ctrl(smu->adev, true);
1272
1273         return 0;
1274 }
1275
1276 static int smu_suspend(void *handle)
1277 {
1278         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1279         struct smu_context *smu = &adev->smu;
1280         int ret;
1281
1282         if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1283                 return 0;
1284
1285         if (!smu->pm_enabled)
1286                 return 0;
1287
1288         adev->pm.dpm_enabled = false;
1289
1290         ret = smu_smc_hw_cleanup(smu);
1291         if (ret)
1292                 return ret;
1293
1294         smu->watermarks_bitmap &= ~(WATERMARKS_LOADED);
1295
1296         if (smu->is_apu)
1297                 smu_set_gfx_cgpg(&adev->smu, false);
1298
1299         return 0;
1300 }
1301
1302 static int smu_resume(void *handle)
1303 {
1304         int ret;
1305         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1306         struct smu_context *smu = &adev->smu;
1307
1308         if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1309                 return 0;
1310
1311         if (!smu->pm_enabled)
1312                 return 0;
1313
1314         dev_info(adev->dev, "SMU is resuming...\n");
1315
1316         ret = smu_start_smc_engine(smu);
1317         if (ret) {
1318                 dev_err(adev->dev, "SMC engine is not correctly up!\n");
1319                 return ret;
1320         }
1321
1322         ret = smu_smc_hw_setup(smu);
1323         if (ret) {
1324                 dev_err(adev->dev, "Failed to setup smc hw!\n");
1325                 return ret;
1326         }
1327
1328         if (smu->is_apu)
1329                 smu_set_gfx_cgpg(&adev->smu, true);
1330
1331         smu->disable_uclk_switch = 0;
1332
1333         adev->pm.dpm_enabled = true;
1334
1335         dev_info(adev->dev, "SMU is resumed successfully!\n");
1336
1337         return 0;
1338 }
1339
1340 int smu_display_configuration_change(struct smu_context *smu,
1341                                      const struct amd_pp_display_configuration *display_config)
1342 {
1343         int index = 0;
1344         int num_of_active_display = 0;
1345
1346         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1347                 return -EOPNOTSUPP;
1348
1349         if (!display_config)
1350                 return -EINVAL;
1351
1352         mutex_lock(&smu->mutex);
1353
1354         smu_set_min_dcef_deep_sleep(smu,
1355                                     display_config->min_dcef_deep_sleep_set_clk / 100);
1356
1357         for (index = 0; index < display_config->num_path_including_non_display; index++) {
1358                 if (display_config->displays[index].controller_id != 0)
1359                         num_of_active_display++;
1360         }
1361
1362         smu_set_active_display_count(smu, num_of_active_display);
1363
1364         smu_store_cc6_data(smu, display_config->cpu_pstate_separation_time,
1365                            display_config->cpu_cc6_disable,
1366                            display_config->cpu_pstate_disable,
1367                            display_config->nb_pstate_switch_disable);
1368
1369         mutex_unlock(&smu->mutex);
1370
1371         return 0;
1372 }
1373
1374 static int smu_get_clock_info(struct smu_context *smu,
1375                               struct smu_clock_info *clk_info,
1376                               enum smu_perf_level_designation designation)
1377 {
1378         int ret;
1379         struct smu_performance_level level = {0};
1380
1381         if (!clk_info)
1382                 return -EINVAL;
1383
1384         ret = smu_get_perf_level(smu, PERF_LEVEL_ACTIVITY, &level);
1385         if (ret)
1386                 return -EINVAL;
1387
1388         clk_info->min_mem_clk = level.memory_clock;
1389         clk_info->min_eng_clk = level.core_clock;
1390         clk_info->min_bus_bandwidth = level.non_local_mem_freq * level.non_local_mem_width;
1391
1392         ret = smu_get_perf_level(smu, designation, &level);
1393         if (ret)
1394                 return -EINVAL;
1395
1396         clk_info->min_mem_clk = level.memory_clock;
1397         clk_info->min_eng_clk = level.core_clock;
1398         clk_info->min_bus_bandwidth = level.non_local_mem_freq * level.non_local_mem_width;
1399
1400         return 0;
1401 }
1402
1403 int smu_get_current_clocks(struct smu_context *smu,
1404                            struct amd_pp_clock_info *clocks)
1405 {
1406         struct amd_pp_simple_clock_info simple_clocks = {0};
1407         struct smu_clock_info hw_clocks;
1408         int ret = 0;
1409
1410         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1411                 return -EOPNOTSUPP;
1412
1413         mutex_lock(&smu->mutex);
1414
1415         smu_get_dal_power_level(smu, &simple_clocks);
1416
1417         if (smu->support_power_containment)
1418                 ret = smu_get_clock_info(smu, &hw_clocks,
1419                                          PERF_LEVEL_POWER_CONTAINMENT);
1420         else
1421                 ret = smu_get_clock_info(smu, &hw_clocks, PERF_LEVEL_ACTIVITY);
1422
1423         if (ret) {
1424                 dev_err(smu->adev->dev, "Error in smu_get_clock_info\n");
1425                 goto failed;
1426         }
1427
1428         clocks->min_engine_clock = hw_clocks.min_eng_clk;
1429         clocks->max_engine_clock = hw_clocks.max_eng_clk;
1430         clocks->min_memory_clock = hw_clocks.min_mem_clk;
1431         clocks->max_memory_clock = hw_clocks.max_mem_clk;
1432         clocks->min_bus_bandwidth = hw_clocks.min_bus_bandwidth;
1433         clocks->max_bus_bandwidth = hw_clocks.max_bus_bandwidth;
1434         clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1435         clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1436
1437         if (simple_clocks.level == 0)
1438                 clocks->max_clocks_state = PP_DAL_POWERLEVEL_7;
1439         else
1440                 clocks->max_clocks_state = simple_clocks.level;
1441
1442         if (!smu_get_current_shallow_sleep_clocks(smu, &hw_clocks)) {
1443                 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1444                 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1445         }
1446
1447 failed:
1448         mutex_unlock(&smu->mutex);
1449         return ret;
1450 }
1451
1452 static int smu_set_clockgating_state(void *handle,
1453                                      enum amd_clockgating_state state)
1454 {
1455         return 0;
1456 }
1457
1458 static int smu_set_powergating_state(void *handle,
1459                                      enum amd_powergating_state state)
1460 {
1461         return 0;
1462 }
1463
1464 static int smu_enable_umd_pstate(void *handle,
1465                       enum amd_dpm_forced_level *level)
1466 {
1467         uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
1468                                         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
1469                                         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
1470                                         AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
1471
1472         struct smu_context *smu = (struct smu_context*)(handle);
1473         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1474
1475         if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1476                 return -EINVAL;
1477
1478         if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) {
1479                 /* enter umd pstate, save current level, disable gfx cg*/
1480                 if (*level & profile_mode_mask) {
1481                         smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
1482                         smu_dpm_ctx->enable_umd_pstate = true;
1483                         amdgpu_device_ip_set_powergating_state(smu->adev,
1484                                                                AMD_IP_BLOCK_TYPE_GFX,
1485                                                                AMD_PG_STATE_UNGATE);
1486                         amdgpu_device_ip_set_clockgating_state(smu->adev,
1487                                                                AMD_IP_BLOCK_TYPE_GFX,
1488                                                                AMD_CG_STATE_UNGATE);
1489                         smu_gfx_ulv_control(smu, false);
1490                         smu_deep_sleep_control(smu, false);
1491                 }
1492         } else {
1493                 /* exit umd pstate, restore level, enable gfx cg*/
1494                 if (!(*level & profile_mode_mask)) {
1495                         if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
1496                                 *level = smu_dpm_ctx->saved_dpm_level;
1497                         smu_dpm_ctx->enable_umd_pstate = false;
1498                         smu_deep_sleep_control(smu, true);
1499                         smu_gfx_ulv_control(smu, true);
1500                         amdgpu_device_ip_set_clockgating_state(smu->adev,
1501                                                                AMD_IP_BLOCK_TYPE_GFX,
1502                                                                AMD_CG_STATE_GATE);
1503                         amdgpu_device_ip_set_powergating_state(smu->adev,
1504                                                                AMD_IP_BLOCK_TYPE_GFX,
1505                                                                AMD_PG_STATE_GATE);
1506                 }
1507         }
1508
1509         return 0;
1510 }
1511
1512 static int smu_adjust_power_state_dynamic(struct smu_context *smu,
1513                                    enum amd_dpm_forced_level level,
1514                                    bool skip_display_settings)
1515 {
1516         int ret = 0;
1517         int index = 0;
1518         long workload;
1519         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1520
1521         if (!skip_display_settings) {
1522                 ret = smu_display_config_changed(smu);
1523                 if (ret) {
1524                         dev_err(smu->adev->dev, "Failed to change display config!");
1525                         return ret;
1526                 }
1527         }
1528
1529         ret = smu_apply_clocks_adjust_rules(smu);
1530         if (ret) {
1531                 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!");
1532                 return ret;
1533         }
1534
1535         if (!skip_display_settings) {
1536                 ret = smu_notify_smc_display_config(smu);
1537                 if (ret) {
1538                         dev_err(smu->adev->dev, "Failed to notify smc display config!");
1539                         return ret;
1540                 }
1541         }
1542
1543         if (smu_dpm_ctx->dpm_level != level) {
1544                 ret = smu_asic_set_performance_level(smu, level);
1545                 if (ret) {
1546                         dev_err(smu->adev->dev, "Failed to set performance level!");
1547                         return ret;
1548                 }
1549
1550                 /* update the saved copy */
1551                 smu_dpm_ctx->dpm_level = level;
1552         }
1553
1554         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1555                 index = fls(smu->workload_mask);
1556                 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1557                 workload = smu->workload_setting[index];
1558
1559                 if (smu->power_profile_mode != workload)
1560                         smu_set_power_profile_mode(smu, &workload, 0, false);
1561         }
1562
1563         return ret;
1564 }
1565
1566 int smu_handle_task(struct smu_context *smu,
1567                     enum amd_dpm_forced_level level,
1568                     enum amd_pp_task task_id,
1569                     bool lock_needed)
1570 {
1571         int ret = 0;
1572
1573         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1574                 return -EOPNOTSUPP;
1575
1576         if (lock_needed)
1577                 mutex_lock(&smu->mutex);
1578
1579         switch (task_id) {
1580         case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
1581                 ret = smu_pre_display_config_changed(smu);
1582                 if (ret)
1583                         goto out;
1584                 ret = smu_set_cpu_power_state(smu);
1585                 if (ret)
1586                         goto out;
1587                 ret = smu_adjust_power_state_dynamic(smu, level, false);
1588                 break;
1589         case AMD_PP_TASK_COMPLETE_INIT:
1590         case AMD_PP_TASK_READJUST_POWER_STATE:
1591                 ret = smu_adjust_power_state_dynamic(smu, level, true);
1592                 break;
1593         default:
1594                 break;
1595         }
1596
1597 out:
1598         if (lock_needed)
1599                 mutex_unlock(&smu->mutex);
1600
1601         return ret;
1602 }
1603
1604 int smu_switch_power_profile(struct smu_context *smu,
1605                              enum PP_SMC_POWER_PROFILE type,
1606                              bool en)
1607 {
1608         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1609         long workload;
1610         uint32_t index;
1611
1612         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1613                 return -EOPNOTSUPP;
1614
1615         if (!(type < PP_SMC_POWER_PROFILE_CUSTOM))
1616                 return -EINVAL;
1617
1618         mutex_lock(&smu->mutex);
1619
1620         if (!en) {
1621                 smu->workload_mask &= ~(1 << smu->workload_prority[type]);
1622                 index = fls(smu->workload_mask);
1623                 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1624                 workload = smu->workload_setting[index];
1625         } else {
1626                 smu->workload_mask |= (1 << smu->workload_prority[type]);
1627                 index = fls(smu->workload_mask);
1628                 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1629                 workload = smu->workload_setting[index];
1630         }
1631
1632         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
1633                 smu_set_power_profile_mode(smu, &workload, 0, false);
1634
1635         mutex_unlock(&smu->mutex);
1636
1637         return 0;
1638 }
1639
1640 enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu)
1641 {
1642         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1643         enum amd_dpm_forced_level level;
1644
1645         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1646                 return -EOPNOTSUPP;
1647
1648         if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1649                 return -EINVAL;
1650
1651         mutex_lock(&(smu->mutex));
1652         level = smu_dpm_ctx->dpm_level;
1653         mutex_unlock(&(smu->mutex));
1654
1655         return level;
1656 }
1657
1658 int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
1659 {
1660         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1661         int ret = 0;
1662
1663         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1664                 return -EOPNOTSUPP;
1665
1666         if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1667                 return -EINVAL;
1668
1669         mutex_lock(&smu->mutex);
1670
1671         ret = smu_enable_umd_pstate(smu, &level);
1672         if (ret) {
1673                 mutex_unlock(&smu->mutex);
1674                 return ret;
1675         }
1676
1677         ret = smu_handle_task(smu, level,
1678                               AMD_PP_TASK_READJUST_POWER_STATE,
1679                               false);
1680
1681         mutex_unlock(&smu->mutex);
1682
1683         return ret;
1684 }
1685
1686 int smu_set_display_count(struct smu_context *smu, uint32_t count)
1687 {
1688         int ret = 0;
1689
1690         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1691                 return -EOPNOTSUPP;
1692
1693         mutex_lock(&smu->mutex);
1694         ret = smu_init_display_count(smu, count);
1695         mutex_unlock(&smu->mutex);
1696
1697         return ret;
1698 }
1699
1700 int smu_force_clk_levels(struct smu_context *smu,
1701                          enum smu_clk_type clk_type,
1702                          uint32_t mask)
1703 {
1704         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1705         int ret = 0;
1706
1707         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1708                 return -EOPNOTSUPP;
1709
1710         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1711                 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n");
1712                 return -EINVAL;
1713         }
1714
1715         mutex_lock(&smu->mutex);
1716
1717         if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels)
1718                 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask);
1719
1720         mutex_unlock(&smu->mutex);
1721
1722         return ret;
1723 }
1724
1725 /*
1726  * On system suspending or resetting, the dpm_enabled
1727  * flag will be cleared. So that those SMU services which
1728  * are not supported will be gated.
1729  * However, the mp1 state setting should still be granted
1730  * even if the dpm_enabled cleared.
1731  */
1732 int smu_set_mp1_state(struct smu_context *smu,
1733                       enum pp_mp1_state mp1_state)
1734 {
1735         uint16_t msg;
1736         int ret;
1737
1738         if (!smu->pm_enabled)
1739                 return -EOPNOTSUPP;
1740
1741         mutex_lock(&smu->mutex);
1742
1743         switch (mp1_state) {
1744         case PP_MP1_STATE_SHUTDOWN:
1745                 msg = SMU_MSG_PrepareMp1ForShutdown;
1746                 break;
1747         case PP_MP1_STATE_UNLOAD:
1748                 msg = SMU_MSG_PrepareMp1ForUnload;
1749                 break;
1750         case PP_MP1_STATE_RESET:
1751                 msg = SMU_MSG_PrepareMp1ForReset;
1752                 break;
1753         case PP_MP1_STATE_NONE:
1754         default:
1755                 mutex_unlock(&smu->mutex);
1756                 return 0;
1757         }
1758
1759         ret = smu_send_smc_msg(smu, msg, NULL);
1760         /* some asics may not support those messages */
1761         if (ret == -EINVAL)
1762                 ret = 0;
1763         if (ret)
1764                 dev_err(smu->adev->dev, "[PrepareMp1] Failed!\n");
1765
1766         mutex_unlock(&smu->mutex);
1767
1768         return ret;
1769 }
1770
1771 int smu_set_df_cstate(struct smu_context *smu,
1772                       enum pp_df_cstate state)
1773 {
1774         int ret = 0;
1775
1776         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1777                 return -EOPNOTSUPP;
1778
1779         if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate)
1780                 return 0;
1781
1782         mutex_lock(&smu->mutex);
1783
1784         ret = smu->ppt_funcs->set_df_cstate(smu, state);
1785         if (ret)
1786                 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n");
1787
1788         mutex_unlock(&smu->mutex);
1789
1790         return ret;
1791 }
1792
1793 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en)
1794 {
1795         int ret = 0;
1796
1797         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1798                 return -EOPNOTSUPP;
1799
1800         if (!smu->ppt_funcs || !smu->ppt_funcs->allow_xgmi_power_down)
1801                 return 0;
1802
1803         mutex_lock(&smu->mutex);
1804
1805         ret = smu->ppt_funcs->allow_xgmi_power_down(smu, en);
1806         if (ret)
1807                 dev_err(smu->adev->dev, "[AllowXgmiPowerDown] failed!\n");
1808
1809         mutex_unlock(&smu->mutex);
1810
1811         return ret;
1812 }
1813
1814 int smu_write_watermarks_table(struct smu_context *smu)
1815 {
1816         int ret = 0;
1817
1818         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1819                 return -EOPNOTSUPP;
1820
1821         mutex_lock(&smu->mutex);
1822
1823         ret = smu_set_watermarks_table(smu, NULL);
1824
1825         mutex_unlock(&smu->mutex);
1826
1827         return ret;
1828 }
1829
1830 int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
1831                 struct pp_smu_wm_range_sets *clock_ranges)
1832 {
1833         int ret = 0;
1834
1835         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1836                 return -EOPNOTSUPP;
1837
1838         mutex_lock(&smu->mutex);
1839
1840         if (!smu->disable_watermark &&
1841                         smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1842                         smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1843                 ret = smu_set_watermarks_table(smu, clock_ranges);
1844
1845                 if (!(smu->watermarks_bitmap & WATERMARKS_EXIST)) {
1846                         smu->watermarks_bitmap |= WATERMARKS_EXIST;
1847                         smu->watermarks_bitmap &= ~WATERMARKS_LOADED;
1848                 }
1849         }
1850
1851         mutex_unlock(&smu->mutex);
1852
1853         return ret;
1854 }
1855
1856 int smu_set_ac_dc(struct smu_context *smu)
1857 {
1858         int ret = 0;
1859
1860         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1861                 return -EOPNOTSUPP;
1862
1863         /* controlled by firmware */
1864         if (smu->dc_controlled_by_gpio)
1865                 return 0;
1866
1867         mutex_lock(&smu->mutex);
1868         ret = smu_set_power_source(smu,
1869                                    smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC :
1870                                    SMU_POWER_SOURCE_DC);
1871         if (ret)
1872                 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n",
1873                        smu->adev->pm.ac_power ? "AC" : "DC");
1874         mutex_unlock(&smu->mutex);
1875
1876         return ret;
1877 }
1878
1879 const struct amd_ip_funcs smu_ip_funcs = {
1880         .name = "smu",
1881         .early_init = smu_early_init,
1882         .late_init = smu_late_init,
1883         .sw_init = smu_sw_init,
1884         .sw_fini = smu_sw_fini,
1885         .hw_init = smu_hw_init,
1886         .hw_fini = smu_hw_fini,
1887         .suspend = smu_suspend,
1888         .resume = smu_resume,
1889         .is_idle = NULL,
1890         .check_soft_reset = NULL,
1891         .wait_for_idle = NULL,
1892         .soft_reset = NULL,
1893         .set_clockgating_state = smu_set_clockgating_state,
1894         .set_powergating_state = smu_set_powergating_state,
1895         .enable_umd_pstate = smu_enable_umd_pstate,
1896 };
1897
1898 const struct amdgpu_ip_block_version smu_v11_0_ip_block =
1899 {
1900         .type = AMD_IP_BLOCK_TYPE_SMC,
1901         .major = 11,
1902         .minor = 0,
1903         .rev = 0,
1904         .funcs = &smu_ip_funcs,
1905 };
1906
1907 const struct amdgpu_ip_block_version smu_v12_0_ip_block =
1908 {
1909         .type = AMD_IP_BLOCK_TYPE_SMC,
1910         .major = 12,
1911         .minor = 0,
1912         .rev = 0,
1913         .funcs = &smu_ip_funcs,
1914 };
1915
1916 int smu_load_microcode(struct smu_context *smu)
1917 {
1918         int ret = 0;
1919
1920         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1921                 return -EOPNOTSUPP;
1922
1923         mutex_lock(&smu->mutex);
1924
1925         if (smu->ppt_funcs->load_microcode)
1926                 ret = smu->ppt_funcs->load_microcode(smu);
1927
1928         mutex_unlock(&smu->mutex);
1929
1930         return ret;
1931 }
1932
1933 int smu_check_fw_status(struct smu_context *smu)
1934 {
1935         int ret = 0;
1936
1937         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1938                 return -EOPNOTSUPP;
1939
1940         mutex_lock(&smu->mutex);
1941
1942         if (smu->ppt_funcs->check_fw_status)
1943                 ret = smu->ppt_funcs->check_fw_status(smu);
1944
1945         mutex_unlock(&smu->mutex);
1946
1947         return ret;
1948 }
1949
1950 int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled)
1951 {
1952         int ret = 0;
1953
1954         mutex_lock(&smu->mutex);
1955
1956         if (smu->ppt_funcs->set_gfx_cgpg)
1957                 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled);
1958
1959         mutex_unlock(&smu->mutex);
1960
1961         return ret;
1962 }
1963
1964 int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed)
1965 {
1966         int ret = 0;
1967
1968         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1969                 return -EOPNOTSUPP;
1970
1971         mutex_lock(&smu->mutex);
1972
1973         if (smu->ppt_funcs->set_fan_speed_rpm)
1974                 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed);
1975
1976         mutex_unlock(&smu->mutex);
1977
1978         return ret;
1979 }
1980
1981 int smu_get_power_limit(struct smu_context *smu,
1982                         uint32_t *limit,
1983                         bool max_setting)
1984 {
1985         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1986                 return -EOPNOTSUPP;
1987
1988         mutex_lock(&smu->mutex);
1989
1990         *limit = (max_setting ? smu->max_power_limit : smu->current_power_limit);
1991
1992         mutex_unlock(&smu->mutex);
1993
1994         return 0;
1995 }
1996
1997 int smu_set_power_limit(struct smu_context *smu, uint32_t limit)
1998 {
1999         int ret = 0;
2000
2001         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2002                 return -EOPNOTSUPP;
2003
2004         mutex_lock(&smu->mutex);
2005
2006         if (limit > smu->max_power_limit) {
2007                 dev_err(smu->adev->dev,
2008                         "New power limit (%d) is over the max allowed %d\n",
2009                         limit, smu->max_power_limit);
2010                 goto out;
2011         }
2012
2013         if (!limit)
2014                 limit = smu->current_power_limit;
2015
2016         if (smu->ppt_funcs->set_power_limit)
2017                 ret = smu->ppt_funcs->set_power_limit(smu, limit);
2018
2019 out:
2020         mutex_unlock(&smu->mutex);
2021
2022         return ret;
2023 }
2024
2025 int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf)
2026 {
2027         int ret = 0;
2028
2029         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2030                 return -EOPNOTSUPP;
2031
2032         mutex_lock(&smu->mutex);
2033
2034         if (smu->ppt_funcs->print_clk_levels)
2035                 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf);
2036
2037         mutex_unlock(&smu->mutex);
2038
2039         return ret;
2040 }
2041
2042 int smu_get_od_percentage(struct smu_context *smu, enum smu_clk_type type)
2043 {
2044         int ret = 0;
2045
2046         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2047                 return -EOPNOTSUPP;
2048
2049         mutex_lock(&smu->mutex);
2050
2051         if (smu->ppt_funcs->get_od_percentage)
2052                 ret = smu->ppt_funcs->get_od_percentage(smu, type);
2053
2054         mutex_unlock(&smu->mutex);
2055
2056         return ret;
2057 }
2058
2059 int smu_set_od_percentage(struct smu_context *smu, enum smu_clk_type type, uint32_t value)
2060 {
2061         int ret = 0;
2062
2063         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2064                 return -EOPNOTSUPP;
2065
2066         mutex_lock(&smu->mutex);
2067
2068         if (smu->ppt_funcs->set_od_percentage)
2069                 ret = smu->ppt_funcs->set_od_percentage(smu, type, value);
2070
2071         mutex_unlock(&smu->mutex);
2072
2073         return ret;
2074 }
2075
2076 int smu_od_edit_dpm_table(struct smu_context *smu,
2077                           enum PP_OD_DPM_TABLE_COMMAND type,
2078                           long *input, uint32_t size)
2079 {
2080         int ret = 0;
2081
2082         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2083                 return -EOPNOTSUPP;
2084
2085         mutex_lock(&smu->mutex);
2086
2087         if (smu->ppt_funcs->od_edit_dpm_table) {
2088                 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size);
2089                 if (!ret && (type == PP_OD_COMMIT_DPM_TABLE))
2090                         ret = smu_handle_task(smu,
2091                                               smu->smu_dpm.dpm_level,
2092                                               AMD_PP_TASK_READJUST_POWER_STATE,
2093                                               false);
2094         }
2095
2096         mutex_unlock(&smu->mutex);
2097
2098         return ret;
2099 }
2100
2101 int smu_read_sensor(struct smu_context *smu,
2102                     enum amd_pp_sensors sensor,
2103                     void *data, uint32_t *size)
2104 {
2105         struct smu_umd_pstate_table *pstate_table =
2106                                 &smu->pstate_table;
2107         int ret = 0;
2108
2109         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2110                 return -EOPNOTSUPP;
2111
2112         if (!data || !size)
2113                 return -EINVAL;
2114
2115         mutex_lock(&smu->mutex);
2116
2117         if (smu->ppt_funcs->read_sensor)
2118                 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size))
2119                         goto unlock;
2120
2121         switch (sensor) {
2122         case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
2123                 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100;
2124                 *size = 4;
2125                 break;
2126         case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
2127                 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100;
2128                 *size = 4;
2129                 break;
2130         case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
2131                 ret = smu_feature_get_enabled_mask(smu, (uint32_t *)data, 2);
2132                 *size = 8;
2133                 break;
2134         case AMDGPU_PP_SENSOR_UVD_POWER:
2135                 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0;
2136                 *size = 4;
2137                 break;
2138         case AMDGPU_PP_SENSOR_VCE_POWER:
2139                 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0;
2140                 *size = 4;
2141                 break;
2142         case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
2143                 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0: 1;
2144                 *size = 4;
2145                 break;
2146         case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
2147                 *(uint32_t *)data = 0;
2148                 *size = 4;
2149                 break;
2150         default:
2151                 *size = 0;
2152                 ret = -EOPNOTSUPP;
2153                 break;
2154         }
2155
2156 unlock:
2157         mutex_unlock(&smu->mutex);
2158
2159         return ret;
2160 }
2161
2162 int smu_get_power_profile_mode(struct smu_context *smu, char *buf)
2163 {
2164         int ret = 0;
2165
2166         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2167                 return -EOPNOTSUPP;
2168
2169         mutex_lock(&smu->mutex);
2170
2171         if (smu->ppt_funcs->get_power_profile_mode)
2172                 ret = smu->ppt_funcs->get_power_profile_mode(smu, buf);
2173
2174         mutex_unlock(&smu->mutex);
2175
2176         return ret;
2177 }
2178
2179 int smu_set_power_profile_mode(struct smu_context *smu,
2180                                long *param,
2181                                uint32_t param_size,
2182                                bool lock_needed)
2183 {
2184         int ret = 0;
2185
2186         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2187                 return -EOPNOTSUPP;
2188
2189         if (lock_needed)
2190                 mutex_lock(&smu->mutex);
2191
2192         if (smu->ppt_funcs->set_power_profile_mode)
2193                 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size);
2194
2195         if (lock_needed)
2196                 mutex_unlock(&smu->mutex);
2197
2198         return ret;
2199 }
2200
2201
2202 int smu_get_fan_control_mode(struct smu_context *smu)
2203 {
2204         int ret = 0;
2205
2206         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2207                 return -EOPNOTSUPP;
2208
2209         mutex_lock(&smu->mutex);
2210
2211         if (smu->ppt_funcs->get_fan_control_mode)
2212                 ret = smu->ppt_funcs->get_fan_control_mode(smu);
2213
2214         mutex_unlock(&smu->mutex);
2215
2216         return ret;
2217 }
2218
2219 int smu_set_fan_control_mode(struct smu_context *smu, int value)
2220 {
2221         int ret = 0;
2222
2223         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2224                 return -EOPNOTSUPP;
2225
2226         mutex_lock(&smu->mutex);
2227
2228         if (smu->ppt_funcs->set_fan_control_mode)
2229                 ret = smu->ppt_funcs->set_fan_control_mode(smu, value);
2230
2231         mutex_unlock(&smu->mutex);
2232
2233         return ret;
2234 }
2235
2236 int smu_get_fan_speed_percent(struct smu_context *smu, uint32_t *speed)
2237 {
2238         int ret = 0;
2239         uint32_t percent;
2240         uint32_t current_rpm;
2241
2242         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2243                 return -EOPNOTSUPP;
2244
2245         mutex_lock(&smu->mutex);
2246
2247         if (smu->ppt_funcs->get_fan_speed_rpm) {
2248                 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, &current_rpm);
2249                 if (!ret) {
2250                         percent = current_rpm * 100 / smu->fan_max_rpm;
2251                         *speed = percent > 100 ? 100 : percent;
2252                 }
2253         }
2254
2255         mutex_unlock(&smu->mutex);
2256
2257
2258         return ret;
2259 }
2260
2261 int smu_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
2262 {
2263         int ret = 0;
2264         uint32_t rpm;
2265
2266         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2267                 return -EOPNOTSUPP;
2268
2269         mutex_lock(&smu->mutex);
2270
2271         if (smu->ppt_funcs->set_fan_speed_rpm) {
2272                 if (speed > 100)
2273                         speed = 100;
2274                 rpm = speed * smu->fan_max_rpm / 100;
2275                 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, rpm);
2276         }
2277
2278         mutex_unlock(&smu->mutex);
2279
2280         return ret;
2281 }
2282
2283 int smu_get_fan_speed_rpm(struct smu_context *smu, uint32_t *speed)
2284 {
2285         int ret = 0;
2286
2287         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2288                 return -EOPNOTSUPP;
2289
2290         mutex_lock(&smu->mutex);
2291
2292         if (smu->ppt_funcs->get_fan_speed_rpm)
2293                 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed);
2294
2295         mutex_unlock(&smu->mutex);
2296
2297         return ret;
2298 }
2299
2300 int smu_set_deep_sleep_dcefclk(struct smu_context *smu, int clk)
2301 {
2302         int ret = 0;
2303
2304         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2305                 return -EOPNOTSUPP;
2306
2307         mutex_lock(&smu->mutex);
2308
2309         ret = smu_set_min_dcef_deep_sleep(smu, clk);
2310
2311         mutex_unlock(&smu->mutex);
2312
2313         return ret;
2314 }
2315
2316 int smu_get_clock_by_type(struct smu_context *smu,
2317                           enum amd_pp_clock_type type,
2318                           struct amd_pp_clocks *clocks)
2319 {
2320         int ret = 0;
2321
2322         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2323                 return -EOPNOTSUPP;
2324
2325         mutex_lock(&smu->mutex);
2326
2327         if (smu->ppt_funcs->get_clock_by_type)
2328                 ret = smu->ppt_funcs->get_clock_by_type(smu, type, clocks);
2329
2330         mutex_unlock(&smu->mutex);
2331
2332         return ret;
2333 }
2334
2335 int smu_get_max_high_clocks(struct smu_context *smu,
2336                             struct amd_pp_simple_clock_info *clocks)
2337 {
2338         int ret = 0;
2339
2340         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2341                 return -EOPNOTSUPP;
2342
2343         mutex_lock(&smu->mutex);
2344
2345         if (smu->ppt_funcs->get_max_high_clocks)
2346                 ret = smu->ppt_funcs->get_max_high_clocks(smu, clocks);
2347
2348         mutex_unlock(&smu->mutex);
2349
2350         return ret;
2351 }
2352
2353 int smu_get_clock_by_type_with_latency(struct smu_context *smu,
2354                                        enum smu_clk_type clk_type,
2355                                        struct pp_clock_levels_with_latency *clocks)
2356 {
2357         int ret = 0;
2358
2359         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2360                 return -EOPNOTSUPP;
2361
2362         mutex_lock(&smu->mutex);
2363
2364         if (smu->ppt_funcs->get_clock_by_type_with_latency)
2365                 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks);
2366
2367         mutex_unlock(&smu->mutex);
2368
2369         return ret;
2370 }
2371
2372 int smu_get_clock_by_type_with_voltage(struct smu_context *smu,
2373                                        enum amd_pp_clock_type type,
2374                                        struct pp_clock_levels_with_voltage *clocks)
2375 {
2376         int ret = 0;
2377
2378         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2379                 return -EOPNOTSUPP;
2380
2381         mutex_lock(&smu->mutex);
2382
2383         if (smu->ppt_funcs->get_clock_by_type_with_voltage)
2384                 ret = smu->ppt_funcs->get_clock_by_type_with_voltage(smu, type, clocks);
2385
2386         mutex_unlock(&smu->mutex);
2387
2388         return ret;
2389 }
2390
2391
2392 int smu_display_clock_voltage_request(struct smu_context *smu,
2393                                       struct pp_display_clock_request *clock_req)
2394 {
2395         int ret = 0;
2396
2397         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2398                 return -EOPNOTSUPP;
2399
2400         mutex_lock(&smu->mutex);
2401
2402         if (smu->ppt_funcs->display_clock_voltage_request)
2403                 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req);
2404
2405         mutex_unlock(&smu->mutex);
2406
2407         return ret;
2408 }
2409
2410
2411 int smu_display_disable_memory_clock_switch(struct smu_context *smu, bool disable_memory_clock_switch)
2412 {
2413         int ret = -EINVAL;
2414
2415         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2416                 return -EOPNOTSUPP;
2417
2418         mutex_lock(&smu->mutex);
2419
2420         if (smu->ppt_funcs->display_disable_memory_clock_switch)
2421                 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch);
2422
2423         mutex_unlock(&smu->mutex);
2424
2425         return ret;
2426 }
2427
2428 int smu_notify_smu_enable_pwe(struct smu_context *smu)
2429 {
2430         int ret = 0;
2431
2432         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2433                 return -EOPNOTSUPP;
2434
2435         mutex_lock(&smu->mutex);
2436
2437         if (smu->ppt_funcs->notify_smu_enable_pwe)
2438                 ret = smu->ppt_funcs->notify_smu_enable_pwe(smu);
2439
2440         mutex_unlock(&smu->mutex);
2441
2442         return ret;
2443 }
2444
2445 int smu_set_xgmi_pstate(struct smu_context *smu,
2446                         uint32_t pstate)
2447 {
2448         int ret = 0;
2449
2450         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2451                 return -EOPNOTSUPP;
2452
2453         mutex_lock(&smu->mutex);
2454
2455         if (smu->ppt_funcs->set_xgmi_pstate)
2456                 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate);
2457
2458         mutex_unlock(&smu->mutex);
2459
2460         if(ret)
2461                 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n");
2462
2463         return ret;
2464 }
2465
2466 int smu_set_azalia_d3_pme(struct smu_context *smu)
2467 {
2468         int ret = 0;
2469
2470         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2471                 return -EOPNOTSUPP;
2472
2473         mutex_lock(&smu->mutex);
2474
2475         if (smu->ppt_funcs->set_azalia_d3_pme)
2476                 ret = smu->ppt_funcs->set_azalia_d3_pme(smu);
2477
2478         mutex_unlock(&smu->mutex);
2479
2480         return ret;
2481 }
2482
2483 /*
2484  * On system suspending or resetting, the dpm_enabled
2485  * flag will be cleared. So that those SMU services which
2486  * are not supported will be gated.
2487  *
2488  * However, the baco/mode1 reset should still be granted
2489  * as they are still supported and necessary.
2490  */
2491 bool smu_baco_is_support(struct smu_context *smu)
2492 {
2493         bool ret = false;
2494
2495         if (!smu->pm_enabled)
2496                 return false;
2497
2498         mutex_lock(&smu->mutex);
2499
2500         if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support)
2501                 ret = smu->ppt_funcs->baco_is_support(smu);
2502
2503         mutex_unlock(&smu->mutex);
2504
2505         return ret;
2506 }
2507
2508 int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state)
2509 {
2510         if (smu->ppt_funcs->baco_get_state)
2511                 return -EINVAL;
2512
2513         mutex_lock(&smu->mutex);
2514         *state = smu->ppt_funcs->baco_get_state(smu);
2515         mutex_unlock(&smu->mutex);
2516
2517         return 0;
2518 }
2519
2520 int smu_baco_enter(struct smu_context *smu)
2521 {
2522         int ret = 0;
2523
2524         if (!smu->pm_enabled)
2525                 return -EOPNOTSUPP;
2526
2527         mutex_lock(&smu->mutex);
2528
2529         if (smu->ppt_funcs->baco_enter)
2530                 ret = smu->ppt_funcs->baco_enter(smu);
2531
2532         mutex_unlock(&smu->mutex);
2533
2534         if (ret)
2535                 dev_err(smu->adev->dev, "Failed to enter BACO state!\n");
2536
2537         return ret;
2538 }
2539
2540 int smu_baco_exit(struct smu_context *smu)
2541 {
2542         int ret = 0;
2543
2544         if (!smu->pm_enabled)
2545                 return -EOPNOTSUPP;
2546
2547         mutex_lock(&smu->mutex);
2548
2549         if (smu->ppt_funcs->baco_exit)
2550                 ret = smu->ppt_funcs->baco_exit(smu);
2551
2552         mutex_unlock(&smu->mutex);
2553
2554         if (ret)
2555                 dev_err(smu->adev->dev, "Failed to exit BACO state!\n");
2556
2557         return ret;
2558 }
2559
2560 bool smu_mode1_reset_is_support(struct smu_context *smu)
2561 {
2562         bool ret = false;
2563
2564         if (!smu->pm_enabled)
2565                 return false;
2566
2567         mutex_lock(&smu->mutex);
2568
2569         if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support)
2570                 ret = smu->ppt_funcs->mode1_reset_is_support(smu);
2571
2572         mutex_unlock(&smu->mutex);
2573
2574         return ret;
2575 }
2576
2577 int smu_mode1_reset(struct smu_context *smu)
2578 {
2579         int ret = 0;
2580
2581         if (!smu->pm_enabled)
2582                 return -EOPNOTSUPP;
2583
2584         mutex_lock(&smu->mutex);
2585
2586         if (smu->ppt_funcs->mode1_reset)
2587                 ret = smu->ppt_funcs->mode1_reset(smu);
2588
2589         mutex_unlock(&smu->mutex);
2590
2591         return ret;
2592 }
2593
2594 int smu_mode2_reset(struct smu_context *smu)
2595 {
2596         int ret = 0;
2597
2598         if (!smu->pm_enabled)
2599                 return -EOPNOTSUPP;
2600
2601         mutex_lock(&smu->mutex);
2602
2603         if (smu->ppt_funcs->mode2_reset)
2604                 ret = smu->ppt_funcs->mode2_reset(smu);
2605
2606         mutex_unlock(&smu->mutex);
2607
2608         if (ret)
2609                 dev_err(smu->adev->dev, "Mode2 reset failed!\n");
2610
2611         return ret;
2612 }
2613
2614 int smu_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
2615                                          struct pp_smu_nv_clock_table *max_clocks)
2616 {
2617         int ret = 0;
2618
2619         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2620                 return -EOPNOTSUPP;
2621
2622         mutex_lock(&smu->mutex);
2623
2624         if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc)
2625                 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks);
2626
2627         mutex_unlock(&smu->mutex);
2628
2629         return ret;
2630 }
2631
2632 int smu_get_uclk_dpm_states(struct smu_context *smu,
2633                             unsigned int *clock_values_in_khz,
2634                             unsigned int *num_states)
2635 {
2636         int ret = 0;
2637
2638         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2639                 return -EOPNOTSUPP;
2640
2641         mutex_lock(&smu->mutex);
2642
2643         if (smu->ppt_funcs->get_uclk_dpm_states)
2644                 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states);
2645
2646         mutex_unlock(&smu->mutex);
2647
2648         return ret;
2649 }
2650
2651 enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu)
2652 {
2653         enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT;
2654
2655         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2656                 return -EOPNOTSUPP;
2657
2658         mutex_lock(&smu->mutex);
2659
2660         if (smu->ppt_funcs->get_current_power_state)
2661                 pm_state = smu->ppt_funcs->get_current_power_state(smu);
2662
2663         mutex_unlock(&smu->mutex);
2664
2665         return pm_state;
2666 }
2667
2668 int smu_get_dpm_clock_table(struct smu_context *smu,
2669                             struct dpm_clocks *clock_table)
2670 {
2671         int ret = 0;
2672
2673         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2674                 return -EOPNOTSUPP;
2675
2676         mutex_lock(&smu->mutex);
2677
2678         if (smu->ppt_funcs->get_dpm_clock_table)
2679                 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table);
2680
2681         mutex_unlock(&smu->mutex);
2682
2683         return ret;
2684 }
2685
2686 ssize_t smu_sys_get_gpu_metrics(struct smu_context *smu,
2687                                 void **table)
2688 {
2689         ssize_t size;
2690
2691         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2692                 return -EOPNOTSUPP;
2693
2694         if (!smu->ppt_funcs->get_gpu_metrics)
2695                 return -EOPNOTSUPP;
2696
2697         mutex_lock(&smu->mutex);
2698
2699         size = smu->ppt_funcs->get_gpu_metrics(smu, table);
2700
2701         mutex_unlock(&smu->mutex);
2702
2703         return size;
2704 }
2705
2706 int smu_enable_mgpu_fan_boost(struct smu_context *smu)
2707 {
2708         int ret = 0;
2709
2710         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2711                 return -EOPNOTSUPP;
2712
2713         mutex_lock(&smu->mutex);
2714
2715         if (smu->ppt_funcs->enable_mgpu_fan_boost)
2716                 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu);
2717
2718         mutex_unlock(&smu->mutex);
2719
2720         return ret;
2721 }