2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/pci.h>
29 #include "smu_ucode_xfer_vi.h"
30 #include "polaris10_smumgr.h"
31 #include "smu74_discrete.h"
32 #include "smu/smu_7_1_3_d.h"
33 #include "smu/smu_7_1_3_sh_mask.h"
34 #include "gmc/gmc_8_1_d.h"
35 #include "gmc/gmc_8_1_sh_mask.h"
36 #include "oss/oss_3_0_d.h"
37 #include "gca/gfx_8_0_d.h"
38 #include "bif/bif_5_0_d.h"
39 #include "bif/bif_5_0_sh_mask.h"
40 #include "ppatomctrl.h"
41 #include "cgs_common.h"
42 #include "smu7_ppsmc.h"
43 #include "smu7_smumgr.h"
45 #include "smu7_dyn_defaults.h"
47 #include "smu7_hwmgr.h"
48 #include "hardwaremanager.h"
50 #include "pppcielanes.h"
52 #include "dce/dce_10_0_d.h"
53 #include "dce/dce_10_0_sh_mask.h"
55 #define POLARIS10_SMC_SIZE 0x20000
56 #define POWERTUNE_DEFAULT_SET_MAX 1
57 #define VDDC_VDDCI_DELTA 200
58 #define MC_CG_ARB_FREQ_F1 0x0b
60 static const struct polaris10_pt_defaults polaris10_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = {
61 /* sviLoadLIneEn, SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt,
62 * TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac, BAPM_TEMP_GRADIENT */
63 { 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
64 { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61},
65 { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 } },
68 static const sclkFcwRange_t Range_Table[NUM_SCLK_RANGE] = {
69 {VCO_2_4, POSTDIV_DIV_BY_16, 75, 160, 112},
70 {VCO_3_6, POSTDIV_DIV_BY_16, 112, 224, 160},
71 {VCO_2_4, POSTDIV_DIV_BY_8, 75, 160, 112},
72 {VCO_3_6, POSTDIV_DIV_BY_8, 112, 224, 160},
73 {VCO_2_4, POSTDIV_DIV_BY_4, 75, 160, 112},
74 {VCO_3_6, POSTDIV_DIV_BY_4, 112, 216, 160},
75 {VCO_2_4, POSTDIV_DIV_BY_2, 75, 160, 108},
76 {VCO_3_6, POSTDIV_DIV_BY_2, 112, 216, 160} };
78 #define PPPOLARIS10_TARGETACTIVITY_DFLT 50
80 static const SMU74_Discrete_GraphicsLevel avfs_graphics_level_polaris10[8] = {
81 /* Min pcie DeepSleep Activity CgSpll CgSpll CcPwr CcPwr Sclk Enabled Enabled Voltage Power */
82 /* Voltage, DpmLevel, DivId, Level, FuncCntl3, FuncCntl4, DynRm, DynRm1 Did, Padding,ForActivity, ForThrottle, UpHyst, DownHyst, DownHyst, Throttle */
83 { 0x100ea446, 0x00, 0x03, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x30750000, 0x3000, 0, 0x2600, 0, 0, 0x0004, 0x8f02, 0xffff, 0x2f00, 0x300e, 0x2700 } },
84 { 0x400ea446, 0x01, 0x04, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x409c0000, 0x2000, 0, 0x1e00, 1, 1, 0x0004, 0x8300, 0xffff, 0x1f00, 0xcb5e, 0x1a00 } },
85 { 0x740ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x50c30000, 0x2800, 0, 0x2000, 1, 1, 0x0004, 0x0c02, 0xffff, 0x2700, 0x6433, 0x2100 } },
86 { 0xa40ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x60ea0000, 0x3000, 0, 0x2600, 1, 1, 0x0004, 0x8f02, 0xffff, 0x2f00, 0x300e, 0x2700 } },
87 { 0xd80ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x70110100, 0x3800, 0, 0x2c00, 1, 1, 0x0004, 0x1203, 0xffff, 0x3600, 0xc9e2, 0x2e00 } },
88 { 0x3c0fa446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x80380100, 0x2000, 0, 0x1e00, 2, 1, 0x0004, 0x8300, 0xffff, 0x1f00, 0xcb5e, 0x1a00 } },
89 { 0x6c0fa446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x905f0100, 0x2400, 0, 0x1e00, 2, 1, 0x0004, 0x8901, 0xffff, 0x2300, 0x314c, 0x1d00 } },
90 { 0xa00fa446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0xa0860100, 0x2800, 0, 0x2000, 2, 1, 0x0004, 0x0c02, 0xffff, 0x2700, 0x6433, 0x2100 } }
93 static const SMU74_Discrete_MemoryLevel avfs_memory_level_polaris10 = {
94 0x100ea446, 0, 0x30750000, 0x01, 0x01, 0x01, 0x00, 0x00, 0x64, 0x00, 0x00, 0x1f00, 0x00, 0x00};
96 static int polaris10_perform_btc(struct pp_hwmgr *hwmgr)
99 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
101 if (0 != smu_data->avfs_btc_param) {
102 if (0 != smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_PerformBtc, smu_data->avfs_btc_param,
104 pr_info("[AVFS][SmuPolaris10_PerformBtc] PerformBTC SMU msg failed");
108 if (smu_data->avfs_btc_param > 1) {
109 /* Soft-Reset to reset the engine before loading uCode */
111 cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, 0x50000000);
112 /* reset everything */
113 cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0xffffffff);
114 cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0);
120 static int polaris10_setup_graphics_level_structure(struct pp_hwmgr *hwmgr)
123 uint32_t dpm_table_start;
125 uint16_t u16_boot_mvdd;
126 uint32_t graphics_level_address, vr_config_address, graphics_level_size;
128 graphics_level_size = sizeof(avfs_graphics_level_polaris10);
129 u16_boot_mvdd = PP_HOST_TO_SMC_US(1300 * VOLTAGE_SCALE);
131 PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(hwmgr,
132 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, DpmTable),
133 &dpm_table_start, 0x40000),
134 "[AVFS][Polaris10_SetupGfxLvlStruct] SMU could not communicate starting address of DPM table",
137 /* Default value for VRConfig = VR_MERGED_WITH_VDDC + VR_STATIC_VOLTAGE(VDDCI) */
138 vr_config = 0x01000500; /* Real value:0x50001 */
140 vr_config_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, VRConfig);
142 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, vr_config_address,
143 (uint8_t *)&vr_config, sizeof(uint32_t), 0x40000),
144 "[AVFS][Polaris10_SetupGfxLvlStruct] Problems copying VRConfig value over to SMC",
147 graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
149 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address,
150 (uint8_t *)(&avfs_graphics_level_polaris10),
151 graphics_level_size, 0x40000),
152 "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of SCLK DPM table failed!",
155 graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
157 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address,
158 (uint8_t *)(&avfs_memory_level_polaris10), sizeof(avfs_memory_level_polaris10), 0x40000),
159 "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of MCLK DPM table failed!",
162 /* MVDD Boot value - neccessary for getting rid of the hang that occurs during Mclk DPM enablement */
164 graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, BootMVdd);
166 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address,
167 (uint8_t *)(&u16_boot_mvdd), sizeof(u16_boot_mvdd), 0x40000),
168 "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of DPM table failed!",
175 static int polaris10_avfs_event_mgr(struct pp_hwmgr *hwmgr)
177 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
179 if (!hwmgr->avfs_supported)
182 PP_ASSERT_WITH_CODE(0 == polaris10_setup_graphics_level_structure(hwmgr),
183 "[AVFS][Polaris10_AVFSEventMgr] Could not Copy Graphics Level table over to SMU",
186 if (smu_data->avfs_btc_param > 1) {
187 pr_info("[AVFS][Polaris10_AVFSEventMgr] AC BTC has not been successfully verified on Fiji. There may be in this setting.");
188 PP_ASSERT_WITH_CODE(0 == smu7_setup_pwr_virus(hwmgr),
189 "[AVFS][Polaris10_AVFSEventMgr] Could not setup Pwr Virus for AVFS ",
193 PP_ASSERT_WITH_CODE(0 == polaris10_perform_btc(hwmgr),
194 "[AVFS][Polaris10_AVFSEventMgr] Failure at SmuPolaris10_PerformBTC. AVFS Disabled",
200 static int polaris10_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr)
204 /* Wait for smc boot up */
205 /* PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0) */
208 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
209 SMC_SYSCON_RESET_CNTL, rst_reg, 1);
211 result = smu7_upload_smu_firmware_image(hwmgr);
216 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMU_STATUS, 0);
218 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
219 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
221 /* De-assert reset */
222 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
223 SMC_SYSCON_RESET_CNTL, rst_reg, 0);
226 PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1);
229 /* Call Test SMU message with 0x20000 offset to trigger SMU start */
230 smu7_send_msg_to_smc_offset(hwmgr);
232 /* Wait done bit to be set */
233 /* Check pass/failed indicator */
235 PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, SMU_STATUS, SMU_DONE, 0);
237 if (1 != PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
238 SMU_STATUS, SMU_PASS))
239 PP_ASSERT_WITH_CODE(false, "SMU Firmware start failed!", return -1);
241 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixFIRMWARE_FLAGS, 0);
243 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
244 SMC_SYSCON_RESET_CNTL, rst_reg, 1);
246 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
247 SMC_SYSCON_RESET_CNTL, rst_reg, 0);
249 /* Wait for firmware to initialize */
250 PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
255 static int polaris10_start_smu_in_non_protection_mode(struct pp_hwmgr *hwmgr)
259 /* wait for smc boot up */
260 PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0);
262 /* Clear firmware interrupt enable flag */
263 /* PHM_WRITE_VFPF_INDIRECT_FIELD(pSmuMgr, SMC_IND, SMC_SYSCON_MISC_CNTL, pre_fetcher_en, 1); */
264 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
265 ixFIRMWARE_FLAGS, 0);
267 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
268 SMC_SYSCON_RESET_CNTL,
271 result = smu7_upload_smu_firmware_image(hwmgr);
275 /* Set smc instruct start point at 0x0 */
276 smu7_program_jump_on_start(hwmgr);
278 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
279 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
281 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
282 SMC_SYSCON_RESET_CNTL, rst_reg, 0);
284 /* Wait for firmware to initialize */
286 PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
287 FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
292 static int polaris10_start_smu(struct pp_hwmgr *hwmgr)
295 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
297 /* Only start SMC if SMC RAM is not running */
298 if (!smu7_is_smc_ram_running(hwmgr) && hwmgr->not_vf) {
299 smu_data->protected_mode = (uint8_t) (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_MODE));
300 smu_data->smu7_data.security_hard_key = (uint8_t) (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_SEL));
302 /* Check if SMU is running in protected mode */
303 if (smu_data->protected_mode == 0)
304 result = polaris10_start_smu_in_non_protection_mode(hwmgr);
306 result = polaris10_start_smu_in_protection_mode(hwmgr);
309 PP_ASSERT_WITH_CODE(0, "Failed to load SMU ucode.", return result);
311 polaris10_avfs_event_mgr(hwmgr);
314 /* Setup SoftRegsStart here for register lookup in case DummyBackEnd is used and ProcessFirmwareHeader is not executed */
315 smu7_read_smc_sram_dword(hwmgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, SoftRegisters),
316 &(smu_data->smu7_data.soft_regs_start), 0x40000);
318 result = smu7_request_smu_load_fw(hwmgr);
323 static bool polaris10_is_hw_avfs_present(struct pp_hwmgr *hwmgr)
327 efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMU_EFUSE_0 + (49*4));
335 static int polaris10_smu_init(struct pp_hwmgr *hwmgr)
337 struct polaris10_smumgr *smu_data;
339 smu_data = kzalloc(sizeof(struct polaris10_smumgr), GFP_KERNEL);
340 if (smu_data == NULL)
343 hwmgr->smu_backend = smu_data;
345 if (smu7_init(hwmgr)) {
353 static int polaris10_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
354 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table,
355 uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
359 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
361 *voltage = *mvdd = 0;
363 /* clock - voltage dependency table is empty table */
364 if (dep_table->count == 0)
367 for (i = 0; i < dep_table->count; i++) {
368 /* find first sclk bigger than request */
369 if (dep_table->entries[i].clk >= clock) {
370 *voltage |= (dep_table->entries[i].vddc *
371 VOLTAGE_SCALE) << VDDC_SHIFT;
372 if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control)
373 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
374 VOLTAGE_SCALE) << VDDCI_SHIFT;
375 else if (dep_table->entries[i].vddci)
376 *voltage |= (dep_table->entries[i].vddci *
377 VOLTAGE_SCALE) << VDDCI_SHIFT;
379 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
380 (dep_table->entries[i].vddc -
381 (uint16_t)VDDC_VDDCI_DELTA));
382 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
385 if (SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control)
386 *mvdd = data->vbios_boot_state.mvdd_bootup_value *
388 else if (dep_table->entries[i].mvdd)
389 *mvdd = (uint32_t) dep_table->entries[i].mvdd *
392 *voltage |= 1 << PHASES_SHIFT;
397 /* sclk is bigger than max sclk in the dependence table */
398 *voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
400 if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control)
401 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
402 VOLTAGE_SCALE) << VDDCI_SHIFT;
403 else if (dep_table->entries[i-1].vddci) {
404 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
405 (dep_table->entries[i].vddc -
406 (uint16_t)VDDC_VDDCI_DELTA));
407 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
410 if (SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control)
411 *mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE;
412 else if (dep_table->entries[i].mvdd)
413 *mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE;
418 static uint16_t scale_fan_gain_settings(uint16_t raw_setting)
421 tmp = raw_setting * 4096 / 100;
422 return (uint16_t)tmp;
425 static int polaris10_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
427 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
429 const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults;
430 SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
431 struct phm_ppt_v1_information *table_info =
432 (struct phm_ppt_v1_information *)(hwmgr->pptable);
433 struct phm_cac_tdp_table *cac_dtp_table = table_info->cac_dtp_table;
434 struct pp_advance_fan_control_parameters *fan_table =
435 &hwmgr->thermal_controller.advanceFanControlParameters;
437 const uint16_t *pdef1;
438 const uint16_t *pdef2;
440 table->DefaultTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 128));
441 table->TargetTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 128));
443 PP_ASSERT_WITH_CODE(cac_dtp_table->usTargetOperatingTemp <= 255,
444 "Target Operating Temp is out of Range!",
447 table->TemperatureLimitEdge = PP_HOST_TO_SMC_US(
448 cac_dtp_table->usTargetOperatingTemp * 256);
449 table->TemperatureLimitHotspot = PP_HOST_TO_SMC_US(
450 cac_dtp_table->usTemperatureLimitHotspot * 256);
451 table->FanGainEdge = PP_HOST_TO_SMC_US(
452 scale_fan_gain_settings(fan_table->usFanGainEdge));
453 table->FanGainHotspot = PP_HOST_TO_SMC_US(
454 scale_fan_gain_settings(fan_table->usFanGainHotspot));
456 pdef1 = defaults->BAPMTI_R;
457 pdef2 = defaults->BAPMTI_RC;
459 for (i = 0; i < SMU74_DTE_ITERATIONS; i++) {
460 for (j = 0; j < SMU74_DTE_SOURCES; j++) {
461 for (k = 0; k < SMU74_DTE_SINKS; k++) {
462 table->BAPMTI_R[i][j][k] = PP_HOST_TO_SMC_US(*pdef1);
463 table->BAPMTI_RC[i][j][k] = PP_HOST_TO_SMC_US(*pdef2);
473 static void polaris10_populate_zero_rpm_parameters(struct pp_hwmgr *hwmgr)
475 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
476 SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
477 uint16_t fan_stop_temp =
478 ((uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucFanStopTemperature) << 8;
479 uint16_t fan_start_temp =
480 ((uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucFanStartTemperature) << 8;
482 if (hwmgr->thermal_controller.advanceFanControlParameters.ucEnableZeroRPM) {
483 table->FanStartTemperature = PP_HOST_TO_SMC_US(fan_start_temp);
484 table->FanStopTemperature = PP_HOST_TO_SMC_US(fan_stop_temp);
488 static int polaris10_populate_svi_load_line(struct pp_hwmgr *hwmgr)
490 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
491 const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults;
493 smu_data->power_tune_table.SviLoadLineEn = defaults->SviLoadLineEn;
494 smu_data->power_tune_table.SviLoadLineVddC = defaults->SviLoadLineVddC;
495 smu_data->power_tune_table.SviLoadLineTrimVddC = 3;
496 smu_data->power_tune_table.SviLoadLineOffsetVddC = 0;
501 static int polaris10_populate_tdc_limit(struct pp_hwmgr *hwmgr)
504 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
505 struct phm_ppt_v1_information *table_info =
506 (struct phm_ppt_v1_information *)(hwmgr->pptable);
507 const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults;
509 tdc_limit = (uint16_t)(table_info->cac_dtp_table->usTDC * 128);
510 smu_data->power_tune_table.TDC_VDDC_PkgLimit =
511 CONVERT_FROM_HOST_TO_SMC_US(tdc_limit);
512 smu_data->power_tune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
513 defaults->TDC_VDDC_ThrottleReleaseLimitPerc;
514 smu_data->power_tune_table.TDC_MAWt = defaults->TDC_MAWt;
519 static int polaris10_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
521 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
522 const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults;
525 if (smu7_read_smc_sram_dword(hwmgr,
527 offsetof(SMU74_Discrete_PmFuses, TdcWaterfallCtl),
528 (uint32_t *)&temp, SMC_RAM_END))
529 PP_ASSERT_WITH_CODE(false,
530 "Attempt to read PmFuses.DW6 (SviLoadLineEn) from SMC Failed!",
533 smu_data->power_tune_table.TdcWaterfallCtl = defaults->TdcWaterfallCtl;
534 smu_data->power_tune_table.LPMLTemperatureMin =
535 (uint8_t)((temp >> 16) & 0xff);
536 smu_data->power_tune_table.LPMLTemperatureMax =
537 (uint8_t)((temp >> 8) & 0xff);
538 smu_data->power_tune_table.Reserved = (uint8_t)(temp & 0xff);
543 static int polaris10_populate_temperature_scaler(struct pp_hwmgr *hwmgr)
546 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
548 /* Currently not used. Set all to zero. */
549 for (i = 0; i < 16; i++)
550 smu_data->power_tune_table.LPMLTemperatureScaler[i] = 0;
555 static int polaris10_populate_fuzzy_fan(struct pp_hwmgr *hwmgr)
557 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
559 /* TO DO move to hwmgr */
560 if ((hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity & (1 << 15))
561 || 0 == hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity)
562 hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity =
563 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultFanOutputSensitivity;
565 smu_data->power_tune_table.FuzzyFan_PwmSetDelta = PP_HOST_TO_SMC_US(
566 hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity);
570 static int polaris10_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
573 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
575 /* Currently not used. Set all to zero. */
576 for (i = 0; i < 16; i++)
577 smu_data->power_tune_table.GnbLPML[i] = 0;
582 static int polaris10_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
584 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
585 struct phm_ppt_v1_information *table_info =
586 (struct phm_ppt_v1_information *)(hwmgr->pptable);
587 uint16_t hi_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd;
588 uint16_t lo_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd;
589 struct phm_cac_tdp_table *cac_table = table_info->cac_dtp_table;
591 hi_sidd = (uint16_t)(cac_table->usHighCACLeakage / 100 * 256);
592 lo_sidd = (uint16_t)(cac_table->usLowCACLeakage / 100 * 256);
594 smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd =
595 CONVERT_FROM_HOST_TO_SMC_US(hi_sidd);
596 smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd =
597 CONVERT_FROM_HOST_TO_SMC_US(lo_sidd);
602 static int polaris10_populate_pm_fuses(struct pp_hwmgr *hwmgr)
604 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
605 uint32_t pm_fuse_table_offset;
607 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
608 PHM_PlatformCaps_PowerContainment)) {
609 if (smu7_read_smc_sram_dword(hwmgr,
610 SMU7_FIRMWARE_HEADER_LOCATION +
611 offsetof(SMU74_Firmware_Header, PmFuseTable),
612 &pm_fuse_table_offset, SMC_RAM_END))
613 PP_ASSERT_WITH_CODE(false,
614 "Attempt to get pm_fuse_table_offset Failed!",
617 if (polaris10_populate_svi_load_line(hwmgr))
618 PP_ASSERT_WITH_CODE(false,
619 "Attempt to populate SviLoadLine Failed!",
622 if (polaris10_populate_tdc_limit(hwmgr))
623 PP_ASSERT_WITH_CODE(false,
624 "Attempt to populate TDCLimit Failed!", return -EINVAL);
626 if (polaris10_populate_dw8(hwmgr, pm_fuse_table_offset))
627 PP_ASSERT_WITH_CODE(false,
628 "Attempt to populate TdcWaterfallCtl, "
629 "LPMLTemperature Min and Max Failed!",
632 if (0 != polaris10_populate_temperature_scaler(hwmgr))
633 PP_ASSERT_WITH_CODE(false,
634 "Attempt to populate LPMLTemperatureScaler Failed!",
637 if (polaris10_populate_fuzzy_fan(hwmgr))
638 PP_ASSERT_WITH_CODE(false,
639 "Attempt to populate Fuzzy Fan Control parameters Failed!",
642 if (polaris10_populate_gnb_lpml(hwmgr))
643 PP_ASSERT_WITH_CODE(false,
644 "Attempt to populate GnbLPML Failed!",
647 if (polaris10_populate_bapm_vddc_base_leakage_sidd(hwmgr))
648 PP_ASSERT_WITH_CODE(false,
649 "Attempt to populate BapmVddCBaseLeakage Hi and Lo "
650 "Sidd Failed!", return -EINVAL);
652 if (smu7_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset,
653 (uint8_t *)&smu_data->power_tune_table,
654 (sizeof(struct SMU74_Discrete_PmFuses) - 92), SMC_RAM_END))
655 PP_ASSERT_WITH_CODE(false,
656 "Attempt to download PmFuseTable Failed!",
662 static int polaris10_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
663 SMU74_Discrete_DpmTable *table)
665 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
666 uint32_t count, level;
668 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
669 count = data->mvdd_voltage_table.count;
670 if (count > SMU_MAX_SMIO_LEVELS)
671 count = SMU_MAX_SMIO_LEVELS;
672 for (level = 0; level < count; level++) {
673 table->SmioTable2.Pattern[level].Voltage =
674 PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[level].value * VOLTAGE_SCALE);
675 /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/
676 table->SmioTable2.Pattern[level].Smio =
678 table->Smio[level] |=
679 data->mvdd_voltage_table.entries[level].smio_low;
681 table->SmioMask2 = data->mvdd_voltage_table.mask_low;
683 table->MvddLevelCount = (uint32_t) PP_HOST_TO_SMC_UL(count);
689 static int polaris10_populate_smc_vddc_table(struct pp_hwmgr *hwmgr,
690 struct SMU74_Discrete_DpmTable *table)
692 uint32_t count, level;
693 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
695 count = data->vddc_voltage_table.count;
697 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->voltage_control) {
698 if (count > SMU_MAX_SMIO_LEVELS)
699 count = SMU_MAX_SMIO_LEVELS;
700 for (level = 0; level < count; ++level) {
701 table->SmioTable1.Pattern[level].Voltage =
702 PP_HOST_TO_SMC_US(data->vddc_voltage_table.entries[level].value * VOLTAGE_SCALE);
703 table->SmioTable1.Pattern[level].Smio = (uint8_t) level;
705 table->Smio[level] |= data->vddc_voltage_table.entries[level].smio_low;
708 table->SmioMask1 = data->vddc_voltage_table.mask_low;
714 static int polaris10_populate_smc_vddci_table(struct pp_hwmgr *hwmgr,
715 struct SMU74_Discrete_DpmTable *table)
717 uint32_t count, level;
718 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
720 count = data->vddci_voltage_table.count;
722 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
723 if (count > SMU_MAX_SMIO_LEVELS)
724 count = SMU_MAX_SMIO_LEVELS;
725 for (level = 0; level < count; ++level) {
726 table->SmioTable1.Pattern[level].Voltage =
727 PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[level].value * VOLTAGE_SCALE);
728 table->SmioTable1.Pattern[level].Smio = (uint8_t) level;
730 table->Smio[level] |= data->vddci_voltage_table.entries[level].smio_low;
733 table->SmioMask1 = data->vddci_voltage_table.mask_low;
739 static int polaris10_populate_cac_table(struct pp_hwmgr *hwmgr,
740 struct SMU74_Discrete_DpmTable *table)
744 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
745 struct phm_ppt_v1_information *table_info =
746 (struct phm_ppt_v1_information *)(hwmgr->pptable);
747 struct phm_ppt_v1_voltage_lookup_table *lookup_table =
748 table_info->vddc_lookup_table;
749 /* tables is already swapped, so in order to use the value from it,
750 * we need to swap it back.
751 * We are populating vddc CAC data to BapmVddc table
752 * in split and merged mode
754 for (count = 0; count < lookup_table->count; count++) {
755 index = phm_get_voltage_index(lookup_table,
756 data->vddc_voltage_table.entries[count].value);
757 table->BapmVddcVidLoSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_low);
758 table->BapmVddcVidHiSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_mid);
759 table->BapmVddcVidHiSidd2[count] = convert_to_vid(lookup_table->entries[index].us_cac_high);
765 static int polaris10_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
766 struct SMU74_Discrete_DpmTable *table)
768 polaris10_populate_smc_vddc_table(hwmgr, table);
769 polaris10_populate_smc_vddci_table(hwmgr, table);
770 polaris10_populate_smc_mvdd_table(hwmgr, table);
771 polaris10_populate_cac_table(hwmgr, table);
776 static int polaris10_populate_ulv_level(struct pp_hwmgr *hwmgr,
777 struct SMU74_Discrete_Ulv *state)
779 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
780 struct phm_ppt_v1_information *table_info =
781 (struct phm_ppt_v1_information *)(hwmgr->pptable);
782 struct amdgpu_device *adev = hwmgr->adev;
784 state->CcPwrDynRm = 0;
785 state->CcPwrDynRm1 = 0;
787 state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
788 state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *
789 VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
791 if ((hwmgr->chip_id == CHIP_POLARIS12) ||
792 ASICID_IS_P20(adev->pdev->device, adev->pdev->revision) ||
793 ASICID_IS_P21(adev->pdev->device, adev->pdev->revision) ||
794 ASICID_IS_P30(adev->pdev->device, adev->pdev->revision) ||
795 ASICID_IS_P31(adev->pdev->device, adev->pdev->revision))
796 state->VddcPhase = data->vddc_phase_shed_control ^ 0x3;
798 state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1;
800 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
801 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
802 CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
807 static int polaris10_populate_ulv_state(struct pp_hwmgr *hwmgr,
808 struct SMU74_Discrete_DpmTable *table)
810 return polaris10_populate_ulv_level(hwmgr, &table->Ulv);
813 static int polaris10_populate_smc_link_level(struct pp_hwmgr *hwmgr,
814 struct SMU74_Discrete_DpmTable *table)
816 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
817 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
818 struct smu7_dpm_table *dpm_table = &data->dpm_table;
821 /* Index (dpm_table->pcie_speed_table.count)
822 * is reserved for PCIE boot level. */
823 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
824 table->LinkLevel[i].PcieGenSpeed =
825 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
826 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
827 dpm_table->pcie_speed_table.dpm_levels[i].param1);
828 table->LinkLevel[i].EnabledForActivity = 1;
829 table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
830 table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
831 table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
834 smu_data->smc_state_table.LinkLevelCount =
835 (uint8_t)dpm_table->pcie_speed_table.count;
837 /* To Do move to hwmgr */
838 data->dpm_level_enable_mask.pcie_dpm_enable_mask =
839 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
845 static void polaris10_get_sclk_range_table(struct pp_hwmgr *hwmgr,
846 SMU74_Discrete_DpmTable *table)
848 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
851 struct pp_atom_ctrl_sclk_range_table range_table_from_vbios = { { {0} } };
853 ref_clk = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
855 if (0 == atomctrl_get_smc_sclk_range_table(hwmgr, &range_table_from_vbios)) {
856 for (i = 0; i < NUM_SCLK_RANGE; i++) {
857 table->SclkFcwRangeTable[i].vco_setting = range_table_from_vbios.entry[i].ucVco_setting;
858 table->SclkFcwRangeTable[i].postdiv = range_table_from_vbios.entry[i].ucPostdiv;
859 table->SclkFcwRangeTable[i].fcw_pcc = range_table_from_vbios.entry[i].usFcw_pcc;
861 table->SclkFcwRangeTable[i].fcw_trans_upper = range_table_from_vbios.entry[i].usFcw_trans_upper;
862 table->SclkFcwRangeTable[i].fcw_trans_lower = range_table_from_vbios.entry[i].usRcw_trans_lower;
864 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
865 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
866 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
871 for (i = 0; i < NUM_SCLK_RANGE; i++) {
872 smu_data->range_table[i].trans_lower_frequency = (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv;
873 smu_data->range_table[i].trans_upper_frequency = (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv;
875 table->SclkFcwRangeTable[i].vco_setting = Range_Table[i].vco_setting;
876 table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv;
877 table->SclkFcwRangeTable[i].fcw_pcc = Range_Table[i].fcw_pcc;
879 table->SclkFcwRangeTable[i].fcw_trans_upper = Range_Table[i].fcw_trans_upper;
880 table->SclkFcwRangeTable[i].fcw_trans_lower = Range_Table[i].fcw_trans_lower;
882 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
883 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
884 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
888 static int polaris10_calculate_sclk_params(struct pp_hwmgr *hwmgr,
889 uint32_t clock, SMU_SclkSetting *sclk_setting)
891 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
892 const SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
893 struct pp_atomctrl_clock_dividers_ai dividers;
895 uint32_t pcc_target_percent, pcc_target_freq, ss_target_percent, ss_target_freq;
900 sclk_setting->SclkFrequency = clock;
901 /* get the engine clock dividers for this clock value */
902 result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock, ÷rs);
904 sclk_setting->Fcw_int = dividers.usSclk_fcw_int;
905 sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac;
906 sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int;
907 sclk_setting->PllRange = dividers.ucSclkPllRange;
908 sclk_setting->Sclk_slew_rate = 0x400;
909 sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac;
910 sclk_setting->Pcc_down_slew_rate = 0xffff;
911 sclk_setting->SSc_En = dividers.ucSscEnable;
912 sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int;
913 sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac;
914 sclk_setting->Sclk_ss_slew_rate = dividers.usSsc_fcw_slew_frac;
918 ref_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
920 for (i = 0; i < NUM_SCLK_RANGE; i++) {
921 if (clock > smu_data->range_table[i].trans_lower_frequency
922 && clock <= smu_data->range_table[i].trans_upper_frequency) {
923 sclk_setting->PllRange = i;
928 sclk_setting->Fcw_int = (uint16_t)((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
929 temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
931 do_div(temp, ref_clock);
932 sclk_setting->Fcw_frac = temp & 0xffff;
934 pcc_target_percent = 10; /* Hardcode 10% for now. */
935 pcc_target_freq = clock - (clock * pcc_target_percent / 100);
936 sclk_setting->Pcc_fcw_int = (uint16_t)((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
938 ss_target_percent = 2; /* Hardcode 2% for now. */
939 sclk_setting->SSc_En = 0;
940 if (ss_target_percent) {
941 sclk_setting->SSc_En = 1;
942 ss_target_freq = clock - (clock * ss_target_percent / 100);
943 sclk_setting->Fcw1_int = (uint16_t)((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
944 temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
946 do_div(temp, ref_clock);
947 sclk_setting->Fcw1_frac = temp & 0xffff;
953 static int polaris10_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
954 uint32_t clock, struct SMU74_Discrete_GraphicsLevel *level)
957 /* PP_Clocks minClocks; */
959 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
960 struct phm_ppt_v1_information *table_info =
961 (struct phm_ppt_v1_information *)(hwmgr->pptable);
962 SMU_SclkSetting curr_sclk_setting = { 0 };
963 phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table = NULL;
965 result = polaris10_calculate_sclk_params(hwmgr, clock, &curr_sclk_setting);
967 if (hwmgr->od_enabled)
968 vdd_dep_table = (phm_ppt_v1_clock_voltage_dependency_table *)&data->odn_dpm_table.vdd_dependency_on_sclk;
970 vdd_dep_table = table_info->vdd_dep_on_sclk;
972 /* populate graphics levels */
973 result = polaris10_get_dependency_volt_by_clk(hwmgr,
974 vdd_dep_table, clock,
975 &level->MinVoltage, &mvdd);
977 PP_ASSERT_WITH_CODE((0 == result),
978 "can not find VDDC voltage value for "
979 "VDDC engine clock dependency table",
981 level->ActivityLevel = data->current_profile_setting.sclk_activity;
983 level->CcPwrDynRm = 0;
984 level->CcPwrDynRm1 = 0;
985 level->EnabledForActivity = 0;
986 level->EnabledForThrottle = 1;
987 level->UpHyst = data->current_profile_setting.sclk_up_hyst;
988 level->DownHyst = data->current_profile_setting.sclk_down_hyst;
989 level->VoltageDownHyst = 0;
990 level->PowerThrottle = 0;
991 data->display_timing.min_clock_in_sr = hwmgr->display_config->min_core_set_clock_in_sr;
993 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
994 level->DeepSleepDivId = smu7_get_sleep_divider_id_from_clock(clock,
995 hwmgr->display_config->min_core_set_clock_in_sr);
997 /* Default to slow, highest DPM level will be
998 * set to PPSMC_DISPLAY_WATERMARK_LOW later.
1000 if (data->update_up_hyst)
1001 level->UpHyst = (uint8_t)data->up_hyst;
1002 if (data->update_down_hyst)
1003 level->DownHyst = (uint8_t)data->down_hyst;
1005 level->SclkSetting = curr_sclk_setting;
1007 CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage);
1008 CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm);
1009 CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1);
1010 CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel);
1011 CONVERT_FROM_HOST_TO_SMC_UL(level->SclkSetting.SclkFrequency);
1012 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_int);
1013 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_frac);
1014 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_fcw_int);
1015 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_slew_rate);
1016 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_up_slew_rate);
1017 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_down_slew_rate);
1018 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_int);
1019 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_frac);
1020 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_ss_slew_rate);
1024 static void polaris10_get_vddc_shared_railinfo(struct pp_hwmgr *hwmgr)
1026 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1027 SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
1028 uint8_t shared_rail;
1030 if (!atomctrl_get_vddc_shared_railinfo(hwmgr, &shared_rail))
1031 table->SharedRails = shared_rail;
1034 static int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
1036 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1037 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1038 struct smu7_dpm_table *dpm_table = &hw_data->dpm_table;
1039 struct phm_ppt_v1_information *table_info =
1040 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1041 struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
1042 uint8_t pcie_entry_cnt = (uint8_t) hw_data->dpm_table.pcie_speed_table.count;
1044 uint32_t array = smu_data->smu7_data.dpm_table_start +
1045 offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
1046 uint32_t array_size = sizeof(struct SMU74_Discrete_GraphicsLevel) *
1047 SMU74_MAX_LEVELS_GRAPHICS;
1048 struct SMU74_Discrete_GraphicsLevel *levels =
1049 smu_data->smc_state_table.GraphicsLevel;
1050 uint32_t i, max_entry;
1051 uint8_t hightest_pcie_level_enabled = 0,
1052 lowest_pcie_level_enabled = 0,
1053 mid_pcie_level_enabled = 0,
1055 struct amdgpu_device *adev = hwmgr->adev;
1056 pp_atomctrl_clock_dividers_vi dividers;
1057 uint32_t dpm0_sclkfrequency = levels[0].SclkSetting.SclkFrequency;
1059 if (ASICID_IS_P20(adev->pdev->device, adev->pdev->revision) ||
1060 ASICID_IS_P30(adev->pdev->device, adev->pdev->revision))
1061 polaris10_get_vddc_shared_railinfo(hwmgr);
1063 polaris10_get_sclk_range_table(hwmgr, &(smu_data->smc_state_table));
1065 for (i = 0; i < dpm_table->sclk_table.count; i++) {
1067 result = polaris10_populate_single_graphic_level(hwmgr,
1068 dpm_table->sclk_table.dpm_levels[i].value,
1069 &(smu_data->smc_state_table.GraphicsLevel[i]));
1073 /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
1075 levels[i].DeepSleepDivId = 0;
1077 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1078 PHM_PlatformCaps_SPLLShutdownSupport)) {
1079 smu_data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0;
1080 if (dpm0_sclkfrequency != levels[0].SclkSetting.SclkFrequency) {
1081 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1082 dpm_table->sclk_table.dpm_levels[0].value,
1084 PP_ASSERT_WITH_CODE((0 == result),
1085 "can not find divide id for sclk",
1087 smum_send_msg_to_smc_with_parameter(hwmgr,
1088 PPSMC_MSG_SetGpuPllDfsForSclk,
1089 dividers.real_clock < dpm_table->sclk_table.dpm_levels[0].value ?
1090 dividers.pll_post_divider - 1 : dividers.pll_post_divider,
1095 smu_data->smc_state_table.GraphicsDpmLevelCount =
1096 (uint8_t)dpm_table->sclk_table.count;
1097 hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask =
1098 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
1100 for (i = 0; i < smu_data->smc_state_table.GraphicsDpmLevelCount; i++)
1101 smu_data->smc_state_table.GraphicsLevel[i].EnabledForActivity =
1102 (hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask & (1 << i)) >> i;
1104 if (pcie_table != NULL) {
1105 PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),
1106 "There must be 1 or more PCIE levels defined in PPTable.",
1108 max_entry = pcie_entry_cnt - 1;
1109 for (i = 0; i < dpm_table->sclk_table.count; i++)
1110 levels[i].pcieDpmLevel =
1111 (uint8_t) ((i < max_entry) ? i : max_entry);
1113 while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1114 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1115 (1 << (hightest_pcie_level_enabled + 1))) != 0))
1116 hightest_pcie_level_enabled++;
1118 while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1119 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1120 (1 << lowest_pcie_level_enabled)) == 0))
1121 lowest_pcie_level_enabled++;
1123 while ((count < hightest_pcie_level_enabled) &&
1124 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1125 (1 << (lowest_pcie_level_enabled + 1 + count))) == 0))
1128 mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1 + count) <
1129 hightest_pcie_level_enabled ?
1130 (lowest_pcie_level_enabled + 1 + count) :
1131 hightest_pcie_level_enabled;
1133 /* set pcieDpmLevel to hightest_pcie_level_enabled */
1134 for (i = 2; i < dpm_table->sclk_table.count; i++)
1135 levels[i].pcieDpmLevel = hightest_pcie_level_enabled;
1137 /* set pcieDpmLevel to lowest_pcie_level_enabled */
1138 levels[0].pcieDpmLevel = lowest_pcie_level_enabled;
1140 /* set pcieDpmLevel to mid_pcie_level_enabled */
1141 levels[1].pcieDpmLevel = mid_pcie_level_enabled;
1143 /* level count will send to smc once at init smc table and never change */
1144 result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
1145 (uint32_t)array_size, SMC_RAM_END);
1151 static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
1152 uint32_t clock, struct SMU74_Discrete_MemoryLevel *mem_level)
1154 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1155 struct phm_ppt_v1_information *table_info =
1156 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1158 uint32_t mclk_stutter_mode_threshold = 40000;
1159 phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table = NULL;
1162 if (hwmgr->od_enabled)
1163 vdd_dep_table = (phm_ppt_v1_clock_voltage_dependency_table *)&data->odn_dpm_table.vdd_dependency_on_mclk;
1165 vdd_dep_table = table_info->vdd_dep_on_mclk;
1167 if (vdd_dep_table) {
1168 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1169 vdd_dep_table, clock,
1170 &mem_level->MinVoltage, &mem_level->MinMvdd);
1171 PP_ASSERT_WITH_CODE((0 == result),
1172 "can not find MinVddc voltage value from memory "
1173 "VDDC voltage dependency table", return result);
1176 mem_level->MclkFrequency = clock;
1177 mem_level->EnabledForThrottle = 1;
1178 mem_level->EnabledForActivity = 0;
1179 mem_level->UpHyst = data->current_profile_setting.mclk_up_hyst;
1180 mem_level->DownHyst = data->current_profile_setting.mclk_down_hyst;
1181 mem_level->VoltageDownHyst = 0;
1182 mem_level->ActivityLevel = data->current_profile_setting.mclk_activity;
1183 mem_level->StutterEnable = false;
1184 mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1186 data->display_timing.num_existing_displays = hwmgr->display_config->num_display;
1187 data->display_timing.vrefresh = hwmgr->display_config->vrefresh;
1189 if (mclk_stutter_mode_threshold &&
1190 (clock <= mclk_stutter_mode_threshold) &&
1191 (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
1192 STUTTER_ENABLE) & 0x1) &&
1193 (data->display_timing.num_existing_displays <= 2) &&
1194 data->display_timing.num_existing_displays)
1195 mem_level->StutterEnable = true;
1198 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd);
1199 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency);
1200 CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel);
1201 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage);
1206 static int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1208 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1209 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1210 struct smu7_dpm_table *dpm_table = &hw_data->dpm_table;
1212 /* populate MCLK dpm table to SMU7 */
1213 uint32_t array = smu_data->smu7_data.dpm_table_start +
1214 offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
1215 uint32_t array_size = sizeof(SMU74_Discrete_MemoryLevel) *
1216 SMU74_MAX_LEVELS_MEMORY;
1217 struct SMU74_Discrete_MemoryLevel *levels =
1218 smu_data->smc_state_table.MemoryLevel;
1221 for (i = 0; i < dpm_table->mclk_table.count; i++) {
1222 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
1223 "can not populate memory level as memory clock is zero",
1225 result = polaris10_populate_single_memory_level(hwmgr,
1226 dpm_table->mclk_table.dpm_levels[i].value,
1228 if (i == dpm_table->mclk_table.count - 1)
1229 levels[i].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
1234 smu_data->smc_state_table.MemoryDpmLevelCount =
1235 (uint8_t)dpm_table->mclk_table.count;
1236 hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask =
1237 phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
1239 for (i = 0; i < smu_data->smc_state_table.MemoryDpmLevelCount; i++)
1240 smu_data->smc_state_table.MemoryLevel[i].EnabledForActivity =
1241 (hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask & (1 << i)) >> i;
1243 /* level count will send to smc once at init smc table and never change */
1244 result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
1245 (uint32_t)array_size, SMC_RAM_END);
1250 static int polaris10_populate_mvdd_value(struct pp_hwmgr *hwmgr,
1251 uint32_t mclk, SMIO_Pattern *smio_pat)
1253 const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1254 struct phm_ppt_v1_information *table_info =
1255 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1258 if (SMU7_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
1259 /* find mvdd value which clock is more than request */
1260 for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
1261 if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
1262 smio_pat->Voltage = data->mvdd_voltage_table.entries[i].value;
1266 PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
1267 "MVDD Voltage is outside the supported range.",
1275 static int polaris10_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
1276 SMU74_Discrete_DpmTable *table)
1279 uint32_t sclk_frequency;
1280 const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1281 struct phm_ppt_v1_information *table_info =
1282 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1283 SMIO_Pattern vol_level;
1286 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
1288 /* Get MinVoltage and Frequency from DPM0,
1289 * already converted to SMC_UL */
1290 sclk_frequency = data->vbios_boot_state.sclk_bootup_value;
1291 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1292 table_info->vdd_dep_on_sclk,
1294 &table->ACPILevel.MinVoltage, &mvdd);
1295 PP_ASSERT_WITH_CODE((0 == result),
1296 "Cannot find ACPI VDDC voltage value "
1297 "in Clock Dependency Table",
1300 result = polaris10_calculate_sclk_params(hwmgr, sclk_frequency, &(table->ACPILevel.SclkSetting));
1301 PP_ASSERT_WITH_CODE(result == 0, "Error retrieving Engine Clock dividers from VBIOS.", return result);
1303 table->ACPILevel.DeepSleepDivId = 0;
1304 table->ACPILevel.CcPwrDynRm = 0;
1305 table->ACPILevel.CcPwrDynRm1 = 0;
1307 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
1308 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);
1309 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
1310 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
1312 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkSetting.SclkFrequency);
1313 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_int);
1314 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_frac);
1315 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_fcw_int);
1316 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_slew_rate);
1317 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_up_slew_rate);
1318 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_down_slew_rate);
1319 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_int);
1320 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_frac);
1321 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_ss_slew_rate);
1324 /* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */
1325 table->MemoryACPILevel.MclkFrequency = data->vbios_boot_state.mclk_bootup_value;
1326 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1327 table_info->vdd_dep_on_mclk,
1328 table->MemoryACPILevel.MclkFrequency,
1329 &table->MemoryACPILevel.MinVoltage, &mvdd);
1330 PP_ASSERT_WITH_CODE((0 == result),
1331 "Cannot find ACPI VDDCI voltage value "
1332 "in Clock Dependency Table",
1335 if (!((SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control) ||
1336 (data->mclk_dpm_key_disabled)))
1337 polaris10_populate_mvdd_value(hwmgr,
1338 data->dpm_table.mclk_table.dpm_levels[0].value,
1341 if (0 == polaris10_populate_mvdd_value(hwmgr, 0, &vol_level))
1342 table->MemoryACPILevel.MinMvdd = PP_HOST_TO_SMC_UL(vol_level.Voltage);
1344 table->MemoryACPILevel.MinMvdd = 0;
1346 table->MemoryACPILevel.StutterEnable = false;
1348 table->MemoryACPILevel.EnabledForThrottle = 0;
1349 table->MemoryACPILevel.EnabledForActivity = 0;
1350 table->MemoryACPILevel.UpHyst = 0;
1351 table->MemoryACPILevel.DownHyst = 100;
1352 table->MemoryACPILevel.VoltageDownHyst = 0;
1353 /* To align with the settings from other OSes */
1354 table->MemoryACPILevel.ActivityLevel =
1355 PP_HOST_TO_SMC_US(data->current_profile_setting.sclk_activity);
1357 CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
1358 CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);
1363 static int polaris10_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
1364 SMU74_Discrete_DpmTable *table)
1366 int result = -EINVAL;
1368 struct pp_atomctrl_clock_dividers_vi dividers;
1369 struct phm_ppt_v1_information *table_info =
1370 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1371 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1372 table_info->mm_dep_table;
1373 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1376 table->VceLevelCount = (uint8_t)(mm_table->count);
1377 table->VceBootLevel = 0;
1379 for (count = 0; count < table->VceLevelCount; count++) {
1380 table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
1381 table->VceLevel[count].MinVoltage = 0;
1382 table->VceLevel[count].MinVoltage |=
1383 (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1385 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
1386 vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
1387 mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
1388 else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
1389 vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
1391 vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
1394 table->VceLevel[count].MinVoltage |=
1395 (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1396 table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1398 /*retrieve divider value for VBIOS */
1399 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1400 table->VceLevel[count].Frequency, ÷rs);
1401 PP_ASSERT_WITH_CODE((0 == result),
1402 "can not find divide id for VCE engine clock",
1405 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1407 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
1408 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);
1413 static int polaris10_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
1414 SMU74_Discrete_DpmTable *table)
1416 int result = -EINVAL;
1418 struct pp_atomctrl_clock_dividers_vi dividers;
1419 struct phm_ppt_v1_information *table_info =
1420 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1421 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1422 table_info->mm_dep_table;
1423 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1426 table->SamuLevelCount = (uint8_t)(mm_table->count);
1427 table->SamuBootLevel = 0;
1429 for (count = 0; count < table->SamuLevelCount; count++) {
1430 table->SamuLevel[count].Frequency = mm_table->entries[count].samclock;
1431 table->SamuLevel[count].MinVoltage |=
1432 (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1434 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
1435 vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
1436 mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
1437 else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
1438 vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
1440 vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
1443 table->SamuLevel[count].MinVoltage |=
1444 (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1445 table->SamuLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1447 /*retrieve divider value for VBIOS */
1448 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1449 table->SamuLevel[count].Frequency, ÷rs);
1450 PP_ASSERT_WITH_CODE((0 == result),
1451 "can not find divide id for VCE engine clock",
1454 table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1456 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
1457 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].MinVoltage);
1462 static int polaris10_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
1463 int32_t eng_clock, int32_t mem_clock,
1464 SMU74_Discrete_MCArbDramTimingTableEntry *arb_regs)
1466 uint32_t dram_timing;
1467 uint32_t dram_timing2;
1468 uint32_t burst_time;
1471 result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
1472 eng_clock, mem_clock);
1473 PP_ASSERT_WITH_CODE(result == 0,
1474 "Error calling VBIOS to set DRAM_TIMING.", return result);
1476 dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
1477 dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
1478 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
1481 arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dram_timing);
1482 arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);
1483 arb_regs->McArbBurstTime = (uint8_t)burst_time;
1488 static int polaris10_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
1490 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1491 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1492 struct SMU74_Discrete_MCArbDramTimingTable arb_regs;
1496 for (i = 0; i < hw_data->dpm_table.sclk_table.count; i++) {
1497 for (j = 0; j < hw_data->dpm_table.mclk_table.count; j++) {
1498 result = polaris10_populate_memory_timing_parameters(hwmgr,
1499 hw_data->dpm_table.sclk_table.dpm_levels[i].value,
1500 hw_data->dpm_table.mclk_table.dpm_levels[j].value,
1501 &arb_regs.entries[i][j]);
1502 if (result == 0 && i == 0)
1503 result = atomctrl_set_ac_timing_ai(hwmgr, hw_data->dpm_table.mclk_table.dpm_levels[j].value, j);
1509 result = smu7_copy_bytes_to_smc(
1511 smu_data->smu7_data.arb_table_start,
1512 (uint8_t *)&arb_regs,
1513 sizeof(SMU74_Discrete_MCArbDramTimingTable),
1518 static int polaris10_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
1519 struct SMU74_Discrete_DpmTable *table)
1521 int result = -EINVAL;
1523 struct pp_atomctrl_clock_dividers_vi dividers;
1524 struct phm_ppt_v1_information *table_info =
1525 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1526 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1527 table_info->mm_dep_table;
1528 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1531 table->UvdLevelCount = (uint8_t)(mm_table->count);
1532 table->UvdBootLevel = 0;
1534 for (count = 0; count < table->UvdLevelCount; count++) {
1535 table->UvdLevel[count].MinVoltage = 0;
1536 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
1537 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
1538 table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
1539 VOLTAGE_SCALE) << VDDC_SHIFT;
1541 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
1542 vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
1543 mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
1544 else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
1545 vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
1547 vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
1549 table->UvdLevel[count].MinVoltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1550 table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1552 /* retrieve divider value for VBIOS */
1553 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1554 table->UvdLevel[count].VclkFrequency, ÷rs);
1555 PP_ASSERT_WITH_CODE((0 == result),
1556 "can not find divide id for Vclk clock", return result);
1558 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
1560 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1561 table->UvdLevel[count].DclkFrequency, ÷rs);
1562 PP_ASSERT_WITH_CODE((0 == result),
1563 "can not find divide id for Dclk clock", return result);
1565 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
1567 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
1568 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
1569 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);
1575 static int polaris10_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
1576 struct SMU74_Discrete_DpmTable *table)
1579 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1581 table->GraphicsBootLevel = 0;
1582 table->MemoryBootLevel = 0;
1584 /* find boot level from dpm table */
1585 result = phm_find_boot_level(&(data->dpm_table.sclk_table),
1586 data->vbios_boot_state.sclk_bootup_value,
1587 (uint32_t *)&(table->GraphicsBootLevel));
1589 result = phm_find_boot_level(&(data->dpm_table.mclk_table),
1590 data->vbios_boot_state.mclk_bootup_value,
1591 (uint32_t *)&(table->MemoryBootLevel));
1593 table->BootVddc = data->vbios_boot_state.vddc_bootup_value *
1595 table->BootVddci = data->vbios_boot_state.vddci_bootup_value *
1597 table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value *
1600 CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc);
1601 CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci);
1602 CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
1607 static int polaris10_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
1609 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1610 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1611 struct phm_ppt_v1_information *table_info =
1612 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1613 uint8_t count, level;
1615 count = (uint8_t)(table_info->vdd_dep_on_sclk->count);
1617 for (level = 0; level < count; level++) {
1618 if (table_info->vdd_dep_on_sclk->entries[level].clk >=
1619 hw_data->vbios_boot_state.sclk_bootup_value) {
1620 smu_data->smc_state_table.GraphicsBootLevel = level;
1625 count = (uint8_t)(table_info->vdd_dep_on_mclk->count);
1626 for (level = 0; level < count; level++) {
1627 if (table_info->vdd_dep_on_mclk->entries[level].clk >=
1628 hw_data->vbios_boot_state.mclk_bootup_value) {
1629 smu_data->smc_state_table.MemoryBootLevel = level;
1637 #define STRAP_ASIC_RO_LSB 2168
1638 #define STRAP_ASIC_RO_MSB 2175
1640 static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
1642 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1643 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1644 struct phm_ppt_v1_information *table_info =
1645 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1646 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1647 table_info->vdd_dep_on_sclk;
1648 uint32_t ro, efuse, volt_without_cks, volt_with_cks, value;
1649 uint8_t i, stretch_amount, volt_offset = 0;
1651 stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
1653 /* Read SMU_Eefuse to read and calculate RO and determine
1654 * if the part is SS or FF. if RO >= 1660MHz, part is FF.
1656 atomctrl_read_efuse(hwmgr, STRAP_ASIC_RO_LSB, STRAP_ASIC_RO_MSB, &efuse);
1657 ro = ((efuse * (data->ro_range_maximum - data->ro_range_minimum)) / 255) +
1658 data->ro_range_minimum;
1660 /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
1661 for (i = 0; i < sclk_table->count; i++) {
1662 smu_data->smc_state_table.Sclk_CKS_masterEn0_7 |=
1663 sclk_table->entries[i].cks_enable << i;
1664 if (hwmgr->chip_id == CHIP_POLARIS10) {
1665 volt_without_cks = (uint32_t)((2753594000U + (sclk_table->entries[i].clk/100) * 136418 - (ro - 70) * 1000000) / \
1666 (2424180 - (sclk_table->entries[i].clk/100) * 1132925/1000));
1667 volt_with_cks = (uint32_t)((2797202000U + sclk_table->entries[i].clk/100 * 3232 - (ro - 65) * 1000000) / \
1668 (2522480 - sclk_table->entries[i].clk/100 * 115764/100));
1670 volt_without_cks = (uint32_t)((2416794800U + (sclk_table->entries[i].clk/100) * 1476925/10 - (ro - 50) * 1000000) / \
1671 (2625416 - (sclk_table->entries[i].clk/100) * (12586807/10000)));
1672 volt_with_cks = (uint32_t)((2999656000U - sclk_table->entries[i].clk/100 * 392803 - (ro - 44) * 1000000) / \
1673 (3422454 - sclk_table->entries[i].clk/100 * (18886376/10000)));
1676 if (volt_without_cks >= volt_with_cks)
1677 volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
1678 sclk_table->entries[i].cks_voffset) * 100 + 624) / 625);
1680 smu_data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
1683 smu_data->smc_state_table.LdoRefSel = (table_info->cac_dtp_table->ucCKS_LDO_REFSEL != 0) ? table_info->cac_dtp_table->ucCKS_LDO_REFSEL : 5;
1685 /* Populate CKS Lookup Table */
1686 if (stretch_amount == 0 || stretch_amount > 5) {
1687 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1688 PHM_PlatformCaps_ClockStretcher);
1689 PP_ASSERT_WITH_CODE(false,
1690 "Stretch Amount in PPTable not supported",
1694 value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
1695 value &= 0xFFFFFFFE;
1696 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value);
1701 static int polaris10_populate_vr_config(struct pp_hwmgr *hwmgr,
1702 struct SMU74_Discrete_DpmTable *table)
1704 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1705 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1708 config = VR_MERGED_WITH_VDDC;
1709 table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);
1711 /* Set Vddc Voltage Controller */
1712 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1713 config = VR_SVI2_PLANE_1;
1714 table->VRConfig |= config;
1716 PP_ASSERT_WITH_CODE(false,
1717 "VDDC should be on SVI2 control in merged mode!",
1720 /* Set Vddci Voltage Controller */
1721 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
1722 config = VR_SVI2_PLANE_2; /* only in merged mode */
1723 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1724 } else if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
1725 config = VR_SMIO_PATTERN_1;
1726 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1728 config = VR_STATIC_VOLTAGE;
1729 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1731 /* Set Mvdd Voltage Controller */
1732 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
1733 config = VR_SVI2_PLANE_2;
1734 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1735 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, smu_data->smu7_data.soft_regs_start +
1736 offsetof(SMU74_SoftRegisters, AllowMvddSwitch), 0x1);
1738 config = VR_STATIC_VOLTAGE;
1739 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1746 static int polaris10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
1748 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1749 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1750 struct amdgpu_device *adev = hwmgr->adev;
1752 SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
1754 struct pp_atom_ctrl__avfs_parameters avfs_params = {0};
1755 AVFS_meanNsigma_t AVFS_meanNsigma = { {0} };
1756 AVFS_Sclk_Offset_t AVFS_SclkOffset = { {0} };
1759 struct phm_ppt_v1_information *table_info =
1760 (struct phm_ppt_v1_information *)hwmgr->pptable;
1761 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1762 table_info->vdd_dep_on_sclk;
1765 if (!hwmgr->avfs_supported)
1769 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->voltage_control) {
1770 hwmgr->avfs_supported = 0;
1774 result = atomctrl_get_avfs_information(hwmgr, &avfs_params);
1777 if (ASICID_IS_P20(adev->pdev->device, adev->pdev->revision) ||
1778 ((hwmgr->chip_id == CHIP_POLARIS12) && !ASICID_IS_P23(adev->pdev->device, adev->pdev->revision)) ||
1779 ASICID_IS_P21(adev->pdev->device, adev->pdev->revision)) {
1780 avfs_params.ucEnableApplyAVFS_CKS_OFF_Voltage = 1;
1781 if ((adev->pdev->device == 0x67ef && adev->pdev->revision == 0xe5) ||
1782 (adev->pdev->device == 0x67ff && adev->pdev->revision == 0xef)) {
1783 if ((avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0 == 0xEA522DD3) &&
1784 (avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1 == 0x5645A) &&
1785 (avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2 == 0x33F9E) &&
1786 (avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1 == 0xFFFFC5CC) &&
1787 (avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2 == 0x1B1A) &&
1788 (avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b == 0xFFFFFCED)) {
1789 avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0 = 0xF718F1D4;
1790 avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1 = 0x323FD;
1791 avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2 = 0x1E455;
1792 avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1 = 0;
1793 avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2 = 0;
1794 avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b = 0x23;
1796 } else if (hwmgr->chip_id == CHIP_POLARIS12 && !ASICID_IS_P23(adev->pdev->device, adev->pdev->revision)) {
1797 avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0 = 0xF6B024DD;
1798 avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1 = 0x3005E;
1799 avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2 = 0x18A5F;
1800 avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1 = 0x315;
1801 avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2 = 0xFED1;
1802 avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b = 0x3B;
1803 } else if (ASICID_IS_P20(adev->pdev->device, adev->pdev->revision)) {
1804 avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0 = 0xF843B66B;
1805 avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1 = 0x59CB5;
1806 avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2 = 0xFFFF287F;
1807 avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1 = 0;
1808 avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2 = 0xFF23;
1809 avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b = 0x58;
1815 table->BTCGB_VDROOP_TABLE[0].a0 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a0);
1816 table->BTCGB_VDROOP_TABLE[0].a1 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a1);
1817 table->BTCGB_VDROOP_TABLE[0].a2 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a2);
1818 table->BTCGB_VDROOP_TABLE[1].a0 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0);
1819 table->BTCGB_VDROOP_TABLE[1].a1 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1);
1820 table->BTCGB_VDROOP_TABLE[1].a2 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2);
1821 table->AVFSGB_VDROOP_TABLE[0].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_m1);
1822 table->AVFSGB_VDROOP_TABLE[0].m2 = PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSON_m2);
1823 table->AVFSGB_VDROOP_TABLE[0].b = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_b);
1824 table->AVFSGB_VDROOP_TABLE[0].m1_shift = 24;
1825 table->AVFSGB_VDROOP_TABLE[0].m2_shift = 12;
1826 table->AVFSGB_VDROOP_TABLE[1].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1);
1827 table->AVFSGB_VDROOP_TABLE[1].m2 = PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2);
1828 table->AVFSGB_VDROOP_TABLE[1].b = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b);
1829 table->AVFSGB_VDROOP_TABLE[1].m1_shift = 24;
1830 table->AVFSGB_VDROOP_TABLE[1].m2_shift = 12;
1831 table->MaxVoltage = PP_HOST_TO_SMC_US(avfs_params.usMaxVoltage_0_25mv);
1832 AVFS_meanNsigma.Aconstant[0] = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant0);
1833 AVFS_meanNsigma.Aconstant[1] = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant1);
1834 AVFS_meanNsigma.Aconstant[2] = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant2);
1835 AVFS_meanNsigma.DC_tol_sigma = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_DC_tol_sigma);
1836 AVFS_meanNsigma.Platform_mean = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_mean);
1837 AVFS_meanNsigma.PSM_Age_CompFactor = PP_HOST_TO_SMC_US(avfs_params.usPSM_Age_ComFactor);
1838 AVFS_meanNsigma.Platform_sigma = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_sigma);
1840 for (i = 0; i < NUM_VFT_COLUMNS; i++) {
1841 AVFS_meanNsigma.Static_Voltage_Offset[i] = (uint8_t)(sclk_table->entries[i].cks_voffset * 100 / 625);
1842 AVFS_SclkOffset.Sclk_Offset[i] = PP_HOST_TO_SMC_US((uint16_t)(sclk_table->entries[i].sclk_offset) / 100);
1845 result = smu7_read_smc_sram_dword(hwmgr,
1846 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsMeanNSigma),
1849 smu7_copy_bytes_to_smc(hwmgr,
1851 (uint8_t *)&AVFS_meanNsigma,
1852 sizeof(AVFS_meanNsigma_t),
1855 result = smu7_read_smc_sram_dword(hwmgr,
1856 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsSclkOffsetTable),
1858 smu7_copy_bytes_to_smc(hwmgr,
1860 (uint8_t *)&AVFS_SclkOffset,
1861 sizeof(AVFS_Sclk_Offset_t),
1864 data->avfs_vdroop_override_setting = (avfs_params.ucEnableGB_VDROOP_TABLE_CKSON << BTCGB0_Vdroop_Enable_SHIFT) |
1865 (avfs_params.ucEnableGB_VDROOP_TABLE_CKSOFF << BTCGB1_Vdroop_Enable_SHIFT) |
1866 (avfs_params.ucEnableGB_FUSE_TABLE_CKSON << AVFSGB0_Vdroop_Enable_SHIFT) |
1867 (avfs_params.ucEnableGB_FUSE_TABLE_CKSOFF << AVFSGB1_Vdroop_Enable_SHIFT);
1868 data->apply_avfs_cks_off_voltage = (avfs_params.ucEnableApplyAVFS_CKS_OFF_Voltage == 1) ? true : false;
1873 static void polaris10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
1875 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1876 struct phm_ppt_v1_information *table_info =
1877 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1880 table_info->cac_dtp_table->usPowerTuneDataSetID <= POWERTUNE_DEFAULT_SET_MAX &&
1881 table_info->cac_dtp_table->usPowerTuneDataSetID)
1882 smu_data->power_tune_defaults =
1883 &polaris10_power_tune_data_set_array
1884 [table_info->cac_dtp_table->usPowerTuneDataSetID - 1];
1886 smu_data->power_tune_defaults = &polaris10_power_tune_data_set_array[0];
1890 static int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
1893 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1894 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1896 struct phm_ppt_v1_information *table_info =
1897 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1898 struct SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
1900 struct pp_atomctrl_gpio_pin_assignment gpio_pin;
1901 pp_atomctrl_clock_dividers_vi dividers;
1902 struct phm_ppt_v1_gpio_table *gpio_table = table_info->gpio_table;
1904 polaris10_initialize_power_tune_defaults(hwmgr);
1906 if (SMU7_VOLTAGE_CONTROL_NONE != hw_data->voltage_control)
1907 polaris10_populate_smc_voltage_tables(hwmgr, table);
1909 table->SystemFlags = 0;
1910 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1911 PHM_PlatformCaps_AutomaticDCTransition))
1912 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
1914 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1915 PHM_PlatformCaps_StepVddc))
1916 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
1918 if (hw_data->is_memory_gddr5)
1919 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
1921 if (hw_data->ulv_supported && table_info->us_ulv_voltage_offset) {
1922 result = polaris10_populate_ulv_state(hwmgr, table);
1923 PP_ASSERT_WITH_CODE(0 == result,
1924 "Failed to initialize ULV state!", return result);
1925 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1926 ixCG_ULV_PARAMETER, SMU7_CGULVPARAMETER_DFLT);
1929 result = polaris10_populate_smc_link_level(hwmgr, table);
1930 PP_ASSERT_WITH_CODE(0 == result,
1931 "Failed to initialize Link Level!", return result);
1933 result = polaris10_populate_all_graphic_levels(hwmgr);
1934 PP_ASSERT_WITH_CODE(0 == result,
1935 "Failed to initialize Graphics Level!", return result);
1937 result = polaris10_populate_all_memory_levels(hwmgr);
1938 PP_ASSERT_WITH_CODE(0 == result,
1939 "Failed to initialize Memory Level!", return result);
1941 result = polaris10_populate_smc_acpi_level(hwmgr, table);
1942 PP_ASSERT_WITH_CODE(0 == result,
1943 "Failed to initialize ACPI Level!", return result);
1945 result = polaris10_populate_smc_vce_level(hwmgr, table);
1946 PP_ASSERT_WITH_CODE(0 == result,
1947 "Failed to initialize VCE Level!", return result);
1949 result = polaris10_populate_smc_samu_level(hwmgr, table);
1950 PP_ASSERT_WITH_CODE(0 == result,
1951 "Failed to initialize SAMU Level!", return result);
1953 /* Since only the initial state is completely set up at this point
1954 * (the other states are just copies of the boot state) we only
1955 * need to populate the ARB settings for the initial state.
1957 result = polaris10_program_memory_timing_parameters(hwmgr);
1958 PP_ASSERT_WITH_CODE(0 == result,
1959 "Failed to Write ARB settings for the initial state.", return result);
1961 result = polaris10_populate_smc_uvd_level(hwmgr, table);
1962 PP_ASSERT_WITH_CODE(0 == result,
1963 "Failed to initialize UVD Level!", return result);
1965 result = polaris10_populate_smc_boot_level(hwmgr, table);
1966 PP_ASSERT_WITH_CODE(0 == result,
1967 "Failed to initialize Boot Level!", return result);
1969 result = polaris10_populate_smc_initailial_state(hwmgr);
1970 PP_ASSERT_WITH_CODE(0 == result,
1971 "Failed to initialize Boot State!", return result);
1973 result = polaris10_populate_bapm_parameters_in_dpm_table(hwmgr);
1974 PP_ASSERT_WITH_CODE(0 == result,
1975 "Failed to populate BAPM Parameters!", return result);
1977 polaris10_populate_zero_rpm_parameters(hwmgr);
1979 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1980 PHM_PlatformCaps_ClockStretcher)) {
1981 result = polaris10_populate_clock_stretcher_data_table(hwmgr);
1982 PP_ASSERT_WITH_CODE(0 == result,
1983 "Failed to populate Clock Stretcher Data Table!",
1987 result = polaris10_populate_avfs_parameters(hwmgr);
1988 PP_ASSERT_WITH_CODE(0 == result, "Failed to populate AVFS Parameters!", return result;);
1990 table->CurrSclkPllRange = 0xff;
1991 table->GraphicsVoltageChangeEnable = 1;
1992 table->GraphicsThermThrottleEnable = 1;
1993 table->GraphicsInterval = 1;
1994 table->VoltageInterval = 1;
1995 table->ThermalInterval = 1;
1996 table->TemperatureLimitHigh =
1997 table_info->cac_dtp_table->usTargetOperatingTemp *
1998 SMU7_Q88_FORMAT_CONVERSION_UNIT;
1999 table->TemperatureLimitLow =
2000 (table_info->cac_dtp_table->usTargetOperatingTemp - 1) *
2001 SMU7_Q88_FORMAT_CONVERSION_UNIT;
2002 table->MemoryVoltageChangeEnable = 1;
2003 table->MemoryInterval = 1;
2004 table->VoltageResponseTime = 0;
2005 table->PhaseResponseTime = 0;
2006 table->MemoryThermThrottleEnable = 1;
2007 table->PCIeBootLinkLevel = hw_data->dpm_table.pcie_speed_table.count;
2008 table->PCIeGenInterval = 1;
2009 table->VRConfig = 0;
2011 result = polaris10_populate_vr_config(hwmgr, table);
2012 PP_ASSERT_WITH_CODE(0 == result,
2013 "Failed to populate VRConfig setting!", return result);
2014 hw_data->vr_config = table->VRConfig;
2015 table->ThermGpio = 17;
2016 table->SclkStepSize = 0x4000;
2018 if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) {
2019 table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;
2021 table->VRHotLevel = gpio_table->vrhot_triggered_sclk_dpm_index;
2023 table->VRHotGpio = SMU7_UNUSED_GPIO_PIN;
2024 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2025 PHM_PlatformCaps_RegulatorHot);
2028 if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID,
2030 table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift;
2031 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2032 PHM_PlatformCaps_AutomaticDCTransition);
2034 table->AcDcGpio = SMU7_UNUSED_GPIO_PIN;
2035 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2036 PHM_PlatformCaps_AutomaticDCTransition);
2039 /* Thermal Output GPIO */
2040 if (atomctrl_get_pp_assign_pin(hwmgr, THERMAL_INT_OUTPUT_GPIO_PINID,
2042 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2043 PHM_PlatformCaps_ThermalOutGPIO);
2045 table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift;
2047 /* For porlarity read GPIOPAD_A with assigned Gpio pin
2048 * since VBIOS will program this register to set 'inactive state',
2049 * driver can then determine 'active state' from this and
2050 * program SMU with correct polarity
2052 table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A)
2053 & (1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0;
2054 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
2056 /* if required, combine VRHot/PCC with thermal out GPIO */
2057 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_RegulatorHot)
2058 && phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_CombinePCCWithThermalSignal))
2059 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
2061 table->ThermOutGpio = 17;
2062 table->ThermOutPolarity = 1;
2063 table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
2066 /* Populate BIF_SCLK levels into SMC DPM table */
2067 for (i = 0; i <= hw_data->dpm_table.pcie_speed_table.count; i++) {
2068 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, smu_data->bif_sclk_table[i], ÷rs);
2069 PP_ASSERT_WITH_CODE((result == 0), "Can not find DFS divide id for Sclk", return result);
2072 table->Ulv.BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
2074 table->LinkLevel[i-1].BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
2077 for (i = 0; i < SMU74_MAX_ENTRIES_SMIO; i++)
2078 table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
2080 CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
2081 CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
2082 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
2083 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
2084 CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
2085 CONVERT_FROM_HOST_TO_SMC_UL(table->CurrSclkPllRange);
2086 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
2087 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
2088 CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
2089 CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
2091 /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
2092 result = smu7_copy_bytes_to_smc(hwmgr,
2093 smu_data->smu7_data.dpm_table_start +
2094 offsetof(SMU74_Discrete_DpmTable, SystemFlags),
2095 (uint8_t *)&(table->SystemFlags),
2096 sizeof(SMU74_Discrete_DpmTable) - 3 * sizeof(SMU74_PIDController),
2098 PP_ASSERT_WITH_CODE(0 == result,
2099 "Failed to upload dpm data to SMC memory!", return result);
2101 result = polaris10_populate_pm_fuses(hwmgr);
2102 PP_ASSERT_WITH_CODE(0 == result,
2103 "Failed to populate PM fuses to SMC memory!", return result);
2108 static int polaris10_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
2110 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2112 if (data->need_update_smu7_dpm_table &
2113 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
2114 return polaris10_program_memory_timing_parameters(hwmgr);
2119 int polaris10_thermal_avfs_enable(struct pp_hwmgr *hwmgr)
2121 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2123 if (!hwmgr->avfs_supported)
2126 smum_send_msg_to_smc_with_parameter(hwmgr,
2127 PPSMC_MSG_SetGBDroopSettings, data->avfs_vdroop_override_setting,
2130 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableAvfs, NULL);
2132 /* Apply avfs cks-off voltages to avoid the overshoot
2133 * when switching to the highest sclk frequency
2135 if (data->apply_avfs_cks_off_voltage)
2136 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ApplyAvfsCksOffVoltage, NULL);
2141 static int polaris10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
2143 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2144 SMU74_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
2146 uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2;
2147 uint16_t fdo_min, slope1, slope2;
2148 uint32_t reference_clock;
2152 if (hwmgr->thermal_controller.fanInfo.bNoFan) {
2153 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2154 PHM_PlatformCaps_MicrocodeFanControl);
2158 if (smu_data->smu7_data.fan_table_start == 0) {
2159 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2160 PHM_PlatformCaps_MicrocodeFanControl);
2164 duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2165 CG_FDO_CTRL1, FMAX_DUTY100);
2168 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2169 PHM_PlatformCaps_MicrocodeFanControl);
2173 /* use hardware fan control */
2174 if (hwmgr->thermal_controller.use_hw_fan_control)
2177 tmp64 = hwmgr->thermal_controller.advanceFanControlParameters.
2179 do_div(tmp64, 10000);
2180 fdo_min = (uint16_t)tmp64;
2182 t_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usTMed -
2183 hwmgr->thermal_controller.advanceFanControlParameters.usTMin;
2184 t_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usTHigh -
2185 hwmgr->thermal_controller.advanceFanControlParameters.usTMed;
2187 pwm_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed -
2188 hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin;
2189 pwm_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh -
2190 hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed;
2192 slope1 = (uint16_t)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
2193 slope2 = (uint16_t)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
2195 fan_table.TempMin = cpu_to_be16((50 + hwmgr->
2196 thermal_controller.advanceFanControlParameters.usTMin) / 100);
2197 fan_table.TempMed = cpu_to_be16((50 + hwmgr->
2198 thermal_controller.advanceFanControlParameters.usTMed) / 100);
2199 fan_table.TempMax = cpu_to_be16((50 + hwmgr->
2200 thermal_controller.advanceFanControlParameters.usTMax) / 100);
2202 fan_table.Slope1 = cpu_to_be16(slope1);
2203 fan_table.Slope2 = cpu_to_be16(slope2);
2205 fan_table.FdoMin = cpu_to_be16(fdo_min);
2207 fan_table.HystDown = cpu_to_be16(hwmgr->
2208 thermal_controller.advanceFanControlParameters.ucTHyst);
2210 fan_table.HystUp = cpu_to_be16(1);
2212 fan_table.HystSlope = cpu_to_be16(1);
2214 fan_table.TempRespLim = cpu_to_be16(5);
2216 reference_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
2218 fan_table.RefreshPeriod = cpu_to_be32((hwmgr->
2219 thermal_controller.advanceFanControlParameters.ulCycleDelay *
2220 reference_clock) / 1600);
2222 fan_table.FdoMax = cpu_to_be16((uint16_t)duty100);
2224 fan_table.TempSrc = (uint8_t)PHM_READ_VFPF_INDIRECT_FIELD(
2225 hwmgr->device, CGS_IND_REG__SMC,
2226 CG_MULT_THERMAL_CTRL, TEMP_SEL);
2228 res = smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.fan_table_start,
2229 (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table),
2232 if (!res && hwmgr->thermal_controller.
2233 advanceFanControlParameters.ucMinimumPWMLimit)
2234 res = smum_send_msg_to_smc_with_parameter(hwmgr,
2235 PPSMC_MSG_SetFanMinPwm,
2236 hwmgr->thermal_controller.
2237 advanceFanControlParameters.ucMinimumPWMLimit,
2240 if (!res && hwmgr->thermal_controller.
2241 advanceFanControlParameters.ulMinFanSCLKAcousticLimit)
2242 res = smum_send_msg_to_smc_with_parameter(hwmgr,
2243 PPSMC_MSG_SetFanSclkTarget,
2244 hwmgr->thermal_controller.
2245 advanceFanControlParameters.ulMinFanSCLKAcousticLimit,
2249 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2250 PHM_PlatformCaps_MicrocodeFanControl);
2255 static int polaris10_update_uvd_smc_table(struct pp_hwmgr *hwmgr)
2257 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2258 uint32_t mm_boot_level_offset, mm_boot_level_value;
2259 struct phm_ppt_v1_information *table_info =
2260 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2262 smu_data->smc_state_table.UvdBootLevel = 0;
2263 if (table_info->mm_dep_table->count > 0)
2264 smu_data->smc_state_table.UvdBootLevel =
2265 (uint8_t) (table_info->mm_dep_table->count - 1);
2266 mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + offsetof(SMU74_Discrete_DpmTable,
2268 mm_boot_level_offset /= 4;
2269 mm_boot_level_offset *= 4;
2270 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
2271 CGS_IND_REG__SMC, mm_boot_level_offset);
2272 mm_boot_level_value &= 0x00FFFFFF;
2273 mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24;
2274 cgs_write_ind_register(hwmgr->device,
2275 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
2277 if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2278 PHM_PlatformCaps_UVDDPM) ||
2279 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2280 PHM_PlatformCaps_StablePState))
2281 smum_send_msg_to_smc_with_parameter(hwmgr,
2282 PPSMC_MSG_UVDDPM_SetEnabledMask,
2283 (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel),
2288 static int polaris10_update_vce_smc_table(struct pp_hwmgr *hwmgr)
2290 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2291 uint32_t mm_boot_level_offset, mm_boot_level_value;
2292 struct phm_ppt_v1_information *table_info =
2293 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2295 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2296 PHM_PlatformCaps_StablePState))
2297 smu_data->smc_state_table.VceBootLevel =
2298 (uint8_t) (table_info->mm_dep_table->count - 1);
2300 smu_data->smc_state_table.VceBootLevel = 0;
2302 mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
2303 offsetof(SMU74_Discrete_DpmTable, VceBootLevel);
2304 mm_boot_level_offset /= 4;
2305 mm_boot_level_offset *= 4;
2306 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
2307 CGS_IND_REG__SMC, mm_boot_level_offset);
2308 mm_boot_level_value &= 0xFF00FFFF;
2309 mm_boot_level_value |= smu_data->smc_state_table.VceBootLevel << 16;
2310 cgs_write_ind_register(hwmgr->device,
2311 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
2313 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
2314 smum_send_msg_to_smc_with_parameter(hwmgr,
2315 PPSMC_MSG_VCEDPM_SetEnabledMask,
2316 (uint32_t)1 << smu_data->smc_state_table.VceBootLevel,
2321 static int polaris10_update_bif_smc_table(struct pp_hwmgr *hwmgr)
2323 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2324 struct phm_ppt_v1_information *table_info =
2325 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2326 struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
2329 max_entry = (SMU74_MAX_LEVELS_LINK < pcie_table->count) ?
2330 SMU74_MAX_LEVELS_LINK :
2332 /* Setup BIF_SCLK levels */
2333 for (i = 0; i < max_entry; i++)
2334 smu_data->bif_sclk_table[i] = pcie_table->entries[i].pcie_sclk;
2338 static int polaris10_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)
2342 polaris10_update_uvd_smc_table(hwmgr);
2345 polaris10_update_vce_smc_table(hwmgr);
2348 polaris10_update_bif_smc_table(hwmgr);
2355 static int polaris10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
2357 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2358 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2361 uint32_t low_sclk_interrupt_threshold = 0;
2363 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2364 PHM_PlatformCaps_SclkThrottleLowNotification)
2365 && (data->low_sclk_interrupt_threshold != 0)) {
2366 low_sclk_interrupt_threshold =
2367 data->low_sclk_interrupt_threshold;
2369 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
2371 result = smu7_copy_bytes_to_smc(
2373 smu_data->smu7_data.dpm_table_start +
2374 offsetof(SMU74_Discrete_DpmTable,
2375 LowSclkInterruptThreshold),
2376 (uint8_t *)&low_sclk_interrupt_threshold,
2380 PP_ASSERT_WITH_CODE((result == 0),
2381 "Failed to update SCLK threshold!", return result);
2383 result = polaris10_program_mem_timing_parameters(hwmgr);
2384 PP_ASSERT_WITH_CODE((result == 0),
2385 "Failed to program memory timing parameters!",
2391 static uint32_t polaris10_get_offsetof(uint32_t type, uint32_t member)
2394 case SMU_SoftRegisters:
2396 case HandshakeDisables:
2397 return offsetof(SMU74_SoftRegisters, HandshakeDisables);
2398 case VoltageChangeTimeout:
2399 return offsetof(SMU74_SoftRegisters, VoltageChangeTimeout);
2400 case AverageGraphicsActivity:
2401 return offsetof(SMU74_SoftRegisters, AverageGraphicsActivity);
2402 case AverageMemoryActivity:
2403 return offsetof(SMU74_SoftRegisters, AverageMemoryActivity);
2405 return offsetof(SMU74_SoftRegisters, PreVBlankGap);
2407 return offsetof(SMU74_SoftRegisters, VBlankTimeout);
2408 case UcodeLoadStatus:
2409 return offsetof(SMU74_SoftRegisters, UcodeLoadStatus);
2410 case DRAM_LOG_ADDR_H:
2411 return offsetof(SMU74_SoftRegisters, DRAM_LOG_ADDR_H);
2412 case DRAM_LOG_ADDR_L:
2413 return offsetof(SMU74_SoftRegisters, DRAM_LOG_ADDR_L);
2414 case DRAM_LOG_PHY_ADDR_H:
2415 return offsetof(SMU74_SoftRegisters, DRAM_LOG_PHY_ADDR_H);
2416 case DRAM_LOG_PHY_ADDR_L:
2417 return offsetof(SMU74_SoftRegisters, DRAM_LOG_PHY_ADDR_L);
2418 case DRAM_LOG_BUFF_SIZE:
2419 return offsetof(SMU74_SoftRegisters, DRAM_LOG_BUFF_SIZE);
2422 case SMU_Discrete_DpmTable:
2425 return offsetof(SMU74_Discrete_DpmTable, UvdBootLevel);
2427 return offsetof(SMU74_Discrete_DpmTable, VceBootLevel);
2428 case LowSclkInterruptThreshold:
2429 return offsetof(SMU74_Discrete_DpmTable, LowSclkInterruptThreshold);
2433 pr_warn("can't get the offset of type %x member %x\n", type, member);
2437 static uint32_t polaris10_get_mac_definition(uint32_t value)
2440 case SMU_MAX_LEVELS_GRAPHICS:
2441 return SMU74_MAX_LEVELS_GRAPHICS;
2442 case SMU_MAX_LEVELS_MEMORY:
2443 return SMU74_MAX_LEVELS_MEMORY;
2444 case SMU_MAX_LEVELS_LINK:
2445 return SMU74_MAX_LEVELS_LINK;
2446 case SMU_MAX_ENTRIES_SMIO:
2447 return SMU74_MAX_ENTRIES_SMIO;
2448 case SMU_MAX_LEVELS_VDDC:
2449 return SMU74_MAX_LEVELS_VDDC;
2450 case SMU_MAX_LEVELS_VDDGFX:
2451 return SMU74_MAX_LEVELS_VDDGFX;
2452 case SMU_MAX_LEVELS_VDDCI:
2453 return SMU74_MAX_LEVELS_VDDCI;
2454 case SMU_MAX_LEVELS_MVDD:
2455 return SMU74_MAX_LEVELS_MVDD;
2456 case SMU_UVD_MCLK_HANDSHAKE_DISABLE:
2457 return SMU7_UVD_MCLK_HANDSHAKE_DISABLE;
2460 pr_warn("can't get the mac of %x\n", value);
2464 static int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr)
2466 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2467 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2472 result = smu7_read_smc_sram_dword(hwmgr,
2473 SMU7_FIRMWARE_HEADER_LOCATION +
2474 offsetof(SMU74_Firmware_Header, DpmTable),
2478 smu_data->smu7_data.dpm_table_start = tmp;
2480 error |= (0 != result);
2482 result = smu7_read_smc_sram_dword(hwmgr,
2483 SMU7_FIRMWARE_HEADER_LOCATION +
2484 offsetof(SMU74_Firmware_Header, SoftRegisters),
2488 data->soft_regs_start = tmp;
2489 smu_data->smu7_data.soft_regs_start = tmp;
2492 error |= (0 != result);
2494 result = smu7_read_smc_sram_dword(hwmgr,
2495 SMU7_FIRMWARE_HEADER_LOCATION +
2496 offsetof(SMU74_Firmware_Header, mcRegisterTable),
2500 smu_data->smu7_data.mc_reg_table_start = tmp;
2502 result = smu7_read_smc_sram_dword(hwmgr,
2503 SMU7_FIRMWARE_HEADER_LOCATION +
2504 offsetof(SMU74_Firmware_Header, FanTable),
2508 smu_data->smu7_data.fan_table_start = tmp;
2510 error |= (0 != result);
2512 result = smu7_read_smc_sram_dword(hwmgr,
2513 SMU7_FIRMWARE_HEADER_LOCATION +
2514 offsetof(SMU74_Firmware_Header, mcArbDramTimingTable),
2518 smu_data->smu7_data.arb_table_start = tmp;
2520 error |= (0 != result);
2522 result = smu7_read_smc_sram_dword(hwmgr,
2523 SMU7_FIRMWARE_HEADER_LOCATION +
2524 offsetof(SMU74_Firmware_Header, Version),
2528 hwmgr->microcode_version_info.SMC = tmp;
2530 error |= (0 != result);
2532 return error ? -1 : 0;
2535 static uint8_t polaris10_get_memory_modile_index(struct pp_hwmgr *hwmgr)
2537 return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device, mmBIOS_SCRATCH_4) >> 16));
2540 static int polaris10_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
2543 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2544 pp_atomctrl_mc_reg_table *mc_reg_table = &smu_data->mc_reg_table;
2545 uint8_t module_index = polaris10_get_memory_modile_index(hwmgr);
2547 memset(mc_reg_table, 0, sizeof(pp_atomctrl_mc_reg_table));
2548 result = atomctrl_initialize_mc_reg_table_v2_2(hwmgr, module_index, mc_reg_table);
2553 static bool polaris10_is_dpm_running(struct pp_hwmgr *hwmgr)
2555 return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
2556 CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
2560 static int polaris10_update_dpm_settings(struct pp_hwmgr *hwmgr,
2561 void *profile_setting)
2563 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2564 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)
2565 (hwmgr->smu_backend);
2566 struct profile_mode_setting *setting;
2567 struct SMU74_Discrete_GraphicsLevel *levels =
2568 smu_data->smc_state_table.GraphicsLevel;
2569 uint32_t array = smu_data->smu7_data.dpm_table_start +
2570 offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
2572 uint32_t mclk_array = smu_data->smu7_data.dpm_table_start +
2573 offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
2574 struct SMU74_Discrete_MemoryLevel *mclk_levels =
2575 smu_data->smc_state_table.MemoryLevel;
2577 uint32_t offset, up_hyst_offset, down_hyst_offset, clk_activity_offset, tmp;
2579 if (profile_setting == NULL)
2582 setting = (struct profile_mode_setting *)profile_setting;
2584 if (setting->bupdate_sclk) {
2585 if (!data->sclk_dpm_key_disabled)
2586 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SCLKDPM_FreezeLevel, NULL);
2587 for (i = 0; i < smu_data->smc_state_table.GraphicsDpmLevelCount; i++) {
2588 if (levels[i].ActivityLevel !=
2589 cpu_to_be16(setting->sclk_activity)) {
2590 levels[i].ActivityLevel = cpu_to_be16(setting->sclk_activity);
2592 clk_activity_offset = array + (sizeof(SMU74_Discrete_GraphicsLevel) * i)
2593 + offsetof(SMU74_Discrete_GraphicsLevel, ActivityLevel);
2594 offset = clk_activity_offset & ~0x3;
2595 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
2596 tmp = phm_set_field_to_u32(clk_activity_offset, tmp, levels[i].ActivityLevel, sizeof(uint16_t));
2597 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
2600 if (levels[i].UpHyst != setting->sclk_up_hyst ||
2601 levels[i].DownHyst != setting->sclk_down_hyst) {
2602 levels[i].UpHyst = setting->sclk_up_hyst;
2603 levels[i].DownHyst = setting->sclk_down_hyst;
2604 up_hyst_offset = array + (sizeof(SMU74_Discrete_GraphicsLevel) * i)
2605 + offsetof(SMU74_Discrete_GraphicsLevel, UpHyst);
2606 down_hyst_offset = array + (sizeof(SMU74_Discrete_GraphicsLevel) * i)
2607 + offsetof(SMU74_Discrete_GraphicsLevel, DownHyst);
2608 offset = up_hyst_offset & ~0x3;
2609 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
2610 tmp = phm_set_field_to_u32(up_hyst_offset, tmp, levels[i].UpHyst, sizeof(uint8_t));
2611 tmp = phm_set_field_to_u32(down_hyst_offset, tmp, levels[i].DownHyst, sizeof(uint8_t));
2612 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
2615 if (!data->sclk_dpm_key_disabled)
2616 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SCLKDPM_UnfreezeLevel, NULL);
2619 if (setting->bupdate_mclk) {
2620 if (!data->mclk_dpm_key_disabled)
2621 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_FreezeLevel, NULL);
2622 for (i = 0; i < smu_data->smc_state_table.MemoryDpmLevelCount; i++) {
2623 if (mclk_levels[i].ActivityLevel !=
2624 cpu_to_be16(setting->mclk_activity)) {
2625 mclk_levels[i].ActivityLevel = cpu_to_be16(setting->mclk_activity);
2627 clk_activity_offset = mclk_array + (sizeof(SMU74_Discrete_MemoryLevel) * i)
2628 + offsetof(SMU74_Discrete_MemoryLevel, ActivityLevel);
2629 offset = clk_activity_offset & ~0x3;
2630 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
2631 tmp = phm_set_field_to_u32(clk_activity_offset, tmp, mclk_levels[i].ActivityLevel, sizeof(uint16_t));
2632 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
2635 if (mclk_levels[i].UpHyst != setting->mclk_up_hyst ||
2636 mclk_levels[i].DownHyst != setting->mclk_down_hyst) {
2637 mclk_levels[i].UpHyst = setting->mclk_up_hyst;
2638 mclk_levels[i].DownHyst = setting->mclk_down_hyst;
2639 up_hyst_offset = mclk_array + (sizeof(SMU74_Discrete_MemoryLevel) * i)
2640 + offsetof(SMU74_Discrete_MemoryLevel, UpHyst);
2641 down_hyst_offset = mclk_array + (sizeof(SMU74_Discrete_MemoryLevel) * i)
2642 + offsetof(SMU74_Discrete_MemoryLevel, DownHyst);
2643 offset = up_hyst_offset & ~0x3;
2644 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
2645 tmp = phm_set_field_to_u32(up_hyst_offset, tmp, mclk_levels[i].UpHyst, sizeof(uint8_t));
2646 tmp = phm_set_field_to_u32(down_hyst_offset, tmp, mclk_levels[i].DownHyst, sizeof(uint8_t));
2647 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
2650 if (!data->mclk_dpm_key_disabled)
2651 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_UnfreezeLevel, NULL);
2656 const struct pp_smumgr_func polaris10_smu_funcs = {
2657 .name = "polaris10_smu",
2658 .smu_init = polaris10_smu_init,
2659 .smu_fini = smu7_smu_fini,
2660 .start_smu = polaris10_start_smu,
2661 .check_fw_load_finish = smu7_check_fw_load_finish,
2662 .request_smu_load_fw = smu7_reload_firmware,
2663 .request_smu_load_specific_fw = NULL,
2664 .send_msg_to_smc = smu7_send_msg_to_smc,
2665 .send_msg_to_smc_with_parameter = smu7_send_msg_to_smc_with_parameter,
2666 .get_argument = smu7_get_argument,
2667 .download_pptable_settings = NULL,
2668 .upload_pptable_settings = NULL,
2669 .update_smc_table = polaris10_update_smc_table,
2670 .get_offsetof = polaris10_get_offsetof,
2671 .process_firmware_header = polaris10_process_firmware_header,
2672 .init_smc_table = polaris10_init_smc_table,
2673 .update_sclk_threshold = polaris10_update_sclk_threshold,
2674 .thermal_avfs_enable = polaris10_thermal_avfs_enable,
2675 .thermal_setup_fan_table = polaris10_thermal_setup_fan_table,
2676 .populate_all_graphic_levels = polaris10_populate_all_graphic_levels,
2677 .populate_all_memory_levels = polaris10_populate_all_memory_levels,
2678 .get_mac_definition = polaris10_get_mac_definition,
2679 .initialize_mc_reg_table = polaris10_initialize_mc_reg_table,
2680 .is_dpm_running = polaris10_is_dpm_running,
2681 .is_hw_avfs_present = polaris10_is_hw_avfs_present,
2682 .update_dpm_settings = polaris10_update_dpm_settings,