2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/pci.h>
29 #include "smu_ucode_xfer_vi.h"
30 #include "polaris10_smumgr.h"
31 #include "smu74_discrete.h"
32 #include "smu/smu_7_1_3_d.h"
33 #include "smu/smu_7_1_3_sh_mask.h"
34 #include "gmc/gmc_8_1_d.h"
35 #include "gmc/gmc_8_1_sh_mask.h"
36 #include "oss/oss_3_0_d.h"
37 #include "gca/gfx_8_0_d.h"
38 #include "bif/bif_5_0_d.h"
39 #include "bif/bif_5_0_sh_mask.h"
40 #include "ppatomctrl.h"
41 #include "cgs_common.h"
42 #include "smu7_ppsmc.h"
43 #include "smu7_smumgr.h"
45 #include "smu7_dyn_defaults.h"
47 #include "smu7_hwmgr.h"
48 #include "hardwaremanager.h"
50 #include "pppcielanes.h"
52 #include "dce/dce_10_0_d.h"
53 #include "dce/dce_10_0_sh_mask.h"
55 #define POLARIS10_SMC_SIZE 0x20000
56 #define POWERTUNE_DEFAULT_SET_MAX 1
57 #define VDDC_VDDCI_DELTA 200
58 #define MC_CG_ARB_FREQ_F1 0x0b
60 static const struct polaris10_pt_defaults polaris10_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = {
61 /* sviLoadLIneEn, SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt,
62 * TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac, BAPM_TEMP_GRADIENT */
63 { 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
64 { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61},
65 { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 } },
68 static const sclkFcwRange_t Range_Table[NUM_SCLK_RANGE] = {
69 {VCO_2_4, POSTDIV_DIV_BY_16, 75, 160, 112},
70 {VCO_3_6, POSTDIV_DIV_BY_16, 112, 224, 160},
71 {VCO_2_4, POSTDIV_DIV_BY_8, 75, 160, 112},
72 {VCO_3_6, POSTDIV_DIV_BY_8, 112, 224, 160},
73 {VCO_2_4, POSTDIV_DIV_BY_4, 75, 160, 112},
74 {VCO_3_6, POSTDIV_DIV_BY_4, 112, 216, 160},
75 {VCO_2_4, POSTDIV_DIV_BY_2, 75, 160, 108},
76 {VCO_3_6, POSTDIV_DIV_BY_2, 112, 216, 160} };
78 #define PPPOLARIS10_TARGETACTIVITY_DFLT 50
80 static const SMU74_Discrete_GraphicsLevel avfs_graphics_level_polaris10[8] = {
81 /* Min pcie DeepSleep Activity CgSpll CgSpll CcPwr CcPwr Sclk Enabled Enabled Voltage Power */
82 /* Voltage, DpmLevel, DivId, Level, FuncCntl3, FuncCntl4, DynRm, DynRm1 Did, Padding,ForActivity, ForThrottle, UpHyst, DownHyst, DownHyst, Throttle */
83 { 0x100ea446, 0x00, 0x03, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x30750000, 0x3000, 0, 0x2600, 0, 0, 0x0004, 0x8f02, 0xffff, 0x2f00, 0x300e, 0x2700 } },
84 { 0x400ea446, 0x01, 0x04, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x409c0000, 0x2000, 0, 0x1e00, 1, 1, 0x0004, 0x8300, 0xffff, 0x1f00, 0xcb5e, 0x1a00 } },
85 { 0x740ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x50c30000, 0x2800, 0, 0x2000, 1, 1, 0x0004, 0x0c02, 0xffff, 0x2700, 0x6433, 0x2100 } },
86 { 0xa40ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x60ea0000, 0x3000, 0, 0x2600, 1, 1, 0x0004, 0x8f02, 0xffff, 0x2f00, 0x300e, 0x2700 } },
87 { 0xd80ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x70110100, 0x3800, 0, 0x2c00, 1, 1, 0x0004, 0x1203, 0xffff, 0x3600, 0xc9e2, 0x2e00 } },
88 { 0x3c0fa446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x80380100, 0x2000, 0, 0x1e00, 2, 1, 0x0004, 0x8300, 0xffff, 0x1f00, 0xcb5e, 0x1a00 } },
89 { 0x6c0fa446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x905f0100, 0x2400, 0, 0x1e00, 2, 1, 0x0004, 0x8901, 0xffff, 0x2300, 0x314c, 0x1d00 } },
90 { 0xa00fa446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0xa0860100, 0x2800, 0, 0x2000, 2, 1, 0x0004, 0x0c02, 0xffff, 0x2700, 0x6433, 0x2100 } }
93 static const SMU74_Discrete_MemoryLevel avfs_memory_level_polaris10 = {
94 0x100ea446, 0, 0x30750000, 0x01, 0x01, 0x01, 0x00, 0x00, 0x64, 0x00, 0x00, 0x1f00, 0x00, 0x00};
96 static int polaris10_perform_btc(struct pp_hwmgr *hwmgr)
99 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
101 if (0 != smu_data->avfs_btc_param) {
102 if (0 != smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_PerformBtc, smu_data->avfs_btc_param,
104 pr_info("[AVFS][SmuPolaris10_PerformBtc] PerformBTC SMU msg failed");
108 if (smu_data->avfs_btc_param > 1) {
109 /* Soft-Reset to reset the engine before loading uCode */
111 cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, 0x50000000);
112 /* reset everything */
113 cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0xffffffff);
114 cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0);
120 static int polaris10_setup_graphics_level_structure(struct pp_hwmgr *hwmgr)
123 uint32_t dpm_table_start;
125 uint16_t u16_boot_mvdd;
126 uint32_t graphics_level_address, vr_config_address, graphics_level_size;
128 graphics_level_size = sizeof(avfs_graphics_level_polaris10);
129 u16_boot_mvdd = PP_HOST_TO_SMC_US(1300 * VOLTAGE_SCALE);
131 PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(hwmgr,
132 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, DpmTable),
133 &dpm_table_start, 0x40000),
134 "[AVFS][Polaris10_SetupGfxLvlStruct] SMU could not communicate starting address of DPM table",
137 /* Default value for VRConfig = VR_MERGED_WITH_VDDC + VR_STATIC_VOLTAGE(VDDCI) */
138 vr_config = 0x01000500; /* Real value:0x50001 */
140 vr_config_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, VRConfig);
142 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, vr_config_address,
143 (uint8_t *)&vr_config, sizeof(uint32_t), 0x40000),
144 "[AVFS][Polaris10_SetupGfxLvlStruct] Problems copying VRConfig value over to SMC",
147 graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
149 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address,
150 (uint8_t *)(&avfs_graphics_level_polaris10),
151 graphics_level_size, 0x40000),
152 "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of SCLK DPM table failed!",
155 graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
157 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address,
158 (uint8_t *)(&avfs_memory_level_polaris10), sizeof(avfs_memory_level_polaris10), 0x40000),
159 "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of MCLK DPM table failed!",
162 /* MVDD Boot value - neccessary for getting rid of the hang that occurs during Mclk DPM enablement */
164 graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, BootMVdd);
166 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address,
167 (uint8_t *)(&u16_boot_mvdd), sizeof(u16_boot_mvdd), 0x40000),
168 "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of DPM table failed!",
175 static int polaris10_avfs_event_mgr(struct pp_hwmgr *hwmgr)
177 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
179 if (!hwmgr->avfs_supported)
182 PP_ASSERT_WITH_CODE(0 == polaris10_setup_graphics_level_structure(hwmgr),
183 "[AVFS][Polaris10_AVFSEventMgr] Could not Copy Graphics Level table over to SMU",
186 if (smu_data->avfs_btc_param > 1) {
187 pr_info("[AVFS][Polaris10_AVFSEventMgr] AC BTC has not been successfully verified on Fiji. There may be in this setting.");
188 PP_ASSERT_WITH_CODE(0 == smu7_setup_pwr_virus(hwmgr),
189 "[AVFS][Polaris10_AVFSEventMgr] Could not setup Pwr Virus for AVFS ",
193 PP_ASSERT_WITH_CODE(0 == polaris10_perform_btc(hwmgr),
194 "[AVFS][Polaris10_AVFSEventMgr] Failure at SmuPolaris10_PerformBTC. AVFS Disabled",
200 static int polaris10_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr)
204 /* Wait for smc boot up */
205 /* PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0) */
208 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
209 SMC_SYSCON_RESET_CNTL, rst_reg, 1);
211 result = smu7_upload_smu_firmware_image(hwmgr);
216 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMU_STATUS, 0);
218 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
219 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
221 /* De-assert reset */
222 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
223 SMC_SYSCON_RESET_CNTL, rst_reg, 0);
226 PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1);
229 /* Call Test SMU message with 0x20000 offset to trigger SMU start */
230 smu7_send_msg_to_smc_offset(hwmgr);
232 /* Wait done bit to be set */
233 /* Check pass/failed indicator */
235 PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, SMU_STATUS, SMU_DONE, 0);
237 if (1 != PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
238 SMU_STATUS, SMU_PASS))
239 PP_ASSERT_WITH_CODE(false, "SMU Firmware start failed!", return -1);
241 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixFIRMWARE_FLAGS, 0);
243 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
244 SMC_SYSCON_RESET_CNTL, rst_reg, 1);
246 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
247 SMC_SYSCON_RESET_CNTL, rst_reg, 0);
249 /* Wait for firmware to initialize */
250 PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
255 static int polaris10_start_smu_in_non_protection_mode(struct pp_hwmgr *hwmgr)
259 /* wait for smc boot up */
260 PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0);
262 /* Clear firmware interrupt enable flag */
263 /* PHM_WRITE_VFPF_INDIRECT_FIELD(pSmuMgr, SMC_IND, SMC_SYSCON_MISC_CNTL, pre_fetcher_en, 1); */
264 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
265 ixFIRMWARE_FLAGS, 0);
267 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
268 SMC_SYSCON_RESET_CNTL,
271 result = smu7_upload_smu_firmware_image(hwmgr);
275 /* Set smc instruct start point at 0x0 */
276 smu7_program_jump_on_start(hwmgr);
278 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
279 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
281 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
282 SMC_SYSCON_RESET_CNTL, rst_reg, 0);
284 /* Wait for firmware to initialize */
286 PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
287 FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
292 static int polaris10_start_smu(struct pp_hwmgr *hwmgr)
295 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
297 /* Only start SMC if SMC RAM is not running */
298 if (!smu7_is_smc_ram_running(hwmgr) && hwmgr->not_vf) {
299 smu_data->protected_mode = (uint8_t) (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_MODE));
300 smu_data->smu7_data.security_hard_key = (uint8_t) (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_SEL));
302 /* Check if SMU is running in protected mode */
303 if (smu_data->protected_mode == 0)
304 result = polaris10_start_smu_in_non_protection_mode(hwmgr);
306 result = polaris10_start_smu_in_protection_mode(hwmgr);
309 PP_ASSERT_WITH_CODE(0, "Failed to load SMU ucode.", return result);
311 polaris10_avfs_event_mgr(hwmgr);
314 /* Setup SoftRegsStart here for register lookup in case DummyBackEnd is used and ProcessFirmwareHeader is not executed */
315 smu7_read_smc_sram_dword(hwmgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, SoftRegisters),
316 &(smu_data->smu7_data.soft_regs_start), 0x40000);
318 result = smu7_request_smu_load_fw(hwmgr);
323 static bool polaris10_is_hw_avfs_present(struct pp_hwmgr *hwmgr)
327 efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMU_EFUSE_0 + (49*4));
335 static int polaris10_smu_init(struct pp_hwmgr *hwmgr)
337 struct polaris10_smumgr *smu_data;
339 smu_data = kzalloc(sizeof(struct polaris10_smumgr), GFP_KERNEL);
340 if (smu_data == NULL)
343 hwmgr->smu_backend = smu_data;
345 if (smu7_init(hwmgr)) {
353 static int polaris10_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
354 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table,
355 uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
359 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
361 *voltage = *mvdd = 0;
363 /* clock - voltage dependency table is empty table */
364 if (dep_table->count == 0)
367 for (i = 0; i < dep_table->count; i++) {
368 /* find first sclk bigger than request */
369 if (dep_table->entries[i].clk >= clock) {
370 *voltage |= (dep_table->entries[i].vddc *
371 VOLTAGE_SCALE) << VDDC_SHIFT;
372 if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control)
373 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
374 VOLTAGE_SCALE) << VDDCI_SHIFT;
375 else if (dep_table->entries[i].vddci)
376 *voltage |= (dep_table->entries[i].vddci *
377 VOLTAGE_SCALE) << VDDCI_SHIFT;
379 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
380 (dep_table->entries[i].vddc -
381 (uint16_t)VDDC_VDDCI_DELTA));
382 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
385 if (SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control)
386 *mvdd = data->vbios_boot_state.mvdd_bootup_value *
388 else if (dep_table->entries[i].mvdd)
389 *mvdd = (uint32_t) dep_table->entries[i].mvdd *
392 *voltage |= 1 << PHASES_SHIFT;
397 /* sclk is bigger than max sclk in the dependence table */
398 *voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
400 if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control)
401 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
402 VOLTAGE_SCALE) << VDDCI_SHIFT;
403 else if (dep_table->entries[i-1].vddci) {
404 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
405 (dep_table->entries[i].vddc -
406 (uint16_t)VDDC_VDDCI_DELTA));
407 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
410 if (SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control)
411 *mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE;
412 else if (dep_table->entries[i].mvdd)
413 *mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE;
418 static uint16_t scale_fan_gain_settings(uint16_t raw_setting)
421 tmp = raw_setting * 4096 / 100;
422 return (uint16_t)tmp;
425 static int polaris10_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
427 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
429 const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults;
430 SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
431 struct phm_ppt_v1_information *table_info =
432 (struct phm_ppt_v1_information *)(hwmgr->pptable);
433 struct phm_cac_tdp_table *cac_dtp_table = table_info->cac_dtp_table;
434 struct pp_advance_fan_control_parameters *fan_table =
435 &hwmgr->thermal_controller.advanceFanControlParameters;
437 const uint16_t *pdef1;
438 const uint16_t *pdef2;
440 table->DefaultTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 128));
441 table->TargetTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 128));
443 PP_ASSERT_WITH_CODE(cac_dtp_table->usTargetOperatingTemp <= 255,
444 "Target Operating Temp is out of Range!",
447 table->TemperatureLimitEdge = PP_HOST_TO_SMC_US(
448 cac_dtp_table->usTargetOperatingTemp * 256);
449 table->TemperatureLimitHotspot = PP_HOST_TO_SMC_US(
450 cac_dtp_table->usTemperatureLimitHotspot * 256);
451 table->FanGainEdge = PP_HOST_TO_SMC_US(
452 scale_fan_gain_settings(fan_table->usFanGainEdge));
453 table->FanGainHotspot = PP_HOST_TO_SMC_US(
454 scale_fan_gain_settings(fan_table->usFanGainHotspot));
456 pdef1 = defaults->BAPMTI_R;
457 pdef2 = defaults->BAPMTI_RC;
459 for (i = 0; i < SMU74_DTE_ITERATIONS; i++) {
460 for (j = 0; j < SMU74_DTE_SOURCES; j++) {
461 for (k = 0; k < SMU74_DTE_SINKS; k++) {
462 table->BAPMTI_R[i][j][k] = PP_HOST_TO_SMC_US(*pdef1);
463 table->BAPMTI_RC[i][j][k] = PP_HOST_TO_SMC_US(*pdef2);
473 static int polaris10_populate_svi_load_line(struct pp_hwmgr *hwmgr)
475 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
476 const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults;
478 smu_data->power_tune_table.SviLoadLineEn = defaults->SviLoadLineEn;
479 smu_data->power_tune_table.SviLoadLineVddC = defaults->SviLoadLineVddC;
480 smu_data->power_tune_table.SviLoadLineTrimVddC = 3;
481 smu_data->power_tune_table.SviLoadLineOffsetVddC = 0;
486 static int polaris10_populate_tdc_limit(struct pp_hwmgr *hwmgr)
489 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
490 struct phm_ppt_v1_information *table_info =
491 (struct phm_ppt_v1_information *)(hwmgr->pptable);
492 const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults;
494 tdc_limit = (uint16_t)(table_info->cac_dtp_table->usTDC * 128);
495 smu_data->power_tune_table.TDC_VDDC_PkgLimit =
496 CONVERT_FROM_HOST_TO_SMC_US(tdc_limit);
497 smu_data->power_tune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
498 defaults->TDC_VDDC_ThrottleReleaseLimitPerc;
499 smu_data->power_tune_table.TDC_MAWt = defaults->TDC_MAWt;
504 static int polaris10_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
506 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
507 const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults;
510 if (smu7_read_smc_sram_dword(hwmgr,
512 offsetof(SMU74_Discrete_PmFuses, TdcWaterfallCtl),
513 (uint32_t *)&temp, SMC_RAM_END))
514 PP_ASSERT_WITH_CODE(false,
515 "Attempt to read PmFuses.DW6 (SviLoadLineEn) from SMC Failed!",
518 smu_data->power_tune_table.TdcWaterfallCtl = defaults->TdcWaterfallCtl;
519 smu_data->power_tune_table.LPMLTemperatureMin =
520 (uint8_t)((temp >> 16) & 0xff);
521 smu_data->power_tune_table.LPMLTemperatureMax =
522 (uint8_t)((temp >> 8) & 0xff);
523 smu_data->power_tune_table.Reserved = (uint8_t)(temp & 0xff);
528 static int polaris10_populate_temperature_scaler(struct pp_hwmgr *hwmgr)
531 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
533 /* Currently not used. Set all to zero. */
534 for (i = 0; i < 16; i++)
535 smu_data->power_tune_table.LPMLTemperatureScaler[i] = 0;
540 static int polaris10_populate_fuzzy_fan(struct pp_hwmgr *hwmgr)
542 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
544 /* TO DO move to hwmgr */
545 if ((hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity & (1 << 15))
546 || 0 == hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity)
547 hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity =
548 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultFanOutputSensitivity;
550 smu_data->power_tune_table.FuzzyFan_PwmSetDelta = PP_HOST_TO_SMC_US(
551 hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity);
555 static int polaris10_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
558 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
560 /* Currently not used. Set all to zero. */
561 for (i = 0; i < 16; i++)
562 smu_data->power_tune_table.GnbLPML[i] = 0;
567 static int polaris10_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
569 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
570 struct phm_ppt_v1_information *table_info =
571 (struct phm_ppt_v1_information *)(hwmgr->pptable);
572 uint16_t hi_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd;
573 uint16_t lo_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd;
574 struct phm_cac_tdp_table *cac_table = table_info->cac_dtp_table;
576 hi_sidd = (uint16_t)(cac_table->usHighCACLeakage / 100 * 256);
577 lo_sidd = (uint16_t)(cac_table->usLowCACLeakage / 100 * 256);
579 smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd =
580 CONVERT_FROM_HOST_TO_SMC_US(hi_sidd);
581 smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd =
582 CONVERT_FROM_HOST_TO_SMC_US(lo_sidd);
587 static int polaris10_populate_pm_fuses(struct pp_hwmgr *hwmgr)
589 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
590 uint32_t pm_fuse_table_offset;
592 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
593 PHM_PlatformCaps_PowerContainment)) {
594 if (smu7_read_smc_sram_dword(hwmgr,
595 SMU7_FIRMWARE_HEADER_LOCATION +
596 offsetof(SMU74_Firmware_Header, PmFuseTable),
597 &pm_fuse_table_offset, SMC_RAM_END))
598 PP_ASSERT_WITH_CODE(false,
599 "Attempt to get pm_fuse_table_offset Failed!",
602 if (polaris10_populate_svi_load_line(hwmgr))
603 PP_ASSERT_WITH_CODE(false,
604 "Attempt to populate SviLoadLine Failed!",
607 if (polaris10_populate_tdc_limit(hwmgr))
608 PP_ASSERT_WITH_CODE(false,
609 "Attempt to populate TDCLimit Failed!", return -EINVAL);
611 if (polaris10_populate_dw8(hwmgr, pm_fuse_table_offset))
612 PP_ASSERT_WITH_CODE(false,
613 "Attempt to populate TdcWaterfallCtl, "
614 "LPMLTemperature Min and Max Failed!",
617 if (0 != polaris10_populate_temperature_scaler(hwmgr))
618 PP_ASSERT_WITH_CODE(false,
619 "Attempt to populate LPMLTemperatureScaler Failed!",
622 if (polaris10_populate_fuzzy_fan(hwmgr))
623 PP_ASSERT_WITH_CODE(false,
624 "Attempt to populate Fuzzy Fan Control parameters Failed!",
627 if (polaris10_populate_gnb_lpml(hwmgr))
628 PP_ASSERT_WITH_CODE(false,
629 "Attempt to populate GnbLPML Failed!",
632 if (polaris10_populate_bapm_vddc_base_leakage_sidd(hwmgr))
633 PP_ASSERT_WITH_CODE(false,
634 "Attempt to populate BapmVddCBaseLeakage Hi and Lo "
635 "Sidd Failed!", return -EINVAL);
637 if (smu7_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset,
638 (uint8_t *)&smu_data->power_tune_table,
639 (sizeof(struct SMU74_Discrete_PmFuses) - 92), SMC_RAM_END))
640 PP_ASSERT_WITH_CODE(false,
641 "Attempt to download PmFuseTable Failed!",
647 static int polaris10_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
648 SMU74_Discrete_DpmTable *table)
650 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
651 uint32_t count, level;
653 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
654 count = data->mvdd_voltage_table.count;
655 if (count > SMU_MAX_SMIO_LEVELS)
656 count = SMU_MAX_SMIO_LEVELS;
657 for (level = 0; level < count; level++) {
658 table->SmioTable2.Pattern[level].Voltage =
659 PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[level].value * VOLTAGE_SCALE);
660 /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/
661 table->SmioTable2.Pattern[level].Smio =
663 table->Smio[level] |=
664 data->mvdd_voltage_table.entries[level].smio_low;
666 table->SmioMask2 = data->mvdd_voltage_table.mask_low;
668 table->MvddLevelCount = (uint32_t) PP_HOST_TO_SMC_UL(count);
674 static int polaris10_populate_smc_vddc_table(struct pp_hwmgr *hwmgr,
675 struct SMU74_Discrete_DpmTable *table)
677 uint32_t count, level;
678 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
680 count = data->vddc_voltage_table.count;
682 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->voltage_control) {
683 if (count > SMU_MAX_SMIO_LEVELS)
684 count = SMU_MAX_SMIO_LEVELS;
685 for (level = 0; level < count; ++level) {
686 table->SmioTable1.Pattern[level].Voltage =
687 PP_HOST_TO_SMC_US(data->vddc_voltage_table.entries[level].value * VOLTAGE_SCALE);
688 table->SmioTable1.Pattern[level].Smio = (uint8_t) level;
690 table->Smio[level] |= data->vddc_voltage_table.entries[level].smio_low;
693 table->SmioMask1 = data->vddc_voltage_table.mask_low;
699 static int polaris10_populate_smc_vddci_table(struct pp_hwmgr *hwmgr,
700 struct SMU74_Discrete_DpmTable *table)
702 uint32_t count, level;
703 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
705 count = data->vddci_voltage_table.count;
707 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
708 if (count > SMU_MAX_SMIO_LEVELS)
709 count = SMU_MAX_SMIO_LEVELS;
710 for (level = 0; level < count; ++level) {
711 table->SmioTable1.Pattern[level].Voltage =
712 PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[level].value * VOLTAGE_SCALE);
713 table->SmioTable1.Pattern[level].Smio = (uint8_t) level;
715 table->Smio[level] |= data->vddci_voltage_table.entries[level].smio_low;
718 table->SmioMask1 = data->vddci_voltage_table.mask_low;
724 static int polaris10_populate_cac_table(struct pp_hwmgr *hwmgr,
725 struct SMU74_Discrete_DpmTable *table)
729 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
730 struct phm_ppt_v1_information *table_info =
731 (struct phm_ppt_v1_information *)(hwmgr->pptable);
732 struct phm_ppt_v1_voltage_lookup_table *lookup_table =
733 table_info->vddc_lookup_table;
734 /* tables is already swapped, so in order to use the value from it,
735 * we need to swap it back.
736 * We are populating vddc CAC data to BapmVddc table
737 * in split and merged mode
739 for (count = 0; count < lookup_table->count; count++) {
740 index = phm_get_voltage_index(lookup_table,
741 data->vddc_voltage_table.entries[count].value);
742 table->BapmVddcVidLoSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_low);
743 table->BapmVddcVidHiSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_mid);
744 table->BapmVddcVidHiSidd2[count] = convert_to_vid(lookup_table->entries[index].us_cac_high);
750 static int polaris10_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
751 struct SMU74_Discrete_DpmTable *table)
753 polaris10_populate_smc_vddc_table(hwmgr, table);
754 polaris10_populate_smc_vddci_table(hwmgr, table);
755 polaris10_populate_smc_mvdd_table(hwmgr, table);
756 polaris10_populate_cac_table(hwmgr, table);
761 static int polaris10_populate_ulv_level(struct pp_hwmgr *hwmgr,
762 struct SMU74_Discrete_Ulv *state)
764 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
765 struct phm_ppt_v1_information *table_info =
766 (struct phm_ppt_v1_information *)(hwmgr->pptable);
768 state->CcPwrDynRm = 0;
769 state->CcPwrDynRm1 = 0;
771 state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
772 state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *
773 VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
775 if (hwmgr->chip_id == CHIP_POLARIS12 || hwmgr->is_kicker)
776 state->VddcPhase = data->vddc_phase_shed_control ^ 0x3;
778 state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1;
780 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
781 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
782 CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
787 static int polaris10_populate_ulv_state(struct pp_hwmgr *hwmgr,
788 struct SMU74_Discrete_DpmTable *table)
790 return polaris10_populate_ulv_level(hwmgr, &table->Ulv);
793 static int polaris10_populate_smc_link_level(struct pp_hwmgr *hwmgr,
794 struct SMU74_Discrete_DpmTable *table)
796 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
797 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
798 struct smu7_dpm_table *dpm_table = &data->dpm_table;
801 /* Index (dpm_table->pcie_speed_table.count)
802 * is reserved for PCIE boot level. */
803 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
804 table->LinkLevel[i].PcieGenSpeed =
805 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
806 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
807 dpm_table->pcie_speed_table.dpm_levels[i].param1);
808 table->LinkLevel[i].EnabledForActivity = 1;
809 table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
810 table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
811 table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
814 smu_data->smc_state_table.LinkLevelCount =
815 (uint8_t)dpm_table->pcie_speed_table.count;
817 /* To Do move to hwmgr */
818 data->dpm_level_enable_mask.pcie_dpm_enable_mask =
819 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
825 static void polaris10_get_sclk_range_table(struct pp_hwmgr *hwmgr,
826 SMU74_Discrete_DpmTable *table)
828 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
831 struct pp_atom_ctrl_sclk_range_table range_table_from_vbios = { { {0} } };
833 ref_clk = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
835 if (0 == atomctrl_get_smc_sclk_range_table(hwmgr, &range_table_from_vbios)) {
836 for (i = 0; i < NUM_SCLK_RANGE; i++) {
837 table->SclkFcwRangeTable[i].vco_setting = range_table_from_vbios.entry[i].ucVco_setting;
838 table->SclkFcwRangeTable[i].postdiv = range_table_from_vbios.entry[i].ucPostdiv;
839 table->SclkFcwRangeTable[i].fcw_pcc = range_table_from_vbios.entry[i].usFcw_pcc;
841 table->SclkFcwRangeTable[i].fcw_trans_upper = range_table_from_vbios.entry[i].usFcw_trans_upper;
842 table->SclkFcwRangeTable[i].fcw_trans_lower = range_table_from_vbios.entry[i].usRcw_trans_lower;
844 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
845 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
846 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
851 for (i = 0; i < NUM_SCLK_RANGE; i++) {
852 smu_data->range_table[i].trans_lower_frequency = (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv;
853 smu_data->range_table[i].trans_upper_frequency = (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv;
855 table->SclkFcwRangeTable[i].vco_setting = Range_Table[i].vco_setting;
856 table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv;
857 table->SclkFcwRangeTable[i].fcw_pcc = Range_Table[i].fcw_pcc;
859 table->SclkFcwRangeTable[i].fcw_trans_upper = Range_Table[i].fcw_trans_upper;
860 table->SclkFcwRangeTable[i].fcw_trans_lower = Range_Table[i].fcw_trans_lower;
862 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
863 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
864 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
868 static int polaris10_calculate_sclk_params(struct pp_hwmgr *hwmgr,
869 uint32_t clock, SMU_SclkSetting *sclk_setting)
871 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
872 const SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
873 struct pp_atomctrl_clock_dividers_ai dividers;
875 uint32_t pcc_target_percent, pcc_target_freq, ss_target_percent, ss_target_freq;
880 sclk_setting->SclkFrequency = clock;
881 /* get the engine clock dividers for this clock value */
882 result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock, ÷rs);
884 sclk_setting->Fcw_int = dividers.usSclk_fcw_int;
885 sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac;
886 sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int;
887 sclk_setting->PllRange = dividers.ucSclkPllRange;
888 sclk_setting->Sclk_slew_rate = 0x400;
889 sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac;
890 sclk_setting->Pcc_down_slew_rate = 0xffff;
891 sclk_setting->SSc_En = dividers.ucSscEnable;
892 sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int;
893 sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac;
894 sclk_setting->Sclk_ss_slew_rate = dividers.usSsc_fcw_slew_frac;
898 ref_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
900 for (i = 0; i < NUM_SCLK_RANGE; i++) {
901 if (clock > smu_data->range_table[i].trans_lower_frequency
902 && clock <= smu_data->range_table[i].trans_upper_frequency) {
903 sclk_setting->PllRange = i;
908 sclk_setting->Fcw_int = (uint16_t)((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
909 temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
911 do_div(temp, ref_clock);
912 sclk_setting->Fcw_frac = temp & 0xffff;
914 pcc_target_percent = 10; /* Hardcode 10% for now. */
915 pcc_target_freq = clock - (clock * pcc_target_percent / 100);
916 sclk_setting->Pcc_fcw_int = (uint16_t)((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
918 ss_target_percent = 2; /* Hardcode 2% for now. */
919 sclk_setting->SSc_En = 0;
920 if (ss_target_percent) {
921 sclk_setting->SSc_En = 1;
922 ss_target_freq = clock - (clock * ss_target_percent / 100);
923 sclk_setting->Fcw1_int = (uint16_t)((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
924 temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
926 do_div(temp, ref_clock);
927 sclk_setting->Fcw1_frac = temp & 0xffff;
933 static int polaris10_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
934 uint32_t clock, struct SMU74_Discrete_GraphicsLevel *level)
937 /* PP_Clocks minClocks; */
939 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
940 struct phm_ppt_v1_information *table_info =
941 (struct phm_ppt_v1_information *)(hwmgr->pptable);
942 SMU_SclkSetting curr_sclk_setting = { 0 };
943 phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table = NULL;
945 result = polaris10_calculate_sclk_params(hwmgr, clock, &curr_sclk_setting);
947 if (hwmgr->od_enabled)
948 vdd_dep_table = (phm_ppt_v1_clock_voltage_dependency_table *)&data->odn_dpm_table.vdd_dependency_on_sclk;
950 vdd_dep_table = table_info->vdd_dep_on_sclk;
952 /* populate graphics levels */
953 result = polaris10_get_dependency_volt_by_clk(hwmgr,
954 vdd_dep_table, clock,
955 &level->MinVoltage, &mvdd);
957 PP_ASSERT_WITH_CODE((0 == result),
958 "can not find VDDC voltage value for "
959 "VDDC engine clock dependency table",
961 level->ActivityLevel = data->current_profile_setting.sclk_activity;
963 level->CcPwrDynRm = 0;
964 level->CcPwrDynRm1 = 0;
965 level->EnabledForActivity = 0;
966 level->EnabledForThrottle = 1;
967 level->UpHyst = data->current_profile_setting.sclk_up_hyst;
968 level->DownHyst = data->current_profile_setting.sclk_down_hyst;
969 level->VoltageDownHyst = 0;
970 level->PowerThrottle = 0;
971 data->display_timing.min_clock_in_sr = hwmgr->display_config->min_core_set_clock_in_sr;
973 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
974 level->DeepSleepDivId = smu7_get_sleep_divider_id_from_clock(clock,
975 hwmgr->display_config->min_core_set_clock_in_sr);
977 /* Default to slow, highest DPM level will be
978 * set to PPSMC_DISPLAY_WATERMARK_LOW later.
980 if (data->update_up_hyst)
981 level->UpHyst = (uint8_t)data->up_hyst;
982 if (data->update_down_hyst)
983 level->DownHyst = (uint8_t)data->down_hyst;
985 level->SclkSetting = curr_sclk_setting;
987 CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage);
988 CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm);
989 CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1);
990 CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel);
991 CONVERT_FROM_HOST_TO_SMC_UL(level->SclkSetting.SclkFrequency);
992 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_int);
993 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_frac);
994 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_fcw_int);
995 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_slew_rate);
996 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_up_slew_rate);
997 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_down_slew_rate);
998 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_int);
999 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_frac);
1000 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_ss_slew_rate);
1004 static int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
1006 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1007 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1008 struct smu7_dpm_table *dpm_table = &hw_data->dpm_table;
1009 struct phm_ppt_v1_information *table_info =
1010 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1011 struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
1012 uint8_t pcie_entry_cnt = (uint8_t) hw_data->dpm_table.pcie_speed_table.count;
1014 uint32_t array = smu_data->smu7_data.dpm_table_start +
1015 offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
1016 uint32_t array_size = sizeof(struct SMU74_Discrete_GraphicsLevel) *
1017 SMU74_MAX_LEVELS_GRAPHICS;
1018 struct SMU74_Discrete_GraphicsLevel *levels =
1019 smu_data->smc_state_table.GraphicsLevel;
1020 uint32_t i, max_entry;
1021 uint8_t hightest_pcie_level_enabled = 0,
1022 lowest_pcie_level_enabled = 0,
1023 mid_pcie_level_enabled = 0,
1026 polaris10_get_sclk_range_table(hwmgr, &(smu_data->smc_state_table));
1028 for (i = 0; i < dpm_table->sclk_table.count; i++) {
1030 result = polaris10_populate_single_graphic_level(hwmgr,
1031 dpm_table->sclk_table.dpm_levels[i].value,
1032 &(smu_data->smc_state_table.GraphicsLevel[i]));
1036 /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
1038 levels[i].DeepSleepDivId = 0;
1040 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1041 PHM_PlatformCaps_SPLLShutdownSupport))
1042 smu_data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0;
1044 smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
1045 smu_data->smc_state_table.GraphicsDpmLevelCount =
1046 (uint8_t)dpm_table->sclk_table.count;
1047 hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask =
1048 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
1051 if (pcie_table != NULL) {
1052 PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),
1053 "There must be 1 or more PCIE levels defined in PPTable.",
1055 max_entry = pcie_entry_cnt - 1;
1056 for (i = 0; i < dpm_table->sclk_table.count; i++)
1057 levels[i].pcieDpmLevel =
1058 (uint8_t) ((i < max_entry) ? i : max_entry);
1060 while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1061 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1062 (1 << (hightest_pcie_level_enabled + 1))) != 0))
1063 hightest_pcie_level_enabled++;
1065 while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1066 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1067 (1 << lowest_pcie_level_enabled)) == 0))
1068 lowest_pcie_level_enabled++;
1070 while ((count < hightest_pcie_level_enabled) &&
1071 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1072 (1 << (lowest_pcie_level_enabled + 1 + count))) == 0))
1075 mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1 + count) <
1076 hightest_pcie_level_enabled ?
1077 (lowest_pcie_level_enabled + 1 + count) :
1078 hightest_pcie_level_enabled;
1080 /* set pcieDpmLevel to hightest_pcie_level_enabled */
1081 for (i = 2; i < dpm_table->sclk_table.count; i++)
1082 levels[i].pcieDpmLevel = hightest_pcie_level_enabled;
1084 /* set pcieDpmLevel to lowest_pcie_level_enabled */
1085 levels[0].pcieDpmLevel = lowest_pcie_level_enabled;
1087 /* set pcieDpmLevel to mid_pcie_level_enabled */
1088 levels[1].pcieDpmLevel = mid_pcie_level_enabled;
1090 /* level count will send to smc once at init smc table and never change */
1091 result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
1092 (uint32_t)array_size, SMC_RAM_END);
1098 static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
1099 uint32_t clock, struct SMU74_Discrete_MemoryLevel *mem_level)
1101 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1102 struct phm_ppt_v1_information *table_info =
1103 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1105 uint32_t mclk_stutter_mode_threshold = 40000;
1106 phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table = NULL;
1109 if (hwmgr->od_enabled)
1110 vdd_dep_table = (phm_ppt_v1_clock_voltage_dependency_table *)&data->odn_dpm_table.vdd_dependency_on_mclk;
1112 vdd_dep_table = table_info->vdd_dep_on_mclk;
1114 if (vdd_dep_table) {
1115 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1116 vdd_dep_table, clock,
1117 &mem_level->MinVoltage, &mem_level->MinMvdd);
1118 PP_ASSERT_WITH_CODE((0 == result),
1119 "can not find MinVddc voltage value from memory "
1120 "VDDC voltage dependency table", return result);
1123 mem_level->MclkFrequency = clock;
1124 mem_level->EnabledForThrottle = 1;
1125 mem_level->EnabledForActivity = 0;
1126 mem_level->UpHyst = data->current_profile_setting.mclk_up_hyst;
1127 mem_level->DownHyst = data->current_profile_setting.mclk_down_hyst;
1128 mem_level->VoltageDownHyst = 0;
1129 mem_level->ActivityLevel = data->current_profile_setting.mclk_activity;
1130 mem_level->StutterEnable = false;
1131 mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1133 data->display_timing.num_existing_displays = hwmgr->display_config->num_display;
1134 data->display_timing.vrefresh = hwmgr->display_config->vrefresh;
1136 if (mclk_stutter_mode_threshold &&
1137 (clock <= mclk_stutter_mode_threshold) &&
1138 (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
1139 STUTTER_ENABLE) & 0x1))
1140 mem_level->StutterEnable = true;
1143 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd);
1144 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency);
1145 CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel);
1146 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage);
1151 static int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1153 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1154 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1155 struct smu7_dpm_table *dpm_table = &hw_data->dpm_table;
1157 /* populate MCLK dpm table to SMU7 */
1158 uint32_t array = smu_data->smu7_data.dpm_table_start +
1159 offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
1160 uint32_t array_size = sizeof(SMU74_Discrete_MemoryLevel) *
1161 SMU74_MAX_LEVELS_MEMORY;
1162 struct SMU74_Discrete_MemoryLevel *levels =
1163 smu_data->smc_state_table.MemoryLevel;
1166 for (i = 0; i < dpm_table->mclk_table.count; i++) {
1167 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
1168 "can not populate memory level as memory clock is zero",
1170 result = polaris10_populate_single_memory_level(hwmgr,
1171 dpm_table->mclk_table.dpm_levels[i].value,
1173 if (i == dpm_table->mclk_table.count - 1) {
1174 levels[i].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
1175 levels[i].EnabledForActivity = 1;
1181 /* In order to prevent MC activity from stutter mode to push DPM up,
1182 * the UVD change complements this by putting the MCLK in
1183 * a higher state by default such that we are not affected by
1184 * up threshold or and MCLK DPM latency.
1186 levels[0].ActivityLevel = 0x1f;
1187 CONVERT_FROM_HOST_TO_SMC_US(levels[0].ActivityLevel);
1189 smu_data->smc_state_table.MemoryDpmLevelCount =
1190 (uint8_t)dpm_table->mclk_table.count;
1191 hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask =
1192 phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
1194 /* level count will send to smc once at init smc table and never change */
1195 result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
1196 (uint32_t)array_size, SMC_RAM_END);
1201 static int polaris10_populate_mvdd_value(struct pp_hwmgr *hwmgr,
1202 uint32_t mclk, SMIO_Pattern *smio_pat)
1204 const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1205 struct phm_ppt_v1_information *table_info =
1206 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1209 if (SMU7_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
1210 /* find mvdd value which clock is more than request */
1211 for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
1212 if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
1213 smio_pat->Voltage = data->mvdd_voltage_table.entries[i].value;
1217 PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
1218 "MVDD Voltage is outside the supported range.",
1226 static int polaris10_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
1227 SMU74_Discrete_DpmTable *table)
1230 uint32_t sclk_frequency;
1231 const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1232 struct phm_ppt_v1_information *table_info =
1233 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1234 SMIO_Pattern vol_level;
1237 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
1239 /* Get MinVoltage and Frequency from DPM0,
1240 * already converted to SMC_UL */
1241 sclk_frequency = data->vbios_boot_state.sclk_bootup_value;
1242 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1243 table_info->vdd_dep_on_sclk,
1245 &table->ACPILevel.MinVoltage, &mvdd);
1246 PP_ASSERT_WITH_CODE((0 == result),
1247 "Cannot find ACPI VDDC voltage value "
1248 "in Clock Dependency Table",
1251 result = polaris10_calculate_sclk_params(hwmgr, sclk_frequency, &(table->ACPILevel.SclkSetting));
1252 PP_ASSERT_WITH_CODE(result == 0, "Error retrieving Engine Clock dividers from VBIOS.", return result);
1254 table->ACPILevel.DeepSleepDivId = 0;
1255 table->ACPILevel.CcPwrDynRm = 0;
1256 table->ACPILevel.CcPwrDynRm1 = 0;
1258 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
1259 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);
1260 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
1261 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
1263 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkSetting.SclkFrequency);
1264 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_int);
1265 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_frac);
1266 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_fcw_int);
1267 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_slew_rate);
1268 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_up_slew_rate);
1269 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_down_slew_rate);
1270 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_int);
1271 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_frac);
1272 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_ss_slew_rate);
1275 /* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */
1276 table->MemoryACPILevel.MclkFrequency = data->vbios_boot_state.mclk_bootup_value;
1277 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1278 table_info->vdd_dep_on_mclk,
1279 table->MemoryACPILevel.MclkFrequency,
1280 &table->MemoryACPILevel.MinVoltage, &mvdd);
1281 PP_ASSERT_WITH_CODE((0 == result),
1282 "Cannot find ACPI VDDCI voltage value "
1283 "in Clock Dependency Table",
1286 if (!((SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control) ||
1287 (data->mclk_dpm_key_disabled)))
1288 polaris10_populate_mvdd_value(hwmgr,
1289 data->dpm_table.mclk_table.dpm_levels[0].value,
1292 if (0 == polaris10_populate_mvdd_value(hwmgr, 0, &vol_level))
1293 table->MemoryACPILevel.MinMvdd = PP_HOST_TO_SMC_UL(vol_level.Voltage);
1295 table->MemoryACPILevel.MinMvdd = 0;
1297 table->MemoryACPILevel.StutterEnable = false;
1299 table->MemoryACPILevel.EnabledForThrottle = 0;
1300 table->MemoryACPILevel.EnabledForActivity = 0;
1301 table->MemoryACPILevel.UpHyst = 0;
1302 table->MemoryACPILevel.DownHyst = 100;
1303 table->MemoryACPILevel.VoltageDownHyst = 0;
1304 table->MemoryACPILevel.ActivityLevel =
1305 PP_HOST_TO_SMC_US(data->current_profile_setting.mclk_activity);
1307 CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
1308 CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);
1313 static int polaris10_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
1314 SMU74_Discrete_DpmTable *table)
1316 int result = -EINVAL;
1318 struct pp_atomctrl_clock_dividers_vi dividers;
1319 struct phm_ppt_v1_information *table_info =
1320 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1321 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1322 table_info->mm_dep_table;
1323 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1326 table->VceLevelCount = (uint8_t)(mm_table->count);
1327 table->VceBootLevel = 0;
1329 for (count = 0; count < table->VceLevelCount; count++) {
1330 table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
1331 table->VceLevel[count].MinVoltage = 0;
1332 table->VceLevel[count].MinVoltage |=
1333 (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1335 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
1336 vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
1337 mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
1338 else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
1339 vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
1341 vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
1344 table->VceLevel[count].MinVoltage |=
1345 (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1346 table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1348 /*retrieve divider value for VBIOS */
1349 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1350 table->VceLevel[count].Frequency, ÷rs);
1351 PP_ASSERT_WITH_CODE((0 == result),
1352 "can not find divide id for VCE engine clock",
1355 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1357 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
1358 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);
1363 static int polaris10_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
1364 SMU74_Discrete_DpmTable *table)
1366 int result = -EINVAL;
1368 struct pp_atomctrl_clock_dividers_vi dividers;
1369 struct phm_ppt_v1_information *table_info =
1370 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1371 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1372 table_info->mm_dep_table;
1373 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1376 table->SamuLevelCount = (uint8_t)(mm_table->count);
1377 table->SamuBootLevel = 0;
1379 for (count = 0; count < table->SamuLevelCount; count++) {
1380 table->SamuLevel[count].Frequency = mm_table->entries[count].samclock;
1381 table->SamuLevel[count].MinVoltage |=
1382 (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1384 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
1385 vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
1386 mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
1387 else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
1388 vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
1390 vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
1393 table->SamuLevel[count].MinVoltage |=
1394 (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1395 table->SamuLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1397 /*retrieve divider value for VBIOS */
1398 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1399 table->SamuLevel[count].Frequency, ÷rs);
1400 PP_ASSERT_WITH_CODE((0 == result),
1401 "can not find divide id for VCE engine clock",
1404 table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1406 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
1407 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].MinVoltage);
1412 static int polaris10_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
1413 int32_t eng_clock, int32_t mem_clock,
1414 SMU74_Discrete_MCArbDramTimingTableEntry *arb_regs)
1416 uint32_t dram_timing;
1417 uint32_t dram_timing2;
1418 uint32_t burst_time;
1421 result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
1422 eng_clock, mem_clock);
1423 PP_ASSERT_WITH_CODE(result == 0,
1424 "Error calling VBIOS to set DRAM_TIMING.", return result);
1426 dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
1427 dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
1428 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
1431 arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dram_timing);
1432 arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);
1433 arb_regs->McArbBurstTime = (uint8_t)burst_time;
1438 static int polaris10_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
1440 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1441 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1442 struct SMU74_Discrete_MCArbDramTimingTable arb_regs;
1446 for (i = 0; i < hw_data->dpm_table.sclk_table.count; i++) {
1447 for (j = 0; j < hw_data->dpm_table.mclk_table.count; j++) {
1448 result = polaris10_populate_memory_timing_parameters(hwmgr,
1449 hw_data->dpm_table.sclk_table.dpm_levels[i].value,
1450 hw_data->dpm_table.mclk_table.dpm_levels[j].value,
1451 &arb_regs.entries[i][j]);
1453 result = atomctrl_set_ac_timing_ai(hwmgr, hw_data->dpm_table.mclk_table.dpm_levels[j].value, j);
1459 result = smu7_copy_bytes_to_smc(
1461 smu_data->smu7_data.arb_table_start,
1462 (uint8_t *)&arb_regs,
1463 sizeof(SMU74_Discrete_MCArbDramTimingTable),
1468 static int polaris10_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
1469 struct SMU74_Discrete_DpmTable *table)
1471 int result = -EINVAL;
1473 struct pp_atomctrl_clock_dividers_vi dividers;
1474 struct phm_ppt_v1_information *table_info =
1475 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1476 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1477 table_info->mm_dep_table;
1478 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1481 table->UvdLevelCount = (uint8_t)(mm_table->count);
1482 table->UvdBootLevel = 0;
1484 for (count = 0; count < table->UvdLevelCount; count++) {
1485 table->UvdLevel[count].MinVoltage = 0;
1486 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
1487 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
1488 table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
1489 VOLTAGE_SCALE) << VDDC_SHIFT;
1491 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
1492 vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
1493 mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
1494 else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
1495 vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
1497 vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
1499 table->UvdLevel[count].MinVoltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1500 table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1502 /* retrieve divider value for VBIOS */
1503 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1504 table->UvdLevel[count].VclkFrequency, ÷rs);
1505 PP_ASSERT_WITH_CODE((0 == result),
1506 "can not find divide id for Vclk clock", return result);
1508 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
1510 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1511 table->UvdLevel[count].DclkFrequency, ÷rs);
1512 PP_ASSERT_WITH_CODE((0 == result),
1513 "can not find divide id for Dclk clock", return result);
1515 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
1517 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
1518 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
1519 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);
1525 static int polaris10_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
1526 struct SMU74_Discrete_DpmTable *table)
1529 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1531 table->GraphicsBootLevel = 0;
1532 table->MemoryBootLevel = 0;
1534 /* find boot level from dpm table */
1535 result = phm_find_boot_level(&(data->dpm_table.sclk_table),
1536 data->vbios_boot_state.sclk_bootup_value,
1537 (uint32_t *)&(table->GraphicsBootLevel));
1539 result = phm_find_boot_level(&(data->dpm_table.mclk_table),
1540 data->vbios_boot_state.mclk_bootup_value,
1541 (uint32_t *)&(table->MemoryBootLevel));
1543 table->BootVddc = data->vbios_boot_state.vddc_bootup_value *
1545 table->BootVddci = data->vbios_boot_state.vddci_bootup_value *
1547 table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value *
1550 CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc);
1551 CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci);
1552 CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
1557 static int polaris10_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
1559 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1560 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1561 struct phm_ppt_v1_information *table_info =
1562 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1563 uint8_t count, level;
1565 count = (uint8_t)(table_info->vdd_dep_on_sclk->count);
1567 for (level = 0; level < count; level++) {
1568 if (table_info->vdd_dep_on_sclk->entries[level].clk >=
1569 hw_data->vbios_boot_state.sclk_bootup_value) {
1570 smu_data->smc_state_table.GraphicsBootLevel = level;
1575 count = (uint8_t)(table_info->vdd_dep_on_mclk->count);
1576 for (level = 0; level < count; level++) {
1577 if (table_info->vdd_dep_on_mclk->entries[level].clk >=
1578 hw_data->vbios_boot_state.mclk_bootup_value) {
1579 smu_data->smc_state_table.MemoryBootLevel = level;
1587 static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
1589 uint32_t ro, efuse, volt_without_cks, volt_with_cks, value, max, min;
1590 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1592 uint8_t i, stretch_amount, volt_offset = 0;
1593 struct phm_ppt_v1_information *table_info =
1594 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1595 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1596 table_info->vdd_dep_on_sclk;
1598 stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
1600 /* Read SMU_Eefuse to read and calculate RO and determine
1601 * if the part is SS or FF. if RO >= 1660MHz, part is FF.
1603 efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1604 ixSMU_EFUSE_0 + (67 * 4));
1605 efuse &= 0xFF000000;
1606 efuse = efuse >> 24;
1608 if (hwmgr->chip_id == CHIP_POLARIS10) {
1609 if (hwmgr->is_kicker) {
1616 } else if (hwmgr->chip_id == CHIP_POLARIS11) {
1617 if (hwmgr->is_kicker) {
1629 ro = efuse * (max - min) / 255 + min;
1631 /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
1632 for (i = 0; i < sclk_table->count; i++) {
1633 smu_data->smc_state_table.Sclk_CKS_masterEn0_7 |=
1634 sclk_table->entries[i].cks_enable << i;
1635 if (hwmgr->chip_id == CHIP_POLARIS10) {
1636 volt_without_cks = (uint32_t)((2753594000U + (sclk_table->entries[i].clk/100) * 136418 - (ro - 70) * 1000000) / \
1637 (2424180 - (sclk_table->entries[i].clk/100) * 1132925/1000));
1638 volt_with_cks = (uint32_t)((2797202000U + sclk_table->entries[i].clk/100 * 3232 - (ro - 65) * 1000000) / \
1639 (2522480 - sclk_table->entries[i].clk/100 * 115764/100));
1641 volt_without_cks = (uint32_t)((2416794800U + (sclk_table->entries[i].clk/100) * 1476925/10 - (ro - 50) * 1000000) / \
1642 (2625416 - (sclk_table->entries[i].clk/100) * (12586807/10000)));
1643 volt_with_cks = (uint32_t)((2999656000U - sclk_table->entries[i].clk/100 * 392803 - (ro - 44) * 1000000) / \
1644 (3422454 - sclk_table->entries[i].clk/100 * (18886376/10000)));
1647 if (volt_without_cks >= volt_with_cks)
1648 volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
1649 sclk_table->entries[i].cks_voffset) * 100 + 624) / 625);
1651 smu_data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
1654 smu_data->smc_state_table.LdoRefSel = (table_info->cac_dtp_table->ucCKS_LDO_REFSEL != 0) ? table_info->cac_dtp_table->ucCKS_LDO_REFSEL : 6;
1655 /* Populate CKS Lookup Table */
1656 if (stretch_amount == 0 || stretch_amount > 5) {
1657 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1658 PHM_PlatformCaps_ClockStretcher);
1659 PP_ASSERT_WITH_CODE(false,
1660 "Stretch Amount in PPTable not supported",
1664 value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
1665 value &= 0xFFFFFFFE;
1666 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value);
1671 static int polaris10_populate_vr_config(struct pp_hwmgr *hwmgr,
1672 struct SMU74_Discrete_DpmTable *table)
1674 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1675 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1678 config = VR_MERGED_WITH_VDDC;
1679 table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);
1681 /* Set Vddc Voltage Controller */
1682 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1683 config = VR_SVI2_PLANE_1;
1684 table->VRConfig |= config;
1686 PP_ASSERT_WITH_CODE(false,
1687 "VDDC should be on SVI2 control in merged mode!",
1690 /* Set Vddci Voltage Controller */
1691 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
1692 config = VR_SVI2_PLANE_2; /* only in merged mode */
1693 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1694 } else if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
1695 config = VR_SMIO_PATTERN_1;
1696 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1698 config = VR_STATIC_VOLTAGE;
1699 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1701 /* Set Mvdd Voltage Controller */
1702 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
1703 config = VR_SVI2_PLANE_2;
1704 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1705 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, smu_data->smu7_data.soft_regs_start +
1706 offsetof(SMU74_SoftRegisters, AllowMvddSwitch), 0x1);
1708 config = VR_STATIC_VOLTAGE;
1709 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1716 static int polaris10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
1718 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1719 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1720 struct amdgpu_device *adev = hwmgr->adev;
1722 SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
1724 struct pp_atom_ctrl__avfs_parameters avfs_params = {0};
1725 AVFS_meanNsigma_t AVFS_meanNsigma = { {0} };
1726 AVFS_Sclk_Offset_t AVFS_SclkOffset = { {0} };
1729 struct phm_ppt_v1_information *table_info =
1730 (struct phm_ppt_v1_information *)hwmgr->pptable;
1731 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1732 table_info->vdd_dep_on_sclk;
1735 if (!hwmgr->avfs_supported)
1738 result = atomctrl_get_avfs_information(hwmgr, &avfs_params);
1741 if (((adev->pdev->device == 0x67ef) &&
1742 ((adev->pdev->revision == 0xe0) ||
1743 (adev->pdev->revision == 0xe5))) ||
1744 ((adev->pdev->device == 0x67ff) &&
1745 ((adev->pdev->revision == 0xcf) ||
1746 (adev->pdev->revision == 0xef) ||
1747 (adev->pdev->revision == 0xff)))) {
1748 avfs_params.ucEnableApplyAVFS_CKS_OFF_Voltage = 1;
1749 if ((adev->pdev->device == 0x67ef && adev->pdev->revision == 0xe5) ||
1750 (adev->pdev->device == 0x67ff && adev->pdev->revision == 0xef)) {
1751 if ((avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0 == 0xEA522DD3) &&
1752 (avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1 == 0x5645A) &&
1753 (avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2 == 0x33F9E) &&
1754 (avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1 == 0xFFFFC5CC) &&
1755 (avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2 == 0x1B1A) &&
1756 (avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b == 0xFFFFFCED)) {
1757 avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0 = 0xF718F1D4;
1758 avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1 = 0x323FD;
1759 avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2 = 0x1E455;
1760 avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1 = 0;
1761 avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2 = 0;
1762 avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b = 0x23;
1765 } else if (hwmgr->chip_id == CHIP_POLARIS12 && !hwmgr->is_kicker) {
1766 avfs_params.ucEnableApplyAVFS_CKS_OFF_Voltage = 1;
1767 avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0 = 0xF6B024DD;
1768 avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1 = 0x3005E;
1769 avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2 = 0x18A5F;
1770 avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1 = 0x315;
1771 avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2 = 0xFED1;
1772 avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b = 0x3B;
1773 } else if (((adev->pdev->device == 0x67df) &&
1774 ((adev->pdev->revision == 0xe0) ||
1775 (adev->pdev->revision == 0xe3) ||
1776 (adev->pdev->revision == 0xe4) ||
1777 (adev->pdev->revision == 0xe5) ||
1778 (adev->pdev->revision == 0xe7) ||
1779 (adev->pdev->revision == 0xef))) ||
1780 ((adev->pdev->device == 0x6fdf) &&
1781 ((adev->pdev->revision == 0xef) ||
1782 (adev->pdev->revision == 0xff)))) {
1783 avfs_params.ucEnableApplyAVFS_CKS_OFF_Voltage = 1;
1784 avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0 = 0xF843B66B;
1785 avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1 = 0x59CB5;
1786 avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2 = 0xFFFF287F;
1787 avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1 = 0;
1788 avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2 = 0xFF23;
1789 avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b = 0x58;
1794 table->BTCGB_VDROOP_TABLE[0].a0 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a0);
1795 table->BTCGB_VDROOP_TABLE[0].a1 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a1);
1796 table->BTCGB_VDROOP_TABLE[0].a2 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a2);
1797 table->BTCGB_VDROOP_TABLE[1].a0 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0);
1798 table->BTCGB_VDROOP_TABLE[1].a1 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1);
1799 table->BTCGB_VDROOP_TABLE[1].a2 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2);
1800 table->AVFSGB_VDROOP_TABLE[0].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_m1);
1801 table->AVFSGB_VDROOP_TABLE[0].m2 = PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSON_m2);
1802 table->AVFSGB_VDROOP_TABLE[0].b = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_b);
1803 table->AVFSGB_VDROOP_TABLE[0].m1_shift = 24;
1804 table->AVFSGB_VDROOP_TABLE[0].m2_shift = 12;
1805 table->AVFSGB_VDROOP_TABLE[1].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1);
1806 table->AVFSGB_VDROOP_TABLE[1].m2 = PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2);
1807 table->AVFSGB_VDROOP_TABLE[1].b = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b);
1808 table->AVFSGB_VDROOP_TABLE[1].m1_shift = 24;
1809 table->AVFSGB_VDROOP_TABLE[1].m2_shift = 12;
1810 table->MaxVoltage = PP_HOST_TO_SMC_US(avfs_params.usMaxVoltage_0_25mv);
1811 AVFS_meanNsigma.Aconstant[0] = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant0);
1812 AVFS_meanNsigma.Aconstant[1] = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant1);
1813 AVFS_meanNsigma.Aconstant[2] = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant2);
1814 AVFS_meanNsigma.DC_tol_sigma = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_DC_tol_sigma);
1815 AVFS_meanNsigma.Platform_mean = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_mean);
1816 AVFS_meanNsigma.PSM_Age_CompFactor = PP_HOST_TO_SMC_US(avfs_params.usPSM_Age_ComFactor);
1817 AVFS_meanNsigma.Platform_sigma = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_sigma);
1819 for (i = 0; i < NUM_VFT_COLUMNS; i++) {
1820 AVFS_meanNsigma.Static_Voltage_Offset[i] = (uint8_t)(sclk_table->entries[i].cks_voffset * 100 / 625);
1821 AVFS_SclkOffset.Sclk_Offset[i] = PP_HOST_TO_SMC_US((uint16_t)(sclk_table->entries[i].sclk_offset) / 100);
1824 result = smu7_read_smc_sram_dword(hwmgr,
1825 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsMeanNSigma),
1828 smu7_copy_bytes_to_smc(hwmgr,
1830 (uint8_t *)&AVFS_meanNsigma,
1831 sizeof(AVFS_meanNsigma_t),
1834 result = smu7_read_smc_sram_dword(hwmgr,
1835 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsSclkOffsetTable),
1837 smu7_copy_bytes_to_smc(hwmgr,
1839 (uint8_t *)&AVFS_SclkOffset,
1840 sizeof(AVFS_Sclk_Offset_t),
1843 data->avfs_vdroop_override_setting = (avfs_params.ucEnableGB_VDROOP_TABLE_CKSON << BTCGB0_Vdroop_Enable_SHIFT) |
1844 (avfs_params.ucEnableGB_VDROOP_TABLE_CKSOFF << BTCGB1_Vdroop_Enable_SHIFT) |
1845 (avfs_params.ucEnableGB_FUSE_TABLE_CKSON << AVFSGB0_Vdroop_Enable_SHIFT) |
1846 (avfs_params.ucEnableGB_FUSE_TABLE_CKSOFF << AVFSGB1_Vdroop_Enable_SHIFT);
1847 data->apply_avfs_cks_off_voltage = (avfs_params.ucEnableApplyAVFS_CKS_OFF_Voltage == 1) ? true : false;
1852 static int polaris10_init_arb_table_index(struct pp_hwmgr *hwmgr)
1854 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1858 /* This is a read-modify-write on the first byte of the ARB table.
1859 * The first byte in the SMU73_Discrete_MCArbDramTimingTable structure
1860 * is the field 'current'.
1861 * This solution is ugly, but we never write the whole table only
1862 * individual fields in it.
1863 * In reality this field should not be in that structure
1864 * but in a soft register.
1866 result = smu7_read_smc_sram_dword(hwmgr,
1867 smu_data->smu7_data.arb_table_start, &tmp, SMC_RAM_END);
1873 tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
1875 return smu7_write_smc_sram_dword(hwmgr,
1876 smu_data->smu7_data.arb_table_start, tmp, SMC_RAM_END);
1879 static void polaris10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
1881 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1882 struct phm_ppt_v1_information *table_info =
1883 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1886 table_info->cac_dtp_table->usPowerTuneDataSetID <= POWERTUNE_DEFAULT_SET_MAX &&
1887 table_info->cac_dtp_table->usPowerTuneDataSetID)
1888 smu_data->power_tune_defaults =
1889 &polaris10_power_tune_data_set_array
1890 [table_info->cac_dtp_table->usPowerTuneDataSetID - 1];
1892 smu_data->power_tune_defaults = &polaris10_power_tune_data_set_array[0];
1896 static int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
1899 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1900 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1902 struct phm_ppt_v1_information *table_info =
1903 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1904 struct SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
1906 struct pp_atomctrl_gpio_pin_assignment gpio_pin;
1907 pp_atomctrl_clock_dividers_vi dividers;
1909 polaris10_initialize_power_tune_defaults(hwmgr);
1911 if (SMU7_VOLTAGE_CONTROL_NONE != hw_data->voltage_control)
1912 polaris10_populate_smc_voltage_tables(hwmgr, table);
1914 table->SystemFlags = 0;
1915 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1916 PHM_PlatformCaps_AutomaticDCTransition))
1917 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
1919 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1920 PHM_PlatformCaps_StepVddc))
1921 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
1923 if (hw_data->is_memory_gddr5)
1924 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
1926 if (hw_data->ulv_supported && table_info->us_ulv_voltage_offset) {
1927 result = polaris10_populate_ulv_state(hwmgr, table);
1928 PP_ASSERT_WITH_CODE(0 == result,
1929 "Failed to initialize ULV state!", return result);
1930 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1931 ixCG_ULV_PARAMETER, SMU7_CGULVPARAMETER_DFLT);
1934 result = polaris10_populate_smc_link_level(hwmgr, table);
1935 PP_ASSERT_WITH_CODE(0 == result,
1936 "Failed to initialize Link Level!", return result);
1938 result = polaris10_populate_all_graphic_levels(hwmgr);
1939 PP_ASSERT_WITH_CODE(0 == result,
1940 "Failed to initialize Graphics Level!", return result);
1942 result = polaris10_populate_all_memory_levels(hwmgr);
1943 PP_ASSERT_WITH_CODE(0 == result,
1944 "Failed to initialize Memory Level!", return result);
1946 result = polaris10_populate_smc_acpi_level(hwmgr, table);
1947 PP_ASSERT_WITH_CODE(0 == result,
1948 "Failed to initialize ACPI Level!", return result);
1950 result = polaris10_populate_smc_vce_level(hwmgr, table);
1951 PP_ASSERT_WITH_CODE(0 == result,
1952 "Failed to initialize VCE Level!", return result);
1954 result = polaris10_populate_smc_samu_level(hwmgr, table);
1955 PP_ASSERT_WITH_CODE(0 == result,
1956 "Failed to initialize SAMU Level!", return result);
1958 /* Since only the initial state is completely set up at this point
1959 * (the other states are just copies of the boot state) we only
1960 * need to populate the ARB settings for the initial state.
1962 result = polaris10_program_memory_timing_parameters(hwmgr);
1963 PP_ASSERT_WITH_CODE(0 == result,
1964 "Failed to Write ARB settings for the initial state.", return result);
1966 result = polaris10_populate_smc_uvd_level(hwmgr, table);
1967 PP_ASSERT_WITH_CODE(0 == result,
1968 "Failed to initialize UVD Level!", return result);
1970 result = polaris10_populate_smc_boot_level(hwmgr, table);
1971 PP_ASSERT_WITH_CODE(0 == result,
1972 "Failed to initialize Boot Level!", return result);
1974 result = polaris10_populate_smc_initailial_state(hwmgr);
1975 PP_ASSERT_WITH_CODE(0 == result,
1976 "Failed to initialize Boot State!", return result);
1978 result = polaris10_populate_bapm_parameters_in_dpm_table(hwmgr);
1979 PP_ASSERT_WITH_CODE(0 == result,
1980 "Failed to populate BAPM Parameters!", return result);
1982 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1983 PHM_PlatformCaps_ClockStretcher)) {
1984 result = polaris10_populate_clock_stretcher_data_table(hwmgr);
1985 PP_ASSERT_WITH_CODE(0 == result,
1986 "Failed to populate Clock Stretcher Data Table!",
1990 result = polaris10_populate_avfs_parameters(hwmgr);
1991 PP_ASSERT_WITH_CODE(0 == result, "Failed to populate AVFS Parameters!", return result;);
1993 table->CurrSclkPllRange = 0xff;
1994 table->GraphicsVoltageChangeEnable = 1;
1995 table->GraphicsThermThrottleEnable = 1;
1996 table->GraphicsInterval = 1;
1997 table->VoltageInterval = 1;
1998 table->ThermalInterval = 1;
1999 table->TemperatureLimitHigh =
2000 table_info->cac_dtp_table->usTargetOperatingTemp *
2001 SMU7_Q88_FORMAT_CONVERSION_UNIT;
2002 table->TemperatureLimitLow =
2003 (table_info->cac_dtp_table->usTargetOperatingTemp - 1) *
2004 SMU7_Q88_FORMAT_CONVERSION_UNIT;
2005 table->MemoryVoltageChangeEnable = 1;
2006 table->MemoryInterval = 1;
2007 table->VoltageResponseTime = 0;
2008 table->PhaseResponseTime = 0;
2009 table->MemoryThermThrottleEnable = 1;
2010 table->PCIeBootLinkLevel = 0;
2011 table->PCIeGenInterval = 1;
2012 table->VRConfig = 0;
2014 result = polaris10_populate_vr_config(hwmgr, table);
2015 PP_ASSERT_WITH_CODE(0 == result,
2016 "Failed to populate VRConfig setting!", return result);
2017 hw_data->vr_config = table->VRConfig;
2018 table->ThermGpio = 17;
2019 table->SclkStepSize = 0x4000;
2021 if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) {
2022 table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;
2024 table->VRHotGpio = SMU7_UNUSED_GPIO_PIN;
2025 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2026 PHM_PlatformCaps_RegulatorHot);
2029 if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID,
2031 table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift;
2032 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2033 PHM_PlatformCaps_AutomaticDCTransition);
2035 table->AcDcGpio = SMU7_UNUSED_GPIO_PIN;
2036 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2037 PHM_PlatformCaps_AutomaticDCTransition);
2040 /* Thermal Output GPIO */
2041 if (atomctrl_get_pp_assign_pin(hwmgr, THERMAL_INT_OUTPUT_GPIO_PINID,
2043 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2044 PHM_PlatformCaps_ThermalOutGPIO);
2046 table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift;
2048 /* For porlarity read GPIOPAD_A with assigned Gpio pin
2049 * since VBIOS will program this register to set 'inactive state',
2050 * driver can then determine 'active state' from this and
2051 * program SMU with correct polarity
2053 table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A)
2054 & (1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0;
2055 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
2057 /* if required, combine VRHot/PCC with thermal out GPIO */
2058 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_RegulatorHot)
2059 && phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_CombinePCCWithThermalSignal))
2060 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
2062 table->ThermOutGpio = 17;
2063 table->ThermOutPolarity = 1;
2064 table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
2067 /* Populate BIF_SCLK levels into SMC DPM table */
2068 for (i = 0; i <= hw_data->dpm_table.pcie_speed_table.count; i++) {
2069 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, smu_data->bif_sclk_table[i], ÷rs);
2070 PP_ASSERT_WITH_CODE((result == 0), "Can not find DFS divide id for Sclk", return result);
2073 table->Ulv.BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
2075 table->LinkLevel[i-1].BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
2078 for (i = 0; i < SMU74_MAX_ENTRIES_SMIO; i++)
2079 table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
2081 CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
2082 CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
2083 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
2084 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
2085 CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
2086 CONVERT_FROM_HOST_TO_SMC_UL(table->CurrSclkPllRange);
2087 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
2088 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
2089 CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
2090 CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
2092 /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
2093 result = smu7_copy_bytes_to_smc(hwmgr,
2094 smu_data->smu7_data.dpm_table_start +
2095 offsetof(SMU74_Discrete_DpmTable, SystemFlags),
2096 (uint8_t *)&(table->SystemFlags),
2097 sizeof(SMU74_Discrete_DpmTable) - 3 * sizeof(SMU74_PIDController),
2099 PP_ASSERT_WITH_CODE(0 == result,
2100 "Failed to upload dpm data to SMC memory!", return result);
2102 result = polaris10_init_arb_table_index(hwmgr);
2103 PP_ASSERT_WITH_CODE(0 == result,
2104 "Failed to upload arb data to SMC memory!", return result);
2106 result = polaris10_populate_pm_fuses(hwmgr);
2107 PP_ASSERT_WITH_CODE(0 == result,
2108 "Failed to populate PM fuses to SMC memory!", return result);
2113 static int polaris10_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
2115 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2117 if (data->need_update_smu7_dpm_table &
2118 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
2119 return polaris10_program_memory_timing_parameters(hwmgr);
2124 int polaris10_thermal_avfs_enable(struct pp_hwmgr *hwmgr)
2126 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2128 if (!hwmgr->avfs_supported)
2131 smum_send_msg_to_smc_with_parameter(hwmgr,
2132 PPSMC_MSG_SetGBDroopSettings, data->avfs_vdroop_override_setting,
2135 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableAvfs, NULL);
2137 /* Apply avfs cks-off voltages to avoid the overshoot
2138 * when switching to the highest sclk frequency
2140 if (data->apply_avfs_cks_off_voltage)
2141 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ApplyAvfsCksOffVoltage, NULL);
2146 static int polaris10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
2148 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2149 SMU74_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
2151 uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2;
2152 uint16_t fdo_min, slope1, slope2;
2153 uint32_t reference_clock;
2157 if (hwmgr->thermal_controller.fanInfo.bNoFan) {
2158 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2159 PHM_PlatformCaps_MicrocodeFanControl);
2163 if (smu_data->smu7_data.fan_table_start == 0) {
2164 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2165 PHM_PlatformCaps_MicrocodeFanControl);
2169 duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2170 CG_FDO_CTRL1, FMAX_DUTY100);
2173 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2174 PHM_PlatformCaps_MicrocodeFanControl);
2178 /* use hardware fan control */
2179 if (hwmgr->thermal_controller.use_hw_fan_control)
2182 tmp64 = hwmgr->thermal_controller.advanceFanControlParameters.
2184 do_div(tmp64, 10000);
2185 fdo_min = (uint16_t)tmp64;
2187 t_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usTMed -
2188 hwmgr->thermal_controller.advanceFanControlParameters.usTMin;
2189 t_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usTHigh -
2190 hwmgr->thermal_controller.advanceFanControlParameters.usTMed;
2192 pwm_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed -
2193 hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin;
2194 pwm_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh -
2195 hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed;
2197 slope1 = (uint16_t)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
2198 slope2 = (uint16_t)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
2200 fan_table.TempMin = cpu_to_be16((50 + hwmgr->
2201 thermal_controller.advanceFanControlParameters.usTMin) / 100);
2202 fan_table.TempMed = cpu_to_be16((50 + hwmgr->
2203 thermal_controller.advanceFanControlParameters.usTMed) / 100);
2204 fan_table.TempMax = cpu_to_be16((50 + hwmgr->
2205 thermal_controller.advanceFanControlParameters.usTMax) / 100);
2207 fan_table.Slope1 = cpu_to_be16(slope1);
2208 fan_table.Slope2 = cpu_to_be16(slope2);
2210 fan_table.FdoMin = cpu_to_be16(fdo_min);
2212 fan_table.HystDown = cpu_to_be16(hwmgr->
2213 thermal_controller.advanceFanControlParameters.ucTHyst);
2215 fan_table.HystUp = cpu_to_be16(1);
2217 fan_table.HystSlope = cpu_to_be16(1);
2219 fan_table.TempRespLim = cpu_to_be16(5);
2221 reference_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
2223 fan_table.RefreshPeriod = cpu_to_be32((hwmgr->
2224 thermal_controller.advanceFanControlParameters.ulCycleDelay *
2225 reference_clock) / 1600);
2227 fan_table.FdoMax = cpu_to_be16((uint16_t)duty100);
2229 fan_table.TempSrc = (uint8_t)PHM_READ_VFPF_INDIRECT_FIELD(
2230 hwmgr->device, CGS_IND_REG__SMC,
2231 CG_MULT_THERMAL_CTRL, TEMP_SEL);
2233 res = smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.fan_table_start,
2234 (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table),
2237 if (!res && hwmgr->thermal_controller.
2238 advanceFanControlParameters.ucMinimumPWMLimit)
2239 res = smum_send_msg_to_smc_with_parameter(hwmgr,
2240 PPSMC_MSG_SetFanMinPwm,
2241 hwmgr->thermal_controller.
2242 advanceFanControlParameters.ucMinimumPWMLimit,
2245 if (!res && hwmgr->thermal_controller.
2246 advanceFanControlParameters.ulMinFanSCLKAcousticLimit)
2247 res = smum_send_msg_to_smc_with_parameter(hwmgr,
2248 PPSMC_MSG_SetFanSclkTarget,
2249 hwmgr->thermal_controller.
2250 advanceFanControlParameters.ulMinFanSCLKAcousticLimit,
2254 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2255 PHM_PlatformCaps_MicrocodeFanControl);
2260 static int polaris10_update_uvd_smc_table(struct pp_hwmgr *hwmgr)
2262 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2263 uint32_t mm_boot_level_offset, mm_boot_level_value;
2264 struct phm_ppt_v1_information *table_info =
2265 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2267 smu_data->smc_state_table.UvdBootLevel = 0;
2268 if (table_info->mm_dep_table->count > 0)
2269 smu_data->smc_state_table.UvdBootLevel =
2270 (uint8_t) (table_info->mm_dep_table->count - 1);
2271 mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + offsetof(SMU74_Discrete_DpmTable,
2273 mm_boot_level_offset /= 4;
2274 mm_boot_level_offset *= 4;
2275 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
2276 CGS_IND_REG__SMC, mm_boot_level_offset);
2277 mm_boot_level_value &= 0x00FFFFFF;
2278 mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24;
2279 cgs_write_ind_register(hwmgr->device,
2280 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
2282 if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2283 PHM_PlatformCaps_UVDDPM) ||
2284 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2285 PHM_PlatformCaps_StablePState))
2286 smum_send_msg_to_smc_with_parameter(hwmgr,
2287 PPSMC_MSG_UVDDPM_SetEnabledMask,
2288 (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel),
2293 static int polaris10_update_vce_smc_table(struct pp_hwmgr *hwmgr)
2295 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2296 uint32_t mm_boot_level_offset, mm_boot_level_value;
2297 struct phm_ppt_v1_information *table_info =
2298 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2300 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2301 PHM_PlatformCaps_StablePState))
2302 smu_data->smc_state_table.VceBootLevel =
2303 (uint8_t) (table_info->mm_dep_table->count - 1);
2305 smu_data->smc_state_table.VceBootLevel = 0;
2307 mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
2308 offsetof(SMU74_Discrete_DpmTable, VceBootLevel);
2309 mm_boot_level_offset /= 4;
2310 mm_boot_level_offset *= 4;
2311 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
2312 CGS_IND_REG__SMC, mm_boot_level_offset);
2313 mm_boot_level_value &= 0xFF00FFFF;
2314 mm_boot_level_value |= smu_data->smc_state_table.VceBootLevel << 16;
2315 cgs_write_ind_register(hwmgr->device,
2316 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
2318 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
2319 smum_send_msg_to_smc_with_parameter(hwmgr,
2320 PPSMC_MSG_VCEDPM_SetEnabledMask,
2321 (uint32_t)1 << smu_data->smc_state_table.VceBootLevel,
2326 static int polaris10_update_bif_smc_table(struct pp_hwmgr *hwmgr)
2328 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2329 struct phm_ppt_v1_information *table_info =
2330 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2331 struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
2334 max_entry = (SMU74_MAX_LEVELS_LINK < pcie_table->count) ?
2335 SMU74_MAX_LEVELS_LINK :
2337 /* Setup BIF_SCLK levels */
2338 for (i = 0; i < max_entry; i++)
2339 smu_data->bif_sclk_table[i] = pcie_table->entries[i].pcie_sclk;
2343 static int polaris10_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)
2347 polaris10_update_uvd_smc_table(hwmgr);
2350 polaris10_update_vce_smc_table(hwmgr);
2353 polaris10_update_bif_smc_table(hwmgr);
2360 static int polaris10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
2362 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2363 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2366 uint32_t low_sclk_interrupt_threshold = 0;
2368 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2369 PHM_PlatformCaps_SclkThrottleLowNotification)
2370 && (data->low_sclk_interrupt_threshold != 0)) {
2371 low_sclk_interrupt_threshold =
2372 data->low_sclk_interrupt_threshold;
2374 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
2376 result = smu7_copy_bytes_to_smc(
2378 smu_data->smu7_data.dpm_table_start +
2379 offsetof(SMU74_Discrete_DpmTable,
2380 LowSclkInterruptThreshold),
2381 (uint8_t *)&low_sclk_interrupt_threshold,
2385 PP_ASSERT_WITH_CODE((result == 0),
2386 "Failed to update SCLK threshold!", return result);
2388 result = polaris10_program_mem_timing_parameters(hwmgr);
2389 PP_ASSERT_WITH_CODE((result == 0),
2390 "Failed to program memory timing parameters!",
2396 static uint32_t polaris10_get_offsetof(uint32_t type, uint32_t member)
2399 case SMU_SoftRegisters:
2401 case HandshakeDisables:
2402 return offsetof(SMU74_SoftRegisters, HandshakeDisables);
2403 case VoltageChangeTimeout:
2404 return offsetof(SMU74_SoftRegisters, VoltageChangeTimeout);
2405 case AverageGraphicsActivity:
2406 return offsetof(SMU74_SoftRegisters, AverageGraphicsActivity);
2407 case AverageMemoryActivity:
2408 return offsetof(SMU74_SoftRegisters, AverageMemoryActivity);
2410 return offsetof(SMU74_SoftRegisters, PreVBlankGap);
2412 return offsetof(SMU74_SoftRegisters, VBlankTimeout);
2413 case UcodeLoadStatus:
2414 return offsetof(SMU74_SoftRegisters, UcodeLoadStatus);
2415 case DRAM_LOG_ADDR_H:
2416 return offsetof(SMU74_SoftRegisters, DRAM_LOG_ADDR_H);
2417 case DRAM_LOG_ADDR_L:
2418 return offsetof(SMU74_SoftRegisters, DRAM_LOG_ADDR_L);
2419 case DRAM_LOG_PHY_ADDR_H:
2420 return offsetof(SMU74_SoftRegisters, DRAM_LOG_PHY_ADDR_H);
2421 case DRAM_LOG_PHY_ADDR_L:
2422 return offsetof(SMU74_SoftRegisters, DRAM_LOG_PHY_ADDR_L);
2423 case DRAM_LOG_BUFF_SIZE:
2424 return offsetof(SMU74_SoftRegisters, DRAM_LOG_BUFF_SIZE);
2427 case SMU_Discrete_DpmTable:
2430 return offsetof(SMU74_Discrete_DpmTable, UvdBootLevel);
2432 return offsetof(SMU74_Discrete_DpmTable, VceBootLevel);
2433 case LowSclkInterruptThreshold:
2434 return offsetof(SMU74_Discrete_DpmTable, LowSclkInterruptThreshold);
2438 pr_warn("can't get the offset of type %x member %x\n", type, member);
2442 static uint32_t polaris10_get_mac_definition(uint32_t value)
2445 case SMU_MAX_LEVELS_GRAPHICS:
2446 return SMU74_MAX_LEVELS_GRAPHICS;
2447 case SMU_MAX_LEVELS_MEMORY:
2448 return SMU74_MAX_LEVELS_MEMORY;
2449 case SMU_MAX_LEVELS_LINK:
2450 return SMU74_MAX_LEVELS_LINK;
2451 case SMU_MAX_ENTRIES_SMIO:
2452 return SMU74_MAX_ENTRIES_SMIO;
2453 case SMU_MAX_LEVELS_VDDC:
2454 return SMU74_MAX_LEVELS_VDDC;
2455 case SMU_MAX_LEVELS_VDDGFX:
2456 return SMU74_MAX_LEVELS_VDDGFX;
2457 case SMU_MAX_LEVELS_VDDCI:
2458 return SMU74_MAX_LEVELS_VDDCI;
2459 case SMU_MAX_LEVELS_MVDD:
2460 return SMU74_MAX_LEVELS_MVDD;
2461 case SMU_UVD_MCLK_HANDSHAKE_DISABLE:
2462 return SMU7_UVD_MCLK_HANDSHAKE_DISABLE;
2465 pr_warn("can't get the mac of %x\n", value);
2469 static int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr)
2471 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2472 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2477 result = smu7_read_smc_sram_dword(hwmgr,
2478 SMU7_FIRMWARE_HEADER_LOCATION +
2479 offsetof(SMU74_Firmware_Header, DpmTable),
2483 smu_data->smu7_data.dpm_table_start = tmp;
2485 error |= (0 != result);
2487 result = smu7_read_smc_sram_dword(hwmgr,
2488 SMU7_FIRMWARE_HEADER_LOCATION +
2489 offsetof(SMU74_Firmware_Header, SoftRegisters),
2493 data->soft_regs_start = tmp;
2494 smu_data->smu7_data.soft_regs_start = tmp;
2497 error |= (0 != result);
2499 result = smu7_read_smc_sram_dword(hwmgr,
2500 SMU7_FIRMWARE_HEADER_LOCATION +
2501 offsetof(SMU74_Firmware_Header, mcRegisterTable),
2505 smu_data->smu7_data.mc_reg_table_start = tmp;
2507 result = smu7_read_smc_sram_dword(hwmgr,
2508 SMU7_FIRMWARE_HEADER_LOCATION +
2509 offsetof(SMU74_Firmware_Header, FanTable),
2513 smu_data->smu7_data.fan_table_start = tmp;
2515 error |= (0 != result);
2517 result = smu7_read_smc_sram_dword(hwmgr,
2518 SMU7_FIRMWARE_HEADER_LOCATION +
2519 offsetof(SMU74_Firmware_Header, mcArbDramTimingTable),
2523 smu_data->smu7_data.arb_table_start = tmp;
2525 error |= (0 != result);
2527 result = smu7_read_smc_sram_dword(hwmgr,
2528 SMU7_FIRMWARE_HEADER_LOCATION +
2529 offsetof(SMU74_Firmware_Header, Version),
2533 hwmgr->microcode_version_info.SMC = tmp;
2535 error |= (0 != result);
2537 return error ? -1 : 0;
2540 static bool polaris10_is_dpm_running(struct pp_hwmgr *hwmgr)
2542 return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
2543 CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
2547 static int polaris10_update_dpm_settings(struct pp_hwmgr *hwmgr,
2548 void *profile_setting)
2550 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2551 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)
2552 (hwmgr->smu_backend);
2553 struct profile_mode_setting *setting;
2554 struct SMU74_Discrete_GraphicsLevel *levels =
2555 smu_data->smc_state_table.GraphicsLevel;
2556 uint32_t array = smu_data->smu7_data.dpm_table_start +
2557 offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
2559 uint32_t mclk_array = smu_data->smu7_data.dpm_table_start +
2560 offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
2561 struct SMU74_Discrete_MemoryLevel *mclk_levels =
2562 smu_data->smc_state_table.MemoryLevel;
2564 uint32_t offset, up_hyst_offset, down_hyst_offset, clk_activity_offset, tmp;
2566 if (profile_setting == NULL)
2569 setting = (struct profile_mode_setting *)profile_setting;
2571 if (setting->bupdate_sclk) {
2572 if (!data->sclk_dpm_key_disabled)
2573 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SCLKDPM_FreezeLevel, NULL);
2574 for (i = 0; i < smu_data->smc_state_table.GraphicsDpmLevelCount; i++) {
2575 if (levels[i].ActivityLevel !=
2576 cpu_to_be16(setting->sclk_activity)) {
2577 levels[i].ActivityLevel = cpu_to_be16(setting->sclk_activity);
2579 clk_activity_offset = array + (sizeof(SMU74_Discrete_GraphicsLevel) * i)
2580 + offsetof(SMU74_Discrete_GraphicsLevel, ActivityLevel);
2581 offset = clk_activity_offset & ~0x3;
2582 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
2583 tmp = phm_set_field_to_u32(clk_activity_offset, tmp, levels[i].ActivityLevel, sizeof(uint16_t));
2584 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
2587 if (levels[i].UpHyst != setting->sclk_up_hyst ||
2588 levels[i].DownHyst != setting->sclk_down_hyst) {
2589 levels[i].UpHyst = setting->sclk_up_hyst;
2590 levels[i].DownHyst = setting->sclk_down_hyst;
2591 up_hyst_offset = array + (sizeof(SMU74_Discrete_GraphicsLevel) * i)
2592 + offsetof(SMU74_Discrete_GraphicsLevel, UpHyst);
2593 down_hyst_offset = array + (sizeof(SMU74_Discrete_GraphicsLevel) * i)
2594 + offsetof(SMU74_Discrete_GraphicsLevel, DownHyst);
2595 offset = up_hyst_offset & ~0x3;
2596 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
2597 tmp = phm_set_field_to_u32(up_hyst_offset, tmp, levels[i].UpHyst, sizeof(uint8_t));
2598 tmp = phm_set_field_to_u32(down_hyst_offset, tmp, levels[i].DownHyst, sizeof(uint8_t));
2599 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
2602 if (!data->sclk_dpm_key_disabled)
2603 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SCLKDPM_UnfreezeLevel, NULL);
2606 if (setting->bupdate_mclk) {
2607 if (!data->mclk_dpm_key_disabled)
2608 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_FreezeLevel, NULL);
2609 for (i = 0; i < smu_data->smc_state_table.MemoryDpmLevelCount; i++) {
2610 if (mclk_levels[i].ActivityLevel !=
2611 cpu_to_be16(setting->mclk_activity)) {
2612 mclk_levels[i].ActivityLevel = cpu_to_be16(setting->mclk_activity);
2614 clk_activity_offset = mclk_array + (sizeof(SMU74_Discrete_MemoryLevel) * i)
2615 + offsetof(SMU74_Discrete_MemoryLevel, ActivityLevel);
2616 offset = clk_activity_offset & ~0x3;
2617 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
2618 tmp = phm_set_field_to_u32(clk_activity_offset, tmp, mclk_levels[i].ActivityLevel, sizeof(uint16_t));
2619 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
2622 if (mclk_levels[i].UpHyst != setting->mclk_up_hyst ||
2623 mclk_levels[i].DownHyst != setting->mclk_down_hyst) {
2624 mclk_levels[i].UpHyst = setting->mclk_up_hyst;
2625 mclk_levels[i].DownHyst = setting->mclk_down_hyst;
2626 up_hyst_offset = mclk_array + (sizeof(SMU74_Discrete_MemoryLevel) * i)
2627 + offsetof(SMU74_Discrete_MemoryLevel, UpHyst);
2628 down_hyst_offset = mclk_array + (sizeof(SMU74_Discrete_MemoryLevel) * i)
2629 + offsetof(SMU74_Discrete_MemoryLevel, DownHyst);
2630 offset = up_hyst_offset & ~0x3;
2631 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
2632 tmp = phm_set_field_to_u32(up_hyst_offset, tmp, mclk_levels[i].UpHyst, sizeof(uint8_t));
2633 tmp = phm_set_field_to_u32(down_hyst_offset, tmp, mclk_levels[i].DownHyst, sizeof(uint8_t));
2634 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
2637 if (!data->mclk_dpm_key_disabled)
2638 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_UnfreezeLevel, NULL);
2643 const struct pp_smumgr_func polaris10_smu_funcs = {
2644 .name = "polaris10_smu",
2645 .smu_init = polaris10_smu_init,
2646 .smu_fini = smu7_smu_fini,
2647 .start_smu = polaris10_start_smu,
2648 .check_fw_load_finish = smu7_check_fw_load_finish,
2649 .request_smu_load_fw = smu7_reload_firmware,
2650 .request_smu_load_specific_fw = NULL,
2651 .send_msg_to_smc = smu7_send_msg_to_smc,
2652 .send_msg_to_smc_with_parameter = smu7_send_msg_to_smc_with_parameter,
2653 .get_argument = smu7_get_argument,
2654 .download_pptable_settings = NULL,
2655 .upload_pptable_settings = NULL,
2656 .update_smc_table = polaris10_update_smc_table,
2657 .get_offsetof = polaris10_get_offsetof,
2658 .process_firmware_header = polaris10_process_firmware_header,
2659 .init_smc_table = polaris10_init_smc_table,
2660 .update_sclk_threshold = polaris10_update_sclk_threshold,
2661 .thermal_avfs_enable = polaris10_thermal_avfs_enable,
2662 .thermal_setup_fan_table = polaris10_thermal_setup_fan_table,
2663 .populate_all_graphic_levels = polaris10_populate_all_graphic_levels,
2664 .populate_all_memory_levels = polaris10_populate_all_memory_levels,
2665 .get_mac_definition = polaris10_get_mac_definition,
2666 .is_dpm_running = polaris10_is_dpm_running,
2667 .is_hw_avfs_present = polaris10_is_hw_avfs_present,
2668 .update_dpm_settings = polaris10_update_dpm_settings,