drivers/gpu/drm/amd/pm/powerplay/sislands_smc.h

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #ifndef PP_SISLANDS_SMC_H
  24 #define PP_SISLANDS_SMC_H
  25
  26 #include "ppsmc.h"
  27
  28 #pragma pack(push, 1)
  29
  30 #define SISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE 16
  31
  32 struct PP_SIslands_Dpm2PerfLevel
  33 {
  34     uint8_t MaxPS;
  35     uint8_t TgtAct;
  36     uint8_t MaxPS_StepInc;
  37     uint8_t MaxPS_StepDec;
  38     uint8_t PSSamplingTime;
  39     uint8_t NearTDPDec;
  40     uint8_t AboveSafeInc;
  41     uint8_t BelowSafeInc;
  42     uint8_t PSDeltaLimit;
  43     uint8_t PSDeltaWin;
  44     uint16_t PwrEfficiencyRatio;
  45     uint8_t Reserved[4];
  46 };
  47
  48 typedef struct PP_SIslands_Dpm2PerfLevel PP_SIslands_Dpm2PerfLevel;
  49
  50 struct PP_SIslands_DPM2Status
  51 {
  52     uint32_t    dpm2Flags;
  53     uint8_t     CurrPSkip;
  54     uint8_t     CurrPSkipPowerShift;
  55     uint8_t     CurrPSkipTDP;
  56     uint8_t     CurrPSkipOCP;
  57     uint8_t     MaxSPLLIndex;
  58     uint8_t     MinSPLLIndex;
  59     uint8_t     CurrSPLLIndex;
  60     uint8_t     InfSweepMode;
  61     uint8_t     InfSweepDir;
  62     uint8_t     TDPexceeded;
  63     uint8_t     reserved;
  64     uint8_t     SwitchDownThreshold;
  65     uint32_t    SwitchDownCounter;
  66     uint32_t    SysScalingFactor;
  67 };
  68
  69 typedef struct PP_SIslands_DPM2Status PP_SIslands_DPM2Status;
  70
  71 struct PP_SIslands_DPM2Parameters
  72 {
  73     uint32_t    TDPLimit;
  74     uint32_t    NearTDPLimit;
  75     uint32_t    SafePowerLimit;
  76     uint32_t    PowerBoostLimit;
  77     uint32_t    MinLimitDelta;
  78 };
  79 typedef struct PP_SIslands_DPM2Parameters PP_SIslands_DPM2Parameters;
  80
  81 struct PP_SIslands_PAPMStatus
  82 {
  83     uint32_t    EstimatedDGPU_T;
  84     uint32_t    EstimatedDGPU_P;
  85     uint32_t    EstimatedAPU_T;
  86     uint32_t    EstimatedAPU_P;
  87     uint8_t     dGPU_T_Limit_Exceeded;
  88     uint8_t     reserved[3];
  89 };
  90 typedef struct PP_SIslands_PAPMStatus PP_SIslands_PAPMStatus;
  91
  92 struct PP_SIslands_PAPMParameters
  93 {
  94     uint32_t    NearTDPLimitTherm;
  95     uint32_t    NearTDPLimitPAPM;
  96     uint32_t    PlatformPowerLimit;
  97     uint32_t    dGPU_T_Limit;
  98     uint32_t    dGPU_T_Warning;
  99     uint32_t    dGPU_T_Hysteresis;
 100 };
 101 typedef struct PP_SIslands_PAPMParameters PP_SIslands_PAPMParameters;
 102
 103 struct SISLANDS_SMC_SCLK_VALUE
 104 {
 105     uint32_t    vCG_SPLL_FUNC_CNTL;
 106     uint32_t    vCG_SPLL_FUNC_CNTL_2;
 107     uint32_t    vCG_SPLL_FUNC_CNTL_3;
 108     uint32_t    vCG_SPLL_FUNC_CNTL_4;
 109     uint32_t    vCG_SPLL_SPREAD_SPECTRUM;
 110     uint32_t    vCG_SPLL_SPREAD_SPECTRUM_2;
 111     uint32_t    sclk_value;
 112 };
 113
 114 typedef struct SISLANDS_SMC_SCLK_VALUE SISLANDS_SMC_SCLK_VALUE;
 115
 116 struct SISLANDS_SMC_MCLK_VALUE
 117 {
 118     uint32_t    vMPLL_FUNC_CNTL;
 119     uint32_t    vMPLL_FUNC_CNTL_1;
 120     uint32_t    vMPLL_FUNC_CNTL_2;
 121     uint32_t    vMPLL_AD_FUNC_CNTL;
 122     uint32_t    vMPLL_DQ_FUNC_CNTL;
 123     uint32_t    vMCLK_PWRMGT_CNTL;
 124     uint32_t    vDLL_CNTL;
 125     uint32_t    vMPLL_SS;
 126     uint32_t    vMPLL_SS2;
 127     uint32_t    mclk_value;
 128 };
 129
 130 typedef struct SISLANDS_SMC_MCLK_VALUE SISLANDS_SMC_MCLK_VALUE;
 131
 132 struct SISLANDS_SMC_VOLTAGE_VALUE
 133 {
 134     uint16_t    value;
 135     uint8_t     index;
 136     uint8_t     phase_settings;
 137 };
 138
 139 typedef struct SISLANDS_SMC_VOLTAGE_VALUE SISLANDS_SMC_VOLTAGE_VALUE;
 140
 141 struct SISLANDS_SMC_HW_PERFORMANCE_LEVEL
 142 {
 143     uint8_t                     ACIndex;
 144     uint8_t                     displayWatermark;
 145     uint8_t                     gen2PCIE;
 146     uint8_t                     UVDWatermark;
 147     uint8_t                     VCEWatermark;
 148     uint8_t                     strobeMode;
 149     uint8_t                     mcFlags;
 150     uint8_t                     padding;
 151     uint32_t                    aT;
 152     uint32_t                    bSP;
 153     SISLANDS_SMC_SCLK_VALUE     sclk;
 154     SISLANDS_SMC_MCLK_VALUE     mclk;
 155     SISLANDS_SMC_VOLTAGE_VALUE  vddc;
 156     SISLANDS_SMC_VOLTAGE_VALUE  mvdd;
 157     SISLANDS_SMC_VOLTAGE_VALUE  vddci;
 158     SISLANDS_SMC_VOLTAGE_VALUE  std_vddc;
 159     uint8_t                     hysteresisUp;
 160     uint8_t                     hysteresisDown;
 161     uint8_t                     stateFlags;
 162     uint8_t                     arbRefreshState;
 163     uint32_t                    SQPowerThrottle;
 164     uint32_t                    SQPowerThrottle_2;
 165     uint32_t                    MaxPoweredUpCU;
 166     SISLANDS_SMC_VOLTAGE_VALUE  high_temp_vddc;
 167     SISLANDS_SMC_VOLTAGE_VALUE  low_temp_vddc;
 168     uint32_t                    reserved[2];
 169     PP_SIslands_Dpm2PerfLevel   dpm2;
 170 };
 171
 172 #define SISLANDS_SMC_STROBE_RATIO    0x0F
 173 #define SISLANDS_SMC_STROBE_ENABLE   0x10
 174
 175 #define SISLANDS_SMC_MC_EDC_RD_FLAG  0x01
 176 #define SISLANDS_SMC_MC_EDC_WR_FLAG  0x02
 177 #define SISLANDS_SMC_MC_RTT_ENABLE   0x04
 178 #define SISLANDS_SMC_MC_STUTTER_EN   0x08
 179 #define SISLANDS_SMC_MC_PG_EN        0x10
 180
 181 typedef struct SISLANDS_SMC_HW_PERFORMANCE_LEVEL SISLANDS_SMC_HW_PERFORMANCE_LEVEL;
 182
 183 struct SISLANDS_SMC_SWSTATE
 184 {
 185         uint8_t                             flags;
 186         uint8_t                             levelCount;
 187         uint8_t                             padding2;
 188         uint8_t                             padding3;
 189         SISLANDS_SMC_HW_PERFORMANCE_LEVEL   levels[];
 190 };
 191
 192 typedef struct SISLANDS_SMC_SWSTATE SISLANDS_SMC_SWSTATE;
 193
 194 #define SISLANDS_SMC_VOLTAGEMASK_VDDC  0
 195 #define SISLANDS_SMC_VOLTAGEMASK_MVDD  1
 196 #define SISLANDS_SMC_VOLTAGEMASK_VDDCI 2
 197 #define SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING 3
 198 #define SISLANDS_SMC_VOLTAGEMASK_MAX   4
 199
 200 struct SISLANDS_SMC_VOLTAGEMASKTABLE
 201 {
 202     uint32_t lowMask[SISLANDS_SMC_VOLTAGEMASK_MAX];
 203 };
 204
 205 typedef struct SISLANDS_SMC_VOLTAGEMASKTABLE SISLANDS_SMC_VOLTAGEMASKTABLE;
 206
 207 #define SISLANDS_MAX_NO_VREG_STEPS 32
 208
 209 struct SISLANDS_SMC_STATETABLE
 210 {
 211     uint8_t                             thermalProtectType;
 212     uint8_t                             systemFlags;
 213     uint8_t                             maxVDDCIndexInPPTable;
 214     uint8_t                             extraFlags;
 215     uint32_t                            lowSMIO[SISLANDS_MAX_NO_VREG_STEPS];
 216     SISLANDS_SMC_VOLTAGEMASKTABLE       voltageMaskTable;
 217     SISLANDS_SMC_VOLTAGEMASKTABLE       phaseMaskTable;
 218     PP_SIslands_DPM2Parameters          dpm2Params;
 219     SISLANDS_SMC_SWSTATE                initialState;
 220     SISLANDS_SMC_SWSTATE                ACPIState;
 221     SISLANDS_SMC_SWSTATE                ULVState;
 222     SISLANDS_SMC_SWSTATE                driverState;
 223     SISLANDS_SMC_HW_PERFORMANCE_LEVEL   dpmLevels[SISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1];
 224 };
 225
 226 typedef struct SISLANDS_SMC_STATETABLE SISLANDS_SMC_STATETABLE;
 227
 228 #define SI_SMC_SOFT_REGISTER_mclk_chg_timeout         0x0
 229 #define SI_SMC_SOFT_REGISTER_delay_vreg               0xC
 230 #define SI_SMC_SOFT_REGISTER_delay_acpi               0x28
 231 #define SI_SMC_SOFT_REGISTER_seq_index                0x5C
 232 #define SI_SMC_SOFT_REGISTER_mvdd_chg_time            0x60
 233 #define SI_SMC_SOFT_REGISTER_mclk_switch_lim          0x70
 234 #define SI_SMC_SOFT_REGISTER_watermark_threshold      0x78
 235 #define SI_SMC_SOFT_REGISTER_phase_shedding_delay     0x88
 236 #define SI_SMC_SOFT_REGISTER_ulv_volt_change_delay    0x8C
 237 #define SI_SMC_SOFT_REGISTER_mc_block_delay           0x98
 238 #define SI_SMC_SOFT_REGISTER_ticks_per_us             0xA8
 239 #define SI_SMC_SOFT_REGISTER_crtc_index               0xC4
 240 #define SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min 0xC8
 241 #define SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max 0xCC
 242 #define SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width  0xF4
 243 #define SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen   0xFC
 244 #define SI_SMC_SOFT_REGISTER_vr_hot_gpio              0x100
 245 #define SI_SMC_SOFT_REGISTER_svi_rework_plat_type     0x118
 246 #define SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd   0x11c
 247 #define SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc   0x120
 248
 249 struct PP_SIslands_FanTable
 250 {
 251         uint8_t  fdo_mode;
 252         uint8_t  padding;
 253         int16_t  temp_min;
 254         int16_t  temp_med;
 255         int16_t  temp_max;
 256         int16_t  slope1;
 257         int16_t  slope2;
 258         int16_t  fdo_min;
 259         int16_t  hys_up;
 260         int16_t  hys_down;
 261         int16_t  hys_slope;
 262         int16_t  temp_resp_lim;
 263         int16_t  temp_curr;
 264         int16_t  slope_curr;
 265         int16_t  pwm_curr;
 266         uint32_t refresh_period;
 267         int16_t  fdo_max;
 268         uint8_t  temp_src;
 269         int8_t  padding2;
 270 };
 271
 272 typedef struct PP_SIslands_FanTable PP_SIslands_FanTable;
 273
 274 #define SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES 16
 275 #define SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES 32
 276
 277 #define SMC_SISLANDS_SCALE_I  7
 278 #define SMC_SISLANDS_SCALE_R 12
 279
 280 struct PP_SIslands_CacConfig
 281 {
 282     uint16_t   cac_lkge_lut[SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES];
 283     uint32_t   lkge_lut_V0;
 284     uint32_t   lkge_lut_Vstep;
 285     uint32_t   WinTime;
 286     uint32_t   R_LL;
 287     uint32_t   calculation_repeats;
 288     uint32_t   l2numWin_TDP;
 289     uint32_t   dc_cac;
 290     uint8_t    lts_truncate_n;
 291     uint8_t    SHIFT_N;
 292     uint8_t    log2_PG_LKG_SCALE;
 293     uint8_t    cac_temp;
 294     uint32_t   lkge_lut_T0;
 295     uint32_t   lkge_lut_Tstep;
 296 };
 297
 298 typedef struct PP_SIslands_CacConfig PP_SIslands_CacConfig;
 299
 300 #define SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE 16
 301 #define SMC_SISLANDS_MC_REGISTER_ARRAY_SET_COUNT 20
 302
 303 struct SMC_SIslands_MCRegisterAddress
 304 {
 305     uint16_t s0;
 306     uint16_t s1;
 307 };
 308
 309 typedef struct SMC_SIslands_MCRegisterAddress SMC_SIslands_MCRegisterAddress;
 310
 311 struct SMC_SIslands_MCRegisterSet
 312 {
 313     uint32_t value[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE];
 314 };
 315
 316 typedef struct SMC_SIslands_MCRegisterSet SMC_SIslands_MCRegisterSet;
 317
 318 struct SMC_SIslands_MCRegisters
 319 {
 320     uint8_t                             last;
 321     uint8_t                             reserved[3];
 322     SMC_SIslands_MCRegisterAddress      address[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE];
 323     SMC_SIslands_MCRegisterSet          data[SMC_SISLANDS_MC_REGISTER_ARRAY_SET_COUNT];
 324 };
 325
 326 typedef struct SMC_SIslands_MCRegisters SMC_SIslands_MCRegisters;
 327
 328 struct SMC_SIslands_MCArbDramTimingRegisterSet
 329 {
 330     uint32_t mc_arb_dram_timing;
 331     uint32_t mc_arb_dram_timing2;
 332     uint8_t  mc_arb_rfsh_rate;
 333     uint8_t  mc_arb_burst_time;
 334     uint8_t  padding[2];
 335 };
 336
 337 typedef struct SMC_SIslands_MCArbDramTimingRegisterSet SMC_SIslands_MCArbDramTimingRegisterSet;
 338
 339 struct SMC_SIslands_MCArbDramTimingRegisters
 340 {
 341     uint8_t                                     arb_current;
 342     uint8_t                                     reserved[3];
 343     SMC_SIslands_MCArbDramTimingRegisterSet     data[16];
 344 };
 345
 346 typedef struct SMC_SIslands_MCArbDramTimingRegisters SMC_SIslands_MCArbDramTimingRegisters;
 347
 348 struct SMC_SISLANDS_SPLL_DIV_TABLE
 349 {
 350     uint32_t    freq[256];
 351     uint32_t    ss[256];
 352 };
 353
 354 #define SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK  0x01ffffff
 355 #define SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT 0
 356 #define SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK   0xfe000000
 357 #define SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT  25
 358 #define SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK   0x000fffff
 359 #define SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT  0
 360 #define SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK   0xfff00000
 361 #define SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT  20
 362
 363 typedef struct SMC_SISLANDS_SPLL_DIV_TABLE SMC_SISLANDS_SPLL_DIV_TABLE;
 364
 365 #define SMC_SISLANDS_DTE_MAX_FILTER_STAGES 5
 366
 367 #define SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE 16
 368
 369 struct Smc_SIslands_DTE_Configuration
 370 {
 371     uint32_t tau[SMC_SISLANDS_DTE_MAX_FILTER_STAGES];
 372     uint32_t R[SMC_SISLANDS_DTE_MAX_FILTER_STAGES];
 373     uint32_t K;
 374     uint32_t T0;
 375     uint32_t MaxT;
 376     uint8_t  WindowSize;
 377     uint8_t  Tdep_count;
 378     uint8_t  temp_select;
 379     uint8_t  DTE_mode;
 380     uint8_t  T_limits[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];
 381     uint32_t Tdep_tau[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];
 382     uint32_t Tdep_R[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];
 383     uint32_t Tthreshold;
 384 };
 385
 386 typedef struct Smc_SIslands_DTE_Configuration Smc_SIslands_DTE_Configuration;
 387
 388 #define SMC_SISLANDS_DTE_STATUS_FLAG_DTE_ON 1
 389
 390 #define SISLANDS_SMC_FIRMWARE_HEADER_LOCATION 0x10000
 391
 392 #define SISLANDS_SMC_FIRMWARE_HEADER_version                   0x0
 393 #define SISLANDS_SMC_FIRMWARE_HEADER_flags                     0x4
 394 #define SISLANDS_SMC_FIRMWARE_HEADER_softRegisters             0xC
 395 #define SISLANDS_SMC_FIRMWARE_HEADER_stateTable                0x10
 396 #define SISLANDS_SMC_FIRMWARE_HEADER_fanTable                  0x14
 397 #define SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable            0x18
 398 #define SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable           0x24
 399 #define SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable 0x30
 400 #define SISLANDS_SMC_FIRMWARE_HEADER_spllTable                 0x38
 401 #define SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration          0x40
 402 #define SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters            0x48
 403
 404 #pragma pack(pop)
 405
 406 int amdgpu_si_copy_bytes_to_smc(struct amdgpu_device *adev,
 407                                 u32 smc_start_address,
 408                                 const u8 *src, u32 byte_count, u32 limit);
 409 void amdgpu_si_start_smc(struct amdgpu_device *adev);
 410 void amdgpu_si_reset_smc(struct amdgpu_device *adev);
 411 int amdgpu_si_program_jump_on_start(struct amdgpu_device *adev);
 412 void amdgpu_si_smc_clock(struct amdgpu_device *adev, bool enable);
 413 bool amdgpu_si_is_smc_running(struct amdgpu_device *adev);
 414 PPSMC_Result amdgpu_si_send_msg_to_smc(struct amdgpu_device *adev, PPSMC_Msg msg);
 415 PPSMC_Result amdgpu_si_wait_for_smc_inactive(struct amdgpu_device *adev);
 416 int amdgpu_si_load_smc_ucode(struct amdgpu_device *adev, u32 limit);
 417 int amdgpu_si_read_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address,
 418                                   u32 *value, u32 limit);
 419 int amdgpu_si_write_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address,
 420                                    u32 value, u32 limit);
 421
 422 #endif
 423