2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include "vega10_thermal.h"
25 #include "vega10_hwmgr.h"
26 #include "vega10_smumgr.h"
27 #include "vega10_ppsmc.h"
28 #include "vega10_inc.h"
29 #include "soc15_common.h"
32 static int vega10_get_current_rpm(struct pp_hwmgr *hwmgr, uint32_t *current_rpm)
34 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentRpm, current_rpm);
38 int vega10_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr,
39 struct phm_fan_speed_info *fan_speed_info)
42 if (hwmgr->thermal_controller.fanInfo.bNoFan)
45 fan_speed_info->supports_percent_read = true;
46 fan_speed_info->supports_percent_write = true;
47 fan_speed_info->min_percent = 0;
48 fan_speed_info->max_percent = 100;
50 if (PP_CAP(PHM_PlatformCaps_FanSpeedInTableIsRPM) &&
51 hwmgr->thermal_controller.fanInfo.
52 ucTachometerPulsesPerRevolution) {
53 fan_speed_info->supports_rpm_read = true;
54 fan_speed_info->supports_rpm_write = true;
55 fan_speed_info->min_rpm =
56 hwmgr->thermal_controller.fanInfo.ulMinRPM;
57 fan_speed_info->max_rpm =
58 hwmgr->thermal_controller.fanInfo.ulMaxRPM;
60 fan_speed_info->min_rpm = 0;
61 fan_speed_info->max_rpm = 0;
67 int vega10_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr,
73 if (hwmgr->thermal_controller.fanInfo.bNoFan)
76 if (vega10_get_current_rpm(hwmgr, ¤t_rpm))
79 if (hwmgr->thermal_controller.
80 advanceFanControlParameters.usMaxFanRPM != 0)
81 percent = current_rpm * 100 /
82 hwmgr->thermal_controller.
83 advanceFanControlParameters.usMaxFanRPM;
85 *speed = percent > 100 ? 100 : percent;
90 int vega10_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed)
92 struct amdgpu_device *adev = hwmgr->adev;
93 struct vega10_hwmgr *data = hwmgr->backend;
95 uint32_t crystal_clock_freq;
98 if (hwmgr->thermal_controller.fanInfo.bNoFan)
101 if (data->smu_features[GNLD_FAN_CONTROL].supported) {
102 result = vega10_get_current_rpm(hwmgr, speed);
105 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_STATUS),
109 if (tach_period == 0)
112 crystal_clock_freq = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
114 *speed = 60 * crystal_clock_freq * 10000 / tach_period;
121 * Set Fan Speed Control to static mode,
122 * so that the user can decide what speed to use.
123 * @param hwmgr the address of the powerplay hardware manager.
124 * mode the fan control mode, 0 default, 1 by percent, 5, by RPM
125 * @exception Should always succeed.
127 int vega10_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
129 struct amdgpu_device *adev = hwmgr->adev;
131 if (hwmgr->fan_ctrl_is_in_default_mode) {
132 hwmgr->fan_ctrl_default_mode =
133 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
134 CG_FDO_CTRL2, FDO_PWM_MODE);
136 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
138 hwmgr->fan_ctrl_is_in_default_mode = false;
141 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
142 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
143 CG_FDO_CTRL2, TMIN, 0));
144 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
145 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
146 CG_FDO_CTRL2, FDO_PWM_MODE, mode));
152 * Reset Fan Speed Control to default mode.
153 * @param hwmgr the address of the powerplay hardware manager.
154 * @exception Should always succeed.
156 int vega10_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr)
158 struct amdgpu_device *adev = hwmgr->adev;
160 if (!hwmgr->fan_ctrl_is_in_default_mode) {
161 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
162 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
163 CG_FDO_CTRL2, FDO_PWM_MODE,
164 hwmgr->fan_ctrl_default_mode));
165 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
166 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
168 hwmgr->tmin << CG_FDO_CTRL2__TMIN__SHIFT));
169 hwmgr->fan_ctrl_is_in_default_mode = true;
176 * @fn vega10_enable_fan_control_feature
177 * @brief Enables the SMC Fan Control Feature.
179 * @param hwmgr - the address of the powerplay hardware manager.
180 * @return 0 on success. -1 otherwise.
182 static int vega10_enable_fan_control_feature(struct pp_hwmgr *hwmgr)
184 struct vega10_hwmgr *data = hwmgr->backend;
186 if (data->smu_features[GNLD_FAN_CONTROL].supported) {
187 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(
189 data->smu_features[GNLD_FAN_CONTROL].
191 "Attempt to Enable FAN CONTROL feature Failed!",
193 data->smu_features[GNLD_FAN_CONTROL].enabled = true;
199 static int vega10_disable_fan_control_feature(struct pp_hwmgr *hwmgr)
201 struct vega10_hwmgr *data = hwmgr->backend;
203 if (data->smu_features[GNLD_FAN_CONTROL].supported) {
204 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(
206 data->smu_features[GNLD_FAN_CONTROL].
208 "Attempt to Enable FAN CONTROL feature Failed!",
210 data->smu_features[GNLD_FAN_CONTROL].enabled = false;
216 int vega10_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr)
218 if (hwmgr->thermal_controller.fanInfo.bNoFan)
221 PP_ASSERT_WITH_CODE(!vega10_enable_fan_control_feature(hwmgr),
222 "Attempt to Enable SMC FAN CONTROL Feature Failed!",
229 int vega10_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr)
231 struct vega10_hwmgr *data = hwmgr->backend;
233 if (hwmgr->thermal_controller.fanInfo.bNoFan)
236 if (data->smu_features[GNLD_FAN_CONTROL].supported) {
237 PP_ASSERT_WITH_CODE(!vega10_disable_fan_control_feature(hwmgr),
238 "Attempt to Disable SMC FAN CONTROL Feature Failed!",
245 * Set Fan Speed in percent.
246 * @param hwmgr the address of the powerplay hardware manager.
247 * @param speed is the percentage value (0% - 100%) to be set.
248 * @exception Fails is the 100% setting appears to be 0.
250 int vega10_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr,
253 struct amdgpu_device *adev = hwmgr->adev;
258 if (hwmgr->thermal_controller.fanInfo.bNoFan)
264 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
265 vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
267 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
268 CG_FDO_CTRL1, FMAX_DUTY100);
273 tmp64 = (uint64_t)speed * duty100;
275 duty = (uint32_t)tmp64;
277 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
278 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),
279 CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
281 return vega10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
285 * Reset Fan Speed to default.
286 * @param hwmgr the address of the powerplay hardware manager.
287 * @exception Always succeeds.
289 int vega10_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr)
291 if (hwmgr->thermal_controller.fanInfo.bNoFan)
294 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
295 return vega10_fan_ctrl_start_smc_fan_control(hwmgr);
297 return vega10_fan_ctrl_set_default_mode(hwmgr);
301 * Set Fan Speed in RPM.
302 * @param hwmgr the address of the powerplay hardware manager.
303 * @param speed is the percentage value (min - max) to be set.
304 * @exception Fails is the speed not lie between min and max.
306 int vega10_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed)
308 struct amdgpu_device *adev = hwmgr->adev;
309 uint32_t tach_period;
310 uint32_t crystal_clock_freq;
313 if (hwmgr->thermal_controller.fanInfo.bNoFan ||
315 (speed < hwmgr->thermal_controller.fanInfo.ulMinRPM) ||
316 (speed > hwmgr->thermal_controller.fanInfo.ulMaxRPM))
319 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
320 result = vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
323 crystal_clock_freq = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
324 tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
325 WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
326 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
327 CG_TACH_CTRL, TARGET_PERIOD,
330 return vega10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC_RPM);
334 * Reads the remote temperature from the SIslands thermal controller.
336 * @param hwmgr The address of the hardware manager.
338 int vega10_thermal_get_temperature(struct pp_hwmgr *hwmgr)
340 struct amdgpu_device *adev = hwmgr->adev;
343 temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS);
345 temp = (temp & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >>
346 CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT;
350 temp *= PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
356 * Set the requested temperature range for high and low alert signals
358 * @param hwmgr The address of the hardware manager.
359 * @param range Temperature range to be programmed for
360 * high and low alert signals
361 * @exception PP_Result_BadInput if the input data is not valid.
363 static int vega10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
364 struct PP_TemperatureRange *range)
366 struct phm_ppt_v2_information *pp_table_info =
367 (struct phm_ppt_v2_information *)(hwmgr->pptable);
368 struct phm_tdp_table *tdp_table = pp_table_info->tdp_table;
369 struct amdgpu_device *adev = hwmgr->adev;
370 int low = VEGA10_THERMAL_MINIMUM_ALERT_TEMP;
371 int high = VEGA10_THERMAL_MAXIMUM_ALERT_TEMP;
374 /* compare them in unit celsius degree */
375 if (low < range->min / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)
376 low = range->min / PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
377 if (high > tdp_table->usSoftwareShutdownTemp)
378 high = tdp_table->usSoftwareShutdownTemp;
383 val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
385 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
386 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
387 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, high);
388 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, low);
389 val &= (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK) &
390 (~THM_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK) &
391 (~THM_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK);
393 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
399 * Programs thermal controller one-time setting registers
401 * @param hwmgr The address of the hardware manager.
403 static int vega10_thermal_initialize(struct pp_hwmgr *hwmgr)
405 struct amdgpu_device *adev = hwmgr->adev;
407 if (hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution) {
408 WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
409 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
410 CG_TACH_CTRL, EDGE_PER_REV,
411 hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution - 1));
414 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
415 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
416 CG_FDO_CTRL2, TACH_PWM_RESP_RATE, 0x28));
422 * Enable thermal alerts on the RV770 thermal controller.
424 * @param hwmgr The address of the hardware manager.
426 static int vega10_thermal_enable_alert(struct pp_hwmgr *hwmgr)
428 struct amdgpu_device *adev = hwmgr->adev;
429 struct vega10_hwmgr *data = hwmgr->backend;
432 if (data->smu_features[GNLD_FW_CTF].supported) {
433 if (data->smu_features[GNLD_FW_CTF].enabled)
434 printk("[Thermal_EnableAlert] FW CTF Already Enabled!\n");
436 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
438 data->smu_features[GNLD_FW_CTF].smu_feature_bitmap),
439 "Attempt to Enable FW CTF feature Failed!",
441 data->smu_features[GNLD_FW_CTF].enabled = true;
444 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
445 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
446 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
448 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val);
454 * Disable thermal alerts on the RV770 thermal controller.
455 * @param hwmgr The address of the hardware manager.
457 int vega10_thermal_disable_alert(struct pp_hwmgr *hwmgr)
459 struct amdgpu_device *adev = hwmgr->adev;
460 struct vega10_hwmgr *data = hwmgr->backend;
462 if (data->smu_features[GNLD_FW_CTF].supported) {
463 if (!data->smu_features[GNLD_FW_CTF].enabled)
464 printk("[Thermal_EnableAlert] FW CTF Already disabled!\n");
467 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
469 data->smu_features[GNLD_FW_CTF].smu_feature_bitmap),
470 "Attempt to disable FW CTF feature Failed!",
472 data->smu_features[GNLD_FW_CTF].enabled = false;
475 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0);
481 * Uninitialize the thermal controller.
482 * Currently just disables alerts.
483 * @param hwmgr The address of the hardware manager.
485 int vega10_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr)
487 int result = vega10_thermal_disable_alert(hwmgr);
489 if (!hwmgr->thermal_controller.fanInfo.bNoFan)
490 vega10_fan_ctrl_set_default_mode(hwmgr);
496 * Set up the fan table to control the fan using the SMC.
497 * @param hwmgr the address of the powerplay hardware manager.
498 * @param pInput the pointer to input data
499 * @param pOutput the pointer to output data
500 * @param pStorage the pointer to temporary storage
501 * @param Result the last failure code
502 * @return result from set temperature range routine
504 static int vega10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
507 struct vega10_hwmgr *data = hwmgr->backend;
508 PPTable_t *table = &(data->smc_state_table.pp_table);
510 if (!data->smu_features[GNLD_FAN_CONTROL].supported)
513 table->FanMaximumRpm = (uint16_t)hwmgr->thermal_controller.
514 advanceFanControlParameters.usMaxFanRPM;
515 table->FanThrottlingRpm = hwmgr->thermal_controller.
516 advanceFanControlParameters.usFanRPMMaxLimit;
517 table->FanAcousticLimitRpm = (uint16_t)(hwmgr->thermal_controller.
518 advanceFanControlParameters.ulMinFanSCLKAcousticLimit);
519 table->FanTargetTemperature = hwmgr->thermal_controller.
520 advanceFanControlParameters.usTMax;
522 smum_send_msg_to_smc_with_parameter(hwmgr,
523 PPSMC_MSG_SetFanTemperatureTarget,
524 (uint32_t)table->FanTargetTemperature,
527 table->FanPwmMin = hwmgr->thermal_controller.
528 advanceFanControlParameters.usPWMMin * 255 / 100;
529 table->FanTargetGfxclk = (uint16_t)(hwmgr->thermal_controller.
530 advanceFanControlParameters.ulTargetGfxClk);
531 table->FanGainEdge = hwmgr->thermal_controller.
532 advanceFanControlParameters.usFanGainEdge;
533 table->FanGainHotspot = hwmgr->thermal_controller.
534 advanceFanControlParameters.usFanGainHotspot;
535 table->FanGainLiquid = hwmgr->thermal_controller.
536 advanceFanControlParameters.usFanGainLiquid;
537 table->FanGainVrVddc = hwmgr->thermal_controller.
538 advanceFanControlParameters.usFanGainVrVddc;
539 table->FanGainVrMvdd = hwmgr->thermal_controller.
540 advanceFanControlParameters.usFanGainVrMvdd;
541 table->FanGainPlx = hwmgr->thermal_controller.
542 advanceFanControlParameters.usFanGainPlx;
543 table->FanGainHbm = hwmgr->thermal_controller.
544 advanceFanControlParameters.usFanGainHbm;
545 table->FanZeroRpmEnable = hwmgr->thermal_controller.
546 advanceFanControlParameters.ucEnableZeroRPM;
547 table->FanStopTemp = hwmgr->thermal_controller.
548 advanceFanControlParameters.usZeroRPMStopTemperature;
549 table->FanStartTemp = hwmgr->thermal_controller.
550 advanceFanControlParameters.usZeroRPMStartTemperature;
552 ret = smum_smc_table_manager(hwmgr,
553 (uint8_t *)(&(data->smc_state_table.pp_table)),
556 pr_info("Failed to update Fan Control Table in PPTable!");
561 int vega10_enable_mgpu_fan_boost(struct pp_hwmgr *hwmgr)
563 struct vega10_hwmgr *data = hwmgr->backend;
564 PPTable_t *table = &(data->smc_state_table.pp_table);
567 if (!data->smu_features[GNLD_FAN_CONTROL].supported)
570 if (!hwmgr->thermal_controller.advanceFanControlParameters.
571 usMGpuThrottlingRPMLimit)
574 table->FanThrottlingRpm = hwmgr->thermal_controller.
575 advanceFanControlParameters.usMGpuThrottlingRPMLimit;
577 ret = smum_smc_table_manager(hwmgr,
578 (uint8_t *)(&(data->smc_state_table.pp_table)),
581 pr_info("Failed to update fan control table in pptable!");
585 ret = vega10_disable_fan_control_feature(hwmgr);
587 pr_info("Attempt to disable SMC fan control feature failed!");
591 ret = vega10_enable_fan_control_feature(hwmgr);
593 pr_info("Attempt to enable SMC fan control feature failed!");
599 * Start the fan control on the SMC.
600 * @param hwmgr the address of the powerplay hardware manager.
601 * @param pInput the pointer to input data
602 * @param pOutput the pointer to output data
603 * @param pStorage the pointer to temporary storage
604 * @param Result the last failure code
605 * @return result from set temperature range routine
607 static int vega10_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr)
609 /* If the fantable setup has failed we could have disabled
610 * PHM_PlatformCaps_MicrocodeFanControl even after
611 * this function was included in the table.
612 * Make sure that we still think controlling the fan is OK.
614 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
615 vega10_fan_ctrl_start_smc_fan_control(hwmgr);
621 int vega10_start_thermal_controller(struct pp_hwmgr *hwmgr,
622 struct PP_TemperatureRange *range)
629 vega10_thermal_initialize(hwmgr);
630 ret = vega10_thermal_set_temperature_range(hwmgr, range);
634 vega10_thermal_enable_alert(hwmgr);
635 /* We should restrict performance levels to low before we halt the SMC.
636 * On the other hand we are still in boot state when we do this
637 * so it would be pointless.
638 * If this assumption changes we have to revisit this table.
640 ret = vega10_thermal_setup_fan_table(hwmgr);
644 vega10_thermal_start_smc_fan_control(hwmgr);
652 int vega10_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr)
654 if (!hwmgr->thermal_controller.fanInfo.bNoFan) {
655 vega10_fan_ctrl_set_default_mode(hwmgr);
656 vega10_fan_ctrl_stop_smc_fan_control(hwmgr);