drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/fb.h>
  26 #include <linux/module.h>
  27 #include <linux/pci.h>
  28 #include <linux/slab.h>
  29
  30 #include "hwmgr.h"
  31 #include "amd_powerplay.h"
  32 #include "hardwaremanager.h"
  33 #include "ppatomfwctrl.h"
  34 #include "atomfirmware.h"
  35 #include "cgs_common.h"
  36 #include "vega10_powertune.h"
  37 #include "smu9.h"
  38 #include "smu9_driver_if.h"
  39 #include "vega10_inc.h"
  40 #include "soc15_common.h"
  41 #include "pppcielanes.h"
  42 #include "vega10_hwmgr.h"
  43 #include "vega10_smumgr.h"
  44 #include "vega10_processpptables.h"
  45 #include "vega10_pptable.h"
  46 #include "vega10_thermal.h"
  47 #include "pp_debug.h"
  48 #include "amd_pcie_helpers.h"
  49 #include "ppinterrupt.h"
  50 #include "pp_overdriver.h"
  51 #include "pp_thermal.h"
  52 #include "vega10_baco.h"
  53
  54 #include "smuio/smuio_9_0_offset.h"
  55 #include "smuio/smuio_9_0_sh_mask.h"
  56
  57 #define HBM_MEMORY_CHANNEL_WIDTH    128
  58
  59 static const uint32_t channel_number[] = {1, 2, 0, 4, 0, 8, 0, 16, 2};
  60
  61 #define mmDF_CS_AON0_DramBaseAddress0                                                                  0x0044
  62 #define mmDF_CS_AON0_DramBaseAddress0_BASE_IDX                                                         0
  63
  64 //DF_CS_AON0_DramBaseAddress0
  65 #define DF_CS_AON0_DramBaseAddress0__AddrRngVal__SHIFT                                                        0x0
  66 #define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn__SHIFT                                                    0x1
  67 #define DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT                                                      0x4
  68 #define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel__SHIFT                                                      0x8
  69 #define DF_CS_AON0_DramBaseAddress0__DramBaseAddr__SHIFT                                                      0xc
  70 #define DF_CS_AON0_DramBaseAddress0__AddrRngVal_MASK                                                          0x00000001L
  71 #define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn_MASK                                                      0x00000002L
  72 #define DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK                                                        0x000000F0L
  73 #define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel_MASK                                                        0x00000700L
  74 #define DF_CS_AON0_DramBaseAddress0__DramBaseAddr_MASK                                                        0xFFFFF000L
  75
  76 typedef enum {
  77         CLK_SMNCLK = 0,
  78         CLK_SOCCLK,
  79         CLK_MP0CLK,
  80         CLK_MP1CLK,
  81         CLK_LCLK,
  82         CLK_DCEFCLK,
  83         CLK_VCLK,
  84         CLK_DCLK,
  85         CLK_ECLK,
  86         CLK_UCLK,
  87         CLK_GFXCLK,
  88         CLK_COUNT,
  89 } CLOCK_ID_e;
  90
  91 static const ULONG PhwVega10_Magic = (ULONG)(PHM_VIslands_Magic);
  92
  93 static struct vega10_power_state *cast_phw_vega10_power_state(
  94                                   struct pp_hw_power_state *hw_ps)
  95 {
  96         PP_ASSERT_WITH_CODE((PhwVega10_Magic == hw_ps->magic),
  97                                 "Invalid Powerstate Type!",
  98                                  return NULL;);
  99
 100         return (struct vega10_power_state *)hw_ps;
 101 }
 102
 103 static const struct vega10_power_state *cast_const_phw_vega10_power_state(
 104                                  const struct pp_hw_power_state *hw_ps)
 105 {
 106         PP_ASSERT_WITH_CODE((PhwVega10_Magic == hw_ps->magic),
 107                                 "Invalid Powerstate Type!",
 108                                  return NULL;);
 109
 110         return (const struct vega10_power_state *)hw_ps;
 111 }
 112
 113 static void vega10_set_default_registry_data(struct pp_hwmgr *hwmgr)
 114 {
 115         struct vega10_hwmgr *data = hwmgr->backend;
 116
 117         data->registry_data.sclk_dpm_key_disabled =
 118                         hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true;
 119         data->registry_data.socclk_dpm_key_disabled =
 120                         hwmgr->feature_mask & PP_SOCCLK_DPM_MASK ? false : true;
 121         data->registry_data.mclk_dpm_key_disabled =
 122                         hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true;
 123         data->registry_data.pcie_dpm_key_disabled =
 124                         hwmgr->feature_mask & PP_PCIE_DPM_MASK ? false : true;
 125
 126         data->registry_data.dcefclk_dpm_key_disabled =
 127                         hwmgr->feature_mask & PP_DCEFCLK_DPM_MASK ? false : true;
 128
 129         if (hwmgr->feature_mask & PP_POWER_CONTAINMENT_MASK) {
 130                 data->registry_data.power_containment_support = 1;
 131                 data->registry_data.enable_pkg_pwr_tracking_feature = 1;
 132                 data->registry_data.enable_tdc_limit_feature = 1;
 133         }
 134
 135         data->registry_data.clock_stretcher_support =
 136                         hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK ? true : false;
 137
 138         data->registry_data.ulv_support =
 139                         hwmgr->feature_mask & PP_ULV_MASK ? true : false;
 140
 141         data->registry_data.sclk_deep_sleep_support =
 142                         hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK ? true : false;
 143
 144         data->registry_data.disable_water_mark = 0;
 145
 146         data->registry_data.fan_control_support = 1;
 147         data->registry_data.thermal_support = 1;
 148         data->registry_data.fw_ctf_enabled = 1;
 149
 150         data->registry_data.avfs_support =
 151                 hwmgr->feature_mask & PP_AVFS_MASK ? true : false;
 152         data->registry_data.led_dpm_enabled = 1;
 153
 154         data->registry_data.vr0hot_enabled = 1;
 155         data->registry_data.vr1hot_enabled = 1;
 156         data->registry_data.regulator_hot_gpio_support = 1;
 157
 158         data->registry_data.didt_support = 1;
 159         if (data->registry_data.didt_support) {
 160                 data->registry_data.didt_mode = 6;
 161                 data->registry_data.sq_ramping_support = 1;
 162                 data->registry_data.db_ramping_support = 0;
 163                 data->registry_data.td_ramping_support = 0;
 164                 data->registry_data.tcp_ramping_support = 0;
 165                 data->registry_data.dbr_ramping_support = 0;
 166                 data->registry_data.edc_didt_support = 1;
 167                 data->registry_data.gc_didt_support = 0;
 168                 data->registry_data.psm_didt_support = 0;
 169         }
 170
 171         data->display_voltage_mode = PPVEGA10_VEGA10DISPLAYVOLTAGEMODE_DFLT;
 172         data->dcef_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 173         data->dcef_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 174         data->dcef_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 175         data->disp_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 176         data->disp_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 177         data->disp_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 178         data->pixel_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 179         data->pixel_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 180         data->pixel_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 181         data->phy_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 182         data->phy_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 183         data->phy_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 184
 185         data->gfxclk_average_alpha = PPVEGA10_VEGA10GFXCLKAVERAGEALPHA_DFLT;
 186         data->socclk_average_alpha = PPVEGA10_VEGA10SOCCLKAVERAGEALPHA_DFLT;
 187         data->uclk_average_alpha = PPVEGA10_VEGA10UCLKCLKAVERAGEALPHA_DFLT;
 188         data->gfx_activity_average_alpha = PPVEGA10_VEGA10GFXACTIVITYAVERAGEALPHA_DFLT;
 189 }
 190
 191 static int vega10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
 192 {
 193         struct vega10_hwmgr *data = hwmgr->backend;
 194         struct phm_ppt_v2_information *table_info =
 195                         (struct phm_ppt_v2_information *)hwmgr->pptable;
 196         struct amdgpu_device *adev = hwmgr->adev;
 197
 198         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 199                         PHM_PlatformCaps_SclkDeepSleep);
 200
 201         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 202                         PHM_PlatformCaps_DynamicPatchPowerState);
 203
 204         if (data->vddci_control == VEGA10_VOLTAGE_CONTROL_NONE)
 205                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 206                                 PHM_PlatformCaps_ControlVDDCI);
 207
 208         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 209                         PHM_PlatformCaps_EnableSMU7ThermalManagement);
 210
 211         if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
 212                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 213                                 PHM_PlatformCaps_UVDPowerGating);
 214
 215         if (adev->pg_flags & AMD_PG_SUPPORT_VCE)
 216                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 217                                 PHM_PlatformCaps_VCEPowerGating);
 218
 219         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 220                         PHM_PlatformCaps_UnTabledHardwareInterface);
 221
 222         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 223                         PHM_PlatformCaps_FanSpeedInTableIsRPM);
 224
 225         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 226                         PHM_PlatformCaps_ODFuzzyFanControlSupport);
 227
 228         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 229                                 PHM_PlatformCaps_DynamicPowerManagement);
 230
 231         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 232                         PHM_PlatformCaps_SMC);
 233
 234         /* power tune caps */
 235         /* assume disabled */
 236         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 237                         PHM_PlatformCaps_PowerContainment);
 238         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 239                         PHM_PlatformCaps_DiDtSupport);
 240         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 241                         PHM_PlatformCaps_SQRamping);
 242         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 243                         PHM_PlatformCaps_DBRamping);
 244         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 245                         PHM_PlatformCaps_TDRamping);
 246         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 247                         PHM_PlatformCaps_TCPRamping);
 248         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 249                         PHM_PlatformCaps_DBRRamping);
 250         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 251                         PHM_PlatformCaps_DiDtEDCEnable);
 252         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 253                         PHM_PlatformCaps_GCEDC);
 254         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 255                         PHM_PlatformCaps_PSM);
 256
 257         if (data->registry_data.didt_support) {
 258                 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtSupport);
 259                 if (data->registry_data.sq_ramping_support)
 260                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping);
 261                 if (data->registry_data.db_ramping_support)
 262                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping);
 263                 if (data->registry_data.td_ramping_support)
 264                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping);
 265                 if (data->registry_data.tcp_ramping_support)
 266                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping);
 267                 if (data->registry_data.dbr_ramping_support)
 268                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRRamping);
 269                 if (data->registry_data.edc_didt_support)
 270                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtEDCEnable);
 271                 if (data->registry_data.gc_didt_support)
 272                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_GCEDC);
 273                 if (data->registry_data.psm_didt_support)
 274                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PSM);
 275         }
 276
 277         if (data->registry_data.power_containment_support)
 278                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 279                                 PHM_PlatformCaps_PowerContainment);
 280         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 281                         PHM_PlatformCaps_CAC);
 282
 283         if (table_info->tdp_table->usClockStretchAmount &&
 284                         data->registry_data.clock_stretcher_support)
 285                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 286                                 PHM_PlatformCaps_ClockStretcher);
 287
 288         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 289                         PHM_PlatformCaps_RegulatorHot);
 290         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 291                         PHM_PlatformCaps_AutomaticDCTransition);
 292
 293         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 294                         PHM_PlatformCaps_UVDDPM);
 295         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 296                         PHM_PlatformCaps_VCEDPM);
 297
 298         return 0;
 299 }
 300
 301 static int vega10_odn_initial_default_setting(struct pp_hwmgr *hwmgr)
 302 {
 303         struct vega10_hwmgr *data = hwmgr->backend;
 304         struct phm_ppt_v2_information *table_info =
 305                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
 306         struct vega10_odn_dpm_table *odn_table = &(data->odn_dpm_table);
 307         struct vega10_odn_vddc_lookup_table *od_lookup_table;
 308         struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
 309         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table[3];
 310         struct phm_ppt_v1_clock_voltage_dependency_table *od_table[3];
 311         struct pp_atomfwctrl_avfs_parameters avfs_params = {0};
 312         uint32_t i;
 313         int result;
 314
 315         result = pp_atomfwctrl_get_avfs_information(hwmgr, &avfs_params);
 316         if (!result) {
 317                 data->odn_dpm_table.max_vddc = avfs_params.ulMaxVddc;
 318                 data->odn_dpm_table.min_vddc = avfs_params.ulMinVddc;
 319         }
 320
 321         od_lookup_table = &odn_table->vddc_lookup_table;
 322         vddc_lookup_table = table_info->vddc_lookup_table;
 323
 324         for (i = 0; i < vddc_lookup_table->count; i++)
 325                 od_lookup_table->entries[i].us_vdd = vddc_lookup_table->entries[i].us_vdd;
 326
 327         od_lookup_table->count = vddc_lookup_table->count;
 328
 329         dep_table[0] = table_info->vdd_dep_on_sclk;
 330         dep_table[1] = table_info->vdd_dep_on_mclk;
 331         dep_table[2] = table_info->vdd_dep_on_socclk;
 332         od_table[0] = (struct phm_ppt_v1_clock_voltage_dependency_table *)&odn_table->vdd_dep_on_sclk;
 333         od_table[1] = (struct phm_ppt_v1_clock_voltage_dependency_table *)&odn_table->vdd_dep_on_mclk;
 334         od_table[2] = (struct phm_ppt_v1_clock_voltage_dependency_table *)&odn_table->vdd_dep_on_socclk;
 335
 336         for (i = 0; i < 3; i++)
 337                 smu_get_voltage_dependency_table_ppt_v1(dep_table[i], od_table[i]);
 338
 339         if (odn_table->max_vddc == 0 || odn_table->max_vddc > 2000)
 340                 odn_table->max_vddc = dep_table[0]->entries[dep_table[0]->count - 1].vddc;
 341         if (odn_table->min_vddc == 0 || odn_table->min_vddc > 2000)
 342                 odn_table->min_vddc = dep_table[0]->entries[0].vddc;
 343
 344         i = od_table[2]->count - 1;
 345         od_table[2]->entries[i].clk = hwmgr->platform_descriptor.overdriveLimit.memoryClock > od_table[2]->entries[i].clk ?
 346                                         hwmgr->platform_descriptor.overdriveLimit.memoryClock :
 347                                         od_table[2]->entries[i].clk;
 348         od_table[2]->entries[i].vddc = odn_table->max_vddc > od_table[2]->entries[i].vddc ?
 349                                         odn_table->max_vddc :
 350                                         od_table[2]->entries[i].vddc;
 351
 352         return 0;
 353 }
 354
 355 static void vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr)
 356 {
 357         struct vega10_hwmgr *data = hwmgr->backend;
 358         int i;
 359         uint32_t sub_vendor_id, hw_revision;
 360         uint32_t top32, bottom32;
 361         struct amdgpu_device *adev = hwmgr->adev;
 362
 363         vega10_initialize_power_tune_defaults(hwmgr);
 364
 365         for (i = 0; i < GNLD_FEATURES_MAX; i++) {
 366                 data->smu_features[i].smu_feature_id = 0xffff;
 367                 data->smu_features[i].smu_feature_bitmap = 1 << i;
 368                 data->smu_features[i].enabled = false;
 369                 data->smu_features[i].supported = false;
 370         }
 371
 372         data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_id =
 373                         FEATURE_DPM_PREFETCHER_BIT;
 374         data->smu_features[GNLD_DPM_GFXCLK].smu_feature_id =
 375                         FEATURE_DPM_GFXCLK_BIT;
 376         data->smu_features[GNLD_DPM_UCLK].smu_feature_id =
 377                         FEATURE_DPM_UCLK_BIT;
 378         data->smu_features[GNLD_DPM_SOCCLK].smu_feature_id =
 379                         FEATURE_DPM_SOCCLK_BIT;
 380         data->smu_features[GNLD_DPM_UVD].smu_feature_id =
 381                         FEATURE_DPM_UVD_BIT;
 382         data->smu_features[GNLD_DPM_VCE].smu_feature_id =
 383                         FEATURE_DPM_VCE_BIT;
 384         data->smu_features[GNLD_DPM_MP0CLK].smu_feature_id =
 385                         FEATURE_DPM_MP0CLK_BIT;
 386         data->smu_features[GNLD_DPM_LINK].smu_feature_id =
 387                         FEATURE_DPM_LINK_BIT;
 388         data->smu_features[GNLD_DPM_DCEFCLK].smu_feature_id =
 389                         FEATURE_DPM_DCEFCLK_BIT;
 390         data->smu_features[GNLD_ULV].smu_feature_id =
 391                         FEATURE_ULV_BIT;
 392         data->smu_features[GNLD_AVFS].smu_feature_id =
 393                         FEATURE_AVFS_BIT;
 394         data->smu_features[GNLD_DS_GFXCLK].smu_feature_id =
 395                         FEATURE_DS_GFXCLK_BIT;
 396         data->smu_features[GNLD_DS_SOCCLK].smu_feature_id =
 397                         FEATURE_DS_SOCCLK_BIT;
 398         data->smu_features[GNLD_DS_LCLK].smu_feature_id =
 399                         FEATURE_DS_LCLK_BIT;
 400         data->smu_features[GNLD_PPT].smu_feature_id =
 401                         FEATURE_PPT_BIT;
 402         data->smu_features[GNLD_TDC].smu_feature_id =
 403                         FEATURE_TDC_BIT;
 404         data->smu_features[GNLD_THERMAL].smu_feature_id =
 405                         FEATURE_THERMAL_BIT;
 406         data->smu_features[GNLD_GFX_PER_CU_CG].smu_feature_id =
 407                         FEATURE_GFX_PER_CU_CG_BIT;
 408         data->smu_features[GNLD_RM].smu_feature_id =
 409                         FEATURE_RM_BIT;
 410         data->smu_features[GNLD_DS_DCEFCLK].smu_feature_id =
 411                         FEATURE_DS_DCEFCLK_BIT;
 412         data->smu_features[GNLD_ACDC].smu_feature_id =
 413                         FEATURE_ACDC_BIT;
 414         data->smu_features[GNLD_VR0HOT].smu_feature_id =
 415                         FEATURE_VR0HOT_BIT;
 416         data->smu_features[GNLD_VR1HOT].smu_feature_id =
 417                         FEATURE_VR1HOT_BIT;
 418         data->smu_features[GNLD_FW_CTF].smu_feature_id =
 419                         FEATURE_FW_CTF_BIT;
 420         data->smu_features[GNLD_LED_DISPLAY].smu_feature_id =
 421                         FEATURE_LED_DISPLAY_BIT;
 422         data->smu_features[GNLD_FAN_CONTROL].smu_feature_id =
 423                         FEATURE_FAN_CONTROL_BIT;
 424         data->smu_features[GNLD_ACG].smu_feature_id = FEATURE_ACG_BIT;
 425         data->smu_features[GNLD_DIDT].smu_feature_id = FEATURE_GFX_EDC_BIT;
 426         data->smu_features[GNLD_PCC_LIMIT].smu_feature_id = FEATURE_PCC_LIMIT_CONTROL_BIT;
 427
 428         if (!data->registry_data.prefetcher_dpm_key_disabled)
 429                 data->smu_features[GNLD_DPM_PREFETCHER].supported = true;
 430
 431         if (!data->registry_data.sclk_dpm_key_disabled)
 432                 data->smu_features[GNLD_DPM_GFXCLK].supported = true;
 433
 434         if (!data->registry_data.mclk_dpm_key_disabled)
 435                 data->smu_features[GNLD_DPM_UCLK].supported = true;
 436
 437         if (!data->registry_data.socclk_dpm_key_disabled)
 438                 data->smu_features[GNLD_DPM_SOCCLK].supported = true;
 439
 440         if (PP_CAP(PHM_PlatformCaps_UVDDPM))
 441                 data->smu_features[GNLD_DPM_UVD].supported = true;
 442
 443         if (PP_CAP(PHM_PlatformCaps_VCEDPM))
 444                 data->smu_features[GNLD_DPM_VCE].supported = true;
 445
 446         if (!data->registry_data.pcie_dpm_key_disabled)
 447                 data->smu_features[GNLD_DPM_LINK].supported = true;
 448
 449         if (!data->registry_data.dcefclk_dpm_key_disabled)
 450                 data->smu_features[GNLD_DPM_DCEFCLK].supported = true;
 451
 452         if (PP_CAP(PHM_PlatformCaps_SclkDeepSleep) &&
 453             data->registry_data.sclk_deep_sleep_support) {
 454                 data->smu_features[GNLD_DS_GFXCLK].supported = true;
 455                 data->smu_features[GNLD_DS_SOCCLK].supported = true;
 456                 data->smu_features[GNLD_DS_LCLK].supported = true;
 457                 data->smu_features[GNLD_DS_DCEFCLK].supported = true;
 458         }
 459
 460         if (data->registry_data.enable_pkg_pwr_tracking_feature)
 461                 data->smu_features[GNLD_PPT].supported = true;
 462
 463         if (data->registry_data.enable_tdc_limit_feature)
 464                 data->smu_features[GNLD_TDC].supported = true;
 465
 466         if (data->registry_data.thermal_support)
 467                 data->smu_features[GNLD_THERMAL].supported = true;
 468
 469         if (data->registry_data.fan_control_support)
 470                 data->smu_features[GNLD_FAN_CONTROL].supported = true;
 471
 472         if (data->registry_data.fw_ctf_enabled)
 473                 data->smu_features[GNLD_FW_CTF].supported = true;
 474
 475         if (data->registry_data.avfs_support)
 476                 data->smu_features[GNLD_AVFS].supported = true;
 477
 478         if (data->registry_data.led_dpm_enabled)
 479                 data->smu_features[GNLD_LED_DISPLAY].supported = true;
 480
 481         if (data->registry_data.vr1hot_enabled)
 482                 data->smu_features[GNLD_VR1HOT].supported = true;
 483
 484         if (data->registry_data.vr0hot_enabled)
 485                 data->smu_features[GNLD_VR0HOT].supported = true;
 486
 487         smum_send_msg_to_smc(hwmgr,
 488                         PPSMC_MSG_GetSmuVersion,
 489                         &hwmgr->smu_version);
 490                 /* ACG firmware has major version 5 */
 491         if ((hwmgr->smu_version & 0xff000000) == 0x5000000)
 492                 data->smu_features[GNLD_ACG].supported = true;
 493         if (data->registry_data.didt_support)
 494                 data->smu_features[GNLD_DIDT].supported = true;
 495
 496         hw_revision = adev->pdev->revision;
 497         sub_vendor_id = adev->pdev->subsystem_vendor;
 498
 499         if ((hwmgr->chip_id == 0x6862 ||
 500                 hwmgr->chip_id == 0x6861 ||
 501                 hwmgr->chip_id == 0x6868) &&
 502                 (hw_revision == 0) &&
 503                 (sub_vendor_id != 0x1002))
 504                 data->smu_features[GNLD_PCC_LIMIT].supported = true;
 505
 506         /* Get the SN to turn into a Unique ID */
 507         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32, &top32);
 508         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32, &bottom32);
 509
 510         adev->unique_id = ((uint64_t)bottom32 << 32) | top32;
 511 }
 512
 513 #ifdef PPLIB_VEGA10_EVV_SUPPORT
 514 static int vega10_get_socclk_for_voltage_evv(struct pp_hwmgr *hwmgr,
 515         phm_ppt_v1_voltage_lookup_table *lookup_table,
 516         uint16_t virtual_voltage_id, int32_t *socclk)
 517 {
 518         uint8_t entry_id;
 519         uint8_t voltage_id;
 520         struct phm_ppt_v2_information *table_info =
 521                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
 522
 523         PP_ASSERT_WITH_CODE(lookup_table->count != 0,
 524                         "Lookup table is empty",
 525                         return -EINVAL);
 526
 527         /* search for leakage voltage ID 0xff01 ~ 0xff08 and sclk */
 528         for (entry_id = 0; entry_id < table_info->vdd_dep_on_sclk->count; entry_id++) {
 529                 voltage_id = table_info->vdd_dep_on_socclk->entries[entry_id].vddInd;
 530                 if (lookup_table->entries[voltage_id].us_vdd == virtual_voltage_id)
 531                         break;
 532         }
 533
 534         PP_ASSERT_WITH_CODE(entry_id < table_info->vdd_dep_on_socclk->count,
 535                         "Can't find requested voltage id in vdd_dep_on_socclk table!",
 536                         return -EINVAL);
 537
 538         *socclk = table_info->vdd_dep_on_socclk->entries[entry_id].clk;
 539
 540         return 0;
 541 }
 542
 543 #define ATOM_VIRTUAL_VOLTAGE_ID0             0xff01
 544 /**
 545  * Get Leakage VDDC based on leakage ID.
 546  *
 547  * @hwmgr:  the address of the powerplay hardware manager.
 548  * return:  always 0.
 549  */
 550 static int vega10_get_evv_voltages(struct pp_hwmgr *hwmgr)
 551 {
 552         struct vega10_hwmgr *data = hwmgr->backend;
 553         uint16_t vv_id;
 554         uint32_t vddc = 0;
 555         uint16_t i, j;
 556         uint32_t sclk = 0;
 557         struct phm_ppt_v2_information *table_info =
 558                         (struct phm_ppt_v2_information *)hwmgr->pptable;
 559         struct phm_ppt_v1_clock_voltage_dependency_table *socclk_table =
 560                         table_info->vdd_dep_on_socclk;
 561         int result;
 562
 563         for (i = 0; i < VEGA10_MAX_LEAKAGE_COUNT; i++) {
 564                 vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
 565
 566                 if (!vega10_get_socclk_for_voltage_evv(hwmgr,
 567                                 table_info->vddc_lookup_table, vv_id, &sclk)) {
 568                         if (PP_CAP(PHM_PlatformCaps_ClockStretcher)) {
 569                                 for (j = 1; j < socclk_table->count; j++) {
 570                                         if (socclk_table->entries[j].clk == sclk &&
 571                                                         socclk_table->entries[j].cks_enable == 0) {
 572                                                 sclk += 5000;
 573                                                 break;
 574                                         }
 575                                 }
 576                         }
 577
 578                         PP_ASSERT_WITH_CODE(!atomctrl_get_voltage_evv_on_sclk_ai(hwmgr,
 579                                         VOLTAGE_TYPE_VDDC, sclk, vv_id, &vddc),
 580                                         "Error retrieving EVV voltage value!",
 581                                         continue);
 582
 583
 584                         /* need to make sure vddc is less than 2v or else, it could burn the ASIC. */
 585                         PP_ASSERT_WITH_CODE((vddc < 2000 && vddc != 0),
 586                                         "Invalid VDDC value", result = -EINVAL;);
 587
 588                         /* the voltage should not be zero nor equal to leakage ID */
 589                         if (vddc != 0 && vddc != vv_id) {
 590                                 data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = (uint16_t)(vddc/100);
 591                                 data->vddc_leakage.leakage_id[data->vddc_leakage.count] = vv_id;
 592                                 data->vddc_leakage.count++;
 593                         }
 594                 }
 595         }
 596
 597         return 0;
 598 }
 599
 600 /**
 601  * Change virtual leakage voltage to actual value.
 602  *
 603  * @hwmgr:         the address of the powerplay hardware manager.
 604  * @voltage:       pointer to changing voltage
 605  * @leakage_table: pointer to leakage table
 606  */
 607 static void vega10_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr,
 608                 uint16_t *voltage, struct vega10_leakage_voltage *leakage_table)
 609 {
 610         uint32_t index;
 611
 612         /* search for leakage voltage ID 0xff01 ~ 0xff08 */
 613         for (index = 0; index < leakage_table->count; index++) {
 614                 /* if this voltage matches a leakage voltage ID */
 615                 /* patch with actual leakage voltage */
 616                 if (leakage_table->leakage_id[index] == *voltage) {
 617                         *voltage = leakage_table->actual_voltage[index];
 618                         break;
 619                 }
 620         }
 621
 622         if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
 623                 pr_info("Voltage value looks like a Leakage ID but it's not patched\n");
 624 }
 625
 626 /**
 627  * Patch voltage lookup table by EVV leakages.
 628  *
 629  * @hwmgr:         the address of the powerplay hardware manager.
 630  * @lookup_table:  pointer to voltage lookup table
 631  * @leakage_table: pointer to leakage table
 632  * return:         always 0
 633  */
 634 static int vega10_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
 635                 phm_ppt_v1_voltage_lookup_table *lookup_table,
 636                 struct vega10_leakage_voltage *leakage_table)
 637 {
 638         uint32_t i;
 639
 640         for (i = 0; i < lookup_table->count; i++)
 641                 vega10_patch_with_vdd_leakage(hwmgr,
 642                                 &lookup_table->entries[i].us_vdd, leakage_table);
 643
 644         return 0;
 645 }
 646
 647 static int vega10_patch_clock_voltage_limits_with_vddc_leakage(
 648                 struct pp_hwmgr *hwmgr, struct vega10_leakage_voltage *leakage_table,
 649                 uint16_t *vddc)
 650 {
 651         vega10_patch_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table);
 652
 653         return 0;
 654 }
 655 #endif
 656
 657 static int vega10_patch_voltage_dependency_tables_with_lookup_table(
 658                 struct pp_hwmgr *hwmgr)
 659 {
 660         uint8_t entry_id, voltage_id;
 661         unsigned i;
 662         struct phm_ppt_v2_information *table_info =
 663                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
 664         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
 665                         table_info->mm_dep_table;
 666         struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table =
 667                         table_info->vdd_dep_on_mclk;
 668
 669         for (i = 0; i < 6; i++) {
 670                 struct phm_ppt_v1_clock_voltage_dependency_table *vdt;
 671                 switch (i) {
 672                         case 0: vdt = table_info->vdd_dep_on_socclk; break;
 673                         case 1: vdt = table_info->vdd_dep_on_sclk; break;
 674                         case 2: vdt = table_info->vdd_dep_on_dcefclk; break;
 675                         case 3: vdt = table_info->vdd_dep_on_pixclk; break;
 676                         case 4: vdt = table_info->vdd_dep_on_dispclk; break;
 677                         case 5: vdt = table_info->vdd_dep_on_phyclk; break;
 678                 }
 679
 680                 for (entry_id = 0; entry_id < vdt->count; entry_id++) {
 681                         voltage_id = vdt->entries[entry_id].vddInd;
 682                         vdt->entries[entry_id].vddc =
 683                                         table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
 684                 }
 685         }
 686
 687         for (entry_id = 0; entry_id < mm_table->count; ++entry_id) {
 688                 voltage_id = mm_table->entries[entry_id].vddcInd;
 689                 mm_table->entries[entry_id].vddc =
 690                         table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
 691         }
 692
 693         for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) {
 694                 voltage_id = mclk_table->entries[entry_id].vddInd;
 695                 mclk_table->entries[entry_id].vddc =
 696                                 table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
 697                 voltage_id = mclk_table->entries[entry_id].vddciInd;
 698                 mclk_table->entries[entry_id].vddci =
 699                                 table_info->vddci_lookup_table->entries[voltage_id].us_vdd;
 700                 voltage_id = mclk_table->entries[entry_id].mvddInd;
 701                 mclk_table->entries[entry_id].mvdd =
 702                                 table_info->vddmem_lookup_table->entries[voltage_id].us_vdd;
 703         }
 704
 705
 706         return 0;
 707
 708 }
 709
 710 static int vega10_sort_lookup_table(struct pp_hwmgr *hwmgr,
 711                 struct phm_ppt_v1_voltage_lookup_table *lookup_table)
 712 {
 713         uint32_t table_size, i, j;
 714
 715         PP_ASSERT_WITH_CODE(lookup_table && lookup_table->count,
 716                 "Lookup table is empty", return -EINVAL);
 717
 718         table_size = lookup_table->count;
 719
 720         /* Sorting voltages */
 721         for (i = 0; i < table_size - 1; i++) {
 722                 for (j = i + 1; j > 0; j--) {
 723                         if (lookup_table->entries[j].us_vdd <
 724                                         lookup_table->entries[j - 1].us_vdd) {
 725                                 swap(lookup_table->entries[j - 1],
 726                                      lookup_table->entries[j]);
 727                         }
 728                 }
 729         }
 730
 731         return 0;
 732 }
 733
 734 static int vega10_complete_dependency_tables(struct pp_hwmgr *hwmgr)
 735 {
 736         int result = 0;
 737         int tmp_result;
 738         struct phm_ppt_v2_information *table_info =
 739                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
 740 #ifdef PPLIB_VEGA10_EVV_SUPPORT
 741         struct vega10_hwmgr *data = hwmgr->backend;
 742
 743         tmp_result = vega10_patch_lookup_table_with_leakage(hwmgr,
 744                         table_info->vddc_lookup_table, &(data->vddc_leakage));
 745         if (tmp_result)
 746                 result = tmp_result;
 747
 748         tmp_result = vega10_patch_clock_voltage_limits_with_vddc_leakage(hwmgr,
 749                         &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc);
 750         if (tmp_result)
 751                 result = tmp_result;
 752 #endif
 753
 754         tmp_result = vega10_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
 755         if (tmp_result)
 756                 result = tmp_result;
 757
 758         tmp_result = vega10_sort_lookup_table(hwmgr, table_info->vddc_lookup_table);
 759         if (tmp_result)
 760                 result = tmp_result;
 761
 762         return result;
 763 }
 764
 765 static int vega10_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
 766 {
 767         struct phm_ppt_v2_information *table_info =
 768                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
 769         struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
 770                         table_info->vdd_dep_on_socclk;
 771         struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
 772                         table_info->vdd_dep_on_mclk;
 773
 774         PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table,
 775                 "VDD dependency on SCLK table is missing. This table is mandatory", return -EINVAL);
 776         PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
 777                 "VDD dependency on SCLK table is empty. This table is mandatory", return -EINVAL);
 778
 779         PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table,
 780                 "VDD dependency on MCLK table is missing.  This table is mandatory", return -EINVAL);
 781         PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
 782                 "VDD dependency on MCLK table is empty.  This table is mandatory", return -EINVAL);
 783
 784         table_info->max_clock_voltage_on_ac.sclk =
 785                 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
 786         table_info->max_clock_voltage_on_ac.mclk =
 787                 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
 788         table_info->max_clock_voltage_on_ac.vddc =
 789                 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
 790         table_info->max_clock_voltage_on_ac.vddci =
 791                 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
 792
 793         hwmgr->dyn_state.max_clock_voltage_on_ac.sclk =
 794                 table_info->max_clock_voltage_on_ac.sclk;
 795         hwmgr->dyn_state.max_clock_voltage_on_ac.mclk =
 796                 table_info->max_clock_voltage_on_ac.mclk;
 797         hwmgr->dyn_state.max_clock_voltage_on_ac.vddc =
 798                 table_info->max_clock_voltage_on_ac.vddc;
 799         hwmgr->dyn_state.max_clock_voltage_on_ac.vddci =
 800                 table_info->max_clock_voltage_on_ac.vddci;
 801
 802         return 0;
 803 }
 804
 805 static int vega10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
 806 {
 807         kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
 808         hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
 809
 810         kfree(hwmgr->backend);
 811         hwmgr->backend = NULL;
 812
 813         return 0;
 814 }
 815
 816 static int vega10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
 817 {
 818         int result = 0;
 819         struct vega10_hwmgr *data;
 820         uint32_t config_telemetry = 0;
 821         struct pp_atomfwctrl_voltage_table vol_table;
 822         struct amdgpu_device *adev = hwmgr->adev;
 823
 824         data = kzalloc(sizeof(struct vega10_hwmgr), GFP_KERNEL);
 825         if (data == NULL)
 826                 return -ENOMEM;
 827
 828         hwmgr->backend = data;
 829
 830         hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
 831         hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 832         hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 833
 834         vega10_set_default_registry_data(hwmgr);
 835         data->disable_dpm_mask = 0xff;
 836
 837         /* need to set voltage control types before EVV patching */
 838         data->vddc_control = VEGA10_VOLTAGE_CONTROL_NONE;
 839         data->mvdd_control = VEGA10_VOLTAGE_CONTROL_NONE;
 840         data->vddci_control = VEGA10_VOLTAGE_CONTROL_NONE;
 841
 842         /* VDDCR_SOC */
 843         if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr,
 844                         VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2)) {
 845                 if (!pp_atomfwctrl_get_voltage_table_v4(hwmgr,
 846                                 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2,
 847                                 &vol_table)) {
 848                         config_telemetry = ((vol_table.telemetry_slope << 8) & 0xff00) |
 849                                         (vol_table.telemetry_offset & 0xff);
 850                         data->vddc_control = VEGA10_VOLTAGE_CONTROL_BY_SVID2;
 851                 }
 852         } else {
 853                 kfree(hwmgr->backend);
 854                 hwmgr->backend = NULL;
 855                 PP_ASSERT_WITH_CODE(false,
 856                                 "VDDCR_SOC is not SVID2!",
 857                                 return -1);
 858         }
 859
 860         /* MVDDC */
 861         if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr,
 862                         VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2)) {
 863                 if (!pp_atomfwctrl_get_voltage_table_v4(hwmgr,
 864                                 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2,
 865                                 &vol_table)) {
 866                         config_telemetry |=
 867                                         ((vol_table.telemetry_slope << 24) & 0xff000000) |
 868                                         ((vol_table.telemetry_offset << 16) & 0xff0000);
 869                         data->mvdd_control = VEGA10_VOLTAGE_CONTROL_BY_SVID2;
 870                 }
 871         }
 872
 873          /* VDDCI_MEM */
 874         if (PP_CAP(PHM_PlatformCaps_ControlVDDCI)) {
 875                 if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr,
 876                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
 877                         data->vddci_control = VEGA10_VOLTAGE_CONTROL_BY_GPIO;
 878         }
 879
 880         data->config_telemetry = config_telemetry;
 881
 882         vega10_set_features_platform_caps(hwmgr);
 883
 884         vega10_init_dpm_defaults(hwmgr);
 885
 886 #ifdef PPLIB_VEGA10_EVV_SUPPORT
 887         /* Get leakage voltage based on leakage ID. */
 888         PP_ASSERT_WITH_CODE(!vega10_get_evv_voltages(hwmgr),
 889                         "Get EVV Voltage Failed.  Abort Driver loading!",
 890                         return -1);
 891 #endif
 892
 893         /* Patch our voltage dependency table with actual leakage voltage
 894          * We need to perform leakage translation before it's used by other functions
 895          */
 896         vega10_complete_dependency_tables(hwmgr);
 897
 898         /* Parse pptable data read from VBIOS */
 899         vega10_set_private_data_based_on_pptable(hwmgr);
 900
 901         data->is_tlu_enabled = false;
 902
 903         hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
 904                         VEGA10_MAX_HARDWARE_POWERLEVELS;
 905         hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
 906         hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
 907
 908         hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
 909         /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
 910         hwmgr->platform_descriptor.clockStep.engineClock = 500;
 911         hwmgr->platform_descriptor.clockStep.memoryClock = 500;
 912
 913         data->total_active_cus = adev->gfx.cu_info.number;
 914         if (!hwmgr->not_vf)
 915                 return result;
 916
 917         /* Setup default Overdrive Fan control settings */
 918         data->odn_fan_table.target_fan_speed =
 919                         hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM;
 920         data->odn_fan_table.target_temperature =
 921                         hwmgr->thermal_controller.
 922                         advanceFanControlParameters.ucTargetTemperature;
 923         data->odn_fan_table.min_performance_clock =
 924                         hwmgr->thermal_controller.advanceFanControlParameters.
 925                         ulMinFanSCLKAcousticLimit;
 926         data->odn_fan_table.min_fan_limit =
 927                         hwmgr->thermal_controller.
 928                         advanceFanControlParameters.usFanPWMMinLimit *
 929                         hwmgr->thermal_controller.fanInfo.ulMaxRPM / 100;
 930
 931         data->mem_channels = (RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0) &
 932                         DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK) >>
 933                         DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
 934         PP_ASSERT_WITH_CODE(data->mem_channels < ARRAY_SIZE(channel_number),
 935                         "Mem Channel Index Exceeded maximum!",
 936                         return -EINVAL);
 937
 938         return result;
 939 }
 940
 941 static int vega10_init_sclk_threshold(struct pp_hwmgr *hwmgr)
 942 {
 943         struct vega10_hwmgr *data = hwmgr->backend;
 944
 945         data->low_sclk_interrupt_threshold = 0;
 946
 947         return 0;
 948 }
 949
 950 static int vega10_setup_dpm_led_config(struct pp_hwmgr *hwmgr)
 951 {
 952         struct vega10_hwmgr *data = hwmgr->backend;
 953         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
 954
 955         struct pp_atomfwctrl_voltage_table table;
 956         uint8_t i, j;
 957         uint32_t mask = 0;
 958         uint32_t tmp;
 959         int32_t ret = 0;
 960
 961         ret = pp_atomfwctrl_get_voltage_table_v4(hwmgr, VOLTAGE_TYPE_LEDDPM,
 962                                                 VOLTAGE_OBJ_GPIO_LUT, &table);
 963
 964         if (!ret) {
 965                 tmp = table.mask_low;
 966                 for (i = 0, j = 0; i < 32; i++) {
 967                         if (tmp & 1) {
 968                                 mask |= (uint32_t)(i << (8 * j));
 969                                 if (++j >= 3)
 970                                         break;
 971                         }
 972                         tmp >>= 1;
 973                 }
 974         }
 975
 976         pp_table->LedPin0 = (uint8_t)(mask & 0xff);
 977         pp_table->LedPin1 = (uint8_t)((mask >> 8) & 0xff);
 978         pp_table->LedPin2 = (uint8_t)((mask >> 16) & 0xff);
 979         return 0;
 980 }
 981
 982 static int vega10_setup_asic_task(struct pp_hwmgr *hwmgr)
 983 {
 984         if (!hwmgr->not_vf)
 985                 return 0;
 986
 987         PP_ASSERT_WITH_CODE(!vega10_init_sclk_threshold(hwmgr),
 988                         "Failed to init sclk threshold!",
 989                         return -EINVAL);
 990
 991         PP_ASSERT_WITH_CODE(!vega10_setup_dpm_led_config(hwmgr),
 992                         "Failed to set up led dpm config!",
 993                         return -EINVAL);
 994
 995         smum_send_msg_to_smc_with_parameter(hwmgr,
 996                                 PPSMC_MSG_NumOfDisplays,
 997                                 0,
 998                                 NULL);
 999
1000         return 0;
1001 }
1002
1003 /**
1004  * Remove repeated voltage values and create table with unique values.
1005  *
1006  * @hwmgr:      the address of the powerplay hardware manager.
1007  * @vol_table:  the pointer to changing voltage table
1008  * return:      0 in success
1009  */
1010 static int vega10_trim_voltage_table(struct pp_hwmgr *hwmgr,
1011                 struct pp_atomfwctrl_voltage_table *vol_table)
1012 {
1013         uint32_t i, j;
1014         uint16_t vvalue;
1015         bool found = false;
1016         struct pp_atomfwctrl_voltage_table *table;
1017
1018         PP_ASSERT_WITH_CODE(vol_table,
1019                         "Voltage Table empty.", return -EINVAL);
1020         table = kzalloc(sizeof(struct pp_atomfwctrl_voltage_table),
1021                         GFP_KERNEL);
1022
1023         if (!table)
1024                 return -ENOMEM;
1025
1026         table->mask_low = vol_table->mask_low;
1027         table->phase_delay = vol_table->phase_delay;
1028
1029         for (i = 0; i < vol_table->count; i++) {
1030                 vvalue = vol_table->entries[i].value;
1031                 found = false;
1032
1033                 for (j = 0; j < table->count; j++) {
1034                         if (vvalue == table->entries[j].value) {
1035                                 found = true;
1036                                 break;
1037                         }
1038                 }
1039
1040                 if (!found) {
1041                         table->entries[table->count].value = vvalue;
1042                         table->entries[table->count].smio_low =
1043                                         vol_table->entries[i].smio_low;
1044                         table->count++;
1045                 }
1046         }
1047
1048         memcpy(vol_table, table, sizeof(struct pp_atomfwctrl_voltage_table));
1049         kfree(table);
1050
1051         return 0;
1052 }
1053
1054 static int vega10_get_mvdd_voltage_table(struct pp_hwmgr *hwmgr,
1055                 phm_ppt_v1_clock_voltage_dependency_table *dep_table,
1056                 struct pp_atomfwctrl_voltage_table *vol_table)
1057 {
1058         int i;
1059
1060         PP_ASSERT_WITH_CODE(dep_table->count,
1061                         "Voltage Dependency Table empty.",
1062                         return -EINVAL);
1063
1064         vol_table->mask_low = 0;
1065         vol_table->phase_delay = 0;
1066         vol_table->count = dep_table->count;
1067
1068         for (i = 0; i < vol_table->count; i++) {
1069                 vol_table->entries[i].value = dep_table->entries[i].mvdd;
1070                 vol_table->entries[i].smio_low = 0;
1071         }
1072
1073         PP_ASSERT_WITH_CODE(!vega10_trim_voltage_table(hwmgr,
1074                         vol_table),
1075                         "Failed to trim MVDD Table!",
1076                         return -1);
1077
1078         return 0;
1079 }
1080
1081 static int vega10_get_vddci_voltage_table(struct pp_hwmgr *hwmgr,
1082                 phm_ppt_v1_clock_voltage_dependency_table *dep_table,
1083                 struct pp_atomfwctrl_voltage_table *vol_table)
1084 {
1085         uint32_t i;
1086
1087         PP_ASSERT_WITH_CODE(dep_table->count,
1088                         "Voltage Dependency Table empty.",
1089                         return -EINVAL);
1090
1091         vol_table->mask_low = 0;
1092         vol_table->phase_delay = 0;
1093         vol_table->count = dep_table->count;
1094
1095         for (i = 0; i < dep_table->count; i++) {
1096                 vol_table->entries[i].value = dep_table->entries[i].vddci;
1097                 vol_table->entries[i].smio_low = 0;
1098         }
1099
1100         PP_ASSERT_WITH_CODE(!vega10_trim_voltage_table(hwmgr, vol_table),
1101                         "Failed to trim VDDCI table.",
1102                         return -1);
1103
1104         return 0;
1105 }
1106
1107 static int vega10_get_vdd_voltage_table(struct pp_hwmgr *hwmgr,
1108                 phm_ppt_v1_clock_voltage_dependency_table *dep_table,
1109                 struct pp_atomfwctrl_voltage_table *vol_table)
1110 {
1111         int i;
1112
1113         PP_ASSERT_WITH_CODE(dep_table->count,
1114                         "Voltage Dependency Table empty.",
1115                         return -EINVAL);
1116
1117         vol_table->mask_low = 0;
1118         vol_table->phase_delay = 0;
1119         vol_table->count = dep_table->count;
1120
1121         for (i = 0; i < vol_table->count; i++) {
1122                 vol_table->entries[i].value = dep_table->entries[i].vddc;
1123                 vol_table->entries[i].smio_low = 0;
1124         }
1125
1126         return 0;
1127 }
1128
1129 /* ---- Voltage Tables ----
1130  * If the voltage table would be bigger than
1131  * what will fit into the state table on
1132  * the SMC keep only the higher entries.
1133  */
1134 static void vega10_trim_voltage_table_to_fit_state_table(
1135                 struct pp_hwmgr *hwmgr,
1136                 uint32_t max_vol_steps,
1137                 struct pp_atomfwctrl_voltage_table *vol_table)
1138 {
1139         unsigned int i, diff;
1140
1141         if (vol_table->count <= max_vol_steps)
1142                 return;
1143
1144         diff = vol_table->count - max_vol_steps;
1145
1146         for (i = 0; i < max_vol_steps; i++)
1147                 vol_table->entries[i] = vol_table->entries[i + diff];
1148
1149         vol_table->count = max_vol_steps;
1150 }
1151
1152 /**
1153  * Create Voltage Tables.
1154  *
1155  * @hwmgr:  the address of the powerplay hardware manager.
1156  * return:  always 0
1157  */
1158 static int vega10_construct_voltage_tables(struct pp_hwmgr *hwmgr)
1159 {
1160         struct vega10_hwmgr *data = hwmgr->backend;
1161         struct phm_ppt_v2_information *table_info =
1162                         (struct phm_ppt_v2_information *)hwmgr->pptable;
1163         int result;
1164
1165         if (data->mvdd_control == VEGA10_VOLTAGE_CONTROL_BY_SVID2 ||
1166                         data->mvdd_control == VEGA10_VOLTAGE_CONTROL_NONE) {
1167                 result = vega10_get_mvdd_voltage_table(hwmgr,
1168                                 table_info->vdd_dep_on_mclk,
1169                                 &(data->mvdd_voltage_table));
1170                 PP_ASSERT_WITH_CODE(!result,
1171                                 "Failed to retrieve MVDDC table!",
1172                                 return result);
1173         }
1174
1175         if (data->vddci_control == VEGA10_VOLTAGE_CONTROL_NONE) {
1176                 result = vega10_get_vddci_voltage_table(hwmgr,
1177                                 table_info->vdd_dep_on_mclk,
1178                                 &(data->vddci_voltage_table));
1179                 PP_ASSERT_WITH_CODE(!result,
1180                                 "Failed to retrieve VDDCI_MEM table!",
1181                                 return result);
1182         }
1183
1184         if (data->vddc_control == VEGA10_VOLTAGE_CONTROL_BY_SVID2 ||
1185                         data->vddc_control == VEGA10_VOLTAGE_CONTROL_NONE) {
1186                 result = vega10_get_vdd_voltage_table(hwmgr,
1187                                 table_info->vdd_dep_on_sclk,
1188                                 &(data->vddc_voltage_table));
1189                 PP_ASSERT_WITH_CODE(!result,
1190                                 "Failed to retrieve VDDCR_SOC table!",
1191                                 return result);
1192         }
1193
1194         PP_ASSERT_WITH_CODE(data->vddc_voltage_table.count <= 16,
1195                         "Too many voltage values for VDDC. Trimming to fit state table.",
1196                         vega10_trim_voltage_table_to_fit_state_table(hwmgr,
1197                                         16, &(data->vddc_voltage_table)));
1198
1199         PP_ASSERT_WITH_CODE(data->vddci_voltage_table.count <= 16,
1200                         "Too many voltage values for VDDCI. Trimming to fit state table.",
1201                         vega10_trim_voltage_table_to_fit_state_table(hwmgr,
1202                                         16, &(data->vddci_voltage_table)));
1203
1204         PP_ASSERT_WITH_CODE(data->mvdd_voltage_table.count <= 16,
1205                         "Too many voltage values for MVDD. Trimming to fit state table.",
1206                         vega10_trim_voltage_table_to_fit_state_table(hwmgr,
1207                                         16, &(data->mvdd_voltage_table)));
1208
1209
1210         return 0;
1211 }
1212
1213 /*
1214  * vega10_init_dpm_state
1215  * Function to initialize all Soft Min/Max and Hard Min/Max to 0xff.
1216  *
1217  * @dpm_state: - the address of the DPM Table to initiailize.
1218  * return:   None.
1219  */
1220 static void vega10_init_dpm_state(struct vega10_dpm_state *dpm_state)
1221 {
1222         dpm_state->soft_min_level = 0xff;
1223         dpm_state->soft_max_level = 0xff;
1224         dpm_state->hard_min_level = 0xff;
1225         dpm_state->hard_max_level = 0xff;
1226 }
1227
1228 static void vega10_setup_default_single_dpm_table(struct pp_hwmgr *hwmgr,
1229                 struct vega10_single_dpm_table *dpm_table,
1230                 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table)
1231 {
1232         int i;
1233
1234         dpm_table->count = 0;
1235
1236         for (i = 0; i < dep_table->count; i++) {
1237                 if (i == 0 || dpm_table->dpm_levels[dpm_table->count - 1].value <=
1238                                 dep_table->entries[i].clk) {
1239                         dpm_table->dpm_levels[dpm_table->count].value =
1240                                         dep_table->entries[i].clk;
1241                         dpm_table->dpm_levels[dpm_table->count].enabled = true;
1242                         dpm_table->count++;
1243                 }
1244         }
1245 }
1246 static int vega10_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
1247 {
1248         struct vega10_hwmgr *data = hwmgr->backend;
1249         struct vega10_pcie_table *pcie_table = &(data->dpm_table.pcie_table);
1250         struct phm_ppt_v2_information *table_info =
1251                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
1252         struct phm_ppt_v1_pcie_table *bios_pcie_table =
1253                         table_info->pcie_table;
1254         uint32_t i;
1255
1256         PP_ASSERT_WITH_CODE(bios_pcie_table->count,
1257                         "Incorrect number of PCIE States from VBIOS!",
1258                         return -1);
1259
1260         for (i = 0; i < NUM_LINK_LEVELS; i++) {
1261                 if (data->registry_data.pcieSpeedOverride)
1262                         pcie_table->pcie_gen[i] =
1263                                         data->registry_data.pcieSpeedOverride;
1264                 else
1265                         pcie_table->pcie_gen[i] =
1266                                         bios_pcie_table->entries[i].gen_speed;
1267
1268                 if (data->registry_data.pcieLaneOverride)
1269                         pcie_table->pcie_lane[i] = (uint8_t)encode_pcie_lane_width(
1270                                         data->registry_data.pcieLaneOverride);
1271                 else
1272                         pcie_table->pcie_lane[i] = (uint8_t)encode_pcie_lane_width(
1273                                                         bios_pcie_table->entries[i].lane_width);
1274                 if (data->registry_data.pcieClockOverride)
1275                         pcie_table->lclk[i] =
1276                                         data->registry_data.pcieClockOverride;
1277                 else
1278                         pcie_table->lclk[i] =
1279                                         bios_pcie_table->entries[i].pcie_sclk;
1280         }
1281
1282         pcie_table->count = NUM_LINK_LEVELS;
1283
1284         return 0;
1285 }
1286
1287 /*
1288  * This function is to initialize all DPM state tables
1289  * for SMU based on the dependency table.
1290  * Dynamic state patching function will then trim these
1291  * state tables to the allowed range based
1292  * on the power policy or external client requests,
1293  * such as UVD request, etc.
1294  */
1295 static int vega10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
1296 {
1297         struct vega10_hwmgr *data = hwmgr->backend;
1298         struct phm_ppt_v2_information *table_info =
1299                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
1300         struct vega10_single_dpm_table *dpm_table;
1301         uint32_t i;
1302
1303         struct phm_ppt_v1_clock_voltage_dependency_table *dep_soc_table =
1304                         table_info->vdd_dep_on_socclk;
1305         struct phm_ppt_v1_clock_voltage_dependency_table *dep_gfx_table =
1306                         table_info->vdd_dep_on_sclk;
1307         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
1308                         table_info->vdd_dep_on_mclk;
1309         struct phm_ppt_v1_mm_clock_voltage_dependency_table *dep_mm_table =
1310                         table_info->mm_dep_table;
1311         struct phm_ppt_v1_clock_voltage_dependency_table *dep_dcef_table =
1312                         table_info->vdd_dep_on_dcefclk;
1313         struct phm_ppt_v1_clock_voltage_dependency_table *dep_pix_table =
1314                         table_info->vdd_dep_on_pixclk;
1315         struct phm_ppt_v1_clock_voltage_dependency_table *dep_disp_table =
1316                         table_info->vdd_dep_on_dispclk;
1317         struct phm_ppt_v1_clock_voltage_dependency_table *dep_phy_table =
1318                         table_info->vdd_dep_on_phyclk;
1319
1320         PP_ASSERT_WITH_CODE(dep_soc_table,
1321                         "SOCCLK dependency table is missing. This table is mandatory",
1322                         return -EINVAL);
1323         PP_ASSERT_WITH_CODE(dep_soc_table->count >= 1,
1324                         "SOCCLK dependency table is empty. This table is mandatory",
1325                         return -EINVAL);
1326
1327         PP_ASSERT_WITH_CODE(dep_gfx_table,
1328                         "GFXCLK dependency table is missing. This table is mandatory",
1329                         return -EINVAL);
1330         PP_ASSERT_WITH_CODE(dep_gfx_table->count >= 1,
1331                         "GFXCLK dependency table is empty. This table is mandatory",
1332                         return -EINVAL);
1333
1334         PP_ASSERT_WITH_CODE(dep_mclk_table,
1335                         "MCLK dependency table is missing. This table is mandatory",
1336                         return -EINVAL);
1337         PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1,
1338                         "MCLK dependency table has to have is missing. This table is mandatory",
1339                         return -EINVAL);
1340
1341         /* Initialize Sclk DPM table based on allow Sclk values */
1342         dpm_table = &(data->dpm_table.soc_table);
1343         vega10_setup_default_single_dpm_table(hwmgr,
1344                         dpm_table,
1345                         dep_soc_table);
1346
1347         vega10_init_dpm_state(&(dpm_table->dpm_state));
1348
1349         dpm_table = &(data->dpm_table.gfx_table);
1350         vega10_setup_default_single_dpm_table(hwmgr,
1351                         dpm_table,
1352                         dep_gfx_table);
1353         if (hwmgr->platform_descriptor.overdriveLimit.engineClock == 0)
1354                 hwmgr->platform_descriptor.overdriveLimit.engineClock =
1355                                         dpm_table->dpm_levels[dpm_table->count-1].value;
1356         vega10_init_dpm_state(&(dpm_table->dpm_state));
1357
1358         /* Initialize Mclk DPM table based on allow Mclk values */
1359         data->dpm_table.mem_table.count = 0;
1360         dpm_table = &(data->dpm_table.mem_table);
1361         vega10_setup_default_single_dpm_table(hwmgr,
1362                         dpm_table,
1363                         dep_mclk_table);
1364         if (hwmgr->platform_descriptor.overdriveLimit.memoryClock == 0)
1365                 hwmgr->platform_descriptor.overdriveLimit.memoryClock =
1366                                         dpm_table->dpm_levels[dpm_table->count-1].value;
1367         vega10_init_dpm_state(&(dpm_table->dpm_state));
1368
1369         data->dpm_table.eclk_table.count = 0;
1370         dpm_table = &(data->dpm_table.eclk_table);
1371         for (i = 0; i < dep_mm_table->count; i++) {
1372                 if (i == 0 || dpm_table->dpm_levels
1373                                 [dpm_table->count - 1].value <=
1374                                                 dep_mm_table->entries[i].eclk) {
1375                         dpm_table->dpm_levels[dpm_table->count].value =
1376                                         dep_mm_table->entries[i].eclk;
1377                         dpm_table->dpm_levels[dpm_table->count].enabled =
1378                                         (i == 0) ? true : false;
1379                         dpm_table->count++;
1380                 }
1381         }
1382         vega10_init_dpm_state(&(dpm_table->dpm_state));
1383
1384         data->dpm_table.vclk_table.count = 0;
1385         data->dpm_table.dclk_table.count = 0;
1386         dpm_table = &(data->dpm_table.vclk_table);
1387         for (i = 0; i < dep_mm_table->count; i++) {
1388                 if (i == 0 || dpm_table->dpm_levels
1389                                 [dpm_table->count - 1].value <=
1390                                                 dep_mm_table->entries[i].vclk) {
1391                         dpm_table->dpm_levels[dpm_table->count].value =
1392                                         dep_mm_table->entries[i].vclk;
1393                         dpm_table->dpm_levels[dpm_table->count].enabled =
1394                                         (i == 0) ? true : false;
1395                         dpm_table->count++;
1396                 }
1397         }
1398         vega10_init_dpm_state(&(dpm_table->dpm_state));
1399
1400         dpm_table = &(data->dpm_table.dclk_table);
1401         for (i = 0; i < dep_mm_table->count; i++) {
1402                 if (i == 0 || dpm_table->dpm_levels
1403                                 [dpm_table->count - 1].value <=
1404                                                 dep_mm_table->entries[i].dclk) {
1405                         dpm_table->dpm_levels[dpm_table->count].value =
1406                                         dep_mm_table->entries[i].dclk;
1407                         dpm_table->dpm_levels[dpm_table->count].enabled =
1408                                         (i == 0) ? true : false;
1409                         dpm_table->count++;
1410                 }
1411         }
1412         vega10_init_dpm_state(&(dpm_table->dpm_state));
1413
1414         /* Assume there is no headless Vega10 for now */
1415         dpm_table = &(data->dpm_table.dcef_table);
1416         vega10_setup_default_single_dpm_table(hwmgr,
1417                         dpm_table,
1418                         dep_dcef_table);
1419
1420         vega10_init_dpm_state(&(dpm_table->dpm_state));
1421
1422         dpm_table = &(data->dpm_table.pixel_table);
1423         vega10_setup_default_single_dpm_table(hwmgr,
1424                         dpm_table,
1425                         dep_pix_table);
1426
1427         vega10_init_dpm_state(&(dpm_table->dpm_state));
1428
1429         dpm_table = &(data->dpm_table.display_table);
1430         vega10_setup_default_single_dpm_table(hwmgr,
1431                         dpm_table,
1432                         dep_disp_table);
1433
1434         vega10_init_dpm_state(&(dpm_table->dpm_state));
1435
1436         dpm_table = &(data->dpm_table.phy_table);
1437         vega10_setup_default_single_dpm_table(hwmgr,
1438                         dpm_table,
1439                         dep_phy_table);
1440
1441         vega10_init_dpm_state(&(dpm_table->dpm_state));
1442
1443         vega10_setup_default_pcie_table(hwmgr);
1444
1445         /* Zero out the saved copy of the CUSTOM profile
1446          * This will be checked when trying to set the profile
1447          * and will require that new values be passed in
1448          */
1449         data->custom_profile_mode[0] = 0;
1450         data->custom_profile_mode[1] = 0;
1451         data->custom_profile_mode[2] = 0;
1452         data->custom_profile_mode[3] = 0;
1453
1454         /* save a copy of the default DPM table */
1455         memcpy(&(data->golden_dpm_table), &(data->dpm_table),
1456                         sizeof(struct vega10_dpm_table));
1457
1458         return 0;
1459 }
1460
1461 /*
1462  * vega10_populate_ulv_state
1463  * Function to provide parameters for Utral Low Voltage state to SMC.
1464  *
1465  * @hwmgr: - the address of the hardware manager.
1466  * return:   Always 0.
1467  */
1468 static int vega10_populate_ulv_state(struct pp_hwmgr *hwmgr)
1469 {
1470         struct vega10_hwmgr *data = hwmgr->backend;
1471         struct phm_ppt_v2_information *table_info =
1472                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
1473
1474         data->smc_state_table.pp_table.UlvOffsetVid =
1475                         (uint8_t)table_info->us_ulv_voltage_offset;
1476
1477         data->smc_state_table.pp_table.UlvSmnclkDid =
1478                         (uint8_t)(table_info->us_ulv_smnclk_did);
1479         data->smc_state_table.pp_table.UlvMp1clkDid =
1480                         (uint8_t)(table_info->us_ulv_mp1clk_did);
1481         data->smc_state_table.pp_table.UlvGfxclkBypass =
1482                         (uint8_t)(table_info->us_ulv_gfxclk_bypass);
1483         data->smc_state_table.pp_table.UlvPhaseSheddingPsi0 =
1484                         (uint8_t)(data->vddc_voltage_table.psi0_enable);
1485         data->smc_state_table.pp_table.UlvPhaseSheddingPsi1 =
1486                         (uint8_t)(data->vddc_voltage_table.psi1_enable);
1487
1488         return 0;
1489 }
1490
1491 static int vega10_populate_single_lclk_level(struct pp_hwmgr *hwmgr,
1492                 uint32_t lclock, uint8_t *curr_lclk_did)
1493 {
1494         struct pp_atomfwctrl_clock_dividers_soc15 dividers;
1495
1496         PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(
1497                         hwmgr,
1498                         COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
1499                         lclock, &dividers),
1500                         "Failed to get LCLK clock settings from VBIOS!",
1501                         return -1);
1502
1503         *curr_lclk_did = dividers.ulDid;
1504
1505         return 0;
1506 }
1507
1508 static int vega10_override_pcie_parameters(struct pp_hwmgr *hwmgr)
1509 {
1510         struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
1511         struct vega10_hwmgr *data =
1512                         (struct vega10_hwmgr *)(hwmgr->backend);
1513         uint32_t pcie_gen = 0, pcie_width = 0;
1514         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1515         int i;
1516
1517         if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
1518                 pcie_gen = 3;
1519         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
1520                 pcie_gen = 2;
1521         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
1522                 pcie_gen = 1;
1523         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
1524                 pcie_gen = 0;
1525
1526         if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
1527                 pcie_width = 6;
1528         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
1529                 pcie_width = 5;
1530         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
1531                 pcie_width = 4;
1532         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
1533                 pcie_width = 3;
1534         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
1535                 pcie_width = 2;
1536         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
1537                 pcie_width = 1;
1538
1539         for (i = 0; i < NUM_LINK_LEVELS; i++) {
1540                 if (pp_table->PcieGenSpeed[i] > pcie_gen)
1541                         pp_table->PcieGenSpeed[i] = pcie_gen;
1542
1543                 if (pp_table->PcieLaneCount[i] > pcie_width)
1544                         pp_table->PcieLaneCount[i] = pcie_width;
1545         }
1546
1547         return 0;
1548 }
1549
1550 static int vega10_populate_smc_link_levels(struct pp_hwmgr *hwmgr)
1551 {
1552         int result = -1;
1553         struct vega10_hwmgr *data = hwmgr->backend;
1554         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1555         struct vega10_pcie_table *pcie_table =
1556                         &(data->dpm_table.pcie_table);
1557         uint32_t i, j;
1558
1559         for (i = 0; i < pcie_table->count; i++) {
1560                 pp_table->PcieGenSpeed[i] = pcie_table->pcie_gen[i];
1561                 pp_table->PcieLaneCount[i] = pcie_table->pcie_lane[i];
1562
1563                 result = vega10_populate_single_lclk_level(hwmgr,
1564                                 pcie_table->lclk[i], &(pp_table->LclkDid[i]));
1565                 if (result) {
1566                         pr_info("Populate LClock Level %d Failed!\n", i);
1567                         return result;
1568                 }
1569         }
1570
1571         j = i - 1;
1572         while (i < NUM_LINK_LEVELS) {
1573                 pp_table->PcieGenSpeed[i] = pcie_table->pcie_gen[j];
1574                 pp_table->PcieLaneCount[i] = pcie_table->pcie_lane[j];
1575
1576                 result = vega10_populate_single_lclk_level(hwmgr,
1577                                 pcie_table->lclk[j], &(pp_table->LclkDid[i]));
1578                 if (result) {
1579                         pr_info("Populate LClock Level %d Failed!\n", i);
1580                         return result;
1581                 }
1582                 i++;
1583         }
1584
1585         return result;
1586 }
1587
1588 /**
1589  * Populates single SMC GFXSCLK structure using the provided engine clock
1590  *
1591  * @hwmgr:      the address of the hardware manager
1592  * @gfx_clock:  the GFX clock to use to populate the structure.
1593  * @current_gfxclk_level:  location in PPTable for the SMC GFXCLK structure.
1594  * @acg_freq:   ACG frequenty to return (MHz)
1595  */
1596 static int vega10_populate_single_gfx_level(struct pp_hwmgr *hwmgr,
1597                 uint32_t gfx_clock, PllSetting_t *current_gfxclk_level,
1598                 uint32_t *acg_freq)
1599 {
1600         struct phm_ppt_v2_information *table_info =
1601                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
1602         struct phm_ppt_v1_clock_voltage_dependency_table *dep_on_sclk;
1603         struct vega10_hwmgr *data = hwmgr->backend;
1604         struct pp_atomfwctrl_clock_dividers_soc15 dividers;
1605         uint32_t gfx_max_clock =
1606                         hwmgr->platform_descriptor.overdriveLimit.engineClock;
1607         uint32_t i = 0;
1608
1609         if (hwmgr->od_enabled)
1610                 dep_on_sclk = (struct phm_ppt_v1_clock_voltage_dependency_table *)
1611                                                 &(data->odn_dpm_table.vdd_dep_on_sclk);
1612         else
1613                 dep_on_sclk = table_info->vdd_dep_on_sclk;
1614
1615         PP_ASSERT_WITH_CODE(dep_on_sclk,
1616                         "Invalid SOC_VDD-GFX_CLK Dependency Table!",
1617                         return -EINVAL);
1618
1619         if (data->need_update_dpm_table & DPMTABLE_OD_UPDATE_SCLK)
1620                 gfx_clock = gfx_clock > gfx_max_clock ? gfx_max_clock : gfx_clock;
1621         else {
1622                 for (i = 0; i < dep_on_sclk->count; i++) {
1623                         if (dep_on_sclk->entries[i].clk == gfx_clock)
1624                                 break;
1625                 }
1626                 PP_ASSERT_WITH_CODE(dep_on_sclk->count > i,
1627                                 "Cannot find gfx_clk in SOC_VDD-GFX_CLK!",
1628                                 return -EINVAL);
1629         }
1630
1631         PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
1632                         COMPUTE_GPUCLK_INPUT_FLAG_GFXCLK,
1633                         gfx_clock, &dividers),
1634                         "Failed to get GFX Clock settings from VBIOS!",
1635                         return -EINVAL);
1636
1637         /* Feedback Multiplier: bit 0:8 int, bit 15:12 post_div, bit 31:16 frac */
1638         current_gfxclk_level->FbMult =
1639                         cpu_to_le32(dividers.ulPll_fb_mult);
1640         /* Spread FB Multiplier bit: bit 0:8 int, bit 31:16 frac */
1641         current_gfxclk_level->SsOn = dividers.ucPll_ss_enable;
1642         current_gfxclk_level->SsFbMult =
1643                         cpu_to_le32(dividers.ulPll_ss_fbsmult);
1644         current_gfxclk_level->SsSlewFrac =
1645                         cpu_to_le16(dividers.usPll_ss_slew_frac);
1646         current_gfxclk_level->Did = (uint8_t)(dividers.ulDid);
1647
1648         *acg_freq = gfx_clock / 100; /* 100 Khz to Mhz conversion */
1649
1650         return 0;
1651 }
1652
1653 /**
1654  * Populates single SMC SOCCLK structure using the provided clock.
1655  *
1656  * @hwmgr:     the address of the hardware manager.
1657  * @soc_clock: the SOC clock to use to populate the structure.
1658  * @current_soc_did:   DFS divider to pass back to caller
1659  * @current_vol_index: index of current VDD to pass back to caller
1660  * return:      0 on success
1661  */
1662 static int vega10_populate_single_soc_level(struct pp_hwmgr *hwmgr,
1663                 uint32_t soc_clock, uint8_t *current_soc_did,
1664                 uint8_t *current_vol_index)
1665 {
1666         struct vega10_hwmgr *data = hwmgr->backend;
1667         struct phm_ppt_v2_information *table_info =
1668                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
1669         struct phm_ppt_v1_clock_voltage_dependency_table *dep_on_soc;
1670         struct pp_atomfwctrl_clock_dividers_soc15 dividers;
1671         uint32_t i;
1672
1673         if (hwmgr->od_enabled) {
1674                 dep_on_soc = (struct phm_ppt_v1_clock_voltage_dependency_table *)
1675                                                 &data->odn_dpm_table.vdd_dep_on_socclk;
1676                 for (i = 0; i < dep_on_soc->count; i++) {
1677                         if (dep_on_soc->entries[i].clk >= soc_clock)
1678                                 break;
1679                 }
1680         } else {
1681                 dep_on_soc = table_info->vdd_dep_on_socclk;
1682                 for (i = 0; i < dep_on_soc->count; i++) {
1683                         if (dep_on_soc->entries[i].clk == soc_clock)
1684                                 break;
1685                 }
1686         }
1687
1688         PP_ASSERT_WITH_CODE(dep_on_soc->count > i,
1689                         "Cannot find SOC_CLK in SOC_VDD-SOC_CLK Dependency Table",
1690                         return -EINVAL);
1691
1692         PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
1693                         COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
1694                         soc_clock, &dividers),
1695                         "Failed to get SOC Clock settings from VBIOS!",
1696                         return -EINVAL);
1697
1698         *current_soc_did = (uint8_t)dividers.ulDid;
1699         *current_vol_index = (uint8_t)(dep_on_soc->entries[i].vddInd);
1700         return 0;
1701 }
1702
1703 /**
1704  * Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
1705  *
1706  * @hwmgr:      the address of the hardware manager
1707  */
1708 static int vega10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
1709 {
1710         struct vega10_hwmgr *data = hwmgr->backend;
1711         struct phm_ppt_v2_information *table_info =
1712                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
1713         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1714         struct vega10_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table);
1715         int result = 0;
1716         uint32_t i, j;
1717
1718         for (i = 0; i < dpm_table->count; i++) {
1719                 result = vega10_populate_single_gfx_level(hwmgr,
1720                                 dpm_table->dpm_levels[i].value,
1721                                 &(pp_table->GfxclkLevel[i]),
1722                                 &(pp_table->AcgFreqTable[i]));
1723                 if (result)
1724                         return result;
1725         }
1726
1727         j = i - 1;
1728         while (i < NUM_GFXCLK_DPM_LEVELS) {
1729                 result = vega10_populate_single_gfx_level(hwmgr,
1730                                 dpm_table->dpm_levels[j].value,
1731                                 &(pp_table->GfxclkLevel[i]),
1732                                 &(pp_table->AcgFreqTable[i]));
1733                 if (result)
1734                         return result;
1735                 i++;
1736         }
1737
1738         pp_table->GfxclkSlewRate =
1739                         cpu_to_le16(table_info->us_gfxclk_slew_rate);
1740
1741         dpm_table = &(data->dpm_table.soc_table);
1742         for (i = 0; i < dpm_table->count; i++) {
1743                 result = vega10_populate_single_soc_level(hwmgr,
1744                                 dpm_table->dpm_levels[i].value,
1745                                 &(pp_table->SocclkDid[i]),
1746                                 &(pp_table->SocDpmVoltageIndex[i]));
1747                 if (result)
1748                         return result;
1749         }
1750
1751         j = i - 1;
1752         while (i < NUM_SOCCLK_DPM_LEVELS) {
1753                 result = vega10_populate_single_soc_level(hwmgr,
1754                                 dpm_table->dpm_levels[j].value,
1755                                 &(pp_table->SocclkDid[i]),
1756                                 &(pp_table->SocDpmVoltageIndex[i]));
1757                 if (result)
1758                         return result;
1759                 i++;
1760         }
1761
1762         return result;
1763 }
1764
1765 static void vega10_populate_vddc_soc_levels(struct pp_hwmgr *hwmgr)
1766 {
1767         struct vega10_hwmgr *data = hwmgr->backend;
1768         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1769         struct phm_ppt_v2_information *table_info = hwmgr->pptable;
1770         struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
1771
1772         uint8_t soc_vid = 0;
1773         uint32_t i, max_vddc_level;
1774
1775         if (hwmgr->od_enabled)
1776                 vddc_lookup_table = (struct phm_ppt_v1_voltage_lookup_table *)&data->odn_dpm_table.vddc_lookup_table;
1777         else
1778                 vddc_lookup_table = table_info->vddc_lookup_table;
1779
1780         max_vddc_level = vddc_lookup_table->count;
1781         for (i = 0; i < max_vddc_level; i++) {
1782                 soc_vid = (uint8_t)convert_to_vid(vddc_lookup_table->entries[i].us_vdd);
1783                 pp_table->SocVid[i] = soc_vid;
1784         }
1785         while (i < MAX_REGULAR_DPM_NUMBER) {
1786                 pp_table->SocVid[i] = soc_vid;
1787                 i++;
1788         }
1789 }
1790
1791 /*
1792  * Populates single SMC GFXCLK structure using the provided clock.
1793  *
1794  * @hwmgr:     the address of the hardware manager.
1795  * @mem_clock: the memory clock to use to populate the structure.
1796  * return:     0 on success..
1797  */
1798 static int vega10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
1799                 uint32_t mem_clock, uint8_t *current_mem_vid,
1800                 PllSetting_t *current_memclk_level, uint8_t *current_mem_soc_vind)
1801 {
1802         struct vega10_hwmgr *data = hwmgr->backend;
1803         struct phm_ppt_v2_information *table_info =
1804                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
1805         struct phm_ppt_v1_clock_voltage_dependency_table *dep_on_mclk;
1806         struct pp_atomfwctrl_clock_dividers_soc15 dividers;
1807         uint32_t mem_max_clock =
1808                         hwmgr->platform_descriptor.overdriveLimit.memoryClock;
1809         uint32_t i = 0;
1810
1811         if (hwmgr->od_enabled)
1812                 dep_on_mclk = (struct phm_ppt_v1_clock_voltage_dependency_table *)
1813                                         &data->odn_dpm_table.vdd_dep_on_mclk;
1814         else
1815                 dep_on_mclk = table_info->vdd_dep_on_mclk;
1816
1817         PP_ASSERT_WITH_CODE(dep_on_mclk,
1818                         "Invalid SOC_VDD-UCLK Dependency Table!",
1819                         return -EINVAL);
1820
1821         if (data->need_update_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
1822                 mem_clock = mem_clock > mem_max_clock ? mem_max_clock : mem_clock;
1823         } else {
1824                 for (i = 0; i < dep_on_mclk->count; i++) {
1825                         if (dep_on_mclk->entries[i].clk == mem_clock)
1826                                 break;
1827                 }
1828                 PP_ASSERT_WITH_CODE(dep_on_mclk->count > i,
1829                                 "Cannot find UCLK in SOC_VDD-UCLK Dependency Table!",
1830                                 return -EINVAL);
1831         }
1832
1833         PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(
1834                         hwmgr, COMPUTE_GPUCLK_INPUT_FLAG_UCLK, mem_clock, &dividers),
1835                         "Failed to get UCLK settings from VBIOS!",
1836                         return -1);
1837
1838         *current_mem_vid =
1839                         (uint8_t)(convert_to_vid(dep_on_mclk->entries[i].mvdd));
1840         *current_mem_soc_vind =
1841                         (uint8_t)(dep_on_mclk->entries[i].vddInd);
1842         current_memclk_level->FbMult = cpu_to_le32(dividers.ulPll_fb_mult);
1843         current_memclk_level->Did = (uint8_t)(dividers.ulDid);
1844
1845         PP_ASSERT_WITH_CODE(current_memclk_level->Did >= 1,
1846                         "Invalid Divider ID!",
1847                         return -EINVAL);
1848
1849         return 0;
1850 }
1851
1852 /**
1853  * Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states.
1854  *
1855  * @hwmgr:  the address of the hardware manager.
1856  * return:   PP_Result_OK on success.
1857  */
1858 static int vega10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1859 {
1860         struct vega10_hwmgr *data = hwmgr->backend;
1861         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1862         struct vega10_single_dpm_table *dpm_table =
1863                         &(data->dpm_table.mem_table);
1864         int result = 0;
1865         uint32_t i, j;
1866
1867         for (i = 0; i < dpm_table->count; i++) {
1868                 result = vega10_populate_single_memory_level(hwmgr,
1869                                 dpm_table->dpm_levels[i].value,
1870                                 &(pp_table->MemVid[i]),
1871                                 &(pp_table->UclkLevel[i]),
1872                                 &(pp_table->MemSocVoltageIndex[i]));
1873                 if (result)
1874                         return result;
1875         }
1876
1877         j = i - 1;
1878         while (i < NUM_UCLK_DPM_LEVELS) {
1879                 result = vega10_populate_single_memory_level(hwmgr,
1880                                 dpm_table->dpm_levels[j].value,
1881                                 &(pp_table->MemVid[i]),
1882                                 &(pp_table->UclkLevel[i]),
1883                                 &(pp_table->MemSocVoltageIndex[i]));
1884                 if (result)
1885                         return result;
1886                 i++;
1887         }
1888
1889         pp_table->NumMemoryChannels = (uint16_t)(data->mem_channels);
1890         pp_table->MemoryChannelWidth =
1891                         (uint16_t)(HBM_MEMORY_CHANNEL_WIDTH *
1892                                         channel_number[data->mem_channels]);
1893
1894         pp_table->LowestUclkReservedForUlv =
1895                         (uint8_t)(data->lowest_uclk_reserved_for_ulv);
1896
1897         return result;
1898 }
1899
1900 static int vega10_populate_single_display_type(struct pp_hwmgr *hwmgr,
1901                 DSPCLK_e disp_clock)
1902 {
1903         struct vega10_hwmgr *data = hwmgr->backend;
1904         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1905         struct phm_ppt_v2_information *table_info =
1906                         (struct phm_ppt_v2_information *)
1907                         (hwmgr->pptable);
1908         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table;
1909         uint32_t i;
1910         uint16_t clk = 0, vddc = 0;
1911         uint8_t vid = 0;
1912
1913         switch (disp_clock) {
1914         case DSPCLK_DCEFCLK:
1915                 dep_table = table_info->vdd_dep_on_dcefclk;
1916                 break;
1917         case DSPCLK_DISPCLK:
1918                 dep_table = table_info->vdd_dep_on_dispclk;
1919                 break;
1920         case DSPCLK_PIXCLK:
1921                 dep_table = table_info->vdd_dep_on_pixclk;
1922                 break;
1923         case DSPCLK_PHYCLK:
1924                 dep_table = table_info->vdd_dep_on_phyclk;
1925                 break;
1926         default:
1927                 return -1;
1928         }
1929
1930         PP_ASSERT_WITH_CODE(dep_table->count <= NUM_DSPCLK_LEVELS,
1931                         "Number Of Entries Exceeded maximum!",
1932                         return -1);
1933
1934         for (i = 0; i < dep_table->count; i++) {
1935                 clk = (uint16_t)(dep_table->entries[i].clk / 100);
1936                 vddc = table_info->vddc_lookup_table->
1937                                 entries[dep_table->entries[i].vddInd].us_vdd;
1938                 vid = (uint8_t)convert_to_vid(vddc);
1939                 pp_table->DisplayClockTable[disp_clock][i].Freq =
1940                                 cpu_to_le16(clk);
1941                 pp_table->DisplayClockTable[disp_clock][i].Vid =
1942                                 cpu_to_le16(vid);
1943         }
1944
1945         while (i < NUM_DSPCLK_LEVELS) {
1946                 pp_table->DisplayClockTable[disp_clock][i].Freq =
1947                                 cpu_to_le16(clk);
1948                 pp_table->DisplayClockTable[disp_clock][i].Vid =
1949                                 cpu_to_le16(vid);
1950                 i++;
1951         }
1952
1953         return 0;
1954 }
1955
1956 static int vega10_populate_all_display_clock_levels(struct pp_hwmgr *hwmgr)
1957 {
1958         uint32_t i;
1959
1960         for (i = 0; i < DSPCLK_COUNT; i++) {
1961                 PP_ASSERT_WITH_CODE(!vega10_populate_single_display_type(hwmgr, i),
1962                                 "Failed to populate Clock in DisplayClockTable!",
1963                                 return -1);
1964         }
1965
1966         return 0;
1967 }
1968
1969 static int vega10_populate_single_eclock_level(struct pp_hwmgr *hwmgr,
1970                 uint32_t eclock, uint8_t *current_eclk_did,
1971                 uint8_t *current_soc_vol)
1972 {
1973         struct phm_ppt_v2_information *table_info =
1974                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
1975         struct phm_ppt_v1_mm_clock_voltage_dependency_table *dep_table =
1976                         table_info->mm_dep_table;
1977         struct pp_atomfwctrl_clock_dividers_soc15 dividers;
1978         uint32_t i;
1979
1980         PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
1981                         COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
1982                         eclock, &dividers),
1983                         "Failed to get ECLK clock settings from VBIOS!",
1984                         return -1);
1985
1986         *current_eclk_did = (uint8_t)dividers.ulDid;
1987
1988         for (i = 0; i < dep_table->count; i++) {
1989                 if (dep_table->entries[i].eclk == eclock)
1990                         *current_soc_vol = dep_table->entries[i].vddcInd;
1991         }
1992
1993         return 0;
1994 }
1995
1996 static int vega10_populate_smc_vce_levels(struct pp_hwmgr *hwmgr)
1997 {
1998         struct vega10_hwmgr *data = hwmgr->backend;
1999         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
2000         struct vega10_single_dpm_table *dpm_table = &(data->dpm_table.eclk_table);
2001         int result = -EINVAL;
2002         uint32_t i, j;
2003
2004         for (i = 0; i < dpm_table->count; i++) {
2005                 result = vega10_populate_single_eclock_level(hwmgr,
2006                                 dpm_table->dpm_levels[i].value,
2007                                 &(pp_table->EclkDid[i]),
2008                                 &(pp_table->VceDpmVoltageIndex[i]));
2009                 if (result)
2010                         return result;
2011         }
2012
2013         j = i - 1;
2014         while (i < NUM_VCE_DPM_LEVELS) {
2015                 result = vega10_populate_single_eclock_level(hwmgr,
2016                                 dpm_table->dpm_levels[j].value,
2017                                 &(pp_table->EclkDid[i]),
2018                                 &(pp_table->VceDpmVoltageIndex[i]));
2019                 if (result)
2020                         return result;
2021                 i++;
2022         }
2023
2024         return result;
2025 }
2026
2027 static int vega10_populate_single_vclock_level(struct pp_hwmgr *hwmgr,
2028                 uint32_t vclock, uint8_t *current_vclk_did)
2029 {
2030         struct pp_atomfwctrl_clock_dividers_soc15 dividers;
2031
2032         PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
2033                         COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2034                         vclock, &dividers),
2035                         "Failed to get VCLK clock settings from VBIOS!",
2036                         return -EINVAL);
2037
2038         *current_vclk_did = (uint8_t)dividers.ulDid;
2039
2040         return 0;
2041 }
2042
2043 static int vega10_populate_single_dclock_level(struct pp_hwmgr *hwmgr,
2044                 uint32_t dclock, uint8_t *current_dclk_did)
2045 {
2046         struct pp_atomfwctrl_clock_dividers_soc15 dividers;
2047
2048         PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
2049                         COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2050                         dclock, &dividers),
2051                         "Failed to get DCLK clock settings from VBIOS!",
2052                         return -EINVAL);
2053
2054         *current_dclk_did = (uint8_t)dividers.ulDid;
2055
2056         return 0;
2057 }
2058
2059 static int vega10_populate_smc_uvd_levels(struct pp_hwmgr *hwmgr)
2060 {
2061         struct vega10_hwmgr *data = hwmgr->backend;
2062         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
2063         struct vega10_single_dpm_table *vclk_dpm_table =
2064                         &(data->dpm_table.vclk_table);
2065         struct vega10_single_dpm_table *dclk_dpm_table =
2066                         &(data->dpm_table.dclk_table);
2067         struct phm_ppt_v2_information *table_info =
2068                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
2069         struct phm_ppt_v1_mm_clock_voltage_dependency_table *dep_table =
2070                         table_info->mm_dep_table;
2071         int result = -EINVAL;
2072         uint32_t i, j;
2073
2074         for (i = 0; i < vclk_dpm_table->count; i++) {
2075                 result = vega10_populate_single_vclock_level(hwmgr,
2076                                 vclk_dpm_table->dpm_levels[i].value,
2077                                 &(pp_table->VclkDid[i]));
2078                 if (result)
2079                         return result;
2080         }
2081
2082         j = i - 1;
2083         while (i < NUM_UVD_DPM_LEVELS) {
2084                 result = vega10_populate_single_vclock_level(hwmgr,
2085                                 vclk_dpm_table->dpm_levels[j].value,
2086                                 &(pp_table->VclkDid[i]));
2087                 if (result)
2088                         return result;
2089                 i++;
2090         }
2091
2092         for (i = 0; i < dclk_dpm_table->count; i++) {
2093                 result = vega10_populate_single_dclock_level(hwmgr,
2094                                 dclk_dpm_table->dpm_levels[i].value,
2095                                 &(pp_table->DclkDid[i]));
2096                 if (result)
2097                         return result;
2098         }
2099
2100         j = i - 1;
2101         while (i < NUM_UVD_DPM_LEVELS) {
2102                 result = vega10_populate_single_dclock_level(hwmgr,
2103                                 dclk_dpm_table->dpm_levels[j].value,
2104                                 &(pp_table->DclkDid[i]));
2105                 if (result)
2106                         return result;
2107                 i++;
2108         }
2109
2110         for (i = 0; i < dep_table->count; i++) {
2111                 if (dep_table->entries[i].vclk ==
2112                                 vclk_dpm_table->dpm_levels[i].value &&
2113                         dep_table->entries[i].dclk ==
2114                                 dclk_dpm_table->dpm_levels[i].value)
2115                         pp_table->UvdDpmVoltageIndex[i] =
2116                                         dep_table->entries[i].vddcInd;
2117                 else
2118                         return -1;
2119         }
2120
2121         j = i - 1;
2122         while (i < NUM_UVD_DPM_LEVELS) {
2123                 pp_table->UvdDpmVoltageIndex[i] = dep_table->entries[j].vddcInd;
2124                 i++;
2125         }
2126
2127         return 0;
2128 }
2129
2130 static int vega10_populate_clock_stretcher_table(struct pp_hwmgr *hwmgr)
2131 {
2132         struct vega10_hwmgr *data = hwmgr->backend;
2133         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
2134         struct phm_ppt_v2_information *table_info =
2135                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
2136         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
2137                         table_info->vdd_dep_on_sclk;
2138         uint32_t i;
2139
2140         for (i = 0; i < dep_table->count; i++) {
2141                 pp_table->CksEnable[i] = dep_table->entries[i].cks_enable;
2142                 pp_table->CksVidOffset[i] = (uint8_t)(dep_table->entries[i].cks_voffset
2143                                 * VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
2144         }
2145
2146         return 0;
2147 }
2148
2149 static int vega10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
2150 {
2151         struct vega10_hwmgr *data = hwmgr->backend;
2152         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
2153         struct phm_ppt_v2_information *table_info =
2154                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
2155         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
2156                         table_info->vdd_dep_on_sclk;
2157         struct pp_atomfwctrl_avfs_parameters avfs_params = {0};
2158         int result = 0;
2159         uint32_t i;
2160
2161         pp_table->MinVoltageVid = (uint8_t)0xff;
2162         pp_table->MaxVoltageVid = (uint8_t)0;
2163
2164         if (data->smu_features[GNLD_AVFS].supported) {
2165                 result = pp_atomfwctrl_get_avfs_information(hwmgr, &avfs_params);
2166                 if (!result) {
2167                         pp_table->MinVoltageVid = (uint8_t)
2168                                         convert_to_vid((uint16_t)(avfs_params.ulMinVddc));
2169                         pp_table->MaxVoltageVid = (uint8_t)
2170                                         convert_to_vid((uint16_t)(avfs_params.ulMaxVddc));
2171
2172                         pp_table->AConstant[0] = cpu_to_le32(avfs_params.ulMeanNsigmaAcontant0);
2173                         pp_table->AConstant[1] = cpu_to_le32(avfs_params.ulMeanNsigmaAcontant1);
2174                         pp_table->AConstant[2] = cpu_to_le32(avfs_params.ulMeanNsigmaAcontant2);
2175                         pp_table->DC_tol_sigma = cpu_to_le16(avfs_params.usMeanNsigmaDcTolSigma);
2176                         pp_table->Platform_mean = cpu_to_le16(avfs_params.usMeanNsigmaPlatformMean);
2177                         pp_table->Platform_sigma = cpu_to_le16(avfs_params.usMeanNsigmaDcTolSigma);
2178                         pp_table->PSM_Age_CompFactor = cpu_to_le16(avfs_params.usPsmAgeComfactor);
2179
2180                         pp_table->BtcGbVdroopTableCksOff.a0 =
2181                                         cpu_to_le32(avfs_params.ulGbVdroopTableCksoffA0);
2182                         pp_table->BtcGbVdroopTableCksOff.a0_shift = 20;
2183                         pp_table->BtcGbVdroopTableCksOff.a1 =
2184                                         cpu_to_le32(avfs_params.ulGbVdroopTableCksoffA1);
2185                         pp_table->BtcGbVdroopTableCksOff.a1_shift = 20;
2186                         pp_table->BtcGbVdroopTableCksOff.a2 =
2187                                         cpu_to_le32(avfs_params.ulGbVdroopTableCksoffA2);
2188                         pp_table->BtcGbVdroopTableCksOff.a2_shift = 20;
2189
2190                         pp_table->OverrideBtcGbCksOn = avfs_params.ucEnableGbVdroopTableCkson;
2191                         pp_table->BtcGbVdroopTableCksOn.a0 =
2192                                         cpu_to_le32(avfs_params.ulGbVdroopTableCksonA0);
2193                         pp_table->BtcGbVdroopTableCksOn.a0_shift = 20;
2194                         pp_table->BtcGbVdroopTableCksOn.a1 =
2195                                         cpu_to_le32(avfs_params.ulGbVdroopTableCksonA1);
2196                         pp_table->BtcGbVdroopTableCksOn.a1_shift = 20;
2197                         pp_table->BtcGbVdroopTableCksOn.a2 =
2198                                         cpu_to_le32(avfs_params.ulGbVdroopTableCksonA2);
2199                         pp_table->BtcGbVdroopTableCksOn.a2_shift = 20;
2200
2201                         pp_table->AvfsGbCksOn.m1 =
2202                                         cpu_to_le32(avfs_params.ulGbFuseTableCksonM1);
2203                         pp_table->AvfsGbCksOn.m2 =
2204                                         cpu_to_le32(avfs_params.ulGbFuseTableCksonM2);
2205                         pp_table->AvfsGbCksOn.b =
2206                                         cpu_to_le32(avfs_params.ulGbFuseTableCksonB);
2207                         pp_table->AvfsGbCksOn.m1_shift = 24;
2208                         pp_table->AvfsGbCksOn.m2_shift = 12;
2209                         pp_table->AvfsGbCksOn.b_shift = 0;
2210
2211                         pp_table->OverrideAvfsGbCksOn =
2212                                         avfs_params.ucEnableGbFuseTableCkson;
2213                         pp_table->AvfsGbCksOff.m1 =
2214                                         cpu_to_le32(avfs_params.ulGbFuseTableCksoffM1);
2215                         pp_table->AvfsGbCksOff.m2 =
2216                                         cpu_to_le32(avfs_params.ulGbFuseTableCksoffM2);
2217                         pp_table->AvfsGbCksOff.b =
2218                                         cpu_to_le32(avfs_params.ulGbFuseTableCksoffB);
2219                         pp_table->AvfsGbCksOff.m1_shift = 24;
2220                         pp_table->AvfsGbCksOff.m2_shift = 12;
2221                         pp_table->AvfsGbCksOff.b_shift = 0;
2222
2223                         for (i = 0; i < dep_table->count; i++)
2224                                 pp_table->StaticVoltageOffsetVid[i] =
2225                                                 convert_to_vid((uint8_t)(dep_table->entries[i].sclk_offset));
2226
2227                         if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2228                                         data->disp_clk_quad_eqn_a) &&
2229                                 (PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2230                                         data->disp_clk_quad_eqn_b)) {
2231                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m1 =
2232                                                 (int32_t)data->disp_clk_quad_eqn_a;
2233                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m2 =
2234                                                 (int32_t)data->disp_clk_quad_eqn_b;
2235                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].b =
2236                                                 (int32_t)data->disp_clk_quad_eqn_c;
2237                         } else {
2238                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m1 =
2239                                                 (int32_t)avfs_params.ulDispclk2GfxclkM1;
2240                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m2 =
2241                                                 (int32_t)avfs_params.ulDispclk2GfxclkM2;
2242                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].b =
2243                                                 (int32_t)avfs_params.ulDispclk2GfxclkB;
2244                         }
2245
2246                         pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m1_shift = 24;
2247                         pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m2_shift = 12;
2248                         pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].b_shift = 12;
2249
2250                         if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2251                                         data->dcef_clk_quad_eqn_a) &&
2252                                 (PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2253                                         data->dcef_clk_quad_eqn_b)) {
2254                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m1 =
2255                                                 (int32_t)data->dcef_clk_quad_eqn_a;
2256                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m2 =
2257                                                 (int32_t)data->dcef_clk_quad_eqn_b;
2258                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].b =
2259                                                 (int32_t)data->dcef_clk_quad_eqn_c;
2260                         } else {
2261                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m1 =
2262                                                 (int32_t)avfs_params.ulDcefclk2GfxclkM1;
2263                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m2 =
2264                                                 (int32_t)avfs_params.ulDcefclk2GfxclkM2;
2265                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].b =
2266                                                 (int32_t)avfs_params.ulDcefclk2GfxclkB;
2267                         }
2268
2269                         pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m1_shift = 24;
2270                         pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m2_shift = 12;
2271                         pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].b_shift = 12;
2272
2273                         if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2274                                         data->pixel_clk_quad_eqn_a) &&
2275                                 (PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2276                                         data->pixel_clk_quad_eqn_b)) {
2277                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m1 =
2278                                                 (int32_t)data->pixel_clk_quad_eqn_a;
2279                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m2 =
2280                                                 (int32_t)data->pixel_clk_quad_eqn_b;
2281                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].b =
2282                                                 (int32_t)data->pixel_clk_quad_eqn_c;
2283                         } else {
2284                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m1 =
2285                                                 (int32_t)avfs_params.ulPixelclk2GfxclkM1;
2286                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m2 =
2287                                                 (int32_t)avfs_params.ulPixelclk2GfxclkM2;
2288                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].b =
2289                                                 (int32_t)avfs_params.ulPixelclk2GfxclkB;
2290                         }
2291
2292                         pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m1_shift = 24;
2293                         pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m2_shift = 12;
2294                         pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].b_shift = 12;
2295                         if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2296                                         data->phy_clk_quad_eqn_a) &&
2297                                 (PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2298                                         data->phy_clk_quad_eqn_b)) {
2299                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m1 =
2300                                                 (int32_t)data->phy_clk_quad_eqn_a;
2301                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m2 =
2302                                                 (int32_t)data->phy_clk_quad_eqn_b;
2303                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].b =
2304                                                 (int32_t)data->phy_clk_quad_eqn_c;
2305                         } else {
2306                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m1 =
2307                                                 (int32_t)avfs_params.ulPhyclk2GfxclkM1;
2308                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m2 =
2309                                                 (int32_t)avfs_params.ulPhyclk2GfxclkM2;
2310                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].b =
2311                                                 (int32_t)avfs_params.ulPhyclk2GfxclkB;
2312                         }
2313
2314                         pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m1_shift = 24;
2315                         pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m2_shift = 12;
2316                         pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].b_shift = 12;
2317
2318                         pp_table->AcgBtcGbVdroopTable.a0       = avfs_params.ulAcgGbVdroopTableA0;
2319                         pp_table->AcgBtcGbVdroopTable.a0_shift = 20;
2320                         pp_table->AcgBtcGbVdroopTable.a1       = avfs_params.ulAcgGbVdroopTableA1;
2321                         pp_table->AcgBtcGbVdroopTable.a1_shift = 20;
2322                         pp_table->AcgBtcGbVdroopTable.a2       = avfs_params.ulAcgGbVdroopTableA2;
2323                         pp_table->AcgBtcGbVdroopTable.a2_shift = 20;
2324
2325                         pp_table->AcgAvfsGb.m1                   = avfs_params.ulAcgGbFuseTableM1;
2326                         pp_table->AcgAvfsGb.m2                   = avfs_params.ulAcgGbFuseTableM2;
2327                         pp_table->AcgAvfsGb.b                    = avfs_params.ulAcgGbFuseTableB;
2328                         pp_table->AcgAvfsGb.m1_shift             = 24;
2329                         pp_table->AcgAvfsGb.m2_shift             = 12;
2330                         pp_table->AcgAvfsGb.b_shift              = 0;
2331
2332                 } else {
2333                         data->smu_features[GNLD_AVFS].supported = false;
2334                 }
2335         }
2336
2337         return 0;
2338 }
2339
2340 static int vega10_acg_enable(struct pp_hwmgr *hwmgr)
2341 {
2342         struct vega10_hwmgr *data = hwmgr->backend;
2343         uint32_t agc_btc_response;
2344
2345         if (data->smu_features[GNLD_ACG].supported) {
2346                 if (0 == vega10_enable_smc_features(hwmgr, true,
2347                                         data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_bitmap))
2348                         data->smu_features[GNLD_DPM_PREFETCHER].enabled = true;
2349
2350                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_InitializeAcg, NULL);
2351
2352                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgBtc, &agc_btc_response);
2353
2354                 if (1 == agc_btc_response) {
2355                         if (1 == data->acg_loop_state)
2356                                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgInClosedLoop, NULL);
2357                         else if (2 == data->acg_loop_state)
2358                                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgInOpenLoop, NULL);
2359                         if (0 == vega10_enable_smc_features(hwmgr, true,
2360                                 data->smu_features[GNLD_ACG].smu_feature_bitmap))
2361                                         data->smu_features[GNLD_ACG].enabled = true;
2362                 } else {
2363                         pr_info("[ACG_Enable] ACG BTC Returned Failed Status!\n");
2364                         data->smu_features[GNLD_ACG].enabled = false;
2365                 }
2366         }
2367
2368         return 0;
2369 }
2370
2371 static int vega10_acg_disable(struct pp_hwmgr *hwmgr)
2372 {
2373         struct vega10_hwmgr *data = hwmgr->backend;
2374
2375         if (data->smu_features[GNLD_ACG].supported &&
2376             data->smu_features[GNLD_ACG].enabled)
2377                 if (!vega10_enable_smc_features(hwmgr, false,
2378                         data->smu_features[GNLD_ACG].smu_feature_bitmap))
2379                         data->smu_features[GNLD_ACG].enabled = false;
2380
2381         return 0;
2382 }
2383
2384 static int vega10_populate_gpio_parameters(struct pp_hwmgr *hwmgr)
2385 {
2386         struct vega10_hwmgr *data = hwmgr->backend;
2387         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
2388         struct pp_atomfwctrl_gpio_parameters gpio_params = {0};
2389         int result;
2390
2391         result = pp_atomfwctrl_get_gpio_information(hwmgr, &gpio_params);
2392         if (!result) {
2393                 if (PP_CAP(PHM_PlatformCaps_RegulatorHot) &&
2394                     data->registry_data.regulator_hot_gpio_support) {
2395                         pp_table->VR0HotGpio = gpio_params.ucVR0HotGpio;
2396                         pp_table->VR0HotPolarity = gpio_params.ucVR0HotPolarity;
2397                         pp_table->VR1HotGpio = gpio_params.ucVR1HotGpio;
2398                         pp_table->VR1HotPolarity = gpio_params.ucVR1HotPolarity;
2399                 } else {
2400                         pp_table->VR0HotGpio = 0;
2401                         pp_table->VR0HotPolarity = 0;
2402                         pp_table->VR1HotGpio = 0;
2403                         pp_table->VR1HotPolarity = 0;
2404                 }
2405
2406                 if (PP_CAP(PHM_PlatformCaps_AutomaticDCTransition) &&
2407                     data->registry_data.ac_dc_switch_gpio_support) {
2408                         pp_table->AcDcGpio = gpio_params.ucAcDcGpio;
2409                         pp_table->AcDcPolarity = gpio_params.ucAcDcPolarity;
2410                 } else {
2411                         pp_table->AcDcGpio = 0;
2412                         pp_table->AcDcPolarity = 0;
2413                 }
2414         }
2415
2416         return result;
2417 }
2418
2419 static int vega10_avfs_enable(struct pp_hwmgr *hwmgr, bool enable)
2420 {
2421         struct vega10_hwmgr *data = hwmgr->backend;
2422
2423         if (data->smu_features[GNLD_AVFS].supported) {
2424                 /* Already enabled or disabled */
2425                 if (!(enable ^ data->smu_features[GNLD_AVFS].enabled))
2426                         return 0;
2427
2428                 if (enable) {
2429                         PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2430                                         true,
2431                                         data->smu_features[GNLD_AVFS].smu_feature_bitmap),
2432                                         "[avfs_control] Attempt to Enable AVFS feature Failed!",
2433                                         return -1);
2434                         data->smu_features[GNLD_AVFS].enabled = true;
2435                 } else {
2436                         PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2437                                         false,
2438                                         data->smu_features[GNLD_AVFS].smu_feature_bitmap),
2439                                         "[avfs_control] Attempt to Disable AVFS feature Failed!",
2440                                         return -1);
2441                         data->smu_features[GNLD_AVFS].enabled = false;
2442                 }
2443         }
2444
2445         return 0;
2446 }
2447
2448 static int vega10_update_avfs(struct pp_hwmgr *hwmgr)
2449 {
2450         struct vega10_hwmgr *data = hwmgr->backend;
2451
2452         if (data->need_update_dpm_table & DPMTABLE_OD_UPDATE_VDDC) {
2453                 vega10_avfs_enable(hwmgr, false);
2454         } else if (data->need_update_dpm_table) {
2455                 vega10_avfs_enable(hwmgr, false);
2456                 vega10_avfs_enable(hwmgr, true);
2457         } else {
2458                 vega10_avfs_enable(hwmgr, true);
2459         }
2460
2461         return 0;
2462 }
2463
2464 static int vega10_populate_and_upload_avfs_fuse_override(struct pp_hwmgr *hwmgr)
2465 {
2466         int result = 0;
2467
2468         uint64_t serial_number = 0;
2469         uint32_t top32, bottom32;
2470         struct phm_fuses_default fuse;
2471
2472         struct vega10_hwmgr *data = hwmgr->backend;
2473         AvfsFuseOverride_t *avfs_fuse_table = &(data->smc_state_table.avfs_fuse_override_table);
2474
2475         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32, &top32);
2476
2477         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32, &bottom32);
2478
2479         serial_number = ((uint64_t)bottom32 << 32) | top32;
2480
2481         if (pp_override_get_default_fuse_value(serial_number, &fuse) == 0) {
2482                 avfs_fuse_table->VFT0_b  = fuse.VFT0_b;
2483                 avfs_fuse_table->VFT0_m1 = fuse.VFT0_m1;
2484                 avfs_fuse_table->VFT0_m2 = fuse.VFT0_m2;
2485                 avfs_fuse_table->VFT1_b  = fuse.VFT1_b;
2486                 avfs_fuse_table->VFT1_m1 = fuse.VFT1_m1;
2487                 avfs_fuse_table->VFT1_m2 = fuse.VFT1_m2;
2488                 avfs_fuse_table->VFT2_b  = fuse.VFT2_b;
2489                 avfs_fuse_table->VFT2_m1 = fuse.VFT2_m1;
2490                 avfs_fuse_table->VFT2_m2 = fuse.VFT2_m2;
2491                 result = smum_smc_table_manager(hwmgr,  (uint8_t *)avfs_fuse_table,
2492                                                 AVFSFUSETABLE, false);
2493                 PP_ASSERT_WITH_CODE(!result,
2494                         "Failed to upload FuseOVerride!",
2495                         );
2496         }
2497
2498         return result;
2499 }
2500
2501 static void vega10_check_dpm_table_updated(struct pp_hwmgr *hwmgr)
2502 {
2503         struct vega10_hwmgr *data = hwmgr->backend;
2504         struct vega10_odn_dpm_table *odn_table = &(data->odn_dpm_table);
2505         struct phm_ppt_v2_information *table_info = hwmgr->pptable;
2506         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table;
2507         struct phm_ppt_v1_clock_voltage_dependency_table *odn_dep_table;
2508         uint32_t i;
2509
2510         dep_table = table_info->vdd_dep_on_mclk;
2511         odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dep_on_mclk);
2512
2513         for (i = 0; i < dep_table->count; i++) {
2514                 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) {
2515                         data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_MCLK;
2516                         return;
2517                 }
2518         }
2519
2520         dep_table = table_info->vdd_dep_on_sclk;
2521         odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dep_on_sclk);
2522         for (i = 0; i < dep_table->count; i++) {
2523                 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) {
2524                         data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_SCLK;
2525                         return;
2526                 }
2527         }
2528 }
2529
2530 /**
2531  * Initializes the SMC table and uploads it
2532  *
2533  * @hwmgr:  the address of the powerplay hardware manager.
2534  * return:  always 0
2535  */
2536 static int vega10_init_smc_table(struct pp_hwmgr *hwmgr)
2537 {
2538         int result;
2539         struct vega10_hwmgr *data = hwmgr->backend;
2540         struct phm_ppt_v2_information *table_info =
2541                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
2542         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
2543         struct pp_atomfwctrl_voltage_table voltage_table;
2544         struct pp_atomfwctrl_bios_boot_up_values boot_up_values;
2545         struct vega10_odn_dpm_table *odn_table = &(data->odn_dpm_table);
2546
2547         result = vega10_setup_default_dpm_tables(hwmgr);
2548         PP_ASSERT_WITH_CODE(!result,
2549                         "Failed to setup default DPM tables!",
2550                         return result);
2551
2552         if (!hwmgr->not_vf)
2553                 return 0;
2554
2555         /* initialize ODN table */
2556         if (hwmgr->od_enabled) {
2557                 if (odn_table->max_vddc) {
2558                         data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK;
2559                         vega10_check_dpm_table_updated(hwmgr);
2560                 } else {
2561                         vega10_odn_initial_default_setting(hwmgr);
2562                 }
2563         }
2564
2565         pp_atomfwctrl_get_voltage_table_v4(hwmgr, VOLTAGE_TYPE_VDDC,
2566                         VOLTAGE_OBJ_SVID2,  &voltage_table);
2567         pp_table->MaxVidStep = voltage_table.max_vid_step;
2568
2569         pp_table->GfxDpmVoltageMode =
2570                         (uint8_t)(table_info->uc_gfx_dpm_voltage_mode);
2571         pp_table->SocDpmVoltageMode =
2572                         (uint8_t)(table_info->uc_soc_dpm_voltage_mode);
2573         pp_table->UclkDpmVoltageMode =
2574                         (uint8_t)(table_info->uc_uclk_dpm_voltage_mode);
2575         pp_table->UvdDpmVoltageMode =
2576                         (uint8_t)(table_info->uc_uvd_dpm_voltage_mode);
2577         pp_table->VceDpmVoltageMode =
2578                         (uint8_t)(table_info->uc_vce_dpm_voltage_mode);
2579         pp_table->Mp0DpmVoltageMode =
2580                         (uint8_t)(table_info->uc_mp0_dpm_voltage_mode);
2581
2582         pp_table->DisplayDpmVoltageMode =
2583                         (uint8_t)(table_info->uc_dcef_dpm_voltage_mode);
2584
2585         data->vddc_voltage_table.psi0_enable = voltage_table.psi0_enable;
2586         data->vddc_voltage_table.psi1_enable = voltage_table.psi1_enable;
2587
2588         if (data->registry_data.ulv_support &&
2589                         table_info->us_ulv_voltage_offset) {
2590                 result = vega10_populate_ulv_state(hwmgr);
2591                 PP_ASSERT_WITH_CODE(!result,
2592                                 "Failed to initialize ULV state!",
2593                                 return result);
2594         }
2595
2596         result = vega10_populate_smc_link_levels(hwmgr);
2597         PP_ASSERT_WITH_CODE(!result,
2598                         "Failed to initialize Link Level!",
2599                         return result);
2600
2601         result = vega10_override_pcie_parameters(hwmgr);
2602         PP_ASSERT_WITH_CODE(!result,
2603                         "Failed to override pcie parameters!",
2604                         return result);
2605
2606         result = vega10_populate_all_graphic_levels(hwmgr);
2607         PP_ASSERT_WITH_CODE(!result,
2608                         "Failed to initialize Graphics Level!",
2609                         return result);
2610
2611         result = vega10_populate_all_memory_levels(hwmgr);
2612         PP_ASSERT_WITH_CODE(!result,
2613                         "Failed to initialize Memory Level!",
2614                         return result);
2615
2616         vega10_populate_vddc_soc_levels(hwmgr);
2617
2618         result = vega10_populate_all_display_clock_levels(hwmgr);
2619         PP_ASSERT_WITH_CODE(!result,
2620                         "Failed to initialize Display Level!",
2621                         return result);
2622
2623         result = vega10_populate_smc_vce_levels(hwmgr);
2624         PP_ASSERT_WITH_CODE(!result,
2625                         "Failed to initialize VCE Level!",
2626                         return result);
2627
2628         result = vega10_populate_smc_uvd_levels(hwmgr);
2629         PP_ASSERT_WITH_CODE(!result,
2630                         "Failed to initialize UVD Level!",
2631                         return result);
2632
2633         if (data->registry_data.clock_stretcher_support) {
2634                 result = vega10_populate_clock_stretcher_table(hwmgr);
2635                 PP_ASSERT_WITH_CODE(!result,
2636                                 "Failed to populate Clock Stretcher Table!",
2637                                 return result);
2638         }
2639
2640         result = pp_atomfwctrl_get_vbios_bootup_values(hwmgr, &boot_up_values);
2641         if (!result) {
2642                 data->vbios_boot_state.vddc     = boot_up_values.usVddc;
2643                 data->vbios_boot_state.vddci    = boot_up_values.usVddci;
2644                 data->vbios_boot_state.mvddc    = boot_up_values.usMvddc;
2645                 data->vbios_boot_state.gfx_clock = boot_up_values.ulGfxClk;
2646                 data->vbios_boot_state.mem_clock = boot_up_values.ulUClk;
2647                 pp_atomfwctrl_get_clk_information_by_clkid(hwmgr,
2648                                 SMU9_SYSPLL0_SOCCLK_ID, 0, &boot_up_values.ulSocClk);
2649
2650                 pp_atomfwctrl_get_clk_information_by_clkid(hwmgr,
2651                                 SMU9_SYSPLL0_DCEFCLK_ID, 0, &boot_up_values.ulDCEFClk);
2652
2653                 data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk;
2654                 data->vbios_boot_state.dcef_clock = boot_up_values.ulDCEFClk;
2655                 if (0 != boot_up_values.usVddc) {
2656                         smum_send_msg_to_smc_with_parameter(hwmgr,
2657                                                 PPSMC_MSG_SetFloorSocVoltage,
2658                                                 (boot_up_values.usVddc * 4),
2659                                                 NULL);
2660                         data->vbios_boot_state.bsoc_vddc_lock = true;
2661                 } else {
2662                         data->vbios_boot_state.bsoc_vddc_lock = false;
2663                 }
2664                 smum_send_msg_to_smc_with_parameter(hwmgr,
2665                                 PPSMC_MSG_SetMinDeepSleepDcefclk,
2666                         (uint32_t)(data->vbios_boot_state.dcef_clock / 100),
2667                                 NULL);
2668         }
2669
2670         result = vega10_populate_avfs_parameters(hwmgr);
2671         PP_ASSERT_WITH_CODE(!result,
2672                         "Failed to initialize AVFS Parameters!",
2673                         return result);
2674
2675         result = vega10_populate_gpio_parameters(hwmgr);
2676         PP_ASSERT_WITH_CODE(!result,
2677                         "Failed to initialize GPIO Parameters!",
2678                         return result);
2679
2680         pp_table->GfxclkAverageAlpha = (uint8_t)
2681                         (data->gfxclk_average_alpha);
2682         pp_table->SocclkAverageAlpha = (uint8_t)
2683                         (data->socclk_average_alpha);
2684         pp_table->UclkAverageAlpha = (uint8_t)
2685                         (data->uclk_average_alpha);
2686         pp_table->GfxActivityAverageAlpha = (uint8_t)
2687                         (data->gfx_activity_average_alpha);
2688
2689         vega10_populate_and_upload_avfs_fuse_override(hwmgr);
2690
2691         result = smum_smc_table_manager(hwmgr, (uint8_t *)pp_table, PPTABLE, false);
2692
2693         PP_ASSERT_WITH_CODE(!result,
2694                         "Failed to upload PPtable!", return result);
2695
2696         result = vega10_avfs_enable(hwmgr, true);
2697         PP_ASSERT_WITH_CODE(!result, "Attempt to enable AVFS feature Failed!",
2698                                         return result);
2699         vega10_acg_enable(hwmgr);
2700
2701         return 0;
2702 }
2703
2704 static int vega10_enable_thermal_protection(struct pp_hwmgr *hwmgr)
2705 {
2706         struct vega10_hwmgr *data = hwmgr->backend;
2707
2708         if (data->smu_features[GNLD_THERMAL].supported) {
2709                 if (data->smu_features[GNLD_THERMAL].enabled)
2710                         pr_info("THERMAL Feature Already enabled!");
2711
2712                 PP_ASSERT_WITH_CODE(
2713                                 !vega10_enable_smc_features(hwmgr,
2714                                 true,
2715                                 data->smu_features[GNLD_THERMAL].smu_feature_bitmap),
2716                                 "Enable THERMAL Feature Failed!",
2717                                 return -1);
2718                 data->smu_features[GNLD_THERMAL].enabled = true;
2719         }
2720
2721         return 0;
2722 }
2723
2724 static int vega10_disable_thermal_protection(struct pp_hwmgr *hwmgr)
2725 {
2726         struct vega10_hwmgr *data = hwmgr->backend;
2727
2728         if (data->smu_features[GNLD_THERMAL].supported) {
2729                 if (!data->smu_features[GNLD_THERMAL].enabled)
2730                         pr_info("THERMAL Feature Already disabled!");
2731
2732                 PP_ASSERT_WITH_CODE(
2733                                 !vega10_enable_smc_features(hwmgr,
2734                                 false,
2735                                 data->smu_features[GNLD_THERMAL].smu_feature_bitmap),
2736                                 "disable THERMAL Feature Failed!",
2737                                 return -1);
2738                 data->smu_features[GNLD_THERMAL].enabled = false;
2739         }
2740
2741         return 0;
2742 }
2743
2744 static int vega10_enable_vrhot_feature(struct pp_hwmgr *hwmgr)
2745 {
2746         struct vega10_hwmgr *data = hwmgr->backend;
2747
2748         if (PP_CAP(PHM_PlatformCaps_RegulatorHot)) {
2749                 if (data->smu_features[GNLD_VR0HOT].supported) {
2750                         PP_ASSERT_WITH_CODE(
2751                                         !vega10_enable_smc_features(hwmgr,
2752                                         true,
2753                                         data->smu_features[GNLD_VR0HOT].smu_feature_bitmap),
2754                                         "Attempt to Enable VR0 Hot feature Failed!",
2755                                         return -1);
2756                         data->smu_features[GNLD_VR0HOT].enabled = true;
2757                 } else {
2758                         if (data->smu_features[GNLD_VR1HOT].supported) {
2759                                 PP_ASSERT_WITH_CODE(
2760                                                 !vega10_enable_smc_features(hwmgr,
2761                                                 true,
2762                                                 data->smu_features[GNLD_VR1HOT].smu_feature_bitmap),
2763                                                 "Attempt to Enable VR0 Hot feature Failed!",
2764                                                 return -1);
2765                                 data->smu_features[GNLD_VR1HOT].enabled = true;
2766                         }
2767                 }
2768         }
2769         return 0;
2770 }
2771
2772 static int vega10_enable_ulv(struct pp_hwmgr *hwmgr)
2773 {
2774         struct vega10_hwmgr *data = hwmgr->backend;
2775
2776         if (data->registry_data.ulv_support) {
2777                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2778                                 true, data->smu_features[GNLD_ULV].smu_feature_bitmap),
2779                                 "Enable ULV Feature Failed!",
2780                                 return -1);
2781                 data->smu_features[GNLD_ULV].enabled = true;
2782         }
2783
2784         return 0;
2785 }
2786
2787 static int vega10_disable_ulv(struct pp_hwmgr *hwmgr)
2788 {
2789         struct vega10_hwmgr *data = hwmgr->backend;
2790
2791         if (data->registry_data.ulv_support) {
2792                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2793                                 false, data->smu_features[GNLD_ULV].smu_feature_bitmap),
2794                                 "disable ULV Feature Failed!",
2795                                 return -EINVAL);
2796                 data->smu_features[GNLD_ULV].enabled = false;
2797         }
2798
2799         return 0;
2800 }
2801
2802 static int vega10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
2803 {
2804         struct vega10_hwmgr *data = hwmgr->backend;
2805
2806         if (data->smu_features[GNLD_DS_GFXCLK].supported) {
2807                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2808                                 true, data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap),
2809                                 "Attempt to Enable DS_GFXCLK Feature Failed!",
2810                                 return -EINVAL);
2811                 data->smu_features[GNLD_DS_GFXCLK].enabled = true;
2812         }
2813
2814         if (data->smu_features[GNLD_DS_SOCCLK].supported) {
2815                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2816                                 true, data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap),
2817                                 "Attempt to Enable DS_SOCCLK Feature Failed!",
2818                                 return -EINVAL);
2819                 data->smu_features[GNLD_DS_SOCCLK].enabled = true;
2820         }
2821
2822         if (data->smu_features[GNLD_DS_LCLK].supported) {
2823                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2824                                 true, data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap),
2825                                 "Attempt to Enable DS_LCLK Feature Failed!",
2826                                 return -EINVAL);
2827                 data->smu_features[GNLD_DS_LCLK].enabled = true;
2828         }
2829
2830         if (data->smu_features[GNLD_DS_DCEFCLK].supported) {
2831                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2832                                 true, data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap),
2833                                 "Attempt to Enable DS_DCEFCLK Feature Failed!",
2834                                 return -EINVAL);
2835                 data->smu_features[GNLD_DS_DCEFCLK].enabled = true;
2836         }
2837
2838         return 0;
2839 }
2840
2841 static int vega10_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
2842 {
2843         struct vega10_hwmgr *data = hwmgr->backend;
2844
2845         if (data->smu_features[GNLD_DS_GFXCLK].supported) {
2846                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2847                                 false, data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap),
2848                                 "Attempt to disable DS_GFXCLK Feature Failed!",
2849                                 return -EINVAL);
2850                 data->smu_features[GNLD_DS_GFXCLK].enabled = false;
2851         }
2852
2853         if (data->smu_features[GNLD_DS_SOCCLK].supported) {
2854                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2855                                 false, data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap),
2856                                 "Attempt to disable DS_ Feature Failed!",
2857                                 return -EINVAL);
2858                 data->smu_features[GNLD_DS_SOCCLK].enabled = false;
2859         }
2860
2861         if (data->smu_features[GNLD_DS_LCLK].supported) {
2862                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2863                                 false, data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap),
2864                                 "Attempt to disable DS_LCLK Feature Failed!",
2865                                 return -EINVAL);
2866                 data->smu_features[GNLD_DS_LCLK].enabled = false;
2867         }
2868
2869         if (data->smu_features[GNLD_DS_DCEFCLK].supported) {
2870                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2871                                 false, data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap),
2872                                 "Attempt to disable DS_DCEFCLK Feature Failed!",
2873                                 return -EINVAL);
2874                 data->smu_features[GNLD_DS_DCEFCLK].enabled = false;
2875         }
2876
2877         return 0;
2878 }
2879
2880 static int vega10_stop_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap)
2881 {
2882         struct vega10_hwmgr *data = hwmgr->backend;
2883         uint32_t i, feature_mask = 0;
2884
2885         if (!hwmgr->not_vf)
2886                 return 0;
2887
2888         if(data->smu_features[GNLD_LED_DISPLAY].supported == true){
2889                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2890                                 false, data->smu_features[GNLD_LED_DISPLAY].smu_feature_bitmap),
2891                 "Attempt to disable LED DPM feature failed!", return -EINVAL);
2892                 data->smu_features[GNLD_LED_DISPLAY].enabled = false;
2893         }
2894
2895         for (i = 0; i < GNLD_DPM_MAX; i++) {
2896                 if (data->smu_features[i].smu_feature_bitmap & bitmap) {
2897                         if (data->smu_features[i].supported) {
2898                                 if (data->smu_features[i].enabled) {
2899                                         feature_mask |= data->smu_features[i].
2900                                                         smu_feature_bitmap;
2901                                         data->smu_features[i].enabled = false;
2902                                 }
2903                         }
2904                 }
2905         }
2906
2907         vega10_enable_smc_features(hwmgr, false, feature_mask);
2908
2909         return 0;
2910 }
2911
2912 /**
2913  * Tell SMC to enabled the supported DPMs.
2914  *
2915  * @hwmgr:   the address of the powerplay hardware manager.
2916  * @bitmap:  bitmap for the features to enabled.
2917  * return:  0 on at least one DPM is successfully enabled.
2918  */
2919 static int vega10_start_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap)
2920 {
2921         struct vega10_hwmgr *data = hwmgr->backend;
2922         uint32_t i, feature_mask = 0;
2923
2924         for (i = 0; i < GNLD_DPM_MAX; i++) {
2925                 if (data->smu_features[i].smu_feature_bitmap & bitmap) {
2926                         if (data->smu_features[i].supported) {
2927                                 if (!data->smu_features[i].enabled) {
2928                                         feature_mask |= data->smu_features[i].
2929                                                         smu_feature_bitmap;
2930                                         data->smu_features[i].enabled = true;
2931                                 }
2932                         }
2933                 }
2934         }
2935
2936         if (vega10_enable_smc_features(hwmgr,
2937                         true, feature_mask)) {
2938                 for (i = 0; i < GNLD_DPM_MAX; i++) {
2939                         if (data->smu_features[i].smu_feature_bitmap &
2940                                         feature_mask)
2941                                 data->smu_features[i].enabled = false;
2942                 }
2943         }
2944
2945         if(data->smu_features[GNLD_LED_DISPLAY].supported == true){
2946                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2947                                 true, data->smu_features[GNLD_LED_DISPLAY].smu_feature_bitmap),
2948                 "Attempt to Enable LED DPM feature Failed!", return -EINVAL);
2949                 data->smu_features[GNLD_LED_DISPLAY].enabled = true;
2950         }
2951
2952         if (data->vbios_boot_state.bsoc_vddc_lock) {
2953                 smum_send_msg_to_smc_with_parameter(hwmgr,
2954                                                 PPSMC_MSG_SetFloorSocVoltage, 0,
2955                                                 NULL);
2956                 data->vbios_boot_state.bsoc_vddc_lock = false;
2957         }
2958
2959         if (PP_CAP(PHM_PlatformCaps_Falcon_QuickTransition)) {
2960                 if (data->smu_features[GNLD_ACDC].supported) {
2961                         PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2962                                         true, data->smu_features[GNLD_ACDC].smu_feature_bitmap),
2963                                         "Attempt to Enable DS_GFXCLK Feature Failed!",
2964                                         return -1);
2965                         data->smu_features[GNLD_ACDC].enabled = true;
2966                 }
2967         }
2968
2969         return 0;
2970 }
2971
2972
2973 static int vega10_enable_disable_PCC_limit_feature(struct pp_hwmgr *hwmgr, bool enable)
2974 {
2975         struct vega10_hwmgr *data = hwmgr->backend;
2976
2977         if (data->smu_features[GNLD_PCC_LIMIT].supported) {
2978                 if (enable == data->smu_features[GNLD_PCC_LIMIT].enabled)
2979                         pr_info("GNLD_PCC_LIMIT has been %s \n", enable ? "enabled" : "disabled");
2980                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2981                                 enable, data->smu_features[GNLD_PCC_LIMIT].smu_feature_bitmap),
2982                                 "Attempt to Enable PCC Limit feature Failed!",
2983                                 return -EINVAL);
2984                 data->smu_features[GNLD_PCC_LIMIT].enabled = enable;
2985         }
2986
2987         return 0;
2988 }
2989
2990 static int vega10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
2991 {
2992         struct vega10_hwmgr *data = hwmgr->backend;
2993         int tmp_result, result = 0;
2994
2995         if (hwmgr->not_vf) {
2996                 vega10_enable_disable_PCC_limit_feature(hwmgr, true);
2997
2998                 smum_send_msg_to_smc_with_parameter(hwmgr,
2999                         PPSMC_MSG_ConfigureTelemetry, data->config_telemetry,
3000                         NULL);
3001
3002                 tmp_result = vega10_construct_voltage_tables(hwmgr);
3003                 PP_ASSERT_WITH_CODE(!tmp_result,
3004                                     "Failed to construct voltage tables!",
3005                                     result = tmp_result);
3006         }
3007
3008         if (hwmgr->not_vf || hwmgr->pp_one_vf) {
3009                 tmp_result = vega10_init_smc_table(hwmgr);
3010                 PP_ASSERT_WITH_CODE(!tmp_result,
3011                                     "Failed to initialize SMC table!",
3012                                     result = tmp_result);
3013         }
3014
3015         if (hwmgr->not_vf) {
3016                 if (PP_CAP(PHM_PlatformCaps_ThermalController)) {
3017                         tmp_result = vega10_enable_thermal_protection(hwmgr);
3018                         PP_ASSERT_WITH_CODE(!tmp_result,
3019                                             "Failed to enable thermal protection!",
3020                                             result = tmp_result);
3021                 }
3022
3023                 tmp_result = vega10_enable_vrhot_feature(hwmgr);
3024                 PP_ASSERT_WITH_CODE(!tmp_result,
3025                                     "Failed to enable VR hot feature!",
3026                                     result = tmp_result);
3027
3028                 tmp_result = vega10_enable_deep_sleep_master_switch(hwmgr);
3029                 PP_ASSERT_WITH_CODE(!tmp_result,
3030                                     "Failed to enable deep sleep master switch!",
3031                                     result = tmp_result);
3032         }
3033
3034         if (hwmgr->not_vf) {
3035                 tmp_result = vega10_start_dpm(hwmgr, SMC_DPM_FEATURES);
3036                 PP_ASSERT_WITH_CODE(!tmp_result,
3037                                     "Failed to start DPM!", result = tmp_result);
3038         }
3039
3040         if (hwmgr->not_vf) {
3041                 /* enable didt, do not abort if failed didt */
3042                 tmp_result = vega10_enable_didt_config(hwmgr);
3043                 PP_ASSERT(!tmp_result,
3044                           "Failed to enable didt config!");
3045         }
3046
3047         tmp_result = vega10_enable_power_containment(hwmgr);
3048         PP_ASSERT_WITH_CODE(!tmp_result,
3049                             "Failed to enable power containment!",
3050                             result = tmp_result);
3051
3052         if (hwmgr->not_vf) {
3053                 tmp_result = vega10_power_control_set_level(hwmgr);
3054                 PP_ASSERT_WITH_CODE(!tmp_result,
3055                                     "Failed to power control set level!",
3056                                     result = tmp_result);
3057
3058                 tmp_result = vega10_enable_ulv(hwmgr);
3059                 PP_ASSERT_WITH_CODE(!tmp_result,
3060                                     "Failed to enable ULV!",
3061                                     result = tmp_result);
3062         }
3063
3064         return result;
3065 }
3066
3067 static int vega10_get_power_state_size(struct pp_hwmgr *hwmgr)
3068 {
3069         return sizeof(struct vega10_power_state);
3070 }
3071
3072 static int vega10_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
3073                 void *state, struct pp_power_state *power_state,
3074                 void *pp_table, uint32_t classification_flag)
3075 {
3076         ATOM_Vega10_GFXCLK_Dependency_Record_V2 *patom_record_V2;
3077         struct vega10_power_state *vega10_power_state =
3078                         cast_phw_vega10_power_state(&(power_state->hardware));
3079         struct vega10_performance_level *performance_level;
3080         ATOM_Vega10_State *state_entry = (ATOM_Vega10_State *)state;
3081         ATOM_Vega10_POWERPLAYTABLE *powerplay_table =
3082                         (ATOM_Vega10_POWERPLAYTABLE *)pp_table;
3083         ATOM_Vega10_SOCCLK_Dependency_Table *socclk_dep_table =
3084                         (ATOM_Vega10_SOCCLK_Dependency_Table *)
3085                         (((unsigned long)powerplay_table) +
3086                         le16_to_cpu(powerplay_table->usSocclkDependencyTableOffset));
3087         ATOM_Vega10_GFXCLK_Dependency_Table *gfxclk_dep_table =
3088                         (ATOM_Vega10_GFXCLK_Dependency_Table *)
3089                         (((unsigned long)powerplay_table) +
3090                         le16_to_cpu(powerplay_table->usGfxclkDependencyTableOffset));
3091         ATOM_Vega10_MCLK_Dependency_Table *mclk_dep_table =
3092                         (ATOM_Vega10_MCLK_Dependency_Table *)
3093                         (((unsigned long)powerplay_table) +
3094                         le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
3095
3096
3097         /* The following fields are not initialized here:
3098          * id orderedList allStatesList
3099          */
3100         power_state->classification.ui_label =
3101                         (le16_to_cpu(state_entry->usClassification) &
3102                         ATOM_PPLIB_CLASSIFICATION_UI_MASK) >>
3103                         ATOM_PPLIB_CLASSIFICATION_UI_SHIFT;
3104         power_state->classification.flags = classification_flag;
3105         /* NOTE: There is a classification2 flag in BIOS
3106          * that is not being used right now
3107          */
3108         power_state->classification.temporary_state = false;
3109         power_state->classification.to_be_deleted = false;
3110
3111         power_state->validation.disallowOnDC =
3112                         ((le32_to_cpu(state_entry->ulCapsAndSettings) &
3113                                         ATOM_Vega10_DISALLOW_ON_DC) != 0);
3114
3115         power_state->display.disableFrameModulation = false;
3116         power_state->display.limitRefreshrate = false;
3117         power_state->display.enableVariBright =
3118                         ((le32_to_cpu(state_entry->ulCapsAndSettings) &
3119                                         ATOM_Vega10_ENABLE_VARIBRIGHT) != 0);
3120
3121         power_state->validation.supportedPowerLevels = 0;
3122         power_state->uvd_clocks.VCLK = 0;
3123         power_state->uvd_clocks.DCLK = 0;
3124         power_state->temperatures.min = 0;
3125         power_state->temperatures.max = 0;
3126
3127         performance_level = &(vega10_power_state->performance_levels
3128                         [vega10_power_state->performance_level_count++]);
3129
3130         PP_ASSERT_WITH_CODE(
3131                         (vega10_power_state->performance_level_count <
3132                                         NUM_GFXCLK_DPM_LEVELS),
3133                         "Performance levels exceeds SMC limit!",
3134                         return -1);
3135
3136         PP_ASSERT_WITH_CODE(
3137                         (vega10_power_state->performance_level_count <=
3138                                         hwmgr->platform_descriptor.
3139                                         hardwareActivityPerformanceLevels),
3140                         "Performance levels exceeds Driver limit!",
3141                         return -1);
3142
3143         /* Performance levels are arranged from low to high. */
3144         performance_level->soc_clock = socclk_dep_table->entries
3145                         [state_entry->ucSocClockIndexLow].ulClk;
3146         performance_level->gfx_clock = gfxclk_dep_table->entries
3147                         [state_entry->ucGfxClockIndexLow].ulClk;
3148         performance_level->mem_clock = mclk_dep_table->entries
3149                         [state_entry->ucMemClockIndexLow].ulMemClk;
3150
3151         performance_level = &(vega10_power_state->performance_levels
3152                                 [vega10_power_state->performance_level_count++]);
3153         performance_level->soc_clock = socclk_dep_table->entries
3154                                 [state_entry->ucSocClockIndexHigh].ulClk;
3155         if (gfxclk_dep_table->ucRevId == 0) {
3156                 /* under vega10 pp one vf mode, the gfx clk dpm need be lower
3157                  * to level-4 due to the limited 110w-power
3158                  */
3159                 if (hwmgr->pp_one_vf && (state_entry->ucGfxClockIndexHigh > 0))
3160                         performance_level->gfx_clock =
3161                                 gfxclk_dep_table->entries[4].ulClk;
3162                 else
3163                         performance_level->gfx_clock = gfxclk_dep_table->entries
3164                                 [state_entry->ucGfxClockIndexHigh].ulClk;
3165         } else if (gfxclk_dep_table->ucRevId == 1) {
3166                 patom_record_V2 = (ATOM_Vega10_GFXCLK_Dependency_Record_V2 *)gfxclk_dep_table->entries;
3167                 if (hwmgr->pp_one_vf && (state_entry->ucGfxClockIndexHigh > 0))
3168                         performance_level->gfx_clock = patom_record_V2[4].ulClk;
3169                 else
3170                         performance_level->gfx_clock =
3171                                 patom_record_V2[state_entry->ucGfxClockIndexHigh].ulClk;
3172         }
3173
3174         performance_level->mem_clock = mclk_dep_table->entries
3175                         [state_entry->ucMemClockIndexHigh].ulMemClk;
3176         return 0;
3177 }
3178
3179 static int vega10_get_pp_table_entry(struct pp_hwmgr *hwmgr,
3180                 unsigned long entry_index, struct pp_power_state *state)
3181 {
3182         int result;
3183         struct vega10_power_state *ps;
3184
3185         state->hardware.magic = PhwVega10_Magic;
3186
3187         ps = cast_phw_vega10_power_state(&state->hardware);
3188
3189         result = vega10_get_powerplay_table_entry(hwmgr, entry_index, state,
3190                         vega10_get_pp_table_entry_callback_func);
3191         if (result)
3192                 return result;
3193
3194         /*
3195          * This is the earliest time we have all the dependency table
3196          * and the VBIOS boot state
3197          */
3198         /* set DC compatible flag if this state supports DC */
3199         if (!state->validation.disallowOnDC)
3200                 ps->dc_compatible = true;
3201
3202         ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
3203         ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
3204
3205         return 0;
3206 }
3207
3208 static int vega10_patch_boot_state(struct pp_hwmgr *hwmgr,
3209              struct pp_hw_power_state *hw_ps)
3210 {
3211         return 0;
3212 }
3213
3214 static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
3215                                 struct pp_power_state  *request_ps,
3216                         const struct pp_power_state *current_ps)
3217 {
3218         struct amdgpu_device *adev = hwmgr->adev;
3219         struct vega10_power_state *vega10_ps =
3220                                 cast_phw_vega10_power_state(&request_ps->hardware);
3221         uint32_t sclk;
3222         uint32_t mclk;
3223         struct PP_Clocks minimum_clocks = {0};
3224         bool disable_mclk_switching;
3225         bool disable_mclk_switching_for_frame_lock;
3226         bool disable_mclk_switching_for_vr;
3227         bool force_mclk_high;
3228         const struct phm_clock_and_voltage_limits *max_limits;
3229         uint32_t i;
3230         struct vega10_hwmgr *data = hwmgr->backend;
3231         struct phm_ppt_v2_information *table_info =
3232                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
3233         int32_t count;
3234         uint32_t stable_pstate_sclk_dpm_percentage;
3235         uint32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
3236         uint32_t latency;
3237
3238         data->battery_state = (PP_StateUILabel_Battery ==
3239                         request_ps->classification.ui_label);
3240
3241         if (vega10_ps->performance_level_count != 2)
3242                 pr_info("VI should always have 2 performance levels");
3243
3244         max_limits = adev->pm.ac_power ?
3245                         &(hwmgr->dyn_state.max_clock_voltage_on_ac) :
3246                         &(hwmgr->dyn_state.max_clock_voltage_on_dc);
3247
3248         /* Cap clock DPM tables at DC MAX if it is in DC. */
3249         if (!adev->pm.ac_power) {
3250                 for (i = 0; i < vega10_ps->performance_level_count; i++) {
3251                         if (vega10_ps->performance_levels[i].mem_clock >
3252                                 max_limits->mclk)
3253                                 vega10_ps->performance_levels[i].mem_clock =
3254                                                 max_limits->mclk;
3255                         if (vega10_ps->performance_levels[i].gfx_clock >
3256                                 max_limits->sclk)
3257                                 vega10_ps->performance_levels[i].gfx_clock =
3258                                                 max_limits->sclk;
3259                 }
3260         }
3261
3262         /* result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
3263         minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock;
3264         minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
3265
3266         if (PP_CAP(PHM_PlatformCaps_StablePState)) {
3267                 stable_pstate_sclk_dpm_percentage =
3268                         data->registry_data.stable_pstate_sclk_dpm_percentage;
3269                 PP_ASSERT_WITH_CODE(
3270                         data->registry_data.stable_pstate_sclk_dpm_percentage >= 1 &&
3271                         data->registry_data.stable_pstate_sclk_dpm_percentage <= 100,
3272                         "percent sclk value must range from 1% to 100%, setting default value",
3273                         stable_pstate_sclk_dpm_percentage = 75);
3274
3275                 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
3276                 stable_pstate_sclk = (max_limits->sclk *
3277                                 stable_pstate_sclk_dpm_percentage) / 100;
3278
3279                 for (count = table_info->vdd_dep_on_sclk->count - 1;
3280                                 count >= 0; count--) {
3281                         if (stable_pstate_sclk >=
3282                                         table_info->vdd_dep_on_sclk->entries[count].clk) {
3283                                 stable_pstate_sclk =
3284                                                 table_info->vdd_dep_on_sclk->entries[count].clk;
3285                                 break;
3286                         }
3287                 }
3288
3289                 if (count < 0)
3290                         stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;
3291
3292                 stable_pstate_mclk = max_limits->mclk;
3293
3294                 minimum_clocks.engineClock = stable_pstate_sclk;
3295                 minimum_clocks.memoryClock = stable_pstate_mclk;
3296         }
3297
3298         disable_mclk_switching_for_frame_lock =
3299                 PP_CAP(PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
3300         disable_mclk_switching_for_vr =
3301                 PP_CAP(PHM_PlatformCaps_DisableMclkSwitchForVR);
3302         force_mclk_high = PP_CAP(PHM_PlatformCaps_ForceMclkHigh);
3303
3304         if (hwmgr->display_config->num_display == 0)
3305                 disable_mclk_switching = false;
3306         else
3307                 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) &&
3308                                           !hwmgr->display_config->multi_monitor_in_sync) ||
3309                         disable_mclk_switching_for_frame_lock ||
3310                         disable_mclk_switching_for_vr ||
3311                         force_mclk_high;
3312
3313         sclk = vega10_ps->performance_levels[0].gfx_clock;
3314         mclk = vega10_ps->performance_levels[0].mem_clock;
3315
3316         if (sclk < minimum_clocks.engineClock)
3317                 sclk = (minimum_clocks.engineClock > max_limits->sclk) ?
3318                                 max_limits->sclk : minimum_clocks.engineClock;
3319
3320         if (mclk < minimum_clocks.memoryClock)
3321                 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ?
3322                                 max_limits->mclk : minimum_clocks.memoryClock;
3323
3324         vega10_ps->performance_levels[0].gfx_clock = sclk;
3325         vega10_ps->performance_levels[0].mem_clock = mclk;
3326
3327         if (vega10_ps->performance_levels[1].gfx_clock <
3328                         vega10_ps->performance_levels[0].gfx_clock)
3329                 vega10_ps->performance_levels[0].gfx_clock =
3330                                 vega10_ps->performance_levels[1].gfx_clock;
3331
3332         if (disable_mclk_switching) {
3333                 /* Set Mclk the max of level 0 and level 1 */
3334                 if (mclk < vega10_ps->performance_levels[1].mem_clock)
3335                         mclk = vega10_ps->performance_levels[1].mem_clock;
3336
3337                 /* Find the lowest MCLK frequency that is within
3338                  * the tolerable latency defined in DAL
3339                  */
3340                 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency;
3341                 for (i = 0; i < data->mclk_latency_table.count; i++) {
3342                         if ((data->mclk_latency_table.entries[i].latency <= latency) &&
3343                                 (data->mclk_latency_table.entries[i].frequency >=
3344                                                 vega10_ps->performance_levels[0].mem_clock) &&
3345                                 (data->mclk_latency_table.entries[i].frequency <=
3346                                                 vega10_ps->performance_levels[1].mem_clock))
3347                                 mclk = data->mclk_latency_table.entries[i].frequency;
3348                 }
3349                 vega10_ps->performance_levels[0].mem_clock = mclk;
3350         } else {
3351                 if (vega10_ps->performance_levels[1].mem_clock <
3352                                 vega10_ps->performance_levels[0].mem_clock)
3353                         vega10_ps->performance_levels[0].mem_clock =
3354                                         vega10_ps->performance_levels[1].mem_clock;
3355         }
3356
3357         if (PP_CAP(PHM_PlatformCaps_StablePState)) {
3358                 for (i = 0; i < vega10_ps->performance_level_count; i++) {
3359                         vega10_ps->performance_levels[i].gfx_clock = stable_pstate_sclk;
3360                         vega10_ps->performance_levels[i].mem_clock = stable_pstate_mclk;
3361                 }
3362         }
3363
3364         return 0;
3365 }
3366
3367 static int vega10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
3368 {
3369         struct vega10_hwmgr *data = hwmgr->backend;
3370         const struct phm_set_power_state_input *states =
3371                         (const struct phm_set_power_state_input *)input;
3372         const struct vega10_power_state *vega10_ps =
3373                         cast_const_phw_vega10_power_state(states->pnew_state);
3374         struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
3375         uint32_t sclk = vega10_ps->performance_levels
3376                         [vega10_ps->performance_level_count - 1].gfx_clock;
3377         struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
3378         uint32_t mclk = vega10_ps->performance_levels
3379                         [vega10_ps->performance_level_count - 1].mem_clock;
3380         uint32_t i;
3381
3382         for (i = 0; i < sclk_table->count; i++) {
3383                 if (sclk == sclk_table->dpm_levels[i].value)
3384                         break;
3385         }
3386
3387         if (i >= sclk_table->count) {
3388                 if (sclk > sclk_table->dpm_levels[i-1].value) {
3389                         data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
3390                         sclk_table->dpm_levels[i-1].value = sclk;
3391                 }
3392         }
3393
3394         for (i = 0; i < mclk_table->count; i++) {
3395                 if (mclk == mclk_table->dpm_levels[i].value)
3396                         break;
3397         }
3398
3399         if (i >= mclk_table->count) {
3400                 if (mclk > mclk_table->dpm_levels[i-1].value) {
3401                         data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
3402                         mclk_table->dpm_levels[i-1].value = mclk;
3403                 }
3404         }
3405
3406         if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
3407                 data->need_update_dpm_table |= DPMTABLE_UPDATE_MCLK;
3408
3409         return 0;
3410 }
3411
3412 static int vega10_populate_and_upload_sclk_mclk_dpm_levels(
3413                 struct pp_hwmgr *hwmgr, const void *input)
3414 {
3415         int result = 0;
3416         struct vega10_hwmgr *data = hwmgr->backend;
3417         struct vega10_dpm_table *dpm_table = &data->dpm_table;
3418         struct vega10_odn_dpm_table *odn_table = &data->odn_dpm_table;
3419         struct vega10_odn_clock_voltage_dependency_table *odn_clk_table = &odn_table->vdd_dep_on_sclk;
3420         int count;
3421
3422         if (!data->need_update_dpm_table)
3423                 return 0;
3424
3425         if (hwmgr->od_enabled && data->need_update_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
3426                 for (count = 0; count < dpm_table->gfx_table.count; count++)
3427                         dpm_table->gfx_table.dpm_levels[count].value = odn_clk_table->entries[count].clk;
3428         }
3429
3430         odn_clk_table = &odn_table->vdd_dep_on_mclk;
3431         if (hwmgr->od_enabled && data->need_update_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
3432                 for (count = 0; count < dpm_table->mem_table.count; count++)
3433                         dpm_table->mem_table.dpm_levels[count].value = odn_clk_table->entries[count].clk;
3434         }
3435
3436         if (data->need_update_dpm_table &
3437                         (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK | DPMTABLE_UPDATE_SOCCLK)) {
3438                 result = vega10_populate_all_graphic_levels(hwmgr);
3439                 PP_ASSERT_WITH_CODE((0 == result),
3440                                 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
3441                                 return result);
3442         }
3443
3444         if (data->need_update_dpm_table &
3445                         (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) {
3446                 result = vega10_populate_all_memory_levels(hwmgr);
3447                 PP_ASSERT_WITH_CODE((0 == result),
3448                                 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
3449                                 return result);
3450         }
3451
3452         vega10_populate_vddc_soc_levels(hwmgr);
3453
3454         return result;
3455 }
3456
3457 static int vega10_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
3458                 struct vega10_single_dpm_table *dpm_table,
3459                 uint32_t low_limit, uint32_t high_limit)
3460 {
3461         uint32_t i;
3462
3463         for (i = 0; i < dpm_table->count; i++) {
3464                 if ((dpm_table->dpm_levels[i].value < low_limit) ||
3465                     (dpm_table->dpm_levels[i].value > high_limit))
3466                         dpm_table->dpm_levels[i].enabled = false;
3467                 else
3468                         dpm_table->dpm_levels[i].enabled = true;
3469         }
3470         return 0;
3471 }
3472
3473 static int vega10_trim_single_dpm_states_with_mask(struct pp_hwmgr *hwmgr,
3474                 struct vega10_single_dpm_table *dpm_table,
3475                 uint32_t low_limit, uint32_t high_limit,
3476                 uint32_t disable_dpm_mask)
3477 {
3478         uint32_t i;
3479
3480         for (i = 0; i < dpm_table->count; i++) {
3481                 if ((dpm_table->dpm_levels[i].value < low_limit) ||
3482                     (dpm_table->dpm_levels[i].value > high_limit))
3483                         dpm_table->dpm_levels[i].enabled = false;
3484                 else if (!((1 << i) & disable_dpm_mask))
3485                         dpm_table->dpm_levels[i].enabled = false;
3486                 else
3487                         dpm_table->dpm_levels[i].enabled = true;
3488         }
3489         return 0;
3490 }
3491
3492 static int vega10_trim_dpm_states(struct pp_hwmgr *hwmgr,
3493                 const struct vega10_power_state *vega10_ps)
3494 {
3495         struct vega10_hwmgr *data = hwmgr->backend;
3496         uint32_t high_limit_count;
3497
3498         PP_ASSERT_WITH_CODE((vega10_ps->performance_level_count >= 1),
3499                         "power state did not have any performance level",
3500                         return -1);
3501
3502         high_limit_count = (vega10_ps->performance_level_count == 1) ? 0 : 1;
3503
3504         vega10_trim_single_dpm_states(hwmgr,
3505                         &(data->dpm_table.soc_table),
3506                         vega10_ps->performance_levels[0].soc_clock,
3507                         vega10_ps->performance_levels[high_limit_count].soc_clock);
3508
3509         vega10_trim_single_dpm_states_with_mask(hwmgr,
3510                         &(data->dpm_table.gfx_table),
3511                         vega10_ps->performance_levels[0].gfx_clock,
3512                         vega10_ps->performance_levels[high_limit_count].gfx_clock,
3513                         data->disable_dpm_mask);
3514
3515         vega10_trim_single_dpm_states(hwmgr,
3516                         &(data->dpm_table.mem_table),
3517                         vega10_ps->performance_levels[0].mem_clock,
3518                         vega10_ps->performance_levels[high_limit_count].mem_clock);
3519
3520         return 0;
3521 }
3522
3523 static uint32_t vega10_find_lowest_dpm_level(
3524                 struct vega10_single_dpm_table *table)
3525 {
3526         uint32_t i;
3527
3528         for (i = 0; i < table->count; i++) {
3529                 if (table->dpm_levels[i].enabled)
3530                         break;
3531         }
3532
3533         return i;
3534 }
3535
3536 static uint32_t vega10_find_highest_dpm_level(
3537                 struct vega10_single_dpm_table *table)
3538 {
3539         uint32_t i = 0;
3540
3541         if (table->count <= MAX_REGULAR_DPM_NUMBER) {
3542                 for (i = table->count; i > 0; i--) {
3543                         if (table->dpm_levels[i - 1].enabled)
3544                                 return i - 1;
3545                 }
3546         } else {
3547                 pr_info("DPM Table Has Too Many Entries!");
3548                 return MAX_REGULAR_DPM_NUMBER - 1;
3549         }
3550
3551         return i;
3552 }
3553
3554 static void vega10_apply_dal_minimum_voltage_request(
3555                 struct pp_hwmgr *hwmgr)
3556 {
3557         return;
3558 }
3559
3560 static int vega10_get_soc_index_for_max_uclk(struct pp_hwmgr *hwmgr)
3561 {
3562         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table_on_mclk;
3563         struct phm_ppt_v2_information *table_info =
3564                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
3565
3566         vdd_dep_table_on_mclk  = table_info->vdd_dep_on_mclk;
3567
3568         return vdd_dep_table_on_mclk->entries[NUM_UCLK_DPM_LEVELS - 1].vddInd + 1;
3569 }
3570
3571 static int vega10_upload_dpm_bootup_level(struct pp_hwmgr *hwmgr)
3572 {
3573         struct vega10_hwmgr *data = hwmgr->backend;
3574         uint32_t socclk_idx;
3575
3576         vega10_apply_dal_minimum_voltage_request(hwmgr);
3577
3578         if (!data->registry_data.sclk_dpm_key_disabled) {
3579                 if (data->smc_state_table.gfx_boot_level !=
3580                                 data->dpm_table.gfx_table.dpm_state.soft_min_level) {
3581                         smum_send_msg_to_smc_with_parameter(hwmgr,
3582                                 PPSMC_MSG_SetSoftMinGfxclkByIndex,
3583                                 data->smc_state_table.gfx_boot_level,
3584                                 NULL);
3585
3586                         data->dpm_table.gfx_table.dpm_state.soft_min_level =
3587                                         data->smc_state_table.gfx_boot_level;
3588                 }
3589         }
3590
3591         if (!data->registry_data.mclk_dpm_key_disabled) {
3592                 if (data->smc_state_table.mem_boot_level !=
3593                                 data->dpm_table.mem_table.dpm_state.soft_min_level) {
3594                         if ((data->smc_state_table.mem_boot_level == NUM_UCLK_DPM_LEVELS - 1)
3595                             && hwmgr->not_vf) {
3596                                 socclk_idx = vega10_get_soc_index_for_max_uclk(hwmgr);
3597                                 smum_send_msg_to_smc_with_parameter(hwmgr,
3598                                                 PPSMC_MSG_SetSoftMinSocclkByIndex,
3599                                                 socclk_idx,
3600                                                 NULL);
3601                         } else {
3602                                 smum_send_msg_to_smc_with_parameter(hwmgr,
3603                                                 PPSMC_MSG_SetSoftMinUclkByIndex,
3604                                                 data->smc_state_table.mem_boot_level,
3605                                                 NULL);
3606                         }
3607                         data->dpm_table.mem_table.dpm_state.soft_min_level =
3608                                         data->smc_state_table.mem_boot_level;
3609                 }
3610         }
3611
3612         if (!hwmgr->not_vf)
3613                 return 0;
3614
3615         if (!data->registry_data.socclk_dpm_key_disabled) {
3616                 if (data->smc_state_table.soc_boot_level !=
3617                                 data->dpm_table.soc_table.dpm_state.soft_min_level) {
3618                         smum_send_msg_to_smc_with_parameter(hwmgr,
3619                                 PPSMC_MSG_SetSoftMinSocclkByIndex,
3620                                 data->smc_state_table.soc_boot_level,
3621                                 NULL);
3622                         data->dpm_table.soc_table.dpm_state.soft_min_level =
3623                                         data->smc_state_table.soc_boot_level;
3624                 }
3625         }
3626
3627         return 0;
3628 }
3629
3630 static int vega10_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
3631 {
3632         struct vega10_hwmgr *data = hwmgr->backend;
3633
3634         vega10_apply_dal_minimum_voltage_request(hwmgr);
3635
3636         if (!data->registry_data.sclk_dpm_key_disabled) {
3637                 if (data->smc_state_table.gfx_max_level !=
3638                         data->dpm_table.gfx_table.dpm_state.soft_max_level) {
3639                         smum_send_msg_to_smc_with_parameter(hwmgr,
3640                                 PPSMC_MSG_SetSoftMaxGfxclkByIndex,
3641                                 data->smc_state_table.gfx_max_level,
3642                                 NULL);
3643                         data->dpm_table.gfx_table.dpm_state.soft_max_level =
3644                                         data->smc_state_table.gfx_max_level;
3645                 }
3646         }
3647
3648         if (!data->registry_data.mclk_dpm_key_disabled) {
3649                 if (data->smc_state_table.mem_max_level !=
3650                         data->dpm_table.mem_table.dpm_state.soft_max_level) {
3651                         smum_send_msg_to_smc_with_parameter(hwmgr,
3652                                         PPSMC_MSG_SetSoftMaxUclkByIndex,
3653                                         data->smc_state_table.mem_max_level,
3654                                         NULL);
3655                         data->dpm_table.mem_table.dpm_state.soft_max_level =
3656                                         data->smc_state_table.mem_max_level;
3657                 }
3658         }
3659
3660         if (!hwmgr->not_vf)
3661                 return 0;
3662
3663         if (!data->registry_data.socclk_dpm_key_disabled) {
3664                 if (data->smc_state_table.soc_max_level !=
3665                         data->dpm_table.soc_table.dpm_state.soft_max_level) {
3666                         smum_send_msg_to_smc_with_parameter(hwmgr,
3667                                 PPSMC_MSG_SetSoftMaxSocclkByIndex,
3668                                 data->smc_state_table.soc_max_level,
3669                                 NULL);
3670                         data->dpm_table.soc_table.dpm_state.soft_max_level =
3671                                         data->smc_state_table.soc_max_level;
3672                 }
3673         }
3674
3675         return 0;
3676 }
3677
3678 static int vega10_generate_dpm_level_enable_mask(
3679                 struct pp_hwmgr *hwmgr, const void *input)
3680 {
3681         struct vega10_hwmgr *data = hwmgr->backend;
3682         const struct phm_set_power_state_input *states =
3683                         (const struct phm_set_power_state_input *)input;
3684         const struct vega10_power_state *vega10_ps =
3685                         cast_const_phw_vega10_power_state(states->pnew_state);
3686         int i;
3687
3688         PP_ASSERT_WITH_CODE(!vega10_trim_dpm_states(hwmgr, vega10_ps),
3689                         "Attempt to Trim DPM States Failed!",
3690                         return -1);
3691
3692         data->smc_state_table.gfx_boot_level =
3693                         vega10_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
3694         data->smc_state_table.gfx_max_level =
3695                         vega10_find_highest_dpm_level(&(data->dpm_table.gfx_table));
3696         data->smc_state_table.mem_boot_level =
3697                         vega10_find_lowest_dpm_level(&(data->dpm_table.mem_table));
3698         data->smc_state_table.mem_max_level =
3699                         vega10_find_highest_dpm_level(&(data->dpm_table.mem_table));
3700         data->smc_state_table.soc_boot_level =
3701                         vega10_find_lowest_dpm_level(&(data->dpm_table.soc_table));
3702         data->smc_state_table.soc_max_level =
3703                         vega10_find_highest_dpm_level(&(data->dpm_table.soc_table));
3704
3705         PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
3706                         "Attempt to upload DPM Bootup Levels Failed!",
3707                         return -1);
3708         PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
3709                         "Attempt to upload DPM Max Levels Failed!",
3710                         return -1);
3711         for(i = data->smc_state_table.gfx_boot_level; i < data->smc_state_table.gfx_max_level; i++)
3712                 data->dpm_table.gfx_table.dpm_levels[i].enabled = true;
3713
3714
3715         for(i = data->smc_state_table.mem_boot_level; i < data->smc_state_table.mem_max_level; i++)
3716                 data->dpm_table.mem_table.dpm_levels[i].enabled = true;
3717
3718         for (i = data->smc_state_table.soc_boot_level; i < data->smc_state_table.soc_max_level; i++)
3719                 data->dpm_table.soc_table.dpm_levels[i].enabled = true;
3720
3721         return 0;
3722 }
3723
3724 int vega10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
3725 {
3726         struct vega10_hwmgr *data = hwmgr->backend;
3727
3728         if (data->smu_features[GNLD_DPM_VCE].supported) {
3729                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
3730                                 enable,
3731                                 data->smu_features[GNLD_DPM_VCE].smu_feature_bitmap),
3732                                 "Attempt to Enable/Disable DPM VCE Failed!",
3733                                 return -1);
3734                 data->smu_features[GNLD_DPM_VCE].enabled = enable;
3735         }
3736
3737         return 0;
3738 }
3739
3740 static int vega10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
3741 {
3742         struct vega10_hwmgr *data = hwmgr->backend;
3743         uint32_t low_sclk_interrupt_threshold = 0;
3744
3745         if (PP_CAP(PHM_PlatformCaps_SclkThrottleLowNotification) &&
3746                 (data->low_sclk_interrupt_threshold != 0)) {
3747                 low_sclk_interrupt_threshold =
3748                                 data->low_sclk_interrupt_threshold;
3749
3750                 data->smc_state_table.pp_table.LowGfxclkInterruptThreshold =
3751                                 cpu_to_le32(low_sclk_interrupt_threshold);
3752
3753                 /* This message will also enable SmcToHost Interrupt */
3754                 smum_send_msg_to_smc_with_parameter(hwmgr,
3755                                 PPSMC_MSG_SetLowGfxclkInterruptThreshold,
3756                                 (uint32_t)low_sclk_interrupt_threshold,
3757                                 NULL);
3758         }
3759
3760         return 0;
3761 }
3762
3763 static int vega10_set_power_state_tasks(struct pp_hwmgr *hwmgr,
3764                 const void *input)
3765 {
3766         int tmp_result, result = 0;
3767         struct vega10_hwmgr *data = hwmgr->backend;
3768         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
3769
3770         tmp_result = vega10_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
3771         PP_ASSERT_WITH_CODE(!tmp_result,
3772                         "Failed to find DPM states clocks in DPM table!",
3773                         result = tmp_result);
3774
3775         tmp_result = vega10_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
3776         PP_ASSERT_WITH_CODE(!tmp_result,
3777                         "Failed to populate and upload SCLK MCLK DPM levels!",
3778                         result = tmp_result);
3779
3780         tmp_result = vega10_generate_dpm_level_enable_mask(hwmgr, input);
3781         PP_ASSERT_WITH_CODE(!tmp_result,
3782                         "Failed to generate DPM level enabled mask!",
3783                         result = tmp_result);
3784
3785         tmp_result = vega10_update_sclk_threshold(hwmgr);
3786         PP_ASSERT_WITH_CODE(!tmp_result,
3787                         "Failed to update SCLK threshold!",
3788                         result = tmp_result);
3789
3790         result = smum_smc_table_manager(hwmgr, (uint8_t *)pp_table, PPTABLE, false);
3791         PP_ASSERT_WITH_CODE(!result,
3792                         "Failed to upload PPtable!", return result);
3793
3794         /*
3795          * If a custom pp table is loaded, set DPMTABLE_OD_UPDATE_VDDC flag.
3796          * That effectively disables AVFS feature.
3797          */
3798         if(hwmgr->hardcode_pp_table != NULL)
3799                 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC;
3800
3801         vega10_update_avfs(hwmgr);
3802
3803         /*
3804          * Clear all OD flags except DPMTABLE_OD_UPDATE_VDDC.
3805          * That will help to keep AVFS disabled.
3806          */
3807         data->need_update_dpm_table &= DPMTABLE_OD_UPDATE_VDDC;
3808
3809         return 0;
3810 }
3811
3812 static uint32_t vega10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
3813 {
3814         struct pp_power_state *ps;
3815         struct vega10_power_state *vega10_ps;
3816
3817         if (hwmgr == NULL)
3818                 return -EINVAL;
3819
3820         ps = hwmgr->request_ps;
3821
3822         if (ps == NULL)
3823                 return -EINVAL;
3824
3825         vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
3826
3827         if (low)
3828                 return vega10_ps->performance_levels[0].gfx_clock;
3829         else
3830                 return vega10_ps->performance_levels
3831                                 [vega10_ps->performance_level_count - 1].gfx_clock;
3832 }
3833
3834 static uint32_t vega10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
3835 {
3836         struct pp_power_state *ps;
3837         struct vega10_power_state *vega10_ps;
3838
3839         if (hwmgr == NULL)
3840                 return -EINVAL;
3841
3842         ps = hwmgr->request_ps;
3843
3844         if (ps == NULL)
3845                 return -EINVAL;
3846
3847         vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
3848
3849         if (low)
3850                 return vega10_ps->performance_levels[0].mem_clock;
3851         else
3852                 return vega10_ps->performance_levels
3853                                 [vega10_ps->performance_level_count-1].mem_clock;
3854 }
3855
3856 static int vega10_get_gpu_power(struct pp_hwmgr *hwmgr,
3857                 uint32_t *query)
3858 {
3859         uint32_t value;
3860
3861         if (!query)
3862                 return -EINVAL;
3863
3864         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrPkgPwr, &value);
3865
3866         /* SMC returning actual watts, keep consistent with legacy asics, low 8 bit as 8 fractional bits */
3867         *query = value << 8;
3868
3869         return 0;
3870 }
3871
3872 static int vega10_read_sensor(struct pp_hwmgr *hwmgr, int idx,
3873                               void *value, int *size)
3874 {
3875         struct amdgpu_device *adev = hwmgr->adev;
3876         uint32_t sclk_mhz, mclk_idx, activity_percent = 0;
3877         struct vega10_hwmgr *data = hwmgr->backend;
3878         struct vega10_dpm_table *dpm_table = &data->dpm_table;
3879         int ret = 0;
3880         uint32_t val_vid;
3881
3882         switch (idx) {
3883         case AMDGPU_PP_SENSOR_GFX_SCLK:
3884                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetAverageGfxclkActualFrequency, &sclk_mhz);
3885                 *((uint32_t *)value) = sclk_mhz * 100;
3886                 break;
3887         case AMDGPU_PP_SENSOR_GFX_MCLK:
3888                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex, &mclk_idx);
3889                 if (mclk_idx < dpm_table->mem_table.count) {
3890                         *((uint32_t *)value) = dpm_table->mem_table.dpm_levels[mclk_idx].value;
3891                         *size = 4;
3892                 } else {
3893                         ret = -EINVAL;
3894                 }
3895                 break;
3896         case AMDGPU_PP_SENSOR_GPU_LOAD:
3897                 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetAverageGfxActivity, 0,
3898                                                 &activity_percent);
3899                 *((uint32_t *)value) = activity_percent > 100 ? 100 : activity_percent;
3900                 *size = 4;
3901                 break;
3902         case AMDGPU_PP_SENSOR_GPU_TEMP:
3903                 *((uint32_t *)value) = vega10_thermal_get_temperature(hwmgr);
3904                 *size = 4;
3905                 break;
3906         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
3907                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetTemperatureHotspot, (uint32_t *)value);
3908                 *((uint32_t *)value) = *((uint32_t *)value) *
3909                         PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
3910                 *size = 4;
3911                 break;
3912         case AMDGPU_PP_SENSOR_MEM_TEMP:
3913                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetTemperatureHBM, (uint32_t *)value);
3914                 *((uint32_t *)value) = *((uint32_t *)value) *
3915                         PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
3916                 *size = 4;
3917                 break;
3918         case AMDGPU_PP_SENSOR_UVD_POWER:
3919                 *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1;
3920                 *size = 4;
3921                 break;
3922         case AMDGPU_PP_SENSOR_VCE_POWER:
3923                 *((uint32_t *)value) = data->vce_power_gated ? 0 : 1;
3924                 *size = 4;
3925                 break;
3926         case AMDGPU_PP_SENSOR_GPU_POWER:
3927                 ret = vega10_get_gpu_power(hwmgr, (uint32_t *)value);
3928                 break;
3929         case AMDGPU_PP_SENSOR_VDDGFX:
3930                 val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_PLANE0_CURRENTVID) &
3931                         SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID_MASK) >>
3932                         SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID__SHIFT;
3933                 *((uint32_t *)value) = (uint32_t)convert_to_vddc((uint8_t)val_vid);
3934                 return 0;
3935         case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
3936                 ret = vega10_get_enabled_smc_features(hwmgr, (uint64_t *)value);
3937                 if (!ret)
3938                         *size = 8;
3939                 break;
3940         default:
3941                 ret = -EINVAL;
3942                 break;
3943         }
3944
3945         return ret;
3946 }
3947
3948 static void vega10_notify_smc_display_change(struct pp_hwmgr *hwmgr,
3949                 bool has_disp)
3950 {
3951         smum_send_msg_to_smc_with_parameter(hwmgr,
3952                         PPSMC_MSG_SetUclkFastSwitch,
3953                         has_disp ? 1 : 0,
3954                         NULL);
3955 }
3956
3957 static int vega10_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
3958                 struct pp_display_clock_request *clock_req)
3959 {
3960         int result = 0;
3961         enum amd_pp_clock_type clk_type = clock_req->clock_type;
3962         uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
3963         DSPCLK_e clk_select = 0;
3964         uint32_t clk_request = 0;
3965
3966         switch (clk_type) {
3967         case amd_pp_dcef_clock:
3968                 clk_select = DSPCLK_DCEFCLK;
3969                 break;
3970         case amd_pp_disp_clock:
3971                 clk_select = DSPCLK_DISPCLK;
3972                 break;
3973         case amd_pp_pixel_clock:
3974                 clk_select = DSPCLK_PIXCLK;
3975                 break;
3976         case amd_pp_phy_clock:
3977                 clk_select = DSPCLK_PHYCLK;
3978                 break;
3979         default:
3980                 pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!");
3981                 result = -1;
3982                 break;
3983         }
3984
3985         if (!result) {
3986                 clk_request = (clk_freq << 16) | clk_select;
3987                 smum_send_msg_to_smc_with_parameter(hwmgr,
3988                                 PPSMC_MSG_RequestDisplayClockByFreq,
3989                                 clk_request,
3990                                 NULL);
3991         }
3992
3993         return result;
3994 }
3995
3996 static uint8_t vega10_get_uclk_index(struct pp_hwmgr *hwmgr,
3997                         struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table,
3998                                                 uint32_t frequency)
3999 {
4000         uint8_t count;
4001         uint8_t i;
4002
4003         if (mclk_table == NULL || mclk_table->count == 0)
4004                 return 0;
4005
4006         count = (uint8_t)(mclk_table->count);
4007
4008         for(i = 0; i < count; i++) {
4009                 if(mclk_table->entries[i].clk >= frequency)
4010                         return i;
4011         }
4012
4013         return i-1;
4014 }
4015
4016 static int vega10_notify_smc_display_config_after_ps_adjustment(
4017                 struct pp_hwmgr *hwmgr)
4018 {
4019         struct vega10_hwmgr *data = hwmgr->backend;
4020         struct vega10_single_dpm_table *dpm_table =
4021                         &data->dpm_table.dcef_table;
4022         struct phm_ppt_v2_information *table_info =
4023                         (struct phm_ppt_v2_information *)hwmgr->pptable;
4024         struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table = table_info->vdd_dep_on_mclk;
4025         uint32_t idx;
4026         struct PP_Clocks min_clocks = {0};
4027         uint32_t i;
4028         struct pp_display_clock_request clock_req;
4029
4030         if ((hwmgr->display_config->num_display > 1) &&
4031              !hwmgr->display_config->multi_monitor_in_sync &&
4032              !hwmgr->display_config->nb_pstate_switch_disable)
4033                 vega10_notify_smc_display_change(hwmgr, false);
4034         else
4035                 vega10_notify_smc_display_change(hwmgr, true);
4036
4037         min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
4038         min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;
4039         min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
4040
4041         for (i = 0; i < dpm_table->count; i++) {
4042                 if (dpm_table->dpm_levels[i].value == min_clocks.dcefClock)
4043                         break;
4044         }
4045
4046         if (i < dpm_table->count) {
4047                 clock_req.clock_type = amd_pp_dcef_clock;
4048                 clock_req.clock_freq_in_khz = dpm_table->dpm_levels[i].value * 10;
4049                 if (!vega10_display_clock_voltage_request(hwmgr, &clock_req)) {
4050                         smum_send_msg_to_smc_with_parameter(
4051                                         hwmgr, PPSMC_MSG_SetMinDeepSleepDcefclk,
4052                                         min_clocks.dcefClockInSR / 100,
4053                                         NULL);
4054                 } else {
4055                         pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
4056                 }
4057         } else {
4058                 pr_debug("Cannot find requested DCEFCLK!");
4059         }
4060
4061         if (min_clocks.memoryClock != 0) {
4062                 idx = vega10_get_uclk_index(hwmgr, mclk_table, min_clocks.memoryClock);
4063                 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetSoftMinUclkByIndex, idx,
4064                                                 NULL);
4065                 data->dpm_table.mem_table.dpm_state.soft_min_level= idx;
4066         }
4067
4068         return 0;
4069 }
4070
4071 static int vega10_force_dpm_highest(struct pp_hwmgr *hwmgr)
4072 {
4073         struct vega10_hwmgr *data = hwmgr->backend;
4074
4075         data->smc_state_table.gfx_boot_level =
4076         data->smc_state_table.gfx_max_level =
4077                         vega10_find_highest_dpm_level(&(data->dpm_table.gfx_table));
4078         data->smc_state_table.mem_boot_level =
4079         data->smc_state_table.mem_max_level =
4080                         vega10_find_highest_dpm_level(&(data->dpm_table.mem_table));
4081
4082         PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
4083                         "Failed to upload boot level to highest!",
4084                         return -1);
4085
4086         PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
4087                         "Failed to upload dpm max level to highest!",
4088                         return -1);
4089
4090         return 0;
4091 }
4092
4093 static int vega10_force_dpm_lowest(struct pp_hwmgr *hwmgr)
4094 {
4095         struct vega10_hwmgr *data = hwmgr->backend;
4096
4097         data->smc_state_table.gfx_boot_level =
4098         data->smc_state_table.gfx_max_level =
4099                         vega10_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
4100         data->smc_state_table.mem_boot_level =
4101         data->smc_state_table.mem_max_level =
4102                         vega10_find_lowest_dpm_level(&(data->dpm_table.mem_table));
4103
4104         PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
4105                         "Failed to upload boot level to highest!",
4106                         return -1);
4107
4108         PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
4109                         "Failed to upload dpm max level to highest!",
4110                         return -1);
4111
4112         return 0;
4113
4114 }
4115
4116 static int vega10_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
4117 {
4118         struct vega10_hwmgr *data = hwmgr->backend;
4119
4120         data->smc_state_table.gfx_boot_level =
4121                         vega10_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
4122         data->smc_state_table.gfx_max_level =
4123                         vega10_find_highest_dpm_level(&(data->dpm_table.gfx_table));
4124         data->smc_state_table.mem_boot_level =
4125                         vega10_find_lowest_dpm_level(&(data->dpm_table.mem_table));
4126         data->smc_state_table.mem_max_level =
4127                         vega10_find_highest_dpm_level(&(data->dpm_table.mem_table));
4128
4129         PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
4130                         "Failed to upload DPM Bootup Levels!",
4131                         return -1);
4132
4133         PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
4134                         "Failed to upload DPM Max Levels!",
4135                         return -1);
4136         return 0;
4137 }
4138
4139 static int vega10_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level,
4140                                 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask)
4141 {
4142         struct phm_ppt_v2_information *table_info =
4143                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
4144
4145         if (table_info->vdd_dep_on_sclk->count > VEGA10_UMD_PSTATE_GFXCLK_LEVEL &&
4146                 table_info->vdd_dep_on_socclk->count > VEGA10_UMD_PSTATE_SOCCLK_LEVEL &&
4147                 table_info->vdd_dep_on_mclk->count > VEGA10_UMD_PSTATE_MCLK_LEVEL) {
4148                 *sclk_mask = VEGA10_UMD_PSTATE_GFXCLK_LEVEL;
4149                 *soc_mask = VEGA10_UMD_PSTATE_SOCCLK_LEVEL;
4150                 *mclk_mask = VEGA10_UMD_PSTATE_MCLK_LEVEL;
4151                 hwmgr->pstate_sclk = table_info->vdd_dep_on_sclk->entries[VEGA10_UMD_PSTATE_GFXCLK_LEVEL].clk;
4152                 hwmgr->pstate_mclk = table_info->vdd_dep_on_mclk->entries[VEGA10_UMD_PSTATE_MCLK_LEVEL].clk;
4153         }
4154
4155         if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
4156                 *sclk_mask = 0;
4157         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
4158                 *mclk_mask = 0;
4159         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
4160                 /* under vega10  pp one vf mode, the gfx clk dpm need be lower
4161                  * to level-4 due to the limited power
4162                  */
4163                 if (hwmgr->pp_one_vf)
4164                         *sclk_mask = 4;
4165                 else
4166                         *sclk_mask = table_info->vdd_dep_on_sclk->count - 1;
4167                 *soc_mask = table_info->vdd_dep_on_socclk->count - 1;
4168                 *mclk_mask = table_info->vdd_dep_on_mclk->count - 1;
4169         }
4170
4171         return 0;
4172 }
4173
4174 static void vega10_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
4175 {
4176         if (!hwmgr->not_vf)
4177                 return;
4178
4179         switch (mode) {
4180         case AMD_FAN_CTRL_NONE:
4181                 vega10_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
4182                 break;
4183         case AMD_FAN_CTRL_MANUAL:
4184                 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
4185                         vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
4186                 break;
4187         case AMD_FAN_CTRL_AUTO:
4188                 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
4189                         vega10_fan_ctrl_start_smc_fan_control(hwmgr);
4190                 break;
4191         default:
4192                 break;
4193         }
4194 }
4195
4196 static int vega10_force_clock_level(struct pp_hwmgr *hwmgr,
4197                 enum pp_clock_type type, uint32_t mask)
4198 {
4199         struct vega10_hwmgr *data = hwmgr->backend;
4200
4201         switch (type) {
4202         case PP_SCLK:
4203                 data->smc_state_table.gfx_boot_level = mask ? (ffs(mask) - 1) : 0;
4204                 data->smc_state_table.gfx_max_level = mask ? (fls(mask) - 1) : 0;
4205
4206                 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
4207                         "Failed to upload boot level to lowest!",
4208                         return -EINVAL);
4209
4210                 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
4211                         "Failed to upload dpm max level to highest!",
4212                         return -EINVAL);
4213                 break;
4214
4215         case PP_MCLK:
4216                 data->smc_state_table.mem_boot_level = mask ? (ffs(mask) - 1) : 0;
4217                 data->smc_state_table.mem_max_level = mask ? (fls(mask) - 1) : 0;
4218
4219                 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
4220                         "Failed to upload boot level to lowest!",
4221                         return -EINVAL);
4222
4223                 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
4224                         "Failed to upload dpm max level to highest!",
4225                         return -EINVAL);
4226
4227                 break;
4228
4229         case PP_SOCCLK:
4230                 data->smc_state_table.soc_boot_level = mask ? (ffs(mask) - 1) : 0;
4231                 data->smc_state_table.soc_max_level = mask ? (fls(mask) - 1) : 0;
4232
4233                 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
4234                         "Failed to upload boot level to lowest!",
4235                         return -EINVAL);
4236
4237                 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
4238                         "Failed to upload dpm max level to highest!",
4239                         return -EINVAL);
4240
4241                 break;
4242
4243         case PP_DCEFCLK:
4244                 pr_info("Setting DCEFCLK min/max dpm level is not supported!\n");
4245                 break;
4246
4247         case PP_PCIE:
4248         default:
4249                 break;
4250         }
4251
4252         return 0;
4253 }
4254
4255 static int vega10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
4256                                 enum amd_dpm_forced_level level)
4257 {
4258         int ret = 0;
4259         uint32_t sclk_mask = 0;
4260         uint32_t mclk_mask = 0;
4261         uint32_t soc_mask = 0;
4262
4263         if (hwmgr->pstate_sclk == 0)
4264                 vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
4265
4266         switch (level) {
4267         case AMD_DPM_FORCED_LEVEL_HIGH:
4268                 ret = vega10_force_dpm_highest(hwmgr);
4269                 break;
4270         case AMD_DPM_FORCED_LEVEL_LOW:
4271                 ret = vega10_force_dpm_lowest(hwmgr);
4272                 break;
4273         case AMD_DPM_FORCED_LEVEL_AUTO:
4274                 ret = vega10_unforce_dpm_levels(hwmgr);
4275                 break;
4276         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
4277         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
4278         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
4279         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
4280                 ret = vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
4281                 if (ret)
4282                         return ret;
4283                 vega10_force_clock_level(hwmgr, PP_SCLK, 1<<sclk_mask);
4284                 vega10_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask);
4285                 break;
4286         case AMD_DPM_FORCED_LEVEL_MANUAL:
4287         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
4288         default:
4289                 break;
4290         }
4291
4292         if (!hwmgr->not_vf)
4293                 return ret;
4294
4295         if (!ret) {
4296                 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
4297                         vega10_set_fan_control_mode(hwmgr, AMD_FAN_CTRL_NONE);
4298                 else if (level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
4299                         vega10_set_fan_control_mode(hwmgr, AMD_FAN_CTRL_AUTO);
4300         }
4301
4302         return ret;
4303 }
4304
4305 static uint32_t vega10_get_fan_control_mode(struct pp_hwmgr *hwmgr)
4306 {
4307         struct vega10_hwmgr *data = hwmgr->backend;
4308
4309         if (data->smu_features[GNLD_FAN_CONTROL].enabled == false)
4310                 return AMD_FAN_CTRL_MANUAL;
4311         else
4312                 return AMD_FAN_CTRL_AUTO;
4313 }
4314
4315 static int vega10_get_dal_power_level(struct pp_hwmgr *hwmgr,
4316                 struct amd_pp_simple_clock_info *info)
4317 {
4318         struct phm_ppt_v2_information *table_info =
4319                         (struct phm_ppt_v2_information *)hwmgr->pptable;
4320         struct phm_clock_and_voltage_limits *max_limits =
4321                         &table_info->max_clock_voltage_on_ac;
4322
4323         info->engine_max_clock = max_limits->sclk;
4324         info->memory_max_clock = max_limits->mclk;
4325
4326         return 0;
4327 }
4328
4329 static void vega10_get_sclks(struct pp_hwmgr *hwmgr,
4330                 struct pp_clock_levels_with_latency *clocks)
4331 {
4332         struct phm_ppt_v2_information *table_info =
4333                         (struct phm_ppt_v2_information *)hwmgr->pptable;
4334         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
4335                         table_info->vdd_dep_on_sclk;
4336         uint32_t i;
4337
4338         clocks->num_levels = 0;
4339         for (i = 0; i < dep_table->count; i++) {
4340                 if (dep_table->entries[i].clk) {
4341                         clocks->data[clocks->num_levels].clocks_in_khz =
4342                                         dep_table->entries[i].clk * 10;
4343                         clocks->num_levels++;
4344                 }
4345         }
4346
4347 }
4348
4349 static void vega10_get_memclocks(struct pp_hwmgr *hwmgr,
4350                 struct pp_clock_levels_with_latency *clocks)
4351 {
4352         struct phm_ppt_v2_information *table_info =
4353                         (struct phm_ppt_v2_information *)hwmgr->pptable;
4354         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
4355                         table_info->vdd_dep_on_mclk;
4356         struct vega10_hwmgr *data = hwmgr->backend;
4357         uint32_t j = 0;
4358         uint32_t i;
4359
4360         for (i = 0; i < dep_table->count; i++) {
4361                 if (dep_table->entries[i].clk) {
4362
4363                         clocks->data[j].clocks_in_khz =
4364                                                 dep_table->entries[i].clk * 10;
4365                         data->mclk_latency_table.entries[j].frequency =
4366                                                         dep_table->entries[i].clk;
4367                         clocks->data[j].latency_in_us =
4368                                 data->mclk_latency_table.entries[j].latency = 25;
4369                         j++;
4370                 }
4371         }
4372         clocks->num_levels = data->mclk_latency_table.count = j;
4373 }
4374
4375 static void vega10_get_dcefclocks(struct pp_hwmgr *hwmgr,
4376                 struct pp_clock_levels_with_latency *clocks)
4377 {
4378         struct phm_ppt_v2_information *table_info =
4379                         (struct phm_ppt_v2_information *)hwmgr->pptable;
4380         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
4381                         table_info->vdd_dep_on_dcefclk;
4382         uint32_t i;
4383
4384         for (i = 0; i < dep_table->count; i++) {
4385                 clocks->data[i].clocks_in_khz = dep_table->entries[i].clk * 10;
4386                 clocks->data[i].latency_in_us = 0;
4387                 clocks->num_levels++;
4388         }
4389 }
4390
4391 static void vega10_get_socclocks(struct pp_hwmgr *hwmgr,
4392                 struct pp_clock_levels_with_latency *clocks)
4393 {
4394         struct phm_ppt_v2_information *table_info =
4395                         (struct phm_ppt_v2_information *)hwmgr->pptable;
4396         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
4397                         table_info->vdd_dep_on_socclk;
4398         uint32_t i;
4399
4400         for (i = 0; i < dep_table->count; i++) {
4401                 clocks->data[i].clocks_in_khz = dep_table->entries[i].clk * 10;
4402                 clocks->data[i].latency_in_us = 0;
4403                 clocks->num_levels++;
4404         }
4405 }
4406
4407 static int vega10_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
4408                 enum amd_pp_clock_type type,
4409                 struct pp_clock_levels_with_latency *clocks)
4410 {
4411         switch (type) {
4412         case amd_pp_sys_clock:
4413                 vega10_get_sclks(hwmgr, clocks);
4414                 break;
4415         case amd_pp_mem_clock:
4416                 vega10_get_memclocks(hwmgr, clocks);
4417                 break;
4418         case amd_pp_dcef_clock:
4419                 vega10_get_dcefclocks(hwmgr, clocks);
4420                 break;
4421         case amd_pp_soc_clock:
4422                 vega10_get_socclocks(hwmgr, clocks);
4423                 break;
4424         default:
4425                 return -1;
4426         }
4427
4428         return 0;
4429 }
4430
4431 static int vega10_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
4432                 enum amd_pp_clock_type type,
4433                 struct pp_clock_levels_with_voltage *clocks)
4434 {
4435         struct phm_ppt_v2_information *table_info =
4436                         (struct phm_ppt_v2_information *)hwmgr->pptable;
4437         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table;
4438         uint32_t i;
4439
4440         switch (type) {
4441         case amd_pp_mem_clock:
4442                 dep_table = table_info->vdd_dep_on_mclk;
4443                 break;
4444         case amd_pp_dcef_clock:
4445                 dep_table = table_info->vdd_dep_on_dcefclk;
4446                 break;
4447         case amd_pp_disp_clock:
4448                 dep_table = table_info->vdd_dep_on_dispclk;
4449                 break;
4450         case amd_pp_pixel_clock:
4451                 dep_table = table_info->vdd_dep_on_pixclk;
4452                 break;
4453         case amd_pp_phy_clock:
4454                 dep_table = table_info->vdd_dep_on_phyclk;
4455                 break;
4456         default:
4457                 return -1;
4458         }
4459
4460         for (i = 0; i < dep_table->count; i++) {
4461                 clocks->data[i].clocks_in_khz = dep_table->entries[i].clk  * 10;
4462                 clocks->data[i].voltage_in_mv = (uint32_t)(table_info->vddc_lookup_table->
4463                                 entries[dep_table->entries[i].vddInd].us_vdd);
4464                 clocks->num_levels++;
4465         }
4466
4467         if (i < dep_table->count)
4468                 return -1;
4469
4470         return 0;
4471 }
4472
4473 static int vega10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
4474                                                         void *clock_range)
4475 {
4476         struct vega10_hwmgr *data = hwmgr->backend;
4477         struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_range;
4478         Watermarks_t *table = &(data->smc_state_table.water_marks_table);
4479
4480         if (!data->registry_data.disable_water_mark) {
4481                 smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges);
4482                 data->water_marks_bitmap = WaterMarksExist;
4483         }
4484
4485         return 0;
4486 }
4487
4488 static int vega10_get_ppfeature_status(struct pp_hwmgr *hwmgr, char *buf)
4489 {
4490         static const char *ppfeature_name[] = {
4491                                 "DPM_PREFETCHER",
4492                                 "GFXCLK_DPM",
4493                                 "UCLK_DPM",
4494                                 "SOCCLK_DPM",
4495                                 "UVD_DPM",
4496                                 "VCE_DPM",
4497                                 "ULV",
4498                                 "MP0CLK_DPM",
4499                                 "LINK_DPM",
4500                                 "DCEFCLK_DPM",
4501                                 "AVFS",
4502                                 "GFXCLK_DS",
4503                                 "SOCCLK_DS",
4504                                 "LCLK_DS",
4505                                 "PPT",
4506                                 "TDC",
4507                                 "THERMAL",
4508                                 "GFX_PER_CU_CG",
4509                                 "RM",
4510                                 "DCEFCLK_DS",
4511                                 "ACDC",
4512                                 "VR0HOT",
4513                                 "VR1HOT",
4514                                 "FW_CTF",
4515                                 "LED_DISPLAY",
4516                                 "FAN_CONTROL",
4517                                 "FAST_PPT",
4518                                 "DIDT",
4519                                 "ACG",
4520                                 "PCC_LIMIT"};
4521         static const char *output_title[] = {
4522                                 "FEATURES",
4523                                 "BITMASK",
4524                                 "ENABLEMENT"};
4525         uint64_t features_enabled;
4526         int i;
4527         int ret = 0;
4528         int size = 0;
4529
4530         ret = vega10_get_enabled_smc_features(hwmgr, &features_enabled);
4531         PP_ASSERT_WITH_CODE(!ret,
4532                         "[EnableAllSmuFeatures] Failed to get enabled smc features!",
4533                         return ret);
4534
4535         size += sprintf(buf + size, "Current ppfeatures: 0x%016llx\n", features_enabled);
4536         size += sprintf(buf + size, "%-19s %-22s %s\n",
4537                                 output_title[0],
4538                                 output_title[1],
4539                                 output_title[2]);
4540         for (i = 0; i < GNLD_FEATURES_MAX; i++) {
4541                 size += sprintf(buf + size, "%-19s 0x%016llx %6s\n",
4542                                         ppfeature_name[i],
4543                                         1ULL << i,
4544                                         (features_enabled & (1ULL << i)) ? "Y" : "N");
4545         }
4546
4547         return size;
4548 }
4549
4550 static int vega10_set_ppfeature_status(struct pp_hwmgr *hwmgr, uint64_t new_ppfeature_masks)
4551 {
4552         uint64_t features_enabled;
4553         uint64_t features_to_enable;
4554         uint64_t features_to_disable;
4555         int ret = 0;
4556
4557         if (new_ppfeature_masks >= (1ULL << GNLD_FEATURES_MAX))
4558                 return -EINVAL;
4559
4560         ret = vega10_get_enabled_smc_features(hwmgr, &features_enabled);
4561         if (ret)
4562                 return ret;
4563
4564         features_to_disable =
4565                 features_enabled & ~new_ppfeature_masks;
4566         features_to_enable =
4567                 ~features_enabled & new_ppfeature_masks;
4568
4569         pr_debug("features_to_disable 0x%llx\n", features_to_disable);
4570         pr_debug("features_to_enable 0x%llx\n", features_to_enable);
4571
4572         if (features_to_disable) {
4573                 ret = vega10_enable_smc_features(hwmgr, false, features_to_disable);
4574                 if (ret)
4575                         return ret;
4576         }
4577
4578         if (features_to_enable) {
4579                 ret = vega10_enable_smc_features(hwmgr, true, features_to_enable);
4580                 if (ret)
4581                         return ret;
4582         }
4583
4584         return 0;
4585 }
4586
4587 static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
4588                 enum pp_clock_type type, char *buf)
4589 {
4590         struct vega10_hwmgr *data = hwmgr->backend;
4591         struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
4592         struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
4593         struct vega10_single_dpm_table *soc_table = &(data->dpm_table.soc_table);
4594         struct vega10_single_dpm_table *dcef_table = &(data->dpm_table.dcef_table);
4595         struct vega10_pcie_table *pcie_table = &(data->dpm_table.pcie_table);
4596         struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep = NULL;
4597
4598         int i, now, size = 0, count = 0;
4599
4600         switch (type) {
4601         case PP_SCLK:
4602                 if (data->registry_data.sclk_dpm_key_disabled)
4603                         break;
4604
4605                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentGfxclkIndex, &now);
4606
4607                 if (hwmgr->pp_one_vf &&
4608                     (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK))
4609                         count = 5;
4610                 else
4611                         count = sclk_table->count;
4612                 for (i = 0; i < count; i++)
4613                         size += sprintf(buf + size, "%d: %uMhz %s\n",
4614                                         i, sclk_table->dpm_levels[i].value / 100,
4615                                         (i == now) ? "*" : "");
4616                 break;
4617         case PP_MCLK:
4618                 if (data->registry_data.mclk_dpm_key_disabled)
4619                         break;
4620
4621                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex, &now);
4622
4623                 for (i = 0; i < mclk_table->count; i++)
4624                         size += sprintf(buf + size, "%d: %uMhz %s\n",
4625                                         i, mclk_table->dpm_levels[i].value / 100,
4626                                         (i == now) ? "*" : "");
4627                 break;
4628         case PP_SOCCLK:
4629                 if (data->registry_data.socclk_dpm_key_disabled)
4630                         break;
4631
4632                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentSocclkIndex, &now);
4633
4634                 for (i = 0; i < soc_table->count; i++)
4635                         size += sprintf(buf + size, "%d: %uMhz %s\n",
4636                                         i, soc_table->dpm_levels[i].value / 100,
4637                                         (i == now) ? "*" : "");
4638                 break;
4639         case PP_DCEFCLK:
4640                 if (data->registry_data.dcefclk_dpm_key_disabled)
4641                         break;
4642
4643                 smum_send_msg_to_smc_with_parameter(hwmgr,
4644                                 PPSMC_MSG_GetClockFreqMHz, CLK_DCEFCLK, &now);
4645
4646                 for (i = 0; i < dcef_table->count; i++)
4647                         size += sprintf(buf + size, "%d: %uMhz %s\n",
4648                                         i, dcef_table->dpm_levels[i].value / 100,
4649                                         (dcef_table->dpm_levels[i].value / 100 == now) ?
4650                                         "*" : "");
4651                 break;
4652         case PP_PCIE:
4653                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentLinkIndex, &now);
4654
4655                 for (i = 0; i < pcie_table->count; i++)
4656                         size += sprintf(buf + size, "%d: %s %s\n", i,
4657                                         (pcie_table->pcie_gen[i] == 0) ? "2.5GT/s, x1" :
4658                                         (pcie_table->pcie_gen[i] == 1) ? "5.0GT/s, x16" :
4659                                         (pcie_table->pcie_gen[i] == 2) ? "8.0GT/s, x16" : "",
4660                                         (i == now) ? "*" : "");
4661                 break;
4662         case OD_SCLK:
4663                 if (hwmgr->od_enabled) {
4664                         size = sprintf(buf, "%s:\n", "OD_SCLK");
4665                         podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_sclk;
4666                         for (i = 0; i < podn_vdd_dep->count; i++)
4667                                 size += sprintf(buf + size, "%d: %10uMhz %10umV\n",
4668                                         i, podn_vdd_dep->entries[i].clk / 100,
4669                                                 podn_vdd_dep->entries[i].vddc);
4670                 }
4671                 break;
4672         case OD_MCLK:
4673                 if (hwmgr->od_enabled) {
4674                         size = sprintf(buf, "%s:\n", "OD_MCLK");
4675                         podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_mclk;
4676                         for (i = 0; i < podn_vdd_dep->count; i++)
4677                                 size += sprintf(buf + size, "%d: %10uMhz %10umV\n",
4678                                         i, podn_vdd_dep->entries[i].clk/100,
4679                                                 podn_vdd_dep->entries[i].vddc);
4680                 }
4681                 break;
4682         case OD_RANGE:
4683                 if (hwmgr->od_enabled) {
4684                         size = sprintf(buf, "%s:\n", "OD_RANGE");
4685                         size += sprintf(buf + size, "SCLK: %7uMHz %10uMHz\n",
4686                                 data->golden_dpm_table.gfx_table.dpm_levels[0].value/100,
4687                                 hwmgr->platform_descriptor.overdriveLimit.engineClock/100);
4688                         size += sprintf(buf + size, "MCLK: %7uMHz %10uMHz\n",
4689                                 data->golden_dpm_table.mem_table.dpm_levels[0].value/100,
4690                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock/100);
4691                         size += sprintf(buf + size, "VDDC: %7umV %11umV\n",
4692                                 data->odn_dpm_table.min_vddc,
4693                                 data->odn_dpm_table.max_vddc);
4694                 }
4695                 break;
4696         default:
4697                 break;
4698         }
4699         return size;
4700 }
4701
4702 static int vega10_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
4703 {
4704         struct vega10_hwmgr *data = hwmgr->backend;
4705         Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table);
4706         int result = 0;
4707
4708         if ((data->water_marks_bitmap & WaterMarksExist) &&
4709                         !(data->water_marks_bitmap & WaterMarksLoaded)) {
4710                 result = smum_smc_table_manager(hwmgr, (uint8_t *)wm_table, WMTABLE, false);
4711                 PP_ASSERT_WITH_CODE(result, "Failed to update WMTABLE!", return -EINVAL);
4712                 data->water_marks_bitmap |= WaterMarksLoaded;
4713         }
4714
4715         if (data->water_marks_bitmap & WaterMarksLoaded) {
4716                 smum_send_msg_to_smc_with_parameter(hwmgr,
4717                         PPSMC_MSG_NumOfDisplays, hwmgr->display_config->num_display,
4718                         NULL);
4719         }
4720
4721         return result;
4722 }
4723
4724 static int vega10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
4725 {
4726         struct vega10_hwmgr *data = hwmgr->backend;
4727
4728         if (data->smu_features[GNLD_DPM_UVD].supported) {
4729                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
4730                                 enable,
4731                                 data->smu_features[GNLD_DPM_UVD].smu_feature_bitmap),
4732                                 "Attempt to Enable/Disable DPM UVD Failed!",
4733                                 return -1);
4734                 data->smu_features[GNLD_DPM_UVD].enabled = enable;
4735         }
4736         return 0;
4737 }
4738
4739 static void vega10_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate)
4740 {
4741         struct vega10_hwmgr *data = hwmgr->backend;
4742
4743         data->vce_power_gated = bgate;
4744         vega10_enable_disable_vce_dpm(hwmgr, !bgate);
4745 }
4746
4747 static void vega10_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
4748 {
4749         struct vega10_hwmgr *data = hwmgr->backend;
4750
4751         data->uvd_power_gated = bgate;
4752         vega10_enable_disable_uvd_dpm(hwmgr, !bgate);
4753 }
4754
4755 static inline bool vega10_are_power_levels_equal(
4756                                 const struct vega10_performance_level *pl1,
4757                                 const struct vega10_performance_level *pl2)
4758 {
4759         return ((pl1->soc_clock == pl2->soc_clock) &&
4760                         (pl1->gfx_clock == pl2->gfx_clock) &&
4761                         (pl1->mem_clock == pl2->mem_clock));
4762 }
4763
4764 static int vega10_check_states_equal(struct pp_hwmgr *hwmgr,
4765                                 const struct pp_hw_power_state *pstate1,
4766                         const struct pp_hw_power_state *pstate2, bool *equal)
4767 {
4768         const struct vega10_power_state *psa;
4769         const struct vega10_power_state *psb;
4770         int i;
4771
4772         if (pstate1 == NULL || pstate2 == NULL || equal == NULL)
4773                 return -EINVAL;
4774
4775         psa = cast_const_phw_vega10_power_state(pstate1);
4776         psb = cast_const_phw_vega10_power_state(pstate2);
4777         /* If the two states don't even have the same number of performance levels they cannot be the same state. */
4778         if (psa->performance_level_count != psb->performance_level_count) {
4779                 *equal = false;
4780                 return 0;
4781         }
4782
4783         for (i = 0; i < psa->performance_level_count; i++) {
4784                 if (!vega10_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) {
4785                         /* If we have found even one performance level pair that is different the states are different. */
4786                         *equal = false;
4787                         return 0;
4788                 }
4789         }
4790
4791         /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
4792         *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk));
4793         *equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk));
4794         *equal &= (psa->sclk_threshold == psb->sclk_threshold);
4795
4796         return 0;
4797 }
4798
4799 static bool
4800 vega10_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
4801 {
4802         struct vega10_hwmgr *data = hwmgr->backend;
4803         bool is_update_required = false;
4804
4805         if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
4806                 is_update_required = true;
4807
4808         if (PP_CAP(PHM_PlatformCaps_SclkDeepSleep)) {
4809                 if (data->display_timing.min_clock_in_sr != hwmgr->display_config->min_core_set_clock_in_sr)
4810                         is_update_required = true;
4811         }
4812
4813         return is_update_required;
4814 }
4815
4816 static int vega10_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
4817 {
4818         int tmp_result, result = 0;
4819
4820         if (!hwmgr->not_vf)
4821                 return 0;
4822
4823         if (PP_CAP(PHM_PlatformCaps_ThermalController))
4824                 vega10_disable_thermal_protection(hwmgr);
4825
4826         tmp_result = vega10_disable_power_containment(hwmgr);
4827         PP_ASSERT_WITH_CODE((tmp_result == 0),
4828                         "Failed to disable power containment!", result = tmp_result);
4829
4830         tmp_result = vega10_disable_didt_config(hwmgr);
4831         PP_ASSERT_WITH_CODE((tmp_result == 0),
4832                         "Failed to disable didt config!", result = tmp_result);
4833
4834         tmp_result = vega10_avfs_enable(hwmgr, false);
4835         PP_ASSERT_WITH_CODE((tmp_result == 0),
4836                         "Failed to disable AVFS!", result = tmp_result);
4837
4838         tmp_result = vega10_stop_dpm(hwmgr, SMC_DPM_FEATURES);
4839         PP_ASSERT_WITH_CODE((tmp_result == 0),
4840                         "Failed to stop DPM!", result = tmp_result);
4841
4842         tmp_result = vega10_disable_deep_sleep_master_switch(hwmgr);
4843         PP_ASSERT_WITH_CODE((tmp_result == 0),
4844                         "Failed to disable deep sleep!", result = tmp_result);
4845
4846         tmp_result = vega10_disable_ulv(hwmgr);
4847         PP_ASSERT_WITH_CODE((tmp_result == 0),
4848                         "Failed to disable ulv!", result = tmp_result);
4849
4850         tmp_result =  vega10_acg_disable(hwmgr);
4851         PP_ASSERT_WITH_CODE((tmp_result == 0),
4852                         "Failed to disable acg!", result = tmp_result);
4853
4854         vega10_enable_disable_PCC_limit_feature(hwmgr, false);
4855         return result;
4856 }
4857
4858 static int vega10_power_off_asic(struct pp_hwmgr *hwmgr)
4859 {
4860         struct vega10_hwmgr *data = hwmgr->backend;
4861         int result;
4862
4863         result = vega10_disable_dpm_tasks(hwmgr);
4864         PP_ASSERT_WITH_CODE((0 == result),
4865                         "[disable_dpm_tasks] Failed to disable DPM!",
4866                         );
4867         data->water_marks_bitmap &= ~(WaterMarksLoaded);
4868
4869         return result;
4870 }
4871
4872 static int vega10_get_sclk_od(struct pp_hwmgr *hwmgr)
4873 {
4874         struct vega10_hwmgr *data = hwmgr->backend;
4875         struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
4876         struct vega10_single_dpm_table *golden_sclk_table =
4877                         &(data->golden_dpm_table.gfx_table);
4878         int value = sclk_table->dpm_levels[sclk_table->count - 1].value;
4879         int golden_value = golden_sclk_table->dpm_levels
4880                         [golden_sclk_table->count - 1].value;
4881
4882         value -= golden_value;
4883         value = DIV_ROUND_UP(value * 100, golden_value);
4884
4885         return value;
4886 }
4887
4888 static int vega10_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
4889 {
4890         struct vega10_hwmgr *data = hwmgr->backend;
4891         struct vega10_single_dpm_table *golden_sclk_table =
4892                         &(data->golden_dpm_table.gfx_table);
4893         struct pp_power_state *ps;
4894         struct vega10_power_state *vega10_ps;
4895
4896         ps = hwmgr->request_ps;
4897
4898         if (ps == NULL)
4899                 return -EINVAL;
4900
4901         vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
4902
4903         vega10_ps->performance_levels
4904         [vega10_ps->performance_level_count - 1].gfx_clock =
4905                         golden_sclk_table->dpm_levels
4906                         [golden_sclk_table->count - 1].value *
4907                         value / 100 +
4908                         golden_sclk_table->dpm_levels
4909                         [golden_sclk_table->count - 1].value;
4910
4911         if (vega10_ps->performance_levels
4912                         [vega10_ps->performance_level_count - 1].gfx_clock >
4913                         hwmgr->platform_descriptor.overdriveLimit.engineClock) {
4914                 vega10_ps->performance_levels
4915                 [vega10_ps->performance_level_count - 1].gfx_clock =
4916                                 hwmgr->platform_descriptor.overdriveLimit.engineClock;
4917                 pr_warn("max sclk supported by vbios is %d\n",
4918                                 hwmgr->platform_descriptor.overdriveLimit.engineClock);
4919         }
4920         return 0;
4921 }
4922
4923 static int vega10_get_mclk_od(struct pp_hwmgr *hwmgr)
4924 {
4925         struct vega10_hwmgr *data = hwmgr->backend;
4926         struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
4927         struct vega10_single_dpm_table *golden_mclk_table =
4928                         &(data->golden_dpm_table.mem_table);
4929         int value = mclk_table->dpm_levels[mclk_table->count - 1].value;
4930         int golden_value = golden_mclk_table->dpm_levels
4931                         [golden_mclk_table->count - 1].value;
4932
4933         value -= golden_value;
4934         value = DIV_ROUND_UP(value * 100, golden_value);
4935
4936         return value;
4937 }
4938
4939 static int vega10_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
4940 {
4941         struct vega10_hwmgr *data = hwmgr->backend;
4942         struct vega10_single_dpm_table *golden_mclk_table =
4943                         &(data->golden_dpm_table.mem_table);
4944         struct pp_power_state  *ps;
4945         struct vega10_power_state  *vega10_ps;
4946
4947         ps = hwmgr->request_ps;
4948
4949         if (ps == NULL)
4950                 return -EINVAL;
4951
4952         vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
4953
4954         vega10_ps->performance_levels
4955         [vega10_ps->performance_level_count - 1].mem_clock =
4956                         golden_mclk_table->dpm_levels
4957                         [golden_mclk_table->count - 1].value *
4958                         value / 100 +
4959                         golden_mclk_table->dpm_levels
4960                         [golden_mclk_table->count - 1].value;
4961
4962         if (vega10_ps->performance_levels
4963                         [vega10_ps->performance_level_count - 1].mem_clock >
4964                         hwmgr->platform_descriptor.overdriveLimit.memoryClock) {
4965                 vega10_ps->performance_levels
4966                 [vega10_ps->performance_level_count - 1].mem_clock =
4967                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock;
4968                 pr_warn("max mclk supported by vbios is %d\n",
4969                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock);
4970         }
4971
4972         return 0;
4973 }
4974
4975 static int vega10_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
4976                                         uint32_t virtual_addr_low,
4977                                         uint32_t virtual_addr_hi,
4978                                         uint32_t mc_addr_low,
4979                                         uint32_t mc_addr_hi,
4980                                         uint32_t size)
4981 {
4982         smum_send_msg_to_smc_with_parameter(hwmgr,
4983                                         PPSMC_MSG_SetSystemVirtualDramAddrHigh,
4984                                         virtual_addr_hi,
4985                                         NULL);
4986         smum_send_msg_to_smc_with_parameter(hwmgr,
4987                                         PPSMC_MSG_SetSystemVirtualDramAddrLow,
4988                                         virtual_addr_low,
4989                                         NULL);
4990         smum_send_msg_to_smc_with_parameter(hwmgr,
4991                                         PPSMC_MSG_DramLogSetDramAddrHigh,
4992                                         mc_addr_hi,
4993                                         NULL);
4994
4995         smum_send_msg_to_smc_with_parameter(hwmgr,
4996                                         PPSMC_MSG_DramLogSetDramAddrLow,
4997                                         mc_addr_low,
4998                                         NULL);
4999
5000         smum_send_msg_to_smc_with_parameter(hwmgr,
5001                                         PPSMC_MSG_DramLogSetDramSize,
5002                                         size,
5003                                         NULL);
5004         return 0;
5005 }
5006
5007 static int vega10_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
5008                 struct PP_TemperatureRange *thermal_data)
5009 {
5010         struct vega10_hwmgr *data = hwmgr->backend;
5011         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
5012
5013         memcpy(thermal_data, &SMU7ThermalWithDelayPolicy[0], sizeof(struct PP_TemperatureRange));
5014
5015         thermal_data->max = pp_table->TedgeLimit *
5016                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
5017         thermal_data->edge_emergency_max = (pp_table->TedgeLimit + CTF_OFFSET_EDGE) *
5018                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
5019         thermal_data->hotspot_crit_max = pp_table->ThotspotLimit *
5020                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
5021         thermal_data->hotspot_emergency_max = (pp_table->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
5022                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
5023         thermal_data->mem_crit_max = pp_table->ThbmLimit *
5024                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
5025         thermal_data->mem_emergency_max = (pp_table->ThbmLimit + CTF_OFFSET_HBM)*
5026                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
5027
5028         return 0;
5029 }
5030
5031 static int vega10_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
5032 {
5033         struct vega10_hwmgr *data = hwmgr->backend;
5034         uint32_t i, size = 0;
5035         static const uint8_t profile_mode_setting[6][4] = {{70, 60, 0, 0,},
5036                                                 {70, 60, 1, 3,},
5037                                                 {90, 60, 0, 0,},
5038                                                 {70, 60, 0, 0,},
5039                                                 {70, 90, 0, 0,},
5040                                                 {30, 60, 0, 6,},
5041                                                 };
5042         static const char *profile_name[7] = {"BOOTUP_DEFAULT",
5043                                         "3D_FULL_SCREEN",
5044                                         "POWER_SAVING",
5045                                         "VIDEO",
5046                                         "VR",
5047                                         "COMPUTE",
5048                                         "CUSTOM"};
5049         static const char *title[6] = {"NUM",
5050                         "MODE_NAME",
5051                         "BUSY_SET_POINT",
5052                         "FPS",
5053                         "USE_RLC_BUSY",
5054                         "MIN_ACTIVE_LEVEL"};
5055
5056         if (!buf)
5057                 return -EINVAL;
5058
5059         size += sprintf(buf + size, "%s %16s %s %s %s %s\n",title[0],
5060                         title[1], title[2], title[3], title[4], title[5]);
5061
5062         for (i = 0; i < PP_SMC_POWER_PROFILE_CUSTOM; i++)
5063                 size += sprintf(buf + size, "%3d %14s%s: %14d %3d %10d %14d\n",
5064                         i, profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ",
5065                         profile_mode_setting[i][0], profile_mode_setting[i][1],
5066                         profile_mode_setting[i][2], profile_mode_setting[i][3]);
5067         size += sprintf(buf + size, "%3d %14s%s: %14d %3d %10d %14d\n", i,
5068                         profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ",
5069                         data->custom_profile_mode[0], data->custom_profile_mode[1],
5070                         data->custom_profile_mode[2], data->custom_profile_mode[3]);
5071         return size;
5072 }
5073
5074 static int vega10_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)
5075 {
5076         struct vega10_hwmgr *data = hwmgr->backend;
5077         uint8_t busy_set_point;
5078         uint8_t FPS;
5079         uint8_t use_rlc_busy;
5080         uint8_t min_active_level;
5081         uint32_t power_profile_mode = input[size];
5082
5083         if (power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
5084                 if (size != 0 && size != 4)
5085                         return -EINVAL;
5086
5087                 /* If size = 0 and the CUSTOM profile has been set already
5088                  * then just apply the profile. The copy stored in the hwmgr
5089                  * is zeroed out on init
5090                  */
5091                 if (size == 0) {
5092                         if (data->custom_profile_mode[0] != 0)
5093                                 goto out;
5094                         else
5095                                 return -EINVAL;
5096                 }
5097
5098                 data->custom_profile_mode[0] = busy_set_point = input[0];
5099                 data->custom_profile_mode[1] = FPS = input[1];
5100                 data->custom_profile_mode[2] = use_rlc_busy = input[2];
5101                 data->custom_profile_mode[3] = min_active_level = input[3];
5102                 smum_send_msg_to_smc_with_parameter(hwmgr,
5103                                         PPSMC_MSG_SetCustomGfxDpmParameters,
5104                                         busy_set_point | FPS<<8 |
5105                                         use_rlc_busy << 16 | min_active_level<<24,
5106                                         NULL);
5107         }
5108
5109 out:
5110         smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask,
5111                                                 1 << power_profile_mode,
5112                                                 NULL);
5113         hwmgr->power_profile_mode = power_profile_mode;
5114
5115         return 0;
5116 }
5117
5118
5119 static bool vega10_check_clk_voltage_valid(struct pp_hwmgr *hwmgr,
5120                                         enum PP_OD_DPM_TABLE_COMMAND type,
5121                                         uint32_t clk,
5122                                         uint32_t voltage)
5123 {
5124         struct vega10_hwmgr *data = hwmgr->backend;
5125         struct vega10_odn_dpm_table *odn_table = &(data->odn_dpm_table);
5126         struct vega10_single_dpm_table *golden_table;
5127
5128         if (voltage < odn_table->min_vddc || voltage > odn_table->max_vddc) {
5129                 pr_info("OD voltage is out of range [%d - %d] mV\n", odn_table->min_vddc, odn_table->max_vddc);
5130                 return false;
5131         }
5132
5133         if (type == PP_OD_EDIT_SCLK_VDDC_TABLE) {
5134                 golden_table = &(data->golden_dpm_table.gfx_table);
5135                 if (golden_table->dpm_levels[0].value > clk ||
5136                         hwmgr->platform_descriptor.overdriveLimit.engineClock < clk) {
5137                         pr_info("OD engine clock is out of range [%d - %d] MHz\n",
5138                                 golden_table->dpm_levels[0].value/100,
5139                                 hwmgr->platform_descriptor.overdriveLimit.engineClock/100);
5140                         return false;
5141                 }
5142         } else if (type == PP_OD_EDIT_MCLK_VDDC_TABLE) {
5143                 golden_table = &(data->golden_dpm_table.mem_table);
5144                 if (golden_table->dpm_levels[0].value > clk ||
5145                         hwmgr->platform_descriptor.overdriveLimit.memoryClock < clk) {
5146                         pr_info("OD memory clock is out of range [%d - %d] MHz\n",
5147                                 golden_table->dpm_levels[0].value/100,
5148                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock/100);
5149                         return false;
5150                 }
5151         } else {
5152                 return false;
5153         }
5154
5155         return true;
5156 }
5157
5158 static void vega10_odn_update_power_state(struct pp_hwmgr *hwmgr)
5159 {
5160         struct vega10_hwmgr *data = hwmgr->backend;
5161         struct pp_power_state *ps = hwmgr->request_ps;
5162         struct vega10_power_state *vega10_ps;
5163         struct vega10_single_dpm_table *gfx_dpm_table =
5164                 &data->dpm_table.gfx_table;
5165         struct vega10_single_dpm_table *soc_dpm_table =
5166                 &data->dpm_table.soc_table;
5167         struct vega10_single_dpm_table *mem_dpm_table =
5168                 &data->dpm_table.mem_table;
5169         int max_level;
5170
5171         if (!ps)
5172                 return;
5173
5174         vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
5175         max_level = vega10_ps->performance_level_count - 1;
5176
5177         if (vega10_ps->performance_levels[max_level].gfx_clock !=
5178             gfx_dpm_table->dpm_levels[gfx_dpm_table->count - 1].value)
5179                 vega10_ps->performance_levels[max_level].gfx_clock =
5180                         gfx_dpm_table->dpm_levels[gfx_dpm_table->count - 1].value;
5181
5182         if (vega10_ps->performance_levels[max_level].soc_clock !=
5183             soc_dpm_table->dpm_levels[soc_dpm_table->count - 1].value)
5184                 vega10_ps->performance_levels[max_level].soc_clock =
5185                         soc_dpm_table->dpm_levels[soc_dpm_table->count - 1].value;
5186
5187         if (vega10_ps->performance_levels[max_level].mem_clock !=
5188             mem_dpm_table->dpm_levels[mem_dpm_table->count - 1].value)
5189                 vega10_ps->performance_levels[max_level].mem_clock =
5190                         mem_dpm_table->dpm_levels[mem_dpm_table->count - 1].value;
5191
5192         if (!hwmgr->ps)
5193                 return;
5194
5195         ps = (struct pp_power_state *)((unsigned long)(hwmgr->ps) + hwmgr->ps_size * (hwmgr->num_ps - 1));
5196         vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
5197         max_level = vega10_ps->performance_level_count - 1;
5198
5199         if (vega10_ps->performance_levels[max_level].gfx_clock !=
5200             gfx_dpm_table->dpm_levels[gfx_dpm_table->count - 1].value)
5201                 vega10_ps->performance_levels[max_level].gfx_clock =
5202                         gfx_dpm_table->dpm_levels[gfx_dpm_table->count - 1].value;
5203
5204         if (vega10_ps->performance_levels[max_level].soc_clock !=
5205             soc_dpm_table->dpm_levels[soc_dpm_table->count - 1].value)
5206                 vega10_ps->performance_levels[max_level].soc_clock =
5207                         soc_dpm_table->dpm_levels[soc_dpm_table->count - 1].value;
5208
5209         if (vega10_ps->performance_levels[max_level].mem_clock !=
5210             mem_dpm_table->dpm_levels[mem_dpm_table->count - 1].value)
5211                 vega10_ps->performance_levels[max_level].mem_clock =
5212                         mem_dpm_table->dpm_levels[mem_dpm_table->count - 1].value;
5213 }
5214
5215 static void vega10_odn_update_soc_table(struct pp_hwmgr *hwmgr,
5216                                                 enum PP_OD_DPM_TABLE_COMMAND type)
5217 {
5218         struct vega10_hwmgr *data = hwmgr->backend;
5219         struct phm_ppt_v2_information *table_info = hwmgr->pptable;
5220         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table = table_info->vdd_dep_on_socclk;
5221         struct vega10_single_dpm_table *dpm_table = &data->golden_dpm_table.mem_table;
5222
5223         struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep_on_socclk =
5224                                                         &data->odn_dpm_table.vdd_dep_on_socclk;
5225         struct vega10_odn_vddc_lookup_table *od_vddc_lookup_table = &data->odn_dpm_table.vddc_lookup_table;
5226
5227         struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep;
5228         uint8_t i, j;
5229
5230         if (type == PP_OD_EDIT_SCLK_VDDC_TABLE) {
5231                 podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_sclk;
5232                 for (i = 0; i < podn_vdd_dep->count; i++)
5233                         od_vddc_lookup_table->entries[i].us_vdd = podn_vdd_dep->entries[i].vddc;
5234         } else if (type == PP_OD_EDIT_MCLK_VDDC_TABLE) {
5235                 podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_mclk;
5236                 for (i = 0; i < dpm_table->count; i++) {
5237                         for (j = 0; j < od_vddc_lookup_table->count; j++) {
5238                                 if (od_vddc_lookup_table->entries[j].us_vdd >
5239                                         podn_vdd_dep->entries[i].vddc)
5240                                         break;
5241                         }
5242                         if (j == od_vddc_lookup_table->count) {
5243                                 j = od_vddc_lookup_table->count - 1;
5244                                 od_vddc_lookup_table->entries[j].us_vdd =
5245                                         podn_vdd_dep->entries[i].vddc;
5246                                 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC;
5247                         }
5248                         podn_vdd_dep->entries[i].vddInd = j;
5249                 }
5250                 dpm_table = &data->dpm_table.soc_table;
5251                 for (i = 0; i < dep_table->count; i++) {
5252                         if (dep_table->entries[i].vddInd == podn_vdd_dep->entries[podn_vdd_dep->count-1].vddInd &&
5253                                         dep_table->entries[i].clk < podn_vdd_dep->entries[podn_vdd_dep->count-1].clk) {
5254                                 data->need_update_dpm_table |= DPMTABLE_UPDATE_SOCCLK;
5255                                 for (; (i < dep_table->count) &&
5256                                        (dep_table->entries[i].clk < podn_vdd_dep->entries[podn_vdd_dep->count - 1].clk); i++) {
5257                                         podn_vdd_dep_on_socclk->entries[i].clk = podn_vdd_dep->entries[podn_vdd_dep->count-1].clk;
5258                                         dpm_table->dpm_levels[i].value = podn_vdd_dep_on_socclk->entries[i].clk;
5259                                 }
5260                                 break;
5261                         } else {
5262                                 dpm_table->dpm_levels[i].value = dep_table->entries[i].clk;
5263                                 podn_vdd_dep_on_socclk->entries[i].vddc = dep_table->entries[i].vddc;
5264                                 podn_vdd_dep_on_socclk->entries[i].vddInd = dep_table->entries[i].vddInd;
5265                                 podn_vdd_dep_on_socclk->entries[i].clk = dep_table->entries[i].clk;
5266                         }
5267                 }
5268                 if (podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].clk <
5269                                         podn_vdd_dep->entries[podn_vdd_dep->count - 1].clk) {
5270                         data->need_update_dpm_table |= DPMTABLE_UPDATE_SOCCLK;
5271                         podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].clk =
5272                                 podn_vdd_dep->entries[podn_vdd_dep->count - 1].clk;
5273                         dpm_table->dpm_levels[podn_vdd_dep_on_socclk->count - 1].value =
5274                                 podn_vdd_dep->entries[podn_vdd_dep->count - 1].clk;
5275                 }
5276                 if (podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].vddInd <
5277                                         podn_vdd_dep->entries[podn_vdd_dep->count - 1].vddInd) {
5278                         data->need_update_dpm_table |= DPMTABLE_UPDATE_SOCCLK;
5279                         podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].vddInd =
5280                                 podn_vdd_dep->entries[podn_vdd_dep->count - 1].vddInd;
5281                 }
5282         }
5283         vega10_odn_update_power_state(hwmgr);
5284 }
5285
5286 static int vega10_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
5287                                         enum PP_OD_DPM_TABLE_COMMAND type,
5288                                         long *input, uint32_t size)
5289 {
5290         struct vega10_hwmgr *data = hwmgr->backend;
5291         struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep_table;
5292         struct vega10_single_dpm_table *dpm_table;
5293
5294         uint32_t input_clk;
5295         uint32_t input_vol;
5296         uint32_t input_level;
5297         uint32_t i;
5298
5299         PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage",
5300                                 return -EINVAL);
5301
5302         if (!hwmgr->od_enabled) {
5303                 pr_info("OverDrive feature not enabled\n");
5304                 return -EINVAL;
5305         }
5306
5307         if (PP_OD_EDIT_SCLK_VDDC_TABLE == type) {
5308                 dpm_table = &data->dpm_table.gfx_table;
5309                 podn_vdd_dep_table = &data->odn_dpm_table.vdd_dep_on_sclk;
5310                 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
5311         } else if (PP_OD_EDIT_MCLK_VDDC_TABLE == type) {
5312                 dpm_table = &data->dpm_table.mem_table;
5313                 podn_vdd_dep_table = &data->odn_dpm_table.vdd_dep_on_mclk;
5314                 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
5315         } else if (PP_OD_RESTORE_DEFAULT_TABLE == type) {
5316                 memcpy(&(data->dpm_table), &(data->golden_dpm_table), sizeof(struct vega10_dpm_table));
5317                 vega10_odn_initial_default_setting(hwmgr);
5318                 vega10_odn_update_power_state(hwmgr);
5319                 /* force to update all clock tables */
5320                 data->need_update_dpm_table = DPMTABLE_UPDATE_SCLK |
5321                                               DPMTABLE_UPDATE_MCLK |
5322                                               DPMTABLE_UPDATE_SOCCLK;
5323                 return 0;
5324         } else if (PP_OD_COMMIT_DPM_TABLE == type) {
5325                 vega10_check_dpm_table_updated(hwmgr);
5326                 return 0;
5327         } else {
5328                 return -EINVAL;
5329         }
5330
5331         for (i = 0; i < size; i += 3) {
5332                 if (i + 3 > size || input[i] >= podn_vdd_dep_table->count) {
5333                         pr_info("invalid clock voltage input\n");
5334                         return 0;
5335                 }
5336                 input_level = input[i];
5337                 input_clk = input[i+1] * 100;
5338                 input_vol = input[i+2];
5339
5340                 if (vega10_check_clk_voltage_valid(hwmgr, type, input_clk, input_vol)) {
5341                         dpm_table->dpm_levels[input_level].value = input_clk;
5342                         podn_vdd_dep_table->entries[input_level].clk = input_clk;
5343                         podn_vdd_dep_table->entries[input_level].vddc = input_vol;
5344                 } else {
5345                         return -EINVAL;
5346                 }
5347         }
5348         vega10_odn_update_soc_table(hwmgr, type);
5349         return 0;
5350 }
5351
5352 static int vega10_set_mp1_state(struct pp_hwmgr *hwmgr,
5353                                 enum pp_mp1_state mp1_state)
5354 {
5355         uint16_t msg;
5356         int ret;
5357
5358         switch (mp1_state) {
5359         case PP_MP1_STATE_UNLOAD:
5360                 msg = PPSMC_MSG_PrepareMp1ForUnload;
5361                 break;
5362         case PP_MP1_STATE_SHUTDOWN:
5363         case PP_MP1_STATE_RESET:
5364         case PP_MP1_STATE_NONE:
5365         default:
5366                 return 0;
5367         }
5368
5369         PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr, msg, NULL)) == 0,
5370                             "[PrepareMp1] Failed!",
5371                             return ret);
5372
5373         return 0;
5374 }
5375
5376 static int vega10_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
5377                                 PHM_PerformanceLevelDesignation designation, uint32_t index,
5378                                 PHM_PerformanceLevel *level)
5379 {
5380         const struct vega10_power_state *ps;
5381         uint32_t i;
5382
5383         if (level == NULL || hwmgr == NULL || state == NULL)
5384                 return -EINVAL;
5385
5386         ps = cast_const_phw_vega10_power_state(state);
5387
5388         i = index > ps->performance_level_count - 1 ?
5389                         ps->performance_level_count - 1 : index;
5390
5391         level->coreClock = ps->performance_levels[i].gfx_clock;
5392         level->memory_clock = ps->performance_levels[i].mem_clock;
5393
5394         return 0;
5395 }
5396
5397 static int vega10_disable_power_features_for_compute_performance(struct pp_hwmgr *hwmgr, bool disable)
5398 {
5399         struct vega10_hwmgr *data = hwmgr->backend;
5400         uint32_t feature_mask = 0;
5401
5402         if (disable) {
5403                 feature_mask |= data->smu_features[GNLD_ULV].enabled ?
5404                         data->smu_features[GNLD_ULV].smu_feature_bitmap : 0;
5405                 feature_mask |= data->smu_features[GNLD_DS_GFXCLK].enabled ?
5406                         data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap : 0;
5407                 feature_mask |= data->smu_features[GNLD_DS_SOCCLK].enabled ?
5408                         data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap : 0;
5409                 feature_mask |= data->smu_features[GNLD_DS_LCLK].enabled ?
5410                         data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap : 0;
5411                 feature_mask |= data->smu_features[GNLD_DS_DCEFCLK].enabled ?
5412                         data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap : 0;
5413         } else {
5414                 feature_mask |= (!data->smu_features[GNLD_ULV].enabled) ?
5415                         data->smu_features[GNLD_ULV].smu_feature_bitmap : 0;
5416                 feature_mask |= (!data->smu_features[GNLD_DS_GFXCLK].enabled) ?
5417                         data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap : 0;
5418                 feature_mask |= (!data->smu_features[GNLD_DS_SOCCLK].enabled) ?
5419                         data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap : 0;
5420                 feature_mask |= (!data->smu_features[GNLD_DS_LCLK].enabled) ?
5421                         data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap : 0;
5422                 feature_mask |= (!data->smu_features[GNLD_DS_DCEFCLK].enabled) ?
5423                         data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap : 0;
5424         }
5425
5426         if (feature_mask)
5427                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
5428                                 !disable, feature_mask),
5429                                 "enable/disable power features for compute performance Failed!",
5430                                 return -EINVAL);
5431
5432         if (disable) {
5433                 data->smu_features[GNLD_ULV].enabled = false;
5434                 data->smu_features[GNLD_DS_GFXCLK].enabled = false;
5435                 data->smu_features[GNLD_DS_SOCCLK].enabled = false;
5436                 data->smu_features[GNLD_DS_LCLK].enabled = false;
5437                 data->smu_features[GNLD_DS_DCEFCLK].enabled = false;
5438         } else {
5439                 data->smu_features[GNLD_ULV].enabled = true;
5440                 data->smu_features[GNLD_DS_GFXCLK].enabled = true;
5441                 data->smu_features[GNLD_DS_SOCCLK].enabled = true;
5442                 data->smu_features[GNLD_DS_LCLK].enabled = true;
5443                 data->smu_features[GNLD_DS_DCEFCLK].enabled = true;
5444         }
5445
5446         return 0;
5447
5448 }
5449
5450 static const struct pp_hwmgr_func vega10_hwmgr_funcs = {
5451         .backend_init = vega10_hwmgr_backend_init,
5452         .backend_fini = vega10_hwmgr_backend_fini,
5453         .asic_setup = vega10_setup_asic_task,
5454         .dynamic_state_management_enable = vega10_enable_dpm_tasks,
5455         .dynamic_state_management_disable = vega10_disable_dpm_tasks,
5456         .get_num_of_pp_table_entries =
5457                         vega10_get_number_of_powerplay_table_entries,
5458         .get_power_state_size = vega10_get_power_state_size,
5459         .get_pp_table_entry = vega10_get_pp_table_entry,
5460         .patch_boot_state = vega10_patch_boot_state,
5461         .apply_state_adjust_rules = vega10_apply_state_adjust_rules,
5462         .power_state_set = vega10_set_power_state_tasks,
5463         .get_sclk = vega10_dpm_get_sclk,
5464         .get_mclk = vega10_dpm_get_mclk,
5465         .notify_smc_display_config_after_ps_adjustment =
5466                         vega10_notify_smc_display_config_after_ps_adjustment,
5467         .force_dpm_level = vega10_dpm_force_dpm_level,
5468         .stop_thermal_controller = vega10_thermal_stop_thermal_controller,
5469         .get_fan_speed_info = vega10_fan_ctrl_get_fan_speed_info,
5470         .get_fan_speed_percent = vega10_fan_ctrl_get_fan_speed_percent,
5471         .set_fan_speed_percent = vega10_fan_ctrl_set_fan_speed_percent,
5472         .reset_fan_speed_to_default =
5473                         vega10_fan_ctrl_reset_fan_speed_to_default,
5474         .get_fan_speed_rpm = vega10_fan_ctrl_get_fan_speed_rpm,
5475         .set_fan_speed_rpm = vega10_fan_ctrl_set_fan_speed_rpm,
5476         .uninitialize_thermal_controller =
5477                         vega10_thermal_ctrl_uninitialize_thermal_controller,
5478         .set_fan_control_mode = vega10_set_fan_control_mode,
5479         .get_fan_control_mode = vega10_get_fan_control_mode,
5480         .read_sensor = vega10_read_sensor,
5481         .get_dal_power_level = vega10_get_dal_power_level,
5482         .get_clock_by_type_with_latency = vega10_get_clock_by_type_with_latency,
5483         .get_clock_by_type_with_voltage = vega10_get_clock_by_type_with_voltage,
5484         .set_watermarks_for_clocks_ranges = vega10_set_watermarks_for_clocks_ranges,
5485         .display_clock_voltage_request = vega10_display_clock_voltage_request,
5486         .force_clock_level = vega10_force_clock_level,
5487         .print_clock_levels = vega10_print_clock_levels,
5488         .display_config_changed = vega10_display_configuration_changed_task,
5489         .powergate_uvd = vega10_power_gate_uvd,
5490         .powergate_vce = vega10_power_gate_vce,
5491         .check_states_equal = vega10_check_states_equal,
5492         .check_smc_update_required_for_display_configuration =
5493                         vega10_check_smc_update_required_for_display_configuration,
5494         .power_off_asic = vega10_power_off_asic,
5495         .disable_smc_firmware_ctf = vega10_thermal_disable_alert,
5496         .get_sclk_od = vega10_get_sclk_od,
5497         .set_sclk_od = vega10_set_sclk_od,
5498         .get_mclk_od = vega10_get_mclk_od,
5499         .set_mclk_od = vega10_set_mclk_od,
5500         .avfs_control = vega10_avfs_enable,
5501         .notify_cac_buffer_info = vega10_notify_cac_buffer_info,
5502         .get_thermal_temperature_range = vega10_get_thermal_temperature_range,
5503         .register_irq_handlers = smu9_register_irq_handlers,
5504         .start_thermal_controller = vega10_start_thermal_controller,
5505         .get_power_profile_mode = vega10_get_power_profile_mode,
5506         .set_power_profile_mode = vega10_set_power_profile_mode,
5507         .set_power_limit = vega10_set_power_limit,
5508         .odn_edit_dpm_table = vega10_odn_edit_dpm_table,
5509         .get_performance_level = vega10_get_performance_level,
5510         .get_asic_baco_capability = smu9_baco_get_capability,
5511         .get_asic_baco_state = smu9_baco_get_state,
5512         .set_asic_baco_state = vega10_baco_set_state,
5513         .enable_mgpu_fan_boost = vega10_enable_mgpu_fan_boost,
5514         .get_ppfeature_status = vega10_get_ppfeature_status,
5515         .set_ppfeature_status = vega10_set_ppfeature_status,
5516         .set_mp1_state = vega10_set_mp1_state,
5517         .disable_power_features_for_compute_performance =
5518                         vega10_disable_power_features_for_compute_performance,
5519 };
5520
5521 int vega10_hwmgr_init(struct pp_hwmgr *hwmgr)
5522 {
5523         struct amdgpu_device *adev = hwmgr->adev;
5524
5525         hwmgr->hwmgr_func = &vega10_hwmgr_funcs;
5526         hwmgr->pptable_func = &vega10_pptable_funcs;
5527         if (amdgpu_passthrough(adev))
5528                 return vega10_baco_set_cap(hwmgr);
5529
5530         return 0;
5531 }