drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/module.h>
  26 #include <linux/pci.h>
  27 #include <linux/slab.h>
  28
  29 #include "hwmgr.h"
  30 #include "amd_powerplay.h"
  31 #include "hardwaremanager.h"
  32 #include "ppatomfwctrl.h"
  33 #include "atomfirmware.h"
  34 #include "cgs_common.h"
  35 #include "vega10_powertune.h"
  36 #include "smu9.h"
  37 #include "smu9_driver_if.h"
  38 #include "vega10_inc.h"
  39 #include "soc15_common.h"
  40 #include "pppcielanes.h"
  41 #include "vega10_hwmgr.h"
  42 #include "vega10_smumgr.h"
  43 #include "vega10_processpptables.h"
  44 #include "vega10_pptable.h"
  45 #include "vega10_thermal.h"
  46 #include "pp_debug.h"
  47 #include "amd_pcie_helpers.h"
  48 #include "ppinterrupt.h"
  49 #include "pp_overdriver.h"
  50 #include "pp_thermal.h"
  51 #include "vega10_baco.h"
  52
  53 #include "smuio/smuio_9_0_offset.h"
  54 #include "smuio/smuio_9_0_sh_mask.h"
  55
  56 #define smnPCIE_LC_SPEED_CNTL                   0x11140290
  57 #define smnPCIE_LC_LINK_WIDTH_CNTL              0x11140288
  58
  59 #define HBM_MEMORY_CHANNEL_WIDTH    128
  60
  61 static const uint32_t channel_number[] = {1, 2, 0, 4, 0, 8, 0, 16, 2};
  62
  63 #define mmDF_CS_AON0_DramBaseAddress0                                                                  0x0044
  64 #define mmDF_CS_AON0_DramBaseAddress0_BASE_IDX                                                         0
  65
  66 //DF_CS_AON0_DramBaseAddress0
  67 #define DF_CS_AON0_DramBaseAddress0__AddrRngVal__SHIFT                                                        0x0
  68 #define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn__SHIFT                                                    0x1
  69 #define DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT                                                      0x4
  70 #define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel__SHIFT                                                      0x8
  71 #define DF_CS_AON0_DramBaseAddress0__DramBaseAddr__SHIFT                                                      0xc
  72 #define DF_CS_AON0_DramBaseAddress0__AddrRngVal_MASK                                                          0x00000001L
  73 #define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn_MASK                                                      0x00000002L
  74 #define DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK                                                        0x000000F0L
  75 #define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel_MASK                                                        0x00000700L
  76 #define DF_CS_AON0_DramBaseAddress0__DramBaseAddr_MASK                                                        0xFFFFF000L
  77
  78 typedef enum {
  79         CLK_SMNCLK = 0,
  80         CLK_SOCCLK,
  81         CLK_MP0CLK,
  82         CLK_MP1CLK,
  83         CLK_LCLK,
  84         CLK_DCEFCLK,
  85         CLK_VCLK,
  86         CLK_DCLK,
  87         CLK_ECLK,
  88         CLK_UCLK,
  89         CLK_GFXCLK,
  90         CLK_COUNT,
  91 } CLOCK_ID_e;
  92
  93 static const ULONG PhwVega10_Magic = (ULONG)(PHM_VIslands_Magic);
  94
  95 static struct vega10_power_state *cast_phw_vega10_power_state(
  96                                   struct pp_hw_power_state *hw_ps)
  97 {
  98         PP_ASSERT_WITH_CODE((PhwVega10_Magic == hw_ps->magic),
  99                                 "Invalid Powerstate Type!",
 100                                  return NULL;);
 101
 102         return (struct vega10_power_state *)hw_ps;
 103 }
 104
 105 static const struct vega10_power_state *cast_const_phw_vega10_power_state(
 106                                  const struct pp_hw_power_state *hw_ps)
 107 {
 108         PP_ASSERT_WITH_CODE((PhwVega10_Magic == hw_ps->magic),
 109                                 "Invalid Powerstate Type!",
 110                                  return NULL;);
 111
 112         return (const struct vega10_power_state *)hw_ps;
 113 }
 114
 115 static void vega10_set_default_registry_data(struct pp_hwmgr *hwmgr)
 116 {
 117         struct vega10_hwmgr *data = hwmgr->backend;
 118
 119         data->registry_data.sclk_dpm_key_disabled =
 120                         hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true;
 121         data->registry_data.socclk_dpm_key_disabled =
 122                         hwmgr->feature_mask & PP_SOCCLK_DPM_MASK ? false : true;
 123         data->registry_data.mclk_dpm_key_disabled =
 124                         hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true;
 125         data->registry_data.pcie_dpm_key_disabled =
 126                         hwmgr->feature_mask & PP_PCIE_DPM_MASK ? false : true;
 127
 128         data->registry_data.dcefclk_dpm_key_disabled =
 129                         hwmgr->feature_mask & PP_DCEFCLK_DPM_MASK ? false : true;
 130
 131         if (hwmgr->feature_mask & PP_POWER_CONTAINMENT_MASK) {
 132                 data->registry_data.power_containment_support = 1;
 133                 data->registry_data.enable_pkg_pwr_tracking_feature = 1;
 134                 data->registry_data.enable_tdc_limit_feature = 1;
 135         }
 136
 137         data->registry_data.clock_stretcher_support =
 138                         hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK ? true : false;
 139
 140         data->registry_data.ulv_support =
 141                         hwmgr->feature_mask & PP_ULV_MASK ? true : false;
 142
 143         data->registry_data.sclk_deep_sleep_support =
 144                         hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK ? true : false;
 145
 146         data->registry_data.disable_water_mark = 0;
 147
 148         data->registry_data.fan_control_support = 1;
 149         data->registry_data.thermal_support = 1;
 150         data->registry_data.fw_ctf_enabled = 1;
 151
 152         data->registry_data.avfs_support =
 153                 hwmgr->feature_mask & PP_AVFS_MASK ? true : false;
 154         data->registry_data.led_dpm_enabled = 1;
 155
 156         data->registry_data.vr0hot_enabled = 1;
 157         data->registry_data.vr1hot_enabled = 1;
 158         data->registry_data.regulator_hot_gpio_support = 1;
 159
 160         data->registry_data.didt_support = 1;
 161         if (data->registry_data.didt_support) {
 162                 data->registry_data.didt_mode = 6;
 163                 data->registry_data.sq_ramping_support = 1;
 164                 data->registry_data.db_ramping_support = 0;
 165                 data->registry_data.td_ramping_support = 0;
 166                 data->registry_data.tcp_ramping_support = 0;
 167                 data->registry_data.dbr_ramping_support = 0;
 168                 data->registry_data.edc_didt_support = 1;
 169                 data->registry_data.gc_didt_support = 0;
 170                 data->registry_data.psm_didt_support = 0;
 171         }
 172
 173         data->display_voltage_mode = PPVEGA10_VEGA10DISPLAYVOLTAGEMODE_DFLT;
 174         data->dcef_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 175         data->dcef_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 176         data->dcef_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 177         data->disp_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 178         data->disp_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 179         data->disp_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 180         data->pixel_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 181         data->pixel_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 182         data->pixel_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 183         data->phy_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 184         data->phy_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 185         data->phy_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 186
 187         data->gfxclk_average_alpha = PPVEGA10_VEGA10GFXCLKAVERAGEALPHA_DFLT;
 188         data->socclk_average_alpha = PPVEGA10_VEGA10SOCCLKAVERAGEALPHA_DFLT;
 189         data->uclk_average_alpha = PPVEGA10_VEGA10UCLKCLKAVERAGEALPHA_DFLT;
 190         data->gfx_activity_average_alpha = PPVEGA10_VEGA10GFXACTIVITYAVERAGEALPHA_DFLT;
 191 }
 192
 193 static int vega10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
 194 {
 195         struct vega10_hwmgr *data = hwmgr->backend;
 196         struct phm_ppt_v2_information *table_info =
 197                         (struct phm_ppt_v2_information *)hwmgr->pptable;
 198         struct amdgpu_device *adev = hwmgr->adev;
 199
 200         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 201                         PHM_PlatformCaps_SclkDeepSleep);
 202
 203         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 204                         PHM_PlatformCaps_DynamicPatchPowerState);
 205
 206         if (data->vddci_control == VEGA10_VOLTAGE_CONTROL_NONE)
 207                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 208                                 PHM_PlatformCaps_ControlVDDCI);
 209
 210         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 211                         PHM_PlatformCaps_EnableSMU7ThermalManagement);
 212
 213         if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
 214                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 215                                 PHM_PlatformCaps_UVDPowerGating);
 216
 217         if (adev->pg_flags & AMD_PG_SUPPORT_VCE)
 218                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 219                                 PHM_PlatformCaps_VCEPowerGating);
 220
 221         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 222                         PHM_PlatformCaps_UnTabledHardwareInterface);
 223
 224         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 225                         PHM_PlatformCaps_FanSpeedInTableIsRPM);
 226
 227         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 228                         PHM_PlatformCaps_ODFuzzyFanControlSupport);
 229
 230         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 231                                 PHM_PlatformCaps_DynamicPowerManagement);
 232
 233         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 234                         PHM_PlatformCaps_SMC);
 235
 236         /* power tune caps */
 237         /* assume disabled */
 238         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 239                         PHM_PlatformCaps_PowerContainment);
 240         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 241                         PHM_PlatformCaps_DiDtSupport);
 242         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 243                         PHM_PlatformCaps_SQRamping);
 244         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 245                         PHM_PlatformCaps_DBRamping);
 246         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 247                         PHM_PlatformCaps_TDRamping);
 248         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 249                         PHM_PlatformCaps_TCPRamping);
 250         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 251                         PHM_PlatformCaps_DBRRamping);
 252         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 253                         PHM_PlatformCaps_DiDtEDCEnable);
 254         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 255                         PHM_PlatformCaps_GCEDC);
 256         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 257                         PHM_PlatformCaps_PSM);
 258
 259         if (data->registry_data.didt_support) {
 260                 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtSupport);
 261                 if (data->registry_data.sq_ramping_support)
 262                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping);
 263                 if (data->registry_data.db_ramping_support)
 264                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping);
 265                 if (data->registry_data.td_ramping_support)
 266                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping);
 267                 if (data->registry_data.tcp_ramping_support)
 268                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping);
 269                 if (data->registry_data.dbr_ramping_support)
 270                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRRamping);
 271                 if (data->registry_data.edc_didt_support)
 272                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtEDCEnable);
 273                 if (data->registry_data.gc_didt_support)
 274                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_GCEDC);
 275                 if (data->registry_data.psm_didt_support)
 276                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PSM);
 277         }
 278
 279         if (data->registry_data.power_containment_support)
 280                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 281                                 PHM_PlatformCaps_PowerContainment);
 282         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 283                         PHM_PlatformCaps_CAC);
 284
 285         if (table_info->tdp_table->usClockStretchAmount &&
 286                         data->registry_data.clock_stretcher_support)
 287                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 288                                 PHM_PlatformCaps_ClockStretcher);
 289
 290         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 291                         PHM_PlatformCaps_RegulatorHot);
 292         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 293                         PHM_PlatformCaps_AutomaticDCTransition);
 294
 295         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 296                         PHM_PlatformCaps_UVDDPM);
 297         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 298                         PHM_PlatformCaps_VCEDPM);
 299
 300         return 0;
 301 }
 302
 303 static int vega10_odn_initial_default_setting(struct pp_hwmgr *hwmgr)
 304 {
 305         struct vega10_hwmgr *data = hwmgr->backend;
 306         struct phm_ppt_v2_information *table_info =
 307                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
 308         struct vega10_odn_dpm_table *odn_table = &(data->odn_dpm_table);
 309         struct vega10_odn_vddc_lookup_table *od_lookup_table;
 310         struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
 311         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table[3];
 312         struct phm_ppt_v1_clock_voltage_dependency_table *od_table[3];
 313         struct pp_atomfwctrl_avfs_parameters avfs_params = {0};
 314         uint32_t i;
 315         int result;
 316
 317         result = pp_atomfwctrl_get_avfs_information(hwmgr, &avfs_params);
 318         if (!result) {
 319                 data->odn_dpm_table.max_vddc = avfs_params.ulMaxVddc;
 320                 data->odn_dpm_table.min_vddc = avfs_params.ulMinVddc;
 321         }
 322
 323         od_lookup_table = &odn_table->vddc_lookup_table;
 324         vddc_lookup_table = table_info->vddc_lookup_table;
 325
 326         for (i = 0; i < vddc_lookup_table->count; i++)
 327                 od_lookup_table->entries[i].us_vdd = vddc_lookup_table->entries[i].us_vdd;
 328
 329         od_lookup_table->count = vddc_lookup_table->count;
 330
 331         dep_table[0] = table_info->vdd_dep_on_sclk;
 332         dep_table[1] = table_info->vdd_dep_on_mclk;
 333         dep_table[2] = table_info->vdd_dep_on_socclk;
 334         od_table[0] = (struct phm_ppt_v1_clock_voltage_dependency_table *)&odn_table->vdd_dep_on_sclk;
 335         od_table[1] = (struct phm_ppt_v1_clock_voltage_dependency_table *)&odn_table->vdd_dep_on_mclk;
 336         od_table[2] = (struct phm_ppt_v1_clock_voltage_dependency_table *)&odn_table->vdd_dep_on_socclk;
 337
 338         for (i = 0; i < 3; i++)
 339                 smu_get_voltage_dependency_table_ppt_v1(dep_table[i], od_table[i]);
 340
 341         if (odn_table->max_vddc == 0 || odn_table->max_vddc > 2000)
 342                 odn_table->max_vddc = dep_table[0]->entries[dep_table[0]->count - 1].vddc;
 343         if (odn_table->min_vddc == 0 || odn_table->min_vddc > 2000)
 344                 odn_table->min_vddc = dep_table[0]->entries[0].vddc;
 345
 346         i = od_table[2]->count - 1;
 347         od_table[2]->entries[i].clk = hwmgr->platform_descriptor.overdriveLimit.memoryClock > od_table[2]->entries[i].clk ?
 348                                         hwmgr->platform_descriptor.overdriveLimit.memoryClock :
 349                                         od_table[2]->entries[i].clk;
 350         od_table[2]->entries[i].vddc = odn_table->max_vddc > od_table[2]->entries[i].vddc ?
 351                                         odn_table->max_vddc :
 352                                         od_table[2]->entries[i].vddc;
 353
 354         return 0;
 355 }
 356
 357 static void vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr)
 358 {
 359         struct vega10_hwmgr *data = hwmgr->backend;
 360         int i;
 361         uint32_t sub_vendor_id, hw_revision;
 362         uint32_t top32, bottom32;
 363         struct amdgpu_device *adev = hwmgr->adev;
 364
 365         vega10_initialize_power_tune_defaults(hwmgr);
 366
 367         for (i = 0; i < GNLD_FEATURES_MAX; i++) {
 368                 data->smu_features[i].smu_feature_id = 0xffff;
 369                 data->smu_features[i].smu_feature_bitmap = 1 << i;
 370                 data->smu_features[i].enabled = false;
 371                 data->smu_features[i].supported = false;
 372         }
 373
 374         data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_id =
 375                         FEATURE_DPM_PREFETCHER_BIT;
 376         data->smu_features[GNLD_DPM_GFXCLK].smu_feature_id =
 377                         FEATURE_DPM_GFXCLK_BIT;
 378         data->smu_features[GNLD_DPM_UCLK].smu_feature_id =
 379                         FEATURE_DPM_UCLK_BIT;
 380         data->smu_features[GNLD_DPM_SOCCLK].smu_feature_id =
 381                         FEATURE_DPM_SOCCLK_BIT;
 382         data->smu_features[GNLD_DPM_UVD].smu_feature_id =
 383                         FEATURE_DPM_UVD_BIT;
 384         data->smu_features[GNLD_DPM_VCE].smu_feature_id =
 385                         FEATURE_DPM_VCE_BIT;
 386         data->smu_features[GNLD_DPM_MP0CLK].smu_feature_id =
 387                         FEATURE_DPM_MP0CLK_BIT;
 388         data->smu_features[GNLD_DPM_LINK].smu_feature_id =
 389                         FEATURE_DPM_LINK_BIT;
 390         data->smu_features[GNLD_DPM_DCEFCLK].smu_feature_id =
 391                         FEATURE_DPM_DCEFCLK_BIT;
 392         data->smu_features[GNLD_ULV].smu_feature_id =
 393                         FEATURE_ULV_BIT;
 394         data->smu_features[GNLD_AVFS].smu_feature_id =
 395                         FEATURE_AVFS_BIT;
 396         data->smu_features[GNLD_DS_GFXCLK].smu_feature_id =
 397                         FEATURE_DS_GFXCLK_BIT;
 398         data->smu_features[GNLD_DS_SOCCLK].smu_feature_id =
 399                         FEATURE_DS_SOCCLK_BIT;
 400         data->smu_features[GNLD_DS_LCLK].smu_feature_id =
 401                         FEATURE_DS_LCLK_BIT;
 402         data->smu_features[GNLD_PPT].smu_feature_id =
 403                         FEATURE_PPT_BIT;
 404         data->smu_features[GNLD_TDC].smu_feature_id =
 405                         FEATURE_TDC_BIT;
 406         data->smu_features[GNLD_THERMAL].smu_feature_id =
 407                         FEATURE_THERMAL_BIT;
 408         data->smu_features[GNLD_GFX_PER_CU_CG].smu_feature_id =
 409                         FEATURE_GFX_PER_CU_CG_BIT;
 410         data->smu_features[GNLD_RM].smu_feature_id =
 411                         FEATURE_RM_BIT;
 412         data->smu_features[GNLD_DS_DCEFCLK].smu_feature_id =
 413                         FEATURE_DS_DCEFCLK_BIT;
 414         data->smu_features[GNLD_ACDC].smu_feature_id =
 415                         FEATURE_ACDC_BIT;
 416         data->smu_features[GNLD_VR0HOT].smu_feature_id =
 417                         FEATURE_VR0HOT_BIT;
 418         data->smu_features[GNLD_VR1HOT].smu_feature_id =
 419                         FEATURE_VR1HOT_BIT;
 420         data->smu_features[GNLD_FW_CTF].smu_feature_id =
 421                         FEATURE_FW_CTF_BIT;
 422         data->smu_features[GNLD_LED_DISPLAY].smu_feature_id =
 423                         FEATURE_LED_DISPLAY_BIT;
 424         data->smu_features[GNLD_FAN_CONTROL].smu_feature_id =
 425                         FEATURE_FAN_CONTROL_BIT;
 426         data->smu_features[GNLD_ACG].smu_feature_id = FEATURE_ACG_BIT;
 427         data->smu_features[GNLD_DIDT].smu_feature_id = FEATURE_GFX_EDC_BIT;
 428         data->smu_features[GNLD_PCC_LIMIT].smu_feature_id = FEATURE_PCC_LIMIT_CONTROL_BIT;
 429
 430         if (!data->registry_data.prefetcher_dpm_key_disabled)
 431                 data->smu_features[GNLD_DPM_PREFETCHER].supported = true;
 432
 433         if (!data->registry_data.sclk_dpm_key_disabled)
 434                 data->smu_features[GNLD_DPM_GFXCLK].supported = true;
 435
 436         if (!data->registry_data.mclk_dpm_key_disabled)
 437                 data->smu_features[GNLD_DPM_UCLK].supported = true;
 438
 439         if (!data->registry_data.socclk_dpm_key_disabled)
 440                 data->smu_features[GNLD_DPM_SOCCLK].supported = true;
 441
 442         if (PP_CAP(PHM_PlatformCaps_UVDDPM))
 443                 data->smu_features[GNLD_DPM_UVD].supported = true;
 444
 445         if (PP_CAP(PHM_PlatformCaps_VCEDPM))
 446                 data->smu_features[GNLD_DPM_VCE].supported = true;
 447
 448         data->smu_features[GNLD_DPM_LINK].supported = true;
 449
 450         if (!data->registry_data.dcefclk_dpm_key_disabled)
 451                 data->smu_features[GNLD_DPM_DCEFCLK].supported = true;
 452
 453         if (PP_CAP(PHM_PlatformCaps_SclkDeepSleep) &&
 454             data->registry_data.sclk_deep_sleep_support) {
 455                 data->smu_features[GNLD_DS_GFXCLK].supported = true;
 456                 data->smu_features[GNLD_DS_SOCCLK].supported = true;
 457                 data->smu_features[GNLD_DS_LCLK].supported = true;
 458                 data->smu_features[GNLD_DS_DCEFCLK].supported = true;
 459         }
 460
 461         if (data->registry_data.enable_pkg_pwr_tracking_feature)
 462                 data->smu_features[GNLD_PPT].supported = true;
 463
 464         if (data->registry_data.enable_tdc_limit_feature)
 465                 data->smu_features[GNLD_TDC].supported = true;
 466
 467         if (data->registry_data.thermal_support)
 468                 data->smu_features[GNLD_THERMAL].supported = true;
 469
 470         if (data->registry_data.fan_control_support)
 471                 data->smu_features[GNLD_FAN_CONTROL].supported = true;
 472
 473         if (data->registry_data.fw_ctf_enabled)
 474                 data->smu_features[GNLD_FW_CTF].supported = true;
 475
 476         if (data->registry_data.avfs_support)
 477                 data->smu_features[GNLD_AVFS].supported = true;
 478
 479         if (data->registry_data.led_dpm_enabled)
 480                 data->smu_features[GNLD_LED_DISPLAY].supported = true;
 481
 482         if (data->registry_data.vr1hot_enabled)
 483                 data->smu_features[GNLD_VR1HOT].supported = true;
 484
 485         if (data->registry_data.vr0hot_enabled)
 486                 data->smu_features[GNLD_VR0HOT].supported = true;
 487
 488         smum_send_msg_to_smc(hwmgr,
 489                         PPSMC_MSG_GetSmuVersion,
 490                         &hwmgr->smu_version);
 491                 /* ACG firmware has major version 5 */
 492         if ((hwmgr->smu_version & 0xff000000) == 0x5000000)
 493                 data->smu_features[GNLD_ACG].supported = true;
 494         if (data->registry_data.didt_support)
 495                 data->smu_features[GNLD_DIDT].supported = true;
 496
 497         hw_revision = adev->pdev->revision;
 498         sub_vendor_id = adev->pdev->subsystem_vendor;
 499
 500         if ((hwmgr->chip_id == 0x6862 ||
 501                 hwmgr->chip_id == 0x6861 ||
 502                 hwmgr->chip_id == 0x6868) &&
 503                 (hw_revision == 0) &&
 504                 (sub_vendor_id != 0x1002))
 505                 data->smu_features[GNLD_PCC_LIMIT].supported = true;
 506
 507         /* Get the SN to turn into a Unique ID */
 508         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32, &top32);
 509         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32, &bottom32);
 510
 511         adev->unique_id = ((uint64_t)bottom32 << 32) | top32;
 512 }
 513
 514 #ifdef PPLIB_VEGA10_EVV_SUPPORT
 515 static int vega10_get_socclk_for_voltage_evv(struct pp_hwmgr *hwmgr,
 516         phm_ppt_v1_voltage_lookup_table *lookup_table,
 517         uint16_t virtual_voltage_id, int32_t *socclk)
 518 {
 519         uint8_t entry_id;
 520         uint8_t voltage_id;
 521         struct phm_ppt_v2_information *table_info =
 522                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
 523
 524         PP_ASSERT_WITH_CODE(lookup_table->count != 0,
 525                         "Lookup table is empty",
 526                         return -EINVAL);
 527
 528         /* search for leakage voltage ID 0xff01 ~ 0xff08 and sclk */
 529         for (entry_id = 0; entry_id < table_info->vdd_dep_on_sclk->count; entry_id++) {
 530                 voltage_id = table_info->vdd_dep_on_socclk->entries[entry_id].vddInd;
 531                 if (lookup_table->entries[voltage_id].us_vdd == virtual_voltage_id)
 532                         break;
 533         }
 534
 535         PP_ASSERT_WITH_CODE(entry_id < table_info->vdd_dep_on_socclk->count,
 536                         "Can't find requested voltage id in vdd_dep_on_socclk table!",
 537                         return -EINVAL);
 538
 539         *socclk = table_info->vdd_dep_on_socclk->entries[entry_id].clk;
 540
 541         return 0;
 542 }
 543
 544 #define ATOM_VIRTUAL_VOLTAGE_ID0             0xff01
 545 /**
 546  * vega10_get_evv_voltages - Get Leakage VDDC based on leakage ID.
 547  *
 548  * @hwmgr:  the address of the powerplay hardware manager.
 549  * return:  always 0.
 550  */
 551 static int vega10_get_evv_voltages(struct pp_hwmgr *hwmgr)
 552 {
 553         struct vega10_hwmgr *data = hwmgr->backend;
 554         uint16_t vv_id;
 555         uint32_t vddc = 0;
 556         uint16_t i, j;
 557         uint32_t sclk = 0;
 558         struct phm_ppt_v2_information *table_info =
 559                         (struct phm_ppt_v2_information *)hwmgr->pptable;
 560         struct phm_ppt_v1_clock_voltage_dependency_table *socclk_table =
 561                         table_info->vdd_dep_on_socclk;
 562         int result;
 563
 564         for (i = 0; i < VEGA10_MAX_LEAKAGE_COUNT; i++) {
 565                 vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
 566
 567                 if (!vega10_get_socclk_for_voltage_evv(hwmgr,
 568                                 table_info->vddc_lookup_table, vv_id, &sclk)) {
 569                         if (PP_CAP(PHM_PlatformCaps_ClockStretcher)) {
 570                                 for (j = 1; j < socclk_table->count; j++) {
 571                                         if (socclk_table->entries[j].clk == sclk &&
 572                                                         socclk_table->entries[j].cks_enable == 0) {
 573                                                 sclk += 5000;
 574                                                 break;
 575                                         }
 576                                 }
 577                         }
 578
 579                         PP_ASSERT_WITH_CODE(!atomctrl_get_voltage_evv_on_sclk_ai(hwmgr,
 580                                         VOLTAGE_TYPE_VDDC, sclk, vv_id, &vddc),
 581                                         "Error retrieving EVV voltage value!",
 582                                         continue);
 583
 584
 585                         /* need to make sure vddc is less than 2v or else, it could burn the ASIC. */
 586                         PP_ASSERT_WITH_CODE((vddc < 2000 && vddc != 0),
 587                                         "Invalid VDDC value", result = -EINVAL;);
 588
 589                         /* the voltage should not be zero nor equal to leakage ID */
 590                         if (vddc != 0 && vddc != vv_id) {
 591                                 data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = (uint16_t)(vddc/100);
 592                                 data->vddc_leakage.leakage_id[data->vddc_leakage.count] = vv_id;
 593                                 data->vddc_leakage.count++;
 594                         }
 595                 }
 596         }
 597
 598         return 0;
 599 }
 600
 601 /**
 602  * vega10_patch_with_vdd_leakage - Change virtual leakage voltage to actual value.
 603  *
 604  * @hwmgr:         the address of the powerplay hardware manager.
 605  * @voltage:       pointer to changing voltage
 606  * @leakage_table: pointer to leakage table
 607  */
 608 static void vega10_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr,
 609                 uint16_t *voltage, struct vega10_leakage_voltage *leakage_table)
 610 {
 611         uint32_t index;
 612
 613         /* search for leakage voltage ID 0xff01 ~ 0xff08 */
 614         for (index = 0; index < leakage_table->count; index++) {
 615                 /* if this voltage matches a leakage voltage ID */
 616                 /* patch with actual leakage voltage */
 617                 if (leakage_table->leakage_id[index] == *voltage) {
 618                         *voltage = leakage_table->actual_voltage[index];
 619                         break;
 620                 }
 621         }
 622
 623         if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
 624                 pr_info("Voltage value looks like a Leakage ID but it's not patched\n");
 625 }
 626
 627 /**
 628  * vega10_patch_lookup_table_with_leakage - Patch voltage lookup table by EVV leakages.
 629  *
 630  * @hwmgr:         the address of the powerplay hardware manager.
 631  * @lookup_table:  pointer to voltage lookup table
 632  * @leakage_table: pointer to leakage table
 633  * return:         always 0
 634  */
 635 static int vega10_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
 636                 phm_ppt_v1_voltage_lookup_table *lookup_table,
 637                 struct vega10_leakage_voltage *leakage_table)
 638 {
 639         uint32_t i;
 640
 641         for (i = 0; i < lookup_table->count; i++)
 642                 vega10_patch_with_vdd_leakage(hwmgr,
 643                                 &lookup_table->entries[i].us_vdd, leakage_table);
 644
 645         return 0;
 646 }
 647
 648 static int vega10_patch_clock_voltage_limits_with_vddc_leakage(
 649                 struct pp_hwmgr *hwmgr, struct vega10_leakage_voltage *leakage_table,
 650                 uint16_t *vddc)
 651 {
 652         vega10_patch_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table);
 653
 654         return 0;
 655 }
 656 #endif
 657
 658 static int vega10_patch_voltage_dependency_tables_with_lookup_table(
 659                 struct pp_hwmgr *hwmgr)
 660 {
 661         uint8_t entry_id, voltage_id;
 662         unsigned i;
 663         struct phm_ppt_v2_information *table_info =
 664                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
 665         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
 666                         table_info->mm_dep_table;
 667         struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table =
 668                         table_info->vdd_dep_on_mclk;
 669
 670         for (i = 0; i < 6; i++) {
 671                 struct phm_ppt_v1_clock_voltage_dependency_table *vdt;
 672                 switch (i) {
 673                         case 0: vdt = table_info->vdd_dep_on_socclk; break;
 674                         case 1: vdt = table_info->vdd_dep_on_sclk; break;
 675                         case 2: vdt = table_info->vdd_dep_on_dcefclk; break;
 676                         case 3: vdt = table_info->vdd_dep_on_pixclk; break;
 677                         case 4: vdt = table_info->vdd_dep_on_dispclk; break;
 678                         case 5: vdt = table_info->vdd_dep_on_phyclk; break;
 679                 }
 680
 681                 for (entry_id = 0; entry_id < vdt->count; entry_id++) {
 682                         voltage_id = vdt->entries[entry_id].vddInd;
 683                         vdt->entries[entry_id].vddc =
 684                                         table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
 685                 }
 686         }
 687
 688         for (entry_id = 0; entry_id < mm_table->count; ++entry_id) {
 689                 voltage_id = mm_table->entries[entry_id].vddcInd;
 690                 mm_table->entries[entry_id].vddc =
 691                         table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
 692         }
 693
 694         for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) {
 695                 voltage_id = mclk_table->entries[entry_id].vddInd;
 696                 mclk_table->entries[entry_id].vddc =
 697                                 table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
 698                 voltage_id = mclk_table->entries[entry_id].vddciInd;
 699                 mclk_table->entries[entry_id].vddci =
 700                                 table_info->vddci_lookup_table->entries[voltage_id].us_vdd;
 701                 voltage_id = mclk_table->entries[entry_id].mvddInd;
 702                 mclk_table->entries[entry_id].mvdd =
 703                                 table_info->vddmem_lookup_table->entries[voltage_id].us_vdd;
 704         }
 705
 706
 707         return 0;
 708
 709 }
 710
 711 static int vega10_sort_lookup_table(struct pp_hwmgr *hwmgr,
 712                 struct phm_ppt_v1_voltage_lookup_table *lookup_table)
 713 {
 714         uint32_t table_size, i, j;
 715
 716         PP_ASSERT_WITH_CODE(lookup_table && lookup_table->count,
 717                 "Lookup table is empty", return -EINVAL);
 718
 719         table_size = lookup_table->count;
 720
 721         /* Sorting voltages */
 722         for (i = 0; i < table_size - 1; i++) {
 723                 for (j = i + 1; j > 0; j--) {
 724                         if (lookup_table->entries[j].us_vdd <
 725                                         lookup_table->entries[j - 1].us_vdd) {
 726                                 swap(lookup_table->entries[j - 1],
 727                                      lookup_table->entries[j]);
 728                         }
 729                 }
 730         }
 731
 732         return 0;
 733 }
 734
 735 static int vega10_complete_dependency_tables(struct pp_hwmgr *hwmgr)
 736 {
 737         int result = 0;
 738         int tmp_result;
 739         struct phm_ppt_v2_information *table_info =
 740                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
 741 #ifdef PPLIB_VEGA10_EVV_SUPPORT
 742         struct vega10_hwmgr *data = hwmgr->backend;
 743
 744         tmp_result = vega10_patch_lookup_table_with_leakage(hwmgr,
 745                         table_info->vddc_lookup_table, &(data->vddc_leakage));
 746         if (tmp_result)
 747                 result = tmp_result;
 748
 749         tmp_result = vega10_patch_clock_voltage_limits_with_vddc_leakage(hwmgr,
 750                         &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc);
 751         if (tmp_result)
 752                 result = tmp_result;
 753 #endif
 754
 755         tmp_result = vega10_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
 756         if (tmp_result)
 757                 result = tmp_result;
 758
 759         tmp_result = vega10_sort_lookup_table(hwmgr, table_info->vddc_lookup_table);
 760         if (tmp_result)
 761                 result = tmp_result;
 762
 763         return result;
 764 }
 765
 766 static int vega10_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
 767 {
 768         struct phm_ppt_v2_information *table_info =
 769                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
 770         struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
 771                         table_info->vdd_dep_on_socclk;
 772         struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
 773                         table_info->vdd_dep_on_mclk;
 774
 775         PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table,
 776                 "VDD dependency on SCLK table is missing. This table is mandatory", return -EINVAL);
 777         PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
 778                 "VDD dependency on SCLK table is empty. This table is mandatory", return -EINVAL);
 779
 780         PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table,
 781                 "VDD dependency on MCLK table is missing.  This table is mandatory", return -EINVAL);
 782         PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
 783                 "VDD dependency on MCLK table is empty.  This table is mandatory", return -EINVAL);
 784
 785         table_info->max_clock_voltage_on_ac.sclk =
 786                 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
 787         table_info->max_clock_voltage_on_ac.mclk =
 788                 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
 789         table_info->max_clock_voltage_on_ac.vddc =
 790                 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
 791         table_info->max_clock_voltage_on_ac.vddci =
 792                 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
 793
 794         hwmgr->dyn_state.max_clock_voltage_on_ac.sclk =
 795                 table_info->max_clock_voltage_on_ac.sclk;
 796         hwmgr->dyn_state.max_clock_voltage_on_ac.mclk =
 797                 table_info->max_clock_voltage_on_ac.mclk;
 798         hwmgr->dyn_state.max_clock_voltage_on_ac.vddc =
 799                 table_info->max_clock_voltage_on_ac.vddc;
 800         hwmgr->dyn_state.max_clock_voltage_on_ac.vddci =
 801                 table_info->max_clock_voltage_on_ac.vddci;
 802
 803         return 0;
 804 }
 805
 806 static int vega10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
 807 {
 808         kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
 809         hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
 810
 811         kfree(hwmgr->backend);
 812         hwmgr->backend = NULL;
 813
 814         return 0;
 815 }
 816
 817 static int vega10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
 818 {
 819         int result = 0;
 820         struct vega10_hwmgr *data;
 821         uint32_t config_telemetry = 0;
 822         struct pp_atomfwctrl_voltage_table vol_table;
 823         struct amdgpu_device *adev = hwmgr->adev;
 824
 825         data = kzalloc(sizeof(struct vega10_hwmgr), GFP_KERNEL);
 826         if (data == NULL)
 827                 return -ENOMEM;
 828
 829         hwmgr->backend = data;
 830
 831         hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
 832         hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 833         hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 834
 835         vega10_set_default_registry_data(hwmgr);
 836         data->disable_dpm_mask = 0xff;
 837
 838         /* need to set voltage control types before EVV patching */
 839         data->vddc_control = VEGA10_VOLTAGE_CONTROL_NONE;
 840         data->mvdd_control = VEGA10_VOLTAGE_CONTROL_NONE;
 841         data->vddci_control = VEGA10_VOLTAGE_CONTROL_NONE;
 842
 843         /* VDDCR_SOC */
 844         if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr,
 845                         VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2)) {
 846                 if (!pp_atomfwctrl_get_voltage_table_v4(hwmgr,
 847                                 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2,
 848                                 &vol_table)) {
 849                         config_telemetry = ((vol_table.telemetry_slope << 8) & 0xff00) |
 850                                         (vol_table.telemetry_offset & 0xff);
 851                         data->vddc_control = VEGA10_VOLTAGE_CONTROL_BY_SVID2;
 852                 }
 853         } else {
 854                 kfree(hwmgr->backend);
 855                 hwmgr->backend = NULL;
 856                 PP_ASSERT_WITH_CODE(false,
 857                                 "VDDCR_SOC is not SVID2!",
 858                                 return -1);
 859         }
 860
 861         /* MVDDC */
 862         if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr,
 863                         VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2)) {
 864                 if (!pp_atomfwctrl_get_voltage_table_v4(hwmgr,
 865                                 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2,
 866                                 &vol_table)) {
 867                         config_telemetry |=
 868                                         ((vol_table.telemetry_slope << 24) & 0xff000000) |
 869                                         ((vol_table.telemetry_offset << 16) & 0xff0000);
 870                         data->mvdd_control = VEGA10_VOLTAGE_CONTROL_BY_SVID2;
 871                 }
 872         }
 873
 874          /* VDDCI_MEM */
 875         if (PP_CAP(PHM_PlatformCaps_ControlVDDCI)) {
 876                 if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr,
 877                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
 878                         data->vddci_control = VEGA10_VOLTAGE_CONTROL_BY_GPIO;
 879         }
 880
 881         data->config_telemetry = config_telemetry;
 882
 883         vega10_set_features_platform_caps(hwmgr);
 884
 885         vega10_init_dpm_defaults(hwmgr);
 886
 887 #ifdef PPLIB_VEGA10_EVV_SUPPORT
 888         /* Get leakage voltage based on leakage ID. */
 889         PP_ASSERT_WITH_CODE(!vega10_get_evv_voltages(hwmgr),
 890                         "Get EVV Voltage Failed.  Abort Driver loading!",
 891                         return -1);
 892 #endif
 893
 894         /* Patch our voltage dependency table with actual leakage voltage
 895          * We need to perform leakage translation before it's used by other functions
 896          */
 897         vega10_complete_dependency_tables(hwmgr);
 898
 899         /* Parse pptable data read from VBIOS */
 900         vega10_set_private_data_based_on_pptable(hwmgr);
 901
 902         data->is_tlu_enabled = false;
 903
 904         hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
 905                         VEGA10_MAX_HARDWARE_POWERLEVELS;
 906         hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
 907         hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
 908
 909         hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
 910         /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
 911         hwmgr->platform_descriptor.clockStep.engineClock = 500;
 912         hwmgr->platform_descriptor.clockStep.memoryClock = 500;
 913
 914         data->total_active_cus = adev->gfx.cu_info.number;
 915         if (!hwmgr->not_vf)
 916                 return result;
 917
 918         /* Setup default Overdrive Fan control settings */
 919         data->odn_fan_table.target_fan_speed =
 920                         hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM;
 921         data->odn_fan_table.target_temperature =
 922                         hwmgr->thermal_controller.
 923                         advanceFanControlParameters.ucTargetTemperature;
 924         data->odn_fan_table.min_performance_clock =
 925                         hwmgr->thermal_controller.advanceFanControlParameters.
 926                         ulMinFanSCLKAcousticLimit;
 927         data->odn_fan_table.min_fan_limit =
 928                         hwmgr->thermal_controller.
 929                         advanceFanControlParameters.usFanPWMMinLimit *
 930                         hwmgr->thermal_controller.fanInfo.ulMaxRPM / 100;
 931
 932         data->mem_channels = (RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0) &
 933                         DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK) >>
 934                         DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
 935         PP_ASSERT_WITH_CODE(data->mem_channels < ARRAY_SIZE(channel_number),
 936                         "Mem Channel Index Exceeded maximum!",
 937                         return -EINVAL);
 938
 939         return result;
 940 }
 941
 942 static int vega10_init_sclk_threshold(struct pp_hwmgr *hwmgr)
 943 {
 944         struct vega10_hwmgr *data = hwmgr->backend;
 945
 946         data->low_sclk_interrupt_threshold = 0;
 947
 948         return 0;
 949 }
 950
 951 static int vega10_setup_dpm_led_config(struct pp_hwmgr *hwmgr)
 952 {
 953         struct vega10_hwmgr *data = hwmgr->backend;
 954         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
 955
 956         struct pp_atomfwctrl_voltage_table table;
 957         uint8_t i, j;
 958         uint32_t mask = 0;
 959         uint32_t tmp;
 960         int32_t ret = 0;
 961
 962         ret = pp_atomfwctrl_get_voltage_table_v4(hwmgr, VOLTAGE_TYPE_LEDDPM,
 963                                                 VOLTAGE_OBJ_GPIO_LUT, &table);
 964
 965         if (!ret) {
 966                 tmp = table.mask_low;
 967                 for (i = 0, j = 0; i < 32; i++) {
 968                         if (tmp & 1) {
 969                                 mask |= (uint32_t)(i << (8 * j));
 970                                 if (++j >= 3)
 971                                         break;
 972                         }
 973                         tmp >>= 1;
 974                 }
 975         }
 976
 977         pp_table->LedPin0 = (uint8_t)(mask & 0xff);
 978         pp_table->LedPin1 = (uint8_t)((mask >> 8) & 0xff);
 979         pp_table->LedPin2 = (uint8_t)((mask >> 16) & 0xff);
 980         return 0;
 981 }
 982
 983 static int vega10_setup_asic_task(struct pp_hwmgr *hwmgr)
 984 {
 985         if (!hwmgr->not_vf)
 986                 return 0;
 987
 988         PP_ASSERT_WITH_CODE(!vega10_init_sclk_threshold(hwmgr),
 989                         "Failed to init sclk threshold!",
 990                         return -EINVAL);
 991
 992         PP_ASSERT_WITH_CODE(!vega10_setup_dpm_led_config(hwmgr),
 993                         "Failed to set up led dpm config!",
 994                         return -EINVAL);
 995
 996         smum_send_msg_to_smc_with_parameter(hwmgr,
 997                                 PPSMC_MSG_NumOfDisplays,
 998                                 0,
 999                                 NULL);
1000
1001         return 0;
1002 }
1003
1004 /**
1005  * vega10_trim_voltage_table - Remove repeated voltage values and create table with unique values.
1006  *
1007  * @hwmgr:      the address of the powerplay hardware manager.
1008  * @vol_table:  the pointer to changing voltage table
1009  * return:      0 in success
1010  */
1011 static int vega10_trim_voltage_table(struct pp_hwmgr *hwmgr,
1012                 struct pp_atomfwctrl_voltage_table *vol_table)
1013 {
1014         uint32_t i, j;
1015         uint16_t vvalue;
1016         bool found = false;
1017         struct pp_atomfwctrl_voltage_table *table;
1018
1019         PP_ASSERT_WITH_CODE(vol_table,
1020                         "Voltage Table empty.", return -EINVAL);
1021         table = kzalloc(sizeof(struct pp_atomfwctrl_voltage_table),
1022                         GFP_KERNEL);
1023
1024         if (!table)
1025                 return -ENOMEM;
1026
1027         table->mask_low = vol_table->mask_low;
1028         table->phase_delay = vol_table->phase_delay;
1029
1030         for (i = 0; i < vol_table->count; i++) {
1031                 vvalue = vol_table->entries[i].value;
1032                 found = false;
1033
1034                 for (j = 0; j < table->count; j++) {
1035                         if (vvalue == table->entries[j].value) {
1036                                 found = true;
1037                                 break;
1038                         }
1039                 }
1040
1041                 if (!found) {
1042                         table->entries[table->count].value = vvalue;
1043                         table->entries[table->count].smio_low =
1044                                         vol_table->entries[i].smio_low;
1045                         table->count++;
1046                 }
1047         }
1048
1049         memcpy(vol_table, table, sizeof(struct pp_atomfwctrl_voltage_table));
1050         kfree(table);
1051
1052         return 0;
1053 }
1054
1055 static int vega10_get_mvdd_voltage_table(struct pp_hwmgr *hwmgr,
1056                 phm_ppt_v1_clock_voltage_dependency_table *dep_table,
1057                 struct pp_atomfwctrl_voltage_table *vol_table)
1058 {
1059         int i;
1060
1061         PP_ASSERT_WITH_CODE(dep_table->count,
1062                         "Voltage Dependency Table empty.",
1063                         return -EINVAL);
1064
1065         vol_table->mask_low = 0;
1066         vol_table->phase_delay = 0;
1067         vol_table->count = dep_table->count;
1068
1069         for (i = 0; i < vol_table->count; i++) {
1070                 vol_table->entries[i].value = dep_table->entries[i].mvdd;
1071                 vol_table->entries[i].smio_low = 0;
1072         }
1073
1074         PP_ASSERT_WITH_CODE(!vega10_trim_voltage_table(hwmgr,
1075                         vol_table),
1076                         "Failed to trim MVDD Table!",
1077                         return -1);
1078
1079         return 0;
1080 }
1081
1082 static int vega10_get_vddci_voltage_table(struct pp_hwmgr *hwmgr,
1083                 phm_ppt_v1_clock_voltage_dependency_table *dep_table,
1084                 struct pp_atomfwctrl_voltage_table *vol_table)
1085 {
1086         uint32_t i;
1087
1088         PP_ASSERT_WITH_CODE(dep_table->count,
1089                         "Voltage Dependency Table empty.",
1090                         return -EINVAL);
1091
1092         vol_table->mask_low = 0;
1093         vol_table->phase_delay = 0;
1094         vol_table->count = dep_table->count;
1095
1096         for (i = 0; i < dep_table->count; i++) {
1097                 vol_table->entries[i].value = dep_table->entries[i].vddci;
1098                 vol_table->entries[i].smio_low = 0;
1099         }
1100
1101         PP_ASSERT_WITH_CODE(!vega10_trim_voltage_table(hwmgr, vol_table),
1102                         "Failed to trim VDDCI table.",
1103                         return -1);
1104
1105         return 0;
1106 }
1107
1108 static int vega10_get_vdd_voltage_table(struct pp_hwmgr *hwmgr,
1109                 phm_ppt_v1_clock_voltage_dependency_table *dep_table,
1110                 struct pp_atomfwctrl_voltage_table *vol_table)
1111 {
1112         int i;
1113
1114         PP_ASSERT_WITH_CODE(dep_table->count,
1115                         "Voltage Dependency Table empty.",
1116                         return -EINVAL);
1117
1118         vol_table->mask_low = 0;
1119         vol_table->phase_delay = 0;
1120         vol_table->count = dep_table->count;
1121
1122         for (i = 0; i < vol_table->count; i++) {
1123                 vol_table->entries[i].value = dep_table->entries[i].vddc;
1124                 vol_table->entries[i].smio_low = 0;
1125         }
1126
1127         return 0;
1128 }
1129
1130 /* ---- Voltage Tables ----
1131  * If the voltage table would be bigger than
1132  * what will fit into the state table on
1133  * the SMC keep only the higher entries.
1134  */
1135 static void vega10_trim_voltage_table_to_fit_state_table(
1136                 struct pp_hwmgr *hwmgr,
1137                 uint32_t max_vol_steps,
1138                 struct pp_atomfwctrl_voltage_table *vol_table)
1139 {
1140         unsigned int i, diff;
1141
1142         if (vol_table->count <= max_vol_steps)
1143                 return;
1144
1145         diff = vol_table->count - max_vol_steps;
1146
1147         for (i = 0; i < max_vol_steps; i++)
1148                 vol_table->entries[i] = vol_table->entries[i + diff];
1149
1150         vol_table->count = max_vol_steps;
1151 }
1152
1153 /**
1154  * vega10_construct_voltage_tables - Create Voltage Tables.
1155  *
1156  * @hwmgr:  the address of the powerplay hardware manager.
1157  * return:  always 0
1158  */
1159 static int vega10_construct_voltage_tables(struct pp_hwmgr *hwmgr)
1160 {
1161         struct vega10_hwmgr *data = hwmgr->backend;
1162         struct phm_ppt_v2_information *table_info =
1163                         (struct phm_ppt_v2_information *)hwmgr->pptable;
1164         int result;
1165
1166         if (data->mvdd_control == VEGA10_VOLTAGE_CONTROL_BY_SVID2 ||
1167                         data->mvdd_control == VEGA10_VOLTAGE_CONTROL_NONE) {
1168                 result = vega10_get_mvdd_voltage_table(hwmgr,
1169                                 table_info->vdd_dep_on_mclk,
1170                                 &(data->mvdd_voltage_table));
1171                 PP_ASSERT_WITH_CODE(!result,
1172                                 "Failed to retrieve MVDDC table!",
1173                                 return result);
1174         }
1175
1176         if (data->vddci_control == VEGA10_VOLTAGE_CONTROL_NONE) {
1177                 result = vega10_get_vddci_voltage_table(hwmgr,
1178                                 table_info->vdd_dep_on_mclk,
1179                                 &(data->vddci_voltage_table));
1180                 PP_ASSERT_WITH_CODE(!result,
1181                                 "Failed to retrieve VDDCI_MEM table!",
1182                                 return result);
1183         }
1184
1185         if (data->vddc_control == VEGA10_VOLTAGE_CONTROL_BY_SVID2 ||
1186                         data->vddc_control == VEGA10_VOLTAGE_CONTROL_NONE) {
1187                 result = vega10_get_vdd_voltage_table(hwmgr,
1188                                 table_info->vdd_dep_on_sclk,
1189                                 &(data->vddc_voltage_table));
1190                 PP_ASSERT_WITH_CODE(!result,
1191                                 "Failed to retrieve VDDCR_SOC table!",
1192                                 return result);
1193         }
1194
1195         PP_ASSERT_WITH_CODE(data->vddc_voltage_table.count <= 16,
1196                         "Too many voltage values for VDDC. Trimming to fit state table.",
1197                         vega10_trim_voltage_table_to_fit_state_table(hwmgr,
1198                                         16, &(data->vddc_voltage_table)));
1199
1200         PP_ASSERT_WITH_CODE(data->vddci_voltage_table.count <= 16,
1201                         "Too many voltage values for VDDCI. Trimming to fit state table.",
1202                         vega10_trim_voltage_table_to_fit_state_table(hwmgr,
1203                                         16, &(data->vddci_voltage_table)));
1204
1205         PP_ASSERT_WITH_CODE(data->mvdd_voltage_table.count <= 16,
1206                         "Too many voltage values for MVDD. Trimming to fit state table.",
1207                         vega10_trim_voltage_table_to_fit_state_table(hwmgr,
1208                                         16, &(data->mvdd_voltage_table)));
1209
1210
1211         return 0;
1212 }
1213
1214 /*
1215  * vega10_init_dpm_state
1216  * Function to initialize all Soft Min/Max and Hard Min/Max to 0xff.
1217  *
1218  * @dpm_state: - the address of the DPM Table to initiailize.
1219  * return:   None.
1220  */
1221 static void vega10_init_dpm_state(struct vega10_dpm_state *dpm_state)
1222 {
1223         dpm_state->soft_min_level = 0xff;
1224         dpm_state->soft_max_level = 0xff;
1225         dpm_state->hard_min_level = 0xff;
1226         dpm_state->hard_max_level = 0xff;
1227 }
1228
1229 static void vega10_setup_default_single_dpm_table(struct pp_hwmgr *hwmgr,
1230                 struct vega10_single_dpm_table *dpm_table,
1231                 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table)
1232 {
1233         int i;
1234
1235         dpm_table->count = 0;
1236
1237         for (i = 0; i < dep_table->count; i++) {
1238                 if (i == 0 || dpm_table->dpm_levels[dpm_table->count - 1].value <=
1239                                 dep_table->entries[i].clk) {
1240                         dpm_table->dpm_levels[dpm_table->count].value =
1241                                         dep_table->entries[i].clk;
1242                         dpm_table->dpm_levels[dpm_table->count].enabled = true;
1243                         dpm_table->count++;
1244                 }
1245         }
1246 }
1247 static int vega10_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
1248 {
1249         struct vega10_hwmgr *data = hwmgr->backend;
1250         struct vega10_pcie_table *pcie_table = &(data->dpm_table.pcie_table);
1251         struct phm_ppt_v2_information *table_info =
1252                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
1253         struct phm_ppt_v1_pcie_table *bios_pcie_table =
1254                         table_info->pcie_table;
1255         uint32_t i;
1256
1257         PP_ASSERT_WITH_CODE(bios_pcie_table->count,
1258                         "Incorrect number of PCIE States from VBIOS!",
1259                         return -1);
1260
1261         for (i = 0; i < NUM_LINK_LEVELS; i++) {
1262                 if (data->registry_data.pcieSpeedOverride)
1263                         pcie_table->pcie_gen[i] =
1264                                         data->registry_data.pcieSpeedOverride;
1265                 else
1266                         pcie_table->pcie_gen[i] =
1267                                         bios_pcie_table->entries[i].gen_speed;
1268
1269                 if (data->registry_data.pcieLaneOverride)
1270                         pcie_table->pcie_lane[i] = (uint8_t)encode_pcie_lane_width(
1271                                         data->registry_data.pcieLaneOverride);
1272                 else
1273                         pcie_table->pcie_lane[i] = (uint8_t)encode_pcie_lane_width(
1274                                                         bios_pcie_table->entries[i].lane_width);
1275                 if (data->registry_data.pcieClockOverride)
1276                         pcie_table->lclk[i] =
1277                                         data->registry_data.pcieClockOverride;
1278                 else
1279                         pcie_table->lclk[i] =
1280                                         bios_pcie_table->entries[i].pcie_sclk;
1281         }
1282
1283         pcie_table->count = NUM_LINK_LEVELS;
1284
1285         return 0;
1286 }
1287
1288 /*
1289  * This function is to initialize all DPM state tables
1290  * for SMU based on the dependency table.
1291  * Dynamic state patching function will then trim these
1292  * state tables to the allowed range based
1293  * on the power policy or external client requests,
1294  * such as UVD request, etc.
1295  */
1296 static int vega10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
1297 {
1298         struct vega10_hwmgr *data = hwmgr->backend;
1299         struct phm_ppt_v2_information *table_info =
1300                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
1301         struct vega10_single_dpm_table *dpm_table;
1302         uint32_t i;
1303
1304         struct phm_ppt_v1_clock_voltage_dependency_table *dep_soc_table =
1305                         table_info->vdd_dep_on_socclk;
1306         struct phm_ppt_v1_clock_voltage_dependency_table *dep_gfx_table =
1307                         table_info->vdd_dep_on_sclk;
1308         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
1309                         table_info->vdd_dep_on_mclk;
1310         struct phm_ppt_v1_mm_clock_voltage_dependency_table *dep_mm_table =
1311                         table_info->mm_dep_table;
1312         struct phm_ppt_v1_clock_voltage_dependency_table *dep_dcef_table =
1313                         table_info->vdd_dep_on_dcefclk;
1314         struct phm_ppt_v1_clock_voltage_dependency_table *dep_pix_table =
1315                         table_info->vdd_dep_on_pixclk;
1316         struct phm_ppt_v1_clock_voltage_dependency_table *dep_disp_table =
1317                         table_info->vdd_dep_on_dispclk;
1318         struct phm_ppt_v1_clock_voltage_dependency_table *dep_phy_table =
1319                         table_info->vdd_dep_on_phyclk;
1320
1321         PP_ASSERT_WITH_CODE(dep_soc_table,
1322                         "SOCCLK dependency table is missing. This table is mandatory",
1323                         return -EINVAL);
1324         PP_ASSERT_WITH_CODE(dep_soc_table->count >= 1,
1325                         "SOCCLK dependency table is empty. This table is mandatory",
1326                         return -EINVAL);
1327
1328         PP_ASSERT_WITH_CODE(dep_gfx_table,
1329                         "GFXCLK dependency table is missing. This table is mandatory",
1330                         return -EINVAL);
1331         PP_ASSERT_WITH_CODE(dep_gfx_table->count >= 1,
1332                         "GFXCLK dependency table is empty. This table is mandatory",
1333                         return -EINVAL);
1334
1335         PP_ASSERT_WITH_CODE(dep_mclk_table,
1336                         "MCLK dependency table is missing. This table is mandatory",
1337                         return -EINVAL);
1338         PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1,
1339                         "MCLK dependency table has to have is missing. This table is mandatory",
1340                         return -EINVAL);
1341
1342         /* Initialize Sclk DPM table based on allow Sclk values */
1343         dpm_table = &(data->dpm_table.soc_table);
1344         vega10_setup_default_single_dpm_table(hwmgr,
1345                         dpm_table,
1346                         dep_soc_table);
1347
1348         vega10_init_dpm_state(&(dpm_table->dpm_state));
1349
1350         dpm_table = &(data->dpm_table.gfx_table);
1351         vega10_setup_default_single_dpm_table(hwmgr,
1352                         dpm_table,
1353                         dep_gfx_table);
1354         if (hwmgr->platform_descriptor.overdriveLimit.engineClock == 0)
1355                 hwmgr->platform_descriptor.overdriveLimit.engineClock =
1356                                         dpm_table->dpm_levels[dpm_table->count-1].value;
1357         vega10_init_dpm_state(&(dpm_table->dpm_state));
1358
1359         /* Initialize Mclk DPM table based on allow Mclk values */
1360         data->dpm_table.mem_table.count = 0;
1361         dpm_table = &(data->dpm_table.mem_table);
1362         vega10_setup_default_single_dpm_table(hwmgr,
1363                         dpm_table,
1364                         dep_mclk_table);
1365         if (hwmgr->platform_descriptor.overdriveLimit.memoryClock == 0)
1366                 hwmgr->platform_descriptor.overdriveLimit.memoryClock =
1367                                         dpm_table->dpm_levels[dpm_table->count-1].value;
1368         vega10_init_dpm_state(&(dpm_table->dpm_state));
1369
1370         data->dpm_table.eclk_table.count = 0;
1371         dpm_table = &(data->dpm_table.eclk_table);
1372         for (i = 0; i < dep_mm_table->count; i++) {
1373                 if (i == 0 || dpm_table->dpm_levels
1374                                 [dpm_table->count - 1].value <=
1375                                                 dep_mm_table->entries[i].eclk) {
1376                         dpm_table->dpm_levels[dpm_table->count].value =
1377                                         dep_mm_table->entries[i].eclk;
1378                         dpm_table->dpm_levels[dpm_table->count].enabled =
1379                                         (i == 0) ? true : false;
1380                         dpm_table->count++;
1381                 }
1382         }
1383         vega10_init_dpm_state(&(dpm_table->dpm_state));
1384
1385         data->dpm_table.vclk_table.count = 0;
1386         data->dpm_table.dclk_table.count = 0;
1387         dpm_table = &(data->dpm_table.vclk_table);
1388         for (i = 0; i < dep_mm_table->count; i++) {
1389                 if (i == 0 || dpm_table->dpm_levels
1390                                 [dpm_table->count - 1].value <=
1391                                                 dep_mm_table->entries[i].vclk) {
1392                         dpm_table->dpm_levels[dpm_table->count].value =
1393                                         dep_mm_table->entries[i].vclk;
1394                         dpm_table->dpm_levels[dpm_table->count].enabled =
1395                                         (i == 0) ? true : false;
1396                         dpm_table->count++;
1397                 }
1398         }
1399         vega10_init_dpm_state(&(dpm_table->dpm_state));
1400
1401         dpm_table = &(data->dpm_table.dclk_table);
1402         for (i = 0; i < dep_mm_table->count; i++) {
1403                 if (i == 0 || dpm_table->dpm_levels
1404                                 [dpm_table->count - 1].value <=
1405                                                 dep_mm_table->entries[i].dclk) {
1406                         dpm_table->dpm_levels[dpm_table->count].value =
1407                                         dep_mm_table->entries[i].dclk;
1408                         dpm_table->dpm_levels[dpm_table->count].enabled =
1409                                         (i == 0) ? true : false;
1410                         dpm_table->count++;
1411                 }
1412         }
1413         vega10_init_dpm_state(&(dpm_table->dpm_state));
1414
1415         /* Assume there is no headless Vega10 for now */
1416         dpm_table = &(data->dpm_table.dcef_table);
1417         vega10_setup_default_single_dpm_table(hwmgr,
1418                         dpm_table,
1419                         dep_dcef_table);
1420
1421         vega10_init_dpm_state(&(dpm_table->dpm_state));
1422
1423         dpm_table = &(data->dpm_table.pixel_table);
1424         vega10_setup_default_single_dpm_table(hwmgr,
1425                         dpm_table,
1426                         dep_pix_table);
1427
1428         vega10_init_dpm_state(&(dpm_table->dpm_state));
1429
1430         dpm_table = &(data->dpm_table.display_table);
1431         vega10_setup_default_single_dpm_table(hwmgr,
1432                         dpm_table,
1433                         dep_disp_table);
1434
1435         vega10_init_dpm_state(&(dpm_table->dpm_state));
1436
1437         dpm_table = &(data->dpm_table.phy_table);
1438         vega10_setup_default_single_dpm_table(hwmgr,
1439                         dpm_table,
1440                         dep_phy_table);
1441
1442         vega10_init_dpm_state(&(dpm_table->dpm_state));
1443
1444         vega10_setup_default_pcie_table(hwmgr);
1445
1446         /* Zero out the saved copy of the CUSTOM profile
1447          * This will be checked when trying to set the profile
1448          * and will require that new values be passed in
1449          */
1450         data->custom_profile_mode[0] = 0;
1451         data->custom_profile_mode[1] = 0;
1452         data->custom_profile_mode[2] = 0;
1453         data->custom_profile_mode[3] = 0;
1454
1455         /* save a copy of the default DPM table */
1456         memcpy(&(data->golden_dpm_table), &(data->dpm_table),
1457                         sizeof(struct vega10_dpm_table));
1458
1459         return 0;
1460 }
1461
1462 /*
1463  * vega10_populate_ulv_state
1464  * Function to provide parameters for Utral Low Voltage state to SMC.
1465  *
1466  * @hwmgr: - the address of the hardware manager.
1467  * return:   Always 0.
1468  */
1469 static int vega10_populate_ulv_state(struct pp_hwmgr *hwmgr)
1470 {
1471         struct vega10_hwmgr *data = hwmgr->backend;
1472         struct phm_ppt_v2_information *table_info =
1473                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
1474
1475         data->smc_state_table.pp_table.UlvOffsetVid =
1476                         (uint8_t)table_info->us_ulv_voltage_offset;
1477
1478         data->smc_state_table.pp_table.UlvSmnclkDid =
1479                         (uint8_t)(table_info->us_ulv_smnclk_did);
1480         data->smc_state_table.pp_table.UlvMp1clkDid =
1481                         (uint8_t)(table_info->us_ulv_mp1clk_did);
1482         data->smc_state_table.pp_table.UlvGfxclkBypass =
1483                         (uint8_t)(table_info->us_ulv_gfxclk_bypass);
1484         data->smc_state_table.pp_table.UlvPhaseSheddingPsi0 =
1485                         (uint8_t)(data->vddc_voltage_table.psi0_enable);
1486         data->smc_state_table.pp_table.UlvPhaseSheddingPsi1 =
1487                         (uint8_t)(data->vddc_voltage_table.psi1_enable);
1488
1489         return 0;
1490 }
1491
1492 static int vega10_populate_single_lclk_level(struct pp_hwmgr *hwmgr,
1493                 uint32_t lclock, uint8_t *curr_lclk_did)
1494 {
1495         struct pp_atomfwctrl_clock_dividers_soc15 dividers;
1496
1497         PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(
1498                         hwmgr,
1499                         COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
1500                         lclock, &dividers),
1501                         "Failed to get LCLK clock settings from VBIOS!",
1502                         return -1);
1503
1504         *curr_lclk_did = dividers.ulDid;
1505
1506         return 0;
1507 }
1508
1509 static int vega10_override_pcie_parameters(struct pp_hwmgr *hwmgr)
1510 {
1511         struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
1512         struct vega10_hwmgr *data =
1513                         (struct vega10_hwmgr *)(hwmgr->backend);
1514         uint32_t pcie_gen = 0, pcie_width = 0;
1515         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1516         int i;
1517
1518         if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
1519                 pcie_gen = 3;
1520         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
1521                 pcie_gen = 2;
1522         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
1523                 pcie_gen = 1;
1524         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
1525                 pcie_gen = 0;
1526
1527         if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
1528                 pcie_width = 6;
1529         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
1530                 pcie_width = 5;
1531         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
1532                 pcie_width = 4;
1533         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
1534                 pcie_width = 3;
1535         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
1536                 pcie_width = 2;
1537         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
1538                 pcie_width = 1;
1539
1540         for (i = 0; i < NUM_LINK_LEVELS; i++) {
1541                 if (pp_table->PcieGenSpeed[i] > pcie_gen)
1542                         pp_table->PcieGenSpeed[i] = pcie_gen;
1543
1544                 if (pp_table->PcieLaneCount[i] > pcie_width)
1545                         pp_table->PcieLaneCount[i] = pcie_width;
1546         }
1547
1548         if (data->registry_data.pcie_dpm_key_disabled) {
1549                 for (i = 0; i < NUM_LINK_LEVELS; i++) {
1550                         pp_table->PcieGenSpeed[i] = pcie_gen;
1551                         pp_table->PcieLaneCount[i] = pcie_width;
1552                 }
1553         }
1554
1555         return 0;
1556 }
1557
1558 static int vega10_populate_smc_link_levels(struct pp_hwmgr *hwmgr)
1559 {
1560         int result = -1;
1561         struct vega10_hwmgr *data = hwmgr->backend;
1562         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1563         struct vega10_pcie_table *pcie_table =
1564                         &(data->dpm_table.pcie_table);
1565         uint32_t i, j;
1566
1567         for (i = 0; i < pcie_table->count; i++) {
1568                 pp_table->PcieGenSpeed[i] = pcie_table->pcie_gen[i];
1569                 pp_table->PcieLaneCount[i] = pcie_table->pcie_lane[i];
1570
1571                 result = vega10_populate_single_lclk_level(hwmgr,
1572                                 pcie_table->lclk[i], &(pp_table->LclkDid[i]));
1573                 if (result) {
1574                         pr_info("Populate LClock Level %d Failed!\n", i);
1575                         return result;
1576                 }
1577         }
1578
1579         j = i - 1;
1580         while (i < NUM_LINK_LEVELS) {
1581                 pp_table->PcieGenSpeed[i] = pcie_table->pcie_gen[j];
1582                 pp_table->PcieLaneCount[i] = pcie_table->pcie_lane[j];
1583
1584                 result = vega10_populate_single_lclk_level(hwmgr,
1585                                 pcie_table->lclk[j], &(pp_table->LclkDid[i]));
1586                 if (result) {
1587                         pr_info("Populate LClock Level %d Failed!\n", i);
1588                         return result;
1589                 }
1590                 i++;
1591         }
1592
1593         return result;
1594 }
1595
1596 /**
1597  * vega10_populate_single_gfx_level - Populates single SMC GFXSCLK structure
1598  *                                    using the provided engine clock
1599  *
1600  * @hwmgr:      the address of the hardware manager
1601  * @gfx_clock:  the GFX clock to use to populate the structure.
1602  * @current_gfxclk_level:  location in PPTable for the SMC GFXCLK structure.
1603  * @acg_freq:   ACG frequenty to return (MHz)
1604  */
1605 static int vega10_populate_single_gfx_level(struct pp_hwmgr *hwmgr,
1606                 uint32_t gfx_clock, PllSetting_t *current_gfxclk_level,
1607                 uint32_t *acg_freq)
1608 {
1609         struct phm_ppt_v2_information *table_info =
1610                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
1611         struct phm_ppt_v1_clock_voltage_dependency_table *dep_on_sclk;
1612         struct vega10_hwmgr *data = hwmgr->backend;
1613         struct pp_atomfwctrl_clock_dividers_soc15 dividers;
1614         uint32_t gfx_max_clock =
1615                         hwmgr->platform_descriptor.overdriveLimit.engineClock;
1616         uint32_t i = 0;
1617
1618         if (hwmgr->od_enabled)
1619                 dep_on_sclk = (struct phm_ppt_v1_clock_voltage_dependency_table *)
1620                                                 &(data->odn_dpm_table.vdd_dep_on_sclk);
1621         else
1622                 dep_on_sclk = table_info->vdd_dep_on_sclk;
1623
1624         PP_ASSERT_WITH_CODE(dep_on_sclk,
1625                         "Invalid SOC_VDD-GFX_CLK Dependency Table!",
1626                         return -EINVAL);
1627
1628         if (data->need_update_dpm_table & DPMTABLE_OD_UPDATE_SCLK)
1629                 gfx_clock = gfx_clock > gfx_max_clock ? gfx_max_clock : gfx_clock;
1630         else {
1631                 for (i = 0; i < dep_on_sclk->count; i++) {
1632                         if (dep_on_sclk->entries[i].clk == gfx_clock)
1633                                 break;
1634                 }
1635                 PP_ASSERT_WITH_CODE(dep_on_sclk->count > i,
1636                                 "Cannot find gfx_clk in SOC_VDD-GFX_CLK!",
1637                                 return -EINVAL);
1638         }
1639
1640         PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
1641                         COMPUTE_GPUCLK_INPUT_FLAG_GFXCLK,
1642                         gfx_clock, &dividers),
1643                         "Failed to get GFX Clock settings from VBIOS!",
1644                         return -EINVAL);
1645
1646         /* Feedback Multiplier: bit 0:8 int, bit 15:12 post_div, bit 31:16 frac */
1647         current_gfxclk_level->FbMult =
1648                         cpu_to_le32(dividers.ulPll_fb_mult);
1649         /* Spread FB Multiplier bit: bit 0:8 int, bit 31:16 frac */
1650         current_gfxclk_level->SsOn = dividers.ucPll_ss_enable;
1651         current_gfxclk_level->SsFbMult =
1652                         cpu_to_le32(dividers.ulPll_ss_fbsmult);
1653         current_gfxclk_level->SsSlewFrac =
1654                         cpu_to_le16(dividers.usPll_ss_slew_frac);
1655         current_gfxclk_level->Did = (uint8_t)(dividers.ulDid);
1656
1657         *acg_freq = gfx_clock / 100; /* 100 Khz to Mhz conversion */
1658
1659         return 0;
1660 }
1661
1662 /**
1663  * vega10_populate_single_soc_level - Populates single SMC SOCCLK structure
1664  *                                    using the provided clock.
1665  *
1666  * @hwmgr:     the address of the hardware manager.
1667  * @soc_clock: the SOC clock to use to populate the structure.
1668  * @current_soc_did:   DFS divider to pass back to caller
1669  * @current_vol_index: index of current VDD to pass back to caller
1670  * return:      0 on success
1671  */
1672 static int vega10_populate_single_soc_level(struct pp_hwmgr *hwmgr,
1673                 uint32_t soc_clock, uint8_t *current_soc_did,
1674                 uint8_t *current_vol_index)
1675 {
1676         struct vega10_hwmgr *data = hwmgr->backend;
1677         struct phm_ppt_v2_information *table_info =
1678                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
1679         struct phm_ppt_v1_clock_voltage_dependency_table *dep_on_soc;
1680         struct pp_atomfwctrl_clock_dividers_soc15 dividers;
1681         uint32_t i;
1682
1683         if (hwmgr->od_enabled) {
1684                 dep_on_soc = (struct phm_ppt_v1_clock_voltage_dependency_table *)
1685                                                 &data->odn_dpm_table.vdd_dep_on_socclk;
1686                 for (i = 0; i < dep_on_soc->count; i++) {
1687                         if (dep_on_soc->entries[i].clk >= soc_clock)
1688                                 break;
1689                 }
1690         } else {
1691                 dep_on_soc = table_info->vdd_dep_on_socclk;
1692                 for (i = 0; i < dep_on_soc->count; i++) {
1693                         if (dep_on_soc->entries[i].clk == soc_clock)
1694                                 break;
1695                 }
1696         }
1697
1698         PP_ASSERT_WITH_CODE(dep_on_soc->count > i,
1699                         "Cannot find SOC_CLK in SOC_VDD-SOC_CLK Dependency Table",
1700                         return -EINVAL);
1701
1702         PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
1703                         COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
1704                         soc_clock, &dividers),
1705                         "Failed to get SOC Clock settings from VBIOS!",
1706                         return -EINVAL);
1707
1708         *current_soc_did = (uint8_t)dividers.ulDid;
1709         *current_vol_index = (uint8_t)(dep_on_soc->entries[i].vddInd);
1710         return 0;
1711 }
1712
1713 /**
1714  * vega10_populate_all_graphic_levels - Populates all SMC SCLK levels' structure
1715  *                                      based on the trimmed allowed dpm engine clock states
1716  *
1717  * @hwmgr:      the address of the hardware manager
1718  */
1719 static int vega10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
1720 {
1721         struct vega10_hwmgr *data = hwmgr->backend;
1722         struct phm_ppt_v2_information *table_info =
1723                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
1724         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1725         struct vega10_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table);
1726         int result = 0;
1727         uint32_t i, j;
1728
1729         for (i = 0; i < dpm_table->count; i++) {
1730                 result = vega10_populate_single_gfx_level(hwmgr,
1731                                 dpm_table->dpm_levels[i].value,
1732                                 &(pp_table->GfxclkLevel[i]),
1733                                 &(pp_table->AcgFreqTable[i]));
1734                 if (result)
1735                         return result;
1736         }
1737
1738         j = i - 1;
1739         while (i < NUM_GFXCLK_DPM_LEVELS) {
1740                 result = vega10_populate_single_gfx_level(hwmgr,
1741                                 dpm_table->dpm_levels[j].value,
1742                                 &(pp_table->GfxclkLevel[i]),
1743                                 &(pp_table->AcgFreqTable[i]));
1744                 if (result)
1745                         return result;
1746                 i++;
1747         }
1748
1749         pp_table->GfxclkSlewRate =
1750                         cpu_to_le16(table_info->us_gfxclk_slew_rate);
1751
1752         dpm_table = &(data->dpm_table.soc_table);
1753         for (i = 0; i < dpm_table->count; i++) {
1754                 result = vega10_populate_single_soc_level(hwmgr,
1755                                 dpm_table->dpm_levels[i].value,
1756                                 &(pp_table->SocclkDid[i]),
1757                                 &(pp_table->SocDpmVoltageIndex[i]));
1758                 if (result)
1759                         return result;
1760         }
1761
1762         j = i - 1;
1763         while (i < NUM_SOCCLK_DPM_LEVELS) {
1764                 result = vega10_populate_single_soc_level(hwmgr,
1765                                 dpm_table->dpm_levels[j].value,
1766                                 &(pp_table->SocclkDid[i]),
1767                                 &(pp_table->SocDpmVoltageIndex[i]));
1768                 if (result)
1769                         return result;
1770                 i++;
1771         }
1772
1773         return result;
1774 }
1775
1776 static void vega10_populate_vddc_soc_levels(struct pp_hwmgr *hwmgr)
1777 {
1778         struct vega10_hwmgr *data = hwmgr->backend;
1779         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1780         struct phm_ppt_v2_information *table_info = hwmgr->pptable;
1781         struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
1782
1783         uint8_t soc_vid = 0;
1784         uint32_t i, max_vddc_level;
1785
1786         if (hwmgr->od_enabled)
1787                 vddc_lookup_table = (struct phm_ppt_v1_voltage_lookup_table *)&data->odn_dpm_table.vddc_lookup_table;
1788         else
1789                 vddc_lookup_table = table_info->vddc_lookup_table;
1790
1791         max_vddc_level = vddc_lookup_table->count;
1792         for (i = 0; i < max_vddc_level; i++) {
1793                 soc_vid = (uint8_t)convert_to_vid(vddc_lookup_table->entries[i].us_vdd);
1794                 pp_table->SocVid[i] = soc_vid;
1795         }
1796         while (i < MAX_REGULAR_DPM_NUMBER) {
1797                 pp_table->SocVid[i] = soc_vid;
1798                 i++;
1799         }
1800 }
1801
1802 /*
1803  * Populates single SMC GFXCLK structure using the provided clock.
1804  *
1805  * @hwmgr:     the address of the hardware manager.
1806  * @mem_clock: the memory clock to use to populate the structure.
1807  * return:     0 on success..
1808  */
1809 static int vega10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
1810                 uint32_t mem_clock, uint8_t *current_mem_vid,
1811                 PllSetting_t *current_memclk_level, uint8_t *current_mem_soc_vind)
1812 {
1813         struct vega10_hwmgr *data = hwmgr->backend;
1814         struct phm_ppt_v2_information *table_info =
1815                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
1816         struct phm_ppt_v1_clock_voltage_dependency_table *dep_on_mclk;
1817         struct pp_atomfwctrl_clock_dividers_soc15 dividers;
1818         uint32_t mem_max_clock =
1819                         hwmgr->platform_descriptor.overdriveLimit.memoryClock;
1820         uint32_t i = 0;
1821
1822         if (hwmgr->od_enabled)
1823                 dep_on_mclk = (struct phm_ppt_v1_clock_voltage_dependency_table *)
1824                                         &data->odn_dpm_table.vdd_dep_on_mclk;
1825         else
1826                 dep_on_mclk = table_info->vdd_dep_on_mclk;
1827
1828         PP_ASSERT_WITH_CODE(dep_on_mclk,
1829                         "Invalid SOC_VDD-UCLK Dependency Table!",
1830                         return -EINVAL);
1831
1832         if (data->need_update_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
1833                 mem_clock = mem_clock > mem_max_clock ? mem_max_clock : mem_clock;
1834         } else {
1835                 for (i = 0; i < dep_on_mclk->count; i++) {
1836                         if (dep_on_mclk->entries[i].clk == mem_clock)
1837                                 break;
1838                 }
1839                 PP_ASSERT_WITH_CODE(dep_on_mclk->count > i,
1840                                 "Cannot find UCLK in SOC_VDD-UCLK Dependency Table!",
1841                                 return -EINVAL);
1842         }
1843
1844         PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(
1845                         hwmgr, COMPUTE_GPUCLK_INPUT_FLAG_UCLK, mem_clock, &dividers),
1846                         "Failed to get UCLK settings from VBIOS!",
1847                         return -1);
1848
1849         *current_mem_vid =
1850                         (uint8_t)(convert_to_vid(dep_on_mclk->entries[i].mvdd));
1851         *current_mem_soc_vind =
1852                         (uint8_t)(dep_on_mclk->entries[i].vddInd);
1853         current_memclk_level->FbMult = cpu_to_le32(dividers.ulPll_fb_mult);
1854         current_memclk_level->Did = (uint8_t)(dividers.ulDid);
1855
1856         PP_ASSERT_WITH_CODE(current_memclk_level->Did >= 1,
1857                         "Invalid Divider ID!",
1858                         return -EINVAL);
1859
1860         return 0;
1861 }
1862
1863 /**
1864  * vega10_populate_all_memory_levels - Populates all SMC MCLK levels' structure
1865  *                                     based on the trimmed allowed dpm memory clock states.
1866  *
1867  * @hwmgr:  the address of the hardware manager.
1868  * return:   PP_Result_OK on success.
1869  */
1870 static int vega10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1871 {
1872         struct vega10_hwmgr *data = hwmgr->backend;
1873         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1874         struct vega10_single_dpm_table *dpm_table =
1875                         &(data->dpm_table.mem_table);
1876         int result = 0;
1877         uint32_t i, j;
1878
1879         for (i = 0; i < dpm_table->count; i++) {
1880                 result = vega10_populate_single_memory_level(hwmgr,
1881                                 dpm_table->dpm_levels[i].value,
1882                                 &(pp_table->MemVid[i]),
1883                                 &(pp_table->UclkLevel[i]),
1884                                 &(pp_table->MemSocVoltageIndex[i]));
1885                 if (result)
1886                         return result;
1887         }
1888
1889         j = i - 1;
1890         while (i < NUM_UCLK_DPM_LEVELS) {
1891                 result = vega10_populate_single_memory_level(hwmgr,
1892                                 dpm_table->dpm_levels[j].value,
1893                                 &(pp_table->MemVid[i]),
1894                                 &(pp_table->UclkLevel[i]),
1895                                 &(pp_table->MemSocVoltageIndex[i]));
1896                 if (result)
1897                         return result;
1898                 i++;
1899         }
1900
1901         pp_table->NumMemoryChannels = (uint16_t)(data->mem_channels);
1902         pp_table->MemoryChannelWidth =
1903                         (uint16_t)(HBM_MEMORY_CHANNEL_WIDTH *
1904                                         channel_number[data->mem_channels]);
1905
1906         pp_table->LowestUclkReservedForUlv =
1907                         (uint8_t)(data->lowest_uclk_reserved_for_ulv);
1908
1909         return result;
1910 }
1911
1912 static int vega10_populate_single_display_type(struct pp_hwmgr *hwmgr,
1913                 DSPCLK_e disp_clock)
1914 {
1915         struct vega10_hwmgr *data = hwmgr->backend;
1916         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1917         struct phm_ppt_v2_information *table_info =
1918                         (struct phm_ppt_v2_information *)
1919                         (hwmgr->pptable);
1920         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table;
1921         uint32_t i;
1922         uint16_t clk = 0, vddc = 0;
1923         uint8_t vid = 0;
1924
1925         switch (disp_clock) {
1926         case DSPCLK_DCEFCLK:
1927                 dep_table = table_info->vdd_dep_on_dcefclk;
1928                 break;
1929         case DSPCLK_DISPCLK:
1930                 dep_table = table_info->vdd_dep_on_dispclk;
1931                 break;
1932         case DSPCLK_PIXCLK:
1933                 dep_table = table_info->vdd_dep_on_pixclk;
1934                 break;
1935         case DSPCLK_PHYCLK:
1936                 dep_table = table_info->vdd_dep_on_phyclk;
1937                 break;
1938         default:
1939                 return -1;
1940         }
1941
1942         PP_ASSERT_WITH_CODE(dep_table->count <= NUM_DSPCLK_LEVELS,
1943                         "Number Of Entries Exceeded maximum!",
1944                         return -1);
1945
1946         for (i = 0; i < dep_table->count; i++) {
1947                 clk = (uint16_t)(dep_table->entries[i].clk / 100);
1948                 vddc = table_info->vddc_lookup_table->
1949                                 entries[dep_table->entries[i].vddInd].us_vdd;
1950                 vid = (uint8_t)convert_to_vid(vddc);
1951                 pp_table->DisplayClockTable[disp_clock][i].Freq =
1952                                 cpu_to_le16(clk);
1953                 pp_table->DisplayClockTable[disp_clock][i].Vid =
1954                                 cpu_to_le16(vid);
1955         }
1956
1957         while (i < NUM_DSPCLK_LEVELS) {
1958                 pp_table->DisplayClockTable[disp_clock][i].Freq =
1959                                 cpu_to_le16(clk);
1960                 pp_table->DisplayClockTable[disp_clock][i].Vid =
1961                                 cpu_to_le16(vid);
1962                 i++;
1963         }
1964
1965         return 0;
1966 }
1967
1968 static int vega10_populate_all_display_clock_levels(struct pp_hwmgr *hwmgr)
1969 {
1970         uint32_t i;
1971
1972         for (i = 0; i < DSPCLK_COUNT; i++) {
1973                 PP_ASSERT_WITH_CODE(!vega10_populate_single_display_type(hwmgr, i),
1974                                 "Failed to populate Clock in DisplayClockTable!",
1975                                 return -1);
1976         }
1977
1978         return 0;
1979 }
1980
1981 static int vega10_populate_single_eclock_level(struct pp_hwmgr *hwmgr,
1982                 uint32_t eclock, uint8_t *current_eclk_did,
1983                 uint8_t *current_soc_vol)
1984 {
1985         struct phm_ppt_v2_information *table_info =
1986                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
1987         struct phm_ppt_v1_mm_clock_voltage_dependency_table *dep_table =
1988                         table_info->mm_dep_table;
1989         struct pp_atomfwctrl_clock_dividers_soc15 dividers;
1990         uint32_t i;
1991
1992         PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
1993                         COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
1994                         eclock, &dividers),
1995                         "Failed to get ECLK clock settings from VBIOS!",
1996                         return -1);
1997
1998         *current_eclk_did = (uint8_t)dividers.ulDid;
1999
2000         for (i = 0; i < dep_table->count; i++) {
2001                 if (dep_table->entries[i].eclk == eclock)
2002                         *current_soc_vol = dep_table->entries[i].vddcInd;
2003         }
2004
2005         return 0;
2006 }
2007
2008 static int vega10_populate_smc_vce_levels(struct pp_hwmgr *hwmgr)
2009 {
2010         struct vega10_hwmgr *data = hwmgr->backend;
2011         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
2012         struct vega10_single_dpm_table *dpm_table = &(data->dpm_table.eclk_table);
2013         int result = -EINVAL;
2014         uint32_t i, j;
2015
2016         for (i = 0; i < dpm_table->count; i++) {
2017                 result = vega10_populate_single_eclock_level(hwmgr,
2018                                 dpm_table->dpm_levels[i].value,
2019                                 &(pp_table->EclkDid[i]),
2020                                 &(pp_table->VceDpmVoltageIndex[i]));
2021                 if (result)
2022                         return result;
2023         }
2024
2025         j = i - 1;
2026         while (i < NUM_VCE_DPM_LEVELS) {
2027                 result = vega10_populate_single_eclock_level(hwmgr,
2028                                 dpm_table->dpm_levels[j].value,
2029                                 &(pp_table->EclkDid[i]),
2030                                 &(pp_table->VceDpmVoltageIndex[i]));
2031                 if (result)
2032                         return result;
2033                 i++;
2034         }
2035
2036         return result;
2037 }
2038
2039 static int vega10_populate_single_vclock_level(struct pp_hwmgr *hwmgr,
2040                 uint32_t vclock, uint8_t *current_vclk_did)
2041 {
2042         struct pp_atomfwctrl_clock_dividers_soc15 dividers;
2043
2044         PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
2045                         COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2046                         vclock, &dividers),
2047                         "Failed to get VCLK clock settings from VBIOS!",
2048                         return -EINVAL);
2049
2050         *current_vclk_did = (uint8_t)dividers.ulDid;
2051
2052         return 0;
2053 }
2054
2055 static int vega10_populate_single_dclock_level(struct pp_hwmgr *hwmgr,
2056                 uint32_t dclock, uint8_t *current_dclk_did)
2057 {
2058         struct pp_atomfwctrl_clock_dividers_soc15 dividers;
2059
2060         PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
2061                         COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2062                         dclock, &dividers),
2063                         "Failed to get DCLK clock settings from VBIOS!",
2064                         return -EINVAL);
2065
2066         *current_dclk_did = (uint8_t)dividers.ulDid;
2067
2068         return 0;
2069 }
2070
2071 static int vega10_populate_smc_uvd_levels(struct pp_hwmgr *hwmgr)
2072 {
2073         struct vega10_hwmgr *data = hwmgr->backend;
2074         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
2075         struct vega10_single_dpm_table *vclk_dpm_table =
2076                         &(data->dpm_table.vclk_table);
2077         struct vega10_single_dpm_table *dclk_dpm_table =
2078                         &(data->dpm_table.dclk_table);
2079         struct phm_ppt_v2_information *table_info =
2080                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
2081         struct phm_ppt_v1_mm_clock_voltage_dependency_table *dep_table =
2082                         table_info->mm_dep_table;
2083         int result = -EINVAL;
2084         uint32_t i, j;
2085
2086         for (i = 0; i < vclk_dpm_table->count; i++) {
2087                 result = vega10_populate_single_vclock_level(hwmgr,
2088                                 vclk_dpm_table->dpm_levels[i].value,
2089                                 &(pp_table->VclkDid[i]));
2090                 if (result)
2091                         return result;
2092         }
2093
2094         j = i - 1;
2095         while (i < NUM_UVD_DPM_LEVELS) {
2096                 result = vega10_populate_single_vclock_level(hwmgr,
2097                                 vclk_dpm_table->dpm_levels[j].value,
2098                                 &(pp_table->VclkDid[i]));
2099                 if (result)
2100                         return result;
2101                 i++;
2102         }
2103
2104         for (i = 0; i < dclk_dpm_table->count; i++) {
2105                 result = vega10_populate_single_dclock_level(hwmgr,
2106                                 dclk_dpm_table->dpm_levels[i].value,
2107                                 &(pp_table->DclkDid[i]));
2108                 if (result)
2109                         return result;
2110         }
2111
2112         j = i - 1;
2113         while (i < NUM_UVD_DPM_LEVELS) {
2114                 result = vega10_populate_single_dclock_level(hwmgr,
2115                                 dclk_dpm_table->dpm_levels[j].value,
2116                                 &(pp_table->DclkDid[i]));
2117                 if (result)
2118                         return result;
2119                 i++;
2120         }
2121
2122         for (i = 0; i < dep_table->count; i++) {
2123                 if (dep_table->entries[i].vclk ==
2124                                 vclk_dpm_table->dpm_levels[i].value &&
2125                         dep_table->entries[i].dclk ==
2126                                 dclk_dpm_table->dpm_levels[i].value)
2127                         pp_table->UvdDpmVoltageIndex[i] =
2128                                         dep_table->entries[i].vddcInd;
2129                 else
2130                         return -1;
2131         }
2132
2133         j = i - 1;
2134         while (i < NUM_UVD_DPM_LEVELS) {
2135                 pp_table->UvdDpmVoltageIndex[i] = dep_table->entries[j].vddcInd;
2136                 i++;
2137         }
2138
2139         return 0;
2140 }
2141
2142 static int vega10_populate_clock_stretcher_table(struct pp_hwmgr *hwmgr)
2143 {
2144         struct vega10_hwmgr *data = hwmgr->backend;
2145         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
2146         struct phm_ppt_v2_information *table_info =
2147                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
2148         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
2149                         table_info->vdd_dep_on_sclk;
2150         uint32_t i;
2151
2152         for (i = 0; i < dep_table->count; i++) {
2153                 pp_table->CksEnable[i] = dep_table->entries[i].cks_enable;
2154                 pp_table->CksVidOffset[i] = (uint8_t)(dep_table->entries[i].cks_voffset
2155                                 * VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
2156         }
2157
2158         return 0;
2159 }
2160
2161 static int vega10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
2162 {
2163         struct vega10_hwmgr *data = hwmgr->backend;
2164         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
2165         struct phm_ppt_v2_information *table_info =
2166                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
2167         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
2168                         table_info->vdd_dep_on_sclk;
2169         struct pp_atomfwctrl_avfs_parameters avfs_params = {0};
2170         int result = 0;
2171         uint32_t i;
2172
2173         pp_table->MinVoltageVid = (uint8_t)0xff;
2174         pp_table->MaxVoltageVid = (uint8_t)0;
2175
2176         if (data->smu_features[GNLD_AVFS].supported) {
2177                 result = pp_atomfwctrl_get_avfs_information(hwmgr, &avfs_params);
2178                 if (!result) {
2179                         pp_table->MinVoltageVid = (uint8_t)
2180                                         convert_to_vid((uint16_t)(avfs_params.ulMinVddc));
2181                         pp_table->MaxVoltageVid = (uint8_t)
2182                                         convert_to_vid((uint16_t)(avfs_params.ulMaxVddc));
2183
2184                         pp_table->AConstant[0] = cpu_to_le32(avfs_params.ulMeanNsigmaAcontant0);
2185                         pp_table->AConstant[1] = cpu_to_le32(avfs_params.ulMeanNsigmaAcontant1);
2186                         pp_table->AConstant[2] = cpu_to_le32(avfs_params.ulMeanNsigmaAcontant2);
2187                         pp_table->DC_tol_sigma = cpu_to_le16(avfs_params.usMeanNsigmaDcTolSigma);
2188                         pp_table->Platform_mean = cpu_to_le16(avfs_params.usMeanNsigmaPlatformMean);
2189                         pp_table->Platform_sigma = cpu_to_le16(avfs_params.usMeanNsigmaDcTolSigma);
2190                         pp_table->PSM_Age_CompFactor = cpu_to_le16(avfs_params.usPsmAgeComfactor);
2191
2192                         pp_table->BtcGbVdroopTableCksOff.a0 =
2193                                         cpu_to_le32(avfs_params.ulGbVdroopTableCksoffA0);
2194                         pp_table->BtcGbVdroopTableCksOff.a0_shift = 20;
2195                         pp_table->BtcGbVdroopTableCksOff.a1 =
2196                                         cpu_to_le32(avfs_params.ulGbVdroopTableCksoffA1);
2197                         pp_table->BtcGbVdroopTableCksOff.a1_shift = 20;
2198                         pp_table->BtcGbVdroopTableCksOff.a2 =
2199                                         cpu_to_le32(avfs_params.ulGbVdroopTableCksoffA2);
2200                         pp_table->BtcGbVdroopTableCksOff.a2_shift = 20;
2201
2202                         pp_table->OverrideBtcGbCksOn = avfs_params.ucEnableGbVdroopTableCkson;
2203                         pp_table->BtcGbVdroopTableCksOn.a0 =
2204                                         cpu_to_le32(avfs_params.ulGbVdroopTableCksonA0);
2205                         pp_table->BtcGbVdroopTableCksOn.a0_shift = 20;
2206                         pp_table->BtcGbVdroopTableCksOn.a1 =
2207                                         cpu_to_le32(avfs_params.ulGbVdroopTableCksonA1);
2208                         pp_table->BtcGbVdroopTableCksOn.a1_shift = 20;
2209                         pp_table->BtcGbVdroopTableCksOn.a2 =
2210                                         cpu_to_le32(avfs_params.ulGbVdroopTableCksonA2);
2211                         pp_table->BtcGbVdroopTableCksOn.a2_shift = 20;
2212
2213                         pp_table->AvfsGbCksOn.m1 =
2214                                         cpu_to_le32(avfs_params.ulGbFuseTableCksonM1);
2215                         pp_table->AvfsGbCksOn.m2 =
2216                                         cpu_to_le32(avfs_params.ulGbFuseTableCksonM2);
2217                         pp_table->AvfsGbCksOn.b =
2218                                         cpu_to_le32(avfs_params.ulGbFuseTableCksonB);
2219                         pp_table->AvfsGbCksOn.m1_shift = 24;
2220                         pp_table->AvfsGbCksOn.m2_shift = 12;
2221                         pp_table->AvfsGbCksOn.b_shift = 0;
2222
2223                         pp_table->OverrideAvfsGbCksOn =
2224                                         avfs_params.ucEnableGbFuseTableCkson;
2225                         pp_table->AvfsGbCksOff.m1 =
2226                                         cpu_to_le32(avfs_params.ulGbFuseTableCksoffM1);
2227                         pp_table->AvfsGbCksOff.m2 =
2228                                         cpu_to_le32(avfs_params.ulGbFuseTableCksoffM2);
2229                         pp_table->AvfsGbCksOff.b =
2230                                         cpu_to_le32(avfs_params.ulGbFuseTableCksoffB);
2231                         pp_table->AvfsGbCksOff.m1_shift = 24;
2232                         pp_table->AvfsGbCksOff.m2_shift = 12;
2233                         pp_table->AvfsGbCksOff.b_shift = 0;
2234
2235                         for (i = 0; i < dep_table->count; i++)
2236                                 pp_table->StaticVoltageOffsetVid[i] =
2237                                                 convert_to_vid((uint8_t)(dep_table->entries[i].sclk_offset));
2238
2239                         if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2240                                         data->disp_clk_quad_eqn_a) &&
2241                                 (PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2242                                         data->disp_clk_quad_eqn_b)) {
2243                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m1 =
2244                                                 (int32_t)data->disp_clk_quad_eqn_a;
2245                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m2 =
2246                                                 (int32_t)data->disp_clk_quad_eqn_b;
2247                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].b =
2248                                                 (int32_t)data->disp_clk_quad_eqn_c;
2249                         } else {
2250                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m1 =
2251                                                 (int32_t)avfs_params.ulDispclk2GfxclkM1;
2252                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m2 =
2253                                                 (int32_t)avfs_params.ulDispclk2GfxclkM2;
2254                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].b =
2255                                                 (int32_t)avfs_params.ulDispclk2GfxclkB;
2256                         }
2257
2258                         pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m1_shift = 24;
2259                         pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m2_shift = 12;
2260                         pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].b_shift = 12;
2261
2262                         if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2263                                         data->dcef_clk_quad_eqn_a) &&
2264                                 (PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2265                                         data->dcef_clk_quad_eqn_b)) {
2266                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m1 =
2267                                                 (int32_t)data->dcef_clk_quad_eqn_a;
2268                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m2 =
2269                                                 (int32_t)data->dcef_clk_quad_eqn_b;
2270                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].b =
2271                                                 (int32_t)data->dcef_clk_quad_eqn_c;
2272                         } else {
2273                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m1 =
2274                                                 (int32_t)avfs_params.ulDcefclk2GfxclkM1;
2275                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m2 =
2276                                                 (int32_t)avfs_params.ulDcefclk2GfxclkM2;
2277                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].b =
2278                                                 (int32_t)avfs_params.ulDcefclk2GfxclkB;
2279                         }
2280
2281                         pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m1_shift = 24;
2282                         pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m2_shift = 12;
2283                         pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].b_shift = 12;
2284
2285                         if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2286                                         data->pixel_clk_quad_eqn_a) &&
2287                                 (PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2288                                         data->pixel_clk_quad_eqn_b)) {
2289                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m1 =
2290                                                 (int32_t)data->pixel_clk_quad_eqn_a;
2291                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m2 =
2292                                                 (int32_t)data->pixel_clk_quad_eqn_b;
2293                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].b =
2294                                                 (int32_t)data->pixel_clk_quad_eqn_c;
2295                         } else {
2296                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m1 =
2297                                                 (int32_t)avfs_params.ulPixelclk2GfxclkM1;
2298                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m2 =
2299                                                 (int32_t)avfs_params.ulPixelclk2GfxclkM2;
2300                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].b =
2301                                                 (int32_t)avfs_params.ulPixelclk2GfxclkB;
2302                         }
2303
2304                         pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m1_shift = 24;
2305                         pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m2_shift = 12;
2306                         pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].b_shift = 12;
2307                         if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2308                                         data->phy_clk_quad_eqn_a) &&
2309                                 (PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2310                                         data->phy_clk_quad_eqn_b)) {
2311                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m1 =
2312                                                 (int32_t)data->phy_clk_quad_eqn_a;
2313                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m2 =
2314                                                 (int32_t)data->phy_clk_quad_eqn_b;
2315                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].b =
2316                                                 (int32_t)data->phy_clk_quad_eqn_c;
2317                         } else {
2318                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m1 =
2319                                                 (int32_t)avfs_params.ulPhyclk2GfxclkM1;
2320                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m2 =
2321                                                 (int32_t)avfs_params.ulPhyclk2GfxclkM2;
2322                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].b =
2323                                                 (int32_t)avfs_params.ulPhyclk2GfxclkB;
2324                         }
2325
2326                         pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m1_shift = 24;
2327                         pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m2_shift = 12;
2328                         pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].b_shift = 12;
2329
2330                         pp_table->AcgBtcGbVdroopTable.a0       = avfs_params.ulAcgGbVdroopTableA0;
2331                         pp_table->AcgBtcGbVdroopTable.a0_shift = 20;
2332                         pp_table->AcgBtcGbVdroopTable.a1       = avfs_params.ulAcgGbVdroopTableA1;
2333                         pp_table->AcgBtcGbVdroopTable.a1_shift = 20;
2334                         pp_table->AcgBtcGbVdroopTable.a2       = avfs_params.ulAcgGbVdroopTableA2;
2335                         pp_table->AcgBtcGbVdroopTable.a2_shift = 20;
2336
2337                         pp_table->AcgAvfsGb.m1                   = avfs_params.ulAcgGbFuseTableM1;
2338                         pp_table->AcgAvfsGb.m2                   = avfs_params.ulAcgGbFuseTableM2;
2339                         pp_table->AcgAvfsGb.b                    = avfs_params.ulAcgGbFuseTableB;
2340                         pp_table->AcgAvfsGb.m1_shift             = 24;
2341                         pp_table->AcgAvfsGb.m2_shift             = 12;
2342                         pp_table->AcgAvfsGb.b_shift              = 0;
2343
2344                 } else {
2345                         data->smu_features[GNLD_AVFS].supported = false;
2346                 }
2347         }
2348
2349         return 0;
2350 }
2351
2352 static int vega10_acg_enable(struct pp_hwmgr *hwmgr)
2353 {
2354         struct vega10_hwmgr *data = hwmgr->backend;
2355         uint32_t agc_btc_response;
2356
2357         if (data->smu_features[GNLD_ACG].supported) {
2358                 if (0 == vega10_enable_smc_features(hwmgr, true,
2359                                         data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_bitmap))
2360                         data->smu_features[GNLD_DPM_PREFETCHER].enabled = true;
2361
2362                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_InitializeAcg, NULL);
2363
2364                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgBtc, &agc_btc_response);
2365
2366                 if (1 == agc_btc_response) {
2367                         if (1 == data->acg_loop_state)
2368                                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgInClosedLoop, NULL);
2369                         else if (2 == data->acg_loop_state)
2370                                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgInOpenLoop, NULL);
2371                         if (0 == vega10_enable_smc_features(hwmgr, true,
2372                                 data->smu_features[GNLD_ACG].smu_feature_bitmap))
2373                                         data->smu_features[GNLD_ACG].enabled = true;
2374                 } else {
2375                         pr_info("[ACG_Enable] ACG BTC Returned Failed Status!\n");
2376                         data->smu_features[GNLD_ACG].enabled = false;
2377                 }
2378         }
2379
2380         return 0;
2381 }
2382
2383 static int vega10_acg_disable(struct pp_hwmgr *hwmgr)
2384 {
2385         struct vega10_hwmgr *data = hwmgr->backend;
2386
2387         if (data->smu_features[GNLD_ACG].supported &&
2388             data->smu_features[GNLD_ACG].enabled)
2389                 if (!vega10_enable_smc_features(hwmgr, false,
2390                         data->smu_features[GNLD_ACG].smu_feature_bitmap))
2391                         data->smu_features[GNLD_ACG].enabled = false;
2392
2393         return 0;
2394 }
2395
2396 static int vega10_populate_gpio_parameters(struct pp_hwmgr *hwmgr)
2397 {
2398         struct vega10_hwmgr *data = hwmgr->backend;
2399         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
2400         struct pp_atomfwctrl_gpio_parameters gpio_params = {0};
2401         int result;
2402
2403         result = pp_atomfwctrl_get_gpio_information(hwmgr, &gpio_params);
2404         if (!result) {
2405                 if (PP_CAP(PHM_PlatformCaps_RegulatorHot) &&
2406                     data->registry_data.regulator_hot_gpio_support) {
2407                         pp_table->VR0HotGpio = gpio_params.ucVR0HotGpio;
2408                         pp_table->VR0HotPolarity = gpio_params.ucVR0HotPolarity;
2409                         pp_table->VR1HotGpio = gpio_params.ucVR1HotGpio;
2410                         pp_table->VR1HotPolarity = gpio_params.ucVR1HotPolarity;
2411                 } else {
2412                         pp_table->VR0HotGpio = 0;
2413                         pp_table->VR0HotPolarity = 0;
2414                         pp_table->VR1HotGpio = 0;
2415                         pp_table->VR1HotPolarity = 0;
2416                 }
2417
2418                 if (PP_CAP(PHM_PlatformCaps_AutomaticDCTransition) &&
2419                     data->registry_data.ac_dc_switch_gpio_support) {
2420                         pp_table->AcDcGpio = gpio_params.ucAcDcGpio;
2421                         pp_table->AcDcPolarity = gpio_params.ucAcDcPolarity;
2422                 } else {
2423                         pp_table->AcDcGpio = 0;
2424                         pp_table->AcDcPolarity = 0;
2425                 }
2426         }
2427
2428         return result;
2429 }
2430
2431 static int vega10_avfs_enable(struct pp_hwmgr *hwmgr, bool enable)
2432 {
2433         struct vega10_hwmgr *data = hwmgr->backend;
2434
2435         if (data->smu_features[GNLD_AVFS].supported) {
2436                 /* Already enabled or disabled */
2437                 if (!(enable ^ data->smu_features[GNLD_AVFS].enabled))
2438                         return 0;
2439
2440                 if (enable) {
2441                         PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2442                                         true,
2443                                         data->smu_features[GNLD_AVFS].smu_feature_bitmap),
2444                                         "[avfs_control] Attempt to Enable AVFS feature Failed!",
2445                                         return -1);
2446                         data->smu_features[GNLD_AVFS].enabled = true;
2447                 } else {
2448                         PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2449                                         false,
2450                                         data->smu_features[GNLD_AVFS].smu_feature_bitmap),
2451                                         "[avfs_control] Attempt to Disable AVFS feature Failed!",
2452                                         return -1);
2453                         data->smu_features[GNLD_AVFS].enabled = false;
2454                 }
2455         }
2456
2457         return 0;
2458 }
2459
2460 static int vega10_update_avfs(struct pp_hwmgr *hwmgr)
2461 {
2462         struct vega10_hwmgr *data = hwmgr->backend;
2463
2464         if (data->need_update_dpm_table & DPMTABLE_OD_UPDATE_VDDC) {
2465                 vega10_avfs_enable(hwmgr, false);
2466         } else if (data->need_update_dpm_table) {
2467                 vega10_avfs_enable(hwmgr, false);
2468                 vega10_avfs_enable(hwmgr, true);
2469         } else {
2470                 vega10_avfs_enable(hwmgr, true);
2471         }
2472
2473         return 0;
2474 }
2475
2476 static int vega10_populate_and_upload_avfs_fuse_override(struct pp_hwmgr *hwmgr)
2477 {
2478         int result = 0;
2479
2480         uint64_t serial_number = 0;
2481         uint32_t top32, bottom32;
2482         struct phm_fuses_default fuse;
2483
2484         struct vega10_hwmgr *data = hwmgr->backend;
2485         AvfsFuseOverride_t *avfs_fuse_table = &(data->smc_state_table.avfs_fuse_override_table);
2486
2487         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32, &top32);
2488
2489         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32, &bottom32);
2490
2491         serial_number = ((uint64_t)bottom32 << 32) | top32;
2492
2493         if (pp_override_get_default_fuse_value(serial_number, &fuse) == 0) {
2494                 avfs_fuse_table->VFT0_b  = fuse.VFT0_b;
2495                 avfs_fuse_table->VFT0_m1 = fuse.VFT0_m1;
2496                 avfs_fuse_table->VFT0_m2 = fuse.VFT0_m2;
2497                 avfs_fuse_table->VFT1_b  = fuse.VFT1_b;
2498                 avfs_fuse_table->VFT1_m1 = fuse.VFT1_m1;
2499                 avfs_fuse_table->VFT1_m2 = fuse.VFT1_m2;
2500                 avfs_fuse_table->VFT2_b  = fuse.VFT2_b;
2501                 avfs_fuse_table->VFT2_m1 = fuse.VFT2_m1;
2502                 avfs_fuse_table->VFT2_m2 = fuse.VFT2_m2;
2503                 result = smum_smc_table_manager(hwmgr,  (uint8_t *)avfs_fuse_table,
2504                                                 AVFSFUSETABLE, false);
2505                 PP_ASSERT_WITH_CODE(!result,
2506                         "Failed to upload FuseOVerride!",
2507                         );
2508         }
2509
2510         return result;
2511 }
2512
2513 static void vega10_check_dpm_table_updated(struct pp_hwmgr *hwmgr)
2514 {
2515         struct vega10_hwmgr *data = hwmgr->backend;
2516         struct vega10_odn_dpm_table *odn_table = &(data->odn_dpm_table);
2517         struct phm_ppt_v2_information *table_info = hwmgr->pptable;
2518         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table;
2519         struct phm_ppt_v1_clock_voltage_dependency_table *odn_dep_table;
2520         uint32_t i;
2521
2522         dep_table = table_info->vdd_dep_on_mclk;
2523         odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dep_on_mclk);
2524
2525         for (i = 0; i < dep_table->count; i++) {
2526                 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) {
2527                         data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_MCLK;
2528                         return;
2529                 }
2530         }
2531
2532         dep_table = table_info->vdd_dep_on_sclk;
2533         odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dep_on_sclk);
2534         for (i = 0; i < dep_table->count; i++) {
2535                 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) {
2536                         data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_SCLK;
2537                         return;
2538                 }
2539         }
2540 }
2541
2542 /**
2543  * vega10_init_smc_table - Initializes the SMC table and uploads it
2544  *
2545  * @hwmgr:  the address of the powerplay hardware manager.
2546  * return:  always 0
2547  */
2548 static int vega10_init_smc_table(struct pp_hwmgr *hwmgr)
2549 {
2550         int result;
2551         struct vega10_hwmgr *data = hwmgr->backend;
2552         struct phm_ppt_v2_information *table_info =
2553                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
2554         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
2555         struct pp_atomfwctrl_voltage_table voltage_table;
2556         struct pp_atomfwctrl_bios_boot_up_values boot_up_values;
2557         struct vega10_odn_dpm_table *odn_table = &(data->odn_dpm_table);
2558
2559         result = vega10_setup_default_dpm_tables(hwmgr);
2560         PP_ASSERT_WITH_CODE(!result,
2561                         "Failed to setup default DPM tables!",
2562                         return result);
2563
2564         if (!hwmgr->not_vf)
2565                 return 0;
2566
2567         /* initialize ODN table */
2568         if (hwmgr->od_enabled) {
2569                 if (odn_table->max_vddc) {
2570                         data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK;
2571                         vega10_check_dpm_table_updated(hwmgr);
2572                 } else {
2573                         vega10_odn_initial_default_setting(hwmgr);
2574                 }
2575         }
2576
2577         pp_atomfwctrl_get_voltage_table_v4(hwmgr, VOLTAGE_TYPE_VDDC,
2578                         VOLTAGE_OBJ_SVID2,  &voltage_table);
2579         pp_table->MaxVidStep = voltage_table.max_vid_step;
2580
2581         pp_table->GfxDpmVoltageMode =
2582                         (uint8_t)(table_info->uc_gfx_dpm_voltage_mode);
2583         pp_table->SocDpmVoltageMode =
2584                         (uint8_t)(table_info->uc_soc_dpm_voltage_mode);
2585         pp_table->UclkDpmVoltageMode =
2586                         (uint8_t)(table_info->uc_uclk_dpm_voltage_mode);
2587         pp_table->UvdDpmVoltageMode =
2588                         (uint8_t)(table_info->uc_uvd_dpm_voltage_mode);
2589         pp_table->VceDpmVoltageMode =
2590                         (uint8_t)(table_info->uc_vce_dpm_voltage_mode);
2591         pp_table->Mp0DpmVoltageMode =
2592                         (uint8_t)(table_info->uc_mp0_dpm_voltage_mode);
2593
2594         pp_table->DisplayDpmVoltageMode =
2595                         (uint8_t)(table_info->uc_dcef_dpm_voltage_mode);
2596
2597         data->vddc_voltage_table.psi0_enable = voltage_table.psi0_enable;
2598         data->vddc_voltage_table.psi1_enable = voltage_table.psi1_enable;
2599
2600         if (data->registry_data.ulv_support &&
2601                         table_info->us_ulv_voltage_offset) {
2602                 result = vega10_populate_ulv_state(hwmgr);
2603                 PP_ASSERT_WITH_CODE(!result,
2604                                 "Failed to initialize ULV state!",
2605                                 return result);
2606         }
2607
2608         result = vega10_populate_smc_link_levels(hwmgr);
2609         PP_ASSERT_WITH_CODE(!result,
2610                         "Failed to initialize Link Level!",
2611                         return result);
2612
2613         result = vega10_override_pcie_parameters(hwmgr);
2614         PP_ASSERT_WITH_CODE(!result,
2615                         "Failed to override pcie parameters!",
2616                         return result);
2617
2618         result = vega10_populate_all_graphic_levels(hwmgr);
2619         PP_ASSERT_WITH_CODE(!result,
2620                         "Failed to initialize Graphics Level!",
2621                         return result);
2622
2623         result = vega10_populate_all_memory_levels(hwmgr);
2624         PP_ASSERT_WITH_CODE(!result,
2625                         "Failed to initialize Memory Level!",
2626                         return result);
2627
2628         vega10_populate_vddc_soc_levels(hwmgr);
2629
2630         result = vega10_populate_all_display_clock_levels(hwmgr);
2631         PP_ASSERT_WITH_CODE(!result,
2632                         "Failed to initialize Display Level!",
2633                         return result);
2634
2635         result = vega10_populate_smc_vce_levels(hwmgr);
2636         PP_ASSERT_WITH_CODE(!result,
2637                         "Failed to initialize VCE Level!",
2638                         return result);
2639
2640         result = vega10_populate_smc_uvd_levels(hwmgr);
2641         PP_ASSERT_WITH_CODE(!result,
2642                         "Failed to initialize UVD Level!",
2643                         return result);
2644
2645         if (data->registry_data.clock_stretcher_support) {
2646                 result = vega10_populate_clock_stretcher_table(hwmgr);
2647                 PP_ASSERT_WITH_CODE(!result,
2648                                 "Failed to populate Clock Stretcher Table!",
2649                                 return result);
2650         }
2651
2652         result = pp_atomfwctrl_get_vbios_bootup_values(hwmgr, &boot_up_values);
2653         if (!result) {
2654                 data->vbios_boot_state.vddc     = boot_up_values.usVddc;
2655                 data->vbios_boot_state.vddci    = boot_up_values.usVddci;
2656                 data->vbios_boot_state.mvddc    = boot_up_values.usMvddc;
2657                 data->vbios_boot_state.gfx_clock = boot_up_values.ulGfxClk;
2658                 data->vbios_boot_state.mem_clock = boot_up_values.ulUClk;
2659                 pp_atomfwctrl_get_clk_information_by_clkid(hwmgr,
2660                                 SMU9_SYSPLL0_SOCCLK_ID, 0, &boot_up_values.ulSocClk);
2661
2662                 pp_atomfwctrl_get_clk_information_by_clkid(hwmgr,
2663                                 SMU9_SYSPLL0_DCEFCLK_ID, 0, &boot_up_values.ulDCEFClk);
2664
2665                 data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk;
2666                 data->vbios_boot_state.dcef_clock = boot_up_values.ulDCEFClk;
2667                 if (0 != boot_up_values.usVddc) {
2668                         smum_send_msg_to_smc_with_parameter(hwmgr,
2669                                                 PPSMC_MSG_SetFloorSocVoltage,
2670                                                 (boot_up_values.usVddc * 4),
2671                                                 NULL);
2672                         data->vbios_boot_state.bsoc_vddc_lock = true;
2673                 } else {
2674                         data->vbios_boot_state.bsoc_vddc_lock = false;
2675                 }
2676                 smum_send_msg_to_smc_with_parameter(hwmgr,
2677                                 PPSMC_MSG_SetMinDeepSleepDcefclk,
2678                         (uint32_t)(data->vbios_boot_state.dcef_clock / 100),
2679                                 NULL);
2680         }
2681
2682         result = vega10_populate_avfs_parameters(hwmgr);
2683         PP_ASSERT_WITH_CODE(!result,
2684                         "Failed to initialize AVFS Parameters!",
2685                         return result);
2686
2687         result = vega10_populate_gpio_parameters(hwmgr);
2688         PP_ASSERT_WITH_CODE(!result,
2689                         "Failed to initialize GPIO Parameters!",
2690                         return result);
2691
2692         pp_table->GfxclkAverageAlpha = (uint8_t)
2693                         (data->gfxclk_average_alpha);
2694         pp_table->SocclkAverageAlpha = (uint8_t)
2695                         (data->socclk_average_alpha);
2696         pp_table->UclkAverageAlpha = (uint8_t)
2697                         (data->uclk_average_alpha);
2698         pp_table->GfxActivityAverageAlpha = (uint8_t)
2699                         (data->gfx_activity_average_alpha);
2700
2701         vega10_populate_and_upload_avfs_fuse_override(hwmgr);
2702
2703         result = smum_smc_table_manager(hwmgr, (uint8_t *)pp_table, PPTABLE, false);
2704
2705         PP_ASSERT_WITH_CODE(!result,
2706                         "Failed to upload PPtable!", return result);
2707
2708         result = vega10_avfs_enable(hwmgr, true);
2709         PP_ASSERT_WITH_CODE(!result, "Attempt to enable AVFS feature Failed!",
2710                                         return result);
2711         vega10_acg_enable(hwmgr);
2712
2713         return 0;
2714 }
2715
2716 static int vega10_enable_thermal_protection(struct pp_hwmgr *hwmgr)
2717 {
2718         struct vega10_hwmgr *data = hwmgr->backend;
2719
2720         if (data->smu_features[GNLD_THERMAL].supported) {
2721                 if (data->smu_features[GNLD_THERMAL].enabled)
2722                         pr_info("THERMAL Feature Already enabled!");
2723
2724                 PP_ASSERT_WITH_CODE(
2725                                 !vega10_enable_smc_features(hwmgr,
2726                                 true,
2727                                 data->smu_features[GNLD_THERMAL].smu_feature_bitmap),
2728                                 "Enable THERMAL Feature Failed!",
2729                                 return -1);
2730                 data->smu_features[GNLD_THERMAL].enabled = true;
2731         }
2732
2733         return 0;
2734 }
2735
2736 static int vega10_disable_thermal_protection(struct pp_hwmgr *hwmgr)
2737 {
2738         struct vega10_hwmgr *data = hwmgr->backend;
2739
2740         if (data->smu_features[GNLD_THERMAL].supported) {
2741                 if (!data->smu_features[GNLD_THERMAL].enabled)
2742                         pr_info("THERMAL Feature Already disabled!");
2743
2744                 PP_ASSERT_WITH_CODE(
2745                                 !vega10_enable_smc_features(hwmgr,
2746                                 false,
2747                                 data->smu_features[GNLD_THERMAL].smu_feature_bitmap),
2748                                 "disable THERMAL Feature Failed!",
2749                                 return -1);
2750                 data->smu_features[GNLD_THERMAL].enabled = false;
2751         }
2752
2753         return 0;
2754 }
2755
2756 static int vega10_enable_vrhot_feature(struct pp_hwmgr *hwmgr)
2757 {
2758         struct vega10_hwmgr *data = hwmgr->backend;
2759
2760         if (PP_CAP(PHM_PlatformCaps_RegulatorHot)) {
2761                 if (data->smu_features[GNLD_VR0HOT].supported) {
2762                         PP_ASSERT_WITH_CODE(
2763                                         !vega10_enable_smc_features(hwmgr,
2764                                         true,
2765                                         data->smu_features[GNLD_VR0HOT].smu_feature_bitmap),
2766                                         "Attempt to Enable VR0 Hot feature Failed!",
2767                                         return -1);
2768                         data->smu_features[GNLD_VR0HOT].enabled = true;
2769                 } else {
2770                         if (data->smu_features[GNLD_VR1HOT].supported) {
2771                                 PP_ASSERT_WITH_CODE(
2772                                                 !vega10_enable_smc_features(hwmgr,
2773                                                 true,
2774                                                 data->smu_features[GNLD_VR1HOT].smu_feature_bitmap),
2775                                                 "Attempt to Enable VR0 Hot feature Failed!",
2776                                                 return -1);
2777                                 data->smu_features[GNLD_VR1HOT].enabled = true;
2778                         }
2779                 }
2780         }
2781         return 0;
2782 }
2783
2784 static int vega10_enable_ulv(struct pp_hwmgr *hwmgr)
2785 {
2786         struct vega10_hwmgr *data = hwmgr->backend;
2787
2788         if (data->registry_data.ulv_support) {
2789                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2790                                 true, data->smu_features[GNLD_ULV].smu_feature_bitmap),
2791                                 "Enable ULV Feature Failed!",
2792                                 return -1);
2793                 data->smu_features[GNLD_ULV].enabled = true;
2794         }
2795
2796         return 0;
2797 }
2798
2799 static int vega10_disable_ulv(struct pp_hwmgr *hwmgr)
2800 {
2801         struct vega10_hwmgr *data = hwmgr->backend;
2802
2803         if (data->registry_data.ulv_support) {
2804                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2805                                 false, data->smu_features[GNLD_ULV].smu_feature_bitmap),
2806                                 "disable ULV Feature Failed!",
2807                                 return -EINVAL);
2808                 data->smu_features[GNLD_ULV].enabled = false;
2809         }
2810
2811         return 0;
2812 }
2813
2814 static int vega10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
2815 {
2816         struct vega10_hwmgr *data = hwmgr->backend;
2817
2818         if (data->smu_features[GNLD_DS_GFXCLK].supported) {
2819                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2820                                 true, data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap),
2821                                 "Attempt to Enable DS_GFXCLK Feature Failed!",
2822                                 return -EINVAL);
2823                 data->smu_features[GNLD_DS_GFXCLK].enabled = true;
2824         }
2825
2826         if (data->smu_features[GNLD_DS_SOCCLK].supported) {
2827                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2828                                 true, data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap),
2829                                 "Attempt to Enable DS_SOCCLK Feature Failed!",
2830                                 return -EINVAL);
2831                 data->smu_features[GNLD_DS_SOCCLK].enabled = true;
2832         }
2833
2834         if (data->smu_features[GNLD_DS_LCLK].supported) {
2835                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2836                                 true, data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap),
2837                                 "Attempt to Enable DS_LCLK Feature Failed!",
2838                                 return -EINVAL);
2839                 data->smu_features[GNLD_DS_LCLK].enabled = true;
2840         }
2841
2842         if (data->smu_features[GNLD_DS_DCEFCLK].supported) {
2843                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2844                                 true, data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap),
2845                                 "Attempt to Enable DS_DCEFCLK Feature Failed!",
2846                                 return -EINVAL);
2847                 data->smu_features[GNLD_DS_DCEFCLK].enabled = true;
2848         }
2849
2850         return 0;
2851 }
2852
2853 static int vega10_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
2854 {
2855         struct vega10_hwmgr *data = hwmgr->backend;
2856
2857         if (data->smu_features[GNLD_DS_GFXCLK].supported) {
2858                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2859                                 false, data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap),
2860                                 "Attempt to disable DS_GFXCLK Feature Failed!",
2861                                 return -EINVAL);
2862                 data->smu_features[GNLD_DS_GFXCLK].enabled = false;
2863         }
2864
2865         if (data->smu_features[GNLD_DS_SOCCLK].supported) {
2866                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2867                                 false, data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap),
2868                                 "Attempt to disable DS_ Feature Failed!",
2869                                 return -EINVAL);
2870                 data->smu_features[GNLD_DS_SOCCLK].enabled = false;
2871         }
2872
2873         if (data->smu_features[GNLD_DS_LCLK].supported) {
2874                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2875                                 false, data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap),
2876                                 "Attempt to disable DS_LCLK Feature Failed!",
2877                                 return -EINVAL);
2878                 data->smu_features[GNLD_DS_LCLK].enabled = false;
2879         }
2880
2881         if (data->smu_features[GNLD_DS_DCEFCLK].supported) {
2882                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2883                                 false, data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap),
2884                                 "Attempt to disable DS_DCEFCLK Feature Failed!",
2885                                 return -EINVAL);
2886                 data->smu_features[GNLD_DS_DCEFCLK].enabled = false;
2887         }
2888
2889         return 0;
2890 }
2891
2892 static int vega10_stop_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap)
2893 {
2894         struct vega10_hwmgr *data = hwmgr->backend;
2895         uint32_t i, feature_mask = 0;
2896
2897         if (!hwmgr->not_vf)
2898                 return 0;
2899
2900         if(data->smu_features[GNLD_LED_DISPLAY].supported == true){
2901                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2902                                 false, data->smu_features[GNLD_LED_DISPLAY].smu_feature_bitmap),
2903                 "Attempt to disable LED DPM feature failed!", return -EINVAL);
2904                 data->smu_features[GNLD_LED_DISPLAY].enabled = false;
2905         }
2906
2907         for (i = 0; i < GNLD_DPM_MAX; i++) {
2908                 if (data->smu_features[i].smu_feature_bitmap & bitmap) {
2909                         if (data->smu_features[i].supported) {
2910                                 if (data->smu_features[i].enabled) {
2911                                         feature_mask |= data->smu_features[i].
2912                                                         smu_feature_bitmap;
2913                                         data->smu_features[i].enabled = false;
2914                                 }
2915                         }
2916                 }
2917         }
2918
2919         vega10_enable_smc_features(hwmgr, false, feature_mask);
2920
2921         return 0;
2922 }
2923
2924 /**
2925  * vega10_start_dpm - Tell SMC to enabled the supported DPMs.
2926  *
2927  * @hwmgr:   the address of the powerplay hardware manager.
2928  * @bitmap:  bitmap for the features to enabled.
2929  * return:  0 on at least one DPM is successfully enabled.
2930  */
2931 static int vega10_start_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap)
2932 {
2933         struct vega10_hwmgr *data = hwmgr->backend;
2934         uint32_t i, feature_mask = 0;
2935
2936         for (i = 0; i < GNLD_DPM_MAX; i++) {
2937                 if (data->smu_features[i].smu_feature_bitmap & bitmap) {
2938                         if (data->smu_features[i].supported) {
2939                                 if (!data->smu_features[i].enabled) {
2940                                         feature_mask |= data->smu_features[i].
2941                                                         smu_feature_bitmap;
2942                                         data->smu_features[i].enabled = true;
2943                                 }
2944                         }
2945                 }
2946         }
2947
2948         if (vega10_enable_smc_features(hwmgr,
2949                         true, feature_mask)) {
2950                 for (i = 0; i < GNLD_DPM_MAX; i++) {
2951                         if (data->smu_features[i].smu_feature_bitmap &
2952                                         feature_mask)
2953                                 data->smu_features[i].enabled = false;
2954                 }
2955         }
2956
2957         if(data->smu_features[GNLD_LED_DISPLAY].supported == true){
2958                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2959                                 true, data->smu_features[GNLD_LED_DISPLAY].smu_feature_bitmap),
2960                 "Attempt to Enable LED DPM feature Failed!", return -EINVAL);
2961                 data->smu_features[GNLD_LED_DISPLAY].enabled = true;
2962         }
2963
2964         if (data->vbios_boot_state.bsoc_vddc_lock) {
2965                 smum_send_msg_to_smc_with_parameter(hwmgr,
2966                                                 PPSMC_MSG_SetFloorSocVoltage, 0,
2967                                                 NULL);
2968                 data->vbios_boot_state.bsoc_vddc_lock = false;
2969         }
2970
2971         if (PP_CAP(PHM_PlatformCaps_Falcon_QuickTransition)) {
2972                 if (data->smu_features[GNLD_ACDC].supported) {
2973                         PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2974                                         true, data->smu_features[GNLD_ACDC].smu_feature_bitmap),
2975                                         "Attempt to Enable DS_GFXCLK Feature Failed!",
2976                                         return -1);
2977                         data->smu_features[GNLD_ACDC].enabled = true;
2978                 }
2979         }
2980
2981         if (data->registry_data.pcie_dpm_key_disabled) {
2982                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2983                                 false, data->smu_features[GNLD_DPM_LINK].smu_feature_bitmap),
2984                 "Attempt to Disable Link DPM feature Failed!", return -EINVAL);
2985                 data->smu_features[GNLD_DPM_LINK].enabled = false;
2986                 data->smu_features[GNLD_DPM_LINK].supported = false;
2987         }
2988
2989         return 0;
2990 }
2991
2992
2993 static int vega10_enable_disable_PCC_limit_feature(struct pp_hwmgr *hwmgr, bool enable)
2994 {
2995         struct vega10_hwmgr *data = hwmgr->backend;
2996
2997         if (data->smu_features[GNLD_PCC_LIMIT].supported) {
2998                 if (enable == data->smu_features[GNLD_PCC_LIMIT].enabled)
2999                         pr_info("GNLD_PCC_LIMIT has been %s \n", enable ? "enabled" : "disabled");
3000                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
3001                                 enable, data->smu_features[GNLD_PCC_LIMIT].smu_feature_bitmap),
3002                                 "Attempt to Enable PCC Limit feature Failed!",
3003                                 return -EINVAL);
3004                 data->smu_features[GNLD_PCC_LIMIT].enabled = enable;
3005         }
3006
3007         return 0;
3008 }
3009
3010 static void vega10_populate_umdpstate_clocks(struct pp_hwmgr *hwmgr)
3011 {
3012         struct phm_ppt_v2_information *table_info =
3013                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
3014
3015         if (table_info->vdd_dep_on_sclk->count > VEGA10_UMD_PSTATE_GFXCLK_LEVEL &&
3016             table_info->vdd_dep_on_mclk->count > VEGA10_UMD_PSTATE_MCLK_LEVEL) {
3017                 hwmgr->pstate_sclk = table_info->vdd_dep_on_sclk->entries[VEGA10_UMD_PSTATE_GFXCLK_LEVEL].clk;
3018                 hwmgr->pstate_mclk = table_info->vdd_dep_on_mclk->entries[VEGA10_UMD_PSTATE_MCLK_LEVEL].clk;
3019         } else {
3020                 hwmgr->pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;
3021                 hwmgr->pstate_mclk = table_info->vdd_dep_on_mclk->entries[0].clk;
3022         }
3023
3024         hwmgr->pstate_sclk_peak = table_info->vdd_dep_on_sclk->entries[table_info->vdd_dep_on_sclk->count - 1].clk;
3025         hwmgr->pstate_mclk_peak = table_info->vdd_dep_on_mclk->entries[table_info->vdd_dep_on_mclk->count - 1].clk;
3026
3027         /* make sure the output is in Mhz */
3028         hwmgr->pstate_sclk /= 100;
3029         hwmgr->pstate_mclk /= 100;
3030         hwmgr->pstate_sclk_peak /= 100;
3031         hwmgr->pstate_mclk_peak /= 100;
3032 }
3033
3034 static int vega10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
3035 {
3036         struct vega10_hwmgr *data = hwmgr->backend;
3037         int tmp_result, result = 0;
3038
3039         if (hwmgr->not_vf) {
3040                 vega10_enable_disable_PCC_limit_feature(hwmgr, true);
3041
3042                 smum_send_msg_to_smc_with_parameter(hwmgr,
3043                         PPSMC_MSG_ConfigureTelemetry, data->config_telemetry,
3044                         NULL);
3045
3046                 tmp_result = vega10_construct_voltage_tables(hwmgr);
3047                 PP_ASSERT_WITH_CODE(!tmp_result,
3048                                     "Failed to construct voltage tables!",
3049                                     result = tmp_result);
3050         }
3051
3052         if (hwmgr->not_vf || hwmgr->pp_one_vf) {
3053                 tmp_result = vega10_init_smc_table(hwmgr);
3054                 PP_ASSERT_WITH_CODE(!tmp_result,
3055                                     "Failed to initialize SMC table!",
3056                                     result = tmp_result);
3057         }
3058
3059         if (hwmgr->not_vf) {
3060                 if (PP_CAP(PHM_PlatformCaps_ThermalController)) {
3061                         tmp_result = vega10_enable_thermal_protection(hwmgr);
3062                         PP_ASSERT_WITH_CODE(!tmp_result,
3063                                             "Failed to enable thermal protection!",
3064                                             result = tmp_result);
3065                 }
3066
3067                 tmp_result = vega10_enable_vrhot_feature(hwmgr);
3068                 PP_ASSERT_WITH_CODE(!tmp_result,
3069                                     "Failed to enable VR hot feature!",
3070                                     result = tmp_result);
3071
3072                 tmp_result = vega10_enable_deep_sleep_master_switch(hwmgr);
3073                 PP_ASSERT_WITH_CODE(!tmp_result,
3074                                     "Failed to enable deep sleep master switch!",
3075                                     result = tmp_result);
3076         }
3077
3078         if (hwmgr->not_vf) {
3079                 tmp_result = vega10_start_dpm(hwmgr, SMC_DPM_FEATURES);
3080                 PP_ASSERT_WITH_CODE(!tmp_result,
3081                                     "Failed to start DPM!", result = tmp_result);
3082         }
3083
3084         if (hwmgr->not_vf) {
3085                 /* enable didt, do not abort if failed didt */
3086                 tmp_result = vega10_enable_didt_config(hwmgr);
3087                 PP_ASSERT(!tmp_result,
3088                           "Failed to enable didt config!");
3089         }
3090
3091         tmp_result = vega10_enable_power_containment(hwmgr);
3092         PP_ASSERT_WITH_CODE(!tmp_result,
3093                             "Failed to enable power containment!",
3094                             result = tmp_result);
3095
3096         if (hwmgr->not_vf) {
3097                 tmp_result = vega10_power_control_set_level(hwmgr);
3098                 PP_ASSERT_WITH_CODE(!tmp_result,
3099                                     "Failed to power control set level!",
3100                                     result = tmp_result);
3101
3102                 tmp_result = vega10_enable_ulv(hwmgr);
3103                 PP_ASSERT_WITH_CODE(!tmp_result,
3104                                     "Failed to enable ULV!",
3105                                     result = tmp_result);
3106         }
3107
3108         vega10_populate_umdpstate_clocks(hwmgr);
3109
3110         return result;
3111 }
3112
3113 static int vega10_get_power_state_size(struct pp_hwmgr *hwmgr)
3114 {
3115         return sizeof(struct vega10_power_state);
3116 }
3117
3118 static int vega10_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
3119                 void *state, struct pp_power_state *power_state,
3120                 void *pp_table, uint32_t classification_flag)
3121 {
3122         ATOM_Vega10_GFXCLK_Dependency_Record_V2 *patom_record_V2;
3123         struct vega10_power_state *vega10_ps =
3124                         cast_phw_vega10_power_state(&(power_state->hardware));
3125         struct vega10_performance_level *performance_level;
3126         ATOM_Vega10_State *state_entry = (ATOM_Vega10_State *)state;
3127         ATOM_Vega10_POWERPLAYTABLE *powerplay_table =
3128                         (ATOM_Vega10_POWERPLAYTABLE *)pp_table;
3129         ATOM_Vega10_SOCCLK_Dependency_Table *socclk_dep_table =
3130                         (ATOM_Vega10_SOCCLK_Dependency_Table *)
3131                         (((unsigned long)powerplay_table) +
3132                         le16_to_cpu(powerplay_table->usSocclkDependencyTableOffset));
3133         ATOM_Vega10_GFXCLK_Dependency_Table *gfxclk_dep_table =
3134                         (ATOM_Vega10_GFXCLK_Dependency_Table *)
3135                         (((unsigned long)powerplay_table) +
3136                         le16_to_cpu(powerplay_table->usGfxclkDependencyTableOffset));
3137         ATOM_Vega10_MCLK_Dependency_Table *mclk_dep_table =
3138                         (ATOM_Vega10_MCLK_Dependency_Table *)
3139                         (((unsigned long)powerplay_table) +
3140                         le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
3141
3142
3143         /* The following fields are not initialized here:
3144          * id orderedList allStatesList
3145          */
3146         power_state->classification.ui_label =
3147                         (le16_to_cpu(state_entry->usClassification) &
3148                         ATOM_PPLIB_CLASSIFICATION_UI_MASK) >>
3149                         ATOM_PPLIB_CLASSIFICATION_UI_SHIFT;
3150         power_state->classification.flags = classification_flag;
3151         /* NOTE: There is a classification2 flag in BIOS
3152          * that is not being used right now
3153          */
3154         power_state->classification.temporary_state = false;
3155         power_state->classification.to_be_deleted = false;
3156
3157         power_state->validation.disallowOnDC =
3158                         ((le32_to_cpu(state_entry->ulCapsAndSettings) &
3159                                         ATOM_Vega10_DISALLOW_ON_DC) != 0);
3160
3161         power_state->display.disableFrameModulation = false;
3162         power_state->display.limitRefreshrate = false;
3163         power_state->display.enableVariBright =
3164                         ((le32_to_cpu(state_entry->ulCapsAndSettings) &
3165                                         ATOM_Vega10_ENABLE_VARIBRIGHT) != 0);
3166
3167         power_state->validation.supportedPowerLevels = 0;
3168         power_state->uvd_clocks.VCLK = 0;
3169         power_state->uvd_clocks.DCLK = 0;
3170         power_state->temperatures.min = 0;
3171         power_state->temperatures.max = 0;
3172
3173         performance_level = &(vega10_ps->performance_levels
3174                         [vega10_ps->performance_level_count++]);
3175
3176         PP_ASSERT_WITH_CODE(
3177                         (vega10_ps->performance_level_count <
3178                                         NUM_GFXCLK_DPM_LEVELS),
3179                         "Performance levels exceeds SMC limit!",
3180                         return -1);
3181
3182         PP_ASSERT_WITH_CODE(
3183                         (vega10_ps->performance_level_count <
3184                                         hwmgr->platform_descriptor.
3185                                         hardwareActivityPerformanceLevels),
3186                         "Performance levels exceeds Driver limit!",
3187                         return -1);
3188
3189         /* Performance levels are arranged from low to high. */
3190         performance_level->soc_clock = socclk_dep_table->entries
3191                         [state_entry->ucSocClockIndexLow].ulClk;
3192         performance_level->gfx_clock = gfxclk_dep_table->entries
3193                         [state_entry->ucGfxClockIndexLow].ulClk;
3194         performance_level->mem_clock = mclk_dep_table->entries
3195                         [state_entry->ucMemClockIndexLow].ulMemClk;
3196
3197         performance_level = &(vega10_ps->performance_levels
3198                                 [vega10_ps->performance_level_count++]);
3199         performance_level->soc_clock = socclk_dep_table->entries
3200                                 [state_entry->ucSocClockIndexHigh].ulClk;
3201         if (gfxclk_dep_table->ucRevId == 0) {
3202                 /* under vega10 pp one vf mode, the gfx clk dpm need be lower
3203                  * to level-4 due to the limited 110w-power
3204                  */
3205                 if (hwmgr->pp_one_vf && (state_entry->ucGfxClockIndexHigh > 0))
3206                         performance_level->gfx_clock =
3207                                 gfxclk_dep_table->entries[4].ulClk;
3208                 else
3209                         performance_level->gfx_clock = gfxclk_dep_table->entries
3210                                 [state_entry->ucGfxClockIndexHigh].ulClk;
3211         } else if (gfxclk_dep_table->ucRevId == 1) {
3212                 patom_record_V2 = (ATOM_Vega10_GFXCLK_Dependency_Record_V2 *)gfxclk_dep_table->entries;
3213                 if (hwmgr->pp_one_vf && (state_entry->ucGfxClockIndexHigh > 0))
3214                         performance_level->gfx_clock = patom_record_V2[4].ulClk;
3215                 else
3216                         performance_level->gfx_clock =
3217                                 patom_record_V2[state_entry->ucGfxClockIndexHigh].ulClk;
3218         }
3219
3220         performance_level->mem_clock = mclk_dep_table->entries
3221                         [state_entry->ucMemClockIndexHigh].ulMemClk;
3222         return 0;
3223 }
3224
3225 static int vega10_get_pp_table_entry(struct pp_hwmgr *hwmgr,
3226                 unsigned long entry_index, struct pp_power_state *state)
3227 {
3228         int result;
3229         struct vega10_power_state *vega10_ps;
3230
3231         state->hardware.magic = PhwVega10_Magic;
3232
3233         vega10_ps = cast_phw_vega10_power_state(&state->hardware);
3234
3235         result = vega10_get_powerplay_table_entry(hwmgr, entry_index, state,
3236                         vega10_get_pp_table_entry_callback_func);
3237         if (result)
3238                 return result;
3239
3240         /*
3241          * This is the earliest time we have all the dependency table
3242          * and the VBIOS boot state
3243          */
3244         /* set DC compatible flag if this state supports DC */
3245         if (!state->validation.disallowOnDC)
3246                 vega10_ps->dc_compatible = true;
3247
3248         vega10_ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
3249         vega10_ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
3250
3251         return 0;
3252 }
3253
3254 static int vega10_patch_boot_state(struct pp_hwmgr *hwmgr,
3255              struct pp_hw_power_state *hw_ps)
3256 {
3257         return 0;
3258 }
3259
3260 static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
3261                                 struct pp_power_state  *request_ps,
3262                         const struct pp_power_state *current_ps)
3263 {
3264         struct amdgpu_device *adev = hwmgr->adev;
3265         struct vega10_power_state *vega10_ps =
3266                                 cast_phw_vega10_power_state(&request_ps->hardware);
3267         uint32_t sclk;
3268         uint32_t mclk;
3269         struct PP_Clocks minimum_clocks = {0};
3270         bool disable_mclk_switching;
3271         bool disable_mclk_switching_for_frame_lock;
3272         bool disable_mclk_switching_for_vr;
3273         bool force_mclk_high;
3274         const struct phm_clock_and_voltage_limits *max_limits;
3275         uint32_t i;
3276         struct vega10_hwmgr *data = hwmgr->backend;
3277         struct phm_ppt_v2_information *table_info =
3278                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
3279         int32_t count;
3280         uint32_t stable_pstate_sclk_dpm_percentage;
3281         uint32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
3282         uint32_t latency;
3283
3284         data->battery_state = (PP_StateUILabel_Battery ==
3285                         request_ps->classification.ui_label);
3286
3287         if (vega10_ps->performance_level_count != 2)
3288                 pr_info("VI should always have 2 performance levels");
3289
3290         max_limits = adev->pm.ac_power ?
3291                         &(hwmgr->dyn_state.max_clock_voltage_on_ac) :
3292                         &(hwmgr->dyn_state.max_clock_voltage_on_dc);
3293
3294         /* Cap clock DPM tables at DC MAX if it is in DC. */
3295         if (!adev->pm.ac_power) {
3296                 for (i = 0; i < vega10_ps->performance_level_count; i++) {
3297                         if (vega10_ps->performance_levels[i].mem_clock >
3298                                 max_limits->mclk)
3299                                 vega10_ps->performance_levels[i].mem_clock =
3300                                                 max_limits->mclk;
3301                         if (vega10_ps->performance_levels[i].gfx_clock >
3302                                 max_limits->sclk)
3303                                 vega10_ps->performance_levels[i].gfx_clock =
3304                                                 max_limits->sclk;
3305                 }
3306         }
3307
3308         /* result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
3309         minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock;
3310         minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
3311
3312         if (PP_CAP(PHM_PlatformCaps_StablePState)) {
3313                 stable_pstate_sclk_dpm_percentage =
3314                         data->registry_data.stable_pstate_sclk_dpm_percentage;
3315                 PP_ASSERT_WITH_CODE(
3316                         data->registry_data.stable_pstate_sclk_dpm_percentage >= 1 &&
3317                         data->registry_data.stable_pstate_sclk_dpm_percentage <= 100,
3318                         "percent sclk value must range from 1% to 100%, setting default value",
3319                         stable_pstate_sclk_dpm_percentage = 75);
3320
3321                 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
3322                 stable_pstate_sclk = (max_limits->sclk *
3323                                 stable_pstate_sclk_dpm_percentage) / 100;
3324
3325                 for (count = table_info->vdd_dep_on_sclk->count - 1;
3326                                 count >= 0; count--) {
3327                         if (stable_pstate_sclk >=
3328                                         table_info->vdd_dep_on_sclk->entries[count].clk) {
3329                                 stable_pstate_sclk =
3330                                                 table_info->vdd_dep_on_sclk->entries[count].clk;
3331                                 break;
3332                         }
3333                 }
3334
3335                 if (count < 0)
3336                         stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;
3337
3338                 stable_pstate_mclk = max_limits->mclk;
3339
3340                 minimum_clocks.engineClock = stable_pstate_sclk;
3341                 minimum_clocks.memoryClock = stable_pstate_mclk;
3342         }
3343
3344         disable_mclk_switching_for_frame_lock =
3345                 PP_CAP(PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
3346         disable_mclk_switching_for_vr =
3347                 PP_CAP(PHM_PlatformCaps_DisableMclkSwitchForVR);
3348         force_mclk_high = PP_CAP(PHM_PlatformCaps_ForceMclkHigh);
3349
3350         if (hwmgr->display_config->num_display == 0)
3351                 disable_mclk_switching = false;
3352         else
3353                 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) &&
3354                                           !hwmgr->display_config->multi_monitor_in_sync) ||
3355                         disable_mclk_switching_for_frame_lock ||
3356                         disable_mclk_switching_for_vr ||
3357                         force_mclk_high;
3358
3359         sclk = vega10_ps->performance_levels[0].gfx_clock;
3360         mclk = vega10_ps->performance_levels[0].mem_clock;
3361
3362         if (sclk < minimum_clocks.engineClock)
3363                 sclk = (minimum_clocks.engineClock > max_limits->sclk) ?
3364                                 max_limits->sclk : minimum_clocks.engineClock;
3365
3366         if (mclk < minimum_clocks.memoryClock)
3367                 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ?
3368                                 max_limits->mclk : minimum_clocks.memoryClock;
3369
3370         vega10_ps->performance_levels[0].gfx_clock = sclk;
3371         vega10_ps->performance_levels[0].mem_clock = mclk;
3372
3373         if (vega10_ps->performance_levels[1].gfx_clock <
3374                         vega10_ps->performance_levels[0].gfx_clock)
3375                 vega10_ps->performance_levels[0].gfx_clock =
3376                                 vega10_ps->performance_levels[1].gfx_clock;
3377
3378         if (disable_mclk_switching) {
3379                 /* Set Mclk the max of level 0 and level 1 */
3380                 if (mclk < vega10_ps->performance_levels[1].mem_clock)
3381                         mclk = vega10_ps->performance_levels[1].mem_clock;
3382
3383                 /* Find the lowest MCLK frequency that is within
3384                  * the tolerable latency defined in DAL
3385                  */
3386                 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency;
3387                 for (i = 0; i < data->mclk_latency_table.count; i++) {
3388                         if ((data->mclk_latency_table.entries[i].latency <= latency) &&
3389                                 (data->mclk_latency_table.entries[i].frequency >=
3390                                                 vega10_ps->performance_levels[0].mem_clock) &&
3391                                 (data->mclk_latency_table.entries[i].frequency <=
3392                                                 vega10_ps->performance_levels[1].mem_clock))
3393                                 mclk = data->mclk_latency_table.entries[i].frequency;
3394                 }
3395                 vega10_ps->performance_levels[0].mem_clock = mclk;
3396         } else {
3397                 if (vega10_ps->performance_levels[1].mem_clock <
3398                                 vega10_ps->performance_levels[0].mem_clock)
3399                         vega10_ps->performance_levels[0].mem_clock =
3400                                         vega10_ps->performance_levels[1].mem_clock;
3401         }
3402
3403         if (PP_CAP(PHM_PlatformCaps_StablePState)) {
3404                 for (i = 0; i < vega10_ps->performance_level_count; i++) {
3405                         vega10_ps->performance_levels[i].gfx_clock = stable_pstate_sclk;
3406                         vega10_ps->performance_levels[i].mem_clock = stable_pstate_mclk;
3407                 }
3408         }
3409
3410         return 0;
3411 }
3412
3413 static int vega10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
3414 {
3415         struct vega10_hwmgr *data = hwmgr->backend;
3416         const struct phm_set_power_state_input *states =
3417                         (const struct phm_set_power_state_input *)input;
3418         const struct vega10_power_state *vega10_ps =
3419                         cast_const_phw_vega10_power_state(states->pnew_state);
3420         struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
3421         uint32_t sclk = vega10_ps->performance_levels
3422                         [vega10_ps->performance_level_count - 1].gfx_clock;
3423         struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
3424         uint32_t mclk = vega10_ps->performance_levels
3425                         [vega10_ps->performance_level_count - 1].mem_clock;
3426         uint32_t i;
3427
3428         for (i = 0; i < sclk_table->count; i++) {
3429                 if (sclk == sclk_table->dpm_levels[i].value)
3430                         break;
3431         }
3432
3433         if (i >= sclk_table->count) {
3434                 if (sclk > sclk_table->dpm_levels[i-1].value) {
3435                         data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
3436                         sclk_table->dpm_levels[i-1].value = sclk;
3437                 }
3438         }
3439
3440         for (i = 0; i < mclk_table->count; i++) {
3441                 if (mclk == mclk_table->dpm_levels[i].value)
3442                         break;
3443         }
3444
3445         if (i >= mclk_table->count) {
3446                 if (mclk > mclk_table->dpm_levels[i-1].value) {
3447                         data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
3448                         mclk_table->dpm_levels[i-1].value = mclk;
3449                 }
3450         }
3451
3452         if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
3453                 data->need_update_dpm_table |= DPMTABLE_UPDATE_MCLK;
3454
3455         return 0;
3456 }
3457
3458 static int vega10_populate_and_upload_sclk_mclk_dpm_levels(
3459                 struct pp_hwmgr *hwmgr, const void *input)
3460 {
3461         int result = 0;
3462         struct vega10_hwmgr *data = hwmgr->backend;
3463         struct vega10_dpm_table *dpm_table = &data->dpm_table;
3464         struct vega10_odn_dpm_table *odn_table = &data->odn_dpm_table;
3465         struct vega10_odn_clock_voltage_dependency_table *odn_clk_table = &odn_table->vdd_dep_on_sclk;
3466         int count;
3467
3468         if (!data->need_update_dpm_table)
3469                 return 0;
3470
3471         if (hwmgr->od_enabled && data->need_update_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
3472                 for (count = 0; count < dpm_table->gfx_table.count; count++)
3473                         dpm_table->gfx_table.dpm_levels[count].value = odn_clk_table->entries[count].clk;
3474         }
3475
3476         odn_clk_table = &odn_table->vdd_dep_on_mclk;
3477         if (hwmgr->od_enabled && data->need_update_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
3478                 for (count = 0; count < dpm_table->mem_table.count; count++)
3479                         dpm_table->mem_table.dpm_levels[count].value = odn_clk_table->entries[count].clk;
3480         }
3481
3482         if (data->need_update_dpm_table &
3483                         (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK | DPMTABLE_UPDATE_SOCCLK)) {
3484                 result = vega10_populate_all_graphic_levels(hwmgr);
3485                 PP_ASSERT_WITH_CODE((0 == result),
3486                                 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
3487                                 return result);
3488         }
3489
3490         if (data->need_update_dpm_table &
3491                         (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) {
3492                 result = vega10_populate_all_memory_levels(hwmgr);
3493                 PP_ASSERT_WITH_CODE((0 == result),
3494                                 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
3495                                 return result);
3496         }
3497
3498         vega10_populate_vddc_soc_levels(hwmgr);
3499
3500         return result;
3501 }
3502
3503 static int vega10_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
3504                 struct vega10_single_dpm_table *dpm_table,
3505                 uint32_t low_limit, uint32_t high_limit)
3506 {
3507         uint32_t i;
3508
3509         for (i = 0; i < dpm_table->count; i++) {
3510                 if ((dpm_table->dpm_levels[i].value < low_limit) ||
3511                     (dpm_table->dpm_levels[i].value > high_limit))
3512                         dpm_table->dpm_levels[i].enabled = false;
3513                 else
3514                         dpm_table->dpm_levels[i].enabled = true;
3515         }
3516         return 0;
3517 }
3518
3519 static int vega10_trim_single_dpm_states_with_mask(struct pp_hwmgr *hwmgr,
3520                 struct vega10_single_dpm_table *dpm_table,
3521                 uint32_t low_limit, uint32_t high_limit,
3522                 uint32_t disable_dpm_mask)
3523 {
3524         uint32_t i;
3525
3526         for (i = 0; i < dpm_table->count; i++) {
3527                 if ((dpm_table->dpm_levels[i].value < low_limit) ||
3528                     (dpm_table->dpm_levels[i].value > high_limit))
3529                         dpm_table->dpm_levels[i].enabled = false;
3530                 else if (!((1 << i) & disable_dpm_mask))
3531                         dpm_table->dpm_levels[i].enabled = false;
3532                 else
3533                         dpm_table->dpm_levels[i].enabled = true;
3534         }
3535         return 0;
3536 }
3537
3538 static int vega10_trim_dpm_states(struct pp_hwmgr *hwmgr,
3539                 const struct vega10_power_state *vega10_ps)
3540 {
3541         struct vega10_hwmgr *data = hwmgr->backend;
3542         uint32_t high_limit_count;
3543
3544         PP_ASSERT_WITH_CODE((vega10_ps->performance_level_count >= 1),
3545                         "power state did not have any performance level",
3546                         return -1);
3547
3548         high_limit_count = (vega10_ps->performance_level_count == 1) ? 0 : 1;
3549
3550         vega10_trim_single_dpm_states(hwmgr,
3551                         &(data->dpm_table.soc_table),
3552                         vega10_ps->performance_levels[0].soc_clock,
3553                         vega10_ps->performance_levels[high_limit_count].soc_clock);
3554
3555         vega10_trim_single_dpm_states_with_mask(hwmgr,
3556                         &(data->dpm_table.gfx_table),
3557                         vega10_ps->performance_levels[0].gfx_clock,
3558                         vega10_ps->performance_levels[high_limit_count].gfx_clock,
3559                         data->disable_dpm_mask);
3560
3561         vega10_trim_single_dpm_states(hwmgr,
3562                         &(data->dpm_table.mem_table),
3563                         vega10_ps->performance_levels[0].mem_clock,
3564                         vega10_ps->performance_levels[high_limit_count].mem_clock);
3565
3566         return 0;
3567 }
3568
3569 static uint32_t vega10_find_lowest_dpm_level(
3570                 struct vega10_single_dpm_table *table)
3571 {
3572         uint32_t i;
3573
3574         for (i = 0; i < table->count; i++) {
3575                 if (table->dpm_levels[i].enabled)
3576                         break;
3577         }
3578
3579         return i;
3580 }
3581
3582 static uint32_t vega10_find_highest_dpm_level(
3583                 struct vega10_single_dpm_table *table)
3584 {
3585         uint32_t i = 0;
3586
3587         if (table->count <= MAX_REGULAR_DPM_NUMBER) {
3588                 for (i = table->count; i > 0; i--) {
3589                         if (table->dpm_levels[i - 1].enabled)
3590                                 return i - 1;
3591                 }
3592         } else {
3593                 pr_info("DPM Table Has Too Many Entries!");
3594                 return MAX_REGULAR_DPM_NUMBER - 1;
3595         }
3596
3597         return i;
3598 }
3599
3600 static void vega10_apply_dal_minimum_voltage_request(
3601                 struct pp_hwmgr *hwmgr)
3602 {
3603         return;
3604 }
3605
3606 static int vega10_get_soc_index_for_max_uclk(struct pp_hwmgr *hwmgr)
3607 {
3608         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table_on_mclk;
3609         struct phm_ppt_v2_information *table_info =
3610                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
3611
3612         vdd_dep_table_on_mclk  = table_info->vdd_dep_on_mclk;
3613
3614         return vdd_dep_table_on_mclk->entries[NUM_UCLK_DPM_LEVELS - 1].vddInd + 1;
3615 }
3616
3617 static int vega10_upload_dpm_bootup_level(struct pp_hwmgr *hwmgr)
3618 {
3619         struct vega10_hwmgr *data = hwmgr->backend;
3620         uint32_t socclk_idx;
3621
3622         vega10_apply_dal_minimum_voltage_request(hwmgr);
3623
3624         if (!data->registry_data.sclk_dpm_key_disabled) {
3625                 if (data->smc_state_table.gfx_boot_level !=
3626                                 data->dpm_table.gfx_table.dpm_state.soft_min_level) {
3627                         smum_send_msg_to_smc_with_parameter(hwmgr,
3628                                 PPSMC_MSG_SetSoftMinGfxclkByIndex,
3629                                 data->smc_state_table.gfx_boot_level,
3630                                 NULL);
3631
3632                         data->dpm_table.gfx_table.dpm_state.soft_min_level =
3633                                         data->smc_state_table.gfx_boot_level;
3634                 }
3635         }
3636
3637         if (!data->registry_data.mclk_dpm_key_disabled) {
3638                 if (data->smc_state_table.mem_boot_level !=
3639                                 data->dpm_table.mem_table.dpm_state.soft_min_level) {
3640                         if ((data->smc_state_table.mem_boot_level == NUM_UCLK_DPM_LEVELS - 1)
3641                             && hwmgr->not_vf) {
3642                                 socclk_idx = vega10_get_soc_index_for_max_uclk(hwmgr);
3643                                 smum_send_msg_to_smc_with_parameter(hwmgr,
3644                                                 PPSMC_MSG_SetSoftMinSocclkByIndex,
3645                                                 socclk_idx,
3646                                                 NULL);
3647                         } else {
3648                                 smum_send_msg_to_smc_with_parameter(hwmgr,
3649                                                 PPSMC_MSG_SetSoftMinUclkByIndex,
3650                                                 data->smc_state_table.mem_boot_level,
3651                                                 NULL);
3652                         }
3653                         data->dpm_table.mem_table.dpm_state.soft_min_level =
3654                                         data->smc_state_table.mem_boot_level;
3655                 }
3656         }
3657
3658         if (!hwmgr->not_vf)
3659                 return 0;
3660
3661         if (!data->registry_data.socclk_dpm_key_disabled) {
3662                 if (data->smc_state_table.soc_boot_level !=
3663                                 data->dpm_table.soc_table.dpm_state.soft_min_level) {
3664                         smum_send_msg_to_smc_with_parameter(hwmgr,
3665                                 PPSMC_MSG_SetSoftMinSocclkByIndex,
3666                                 data->smc_state_table.soc_boot_level,
3667                                 NULL);
3668                         data->dpm_table.soc_table.dpm_state.soft_min_level =
3669                                         data->smc_state_table.soc_boot_level;
3670                 }
3671         }
3672
3673         return 0;
3674 }
3675
3676 static int vega10_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
3677 {
3678         struct vega10_hwmgr *data = hwmgr->backend;
3679
3680         vega10_apply_dal_minimum_voltage_request(hwmgr);
3681
3682         if (!data->registry_data.sclk_dpm_key_disabled) {
3683                 if (data->smc_state_table.gfx_max_level !=
3684                         data->dpm_table.gfx_table.dpm_state.soft_max_level) {
3685                         smum_send_msg_to_smc_with_parameter(hwmgr,
3686                                 PPSMC_MSG_SetSoftMaxGfxclkByIndex,
3687                                 data->smc_state_table.gfx_max_level,
3688                                 NULL);
3689                         data->dpm_table.gfx_table.dpm_state.soft_max_level =
3690                                         data->smc_state_table.gfx_max_level;
3691                 }
3692         }
3693
3694         if (!data->registry_data.mclk_dpm_key_disabled) {
3695                 if (data->smc_state_table.mem_max_level !=
3696                         data->dpm_table.mem_table.dpm_state.soft_max_level) {
3697                         smum_send_msg_to_smc_with_parameter(hwmgr,
3698                                         PPSMC_MSG_SetSoftMaxUclkByIndex,
3699                                         data->smc_state_table.mem_max_level,
3700                                         NULL);
3701                         data->dpm_table.mem_table.dpm_state.soft_max_level =
3702                                         data->smc_state_table.mem_max_level;
3703                 }
3704         }
3705
3706         if (!hwmgr->not_vf)
3707                 return 0;
3708
3709         if (!data->registry_data.socclk_dpm_key_disabled) {
3710                 if (data->smc_state_table.soc_max_level !=
3711                         data->dpm_table.soc_table.dpm_state.soft_max_level) {
3712                         smum_send_msg_to_smc_with_parameter(hwmgr,
3713                                 PPSMC_MSG_SetSoftMaxSocclkByIndex,
3714                                 data->smc_state_table.soc_max_level,
3715                                 NULL);
3716                         data->dpm_table.soc_table.dpm_state.soft_max_level =
3717                                         data->smc_state_table.soc_max_level;
3718                 }
3719         }
3720
3721         return 0;
3722 }
3723
3724 static int vega10_generate_dpm_level_enable_mask(
3725                 struct pp_hwmgr *hwmgr, const void *input)
3726 {
3727         struct vega10_hwmgr *data = hwmgr->backend;
3728         const struct phm_set_power_state_input *states =
3729                         (const struct phm_set_power_state_input *)input;
3730         const struct vega10_power_state *vega10_ps =
3731                         cast_const_phw_vega10_power_state(states->pnew_state);
3732         int i;
3733
3734         PP_ASSERT_WITH_CODE(!vega10_trim_dpm_states(hwmgr, vega10_ps),
3735                         "Attempt to Trim DPM States Failed!",
3736                         return -1);
3737
3738         data->smc_state_table.gfx_boot_level =
3739                         vega10_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
3740         data->smc_state_table.gfx_max_level =
3741                         vega10_find_highest_dpm_level(&(data->dpm_table.gfx_table));
3742         data->smc_state_table.mem_boot_level =
3743                         vega10_find_lowest_dpm_level(&(data->dpm_table.mem_table));
3744         data->smc_state_table.mem_max_level =
3745                         vega10_find_highest_dpm_level(&(data->dpm_table.mem_table));
3746         data->smc_state_table.soc_boot_level =
3747                         vega10_find_lowest_dpm_level(&(data->dpm_table.soc_table));
3748         data->smc_state_table.soc_max_level =
3749                         vega10_find_highest_dpm_level(&(data->dpm_table.soc_table));
3750
3751         PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
3752                         "Attempt to upload DPM Bootup Levels Failed!",
3753                         return -1);
3754         PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
3755                         "Attempt to upload DPM Max Levels Failed!",
3756                         return -1);
3757         for(i = data->smc_state_table.gfx_boot_level; i < data->smc_state_table.gfx_max_level; i++)
3758                 data->dpm_table.gfx_table.dpm_levels[i].enabled = true;
3759
3760
3761         for(i = data->smc_state_table.mem_boot_level; i < data->smc_state_table.mem_max_level; i++)
3762                 data->dpm_table.mem_table.dpm_levels[i].enabled = true;
3763
3764         for (i = data->smc_state_table.soc_boot_level; i < data->smc_state_table.soc_max_level; i++)
3765                 data->dpm_table.soc_table.dpm_levels[i].enabled = true;
3766
3767         return 0;
3768 }
3769
3770 int vega10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
3771 {
3772         struct vega10_hwmgr *data = hwmgr->backend;
3773
3774         if (data->smu_features[GNLD_DPM_VCE].supported) {
3775                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
3776                                 enable,
3777                                 data->smu_features[GNLD_DPM_VCE].smu_feature_bitmap),
3778                                 "Attempt to Enable/Disable DPM VCE Failed!",
3779                                 return -1);
3780                 data->smu_features[GNLD_DPM_VCE].enabled = enable;
3781         }
3782
3783         return 0;
3784 }
3785
3786 static int vega10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
3787 {
3788         struct vega10_hwmgr *data = hwmgr->backend;
3789         uint32_t low_sclk_interrupt_threshold = 0;
3790
3791         if (PP_CAP(PHM_PlatformCaps_SclkThrottleLowNotification) &&
3792                 (data->low_sclk_interrupt_threshold != 0)) {
3793                 low_sclk_interrupt_threshold =
3794                                 data->low_sclk_interrupt_threshold;
3795
3796                 data->smc_state_table.pp_table.LowGfxclkInterruptThreshold =
3797                                 cpu_to_le32(low_sclk_interrupt_threshold);
3798
3799                 /* This message will also enable SmcToHost Interrupt */
3800                 smum_send_msg_to_smc_with_parameter(hwmgr,
3801                                 PPSMC_MSG_SetLowGfxclkInterruptThreshold,
3802                                 (uint32_t)low_sclk_interrupt_threshold,
3803                                 NULL);
3804         }
3805
3806         return 0;
3807 }
3808
3809 static int vega10_set_power_state_tasks(struct pp_hwmgr *hwmgr,
3810                 const void *input)
3811 {
3812         int tmp_result, result = 0;
3813         struct vega10_hwmgr *data = hwmgr->backend;
3814         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
3815
3816         tmp_result = vega10_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
3817         PP_ASSERT_WITH_CODE(!tmp_result,
3818                         "Failed to find DPM states clocks in DPM table!",
3819                         result = tmp_result);
3820
3821         tmp_result = vega10_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
3822         PP_ASSERT_WITH_CODE(!tmp_result,
3823                         "Failed to populate and upload SCLK MCLK DPM levels!",
3824                         result = tmp_result);
3825
3826         tmp_result = vega10_generate_dpm_level_enable_mask(hwmgr, input);
3827         PP_ASSERT_WITH_CODE(!tmp_result,
3828                         "Failed to generate DPM level enabled mask!",
3829                         result = tmp_result);
3830
3831         tmp_result = vega10_update_sclk_threshold(hwmgr);
3832         PP_ASSERT_WITH_CODE(!tmp_result,
3833                         "Failed to update SCLK threshold!",
3834                         result = tmp_result);
3835
3836         result = smum_smc_table_manager(hwmgr, (uint8_t *)pp_table, PPTABLE, false);
3837         PP_ASSERT_WITH_CODE(!result,
3838                         "Failed to upload PPtable!", return result);
3839
3840         /*
3841          * If a custom pp table is loaded, set DPMTABLE_OD_UPDATE_VDDC flag.
3842          * That effectively disables AVFS feature.
3843          */
3844         if(hwmgr->hardcode_pp_table != NULL)
3845                 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC;
3846
3847         vega10_update_avfs(hwmgr);
3848
3849         /*
3850          * Clear all OD flags except DPMTABLE_OD_UPDATE_VDDC.
3851          * That will help to keep AVFS disabled.
3852          */
3853         data->need_update_dpm_table &= DPMTABLE_OD_UPDATE_VDDC;
3854
3855         return 0;
3856 }
3857
3858 static uint32_t vega10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
3859 {
3860         struct pp_power_state *ps;
3861         struct vega10_power_state *vega10_ps;
3862
3863         if (hwmgr == NULL)
3864                 return -EINVAL;
3865
3866         ps = hwmgr->request_ps;
3867
3868         if (ps == NULL)
3869                 return -EINVAL;
3870
3871         vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
3872
3873         if (low)
3874                 return vega10_ps->performance_levels[0].gfx_clock;
3875         else
3876                 return vega10_ps->performance_levels
3877                                 [vega10_ps->performance_level_count - 1].gfx_clock;
3878 }
3879
3880 static uint32_t vega10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
3881 {
3882         struct pp_power_state *ps;
3883         struct vega10_power_state *vega10_ps;
3884
3885         if (hwmgr == NULL)
3886                 return -EINVAL;
3887
3888         ps = hwmgr->request_ps;
3889
3890         if (ps == NULL)
3891                 return -EINVAL;
3892
3893         vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
3894
3895         if (low)
3896                 return vega10_ps->performance_levels[0].mem_clock;
3897         else
3898                 return vega10_ps->performance_levels
3899                                 [vega10_ps->performance_level_count-1].mem_clock;
3900 }
3901
3902 static int vega10_get_gpu_power(struct pp_hwmgr *hwmgr,
3903                 uint32_t *query)
3904 {
3905         uint32_t value;
3906
3907         if (!query)
3908                 return -EINVAL;
3909
3910         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrPkgPwr, &value);
3911
3912         /* SMC returning actual watts, keep consistent with legacy asics, low 8 bit as 8 fractional bits */
3913         *query = value << 8;
3914
3915         return 0;
3916 }
3917
3918 static int vega10_read_sensor(struct pp_hwmgr *hwmgr, int idx,
3919                               void *value, int *size)
3920 {
3921         struct amdgpu_device *adev = hwmgr->adev;
3922         uint32_t sclk_mhz, mclk_idx, activity_percent = 0;
3923         struct vega10_hwmgr *data = hwmgr->backend;
3924         struct vega10_dpm_table *dpm_table = &data->dpm_table;
3925         int ret = 0;
3926         uint32_t val_vid;
3927
3928         switch (idx) {
3929         case AMDGPU_PP_SENSOR_GFX_SCLK:
3930                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetAverageGfxclkActualFrequency, &sclk_mhz);
3931                 *((uint32_t *)value) = sclk_mhz * 100;
3932                 break;
3933         case AMDGPU_PP_SENSOR_GFX_MCLK:
3934                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex, &mclk_idx);
3935                 if (mclk_idx < dpm_table->mem_table.count) {
3936                         *((uint32_t *)value) = dpm_table->mem_table.dpm_levels[mclk_idx].value;
3937                         *size = 4;
3938                 } else {
3939                         ret = -EINVAL;
3940                 }
3941                 break;
3942         case AMDGPU_PP_SENSOR_GPU_LOAD:
3943                 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetAverageGfxActivity, 0,
3944                                                 &activity_percent);
3945                 *((uint32_t *)value) = activity_percent > 100 ? 100 : activity_percent;
3946                 *size = 4;
3947                 break;
3948         case AMDGPU_PP_SENSOR_GPU_TEMP:
3949                 *((uint32_t *)value) = vega10_thermal_get_temperature(hwmgr);
3950                 *size = 4;
3951                 break;
3952         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
3953                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetTemperatureHotspot, (uint32_t *)value);
3954                 *((uint32_t *)value) = *((uint32_t *)value) *
3955                         PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
3956                 *size = 4;
3957                 break;
3958         case AMDGPU_PP_SENSOR_MEM_TEMP:
3959                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetTemperatureHBM, (uint32_t *)value);
3960                 *((uint32_t *)value) = *((uint32_t *)value) *
3961                         PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
3962                 *size = 4;
3963                 break;
3964         case AMDGPU_PP_SENSOR_UVD_POWER:
3965                 *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1;
3966                 *size = 4;
3967                 break;
3968         case AMDGPU_PP_SENSOR_VCE_POWER:
3969                 *((uint32_t *)value) = data->vce_power_gated ? 0 : 1;
3970                 *size = 4;
3971                 break;
3972         case AMDGPU_PP_SENSOR_GPU_POWER:
3973                 ret = vega10_get_gpu_power(hwmgr, (uint32_t *)value);
3974                 break;
3975         case AMDGPU_PP_SENSOR_VDDGFX:
3976                 val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_PLANE0_CURRENTVID) &
3977                         SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID_MASK) >>
3978                         SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID__SHIFT;
3979                 *((uint32_t *)value) = (uint32_t)convert_to_vddc((uint8_t)val_vid);
3980                 return 0;
3981         case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
3982                 ret = vega10_get_enabled_smc_features(hwmgr, (uint64_t *)value);
3983                 if (!ret)
3984                         *size = 8;
3985                 break;
3986         default:
3987                 ret = -EOPNOTSUPP;
3988                 break;
3989         }
3990
3991         return ret;
3992 }
3993
3994 static void vega10_notify_smc_display_change(struct pp_hwmgr *hwmgr,
3995                 bool has_disp)
3996 {
3997         smum_send_msg_to_smc_with_parameter(hwmgr,
3998                         PPSMC_MSG_SetUclkFastSwitch,
3999                         has_disp ? 1 : 0,
4000                         NULL);
4001 }
4002
4003 static int vega10_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
4004                 struct pp_display_clock_request *clock_req)
4005 {
4006         int result = 0;
4007         enum amd_pp_clock_type clk_type = clock_req->clock_type;
4008         uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
4009         DSPCLK_e clk_select = 0;
4010         uint32_t clk_request = 0;
4011
4012         switch (clk_type) {
4013         case amd_pp_dcef_clock:
4014                 clk_select = DSPCLK_DCEFCLK;
4015                 break;
4016         case amd_pp_disp_clock:
4017                 clk_select = DSPCLK_DISPCLK;
4018                 break;
4019         case amd_pp_pixel_clock:
4020                 clk_select = DSPCLK_PIXCLK;
4021                 break;
4022         case amd_pp_phy_clock:
4023                 clk_select = DSPCLK_PHYCLK;
4024                 break;
4025         default:
4026                 pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!");
4027                 result = -1;
4028                 break;
4029         }
4030
4031         if (!result) {
4032                 clk_request = (clk_freq << 16) | clk_select;
4033                 smum_send_msg_to_smc_with_parameter(hwmgr,
4034                                 PPSMC_MSG_RequestDisplayClockByFreq,
4035                                 clk_request,
4036                                 NULL);
4037         }
4038
4039         return result;
4040 }
4041
4042 static uint8_t vega10_get_uclk_index(struct pp_hwmgr *hwmgr,
4043                         struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table,
4044                                                 uint32_t frequency)
4045 {
4046         uint8_t count;
4047         uint8_t i;
4048
4049         if (mclk_table == NULL || mclk_table->count == 0)
4050                 return 0;
4051
4052         count = (uint8_t)(mclk_table->count);
4053
4054         for(i = 0; i < count; i++) {
4055                 if(mclk_table->entries[i].clk >= frequency)
4056                         return i;
4057         }
4058
4059         return i-1;
4060 }
4061
4062 static int vega10_notify_smc_display_config_after_ps_adjustment(
4063                 struct pp_hwmgr *hwmgr)
4064 {
4065         struct vega10_hwmgr *data = hwmgr->backend;
4066         struct vega10_single_dpm_table *dpm_table =
4067                         &data->dpm_table.dcef_table;
4068         struct phm_ppt_v2_information *table_info =
4069                         (struct phm_ppt_v2_information *)hwmgr->pptable;
4070         struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table = table_info->vdd_dep_on_mclk;
4071         uint32_t idx;
4072         struct PP_Clocks min_clocks = {0};
4073         uint32_t i;
4074         struct pp_display_clock_request clock_req;
4075
4076         if ((hwmgr->display_config->num_display > 1) &&
4077              !hwmgr->display_config->multi_monitor_in_sync &&
4078              !hwmgr->display_config->nb_pstate_switch_disable)
4079                 vega10_notify_smc_display_change(hwmgr, false);
4080         else
4081                 vega10_notify_smc_display_change(hwmgr, true);
4082
4083         min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
4084         min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;
4085         min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
4086
4087         for (i = 0; i < dpm_table->count; i++) {
4088                 if (dpm_table->dpm_levels[i].value == min_clocks.dcefClock)
4089                         break;
4090         }
4091
4092         if (i < dpm_table->count) {
4093                 clock_req.clock_type = amd_pp_dcef_clock;
4094                 clock_req.clock_freq_in_khz = dpm_table->dpm_levels[i].value * 10;
4095                 if (!vega10_display_clock_voltage_request(hwmgr, &clock_req)) {
4096                         smum_send_msg_to_smc_with_parameter(
4097                                         hwmgr, PPSMC_MSG_SetMinDeepSleepDcefclk,
4098                                         min_clocks.dcefClockInSR / 100,
4099                                         NULL);
4100                 } else {
4101                         pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
4102                 }
4103         } else {
4104                 pr_debug("Cannot find requested DCEFCLK!");
4105         }
4106
4107         if (min_clocks.memoryClock != 0) {
4108                 idx = vega10_get_uclk_index(hwmgr, mclk_table, min_clocks.memoryClock);
4109                 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetSoftMinUclkByIndex, idx,
4110                                                 NULL);
4111                 data->dpm_table.mem_table.dpm_state.soft_min_level= idx;
4112         }
4113
4114         return 0;
4115 }
4116
4117 static int vega10_force_dpm_highest(struct pp_hwmgr *hwmgr)
4118 {
4119         struct vega10_hwmgr *data = hwmgr->backend;
4120
4121         data->smc_state_table.gfx_boot_level =
4122         data->smc_state_table.gfx_max_level =
4123                         vega10_find_highest_dpm_level(&(data->dpm_table.gfx_table));
4124         data->smc_state_table.mem_boot_level =
4125         data->smc_state_table.mem_max_level =
4126                         vega10_find_highest_dpm_level(&(data->dpm_table.mem_table));
4127
4128         PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
4129                         "Failed to upload boot level to highest!",
4130                         return -1);
4131
4132         PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
4133                         "Failed to upload dpm max level to highest!",
4134                         return -1);
4135
4136         return 0;
4137 }
4138
4139 static int vega10_force_dpm_lowest(struct pp_hwmgr *hwmgr)
4140 {
4141         struct vega10_hwmgr *data = hwmgr->backend;
4142
4143         data->smc_state_table.gfx_boot_level =
4144         data->smc_state_table.gfx_max_level =
4145                         vega10_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
4146         data->smc_state_table.mem_boot_level =
4147         data->smc_state_table.mem_max_level =
4148                         vega10_find_lowest_dpm_level(&(data->dpm_table.mem_table));
4149
4150         PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
4151                         "Failed to upload boot level to highest!",
4152                         return -1);
4153
4154         PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
4155                         "Failed to upload dpm max level to highest!",
4156                         return -1);
4157
4158         return 0;
4159
4160 }
4161
4162 static int vega10_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
4163 {
4164         struct vega10_hwmgr *data = hwmgr->backend;
4165
4166         data->smc_state_table.gfx_boot_level =
4167                         vega10_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
4168         data->smc_state_table.gfx_max_level =
4169                         vega10_find_highest_dpm_level(&(data->dpm_table.gfx_table));
4170         data->smc_state_table.mem_boot_level =
4171                         vega10_find_lowest_dpm_level(&(data->dpm_table.mem_table));
4172         data->smc_state_table.mem_max_level =
4173                         vega10_find_highest_dpm_level(&(data->dpm_table.mem_table));
4174
4175         PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
4176                         "Failed to upload DPM Bootup Levels!",
4177                         return -1);
4178
4179         PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
4180                         "Failed to upload DPM Max Levels!",
4181                         return -1);
4182         return 0;
4183 }
4184
4185 static int vega10_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level,
4186                                 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask)
4187 {
4188         struct phm_ppt_v2_information *table_info =
4189                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
4190
4191         if (table_info->vdd_dep_on_sclk->count > VEGA10_UMD_PSTATE_GFXCLK_LEVEL &&
4192                 table_info->vdd_dep_on_socclk->count > VEGA10_UMD_PSTATE_SOCCLK_LEVEL &&
4193                 table_info->vdd_dep_on_mclk->count > VEGA10_UMD_PSTATE_MCLK_LEVEL) {
4194                 *sclk_mask = VEGA10_UMD_PSTATE_GFXCLK_LEVEL;
4195                 *soc_mask = VEGA10_UMD_PSTATE_SOCCLK_LEVEL;
4196                 *mclk_mask = VEGA10_UMD_PSTATE_MCLK_LEVEL;
4197         }
4198
4199         if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
4200                 *sclk_mask = 0;
4201         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
4202                 *mclk_mask = 0;
4203         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
4204                 /* under vega10  pp one vf mode, the gfx clk dpm need be lower
4205                  * to level-4 due to the limited power
4206                  */
4207                 if (hwmgr->pp_one_vf)
4208                         *sclk_mask = 4;
4209                 else
4210                         *sclk_mask = table_info->vdd_dep_on_sclk->count - 1;
4211                 *soc_mask = table_info->vdd_dep_on_socclk->count - 1;
4212                 *mclk_mask = table_info->vdd_dep_on_mclk->count - 1;
4213         }
4214
4215         return 0;
4216 }
4217
4218 static void vega10_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
4219 {
4220         if (!hwmgr->not_vf)
4221                 return;
4222
4223         switch (mode) {
4224         case AMD_FAN_CTRL_NONE:
4225                 vega10_fan_ctrl_set_fan_speed_pwm(hwmgr, 255);
4226                 break;
4227         case AMD_FAN_CTRL_MANUAL:
4228                 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
4229                         vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
4230                 break;
4231         case AMD_FAN_CTRL_AUTO:
4232                 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
4233                         vega10_fan_ctrl_start_smc_fan_control(hwmgr);
4234                 break;
4235         default:
4236                 break;
4237         }
4238 }
4239
4240 static int vega10_force_clock_level(struct pp_hwmgr *hwmgr,
4241                 enum pp_clock_type type, uint32_t mask)
4242 {
4243         struct vega10_hwmgr *data = hwmgr->backend;
4244
4245         switch (type) {
4246         case PP_SCLK:
4247                 data->smc_state_table.gfx_boot_level = mask ? (ffs(mask) - 1) : 0;
4248                 data->smc_state_table.gfx_max_level = mask ? (fls(mask) - 1) : 0;
4249
4250                 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
4251                         "Failed to upload boot level to lowest!",
4252                         return -EINVAL);
4253
4254                 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
4255                         "Failed to upload dpm max level to highest!",
4256                         return -EINVAL);
4257                 break;
4258
4259         case PP_MCLK:
4260                 data->smc_state_table.mem_boot_level = mask ? (ffs(mask) - 1) : 0;
4261                 data->smc_state_table.mem_max_level = mask ? (fls(mask) - 1) : 0;
4262
4263                 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
4264                         "Failed to upload boot level to lowest!",
4265                         return -EINVAL);
4266
4267                 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
4268                         "Failed to upload dpm max level to highest!",
4269                         return -EINVAL);
4270
4271                 break;
4272
4273         case PP_SOCCLK:
4274                 data->smc_state_table.soc_boot_level = mask ? (ffs(mask) - 1) : 0;
4275                 data->smc_state_table.soc_max_level = mask ? (fls(mask) - 1) : 0;
4276
4277                 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
4278                         "Failed to upload boot level to lowest!",
4279                         return -EINVAL);
4280
4281                 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
4282                         "Failed to upload dpm max level to highest!",
4283                         return -EINVAL);
4284
4285                 break;
4286
4287         case PP_DCEFCLK:
4288                 pr_info("Setting DCEFCLK min/max dpm level is not supported!\n");
4289                 break;
4290
4291         case PP_PCIE:
4292         default:
4293                 break;
4294         }
4295
4296         return 0;
4297 }
4298
4299 static int vega10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
4300                                 enum amd_dpm_forced_level level)
4301 {
4302         int ret = 0;
4303         uint32_t sclk_mask = 0;
4304         uint32_t mclk_mask = 0;
4305         uint32_t soc_mask = 0;
4306
4307         switch (level) {
4308         case AMD_DPM_FORCED_LEVEL_HIGH:
4309                 ret = vega10_force_dpm_highest(hwmgr);
4310                 break;
4311         case AMD_DPM_FORCED_LEVEL_LOW:
4312                 ret = vega10_force_dpm_lowest(hwmgr);
4313                 break;
4314         case AMD_DPM_FORCED_LEVEL_AUTO:
4315                 ret = vega10_unforce_dpm_levels(hwmgr);
4316                 break;
4317         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
4318         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
4319         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
4320         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
4321                 ret = vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
4322                 if (ret)
4323                         return ret;
4324                 vega10_force_clock_level(hwmgr, PP_SCLK, 1<<sclk_mask);
4325                 vega10_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask);
4326                 break;
4327         case AMD_DPM_FORCED_LEVEL_MANUAL:
4328         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
4329         default:
4330                 break;
4331         }
4332
4333         if (!hwmgr->not_vf)
4334                 return ret;
4335
4336         if (!ret) {
4337                 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
4338                         vega10_set_fan_control_mode(hwmgr, AMD_FAN_CTRL_NONE);
4339                 else if (level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
4340                         vega10_set_fan_control_mode(hwmgr, AMD_FAN_CTRL_AUTO);
4341         }
4342
4343         return ret;
4344 }
4345
4346 static uint32_t vega10_get_fan_control_mode(struct pp_hwmgr *hwmgr)
4347 {
4348         struct vega10_hwmgr *data = hwmgr->backend;
4349
4350         if (data->smu_features[GNLD_FAN_CONTROL].enabled == false)
4351                 return AMD_FAN_CTRL_MANUAL;
4352         else
4353                 return AMD_FAN_CTRL_AUTO;
4354 }
4355
4356 static int vega10_get_dal_power_level(struct pp_hwmgr *hwmgr,
4357                 struct amd_pp_simple_clock_info *info)
4358 {
4359         struct phm_ppt_v2_information *table_info =
4360                         (struct phm_ppt_v2_information *)hwmgr->pptable;
4361         struct phm_clock_and_voltage_limits *max_limits =
4362                         &table_info->max_clock_voltage_on_ac;
4363
4364         info->engine_max_clock = max_limits->sclk;
4365         info->memory_max_clock = max_limits->mclk;
4366
4367         return 0;
4368 }
4369
4370 static void vega10_get_sclks(struct pp_hwmgr *hwmgr,
4371                 struct pp_clock_levels_with_latency *clocks)
4372 {
4373         struct phm_ppt_v2_information *table_info =
4374                         (struct phm_ppt_v2_information *)hwmgr->pptable;
4375         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
4376                         table_info->vdd_dep_on_sclk;
4377         uint32_t i;
4378
4379         clocks->num_levels = 0;
4380         for (i = 0; i < dep_table->count; i++) {
4381                 if (dep_table->entries[i].clk) {
4382                         clocks->data[clocks->num_levels].clocks_in_khz =
4383                                         dep_table->entries[i].clk * 10;
4384                         clocks->num_levels++;
4385                 }
4386         }
4387
4388 }
4389
4390 static void vega10_get_memclocks(struct pp_hwmgr *hwmgr,
4391                 struct pp_clock_levels_with_latency *clocks)
4392 {
4393         struct phm_ppt_v2_information *table_info =
4394                         (struct phm_ppt_v2_information *)hwmgr->pptable;
4395         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
4396                         table_info->vdd_dep_on_mclk;
4397         struct vega10_hwmgr *data = hwmgr->backend;
4398         uint32_t j = 0;
4399         uint32_t i;
4400
4401         for (i = 0; i < dep_table->count; i++) {
4402                 if (dep_table->entries[i].clk) {
4403
4404                         clocks->data[j].clocks_in_khz =
4405                                                 dep_table->entries[i].clk * 10;
4406                         data->mclk_latency_table.entries[j].frequency =
4407                                                         dep_table->entries[i].clk;
4408                         clocks->data[j].latency_in_us =
4409                                 data->mclk_latency_table.entries[j].latency = 25;
4410                         j++;
4411                 }
4412         }
4413         clocks->num_levels = data->mclk_latency_table.count = j;
4414 }
4415
4416 static void vega10_get_dcefclocks(struct pp_hwmgr *hwmgr,
4417                 struct pp_clock_levels_with_latency *clocks)
4418 {
4419         struct phm_ppt_v2_information *table_info =
4420                         (struct phm_ppt_v2_information *)hwmgr->pptable;
4421         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
4422                         table_info->vdd_dep_on_dcefclk;
4423         uint32_t i;
4424
4425         for (i = 0; i < dep_table->count; i++) {
4426                 clocks->data[i].clocks_in_khz = dep_table->entries[i].clk * 10;
4427                 clocks->data[i].latency_in_us = 0;
4428                 clocks->num_levels++;
4429         }
4430 }
4431
4432 static void vega10_get_socclocks(struct pp_hwmgr *hwmgr,
4433                 struct pp_clock_levels_with_latency *clocks)
4434 {
4435         struct phm_ppt_v2_information *table_info =
4436                         (struct phm_ppt_v2_information *)hwmgr->pptable;
4437         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
4438                         table_info->vdd_dep_on_socclk;
4439         uint32_t i;
4440
4441         for (i = 0; i < dep_table->count; i++) {
4442                 clocks->data[i].clocks_in_khz = dep_table->entries[i].clk * 10;
4443                 clocks->data[i].latency_in_us = 0;
4444                 clocks->num_levels++;
4445         }
4446 }
4447
4448 static int vega10_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
4449                 enum amd_pp_clock_type type,
4450                 struct pp_clock_levels_with_latency *clocks)
4451 {
4452         switch (type) {
4453         case amd_pp_sys_clock:
4454                 vega10_get_sclks(hwmgr, clocks);
4455                 break;
4456         case amd_pp_mem_clock:
4457                 vega10_get_memclocks(hwmgr, clocks);
4458                 break;
4459         case amd_pp_dcef_clock:
4460                 vega10_get_dcefclocks(hwmgr, clocks);
4461                 break;
4462         case amd_pp_soc_clock:
4463                 vega10_get_socclocks(hwmgr, clocks);
4464                 break;
4465         default:
4466                 return -1;
4467         }
4468
4469         return 0;
4470 }
4471
4472 static int vega10_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
4473                 enum amd_pp_clock_type type,
4474                 struct pp_clock_levels_with_voltage *clocks)
4475 {
4476         struct phm_ppt_v2_information *table_info =
4477                         (struct phm_ppt_v2_information *)hwmgr->pptable;
4478         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table;
4479         uint32_t i;
4480
4481         switch (type) {
4482         case amd_pp_mem_clock:
4483                 dep_table = table_info->vdd_dep_on_mclk;
4484                 break;
4485         case amd_pp_dcef_clock:
4486                 dep_table = table_info->vdd_dep_on_dcefclk;
4487                 break;
4488         case amd_pp_disp_clock:
4489                 dep_table = table_info->vdd_dep_on_dispclk;
4490                 break;
4491         case amd_pp_pixel_clock:
4492                 dep_table = table_info->vdd_dep_on_pixclk;
4493                 break;
4494         case amd_pp_phy_clock:
4495                 dep_table = table_info->vdd_dep_on_phyclk;
4496                 break;
4497         default:
4498                 return -1;
4499         }
4500
4501         for (i = 0; i < dep_table->count; i++) {
4502                 clocks->data[i].clocks_in_khz = dep_table->entries[i].clk  * 10;
4503                 clocks->data[i].voltage_in_mv = (uint32_t)(table_info->vddc_lookup_table->
4504                                 entries[dep_table->entries[i].vddInd].us_vdd);
4505                 clocks->num_levels++;
4506         }
4507
4508         if (i < dep_table->count)
4509                 return -1;
4510
4511         return 0;
4512 }
4513
4514 static int vega10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
4515                                                         void *clock_range)
4516 {
4517         struct vega10_hwmgr *data = hwmgr->backend;
4518         struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_range;
4519         Watermarks_t *table = &(data->smc_state_table.water_marks_table);
4520
4521         if (!data->registry_data.disable_water_mark) {
4522                 smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges);
4523                 data->water_marks_bitmap = WaterMarksExist;
4524         }
4525
4526         return 0;
4527 }
4528
4529 static int vega10_get_ppfeature_status(struct pp_hwmgr *hwmgr, char *buf)
4530 {
4531         static const char *ppfeature_name[] = {
4532                                 "DPM_PREFETCHER",
4533                                 "GFXCLK_DPM",
4534                                 "UCLK_DPM",
4535                                 "SOCCLK_DPM",
4536                                 "UVD_DPM",
4537                                 "VCE_DPM",
4538                                 "ULV",
4539                                 "MP0CLK_DPM",
4540                                 "LINK_DPM",
4541                                 "DCEFCLK_DPM",
4542                                 "AVFS",
4543                                 "GFXCLK_DS",
4544                                 "SOCCLK_DS",
4545                                 "LCLK_DS",
4546                                 "PPT",
4547                                 "TDC",
4548                                 "THERMAL",
4549                                 "GFX_PER_CU_CG",
4550                                 "RM",
4551                                 "DCEFCLK_DS",
4552                                 "ACDC",
4553                                 "VR0HOT",
4554                                 "VR1HOT",
4555                                 "FW_CTF",
4556                                 "LED_DISPLAY",
4557                                 "FAN_CONTROL",
4558                                 "FAST_PPT",
4559                                 "DIDT",
4560                                 "ACG",
4561                                 "PCC_LIMIT"};
4562         static const char *output_title[] = {
4563                                 "FEATURES",
4564                                 "BITMASK",
4565                                 "ENABLEMENT"};
4566         uint64_t features_enabled;
4567         int i;
4568         int ret = 0;
4569         int size = 0;
4570
4571         phm_get_sysfs_buf(&buf, &size);
4572
4573         ret = vega10_get_enabled_smc_features(hwmgr, &features_enabled);
4574         PP_ASSERT_WITH_CODE(!ret,
4575                         "[EnableAllSmuFeatures] Failed to get enabled smc features!",
4576                         return ret);
4577
4578         size += sysfs_emit_at(buf, size, "Current ppfeatures: 0x%016llx\n", features_enabled);
4579         size += sysfs_emit_at(buf, size, "%-19s %-22s %s\n",
4580                                 output_title[0],
4581                                 output_title[1],
4582                                 output_title[2]);
4583         for (i = 0; i < GNLD_FEATURES_MAX; i++) {
4584                 size += sysfs_emit_at(buf, size, "%-19s 0x%016llx %6s\n",
4585                                         ppfeature_name[i],
4586                                         1ULL << i,
4587                                         (features_enabled & (1ULL << i)) ? "Y" : "N");
4588         }
4589
4590         return size;
4591 }
4592
4593 static int vega10_set_ppfeature_status(struct pp_hwmgr *hwmgr, uint64_t new_ppfeature_masks)
4594 {
4595         uint64_t features_enabled;
4596         uint64_t features_to_enable;
4597         uint64_t features_to_disable;
4598         int ret = 0;
4599
4600         if (new_ppfeature_masks >= (1ULL << GNLD_FEATURES_MAX))
4601                 return -EINVAL;
4602
4603         ret = vega10_get_enabled_smc_features(hwmgr, &features_enabled);
4604         if (ret)
4605                 return ret;
4606
4607         features_to_disable =
4608                 features_enabled & ~new_ppfeature_masks;
4609         features_to_enable =
4610                 ~features_enabled & new_ppfeature_masks;
4611
4612         pr_debug("features_to_disable 0x%llx\n", features_to_disable);
4613         pr_debug("features_to_enable 0x%llx\n", features_to_enable);
4614
4615         if (features_to_disable) {
4616                 ret = vega10_enable_smc_features(hwmgr, false, features_to_disable);
4617                 if (ret)
4618                         return ret;
4619         }
4620
4621         if (features_to_enable) {
4622                 ret = vega10_enable_smc_features(hwmgr, true, features_to_enable);
4623                 if (ret)
4624                         return ret;
4625         }
4626
4627         return 0;
4628 }
4629
4630 static int vega10_get_current_pcie_link_width_level(struct pp_hwmgr *hwmgr)
4631 {
4632         struct amdgpu_device *adev = hwmgr->adev;
4633
4634         return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
4635                 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
4636                 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
4637 }
4638
4639 static int vega10_get_current_pcie_link_speed_level(struct pp_hwmgr *hwmgr)
4640 {
4641         struct amdgpu_device *adev = hwmgr->adev;
4642
4643         return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
4644                 PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
4645                 >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
4646 }
4647
4648 static int vega10_emit_clock_levels(struct pp_hwmgr *hwmgr,
4649                                     enum pp_clock_type type, char *buf, int *offset)
4650 {
4651         struct vega10_hwmgr *data = hwmgr->backend;
4652         struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
4653         struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
4654         struct vega10_single_dpm_table *soc_table = &(data->dpm_table.soc_table);
4655         struct vega10_single_dpm_table *dcef_table = &(data->dpm_table.dcef_table);
4656         struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep = NULL;
4657         uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width;
4658         PPTable_t *pptable = &(data->smc_state_table.pp_table);
4659
4660         uint32_t i, now, count = 0;
4661         int ret = 0;
4662
4663         switch (type) {
4664         case PP_SCLK:
4665                 if (data->registry_data.sclk_dpm_key_disabled)
4666                         return -EOPNOTSUPP;
4667
4668                 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentGfxclkIndex, &now);
4669                 if (unlikely(ret != 0))
4670                         return ret;
4671
4672                 if (hwmgr->pp_one_vf &&
4673                     (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK))
4674                         count = 5;
4675                 else
4676                         count = sclk_table->count;
4677                 for (i = 0; i < count; i++)
4678                         *offset += sysfs_emit_at(buf, *offset, "%d: %uMhz %s\n",
4679                                         i, sclk_table->dpm_levels[i].value / 100,
4680                                         (i == now) ? "*" : "");
4681                 break;
4682         case PP_MCLK:
4683                 if (data->registry_data.mclk_dpm_key_disabled)
4684                         return -EOPNOTSUPP;
4685
4686                 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex, &now);
4687                 if (unlikely(ret != 0))
4688                         return ret;
4689
4690                 for (i = 0; i < mclk_table->count; i++)
4691                         *offset += sysfs_emit_at(buf, *offset, "%d: %uMhz %s\n",
4692                                         i, mclk_table->dpm_levels[i].value / 100,
4693                                         (i == now) ? "*" : "");
4694                 break;
4695         case PP_SOCCLK:
4696                 if (data->registry_data.socclk_dpm_key_disabled)
4697                         return -EOPNOTSUPP;
4698
4699                 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentSocclkIndex, &now);
4700                 if (unlikely(ret != 0))
4701                         return ret;
4702
4703                 for (i = 0; i < soc_table->count; i++)
4704                         *offset += sysfs_emit_at(buf, *offset, "%d: %uMhz %s\n",
4705                                         i, soc_table->dpm_levels[i].value / 100,
4706                                         (i == now) ? "*" : "");
4707                 break;
4708         case PP_DCEFCLK:
4709                 if (data->registry_data.dcefclk_dpm_key_disabled)
4710                         return -EOPNOTSUPP;
4711
4712                 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
4713                                                           PPSMC_MSG_GetClockFreqMHz,
4714                                                           CLK_DCEFCLK, &now);
4715                 if (unlikely(ret != 0))
4716                         return ret;
4717
4718                 for (i = 0; i < dcef_table->count; i++)
4719                         *offset += sysfs_emit_at(buf, *offset, "%d: %uMhz %s\n",
4720                                         i, dcef_table->dpm_levels[i].value / 100,
4721                                         (dcef_table->dpm_levels[i].value / 100 == now) ?
4722                                         "*" : "");
4723                 break;
4724         case PP_PCIE:
4725                 current_gen_speed =
4726                         vega10_get_current_pcie_link_speed_level(hwmgr);
4727                 current_lane_width =
4728                         vega10_get_current_pcie_link_width_level(hwmgr);
4729                 for (i = 0; i < NUM_LINK_LEVELS; i++) {
4730                         gen_speed = pptable->PcieGenSpeed[i];
4731                         lane_width = pptable->PcieLaneCount[i];
4732
4733                         *offset += sysfs_emit_at(buf, *offset, "%d: %s %s %s\n", i,
4734                                         (gen_speed == 0) ? "2.5GT/s," :
4735                                         (gen_speed == 1) ? "5.0GT/s," :
4736                                         (gen_speed == 2) ? "8.0GT/s," :
4737                                         (gen_speed == 3) ? "16.0GT/s," : "",
4738                                         (lane_width == 1) ? "x1" :
4739                                         (lane_width == 2) ? "x2" :
4740                                         (lane_width == 3) ? "x4" :
4741                                         (lane_width == 4) ? "x8" :
4742                                         (lane_width == 5) ? "x12" :
4743                                         (lane_width == 6) ? "x16" : "",
4744                                         (current_gen_speed == gen_speed) &&
4745                                         (current_lane_width == lane_width) ?
4746                                         "*" : "");
4747                 }
4748                 break;
4749
4750         case OD_SCLK:
4751                 if (!hwmgr->od_enabled)
4752                         return -EOPNOTSUPP;
4753
4754                 *offset += sysfs_emit_at(buf, *offset, "%s:\n", "OD_SCLK");
4755                 podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_sclk;
4756                 for (i = 0; i < podn_vdd_dep->count; i++)
4757                         *offset += sysfs_emit_at(buf, *offset, "%d: %10uMhz %10umV\n",
4758                                                  i, podn_vdd_dep->entries[i].clk / 100,
4759                                                  podn_vdd_dep->entries[i].vddc);
4760                 break;
4761         case OD_MCLK:
4762                 if (!hwmgr->od_enabled)
4763                         return -EOPNOTSUPP;
4764
4765                 *offset += sysfs_emit_at(buf, *offset, "%s:\n", "OD_MCLK");
4766                 podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_mclk;
4767                 for (i = 0; i < podn_vdd_dep->count; i++)
4768                         *offset += sysfs_emit_at(buf, *offset, "%d: %10uMhz %10umV\n",
4769                                                  i, podn_vdd_dep->entries[i].clk/100,
4770                                                  podn_vdd_dep->entries[i].vddc);
4771                 break;
4772         case OD_RANGE:
4773                 if (!hwmgr->od_enabled)
4774                         return -EOPNOTSUPP;
4775
4776                 *offset += sysfs_emit_at(buf, *offset, "%s:\n", "OD_RANGE");
4777                 *offset += sysfs_emit_at(buf, *offset, "SCLK: %7uMHz %10uMHz\n",
4778                                          data->golden_dpm_table.gfx_table.dpm_levels[0].value/100,
4779                                 hwmgr->platform_descriptor.overdriveLimit.engineClock/100);
4780                 *offset += sysfs_emit_at(buf, *offset, "MCLK: %7uMHz %10uMHz\n",
4781                                          data->golden_dpm_table.mem_table.dpm_levels[0].value/100,
4782                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock/100);
4783                 *offset += sysfs_emit_at(buf, *offset, "VDDC: %7umV %11umV\n",
4784                                          data->odn_dpm_table.min_vddc,
4785                                          data->odn_dpm_table.max_vddc);
4786                 break;
4787         default:
4788                 ret = -ENOENT;
4789                 break;
4790         }
4791         return ret;
4792 }
4793
4794 static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
4795                 enum pp_clock_type type, char *buf)
4796 {
4797         struct vega10_hwmgr *data = hwmgr->backend;
4798         struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
4799         struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
4800         struct vega10_single_dpm_table *soc_table = &(data->dpm_table.soc_table);
4801         struct vega10_single_dpm_table *dcef_table = &(data->dpm_table.dcef_table);
4802         struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep = NULL;
4803         uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width;
4804         PPTable_t *pptable = &(data->smc_state_table.pp_table);
4805
4806         int i, now, size = 0, count = 0;
4807
4808         switch (type) {
4809         case PP_SCLK:
4810                 if (data->registry_data.sclk_dpm_key_disabled)
4811                         break;
4812
4813                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentGfxclkIndex, &now);
4814
4815                 if (hwmgr->pp_one_vf &&
4816                     (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK))
4817                         count = 5;
4818                 else
4819                         count = sclk_table->count;
4820                 for (i = 0; i < count; i++)
4821                         size += sprintf(buf + size, "%d: %uMhz %s\n",
4822                                         i, sclk_table->dpm_levels[i].value / 100,
4823                                         (i == now) ? "*" : "");
4824                 break;
4825         case PP_MCLK:
4826                 if (data->registry_data.mclk_dpm_key_disabled)
4827                         break;
4828
4829                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex, &now);
4830
4831                 for (i = 0; i < mclk_table->count; i++)
4832                         size += sprintf(buf + size, "%d: %uMhz %s\n",
4833                                         i, mclk_table->dpm_levels[i].value / 100,
4834                                         (i == now) ? "*" : "");
4835                 break;
4836         case PP_SOCCLK:
4837                 if (data->registry_data.socclk_dpm_key_disabled)
4838                         break;
4839
4840                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentSocclkIndex, &now);
4841
4842                 for (i = 0; i < soc_table->count; i++)
4843                         size += sprintf(buf + size, "%d: %uMhz %s\n",
4844                                         i, soc_table->dpm_levels[i].value / 100,
4845                                         (i == now) ? "*" : "");
4846                 break;
4847         case PP_DCEFCLK:
4848                 if (data->registry_data.dcefclk_dpm_key_disabled)
4849                         break;
4850
4851                 smum_send_msg_to_smc_with_parameter(hwmgr,
4852                                 PPSMC_MSG_GetClockFreqMHz, CLK_DCEFCLK, &now);
4853
4854                 for (i = 0; i < dcef_table->count; i++)
4855                         size += sprintf(buf + size, "%d: %uMhz %s\n",
4856                                         i, dcef_table->dpm_levels[i].value / 100,
4857                                         (dcef_table->dpm_levels[i].value / 100 == now) ?
4858                                         "*" : "");
4859                 break;
4860         case PP_PCIE:
4861                 current_gen_speed =
4862                         vega10_get_current_pcie_link_speed_level(hwmgr);
4863                 current_lane_width =
4864                         vega10_get_current_pcie_link_width_level(hwmgr);
4865                 for (i = 0; i < NUM_LINK_LEVELS; i++) {
4866                         gen_speed = pptable->PcieGenSpeed[i];
4867                         lane_width = pptable->PcieLaneCount[i];
4868
4869                         size += sprintf(buf + size, "%d: %s %s %s\n", i,
4870                                         (gen_speed == 0) ? "2.5GT/s," :
4871                                         (gen_speed == 1) ? "5.0GT/s," :
4872                                         (gen_speed == 2) ? "8.0GT/s," :
4873                                         (gen_speed == 3) ? "16.0GT/s," : "",
4874                                         (lane_width == 1) ? "x1" :
4875                                         (lane_width == 2) ? "x2" :
4876                                         (lane_width == 3) ? "x4" :
4877                                         (lane_width == 4) ? "x8" :
4878                                         (lane_width == 5) ? "x12" :
4879                                         (lane_width == 6) ? "x16" : "",
4880                                         (current_gen_speed == gen_speed) &&
4881                                         (current_lane_width == lane_width) ?
4882                                         "*" : "");
4883                 }
4884                 break;
4885
4886         case OD_SCLK:
4887                 if (hwmgr->od_enabled) {
4888                         size += sprintf(buf + size, "%s:\n", "OD_SCLK");
4889                         podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_sclk;
4890                         for (i = 0; i < podn_vdd_dep->count; i++)
4891                                 size += sprintf(buf + size, "%d: %10uMhz %10umV\n",
4892                                         i, podn_vdd_dep->entries[i].clk / 100,
4893                                                 podn_vdd_dep->entries[i].vddc);
4894                 }
4895                 break;
4896         case OD_MCLK:
4897                 if (hwmgr->od_enabled) {
4898                         size += sprintf(buf + size, "%s:\n", "OD_MCLK");
4899                         podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_mclk;
4900                         for (i = 0; i < podn_vdd_dep->count; i++)
4901                                 size += sprintf(buf + size, "%d: %10uMhz %10umV\n",
4902                                         i, podn_vdd_dep->entries[i].clk/100,
4903                                                 podn_vdd_dep->entries[i].vddc);
4904                 }
4905                 break;
4906         case OD_RANGE:
4907                 if (hwmgr->od_enabled) {
4908                         size += sprintf(buf + size, "%s:\n", "OD_RANGE");
4909                         size += sprintf(buf + size, "SCLK: %7uMHz %10uMHz\n",
4910                                 data->golden_dpm_table.gfx_table.dpm_levels[0].value/100,
4911                                 hwmgr->platform_descriptor.overdriveLimit.engineClock/100);
4912                         size += sprintf(buf + size, "MCLK: %7uMHz %10uMHz\n",
4913                                 data->golden_dpm_table.mem_table.dpm_levels[0].value/100,
4914                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock/100);
4915                         size += sprintf(buf + size, "VDDC: %7umV %11umV\n",
4916                                 data->odn_dpm_table.min_vddc,
4917                                 data->odn_dpm_table.max_vddc);
4918                 }
4919                 break;
4920         default:
4921                 break;
4922         }
4923         return size;
4924 }
4925
4926 static int vega10_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
4927 {
4928         struct vega10_hwmgr *data = hwmgr->backend;
4929         Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table);
4930         int result = 0;
4931
4932         if ((data->water_marks_bitmap & WaterMarksExist) &&
4933                         !(data->water_marks_bitmap & WaterMarksLoaded)) {
4934                 result = smum_smc_table_manager(hwmgr, (uint8_t *)wm_table, WMTABLE, false);
4935                 PP_ASSERT_WITH_CODE(result, "Failed to update WMTABLE!", return -EINVAL);
4936                 data->water_marks_bitmap |= WaterMarksLoaded;
4937         }
4938
4939         if (data->water_marks_bitmap & WaterMarksLoaded) {
4940                 smum_send_msg_to_smc_with_parameter(hwmgr,
4941                         PPSMC_MSG_NumOfDisplays, hwmgr->display_config->num_display,
4942                         NULL);
4943         }
4944
4945         return result;
4946 }
4947
4948 static int vega10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
4949 {
4950         struct vega10_hwmgr *data = hwmgr->backend;
4951
4952         if (data->smu_features[GNLD_DPM_UVD].supported) {
4953                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
4954                                 enable,
4955                                 data->smu_features[GNLD_DPM_UVD].smu_feature_bitmap),
4956                                 "Attempt to Enable/Disable DPM UVD Failed!",
4957                                 return -1);
4958                 data->smu_features[GNLD_DPM_UVD].enabled = enable;
4959         }
4960         return 0;
4961 }
4962
4963 static void vega10_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate)
4964 {
4965         struct vega10_hwmgr *data = hwmgr->backend;
4966
4967         data->vce_power_gated = bgate;
4968         vega10_enable_disable_vce_dpm(hwmgr, !bgate);
4969 }
4970
4971 static void vega10_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
4972 {
4973         struct vega10_hwmgr *data = hwmgr->backend;
4974
4975         data->uvd_power_gated = bgate;
4976         vega10_enable_disable_uvd_dpm(hwmgr, !bgate);
4977 }
4978
4979 static inline bool vega10_are_power_levels_equal(
4980                                 const struct vega10_performance_level *pl1,
4981                                 const struct vega10_performance_level *pl2)
4982 {
4983         return ((pl1->soc_clock == pl2->soc_clock) &&
4984                         (pl1->gfx_clock == pl2->gfx_clock) &&
4985                         (pl1->mem_clock == pl2->mem_clock));
4986 }
4987
4988 static int vega10_check_states_equal(struct pp_hwmgr *hwmgr,
4989                                 const struct pp_hw_power_state *pstate1,
4990                         const struct pp_hw_power_state *pstate2, bool *equal)
4991 {
4992         const struct vega10_power_state *vega10_psa;
4993         const struct vega10_power_state *vega10_psb;
4994         int i;
4995
4996         if (pstate1 == NULL || pstate2 == NULL || equal == NULL)
4997                 return -EINVAL;
4998
4999         vega10_psa = cast_const_phw_vega10_power_state(pstate1);
5000         vega10_psb = cast_const_phw_vega10_power_state(pstate2);
5001
5002         /* If the two states don't even have the same number of performance levels
5003          * they cannot be the same state.
5004          */
5005         if (vega10_psa->performance_level_count != vega10_psb->performance_level_count) {
5006                 *equal = false;
5007                 return 0;
5008         }
5009
5010         for (i = 0; i < vega10_psa->performance_level_count; i++) {
5011                 if (!vega10_are_power_levels_equal(&(vega10_psa->performance_levels[i]),
5012                                                    &(vega10_psb->performance_levels[i]))) {
5013                         /* If we have found even one performance level pair
5014                          * that is different the states are different.
5015                          */
5016                         *equal = false;
5017                         return 0;
5018                 }
5019         }
5020
5021         /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
5022         *equal = ((vega10_psa->uvd_clks.vclk == vega10_psb->uvd_clks.vclk) &&
5023                   (vega10_psa->uvd_clks.dclk == vega10_psb->uvd_clks.dclk));
5024         *equal &= ((vega10_psa->vce_clks.evclk == vega10_psb->vce_clks.evclk) &&
5025                    (vega10_psa->vce_clks.ecclk == vega10_psb->vce_clks.ecclk));
5026         *equal &= (vega10_psa->sclk_threshold == vega10_psb->sclk_threshold);
5027
5028         return 0;
5029 }
5030
5031 static bool
5032 vega10_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
5033 {
5034         struct vega10_hwmgr *data = hwmgr->backend;
5035         bool is_update_required = false;
5036
5037         if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
5038                 is_update_required = true;
5039
5040         if (PP_CAP(PHM_PlatformCaps_SclkDeepSleep)) {
5041                 if (data->display_timing.min_clock_in_sr != hwmgr->display_config->min_core_set_clock_in_sr)
5042                         is_update_required = true;
5043         }
5044
5045         return is_update_required;
5046 }
5047
5048 static int vega10_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
5049 {
5050         int tmp_result, result = 0;
5051
5052         if (!hwmgr->not_vf)
5053                 return 0;
5054
5055         if (PP_CAP(PHM_PlatformCaps_ThermalController))
5056                 vega10_disable_thermal_protection(hwmgr);
5057
5058         tmp_result = vega10_disable_power_containment(hwmgr);
5059         PP_ASSERT_WITH_CODE((tmp_result == 0),
5060                         "Failed to disable power containment!", result = tmp_result);
5061
5062         tmp_result = vega10_disable_didt_config(hwmgr);
5063         PP_ASSERT_WITH_CODE((tmp_result == 0),
5064                         "Failed to disable didt config!", result = tmp_result);
5065
5066         tmp_result = vega10_avfs_enable(hwmgr, false);
5067         PP_ASSERT_WITH_CODE((tmp_result == 0),
5068                         "Failed to disable AVFS!", result = tmp_result);
5069
5070         tmp_result = vega10_stop_dpm(hwmgr, SMC_DPM_FEATURES);
5071         PP_ASSERT_WITH_CODE((tmp_result == 0),
5072                         "Failed to stop DPM!", result = tmp_result);
5073
5074         tmp_result = vega10_disable_deep_sleep_master_switch(hwmgr);
5075         PP_ASSERT_WITH_CODE((tmp_result == 0),
5076                         "Failed to disable deep sleep!", result = tmp_result);
5077
5078         tmp_result = vega10_disable_ulv(hwmgr);
5079         PP_ASSERT_WITH_CODE((tmp_result == 0),
5080                         "Failed to disable ulv!", result = tmp_result);
5081
5082         tmp_result =  vega10_acg_disable(hwmgr);
5083         PP_ASSERT_WITH_CODE((tmp_result == 0),
5084                         "Failed to disable acg!", result = tmp_result);
5085
5086         vega10_enable_disable_PCC_limit_feature(hwmgr, false);
5087         return result;
5088 }
5089
5090 static int vega10_power_off_asic(struct pp_hwmgr *hwmgr)
5091 {
5092         struct vega10_hwmgr *data = hwmgr->backend;
5093         int result;
5094
5095         result = vega10_disable_dpm_tasks(hwmgr);
5096         PP_ASSERT_WITH_CODE((0 == result),
5097                         "[disable_dpm_tasks] Failed to disable DPM!",
5098                         );
5099         data->water_marks_bitmap &= ~(WaterMarksLoaded);
5100
5101         return result;
5102 }
5103
5104 static int vega10_get_sclk_od(struct pp_hwmgr *hwmgr)
5105 {
5106         struct vega10_hwmgr *data = hwmgr->backend;
5107         struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
5108         struct vega10_single_dpm_table *golden_sclk_table =
5109                         &(data->golden_dpm_table.gfx_table);
5110         int value = sclk_table->dpm_levels[sclk_table->count - 1].value;
5111         int golden_value = golden_sclk_table->dpm_levels
5112                         [golden_sclk_table->count - 1].value;
5113
5114         value -= golden_value;
5115         value = DIV_ROUND_UP(value * 100, golden_value);
5116
5117         return value;
5118 }
5119
5120 static int vega10_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
5121 {
5122         struct vega10_hwmgr *data = hwmgr->backend;
5123         struct vega10_single_dpm_table *golden_sclk_table =
5124                         &(data->golden_dpm_table.gfx_table);
5125         struct pp_power_state *ps;
5126         struct vega10_power_state *vega10_ps;
5127
5128         ps = hwmgr->request_ps;
5129
5130         if (ps == NULL)
5131                 return -EINVAL;
5132
5133         vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
5134
5135         vega10_ps->performance_levels
5136         [vega10_ps->performance_level_count - 1].gfx_clock =
5137                         golden_sclk_table->dpm_levels
5138                         [golden_sclk_table->count - 1].value *
5139                         value / 100 +
5140                         golden_sclk_table->dpm_levels
5141                         [golden_sclk_table->count - 1].value;
5142
5143         if (vega10_ps->performance_levels
5144                         [vega10_ps->performance_level_count - 1].gfx_clock >
5145                         hwmgr->platform_descriptor.overdriveLimit.engineClock) {
5146                 vega10_ps->performance_levels
5147                 [vega10_ps->performance_level_count - 1].gfx_clock =
5148                                 hwmgr->platform_descriptor.overdriveLimit.engineClock;
5149                 pr_warn("max sclk supported by vbios is %d\n",
5150                                 hwmgr->platform_descriptor.overdriveLimit.engineClock);
5151         }
5152         return 0;
5153 }
5154
5155 static int vega10_get_mclk_od(struct pp_hwmgr *hwmgr)
5156 {
5157         struct vega10_hwmgr *data = hwmgr->backend;
5158         struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
5159         struct vega10_single_dpm_table *golden_mclk_table =
5160                         &(data->golden_dpm_table.mem_table);
5161         int value = mclk_table->dpm_levels[mclk_table->count - 1].value;
5162         int golden_value = golden_mclk_table->dpm_levels
5163                         [golden_mclk_table->count - 1].value;
5164
5165         value -= golden_value;
5166         value = DIV_ROUND_UP(value * 100, golden_value);
5167
5168         return value;
5169 }
5170
5171 static int vega10_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
5172 {
5173         struct vega10_hwmgr *data = hwmgr->backend;
5174         struct vega10_single_dpm_table *golden_mclk_table =
5175                         &(data->golden_dpm_table.mem_table);
5176         struct pp_power_state  *ps;
5177         struct vega10_power_state  *vega10_ps;
5178
5179         ps = hwmgr->request_ps;
5180
5181         if (ps == NULL)
5182                 return -EINVAL;
5183
5184         vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
5185
5186         vega10_ps->performance_levels
5187         [vega10_ps->performance_level_count - 1].mem_clock =
5188                         golden_mclk_table->dpm_levels
5189                         [golden_mclk_table->count - 1].value *
5190                         value / 100 +
5191                         golden_mclk_table->dpm_levels
5192                         [golden_mclk_table->count - 1].value;
5193
5194         if (vega10_ps->performance_levels
5195                         [vega10_ps->performance_level_count - 1].mem_clock >
5196                         hwmgr->platform_descriptor.overdriveLimit.memoryClock) {
5197                 vega10_ps->performance_levels
5198                 [vega10_ps->performance_level_count - 1].mem_clock =
5199                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock;
5200                 pr_warn("max mclk supported by vbios is %d\n",
5201                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock);
5202         }
5203
5204         return 0;
5205 }
5206
5207 static int vega10_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
5208                                         uint32_t virtual_addr_low,
5209                                         uint32_t virtual_addr_hi,
5210                                         uint32_t mc_addr_low,
5211                                         uint32_t mc_addr_hi,
5212                                         uint32_t size)
5213 {
5214         smum_send_msg_to_smc_with_parameter(hwmgr,
5215                                         PPSMC_MSG_SetSystemVirtualDramAddrHigh,
5216                                         virtual_addr_hi,
5217                                         NULL);
5218         smum_send_msg_to_smc_with_parameter(hwmgr,
5219                                         PPSMC_MSG_SetSystemVirtualDramAddrLow,
5220                                         virtual_addr_low,
5221                                         NULL);
5222         smum_send_msg_to_smc_with_parameter(hwmgr,
5223                                         PPSMC_MSG_DramLogSetDramAddrHigh,
5224                                         mc_addr_hi,
5225                                         NULL);
5226
5227         smum_send_msg_to_smc_with_parameter(hwmgr,
5228                                         PPSMC_MSG_DramLogSetDramAddrLow,
5229                                         mc_addr_low,
5230                                         NULL);
5231
5232         smum_send_msg_to_smc_with_parameter(hwmgr,
5233                                         PPSMC_MSG_DramLogSetDramSize,
5234                                         size,
5235                                         NULL);
5236         return 0;
5237 }
5238
5239 static int vega10_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
5240                 struct PP_TemperatureRange *thermal_data)
5241 {
5242         struct vega10_hwmgr *data = hwmgr->backend;
5243         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
5244
5245         memcpy(thermal_data, &SMU7ThermalWithDelayPolicy[0], sizeof(struct PP_TemperatureRange));
5246
5247         thermal_data->max = pp_table->TedgeLimit *
5248                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
5249         thermal_data->edge_emergency_max = (pp_table->TedgeLimit + CTF_OFFSET_EDGE) *
5250                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
5251         thermal_data->hotspot_crit_max = pp_table->ThotspotLimit *
5252                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
5253         thermal_data->hotspot_emergency_max = (pp_table->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
5254                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
5255         thermal_data->mem_crit_max = pp_table->ThbmLimit *
5256                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
5257         thermal_data->mem_emergency_max = (pp_table->ThbmLimit + CTF_OFFSET_HBM)*
5258                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
5259
5260         return 0;
5261 }
5262
5263 static int vega10_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
5264 {
5265         struct vega10_hwmgr *data = hwmgr->backend;
5266         uint32_t i, size = 0;
5267         static const uint8_t profile_mode_setting[6][4] = {{70, 60, 0, 0,},
5268                                                 {70, 60, 1, 3,},
5269                                                 {90, 60, 0, 0,},
5270                                                 {70, 60, 0, 0,},
5271                                                 {70, 90, 0, 0,},
5272                                                 {30, 60, 0, 6,},
5273                                                 };
5274         static const char *title[6] = {"NUM",
5275                         "MODE_NAME",
5276                         "BUSY_SET_POINT",
5277                         "FPS",
5278                         "USE_RLC_BUSY",
5279                         "MIN_ACTIVE_LEVEL"};
5280
5281         if (!buf)
5282                 return -EINVAL;
5283
5284         phm_get_sysfs_buf(&buf, &size);
5285
5286         size += sysfs_emit_at(buf, size, "%s %16s %s %s %s %s\n",title[0],
5287                         title[1], title[2], title[3], title[4], title[5]);
5288
5289         for (i = 0; i < PP_SMC_POWER_PROFILE_CUSTOM; i++)
5290                 size += sysfs_emit_at(buf, size, "%3d %14s%s: %14d %3d %10d %14d\n",
5291                         i, amdgpu_pp_profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ",
5292                         profile_mode_setting[i][0], profile_mode_setting[i][1],
5293                         profile_mode_setting[i][2], profile_mode_setting[i][3]);
5294
5295         size += sysfs_emit_at(buf, size, "%3d %14s%s: %14d %3d %10d %14d\n", i,
5296                         amdgpu_pp_profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ",
5297                         data->custom_profile_mode[0], data->custom_profile_mode[1],
5298                         data->custom_profile_mode[2], data->custom_profile_mode[3]);
5299         return size;
5300 }
5301
5302 static bool vega10_get_power_profile_mode_quirks(struct pp_hwmgr *hwmgr)
5303 {
5304         struct amdgpu_device *adev = hwmgr->adev;
5305
5306         return (adev->pdev->device == 0x6860);
5307 }
5308
5309 static int vega10_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)
5310 {
5311         struct vega10_hwmgr *data = hwmgr->backend;
5312         uint8_t busy_set_point;
5313         uint8_t FPS;
5314         uint8_t use_rlc_busy;
5315         uint8_t min_active_level;
5316         uint32_t power_profile_mode = input[size];
5317
5318         if (power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
5319                 if (size != 0 && size != 4)
5320                         return -EINVAL;
5321
5322                 /* If size = 0 and the CUSTOM profile has been set already
5323                  * then just apply the profile. The copy stored in the hwmgr
5324                  * is zeroed out on init
5325                  */
5326                 if (size == 0) {
5327                         if (data->custom_profile_mode[0] != 0)
5328                                 goto out;
5329                         else
5330                                 return -EINVAL;
5331                 }
5332
5333                 data->custom_profile_mode[0] = busy_set_point = input[0];
5334                 data->custom_profile_mode[1] = FPS = input[1];
5335                 data->custom_profile_mode[2] = use_rlc_busy = input[2];
5336                 data->custom_profile_mode[3] = min_active_level = input[3];
5337                 smum_send_msg_to_smc_with_parameter(hwmgr,
5338                                         PPSMC_MSG_SetCustomGfxDpmParameters,
5339                                         busy_set_point | FPS<<8 |
5340                                         use_rlc_busy << 16 | min_active_level<<24,
5341                                         NULL);
5342         }
5343
5344 out:
5345         if (vega10_get_power_profile_mode_quirks(hwmgr))
5346                 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask,
5347                                                 1 << power_profile_mode,
5348                                                 NULL);
5349         else
5350                 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask,
5351                                                 (!power_profile_mode) ? 0 : 1 << (power_profile_mode - 1),
5352                                                 NULL);
5353
5354         hwmgr->power_profile_mode = power_profile_mode;
5355
5356         return 0;
5357 }
5358
5359
5360 static bool vega10_check_clk_voltage_valid(struct pp_hwmgr *hwmgr,
5361                                         enum PP_OD_DPM_TABLE_COMMAND type,
5362                                         uint32_t clk,
5363                                         uint32_t voltage)
5364 {
5365         struct vega10_hwmgr *data = hwmgr->backend;
5366         struct vega10_odn_dpm_table *odn_table = &(data->odn_dpm_table);
5367         struct vega10_single_dpm_table *golden_table;
5368
5369         if (voltage < odn_table->min_vddc || voltage > odn_table->max_vddc) {
5370                 pr_info("OD voltage is out of range [%d - %d] mV\n", odn_table->min_vddc, odn_table->max_vddc);
5371                 return false;
5372         }
5373
5374         if (type == PP_OD_EDIT_SCLK_VDDC_TABLE) {
5375                 golden_table = &(data->golden_dpm_table.gfx_table);
5376                 if (golden_table->dpm_levels[0].value > clk ||
5377                         hwmgr->platform_descriptor.overdriveLimit.engineClock < clk) {
5378                         pr_info("OD engine clock is out of range [%d - %d] MHz\n",
5379                                 golden_table->dpm_levels[0].value/100,
5380                                 hwmgr->platform_descriptor.overdriveLimit.engineClock/100);
5381                         return false;
5382                 }
5383         } else if (type == PP_OD_EDIT_MCLK_VDDC_TABLE) {
5384                 golden_table = &(data->golden_dpm_table.mem_table);
5385                 if (golden_table->dpm_levels[0].value > clk ||
5386                         hwmgr->platform_descriptor.overdriveLimit.memoryClock < clk) {
5387                         pr_info("OD memory clock is out of range [%d - %d] MHz\n",
5388                                 golden_table->dpm_levels[0].value/100,
5389                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock/100);
5390                         return false;
5391                 }
5392         } else {
5393                 return false;
5394         }
5395
5396         return true;
5397 }
5398
5399 static void vega10_odn_update_power_state(struct pp_hwmgr *hwmgr)
5400 {
5401         struct vega10_hwmgr *data = hwmgr->backend;
5402         struct pp_power_state *ps = hwmgr->request_ps;
5403         struct vega10_power_state *vega10_ps;
5404         struct vega10_single_dpm_table *gfx_dpm_table =
5405                 &data->dpm_table.gfx_table;
5406         struct vega10_single_dpm_table *soc_dpm_table =
5407                 &data->dpm_table.soc_table;
5408         struct vega10_single_dpm_table *mem_dpm_table =
5409                 &data->dpm_table.mem_table;
5410         int max_level;
5411
5412         if (!ps)
5413                 return;
5414
5415         vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
5416         max_level = vega10_ps->performance_level_count - 1;
5417
5418         if (vega10_ps->performance_levels[max_level].gfx_clock !=
5419             gfx_dpm_table->dpm_levels[gfx_dpm_table->count - 1].value)
5420                 vega10_ps->performance_levels[max_level].gfx_clock =
5421                         gfx_dpm_table->dpm_levels[gfx_dpm_table->count - 1].value;
5422
5423         if (vega10_ps->performance_levels[max_level].soc_clock !=
5424             soc_dpm_table->dpm_levels[soc_dpm_table->count - 1].value)
5425                 vega10_ps->performance_levels[max_level].soc_clock =
5426                         soc_dpm_table->dpm_levels[soc_dpm_table->count - 1].value;
5427
5428         if (vega10_ps->performance_levels[max_level].mem_clock !=
5429             mem_dpm_table->dpm_levels[mem_dpm_table->count - 1].value)
5430                 vega10_ps->performance_levels[max_level].mem_clock =
5431                         mem_dpm_table->dpm_levels[mem_dpm_table->count - 1].value;
5432
5433         if (!hwmgr->ps)
5434                 return;
5435
5436         ps = (struct pp_power_state *)((unsigned long)(hwmgr->ps) + hwmgr->ps_size * (hwmgr->num_ps - 1));
5437         vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
5438         max_level = vega10_ps->performance_level_count - 1;
5439
5440         if (vega10_ps->performance_levels[max_level].gfx_clock !=
5441             gfx_dpm_table->dpm_levels[gfx_dpm_table->count - 1].value)
5442                 vega10_ps->performance_levels[max_level].gfx_clock =
5443                         gfx_dpm_table->dpm_levels[gfx_dpm_table->count - 1].value;
5444
5445         if (vega10_ps->performance_levels[max_level].soc_clock !=
5446             soc_dpm_table->dpm_levels[soc_dpm_table->count - 1].value)
5447                 vega10_ps->performance_levels[max_level].soc_clock =
5448                         soc_dpm_table->dpm_levels[soc_dpm_table->count - 1].value;
5449
5450         if (vega10_ps->performance_levels[max_level].mem_clock !=
5451             mem_dpm_table->dpm_levels[mem_dpm_table->count - 1].value)
5452                 vega10_ps->performance_levels[max_level].mem_clock =
5453                         mem_dpm_table->dpm_levels[mem_dpm_table->count - 1].value;
5454 }
5455
5456 static void vega10_odn_update_soc_table(struct pp_hwmgr *hwmgr,
5457                                                 enum PP_OD_DPM_TABLE_COMMAND type)
5458 {
5459         struct vega10_hwmgr *data = hwmgr->backend;
5460         struct phm_ppt_v2_information *table_info = hwmgr->pptable;
5461         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table = table_info->vdd_dep_on_socclk;
5462         struct vega10_single_dpm_table *dpm_table = &data->golden_dpm_table.mem_table;
5463
5464         struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep_on_socclk =
5465                                                         &data->odn_dpm_table.vdd_dep_on_socclk;
5466         struct vega10_odn_vddc_lookup_table *od_vddc_lookup_table = &data->odn_dpm_table.vddc_lookup_table;
5467
5468         struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep;
5469         uint8_t i, j;
5470
5471         if (type == PP_OD_EDIT_SCLK_VDDC_TABLE) {
5472                 podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_sclk;
5473                 for (i = 0; i < podn_vdd_dep->count; i++)
5474                         od_vddc_lookup_table->entries[i].us_vdd = podn_vdd_dep->entries[i].vddc;
5475         } else if (type == PP_OD_EDIT_MCLK_VDDC_TABLE) {
5476                 podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_mclk;
5477                 for (i = 0; i < dpm_table->count; i++) {
5478                         for (j = 0; j < od_vddc_lookup_table->count; j++) {
5479                                 if (od_vddc_lookup_table->entries[j].us_vdd >
5480                                         podn_vdd_dep->entries[i].vddc)
5481                                         break;
5482                         }
5483                         if (j == od_vddc_lookup_table->count) {
5484                                 j = od_vddc_lookup_table->count - 1;
5485                                 od_vddc_lookup_table->entries[j].us_vdd =
5486                                         podn_vdd_dep->entries[i].vddc;
5487                                 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC;
5488                         }
5489                         podn_vdd_dep->entries[i].vddInd = j;
5490                 }
5491                 dpm_table = &data->dpm_table.soc_table;
5492                 for (i = 0; i < dep_table->count; i++) {
5493                         if (dep_table->entries[i].vddInd == podn_vdd_dep->entries[podn_vdd_dep->count-1].vddInd &&
5494                                         dep_table->entries[i].clk < podn_vdd_dep->entries[podn_vdd_dep->count-1].clk) {
5495                                 data->need_update_dpm_table |= DPMTABLE_UPDATE_SOCCLK;
5496                                 for (; (i < dep_table->count) &&
5497                                        (dep_table->entries[i].clk < podn_vdd_dep->entries[podn_vdd_dep->count - 1].clk); i++) {
5498                                         podn_vdd_dep_on_socclk->entries[i].clk = podn_vdd_dep->entries[podn_vdd_dep->count-1].clk;
5499                                         dpm_table->dpm_levels[i].value = podn_vdd_dep_on_socclk->entries[i].clk;
5500                                 }
5501                                 break;
5502                         } else {
5503                                 dpm_table->dpm_levels[i].value = dep_table->entries[i].clk;
5504                                 podn_vdd_dep_on_socclk->entries[i].vddc = dep_table->entries[i].vddc;
5505                                 podn_vdd_dep_on_socclk->entries[i].vddInd = dep_table->entries[i].vddInd;
5506                                 podn_vdd_dep_on_socclk->entries[i].clk = dep_table->entries[i].clk;
5507                         }
5508                 }
5509                 if (podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].clk <
5510                                         podn_vdd_dep->entries[podn_vdd_dep->count - 1].clk) {
5511                         data->need_update_dpm_table |= DPMTABLE_UPDATE_SOCCLK;
5512                         podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].clk =
5513                                 podn_vdd_dep->entries[podn_vdd_dep->count - 1].clk;
5514                         dpm_table->dpm_levels[podn_vdd_dep_on_socclk->count - 1].value =
5515                                 podn_vdd_dep->entries[podn_vdd_dep->count - 1].clk;
5516                 }
5517                 if (podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].vddInd <
5518                                         podn_vdd_dep->entries[podn_vdd_dep->count - 1].vddInd) {
5519                         data->need_update_dpm_table |= DPMTABLE_UPDATE_SOCCLK;
5520                         podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].vddInd =
5521                                 podn_vdd_dep->entries[podn_vdd_dep->count - 1].vddInd;
5522                 }
5523         }
5524         vega10_odn_update_power_state(hwmgr);
5525 }
5526
5527 static int vega10_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
5528                                         enum PP_OD_DPM_TABLE_COMMAND type,
5529                                         long *input, uint32_t size)
5530 {
5531         struct vega10_hwmgr *data = hwmgr->backend;
5532         struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep_table;
5533         struct vega10_single_dpm_table *dpm_table;
5534
5535         uint32_t input_clk;
5536         uint32_t input_vol;
5537         uint32_t input_level;
5538         uint32_t i;
5539
5540         PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage",
5541                                 return -EINVAL);
5542
5543         if (!hwmgr->od_enabled) {
5544                 pr_info("OverDrive feature not enabled\n");
5545                 return -EINVAL;
5546         }
5547
5548         if (PP_OD_EDIT_SCLK_VDDC_TABLE == type) {
5549                 dpm_table = &data->dpm_table.gfx_table;
5550                 podn_vdd_dep_table = &data->odn_dpm_table.vdd_dep_on_sclk;
5551                 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
5552         } else if (PP_OD_EDIT_MCLK_VDDC_TABLE == type) {
5553                 dpm_table = &data->dpm_table.mem_table;
5554                 podn_vdd_dep_table = &data->odn_dpm_table.vdd_dep_on_mclk;
5555                 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
5556         } else if (PP_OD_RESTORE_DEFAULT_TABLE == type) {
5557                 memcpy(&(data->dpm_table), &(data->golden_dpm_table), sizeof(struct vega10_dpm_table));
5558                 vega10_odn_initial_default_setting(hwmgr);
5559                 vega10_odn_update_power_state(hwmgr);
5560                 /* force to update all clock tables */
5561                 data->need_update_dpm_table = DPMTABLE_UPDATE_SCLK |
5562                                               DPMTABLE_UPDATE_MCLK |
5563                                               DPMTABLE_UPDATE_SOCCLK;
5564                 return 0;
5565         } else if (PP_OD_COMMIT_DPM_TABLE == type) {
5566                 vega10_check_dpm_table_updated(hwmgr);
5567                 return 0;
5568         } else {
5569                 return -EINVAL;
5570         }
5571
5572         for (i = 0; i < size; i += 3) {
5573                 if (i + 3 > size || input[i] >= podn_vdd_dep_table->count) {
5574                         pr_info("invalid clock voltage input\n");
5575                         return 0;
5576                 }
5577                 input_level = input[i];
5578                 input_clk = input[i+1] * 100;
5579                 input_vol = input[i+2];
5580
5581                 if (vega10_check_clk_voltage_valid(hwmgr, type, input_clk, input_vol)) {
5582                         dpm_table->dpm_levels[input_level].value = input_clk;
5583                         podn_vdd_dep_table->entries[input_level].clk = input_clk;
5584                         podn_vdd_dep_table->entries[input_level].vddc = input_vol;
5585                 } else {
5586                         return -EINVAL;
5587                 }
5588         }
5589         vega10_odn_update_soc_table(hwmgr, type);
5590         return 0;
5591 }
5592
5593 static int vega10_set_mp1_state(struct pp_hwmgr *hwmgr,
5594                                 enum pp_mp1_state mp1_state)
5595 {
5596         uint16_t msg;
5597         int ret;
5598
5599         switch (mp1_state) {
5600         case PP_MP1_STATE_UNLOAD:
5601                 msg = PPSMC_MSG_PrepareMp1ForUnload;
5602                 break;
5603         case PP_MP1_STATE_SHUTDOWN:
5604         case PP_MP1_STATE_RESET:
5605         case PP_MP1_STATE_NONE:
5606         default:
5607                 return 0;
5608         }
5609
5610         PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr, msg, NULL)) == 0,
5611                             "[PrepareMp1] Failed!",
5612                             return ret);
5613
5614         return 0;
5615 }
5616
5617 static int vega10_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
5618                                 PHM_PerformanceLevelDesignation designation, uint32_t index,
5619                                 PHM_PerformanceLevel *level)
5620 {
5621         const struct vega10_power_state *vega10_ps;
5622         uint32_t i;
5623
5624         if (level == NULL || hwmgr == NULL || state == NULL)
5625                 return -EINVAL;
5626
5627         vega10_ps = cast_const_phw_vega10_power_state(state);
5628
5629         i = index > vega10_ps->performance_level_count - 1 ?
5630                         vega10_ps->performance_level_count - 1 : index;
5631
5632         level->coreClock = vega10_ps->performance_levels[i].gfx_clock;
5633         level->memory_clock = vega10_ps->performance_levels[i].mem_clock;
5634
5635         return 0;
5636 }
5637
5638 static int vega10_disable_power_features_for_compute_performance(struct pp_hwmgr *hwmgr, bool disable)
5639 {
5640         struct vega10_hwmgr *data = hwmgr->backend;
5641         uint32_t feature_mask = 0;
5642
5643         if (disable) {
5644                 feature_mask |= data->smu_features[GNLD_ULV].enabled ?
5645                         data->smu_features[GNLD_ULV].smu_feature_bitmap : 0;
5646                 feature_mask |= data->smu_features[GNLD_DS_GFXCLK].enabled ?
5647                         data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap : 0;
5648                 feature_mask |= data->smu_features[GNLD_DS_SOCCLK].enabled ?
5649                         data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap : 0;
5650                 feature_mask |= data->smu_features[GNLD_DS_LCLK].enabled ?
5651                         data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap : 0;
5652                 feature_mask |= data->smu_features[GNLD_DS_DCEFCLK].enabled ?
5653                         data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap : 0;
5654         } else {
5655                 feature_mask |= (!data->smu_features[GNLD_ULV].enabled) ?
5656                         data->smu_features[GNLD_ULV].smu_feature_bitmap : 0;
5657                 feature_mask |= (!data->smu_features[GNLD_DS_GFXCLK].enabled) ?
5658                         data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap : 0;
5659                 feature_mask |= (!data->smu_features[GNLD_DS_SOCCLK].enabled) ?
5660                         data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap : 0;
5661                 feature_mask |= (!data->smu_features[GNLD_DS_LCLK].enabled) ?
5662                         data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap : 0;
5663                 feature_mask |= (!data->smu_features[GNLD_DS_DCEFCLK].enabled) ?
5664                         data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap : 0;
5665         }
5666
5667         if (feature_mask)
5668                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
5669                                 !disable, feature_mask),
5670                                 "enable/disable power features for compute performance Failed!",
5671                                 return -EINVAL);
5672
5673         if (disable) {
5674                 data->smu_features[GNLD_ULV].enabled = false;
5675                 data->smu_features[GNLD_DS_GFXCLK].enabled = false;
5676                 data->smu_features[GNLD_DS_SOCCLK].enabled = false;
5677                 data->smu_features[GNLD_DS_LCLK].enabled = false;
5678                 data->smu_features[GNLD_DS_DCEFCLK].enabled = false;
5679         } else {
5680                 data->smu_features[GNLD_ULV].enabled = true;
5681                 data->smu_features[GNLD_DS_GFXCLK].enabled = true;
5682                 data->smu_features[GNLD_DS_SOCCLK].enabled = true;
5683                 data->smu_features[GNLD_DS_LCLK].enabled = true;
5684                 data->smu_features[GNLD_DS_DCEFCLK].enabled = true;
5685         }
5686
5687         return 0;
5688
5689 }
5690
5691 static const struct pp_hwmgr_func vega10_hwmgr_funcs = {
5692         .backend_init = vega10_hwmgr_backend_init,
5693         .backend_fini = vega10_hwmgr_backend_fini,
5694         .asic_setup = vega10_setup_asic_task,
5695         .dynamic_state_management_enable = vega10_enable_dpm_tasks,
5696         .dynamic_state_management_disable = vega10_disable_dpm_tasks,
5697         .get_num_of_pp_table_entries =
5698                         vega10_get_number_of_powerplay_table_entries,
5699         .get_power_state_size = vega10_get_power_state_size,
5700         .get_pp_table_entry = vega10_get_pp_table_entry,
5701         .patch_boot_state = vega10_patch_boot_state,
5702         .apply_state_adjust_rules = vega10_apply_state_adjust_rules,
5703         .power_state_set = vega10_set_power_state_tasks,
5704         .get_sclk = vega10_dpm_get_sclk,
5705         .get_mclk = vega10_dpm_get_mclk,
5706         .notify_smc_display_config_after_ps_adjustment =
5707                         vega10_notify_smc_display_config_after_ps_adjustment,
5708         .force_dpm_level = vega10_dpm_force_dpm_level,
5709         .stop_thermal_controller = vega10_thermal_stop_thermal_controller,
5710         .get_fan_speed_info = vega10_fan_ctrl_get_fan_speed_info,
5711         .get_fan_speed_pwm = vega10_fan_ctrl_get_fan_speed_pwm,
5712         .set_fan_speed_pwm = vega10_fan_ctrl_set_fan_speed_pwm,
5713         .reset_fan_speed_to_default =
5714                         vega10_fan_ctrl_reset_fan_speed_to_default,
5715         .get_fan_speed_rpm = vega10_fan_ctrl_get_fan_speed_rpm,
5716         .set_fan_speed_rpm = vega10_fan_ctrl_set_fan_speed_rpm,
5717         .uninitialize_thermal_controller =
5718                         vega10_thermal_ctrl_uninitialize_thermal_controller,
5719         .set_fan_control_mode = vega10_set_fan_control_mode,
5720         .get_fan_control_mode = vega10_get_fan_control_mode,
5721         .read_sensor = vega10_read_sensor,
5722         .get_dal_power_level = vega10_get_dal_power_level,
5723         .get_clock_by_type_with_latency = vega10_get_clock_by_type_with_latency,
5724         .get_clock_by_type_with_voltage = vega10_get_clock_by_type_with_voltage,
5725         .set_watermarks_for_clocks_ranges = vega10_set_watermarks_for_clocks_ranges,
5726         .display_clock_voltage_request = vega10_display_clock_voltage_request,
5727         .force_clock_level = vega10_force_clock_level,
5728         .emit_clock_levels = vega10_emit_clock_levels,
5729         .print_clock_levels = vega10_print_clock_levels,
5730         .display_config_changed = vega10_display_configuration_changed_task,
5731         .powergate_uvd = vega10_power_gate_uvd,
5732         .powergate_vce = vega10_power_gate_vce,
5733         .check_states_equal = vega10_check_states_equal,
5734         .check_smc_update_required_for_display_configuration =
5735                         vega10_check_smc_update_required_for_display_configuration,
5736         .power_off_asic = vega10_power_off_asic,
5737         .disable_smc_firmware_ctf = vega10_thermal_disable_alert,
5738         .get_sclk_od = vega10_get_sclk_od,
5739         .set_sclk_od = vega10_set_sclk_od,
5740         .get_mclk_od = vega10_get_mclk_od,
5741         .set_mclk_od = vega10_set_mclk_od,
5742         .avfs_control = vega10_avfs_enable,
5743         .notify_cac_buffer_info = vega10_notify_cac_buffer_info,
5744         .get_thermal_temperature_range = vega10_get_thermal_temperature_range,
5745         .register_irq_handlers = smu9_register_irq_handlers,
5746         .start_thermal_controller = vega10_start_thermal_controller,
5747         .get_power_profile_mode = vega10_get_power_profile_mode,
5748         .set_power_profile_mode = vega10_set_power_profile_mode,
5749         .set_power_limit = vega10_set_power_limit,
5750         .odn_edit_dpm_table = vega10_odn_edit_dpm_table,
5751         .get_performance_level = vega10_get_performance_level,
5752         .get_asic_baco_capability = smu9_baco_get_capability,
5753         .get_asic_baco_state = smu9_baco_get_state,
5754         .set_asic_baco_state = vega10_baco_set_state,
5755         .enable_mgpu_fan_boost = vega10_enable_mgpu_fan_boost,
5756         .get_ppfeature_status = vega10_get_ppfeature_status,
5757         .set_ppfeature_status = vega10_set_ppfeature_status,
5758         .set_mp1_state = vega10_set_mp1_state,
5759         .disable_power_features_for_compute_performance =
5760                         vega10_disable_power_features_for_compute_performance,
5761 };
5762
5763 int vega10_hwmgr_init(struct pp_hwmgr *hwmgr)
5764 {
5765         struct amdgpu_device *adev = hwmgr->adev;
5766
5767         hwmgr->hwmgr_func = &vega10_hwmgr_funcs;
5768         hwmgr->pptable_func = &vega10_pptable_funcs;
5769         if (amdgpu_passthrough(adev))
5770                 return vega10_baco_set_cap(hwmgr);
5771
5772         return 0;
5773 }