2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/types.h>
25 #include <linux/kernel.h>
26 #include <linux/slab.h>
27 #include "atom-types.h"
29 #include "processpptables.h"
30 #include "cgs_common.h"
33 #include "hardwaremanager.h"
35 #include "smu10_hwmgr.h"
36 #include "power_state.h"
37 #include "soc15_common.h"
39 #include "asic_reg/pwr/pwr_10_0_offset.h"
40 #include "asic_reg/pwr/pwr_10_0_sh_mask.h"
42 #define SMU10_MAX_DEEPSLEEP_DIVIDER_ID 5
43 #define SMU10_MINIMUM_ENGINE_CLOCK 800 /* 8Mhz, the low boundary of engine clock allowed on this chip */
44 #define SCLK_MIN_DIV_INTV_SHIFT 12
45 #define SMU10_DISPCLK_BYPASS_THRESHOLD 10000 /* 100Mhz */
46 #define SMC_RAM_END 0x40000
48 static const unsigned long SMU10_Magic = (unsigned long) PHM_Rv_Magic;
51 static int smu10_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
52 struct pp_display_clock_request *clock_req)
54 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
55 enum amd_pp_clock_type clk_type = clock_req->clock_type;
56 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
60 case amd_pp_dcf_clock:
61 if (clk_freq == smu10_data->dcf_actual_hard_min_freq)
63 msg = PPSMC_MSG_SetHardMinDcefclkByFreq;
64 smu10_data->dcf_actual_hard_min_freq = clk_freq;
66 case amd_pp_soc_clock:
67 msg = PPSMC_MSG_SetHardMinSocclkByFreq;
70 if (clk_freq == smu10_data->f_actual_hard_min_freq)
72 smu10_data->f_actual_hard_min_freq = clk_freq;
73 msg = PPSMC_MSG_SetHardMinFclkByFreq;
76 pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!");
79 smum_send_msg_to_smc_with_parameter(hwmgr, msg, clk_freq, NULL);
84 static struct smu10_power_state *cast_smu10_ps(struct pp_hw_power_state *hw_ps)
86 if (SMU10_Magic != hw_ps->magic)
89 return (struct smu10_power_state *)hw_ps;
92 static const struct smu10_power_state *cast_const_smu10_ps(
93 const struct pp_hw_power_state *hw_ps)
95 if (SMU10_Magic != hw_ps->magic)
98 return (struct smu10_power_state *)hw_ps;
101 static int smu10_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
103 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
105 smu10_data->dce_slow_sclk_threshold = 30000;
106 smu10_data->thermal_auto_throttling_treshold = 0;
107 smu10_data->is_nb_dpm_enabled = 1;
108 smu10_data->dpm_flags = 1;
109 smu10_data->need_min_deep_sleep_dcefclk = true;
110 smu10_data->num_active_display = 0;
111 smu10_data->deep_sleep_dcefclk = 0;
113 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
114 PHM_PlatformCaps_SclkDeepSleep);
116 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
117 PHM_PlatformCaps_SclkThrottleLowNotification);
119 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
120 PHM_PlatformCaps_PowerPlaySupport);
124 static int smu10_construct_max_power_limits_table(struct pp_hwmgr *hwmgr,
125 struct phm_clock_and_voltage_limits *table)
130 static int smu10_init_dynamic_state_adjustment_rule_settings(
131 struct pp_hwmgr *hwmgr)
134 struct phm_clock_voltage_dependency_table *table_clk_vlt;
136 table_clk_vlt = kzalloc(struct_size(table_clk_vlt, entries, count),
139 if (NULL == table_clk_vlt) {
140 pr_err("Can not allocate memory!\n");
144 table_clk_vlt->count = count;
145 table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_0;
146 table_clk_vlt->entries[0].v = 0;
147 table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_1;
148 table_clk_vlt->entries[1].v = 1;
149 table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_2;
150 table_clk_vlt->entries[2].v = 2;
151 table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_3;
152 table_clk_vlt->entries[3].v = 3;
153 table_clk_vlt->entries[4].clk = PP_DAL_POWERLEVEL_4;
154 table_clk_vlt->entries[4].v = 4;
155 table_clk_vlt->entries[5].clk = PP_DAL_POWERLEVEL_5;
156 table_clk_vlt->entries[5].v = 5;
157 table_clk_vlt->entries[6].clk = PP_DAL_POWERLEVEL_6;
158 table_clk_vlt->entries[6].v = 6;
159 table_clk_vlt->entries[7].clk = PP_DAL_POWERLEVEL_7;
160 table_clk_vlt->entries[7].v = 7;
161 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt;
166 static int smu10_get_system_info_data(struct pp_hwmgr *hwmgr)
168 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)hwmgr->backend;
170 smu10_data->sys_info.htc_hyst_lmt = 5;
171 smu10_data->sys_info.htc_tmp_lmt = 203;
173 if (smu10_data->thermal_auto_throttling_treshold == 0)
174 smu10_data->thermal_auto_throttling_treshold = 203;
176 smu10_construct_max_power_limits_table (hwmgr,
177 &hwmgr->dyn_state.max_clock_voltage_on_ac);
179 smu10_init_dynamic_state_adjustment_rule_settings(hwmgr);
184 static int smu10_construct_boot_state(struct pp_hwmgr *hwmgr)
189 static int smu10_set_clock_limit(struct pp_hwmgr *hwmgr, const void *input)
191 struct PP_Clocks clocks = {0};
192 struct pp_display_clock_request clock_req;
194 clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
195 clock_req.clock_type = amd_pp_dcf_clock;
196 clock_req.clock_freq_in_khz = clocks.dcefClock * 10;
198 PP_ASSERT_WITH_CODE(!smu10_display_clock_voltage_request(hwmgr, &clock_req),
199 "Attempt to set DCF Clock Failed!", return -EINVAL);
204 static int smu10_set_min_deep_sleep_dcefclk(struct pp_hwmgr *hwmgr, uint32_t clock)
206 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
208 if (clock && smu10_data->deep_sleep_dcefclk != clock) {
209 smu10_data->deep_sleep_dcefclk = clock;
210 smum_send_msg_to_smc_with_parameter(hwmgr,
211 PPSMC_MSG_SetMinDeepSleepDcefclk,
212 smu10_data->deep_sleep_dcefclk,
218 static int smu10_set_hard_min_dcefclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock)
220 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
222 if (clock && smu10_data->dcf_actual_hard_min_freq != clock) {
223 smu10_data->dcf_actual_hard_min_freq = clock;
224 smum_send_msg_to_smc_with_parameter(hwmgr,
225 PPSMC_MSG_SetHardMinDcefclkByFreq,
226 smu10_data->dcf_actual_hard_min_freq,
232 static int smu10_set_hard_min_fclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock)
234 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
236 if (clock && smu10_data->f_actual_hard_min_freq != clock) {
237 smu10_data->f_actual_hard_min_freq = clock;
238 smum_send_msg_to_smc_with_parameter(hwmgr,
239 PPSMC_MSG_SetHardMinFclkByFreq,
240 smu10_data->f_actual_hard_min_freq,
246 static int smu10_set_hard_min_gfxclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock)
248 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
250 if (clock && smu10_data->gfx_actual_soft_min_freq != clock) {
251 smu10_data->gfx_actual_soft_min_freq = clock;
252 smum_send_msg_to_smc_with_parameter(hwmgr,
253 PPSMC_MSG_SetHardMinGfxClk,
260 static int smu10_set_soft_max_gfxclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock)
262 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
264 if (clock && smu10_data->gfx_max_freq_limit != (clock * 100)) {
265 smu10_data->gfx_max_freq_limit = clock * 100;
266 smum_send_msg_to_smc_with_parameter(hwmgr,
267 PPSMC_MSG_SetSoftMaxGfxClk,
274 static int smu10_set_active_display_count(struct pp_hwmgr *hwmgr, uint32_t count)
276 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
278 if (smu10_data->num_active_display != count) {
279 smu10_data->num_active_display = count;
280 smum_send_msg_to_smc_with_parameter(hwmgr,
281 PPSMC_MSG_SetDisplayCount,
282 smu10_data->num_active_display,
289 static int smu10_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
291 return smu10_set_clock_limit(hwmgr, input);
294 static int smu10_init_power_gate_state(struct pp_hwmgr *hwmgr)
296 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
297 struct amdgpu_device *adev = hwmgr->adev;
299 smu10_data->vcn_power_gated = true;
300 smu10_data->isp_tileA_power_gated = true;
301 smu10_data->isp_tileB_power_gated = true;
303 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)
304 return smum_send_msg_to_smc_with_parameter(hwmgr,
305 PPSMC_MSG_SetGfxCGPG,
313 static int smu10_setup_asic_task(struct pp_hwmgr *hwmgr)
315 return smu10_init_power_gate_state(hwmgr);
318 static int smu10_reset_cc6_data(struct pp_hwmgr *hwmgr)
320 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
322 smu10_data->separation_time = 0;
323 smu10_data->cc6_disable = false;
324 smu10_data->pstate_disable = false;
325 smu10_data->cc6_setting_changed = false;
330 static int smu10_power_off_asic(struct pp_hwmgr *hwmgr)
332 return smu10_reset_cc6_data(hwmgr);
335 static bool smu10_is_gfx_on(struct pp_hwmgr *hwmgr)
338 struct amdgpu_device *adev = hwmgr->adev;
340 reg = RREG32_SOC15(PWR, 0, mmPWR_MISC_CNTL_STATUS);
341 if ((reg & PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK) ==
342 (0x2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT))
348 static int smu10_disable_gfx_off(struct pp_hwmgr *hwmgr)
350 struct amdgpu_device *adev = hwmgr->adev;
352 if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
353 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableGfxOff, NULL);
355 /* confirm gfx is back to "on" state */
356 while (!smu10_is_gfx_on(hwmgr))
363 static int smu10_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
368 static int smu10_enable_gfx_off(struct pp_hwmgr *hwmgr)
370 struct amdgpu_device *adev = hwmgr->adev;
372 if (adev->pm.pp_feature & PP_GFXOFF_MASK)
373 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableGfxOff, NULL);
378 static int smu10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
380 struct amdgpu_device *adev = hwmgr->adev;
381 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
384 if (adev->in_suspend) {
385 pr_info("restore the fine grain parameters\n");
387 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
388 PPSMC_MSG_SetHardMinGfxClk,
389 smu10_data->gfx_actual_soft_min_freq,
393 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
394 PPSMC_MSG_SetSoftMaxGfxClk,
395 smu10_data->gfx_actual_soft_max_freq,
404 static int smu10_gfx_off_control(struct pp_hwmgr *hwmgr, bool enable)
407 return smu10_enable_gfx_off(hwmgr);
409 return smu10_disable_gfx_off(hwmgr);
412 static int smu10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
413 struct pp_power_state *prequest_ps,
414 const struct pp_power_state *pcurrent_ps)
419 /* temporary hardcoded clock voltage breakdown tables */
420 static const DpmClock_t VddDcfClk[]= {
426 static const DpmClock_t VddSocClk[]= {
432 static const DpmClock_t VddFClk[]= {
438 static const DpmClock_t VddDispClk[]= {
444 static const DpmClock_t VddDppClk[]= {
450 static const DpmClock_t VddPhyClk[]= {
456 static int smu10_get_clock_voltage_dependency_table(struct pp_hwmgr *hwmgr,
457 struct smu10_voltage_dependency_table **pptable,
458 uint32_t num_entry, const DpmClock_t *pclk_dependency_table)
461 struct smu10_voltage_dependency_table *ptable;
463 ptable = kzalloc(struct_size(ptable, entries, num_entry), GFP_KERNEL);
467 ptable->count = num_entry;
469 for (i = 0; i < ptable->count; i++) {
470 ptable->entries[i].clk = pclk_dependency_table->Freq * 100;
471 ptable->entries[i].vol = pclk_dependency_table->Vol;
472 pclk_dependency_table++;
481 static int smu10_populate_clock_table(struct pp_hwmgr *hwmgr)
485 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
486 DpmClocks_t *table = &(smu10_data->clock_table);
487 struct smu10_clock_voltage_information *pinfo = &(smu10_data->clock_vol_info);
489 result = smum_smc_table_manager(hwmgr, (uint8_t *)table, SMU10_CLOCKTABLE, true);
491 PP_ASSERT_WITH_CODE((0 == result),
492 "Attempt to copy clock table from smc failed",
495 if (0 == result && table->DcefClocks[0].Freq != 0) {
496 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dcefclk,
497 NUM_DCEFCLK_DPM_LEVELS,
498 &smu10_data->clock_table.DcefClocks[0]);
499 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_socclk,
500 NUM_SOCCLK_DPM_LEVELS,
501 &smu10_data->clock_table.SocClocks[0]);
502 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_fclk,
504 &smu10_data->clock_table.FClocks[0]);
505 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_mclk,
506 NUM_MEMCLK_DPM_LEVELS,
507 &smu10_data->clock_table.MemClocks[0]);
509 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dcefclk,
510 ARRAY_SIZE(VddDcfClk),
512 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_socclk,
513 ARRAY_SIZE(VddSocClk),
515 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_fclk,
519 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dispclk,
520 ARRAY_SIZE(VddDispClk),
522 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dppclk,
523 ARRAY_SIZE(VddDppClk), &VddDppClk[0]);
524 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_phyclk,
525 ARRAY_SIZE(VddPhyClk), &VddPhyClk[0]);
527 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &result);
528 smu10_data->gfx_min_freq_limit = result / 10 * 1000;
530 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &result);
531 smu10_data->gfx_max_freq_limit = result / 10 * 1000;
536 static int smu10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
539 struct smu10_hwmgr *data;
541 data = kzalloc(sizeof(struct smu10_hwmgr), GFP_KERNEL);
545 hwmgr->backend = data;
547 result = smu10_initialize_dpm_defaults(hwmgr);
549 pr_err("smu10_initialize_dpm_defaults failed\n");
553 smu10_populate_clock_table(hwmgr);
555 result = smu10_get_system_info_data(hwmgr);
557 pr_err("smu10_get_system_info_data failed\n");
561 smu10_construct_boot_state(hwmgr);
563 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
564 SMU10_MAX_HARDWARE_POWERLEVELS;
566 hwmgr->platform_descriptor.hardwarePerformanceLevels =
567 SMU10_MAX_HARDWARE_POWERLEVELS;
569 hwmgr->platform_descriptor.vbiosInterruptId = 0;
571 hwmgr->platform_descriptor.clockStep.engineClock = 500;
573 hwmgr->platform_descriptor.clockStep.memoryClock = 500;
575 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
577 hwmgr->pstate_sclk = SMU10_UMD_PSTATE_GFXCLK * 100;
578 hwmgr->pstate_mclk = SMU10_UMD_PSTATE_FCLK * 100;
580 /* enable the pp_od_clk_voltage sysfs file */
581 hwmgr->od_enabled = 1;
582 /* disabled fine grain tuning function by default */
583 data->fine_grain_enabled = 0;
587 static int smu10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
589 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
590 struct smu10_clock_voltage_information *pinfo = &(smu10_data->clock_vol_info);
592 kfree(pinfo->vdd_dep_on_dcefclk);
593 pinfo->vdd_dep_on_dcefclk = NULL;
594 kfree(pinfo->vdd_dep_on_socclk);
595 pinfo->vdd_dep_on_socclk = NULL;
596 kfree(pinfo->vdd_dep_on_fclk);
597 pinfo->vdd_dep_on_fclk = NULL;
598 kfree(pinfo->vdd_dep_on_dispclk);
599 pinfo->vdd_dep_on_dispclk = NULL;
600 kfree(pinfo->vdd_dep_on_dppclk);
601 pinfo->vdd_dep_on_dppclk = NULL;
602 kfree(pinfo->vdd_dep_on_phyclk);
603 pinfo->vdd_dep_on_phyclk = NULL;
605 kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
606 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
608 kfree(hwmgr->backend);
609 hwmgr->backend = NULL;
614 static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
615 enum amd_dpm_forced_level level)
617 struct smu10_hwmgr *data = hwmgr->backend;
618 uint32_t min_sclk = hwmgr->display_config->min_core_set_clock;
619 uint32_t min_mclk = hwmgr->display_config->min_mem_set_clock/100;
620 uint32_t index_fclk = data->clock_vol_info.vdd_dep_on_fclk->count - 1;
621 uint32_t index_socclk = data->clock_vol_info.vdd_dep_on_socclk->count - 1;
622 uint32_t fine_grain_min_freq = 0, fine_grain_max_freq = 0;
624 if (hwmgr->smu_version < 0x1E3700) {
625 pr_info("smu firmware version too old, can not set dpm level\n");
629 if (min_sclk < data->gfx_min_freq_limit)
630 min_sclk = data->gfx_min_freq_limit;
632 min_sclk /= 100; /* transfer 10KHz to MHz */
633 if (min_mclk < data->clock_table.FClocks[0].Freq)
634 min_mclk = data->clock_table.FClocks[0].Freq;
637 case AMD_DPM_FORCED_LEVEL_HIGH:
638 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
639 data->fine_grain_enabled = 0;
641 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &fine_grain_min_freq);
642 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &fine_grain_max_freq);
644 data->gfx_actual_soft_min_freq = fine_grain_min_freq;
645 data->gfx_actual_soft_max_freq = fine_grain_max_freq;
647 smum_send_msg_to_smc_with_parameter(hwmgr,
648 PPSMC_MSG_SetHardMinGfxClk,
649 data->gfx_max_freq_limit/100,
651 smum_send_msg_to_smc_with_parameter(hwmgr,
652 PPSMC_MSG_SetHardMinFclkByFreq,
653 SMU10_UMD_PSTATE_PEAK_FCLK,
655 smum_send_msg_to_smc_with_parameter(hwmgr,
656 PPSMC_MSG_SetHardMinSocclkByFreq,
657 SMU10_UMD_PSTATE_PEAK_SOCCLK,
659 smum_send_msg_to_smc_with_parameter(hwmgr,
660 PPSMC_MSG_SetHardMinVcn,
661 SMU10_UMD_PSTATE_VCE,
664 smum_send_msg_to_smc_with_parameter(hwmgr,
665 PPSMC_MSG_SetSoftMaxGfxClk,
666 data->gfx_max_freq_limit/100,
668 smum_send_msg_to_smc_with_parameter(hwmgr,
669 PPSMC_MSG_SetSoftMaxFclkByFreq,
670 SMU10_UMD_PSTATE_PEAK_FCLK,
672 smum_send_msg_to_smc_with_parameter(hwmgr,
673 PPSMC_MSG_SetSoftMaxSocclkByFreq,
674 SMU10_UMD_PSTATE_PEAK_SOCCLK,
676 smum_send_msg_to_smc_with_parameter(hwmgr,
677 PPSMC_MSG_SetSoftMaxVcn,
678 SMU10_UMD_PSTATE_VCE,
681 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
682 data->fine_grain_enabled = 0;
684 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &fine_grain_min_freq);
685 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &fine_grain_max_freq);
687 data->gfx_actual_soft_min_freq = fine_grain_min_freq;
688 data->gfx_actual_soft_max_freq = fine_grain_max_freq;
690 smum_send_msg_to_smc_with_parameter(hwmgr,
691 PPSMC_MSG_SetHardMinGfxClk,
694 smum_send_msg_to_smc_with_parameter(hwmgr,
695 PPSMC_MSG_SetSoftMaxGfxClk,
699 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
700 data->fine_grain_enabled = 0;
702 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &fine_grain_min_freq);
703 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &fine_grain_max_freq);
705 data->gfx_actual_soft_min_freq = fine_grain_min_freq;
706 data->gfx_actual_soft_max_freq = fine_grain_max_freq;
708 smum_send_msg_to_smc_with_parameter(hwmgr,
709 PPSMC_MSG_SetHardMinFclkByFreq,
712 smum_send_msg_to_smc_with_parameter(hwmgr,
713 PPSMC_MSG_SetSoftMaxFclkByFreq,
717 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
718 data->fine_grain_enabled = 0;
720 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &fine_grain_min_freq);
721 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &fine_grain_max_freq);
723 data->gfx_actual_soft_min_freq = fine_grain_min_freq;
724 data->gfx_actual_soft_max_freq = fine_grain_max_freq;
726 smum_send_msg_to_smc_with_parameter(hwmgr,
727 PPSMC_MSG_SetHardMinGfxClk,
728 SMU10_UMD_PSTATE_GFXCLK,
730 smum_send_msg_to_smc_with_parameter(hwmgr,
731 PPSMC_MSG_SetHardMinFclkByFreq,
732 SMU10_UMD_PSTATE_FCLK,
734 smum_send_msg_to_smc_with_parameter(hwmgr,
735 PPSMC_MSG_SetHardMinSocclkByFreq,
736 SMU10_UMD_PSTATE_SOCCLK,
738 smum_send_msg_to_smc_with_parameter(hwmgr,
739 PPSMC_MSG_SetHardMinVcn,
740 SMU10_UMD_PSTATE_PROFILE_VCE,
743 smum_send_msg_to_smc_with_parameter(hwmgr,
744 PPSMC_MSG_SetSoftMaxGfxClk,
745 SMU10_UMD_PSTATE_GFXCLK,
747 smum_send_msg_to_smc_with_parameter(hwmgr,
748 PPSMC_MSG_SetSoftMaxFclkByFreq,
749 SMU10_UMD_PSTATE_FCLK,
751 smum_send_msg_to_smc_with_parameter(hwmgr,
752 PPSMC_MSG_SetSoftMaxSocclkByFreq,
753 SMU10_UMD_PSTATE_SOCCLK,
755 smum_send_msg_to_smc_with_parameter(hwmgr,
756 PPSMC_MSG_SetSoftMaxVcn,
757 SMU10_UMD_PSTATE_PROFILE_VCE,
760 case AMD_DPM_FORCED_LEVEL_AUTO:
761 data->fine_grain_enabled = 0;
763 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &fine_grain_min_freq);
764 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &fine_grain_max_freq);
766 data->gfx_actual_soft_min_freq = fine_grain_min_freq;
767 data->gfx_actual_soft_max_freq = fine_grain_max_freq;
769 smum_send_msg_to_smc_with_parameter(hwmgr,
770 PPSMC_MSG_SetHardMinGfxClk,
773 smum_send_msg_to_smc_with_parameter(hwmgr,
774 PPSMC_MSG_SetHardMinFclkByFreq,
775 hwmgr->display_config->num_display > 3 ?
776 data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk :
780 smum_send_msg_to_smc_with_parameter(hwmgr,
781 PPSMC_MSG_SetHardMinSocclkByFreq,
782 data->clock_vol_info.vdd_dep_on_socclk->entries[0].clk,
784 smum_send_msg_to_smc_with_parameter(hwmgr,
785 PPSMC_MSG_SetHardMinVcn,
786 SMU10_UMD_PSTATE_MIN_VCE,
789 smum_send_msg_to_smc_with_parameter(hwmgr,
790 PPSMC_MSG_SetSoftMaxGfxClk,
791 data->gfx_max_freq_limit/100,
793 smum_send_msg_to_smc_with_parameter(hwmgr,
794 PPSMC_MSG_SetSoftMaxFclkByFreq,
795 data->clock_vol_info.vdd_dep_on_fclk->entries[index_fclk].clk,
797 smum_send_msg_to_smc_with_parameter(hwmgr,
798 PPSMC_MSG_SetSoftMaxSocclkByFreq,
799 data->clock_vol_info.vdd_dep_on_socclk->entries[index_socclk].clk,
801 smum_send_msg_to_smc_with_parameter(hwmgr,
802 PPSMC_MSG_SetSoftMaxVcn,
803 SMU10_UMD_PSTATE_VCE,
806 case AMD_DPM_FORCED_LEVEL_LOW:
807 data->fine_grain_enabled = 0;
809 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &fine_grain_min_freq);
810 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &fine_grain_max_freq);
812 data->gfx_actual_soft_min_freq = fine_grain_min_freq;
813 data->gfx_actual_soft_max_freq = fine_grain_max_freq;
815 smum_send_msg_to_smc_with_parameter(hwmgr,
816 PPSMC_MSG_SetHardMinGfxClk,
817 data->gfx_min_freq_limit/100,
819 smum_send_msg_to_smc_with_parameter(hwmgr,
820 PPSMC_MSG_SetSoftMaxGfxClk,
821 data->gfx_min_freq_limit/100,
823 smum_send_msg_to_smc_with_parameter(hwmgr,
824 PPSMC_MSG_SetHardMinFclkByFreq,
827 smum_send_msg_to_smc_with_parameter(hwmgr,
828 PPSMC_MSG_SetSoftMaxFclkByFreq,
832 case AMD_DPM_FORCED_LEVEL_MANUAL:
833 data->fine_grain_enabled = 1;
835 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
842 static uint32_t smu10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
844 struct smu10_hwmgr *data;
849 data = (struct smu10_hwmgr *)(hwmgr->backend);
852 return data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk;
854 return data->clock_vol_info.vdd_dep_on_fclk->entries[
855 data->clock_vol_info.vdd_dep_on_fclk->count - 1].clk;
858 static uint32_t smu10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
860 struct smu10_hwmgr *data;
865 data = (struct smu10_hwmgr *)(hwmgr->backend);
868 return data->gfx_min_freq_limit;
870 return data->gfx_max_freq_limit;
873 static int smu10_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
874 struct pp_hw_power_state *hw_ps)
879 static int smu10_dpm_get_pp_table_entry_callback(
880 struct pp_hwmgr *hwmgr,
881 struct pp_hw_power_state *hw_ps,
883 const void *clock_info)
885 struct smu10_power_state *smu10_ps = cast_smu10_ps(hw_ps);
887 smu10_ps->levels[index].engine_clock = 0;
889 smu10_ps->levels[index].vddc_index = 0;
890 smu10_ps->level = index + 1;
892 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
893 smu10_ps->levels[index].ds_divider_index = 5;
894 smu10_ps->levels[index].ss_divider_index = 5;
900 static int smu10_dpm_get_num_of_pp_table_entries(struct pp_hwmgr *hwmgr)
903 unsigned long ret = 0;
905 result = pp_tables_get_num_of_entries(hwmgr, &ret);
907 return result ? 0 : ret;
910 static int smu10_dpm_get_pp_table_entry(struct pp_hwmgr *hwmgr,
911 unsigned long entry, struct pp_power_state *ps)
914 struct smu10_power_state *smu10_ps;
916 ps->hardware.magic = SMU10_Magic;
918 smu10_ps = cast_smu10_ps(&(ps->hardware));
920 result = pp_tables_get_entry(hwmgr, entry, ps,
921 smu10_dpm_get_pp_table_entry_callback);
923 smu10_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK;
924 smu10_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK;
929 static int smu10_get_power_state_size(struct pp_hwmgr *hwmgr)
931 return sizeof(struct smu10_power_state);
934 static int smu10_set_cpu_power_state(struct pp_hwmgr *hwmgr)
940 static int smu10_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time,
941 bool cc6_disable, bool pstate_disable, bool pstate_switch_disable)
943 struct smu10_hwmgr *data = (struct smu10_hwmgr *)(hwmgr->backend);
945 if (separation_time != data->separation_time ||
946 cc6_disable != data->cc6_disable ||
947 pstate_disable != data->pstate_disable) {
948 data->separation_time = separation_time;
949 data->cc6_disable = cc6_disable;
950 data->pstate_disable = pstate_disable;
951 data->cc6_setting_changed = true;
956 static int smu10_get_dal_power_level(struct pp_hwmgr *hwmgr,
957 struct amd_pp_simple_clock_info *info)
962 static int smu10_force_clock_level(struct pp_hwmgr *hwmgr,
963 enum pp_clock_type type, uint32_t mask)
965 struct smu10_hwmgr *data = hwmgr->backend;
966 struct smu10_voltage_dependency_table *mclk_table =
967 data->clock_vol_info.vdd_dep_on_fclk;
970 low = mask ? (ffs(mask) - 1) : 0;
971 high = mask ? (fls(mask) - 1) : 0;
975 if (low > 2 || high > 2) {
976 pr_info("Currently sclk only support 3 levels on RV\n");
980 smum_send_msg_to_smc_with_parameter(hwmgr,
981 PPSMC_MSG_SetHardMinGfxClk,
982 low == 2 ? data->gfx_max_freq_limit/100 :
983 low == 1 ? SMU10_UMD_PSTATE_GFXCLK :
984 data->gfx_min_freq_limit/100,
987 smum_send_msg_to_smc_with_parameter(hwmgr,
988 PPSMC_MSG_SetSoftMaxGfxClk,
989 high == 0 ? data->gfx_min_freq_limit/100 :
990 high == 1 ? SMU10_UMD_PSTATE_GFXCLK :
991 data->gfx_max_freq_limit/100,
996 if (low > mclk_table->count - 1 || high > mclk_table->count - 1)
999 smum_send_msg_to_smc_with_parameter(hwmgr,
1000 PPSMC_MSG_SetHardMinFclkByFreq,
1001 mclk_table->entries[low].clk/100,
1004 smum_send_msg_to_smc_with_parameter(hwmgr,
1005 PPSMC_MSG_SetSoftMaxFclkByFreq,
1006 mclk_table->entries[high].clk/100,
1017 static int smu10_print_clock_levels(struct pp_hwmgr *hwmgr,
1018 enum pp_clock_type type, char *buf)
1020 struct smu10_hwmgr *data = (struct smu10_hwmgr *)(hwmgr->backend);
1021 struct smu10_voltage_dependency_table *mclk_table =
1022 data->clock_vol_info.vdd_dep_on_fclk;
1023 uint32_t i, now, size = 0;
1024 uint32_t min_freq, max_freq = 0;
1029 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetGfxclkFrequency, &now);
1031 /* driver only know min/max gfx_clk, Add level 1 for all other gfx clks */
1032 if (now == data->gfx_max_freq_limit/100)
1034 else if (now == data->gfx_min_freq_limit/100)
1039 size += sprintf(buf + size, "0: %uMhz %s\n",
1040 data->gfx_min_freq_limit/100,
1042 size += sprintf(buf + size, "1: %uMhz %s\n",
1043 i == 1 ? now : SMU10_UMD_PSTATE_GFXCLK,
1045 size += sprintf(buf + size, "2: %uMhz %s\n",
1046 data->gfx_max_freq_limit/100,
1050 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetFclkFrequency, &now);
1052 for (i = 0; i < mclk_table->count; i++)
1053 size += sprintf(buf + size, "%d: %uMhz %s\n",
1055 mclk_table->entries[i].clk / 100,
1056 ((mclk_table->entries[i].clk / 100)
1057 == now) ? "*" : "");
1060 if (hwmgr->od_enabled) {
1061 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &min_freq);
1064 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &max_freq);
1068 size = sprintf(buf, "%s:\n", "OD_SCLK");
1069 size += sprintf(buf + size, "0: %10uMhz\n",
1070 (data->gfx_actual_soft_min_freq > 0) ? data->gfx_actual_soft_min_freq : min_freq);
1071 size += sprintf(buf + size, "1: %10uMhz\n",
1072 (data->gfx_actual_soft_max_freq > 0) ? data->gfx_actual_soft_max_freq : max_freq);
1076 if (hwmgr->od_enabled) {
1077 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &min_freq);
1080 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &max_freq);
1084 size = sprintf(buf, "%s:\n", "OD_RANGE");
1085 size += sprintf(buf + size, "SCLK: %7uMHz %10uMHz\n",
1086 min_freq, max_freq);
1096 static int smu10_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
1097 PHM_PerformanceLevelDesignation designation, uint32_t index,
1098 PHM_PerformanceLevel *level)
1100 struct smu10_hwmgr *data;
1102 if (level == NULL || hwmgr == NULL || state == NULL)
1105 data = (struct smu10_hwmgr *)(hwmgr->backend);
1108 level->memory_clock = data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk;
1109 level->coreClock = data->gfx_min_freq_limit;
1111 level->memory_clock = data->clock_vol_info.vdd_dep_on_fclk->entries[
1112 data->clock_vol_info.vdd_dep_on_fclk->count - 1].clk;
1113 level->coreClock = data->gfx_max_freq_limit;
1116 level->nonLocalMemoryFreq = 0;
1117 level->nonLocalMemoryWidth = 0;
1122 static int smu10_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr,
1123 const struct pp_hw_power_state *state, struct pp_clock_info *clock_info)
1125 const struct smu10_power_state *ps = cast_const_smu10_ps(state);
1127 clock_info->min_eng_clk = ps->levels[0].engine_clock / (1 << (ps->levels[0].ss_divider_index));
1128 clock_info->max_eng_clk = ps->levels[ps->level - 1].engine_clock / (1 << (ps->levels[ps->level - 1].ss_divider_index));
1133 #define MEM_FREQ_LOW_LATENCY 25000
1134 #define MEM_FREQ_HIGH_LATENCY 80000
1135 #define MEM_LATENCY_HIGH 245
1136 #define MEM_LATENCY_LOW 35
1137 #define MEM_LATENCY_ERR 0xFFFF
1140 static uint32_t smu10_get_mem_latency(struct pp_hwmgr *hwmgr,
1143 if (clock >= MEM_FREQ_LOW_LATENCY &&
1144 clock < MEM_FREQ_HIGH_LATENCY)
1145 return MEM_LATENCY_HIGH;
1146 else if (clock >= MEM_FREQ_HIGH_LATENCY)
1147 return MEM_LATENCY_LOW;
1149 return MEM_LATENCY_ERR;
1152 static int smu10_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
1153 enum amd_pp_clock_type type,
1154 struct pp_clock_levels_with_latency *clocks)
1157 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
1158 struct smu10_clock_voltage_information *pinfo = &(smu10_data->clock_vol_info);
1159 struct smu10_voltage_dependency_table *pclk_vol_table;
1160 bool latency_required = false;
1166 case amd_pp_mem_clock:
1167 pclk_vol_table = pinfo->vdd_dep_on_mclk;
1168 latency_required = true;
1170 case amd_pp_f_clock:
1171 pclk_vol_table = pinfo->vdd_dep_on_fclk;
1172 latency_required = true;
1174 case amd_pp_dcf_clock:
1175 pclk_vol_table = pinfo->vdd_dep_on_dcefclk;
1177 case amd_pp_disp_clock:
1178 pclk_vol_table = pinfo->vdd_dep_on_dispclk;
1180 case amd_pp_phy_clock:
1181 pclk_vol_table = pinfo->vdd_dep_on_phyclk;
1183 case amd_pp_dpp_clock:
1184 pclk_vol_table = pinfo->vdd_dep_on_dppclk;
1190 if (pclk_vol_table == NULL || pclk_vol_table->count == 0)
1193 clocks->num_levels = 0;
1194 for (i = 0; i < pclk_vol_table->count; i++) {
1195 if (pclk_vol_table->entries[i].clk) {
1196 clocks->data[clocks->num_levels].clocks_in_khz =
1197 pclk_vol_table->entries[i].clk * 10;
1198 clocks->data[clocks->num_levels].latency_in_us = latency_required ?
1199 smu10_get_mem_latency(hwmgr,
1200 pclk_vol_table->entries[i].clk) :
1202 clocks->num_levels++;
1209 static int smu10_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
1210 enum amd_pp_clock_type type,
1211 struct pp_clock_levels_with_voltage *clocks)
1214 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
1215 struct smu10_clock_voltage_information *pinfo = &(smu10_data->clock_vol_info);
1216 struct smu10_voltage_dependency_table *pclk_vol_table = NULL;
1222 case amd_pp_mem_clock:
1223 pclk_vol_table = pinfo->vdd_dep_on_mclk;
1225 case amd_pp_f_clock:
1226 pclk_vol_table = pinfo->vdd_dep_on_fclk;
1228 case amd_pp_dcf_clock:
1229 pclk_vol_table = pinfo->vdd_dep_on_dcefclk;
1231 case amd_pp_soc_clock:
1232 pclk_vol_table = pinfo->vdd_dep_on_socclk;
1234 case amd_pp_disp_clock:
1235 pclk_vol_table = pinfo->vdd_dep_on_dispclk;
1237 case amd_pp_phy_clock:
1238 pclk_vol_table = pinfo->vdd_dep_on_phyclk;
1244 if (pclk_vol_table == NULL || pclk_vol_table->count == 0)
1247 clocks->num_levels = 0;
1248 for (i = 0; i < pclk_vol_table->count; i++) {
1249 if (pclk_vol_table->entries[i].clk) {
1250 clocks->data[clocks->num_levels].clocks_in_khz = pclk_vol_table->entries[i].clk * 10;
1251 clocks->data[clocks->num_levels].voltage_in_mv = pclk_vol_table->entries[i].vol;
1252 clocks->num_levels++;
1261 static int smu10_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks)
1263 clocks->engine_max_clock = 80000; /* driver can't get engine clock, temp hard code to 800MHz */
1267 static int smu10_thermal_get_temperature(struct pp_hwmgr *hwmgr)
1269 struct amdgpu_device *adev = hwmgr->adev;
1270 uint32_t reg_value = RREG32_SOC15(THM, 0, mmTHM_TCON_CUR_TMP);
1272 (reg_value & THM_TCON_CUR_TMP__CUR_TEMP_MASK) >> THM_TCON_CUR_TMP__CUR_TEMP__SHIFT;
1274 if (cur_temp & THM_TCON_CUR_TMP__CUR_TEMP_RANGE_SEL_MASK)
1275 cur_temp = ((cur_temp / 8) - 49) * PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1277 cur_temp = (cur_temp / 8) * PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1282 static int smu10_read_sensor(struct pp_hwmgr *hwmgr, int idx,
1283 void *value, int *size)
1285 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
1286 struct amdgpu_device *adev = hwmgr->adev;
1287 uint32_t sclk, mclk, activity_percent;
1291 /* GetGfxBusy support was added on RV SMU FW 30.85.00 and PCO 4.30.59 */
1292 if ((adev->apu_flags & AMD_APU_IS_PICASSO) &&
1293 (hwmgr->smu_version >= 0x41e3b))
1294 has_gfx_busy = true;
1295 else if ((adev->apu_flags & AMD_APU_IS_RAVEN) &&
1296 (hwmgr->smu_version >= 0x1e5500))
1297 has_gfx_busy = true;
1299 has_gfx_busy = false;
1302 case AMDGPU_PP_SENSOR_GFX_SCLK:
1303 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetGfxclkFrequency, &sclk);
1304 /* in units of 10KHZ */
1305 *((uint32_t *)value) = sclk * 100;
1308 case AMDGPU_PP_SENSOR_GFX_MCLK:
1309 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetFclkFrequency, &mclk);
1310 /* in units of 10KHZ */
1311 *((uint32_t *)value) = mclk * 100;
1314 case AMDGPU_PP_SENSOR_GPU_TEMP:
1315 *((uint32_t *)value) = smu10_thermal_get_temperature(hwmgr);
1317 case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
1318 *(uint32_t *)value = smu10_data->vcn_power_gated ? 0 : 1;
1321 case AMDGPU_PP_SENSOR_GPU_LOAD:
1325 ret = smum_send_msg_to_smc(hwmgr,
1326 PPSMC_MSG_GetGfxBusy,
1329 *((uint32_t *)value) = min(activity_percent, (u32)100);
1342 static int smu10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
1345 struct smu10_hwmgr *data = hwmgr->backend;
1346 struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges;
1347 Watermarks_t *table = &(data->water_marks_table);
1348 struct amdgpu_device *adev = hwmgr->adev;
1351 smu_set_watermarks_for_clocks_ranges(table,wm_with_clock_ranges);
1353 if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
1354 for (i = 0; i < NUM_WM_RANGES; i++)
1355 table->WatermarkRow[WM_DCFCLK][i].WmType = (uint8_t)0;
1357 for (i = 0; i < NUM_WM_RANGES; i++)
1358 table->WatermarkRow[WM_SOCCLK][i].WmType = (uint8_t)0;
1361 smum_smc_table_manager(hwmgr, (uint8_t *)table, (uint16_t)SMU10_WMTABLE, false);
1362 data->water_marks_exist = true;
1366 static int smu10_smus_notify_pwe(struct pp_hwmgr *hwmgr)
1369 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SetRccPfcPmeRestoreRegister, NULL);
1372 static int smu10_powergate_mmhub(struct pp_hwmgr *hwmgr)
1374 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerGateMmHub, NULL);
1377 static int smu10_powergate_sdma(struct pp_hwmgr *hwmgr, bool gate)
1380 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerDownSdma, NULL);
1382 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerUpSdma, NULL);
1385 static void smu10_powergate_vcn(struct pp_hwmgr *hwmgr, bool bgate)
1387 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
1390 amdgpu_device_ip_set_powergating_state(hwmgr->adev,
1391 AMD_IP_BLOCK_TYPE_VCN,
1393 smum_send_msg_to_smc_with_parameter(hwmgr,
1394 PPSMC_MSG_PowerDownVcn, 0, NULL);
1395 smu10_data->vcn_power_gated = true;
1397 smum_send_msg_to_smc_with_parameter(hwmgr,
1398 PPSMC_MSG_PowerUpVcn, 0, NULL);
1399 amdgpu_device_ip_set_powergating_state(hwmgr->adev,
1400 AMD_IP_BLOCK_TYPE_VCN,
1401 AMD_PG_STATE_UNGATE);
1402 smu10_data->vcn_power_gated = false;
1406 static int conv_power_profile_to_pplib_workload(int power_profile)
1408 int pplib_workload = 0;
1410 switch (power_profile) {
1411 case PP_SMC_POWER_PROFILE_FULLSCREEN3D:
1412 pplib_workload = WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT;
1414 case PP_SMC_POWER_PROFILE_VIDEO:
1415 pplib_workload = WORKLOAD_PPLIB_VIDEO_BIT;
1417 case PP_SMC_POWER_PROFILE_VR:
1418 pplib_workload = WORKLOAD_PPLIB_VR_BIT;
1420 case PP_SMC_POWER_PROFILE_COMPUTE:
1421 pplib_workload = WORKLOAD_PPLIB_COMPUTE_BIT;
1423 case PP_SMC_POWER_PROFILE_CUSTOM:
1424 pplib_workload = WORKLOAD_PPLIB_CUSTOM_BIT;
1428 return pplib_workload;
1431 static int smu10_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
1433 uint32_t i, size = 0;
1434 static const uint8_t
1435 profile_mode_setting[6][4] = {{70, 60, 0, 0,},
1442 static const char *profile_name[6] = {
1449 static const char *title[6] = {"NUM",
1454 "MIN_ACTIVE_LEVEL"};
1459 size += sprintf(buf + size, "%s %16s %s %s %s %s\n",title[0],
1460 title[1], title[2], title[3], title[4], title[5]);
1462 for (i = 0; i <= PP_SMC_POWER_PROFILE_COMPUTE; i++)
1463 size += sprintf(buf + size, "%3d %14s%s: %14d %3d %10d %14d\n",
1464 i, profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ",
1465 profile_mode_setting[i][0], profile_mode_setting[i][1],
1466 profile_mode_setting[i][2], profile_mode_setting[i][3]);
1471 static bool smu10_is_raven1_refresh(struct pp_hwmgr *hwmgr)
1473 struct amdgpu_device *adev = hwmgr->adev;
1474 if ((adev->apu_flags & AMD_APU_IS_RAVEN) &&
1475 (hwmgr->smu_version >= 0x41e2b))
1481 static int smu10_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)
1483 int workload_type = 0;
1486 if (input[size] > PP_SMC_POWER_PROFILE_COMPUTE) {
1487 pr_err("Invalid power profile mode %ld\n", input[size]);
1490 if (hwmgr->power_profile_mode == input[size])
1493 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1495 conv_power_profile_to_pplib_workload(input[size]);
1496 if (workload_type &&
1497 smu10_is_raven1_refresh(hwmgr) &&
1498 !hwmgr->gfxoff_state_changed_by_workload) {
1499 smu10_gfx_off_control(hwmgr, false);
1500 hwmgr->gfxoff_state_changed_by_workload = true;
1502 result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ActiveProcessNotify,
1506 hwmgr->power_profile_mode = input[size];
1507 if (workload_type && hwmgr->gfxoff_state_changed_by_workload) {
1508 smu10_gfx_off_control(hwmgr, true);
1509 hwmgr->gfxoff_state_changed_by_workload = false;
1515 static int smu10_asic_reset(struct pp_hwmgr *hwmgr, enum SMU_ASIC_RESET_MODE mode)
1517 return smum_send_msg_to_smc_with_parameter(hwmgr,
1518 PPSMC_MSG_DeviceDriverReset,
1523 static int smu10_set_fine_grain_clk_vol(struct pp_hwmgr *hwmgr,
1524 enum PP_OD_DPM_TABLE_COMMAND type,
1525 long *input, uint32_t size)
1527 uint32_t min_freq, max_freq = 0;
1528 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
1531 if (!hwmgr->od_enabled) {
1532 pr_err("Fine grain not support\n");
1536 if (!smu10_data->fine_grain_enabled) {
1537 pr_err("pp_od_clk_voltage is not accessible if power_dpm_force_performance_level is not in manual mode!\n");
1541 if (type == PP_OD_EDIT_SCLK_VDDC_TABLE) {
1543 pr_err("Input parameter number not correct\n");
1547 if (input[0] == 0) {
1548 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &min_freq);
1549 if (input[1] < min_freq) {
1550 pr_err("Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
1551 input[1], min_freq);
1554 smu10_data->gfx_actual_soft_min_freq = input[1];
1555 } else if (input[0] == 1) {
1556 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &max_freq);
1557 if (input[1] > max_freq) {
1558 pr_err("Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
1559 input[1], max_freq);
1562 smu10_data->gfx_actual_soft_max_freq = input[1];
1566 } else if (type == PP_OD_RESTORE_DEFAULT_TABLE) {
1568 pr_err("Input parameter number not correct\n");
1571 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &min_freq);
1572 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &max_freq);
1574 smu10_data->gfx_actual_soft_min_freq = min_freq;
1575 smu10_data->gfx_actual_soft_max_freq = max_freq;
1576 } else if (type == PP_OD_COMMIT_DPM_TABLE) {
1578 pr_err("Input parameter number not correct\n");
1582 if (smu10_data->gfx_actual_soft_min_freq > smu10_data->gfx_actual_soft_max_freq) {
1583 pr_err("The setting minimun sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
1584 smu10_data->gfx_actual_soft_min_freq, smu10_data->gfx_actual_soft_max_freq);
1588 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1589 PPSMC_MSG_SetHardMinGfxClk,
1590 smu10_data->gfx_actual_soft_min_freq,
1595 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1596 PPSMC_MSG_SetSoftMaxGfxClk,
1597 smu10_data->gfx_actual_soft_max_freq,
1608 static int smu10_gfx_state_change(struct pp_hwmgr *hwmgr, uint32_t state)
1610 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GpuChangeState, state, NULL);
1615 static const struct pp_hwmgr_func smu10_hwmgr_funcs = {
1616 .backend_init = smu10_hwmgr_backend_init,
1617 .backend_fini = smu10_hwmgr_backend_fini,
1618 .apply_state_adjust_rules = smu10_apply_state_adjust_rules,
1619 .force_dpm_level = smu10_dpm_force_dpm_level,
1620 .get_power_state_size = smu10_get_power_state_size,
1621 .powerdown_uvd = NULL,
1622 .powergate_uvd = smu10_powergate_vcn,
1623 .powergate_vce = NULL,
1624 .get_mclk = smu10_dpm_get_mclk,
1625 .get_sclk = smu10_dpm_get_sclk,
1626 .patch_boot_state = smu10_dpm_patch_boot_state,
1627 .get_pp_table_entry = smu10_dpm_get_pp_table_entry,
1628 .get_num_of_pp_table_entries = smu10_dpm_get_num_of_pp_table_entries,
1629 .set_cpu_power_state = smu10_set_cpu_power_state,
1630 .store_cc6_data = smu10_store_cc6_data,
1631 .force_clock_level = smu10_force_clock_level,
1632 .print_clock_levels = smu10_print_clock_levels,
1633 .get_dal_power_level = smu10_get_dal_power_level,
1634 .get_performance_level = smu10_get_performance_level,
1635 .get_current_shallow_sleep_clocks = smu10_get_current_shallow_sleep_clocks,
1636 .get_clock_by_type_with_latency = smu10_get_clock_by_type_with_latency,
1637 .get_clock_by_type_with_voltage = smu10_get_clock_by_type_with_voltage,
1638 .set_watermarks_for_clocks_ranges = smu10_set_watermarks_for_clocks_ranges,
1639 .get_max_high_clocks = smu10_get_max_high_clocks,
1640 .read_sensor = smu10_read_sensor,
1641 .set_active_display_count = smu10_set_active_display_count,
1642 .set_min_deep_sleep_dcefclk = smu10_set_min_deep_sleep_dcefclk,
1643 .dynamic_state_management_enable = smu10_enable_dpm_tasks,
1644 .power_off_asic = smu10_power_off_asic,
1645 .asic_setup = smu10_setup_asic_task,
1646 .power_state_set = smu10_set_power_state_tasks,
1647 .dynamic_state_management_disable = smu10_disable_dpm_tasks,
1648 .powergate_mmhub = smu10_powergate_mmhub,
1649 .smus_notify_pwe = smu10_smus_notify_pwe,
1650 .display_clock_voltage_request = smu10_display_clock_voltage_request,
1651 .powergate_gfx = smu10_gfx_off_control,
1652 .powergate_sdma = smu10_powergate_sdma,
1653 .set_hard_min_dcefclk_by_freq = smu10_set_hard_min_dcefclk_by_freq,
1654 .set_hard_min_fclk_by_freq = smu10_set_hard_min_fclk_by_freq,
1655 .set_hard_min_gfxclk_by_freq = smu10_set_hard_min_gfxclk_by_freq,
1656 .set_soft_max_gfxclk_by_freq = smu10_set_soft_max_gfxclk_by_freq,
1657 .get_power_profile_mode = smu10_get_power_profile_mode,
1658 .set_power_profile_mode = smu10_set_power_profile_mode,
1659 .asic_reset = smu10_asic_reset,
1660 .set_fine_grain_clk_vol = smu10_set_fine_grain_clk_vol,
1661 .gfx_state_change = smu10_gfx_state_change,
1664 int smu10_init_function_pointers(struct pp_hwmgr *hwmgr)
1666 hwmgr->hwmgr_func = &smu10_hwmgr_funcs;
1667 hwmgr->pptable_func = &pptable_funcs;