drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #ifndef PP_ATOMVOLTAGECTRL_H
  25 #define PP_ATOMVOLTAGECTRL_H
  26
  27 #include "hwmgr.h"
  28
  29 /* As returned from PowerConnectorDetectionTable. */
  30 #define PP_ATOM_POWER_BUDGET_DISABLE_OVERDRIVE  0x80
  31 #define PP_ATOM_POWER_BUDGET_SHOW_WARNING       0x40
  32 #define PP_ATOM_POWER_BUDGET_SHOW_WAIVER        0x20
  33 #define PP_ATOM_POWER_POWER_BUDGET_BEHAVIOUR    0x0F
  34
  35 /* New functions for Evergreen and beyond. */
  36 #define PP_ATOMCTRL_MAX_VOLTAGE_ENTRIES 32
  37
  38 struct pp_atomctrl_clock_dividers {
  39         uint32_t pll_post_divider;
  40         uint32_t pll_feedback_divider;
  41         uint32_t pll_ref_divider;
  42         bool  enable_post_divider;
  43 };
  44
  45 typedef struct pp_atomctrl_clock_dividers pp_atomctrl_clock_dividers;
  46
  47 union pp_atomctrl_tcipll_fb_divider {
  48         struct {
  49                 uint32_t ul_fb_div_frac : 14;
  50                 uint32_t ul_fb_div : 12;
  51                 uint32_t un_used : 6;
  52         };
  53         uint32_t ul_fb_divider;
  54 };
  55
  56 typedef union pp_atomctrl_tcipll_fb_divider pp_atomctrl_tcipll_fb_divider;
  57
  58 struct pp_atomctrl_clock_dividers_rv730 {
  59         uint32_t pll_post_divider;
  60         pp_atomctrl_tcipll_fb_divider mpll_feedback_divider;
  61         uint32_t pll_ref_divider;
  62         bool  enable_post_divider;
  63         bool  enable_dithen;
  64         uint32_t vco_mode;
  65 };
  66 typedef struct pp_atomctrl_clock_dividers_rv730 pp_atomctrl_clock_dividers_rv730;
  67
  68
  69 struct pp_atomctrl_clock_dividers_kong {
  70         uint32_t    pll_post_divider;
  71         uint32_t    real_clock;
  72 };
  73 typedef struct pp_atomctrl_clock_dividers_kong pp_atomctrl_clock_dividers_kong;
  74
  75 struct pp_atomctrl_clock_dividers_ci {
  76         uint32_t    pll_post_divider;               /* post divider value */
  77         uint32_t    real_clock;
  78         pp_atomctrl_tcipll_fb_divider   ul_fb_div;         /* Output Parameter: PLL FB divider */
  79         uint8_t   uc_pll_ref_div;                      /* Output Parameter: PLL ref divider */
  80         uint8_t   uc_pll_post_div;                      /* Output Parameter: PLL post divider */
  81         uint8_t   uc_pll_cntl_flag;                    /*Output Flags: control flag */
  82 };
  83 typedef struct pp_atomctrl_clock_dividers_ci pp_atomctrl_clock_dividers_ci;
  84
  85 struct pp_atomctrl_clock_dividers_vi {
  86         uint32_t    pll_post_divider;               /* post divider value */
  87         uint32_t    real_clock;
  88         pp_atomctrl_tcipll_fb_divider   ul_fb_div;         /*Output Parameter: PLL FB divider */
  89         uint8_t   uc_pll_ref_div;                      /*Output Parameter: PLL ref divider */
  90         uint8_t   uc_pll_post_div;                     /*Output Parameter: PLL post divider */
  91         uint8_t   uc_pll_cntl_flag;                    /*Output Flags: control flag */
  92 };
  93 typedef struct pp_atomctrl_clock_dividers_vi pp_atomctrl_clock_dividers_vi;
  94
  95 struct pp_atomctrl_clock_dividers_ai {
  96         u16 usSclk_fcw_frac;
  97         u16  usSclk_fcw_int;
  98         u8   ucSclkPostDiv;
  99         u8   ucSclkVcoMode;
 100         u8   ucSclkPllRange;
 101         u8   ucSscEnable;
 102         u16  usSsc_fcw1_frac;
 103         u16  usSsc_fcw1_int;
 104         u16  usReserved;
 105         u16  usPcc_fcw_int;
 106         u16  usSsc_fcw_slew_frac;
 107         u16  usPcc_fcw_slew_frac;
 108 };
 109 typedef struct pp_atomctrl_clock_dividers_ai pp_atomctrl_clock_dividers_ai;
 110
 111
 112 union pp_atomctrl_s_mpll_fb_divider {
 113         struct {
 114                 uint32_t cl_kf : 12;
 115                 uint32_t clk_frac : 12;
 116                 uint32_t un_used : 8;
 117         };
 118         uint32_t ul_fb_divider;
 119 };
 120 typedef union pp_atomctrl_s_mpll_fb_divider pp_atomctrl_s_mpll_fb_divider;
 121
 122 enum pp_atomctrl_spread_spectrum_mode {
 123         pp_atomctrl_spread_spectrum_mode_down = 0,
 124         pp_atomctrl_spread_spectrum_mode_center
 125 };
 126 typedef enum pp_atomctrl_spread_spectrum_mode pp_atomctrl_spread_spectrum_mode;
 127
 128 struct pp_atomctrl_memory_clock_param {
 129         pp_atomctrl_s_mpll_fb_divider mpll_fb_divider;
 130         uint32_t mpll_post_divider;
 131         uint32_t bw_ctrl;
 132         uint32_t dll_speed;
 133         uint32_t vco_mode;
 134         uint32_t yclk_sel;
 135         uint32_t qdr;
 136         uint32_t half_rate;
 137 };
 138 typedef struct pp_atomctrl_memory_clock_param pp_atomctrl_memory_clock_param;
 139
 140 struct pp_atomctrl_memory_clock_param_ai {
 141         uint32_t ulClock;
 142         uint32_t ulPostDiv;
 143         uint16_t ulMclk_fcw_frac;
 144         uint16_t ulMclk_fcw_int;
 145 };
 146 typedef struct pp_atomctrl_memory_clock_param_ai pp_atomctrl_memory_clock_param_ai;
 147
 148 struct pp_atomctrl_internal_ss_info {
 149         uint32_t speed_spectrum_percentage;                      /* in 1/100 percentage */
 150         uint32_t speed_spectrum_rate;                            /* in KHz */
 151         pp_atomctrl_spread_spectrum_mode speed_spectrum_mode;
 152 };
 153 typedef struct pp_atomctrl_internal_ss_info pp_atomctrl_internal_ss_info;
 154
 155 #ifndef NUMBER_OF_M3ARB_PARAMS
 156 #define NUMBER_OF_M3ARB_PARAMS 3
 157 #endif
 158
 159 #ifndef NUMBER_OF_M3ARB_PARAM_SETS
 160 #define NUMBER_OF_M3ARB_PARAM_SETS 10
 161 #endif
 162
 163 struct pp_atomctrl_kong_system_info {
 164         uint32_t                        ul_bootup_uma_clock;          /* in 10kHz unit */
 165         uint16_t                        us_max_nb_voltage;            /* high NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; */
 166         uint16_t                        us_min_nb_voltage;            /* low NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; */
 167         uint16_t                        us_bootup_nb_voltage;         /* boot up NB voltage */
 168         uint8_t                 uc_htc_tmp_lmt;               /* bit [22:16] of D24F3x64 Hardware Thermal Control (HTC) Register, may not be needed, TBD */
 169         uint8_t                 uc_tj_offset;                /* bit [28:22] of D24F3xE4 Thermtrip Status Register,may not be needed, TBD */
 170         /* 0: default 1: uvd 2: fs-3d */
 171         uint32_t          ul_csr_m3_srb_cntl[NUMBER_OF_M3ARB_PARAM_SETS][NUMBER_OF_M3ARB_PARAMS];/* arrays with values for CSR M3 arbiter for default */
 172 };
 173 typedef struct pp_atomctrl_kong_system_info pp_atomctrl_kong_system_info;
 174
 175 struct pp_atomctrl_memory_info {
 176         uint8_t memory_vendor;
 177         uint8_t memory_type;
 178 };
 179 typedef struct pp_atomctrl_memory_info pp_atomctrl_memory_info;
 180
 181 #define MAX_AC_TIMING_ENTRIES 16
 182
 183 struct pp_atomctrl_memory_clock_range_table {
 184         uint8_t   num_entries;
 185         uint8_t   rsv[3];
 186
 187         uint32_t mclk[MAX_AC_TIMING_ENTRIES];
 188 };
 189 typedef struct pp_atomctrl_memory_clock_range_table pp_atomctrl_memory_clock_range_table;
 190
 191 struct pp_atomctrl_voltage_table_entry {
 192         uint16_t value;
 193         uint32_t smio_low;
 194 };
 195
 196 typedef struct pp_atomctrl_voltage_table_entry pp_atomctrl_voltage_table_entry;
 197
 198 struct pp_atomctrl_voltage_table {
 199         uint32_t count;
 200         uint32_t mask_low;
 201         uint32_t phase_delay;   /* Used for ATOM_GPIO_VOLTAGE_OBJECT_V3 and later */
 202         pp_atomctrl_voltage_table_entry entries[PP_ATOMCTRL_MAX_VOLTAGE_ENTRIES];
 203 };
 204
 205 typedef struct pp_atomctrl_voltage_table pp_atomctrl_voltage_table;
 206
 207 #define VBIOS_MC_REGISTER_ARRAY_SIZE           32
 208 #define VBIOS_MAX_AC_TIMING_ENTRIES            20
 209
 210 struct pp_atomctrl_mc_reg_entry {
 211         uint32_t           mclk_max;
 212         uint32_t mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE];
 213 };
 214 typedef struct pp_atomctrl_mc_reg_entry pp_atomctrl_mc_reg_entry;
 215
 216 struct pp_atomctrl_mc_register_address {
 217         uint16_t s1;
 218         uint8_t  uc_pre_reg_data;
 219 };
 220
 221 typedef struct pp_atomctrl_mc_register_address pp_atomctrl_mc_register_address;
 222
 223 #define MAX_SCLK_RANGE 8
 224
 225 struct pp_atom_ctrl_sclk_range_table_entry{
 226         uint8_t  ucVco_setting;
 227         uint8_t  ucPostdiv;
 228         uint16_t usFcw_pcc;
 229         uint16_t usFcw_trans_upper;
 230         uint16_t usRcw_trans_lower;
 231 };
 232
 233
 234 struct pp_atom_ctrl_sclk_range_table{
 235         struct pp_atom_ctrl_sclk_range_table_entry entry[MAX_SCLK_RANGE];
 236 };
 237
 238 struct pp_atomctrl_mc_reg_table {
 239         uint8_t                         last;                    /* number of registers */
 240         uint8_t                         num_entries;             /* number of AC timing entries */
 241         pp_atomctrl_mc_reg_entry        mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES];
 242         pp_atomctrl_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE];
 243 };
 244 typedef struct pp_atomctrl_mc_reg_table pp_atomctrl_mc_reg_table;
 245
 246 struct pp_atomctrl_gpio_pin_assignment {
 247         uint16_t                   us_gpio_pin_aindex;
 248         uint8_t                    uc_gpio_pin_bit_shift;
 249 };
 250 typedef struct pp_atomctrl_gpio_pin_assignment pp_atomctrl_gpio_pin_assignment;
 251
 252 struct pp_atom_ctrl__avfs_parameters {
 253         uint32_t  ulAVFS_meanNsigma_Acontant0;
 254         uint32_t  ulAVFS_meanNsigma_Acontant1;
 255         uint32_t  ulAVFS_meanNsigma_Acontant2;
 256         uint16_t usAVFS_meanNsigma_DC_tol_sigma;
 257         uint16_t usAVFS_meanNsigma_Platform_mean;
 258         uint16_t usAVFS_meanNsigma_Platform_sigma;
 259         uint32_t  ulGB_VDROOP_TABLE_CKSOFF_a0;
 260         uint32_t  ulGB_VDROOP_TABLE_CKSOFF_a1;
 261         uint32_t  ulGB_VDROOP_TABLE_CKSOFF_a2;
 262         uint32_t  ulGB_VDROOP_TABLE_CKSON_a0;
 263         uint32_t  ulGB_VDROOP_TABLE_CKSON_a1;
 264         uint32_t  ulGB_VDROOP_TABLE_CKSON_a2;
 265         uint32_t  ulAVFSGB_FUSE_TABLE_CKSOFF_m1;
 266         uint16_t  usAVFSGB_FUSE_TABLE_CKSOFF_m2;
 267         uint32_t  ulAVFSGB_FUSE_TABLE_CKSOFF_b;
 268         uint32_t  ulAVFSGB_FUSE_TABLE_CKSON_m1;
 269         uint16_t  usAVFSGB_FUSE_TABLE_CKSON_m2;
 270         uint32_t  ulAVFSGB_FUSE_TABLE_CKSON_b;
 271         uint16_t  usMaxVoltage_0_25mv;
 272         uint8_t  ucEnableGB_VDROOP_TABLE_CKSOFF;
 273         uint8_t  ucEnableGB_VDROOP_TABLE_CKSON;
 274         uint8_t  ucEnableGB_FUSE_TABLE_CKSOFF;
 275         uint8_t  ucEnableGB_FUSE_TABLE_CKSON;
 276         uint16_t usPSM_Age_ComFactor;
 277         uint8_t  ucEnableApplyAVFS_CKS_OFF_Voltage;
 278         uint8_t  ucReserved;
 279 };
 280
 281 struct _AtomCtrl_HiLoLeakageOffsetTable
 282 {
 283     USHORT usHiLoLeakageThreshold;
 284     USHORT usEdcDidtLoDpm7TableOffset;
 285     USHORT usEdcDidtHiDpm7TableOffset;
 286 };
 287 typedef struct _AtomCtrl_HiLoLeakageOffsetTable AtomCtrl_HiLoLeakageOffsetTable;
 288
 289 struct _AtomCtrl_EDCLeakgeTable
 290 {
 291     ULONG DIDT_REG[24];
 292 };
 293 typedef struct _AtomCtrl_EDCLeakgeTable AtomCtrl_EDCLeakgeTable;
 294
 295 extern bool atomctrl_get_pp_assign_pin(struct pp_hwmgr *hwmgr, const uint32_t pinId, pp_atomctrl_gpio_pin_assignment *gpio_pin_assignment);
 296 extern int atomctrl_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage);
 297 extern int atomctrl_get_voltage_evv(struct pp_hwmgr *hwmgr, uint16_t virtual_voltage_id, uint16_t *voltage);
 298 extern uint32_t atomctrl_get_mpll_reference_clock(struct pp_hwmgr *hwmgr);
 299
 300 bool atomctrl_is_asic_internal_ss_supported(struct pp_hwmgr *hwmgr);
 301 extern int atomctrl_get_memory_clock_spread_spectrum(struct pp_hwmgr *hwmgr, const uint32_t memory_clock, pp_atomctrl_internal_ss_info *ssInfo);
 302 extern int atomctrl_get_engine_clock_spread_spectrum(struct pp_hwmgr *hwmgr, const uint32_t engine_clock, pp_atomctrl_internal_ss_info *ssInfo);
 303 extern int atomctrl_initialize_mc_reg_table(struct pp_hwmgr *hwmgr, uint8_t module_index, pp_atomctrl_mc_reg_table *table);
 304 extern int atomctrl_initialize_mc_reg_table_v2_2(struct pp_hwmgr *hwmgr, uint8_t module_index, pp_atomctrl_mc_reg_table *table);
 305 extern int atomctrl_set_engine_dram_timings_rv770(struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint32_t memory_clock);
 306 extern uint32_t atomctrl_get_reference_clock(struct pp_hwmgr *hwmgr);
 307 extern int atomctrl_get_memory_pll_dividers_si(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param, bool strobe_mode);
 308 extern int atomctrl_get_engine_pll_dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers);
 309 extern int atomctrl_get_dfs_pll_dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers);
 310 extern bool atomctrl_is_voltage_controlled_by_gpio_v3(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint8_t voltage_mode);
 311 extern int atomctrl_get_voltage_table_v3(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint8_t voltage_mode, pp_atomctrl_voltage_table *voltage_table);
 312 extern int atomctrl_get_memory_pll_dividers_vi(struct pp_hwmgr *hwmgr,
 313                 uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param);
 314 extern int atomctrl_get_memory_pll_dividers_ai(struct pp_hwmgr *hwmgr,
 315                 uint32_t clock_value, pp_atomctrl_memory_clock_param_ai *mpll_param);
 316 extern int atomctrl_get_engine_pll_dividers_kong(struct pp_hwmgr *hwmgr,
 317                                                  uint32_t clock_value,
 318                                                  pp_atomctrl_clock_dividers_kong *dividers);
 319 extern int atomctrl_read_efuse(struct pp_hwmgr *hwmgr, uint16_t start_index,
 320                 uint16_t end_index, uint32_t *efuse);
 321 extern int atomctrl_calculate_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
 322                 uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage, uint16_t dpm_level, bool debug);
 323 extern int atomctrl_get_engine_pll_dividers_ai(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_ai *dividers);
 324 extern int atomctrl_set_ac_timing_ai(struct pp_hwmgr *hwmgr, uint32_t memory_clock,
 325                                                                 uint8_t level);
 326 extern int atomctrl_get_voltage_evv_on_sclk_ai(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
 327                                 uint32_t sclk, uint16_t virtual_voltage_Id, uint32_t *voltage);
 328 extern int atomctrl_get_smc_sclk_range_table(struct pp_hwmgr *hwmgr, struct pp_atom_ctrl_sclk_range_table *table);
 329
 330 extern int atomctrl_get_avfs_information(struct pp_hwmgr *hwmgr, struct pp_atom_ctrl__avfs_parameters *param);
 331
 332 extern int  atomctrl_get_svi2_info(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
 333                                 uint8_t *svd_gpio_id, uint8_t *svc_gpio_id,
 334                                 uint16_t *load_line);
 335
 336 extern int atomctrl_get_leakage_vddc_base_on_leakage(struct pp_hwmgr *hwmgr,
 337                                         uint16_t *vddc, uint16_t *vddci,
 338                                         uint16_t virtual_voltage_id,
 339                                         uint16_t efuse_voltage_id);
 340 extern int atomctrl_get_leakage_id_from_efuse(struct pp_hwmgr *hwmgr, uint16_t *virtual_voltage_id);
 341
 342 extern void atomctrl_get_voltage_range(struct pp_hwmgr *hwmgr, uint32_t *max_vddc,
 343                                                         uint32_t *min_vddc);
 344
 345 extern int atomctrl_get_edc_hilo_leakage_offset_table(struct pp_hwmgr *hwmgr,
 346                                                       AtomCtrl_HiLoLeakageOffsetTable *table);
 347
 348 extern int atomctrl_get_edc_leakage_table(struct pp_hwmgr *hwmgr,
 349                                           AtomCtrl_EDCLeakgeTable *table,
 350                                           uint16_t offset);
 351
 352 extern int atomctrl_get_vddc_shared_railinfo(struct pp_hwmgr *hwmgr, uint8_t *shared_rail);
 353 #endif
 354