2 * Copyright 2020 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #ifndef __SMU_V13_0_H__
24 #define __SMU_V13_0_H__
26 #include "amdgpu_smu.h"
28 #define SMU13_DRIVER_IF_VERSION_INV 0xFFFFFFFF
29 #define SMU13_DRIVER_IF_VERSION_ALDE 0x07
32 #define MP0_Public 0x03800000
33 #define MP0_SRAM 0x03900000
34 #define MP1_Public 0x03b00000
35 #define MP1_SRAM 0x03c00004
38 #define smnMP1_FIRMWARE_FLAGS 0x3010024
39 #define smnMP0_FW_INTF 0x30101c0
40 #define smnMP1_PUB_CTRL 0x3010b14
42 #define TEMP_RANGE_MIN (0)
43 #define TEMP_RANGE_MAX (80 * 1000)
45 #define SMU13_TOOL_SIZE 0x19000
47 #define MAX_DPM_LEVELS 16
48 #define MAX_PCIE_CONF 2
50 #define CTF_OFFSET_EDGE 5
51 #define CTF_OFFSET_HOTSPOT 5
52 #define CTF_OFFSET_MEM 5
54 struct smu_13_0_max_sustainable_clocks {
55 uint32_t display_clock;
63 struct smu_13_0_dpm_clk_level {
68 struct smu_13_0_dpm_table {
69 uint32_t min; /* MHz */
70 uint32_t max; /* MHz */
72 struct smu_13_0_dpm_clk_level dpm_levels[MAX_DPM_LEVELS];
75 struct smu_13_0_pcie_table {
76 uint8_t pcie_gen[MAX_PCIE_CONF];
77 uint8_t pcie_lane[MAX_PCIE_CONF];
80 struct smu_13_0_dpm_tables {
81 struct smu_13_0_dpm_table soc_table;
82 struct smu_13_0_dpm_table gfx_table;
83 struct smu_13_0_dpm_table uclk_table;
84 struct smu_13_0_dpm_table eclk_table;
85 struct smu_13_0_dpm_table vclk_table;
86 struct smu_13_0_dpm_table dclk_table;
87 struct smu_13_0_dpm_table dcef_table;
88 struct smu_13_0_dpm_table pixel_table;
89 struct smu_13_0_dpm_table display_table;
90 struct smu_13_0_dpm_table phy_table;
91 struct smu_13_0_dpm_table fclk_table;
92 struct smu_13_0_pcie_table pcie_table;
95 struct smu_13_0_dpm_context {
96 struct smu_13_0_dpm_tables dpm_tables;
97 uint32_t workload_policy_mask;
98 uint32_t dcef_min_ds_clk;
101 enum smu_13_0_power_state {
102 SMU_13_0_POWER_STATE__D0 = 0,
103 SMU_13_0_POWER_STATE__D1,
104 SMU_13_0_POWER_STATE__D3, /* Sleep*/
105 SMU_13_0_POWER_STATE__D4, /* Hibernate*/
106 SMU_13_0_POWER_STATE__D5, /* Power off*/
109 struct smu_13_0_power_context {
110 uint32_t power_source;
111 uint8_t in_power_limit_boost_mode;
112 enum smu_13_0_power_state power_state;
115 enum smu_v13_0_baco_seq {
123 #if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3)
125 int smu_v13_0_init_microcode(struct smu_context *smu);
127 void smu_v13_0_fini_microcode(struct smu_context *smu);
129 int smu_v13_0_load_microcode(struct smu_context *smu);
131 int smu_v13_0_init_smc_tables(struct smu_context *smu);
133 int smu_v13_0_fini_smc_tables(struct smu_context *smu);
135 int smu_v13_0_init_power(struct smu_context *smu);
137 int smu_v13_0_fini_power(struct smu_context *smu);
139 int smu_v13_0_check_fw_status(struct smu_context *smu);
141 int smu_v13_0_setup_pptable(struct smu_context *smu);
143 int smu_v13_0_get_vbios_bootup_values(struct smu_context *smu);
145 int smu_v13_0_check_fw_version(struct smu_context *smu);
147 int smu_v13_0_set_driver_table_location(struct smu_context *smu);
149 int smu_v13_0_set_tool_table_location(struct smu_context *smu);
151 int smu_v13_0_notify_memory_pool_location(struct smu_context *smu);
153 int smu_v13_0_system_features_control(struct smu_context *smu,
156 int smu_v13_0_init_display_count(struct smu_context *smu, uint32_t count);
158 int smu_v13_0_set_allowed_mask(struct smu_context *smu);
160 int smu_v13_0_notify_display_change(struct smu_context *smu);
162 int smu_v13_0_get_current_power_limit(struct smu_context *smu,
163 uint32_t *power_limit);
165 int smu_v13_0_set_power_limit(struct smu_context *smu, uint32_t n);
167 int smu_v13_0_init_max_sustainable_clocks(struct smu_context *smu);
169 int smu_v13_0_enable_thermal_alert(struct smu_context *smu);
171 int smu_v13_0_disable_thermal_alert(struct smu_context *smu);
173 int smu_v13_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value);
175 int smu_v13_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk);
178 smu_v13_0_display_clock_voltage_request(struct smu_context *smu,
179 struct pp_display_clock_request
183 smu_v13_0_get_fan_control_mode(struct smu_context *smu);
186 smu_v13_0_set_fan_control_mode(struct smu_context *smu,
190 smu_v13_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed);
192 int smu_v13_0_set_fan_speed_rpm(struct smu_context *smu,
195 int smu_v13_0_set_xgmi_pstate(struct smu_context *smu,
198 int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable);
200 int smu_v13_0_register_irq_handler(struct smu_context *smu);
202 int smu_v13_0_set_azalia_d3_pme(struct smu_context *smu);
204 int smu_v13_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
205 struct pp_smu_nv_clock_table *max_clocks);
207 bool smu_v13_0_baco_is_support(struct smu_context *smu);
209 enum smu_baco_state smu_v13_0_baco_get_state(struct smu_context *smu);
211 int smu_v13_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state);
213 int smu_v13_0_baco_enter(struct smu_context *smu);
214 int smu_v13_0_baco_exit(struct smu_context *smu);
216 int smu_v13_0_mode1_reset(struct smu_context *smu);
217 int smu_v13_0_mode2_reset(struct smu_context *smu);
219 int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
220 uint32_t *min, uint32_t *max);
222 int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
223 uint32_t min, uint32_t max);
225 int smu_v13_0_set_hard_freq_limited_range(struct smu_context *smu,
226 enum smu_clk_type clk_type,
230 int smu_v13_0_set_performance_level(struct smu_context *smu,
231 enum amd_dpm_forced_level level);
233 int smu_v13_0_set_power_source(struct smu_context *smu,
234 enum smu_power_src_type power_src);
236 int smu_v13_0_get_dpm_freq_by_index(struct smu_context *smu,
237 enum smu_clk_type clk_type,
241 int smu_v13_0_get_dpm_level_count(struct smu_context *smu,
242 enum smu_clk_type clk_type,
245 int smu_v13_0_set_single_dpm_table(struct smu_context *smu,
246 enum smu_clk_type clk_type,
247 struct smu_13_0_dpm_table *single_dpm_table);
249 int smu_v13_0_get_dpm_level_range(struct smu_context *smu,
250 enum smu_clk_type clk_type,
252 uint32_t *max_value);
254 int smu_v13_0_get_current_pcie_link_width_level(struct smu_context *smu);
256 int smu_v13_0_get_current_pcie_link_width(struct smu_context *smu);
258 int smu_v13_0_get_current_pcie_link_speed_level(struct smu_context *smu);
260 int smu_v13_0_get_current_pcie_link_speed(struct smu_context *smu);
262 int smu_v13_0_gfx_ulv_control(struct smu_context *smu,
265 int smu_v13_0_wait_for_event(struct smu_context *smu, enum smu_event_type event,