2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #ifndef __SMU_V11_0_H__
24 #define __SMU_V11_0_H__
26 #include "amdgpu_smu.h"
28 #define SMU11_DRIVER_IF_VERSION_INV 0xFFFFFFFF
29 #define SMU11_DRIVER_IF_VERSION_ARCT 0x17
30 #define SMU11_DRIVER_IF_VERSION_NV10 0x36
31 #define SMU11_DRIVER_IF_VERSION_NV12 0x36
32 #define SMU11_DRIVER_IF_VERSION_NV14 0x36
33 #define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x39
34 #define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0x5
35 #define SMU11_DRIVER_IF_VERSION_VANGOGH 0x01
36 #define SMU11_DRIVER_IF_VERSION_Dimgrey_Cavefish 0x9
39 #define MP0_Public 0x03800000
40 #define MP0_SRAM 0x03900000
41 #define MP1_Public 0x03b00000
42 #define MP1_SRAM 0x03c00004
45 #define smnMP1_FIRMWARE_FLAGS 0x3010024
46 #define smnMP0_FW_INTF 0x30101c0
47 #define smnMP1_PUB_CTRL 0x3010b14
49 #define TEMP_RANGE_MIN (0)
50 #define TEMP_RANGE_MAX (80 * 1000)
52 #define SMU11_TOOL_SIZE 0x19000
54 #define MAX_DPM_LEVELS 16
55 #define MAX_PCIE_CONF 2
57 #define CTF_OFFSET_EDGE 5
58 #define CTF_OFFSET_HOTSPOT 5
59 #define CTF_OFFSET_MEM 5
61 static const struct smu_temperature_range smu11_thermal_policy[] =
63 {-273150, 99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
64 { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000},
67 struct smu_11_0_max_sustainable_clocks {
68 uint32_t display_clock;
76 struct smu_11_0_dpm_clk_level {
81 struct smu_11_0_dpm_table {
82 uint32_t min; /* MHz */
83 uint32_t max; /* MHz */
86 struct smu_11_0_dpm_clk_level dpm_levels[MAX_DPM_LEVELS];
89 struct smu_11_0_pcie_table {
90 uint8_t pcie_gen[MAX_PCIE_CONF];
91 uint8_t pcie_lane[MAX_PCIE_CONF];
94 struct smu_11_0_dpm_tables {
95 struct smu_11_0_dpm_table soc_table;
96 struct smu_11_0_dpm_table gfx_table;
97 struct smu_11_0_dpm_table uclk_table;
98 struct smu_11_0_dpm_table eclk_table;
99 struct smu_11_0_dpm_table vclk_table;
100 struct smu_11_0_dpm_table vclk1_table;
101 struct smu_11_0_dpm_table dclk_table;
102 struct smu_11_0_dpm_table dclk1_table;
103 struct smu_11_0_dpm_table dcef_table;
104 struct smu_11_0_dpm_table pixel_table;
105 struct smu_11_0_dpm_table display_table;
106 struct smu_11_0_dpm_table phy_table;
107 struct smu_11_0_dpm_table fclk_table;
108 struct smu_11_0_pcie_table pcie_table;
111 struct smu_11_0_dpm_context {
112 struct smu_11_0_dpm_tables dpm_tables;
113 uint32_t workload_policy_mask;
114 uint32_t dcef_min_ds_clk;
117 enum smu_11_0_power_state {
118 SMU_11_0_POWER_STATE__D0 = 0,
119 SMU_11_0_POWER_STATE__D1,
120 SMU_11_0_POWER_STATE__D3, /* Sleep*/
121 SMU_11_0_POWER_STATE__D4, /* Hibernate*/
122 SMU_11_0_POWER_STATE__D5, /* Power off*/
125 struct smu_11_0_power_context {
126 uint32_t power_source;
127 uint8_t in_power_limit_boost_mode;
128 enum smu_11_0_power_state power_state;
131 enum smu_v11_0_baco_seq {
139 #if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3)
141 int smu_v11_0_init_microcode(struct smu_context *smu);
143 void smu_v11_0_fini_microcode(struct smu_context *smu);
145 int smu_v11_0_load_microcode(struct smu_context *smu);
147 int smu_v11_0_init_smc_tables(struct smu_context *smu);
149 int smu_v11_0_fini_smc_tables(struct smu_context *smu);
151 int smu_v11_0_init_power(struct smu_context *smu);
153 int smu_v11_0_fini_power(struct smu_context *smu);
155 int smu_v11_0_check_fw_status(struct smu_context *smu);
157 int smu_v11_0_setup_pptable(struct smu_context *smu);
159 int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu);
161 int smu_v11_0_check_fw_version(struct smu_context *smu);
163 int smu_v11_0_set_driver_table_location(struct smu_context *smu);
165 int smu_v11_0_set_tool_table_location(struct smu_context *smu);
167 int smu_v11_0_notify_memory_pool_location(struct smu_context *smu);
169 int smu_v11_0_system_features_control(struct smu_context *smu,
172 int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count);
174 int smu_v11_0_set_allowed_mask(struct smu_context *smu);
176 int smu_v11_0_notify_display_change(struct smu_context *smu);
178 int smu_v11_0_get_current_power_limit(struct smu_context *smu,
179 uint32_t *power_limit);
181 int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n);
183 int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu);
185 int smu_v11_0_enable_thermal_alert(struct smu_context *smu);
187 int smu_v11_0_disable_thermal_alert(struct smu_context *smu);
189 int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value);
191 int smu_v11_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk);
194 smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
195 struct pp_display_clock_request
199 smu_v11_0_get_fan_control_mode(struct smu_context *smu);
202 smu_v11_0_set_fan_control_mode(struct smu_context *smu,
205 int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
208 int smu_v11_0_get_fan_speed_rpm(struct smu_context *smu,
211 int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
214 int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable);
216 int smu_v11_0_register_irq_handler(struct smu_context *smu);
218 int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu);
220 int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
221 struct pp_smu_nv_clock_table *max_clocks);
223 bool smu_v11_0_baco_is_support(struct smu_context *smu);
225 enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu);
227 int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state);
229 int smu_v11_0_baco_enter(struct smu_context *smu);
230 int smu_v11_0_baco_exit(struct smu_context *smu);
232 int smu_v11_0_mode1_reset(struct smu_context *smu);
234 int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
235 uint32_t *min, uint32_t *max);
237 int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
238 uint32_t min, uint32_t max);
240 int smu_v11_0_set_hard_freq_limited_range(struct smu_context *smu,
241 enum smu_clk_type clk_type,
245 int smu_v11_0_set_performance_level(struct smu_context *smu,
246 enum amd_dpm_forced_level level);
248 int smu_v11_0_set_power_source(struct smu_context *smu,
249 enum smu_power_src_type power_src);
251 int smu_v11_0_get_dpm_freq_by_index(struct smu_context *smu,
252 enum smu_clk_type clk_type,
256 int smu_v11_0_get_dpm_level_count(struct smu_context *smu,
257 enum smu_clk_type clk_type,
260 int smu_v11_0_set_single_dpm_table(struct smu_context *smu,
261 enum smu_clk_type clk_type,
262 struct smu_11_0_dpm_table *single_dpm_table);
264 int smu_v11_0_get_dpm_level_range(struct smu_context *smu,
265 enum smu_clk_type clk_type,
267 uint32_t *max_value);
269 int smu_v11_0_get_current_pcie_link_width_level(struct smu_context *smu);
271 int smu_v11_0_get_current_pcie_link_width(struct smu_context *smu);
273 int smu_v11_0_get_current_pcie_link_speed_level(struct smu_context *smu);
275 int smu_v11_0_get_current_pcie_link_speed(struct smu_context *smu);
277 void smu_v11_0_init_gpu_metrics_v1_0(struct gpu_metrics_v1_0 *gpu_metrics);
279 int smu_v11_0_gfx_ulv_control(struct smu_context *smu,
282 int smu_v11_0_deep_sleep_control(struct smu_context *smu,
285 void smu_v11_0_interrupt_work(struct smu_context *smu);