2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #ifndef SMU74_DISCRETE_H
25 #define SMU74_DISCRETE_H
32 #define NUM_SCLK_RANGE 8
37 #define POSTDIV_DIV_BY_1 0
38 #define POSTDIV_DIV_BY_2 1
39 #define POSTDIV_DIV_BY_4 2
40 #define POSTDIV_DIV_BY_8 3
41 #define POSTDIV_DIV_BY_16 4
43 struct sclkFcwRange_t {
48 uint16_t fcw_trans_upper;
49 uint16_t fcw_trans_lower;
51 typedef struct sclkFcwRange_t sclkFcwRange_t;
59 typedef struct SMIO_Pattern SMIO_Pattern;
62 SMIO_Pattern Pattern[SMU_MAX_SMIO_LEVELS];
65 typedef struct SMIO_Table SMIO_Table;
67 struct SMU_SclkSetting {
68 uint32_t SclkFrequency;
74 uint16_t Sclk_slew_rate;
75 uint16_t Pcc_up_slew_rate;
76 uint16_t Pcc_down_slew_rate;
79 uint16_t Sclk_ss_slew_rate;
81 typedef struct SMU_SclkSetting SMU_SclkSetting;
83 struct SMU74_Discrete_GraphicsLevel {
84 SMU_VoltageLevel MinVoltage;
86 uint8_t DeepSleepDivId;
87 uint16_t ActivityLevel;
88 uint32_t CgSpllFuncCntl3;
89 uint32_t CgSpllFuncCntl4;
94 uint8_t EnabledForActivity;
95 uint8_t EnabledForThrottle;
98 uint8_t VoltageDownHyst;
99 uint8_t PowerThrottle;
100 SMU_SclkSetting SclkSetting;
103 typedef struct SMU74_Discrete_GraphicsLevel SMU74_Discrete_GraphicsLevel;
105 struct SMU74_Discrete_ACPILevel {
107 SMU_VoltageLevel MinVoltage;
108 uint32_t SclkFrequency;
110 uint8_t DisplayWatermark;
111 uint8_t DeepSleepDivId;
114 uint32_t CcPwrDynRm1;
116 SMU_SclkSetting SclkSetting;
119 typedef struct SMU74_Discrete_ACPILevel SMU74_Discrete_ACPILevel;
121 struct SMU74_Discrete_Ulv {
123 uint32_t CcPwrDynRm1;
125 uint8_t VddcOffsetVid;
131 typedef struct SMU74_Discrete_Ulv SMU74_Discrete_Ulv;
133 struct SMU74_Discrete_MemoryLevel {
134 SMU_VoltageLevel MinVoltage;
137 uint32_t MclkFrequency;
139 uint8_t StutterEnable;
140 uint8_t EnabledForThrottle;
141 uint8_t EnabledForActivity;
146 uint8_t VoltageDownHyst;
149 uint16_t ActivityLevel;
150 uint8_t DisplayWatermark;
154 typedef struct SMU74_Discrete_MemoryLevel SMU74_Discrete_MemoryLevel;
156 struct SMU74_Discrete_LinkLevel {
157 uint8_t PcieGenSpeed;
158 uint8_t PcieLaneCount;
159 uint8_t EnabledForActivity;
161 uint32_t DownThreshold;
162 uint32_t UpThreshold;
167 typedef struct SMU74_Discrete_LinkLevel SMU74_Discrete_LinkLevel;
169 struct SMU74_Discrete_MCArbDramTimingTableEntry {
170 uint32_t McArbDramTiming;
171 uint32_t McArbDramTiming2;
172 uint8_t McArbBurstTime;
176 typedef struct SMU74_Discrete_MCArbDramTimingTableEntry SMU74_Discrete_MCArbDramTimingTableEntry;
178 struct SMU74_Discrete_MCArbDramTimingTable {
179 SMU74_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
182 typedef struct SMU74_Discrete_MCArbDramTimingTable SMU74_Discrete_MCArbDramTimingTable;
184 struct SMU74_Discrete_UvdLevel {
185 uint32_t VclkFrequency;
186 uint32_t DclkFrequency;
187 SMU_VoltageLevel MinVoltage;
193 typedef struct SMU74_Discrete_UvdLevel SMU74_Discrete_UvdLevel;
195 struct SMU74_Discrete_ExtClkLevel {
197 SMU_VoltageLevel MinVoltage;
202 typedef struct SMU74_Discrete_ExtClkLevel SMU74_Discrete_ExtClkLevel;
204 struct SMU74_Discrete_StateInfo {
205 uint32_t SclkFrequency;
206 uint32_t MclkFrequency;
207 uint32_t VclkFrequency;
208 uint32_t DclkFrequency;
209 uint32_t SamclkFrequency;
210 uint32_t AclkFrequency;
211 uint32_t EclkFrequency;
212 uint16_t MvddVoltage;
214 uint8_t DisplayWatermark;
224 typedef struct SMU74_Discrete_StateInfo SMU74_Discrete_StateInfo;
226 struct SMU_QuadraticCoeffs {
234 typedef struct SMU_QuadraticCoeffs SMU_QuadraticCoeffs;
236 struct SMU74_Discrete_DpmTable {
238 SMU74_PIDController GraphicsPIDController;
239 SMU74_PIDController MemoryPIDController;
240 SMU74_PIDController LinkPIDController;
242 uint32_t SystemFlags;
247 SMIO_Table SmioTable1;
248 SMIO_Table SmioTable2;
250 uint32_t MvddLevelCount;
253 uint8_t BapmVddcVidHiSidd[SMU74_MAX_LEVELS_VDDC];
254 uint8_t BapmVddcVidLoSidd[SMU74_MAX_LEVELS_VDDC];
255 uint8_t BapmVddcVidHiSidd2[SMU74_MAX_LEVELS_VDDC];
257 uint8_t GraphicsDpmLevelCount;
258 uint8_t MemoryDpmLevelCount;
259 uint8_t LinkLevelCount;
260 uint8_t MasterDeepSleepControl;
262 uint8_t UvdLevelCount;
263 uint8_t VceLevelCount;
264 uint8_t AcpLevelCount;
265 uint8_t SamuLevelCount;
267 uint8_t ThermOutGpio;
268 uint8_t ThermOutPolarity;
269 uint8_t ThermOutMode;
276 uint16_t FanStartTemperature;
277 uint16_t FanStopTemperature;
280 uint32_t Reserved[1];
282 SMU74_Discrete_GraphicsLevel GraphicsLevel[SMU74_MAX_LEVELS_GRAPHICS];
283 SMU74_Discrete_MemoryLevel MemoryACPILevel;
284 SMU74_Discrete_MemoryLevel MemoryLevel[SMU74_MAX_LEVELS_MEMORY];
285 SMU74_Discrete_LinkLevel LinkLevel[SMU74_MAX_LEVELS_LINK];
286 SMU74_Discrete_ACPILevel ACPILevel;
287 SMU74_Discrete_UvdLevel UvdLevel[SMU74_MAX_LEVELS_UVD];
288 SMU74_Discrete_ExtClkLevel VceLevel[SMU74_MAX_LEVELS_VCE];
289 SMU74_Discrete_ExtClkLevel AcpLevel[SMU74_MAX_LEVELS_ACP];
290 SMU74_Discrete_ExtClkLevel SamuLevel[SMU74_MAX_LEVELS_SAMU];
291 SMU74_Discrete_Ulv Ulv;
293 uint8_t DisplayWatermark[SMU74_MAX_LEVELS_MEMORY][SMU74_MAX_LEVELS_GRAPHICS];
295 uint32_t SclkStepSize;
296 uint32_t Smio[SMU74_MAX_ENTRIES_SMIO];
298 uint8_t UvdBootLevel;
299 uint8_t VceBootLevel;
300 uint8_t AcpBootLevel;
301 uint8_t SamuBootLevel;
303 uint8_t GraphicsBootLevel;
304 uint8_t GraphicsVoltageChangeEnable;
305 uint8_t GraphicsThermThrottleEnable;
306 uint8_t GraphicsInterval;
308 uint8_t VoltageInterval;
309 uint8_t ThermalInterval;
310 uint16_t TemperatureLimitHigh;
312 uint16_t TemperatureLimitLow;
313 uint8_t MemoryBootLevel;
314 uint8_t MemoryVoltageChangeEnable;
317 uint8_t MemoryInterval;
318 uint8_t MemoryThermThrottleEnable;
320 uint16_t VoltageResponseTime;
321 uint16_t PhaseResponseTime;
323 uint8_t PCIeBootLinkLevel;
324 uint8_t PCIeGenInterval;
333 uint16_t PPM_PkgPwrLimit;
334 uint16_t PPM_TemperatureLimit;
339 uint16_t FpsHighThreshold;
340 uint16_t FpsLowThreshold;
342 uint16_t BAPMTI_R[SMU74_DTE_ITERATIONS][SMU74_DTE_SOURCES][SMU74_DTE_SINKS];
343 uint16_t BAPMTI_RC[SMU74_DTE_ITERATIONS][SMU74_DTE_SOURCES][SMU74_DTE_SINKS];
345 uint16_t TemperatureLimitEdge;
346 uint16_t TemperatureLimitHotspot;
351 uint16_t FanGainEdge;
352 uint16_t FanGainHotspot;
354 uint32_t LowSclkInterruptThreshold;
355 uint32_t VddGfxReChkWait;
357 uint8_t ClockStretcherAmount;
358 uint8_t Sclk_CKS_masterEn0_7;
359 uint8_t Sclk_CKS_masterEn8_15;
360 uint8_t DPMFreezeAndForced;
362 uint8_t Sclk_voltageOffset[8];
364 SMU_ClockStretcherDataTable ClockStretcherDataTable;
365 SMU_CKS_LOOKUPTable CKS_LOOKUPTable;
367 uint32_t CurrSclkPllRange;
368 sclkFcwRange_t SclkFcwRangeTable[NUM_SCLK_RANGE];
369 GB_VDROOP_TABLE_t BTCGB_VDROOP_TABLE[BTCGB_VDROOP_TABLE_MAX_ENTRIES];
370 SMU_QuadraticCoeffs AVFSGB_VDROOP_TABLE[AVFSGB_VDROOP_TABLE_MAX_ENTRIES];
373 typedef struct SMU74_Discrete_DpmTable SMU74_Discrete_DpmTable;
376 struct SMU74_Discrete_FanTable {
391 uint32_t RefreshPeriod;
397 typedef struct SMU74_Discrete_FanTable SMU74_Discrete_FanTable;
399 #define SMU7_DISCRETE_GPIO_SCLK_DEBUG 4
400 #define SMU7_DISCRETE_GPIO_SCLK_DEBUG_BIT (0x1 << SMU7_DISCRETE_GPIO_SCLK_DEBUG)
403 struct SMU7_MclkDpmScoreboard {
404 uint32_t PercentageBusy;
410 uint32_t SigmaDeltaAccum;
411 uint32_t SigmaDeltaOutput;
412 uint32_t SigmaDeltaLevel;
414 uint32_t UtilizationSetpoint;
416 uint8_t TdpClampMode;
417 uint8_t TdcClampMode;
418 uint8_t ThermClampMode;
423 uint8_t LevelChangeInProgress;
427 uint8_t VoltageDownHyst;
432 uint8_t DpmForceLevel;
436 uint32_t MinimumPerfMclk;
440 uint8_t MclkSwitchInProgress;
441 uint8_t MclkSwitchCritical;
443 uint8_t IgnoreVBlank;
444 uint8_t TargetMclkIndex;
445 uint16_t VbiFailureCount;
446 uint8_t VbiWaitCounter;
447 uint8_t EnabledLevelsChange;
449 uint16_t LevelResidencyCounters[SMU74_MAX_LEVELS_MEMORY];
450 uint16_t LevelSwitchCounters[SMU74_MAX_LEVELS_MEMORY];
452 void (*TargetStateCalculator)(uint8_t);
453 void (*SavedTargetStateCalculator)(uint8_t);
455 uint16_t AutoDpmInterval;
456 uint16_t AutoDpmRange;
458 uint16_t VbiTimeoutCount;
459 uint16_t MclkSwitchingTime;
462 uint8_t Save_PIC_VDDGFX_EXIT;
463 uint8_t Save_PIC_VDDGFX_ENTER;
467 typedef struct SMU7_MclkDpmScoreboard SMU7_MclkDpmScoreboard;
469 struct SMU7_UlvScoreboard {
473 uint8_t WaitingForUlv;
476 uint8_t UlvMasterEnable;
478 uint32_t UlvAbortedCount;
479 uint32_t UlvTimeStamp;
482 typedef struct SMU7_UlvScoreboard SMU7_UlvScoreboard;
484 struct VddgfxSavedRegisters {
486 uint32_t MEC_BaseAddress_Hi;
487 uint32_t MEC_BaseAddress_Lo;
488 uint32_t THM_TMON0_CTRL2__RDIR_PRESENT;
489 uint32_t THM_TMON1_CTRL2__RDIR_PRESENT;
490 uint32_t CP_INT_CNTL;
493 typedef struct VddgfxSavedRegisters VddgfxSavedRegisters;
495 struct SMU7_VddGfxScoreboard {
496 uint8_t VddGfxEnable;
497 uint8_t VddGfxActive;
498 uint8_t VPUResetOccured;
501 uint32_t VddGfxEnteredCount;
502 uint32_t VddGfxAbortedCount;
506 VddgfxSavedRegisters SavedRegisters;
509 typedef struct SMU7_VddGfxScoreboard SMU7_VddGfxScoreboard;
511 struct SMU7_TdcLimitScoreboard {
515 uint32_t FilteredIddc;
518 SMU7_HystController_Data HystControllerData;
521 typedef struct SMU7_TdcLimitScoreboard SMU7_TdcLimitScoreboard;
523 struct SMU7_PkgPwrLimitScoreboard {
527 uint32_t FilteredPkgPwr;
530 uint32_t LimitFromDriver;
531 SMU7_HystController_Data HystControllerData;
534 typedef struct SMU7_PkgPwrLimitScoreboard SMU7_PkgPwrLimitScoreboard;
536 struct SMU7_BapmScoreboard {
537 uint32_t source_powers[SMU74_DTE_SOURCES];
538 uint32_t source_powers_last[SMU74_DTE_SOURCES];
539 int32_t entity_temperatures[SMU74_NUM_GPU_TES];
540 int32_t initial_entity_temperatures[SMU74_NUM_GPU_TES];
543 int32_t therm_influence_coeff_table[SMU74_DTE_ITERATIONS * SMU74_DTE_SOURCES * SMU74_DTE_SINKS * 2];
544 int32_t therm_node_table[SMU74_DTE_ITERATIONS * SMU74_DTE_SOURCES * SMU74_DTE_SINKS];
545 uint16_t ConfigTDPPowerScalar;
546 uint16_t FanSpeedPowerScalar;
547 uint16_t OverDrivePowerScalar;
548 uint16_t OverDriveLimitScalar;
549 uint16_t FinalPowerScalar;
553 SMU7_HystController_Data HystControllerData;
555 int32_t temperature_gradient_slope;
556 int32_t temperature_gradient;
557 uint32_t measured_temperature;
561 typedef struct SMU7_BapmScoreboard SMU7_BapmScoreboard;
563 struct SMU7_AcpiScoreboard {
564 uint32_t SavedInterruptMask[2];
565 uint8_t LastACPIRequest;
569 SMU74_Discrete_ACPILevel D0Level;
572 typedef struct SMU7_AcpiScoreboard SMU7_AcpiScoreboard;
574 struct SMU74_Discrete_PmFuses {
575 uint8_t BapmVddCVidHiSidd[8];
576 uint8_t BapmVddCVidLoSidd[8];
578 uint8_t SviLoadLineEn;
579 uint8_t SviLoadLineVddC;
580 uint8_t SviLoadLineTrimVddC;
581 uint8_t SviLoadLineOffsetVddC;
582 uint16_t TDC_VDDC_PkgLimit;
583 uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;
585 uint8_t TdcWaterfallCtl;
586 uint8_t LPMLTemperatureMin;
587 uint8_t LPMLTemperatureMax;
590 uint8_t LPMLTemperatureScaler[16];
592 int16_t FuzzyFan_ErrorSetDelta;
593 int16_t FuzzyFan_ErrorRateSetDelta;
594 int16_t FuzzyFan_PwmSetDelta;
599 uint8_t GnbLPMLMaxVid;
600 uint8_t GnbLPMLMinVid;
601 uint8_t Reserved1[2];
603 uint16_t BapmVddCBaseLeakageHiSidd;
604 uint16_t BapmVddCBaseLeakageLoSidd;
606 uint16_t VFT_Temp[3];
609 SMU_QuadraticCoeffs VFT_ATE[3];
611 SMU_QuadraticCoeffs AVFS_GB;
612 SMU_QuadraticCoeffs ATE_ACBTC_GB;
614 SMU_QuadraticCoeffs P2V;
616 uint32_t PsmCharzFreq;
618 uint16_t InversionVoltage;
619 uint16_t PsmCharzTemp;
621 uint32_t EnabledAvfsModules;
624 typedef struct SMU74_Discrete_PmFuses SMU74_Discrete_PmFuses;
626 struct SMU7_Discrete_Log_Header_Table {
632 uint32_t num_of_entries;
636 uint32_t filler_1[2];
639 typedef struct SMU7_Discrete_Log_Header_Table SMU7_Discrete_Log_Header_Table;
641 struct SMU7_Discrete_Log_Cntl {
646 uint32_t SamplesLogged;
652 typedef struct SMU7_Discrete_Log_Cntl SMU7_Discrete_Log_Cntl;
654 #if defined SMU__DGPU_ONLY
655 #define CAC_ACC_NW_NUM_OF_SIGNALS 87
659 struct SMU7_Discrete_Cac_Collection_Table {
660 uint32_t temperature;
661 uint32_t cac_acc_nw[CAC_ACC_NW_NUM_OF_SIGNALS];
664 typedef struct SMU7_Discrete_Cac_Collection_Table SMU7_Discrete_Cac_Collection_Table;
666 struct SMU7_Discrete_Cac_Verification_Table {
667 uint32_t VddcTotalPower;
668 uint32_t VddcLeakagePower;
669 uint32_t VddcConstantPower;
670 uint32_t VddcGfxDynamicPower;
671 uint32_t VddcUvdDynamicPower;
672 uint32_t VddcVceDynamicPower;
673 uint32_t VddcAcpDynamicPower;
674 uint32_t VddcPcieDynamicPower;
675 uint32_t VddcDceDynamicPower;
676 uint32_t VddcCurrent;
677 uint32_t VddcVoltage;
678 uint32_t VddciTotalPower;
679 uint32_t VddciLeakagePower;
680 uint32_t VddciConstantPower;
681 uint32_t VddciDynamicPower;
682 uint32_t Vddr1TotalPower;
683 uint32_t Vddr1LeakagePower;
684 uint32_t Vddr1ConstantPower;
685 uint32_t Vddr1DynamicPower;
687 uint32_t temperature;
690 typedef struct SMU7_Discrete_Cac_Verification_Table SMU7_Discrete_Cac_Verification_Table;
692 struct SMU7_Discrete_Pm_Status_Table {
697 uint32_t P_scalar_acc;
703 uint32_t I_calc_acc_vddci;
704 uint32_t V_calc_noload_acc;
705 uint32_t V_calc_load_acc;
706 uint32_t V_calc_noload_acc_vddci;
708 uint32_t V_meas_noload_acc;
709 uint32_t V_meas_load_acc;
711 uint32_t P_meas_acc_vddci;
712 uint32_t V_meas_noload_acc_vddci;
713 uint32_t V_meas_load_acc_vddci;
714 uint32_t I_meas_acc_vddci;
716 uint16_t Sclk_dpm_residency[8];
717 uint16_t Uvd_dpm_residency[8];
718 uint16_t Vce_dpm_residency[8];
719 uint16_t Mclk_dpm_residency[4];
721 uint32_t P_vddci_acc;
722 uint32_t P_vddr1_acc;
726 uint32_t MclkSwitchingTime_max;
727 uint32_t MclkSwitchingTime_acc;
734 typedef struct SMU7_Discrete_Pm_Status_Table SMU7_Discrete_Pm_Status_Table;
736 #define SMU7_MAX_GFX_CU_COUNT 16
738 struct SMU7_GfxCuPgScoreboard {
741 uint8_t WaterfallDown;
742 uint8_t WaterfallLimit;
747 uint8_t MaxSupportedCu;
748 uint8_t MinSupportedCu;
749 uint8_t PendingGfxCuHostInterrupt;
750 uint8_t LastFilteredMaxCuInteger;
751 uint16_t FilteredMaxCu;
752 uint16_t FilteredMaxCuAlpha;
753 uint16_t FilterResetCount;
754 uint16_t FilterResetCountLimit;
756 uint8_t ForceCuCount;
760 typedef struct SMU7_GfxCuPgScoreboard SMU7_GfxCuPgScoreboard;
762 #define SMU7_SCLK_CAC 0x561
763 #define SMU7_MCLK_CAC 0xF9
764 #define SMU7_VCLK_CAC 0x2DE
765 #define SMU7_DCLK_CAC 0x2DE
766 #define SMU7_ECLK_CAC 0x25E
767 #define SMU7_ACLK_CAC 0x25E
768 #define SMU7_SAMCLK_CAC 0x25E
769 #define SMU7_DISPCLK_CAC 0x100
770 #define SMU7_CAC_CONSTANT 0x2EE3430
771 #define SMU7_CAC_CONSTANT_SHIFT 18
773 #define SMU7_VDDCI_MCLK_CONST 1765
774 #define SMU7_VDDCI_MCLK_CONST_SHIFT 16
775 #define SMU7_VDDCI_VDDCI_CONST 50958
776 #define SMU7_VDDCI_VDDCI_CONST_SHIFT 14
777 #define SMU7_VDDCI_CONST 11781
778 #define SMU7_VDDCI_STROBE_PWR 1331
780 #define SMU7_VDDR1_CONST 693
781 #define SMU7_VDDR1_CAC_WEIGHT 20
782 #define SMU7_VDDR1_CAC_WEIGHT_SHIFT 19
783 #define SMU7_VDDR1_STROBE_PWR 512
785 #define SMU7_AREA_COEFF_UVD 0xA78
786 #define SMU7_AREA_COEFF_VCE 0x190A
787 #define SMU7_AREA_COEFF_ACP 0x22D1
788 #define SMU7_AREA_COEFF_SAMU 0x534
790 #define SMU7_THERM_OUT_MODE_DISABLE 0x0
791 #define SMU7_THERM_OUT_MODE_THERM_ONLY 0x1
792 #define SMU7_THERM_OUT_MODE_THERM_VRHOT 0x2
795 #define SQ_Enable_MASK 0x1
796 #define SQ_IR_MASK 0x2
797 #define SQ_PCC_MASK 0x4
798 #define SQ_EDC_MASK 0x8
800 #define TCP_Enable_MASK 0x100
801 #define TCP_IR_MASK 0x200
802 #define TCP_PCC_MASK 0x400
803 #define TCP_EDC_MASK 0x800
805 #define TD_Enable_MASK 0x10000
806 #define TD_IR_MASK 0x20000
807 #define TD_PCC_MASK 0x40000
808 #define TD_EDC_MASK 0x80000
810 #define DB_Enable_MASK 0x1000000
811 #define DB_IR_MASK 0x2000000
812 #define DB_PCC_MASK 0x4000000
813 #define DB_EDC_MASK 0x8000000
815 #define SQ_Enable_SHIFT 0
816 #define SQ_IR_SHIFT 1
817 #define SQ_PCC_SHIFT 2
818 #define SQ_EDC_SHIFT 3
820 #define TCP_Enable_SHIFT 8
821 #define TCP_IR_SHIFT 9
822 #define TCP_PCC_SHIFT 10
823 #define TCP_EDC_SHIFT 11
825 #define TD_Enable_SHIFT 16
826 #define TD_IR_SHIFT 17
827 #define TD_PCC_SHIFT 18
828 #define TD_EDC_SHIFT 19
830 #define DB_Enable_SHIFT 24
831 #define DB_IR_SHIFT 25
832 #define DB_PCC_SHIFT 26
833 #define DB_EDC_SHIFT 27
835 #define BTCGB0_Vdroop_Enable_MASK 0x1
836 #define BTCGB1_Vdroop_Enable_MASK 0x2
837 #define AVFSGB0_Vdroop_Enable_MASK 0x4
838 #define AVFSGB1_Vdroop_Enable_MASK 0x8
840 #define BTCGB0_Vdroop_Enable_SHIFT 0
841 #define BTCGB1_Vdroop_Enable_SHIFT 1
842 #define AVFSGB0_Vdroop_Enable_SHIFT 2
843 #define AVFSGB1_Vdroop_Enable_SHIFT 3