2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <linux/seq_file.h>
27 #include "amd_powerplay.h"
28 #include "hardwaremanager.h"
29 #include "hwmgr_ppt.h"
30 #include "ppatomctrl.h"
31 #include "power_state.h"
32 #include "smu_helper.h"
35 struct phm_fan_speed_info;
36 struct pp_atomctrl_voltage_table;
38 #define VOLTAGE_SCALE 4
39 #define VOLTAGE_VID_OFFSET_SCALE1 625
40 #define VOLTAGE_VID_OFFSET_SCALE2 100
43 DISPLAY_GAP_VBLANK_OR_WM = 0, /* Wait for vblank or MCHG watermark. */
44 DISPLAY_GAP_VBLANK = 1, /* Wait for vblank. */
45 DISPLAY_GAP_WATERMARK = 2, /* Wait for MCHG watermark. (Note that HW may deassert WM in VBI depending on DC_STUTTER_CNTL.) */
46 DISPLAY_GAP_IGNORE = 3 /* Do not wait. */
48 typedef enum DISPLAY_GAP DISPLAY_GAP;
63 struct vi_dpm_level dpm_level[1];
66 #define PCIE_PERF_REQ_REMOVE_REGISTRY 0
67 #define PCIE_PERF_REQ_FORCE_LOWPOWER 1
68 #define PCIE_PERF_REQ_GEN1 2
69 #define PCIE_PERF_REQ_GEN2 3
70 #define PCIE_PERF_REQ_GEN3 4
72 enum PHM_BackEnd_Magic {
73 PHM_Dummy_Magic = 0xAA5555AA,
74 PHM_RV770_Magic = 0xDCBAABCD,
75 PHM_Kong_Magic = 0x239478DF,
76 PHM_NIslands_Magic = 0x736C494E,
77 PHM_Sumo_Magic = 0x8339FA11,
78 PHM_SIslands_Magic = 0x369431AC,
79 PHM_Trinity_Magic = 0x96751873,
80 PHM_CIslands_Magic = 0x38AC78B0,
81 PHM_Kv_Magic = 0xDCBBABC0,
82 PHM_VIslands_Magic = 0x20130307,
83 PHM_Cz_Magic = 0x67DCBA25,
84 PHM_Rv_Magic = 0x20161121
87 struct phm_set_power_state_input {
88 const struct pp_hw_power_state *pcurrent_state;
89 const struct pp_hw_power_state *pnew_state;
92 struct phm_clock_array {
97 struct phm_clock_voltage_dependency_record {
102 struct phm_vceclock_voltage_dependency_record {
108 struct phm_uvdclock_voltage_dependency_record {
114 struct phm_samuclock_voltage_dependency_record {
119 struct phm_acpclock_voltage_dependency_record {
124 struct phm_clock_voltage_dependency_table {
125 uint32_t count; /* Number of entries. */
126 struct phm_clock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
129 struct phm_phase_shedding_limits_record {
135 struct phm_uvd_clock_voltage_dependency_record {
141 struct phm_uvd_clock_voltage_dependency_table {
143 struct phm_uvd_clock_voltage_dependency_record entries[1];
146 struct phm_acp_clock_voltage_dependency_record {
151 struct phm_acp_clock_voltage_dependency_table {
153 struct phm_acp_clock_voltage_dependency_record entries[1];
156 struct phm_vce_clock_voltage_dependency_record {
162 struct phm_phase_shedding_limits_table {
164 struct phm_phase_shedding_limits_record entries[1];
167 struct phm_vceclock_voltage_dependency_table {
168 uint8_t count; /* Number of entries. */
169 struct phm_vceclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
172 struct phm_uvdclock_voltage_dependency_table {
173 uint8_t count; /* Number of entries. */
174 struct phm_uvdclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
177 struct phm_samuclock_voltage_dependency_table {
178 uint8_t count; /* Number of entries. */
179 struct phm_samuclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
182 struct phm_acpclock_voltage_dependency_table {
183 uint32_t count; /* Number of entries. */
184 struct phm_acpclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
187 struct phm_vce_clock_voltage_dependency_table {
189 struct phm_vce_clock_voltage_dependency_record entries[1];
193 enum SMU_ASIC_RESET_MODE
195 SMU_ASIC_RESET_MODE_0,
196 SMU_ASIC_RESET_MODE_1,
197 SMU_ASIC_RESET_MODE_2,
200 struct pp_smumgr_func {
202 int (*smu_init)(struct pp_hwmgr *hwmgr);
203 int (*smu_fini)(struct pp_hwmgr *hwmgr);
204 int (*start_smu)(struct pp_hwmgr *hwmgr);
205 int (*check_fw_load_finish)(struct pp_hwmgr *hwmgr,
207 int (*request_smu_load_fw)(struct pp_hwmgr *hwmgr);
208 int (*request_smu_load_specific_fw)(struct pp_hwmgr *hwmgr,
210 uint32_t (*get_argument)(struct pp_hwmgr *hwmgr);
211 int (*send_msg_to_smc)(struct pp_hwmgr *hwmgr, uint16_t msg);
212 int (*send_msg_to_smc_with_parameter)(struct pp_hwmgr *hwmgr,
213 uint16_t msg, uint32_t parameter);
214 int (*download_pptable_settings)(struct pp_hwmgr *hwmgr,
216 int (*upload_pptable_settings)(struct pp_hwmgr *hwmgr);
217 int (*update_smc_table)(struct pp_hwmgr *hwmgr, uint32_t type);
218 int (*process_firmware_header)(struct pp_hwmgr *hwmgr);
219 int (*update_sclk_threshold)(struct pp_hwmgr *hwmgr);
220 int (*thermal_setup_fan_table)(struct pp_hwmgr *hwmgr);
221 int (*thermal_avfs_enable)(struct pp_hwmgr *hwmgr);
222 int (*init_smc_table)(struct pp_hwmgr *hwmgr);
223 int (*populate_all_graphic_levels)(struct pp_hwmgr *hwmgr);
224 int (*populate_all_memory_levels)(struct pp_hwmgr *hwmgr);
225 int (*initialize_mc_reg_table)(struct pp_hwmgr *hwmgr);
226 uint32_t (*get_offsetof)(uint32_t type, uint32_t member);
227 uint32_t (*get_mac_definition)(uint32_t value);
228 bool (*is_dpm_running)(struct pp_hwmgr *hwmgr);
229 bool (*is_hw_avfs_present)(struct pp_hwmgr *hwmgr);
230 int (*update_dpm_settings)(struct pp_hwmgr *hwmgr, void *profile_setting);
231 int (*smc_table_manager)(struct pp_hwmgr *hwmgr, uint8_t *table, uint16_t table_id, bool rw); /*rw: true for read, false for write */
232 int (*stop_smc)(struct pp_hwmgr *hwmgr);
235 struct pp_hwmgr_func {
236 int (*backend_init)(struct pp_hwmgr *hw_mgr);
237 int (*backend_fini)(struct pp_hwmgr *hw_mgr);
238 int (*asic_setup)(struct pp_hwmgr *hw_mgr);
239 int (*get_power_state_size)(struct pp_hwmgr *hw_mgr);
241 int (*apply_state_adjust_rules)(struct pp_hwmgr *hwmgr,
242 struct pp_power_state *prequest_ps,
243 const struct pp_power_state *pcurrent_ps);
245 int (*apply_clocks_adjust_rules)(struct pp_hwmgr *hwmgr);
247 int (*force_dpm_level)(struct pp_hwmgr *hw_mgr,
248 enum amd_dpm_forced_level level);
250 int (*dynamic_state_management_enable)(
251 struct pp_hwmgr *hw_mgr);
252 int (*dynamic_state_management_disable)(
253 struct pp_hwmgr *hw_mgr);
255 int (*patch_boot_state)(struct pp_hwmgr *hwmgr,
256 struct pp_hw_power_state *hw_ps);
258 int (*get_pp_table_entry)(struct pp_hwmgr *hwmgr,
259 unsigned long, struct pp_power_state *);
260 int (*get_num_of_pp_table_entries)(struct pp_hwmgr *hwmgr);
261 int (*powerdown_uvd)(struct pp_hwmgr *hwmgr);
262 void (*powergate_vce)(struct pp_hwmgr *hwmgr, bool bgate);
263 void (*powergate_uvd)(struct pp_hwmgr *hwmgr, bool bgate);
264 void (*powergate_acp)(struct pp_hwmgr *hwmgr, bool bgate);
265 uint32_t (*get_mclk)(struct pp_hwmgr *hwmgr, bool low);
266 uint32_t (*get_sclk)(struct pp_hwmgr *hwmgr, bool low);
267 int (*power_state_set)(struct pp_hwmgr *hwmgr,
269 int (*notify_smc_display_config_after_ps_adjustment)(struct pp_hwmgr *hwmgr);
270 int (*pre_display_config_changed)(struct pp_hwmgr *hwmgr);
271 int (*display_config_changed)(struct pp_hwmgr *hwmgr);
272 int (*disable_clock_power_gating)(struct pp_hwmgr *hwmgr);
273 int (*update_clock_gatings)(struct pp_hwmgr *hwmgr,
274 const uint32_t *msg_id);
275 int (*set_max_fan_rpm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm);
276 int (*set_max_fan_pwm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm);
277 int (*stop_thermal_controller)(struct pp_hwmgr *hwmgr);
278 int (*get_fan_speed_info)(struct pp_hwmgr *hwmgr, struct phm_fan_speed_info *fan_speed_info);
279 void (*set_fan_control_mode)(struct pp_hwmgr *hwmgr, uint32_t mode);
280 uint32_t (*get_fan_control_mode)(struct pp_hwmgr *hwmgr);
281 int (*set_fan_speed_percent)(struct pp_hwmgr *hwmgr, uint32_t percent);
282 int (*get_fan_speed_percent)(struct pp_hwmgr *hwmgr, uint32_t *speed);
283 int (*set_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t percent);
284 int (*get_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t *speed);
285 int (*reset_fan_speed_to_default)(struct pp_hwmgr *hwmgr);
286 int (*uninitialize_thermal_controller)(struct pp_hwmgr *hwmgr);
287 int (*register_irq_handlers)(struct pp_hwmgr *hwmgr);
288 bool (*check_smc_update_required_for_display_configuration)(struct pp_hwmgr *hwmgr);
289 int (*check_states_equal)(struct pp_hwmgr *hwmgr,
290 const struct pp_hw_power_state *pstate1,
291 const struct pp_hw_power_state *pstate2,
293 int (*set_cpu_power_state)(struct pp_hwmgr *hwmgr);
294 int (*store_cc6_data)(struct pp_hwmgr *hwmgr, uint32_t separation_time,
295 bool cc6_disable, bool pstate_disable,
296 bool pstate_switch_disable);
297 int (*get_dal_power_level)(struct pp_hwmgr *hwmgr,
298 struct amd_pp_simple_clock_info *info);
299 int (*get_performance_level)(struct pp_hwmgr *, const struct pp_hw_power_state *,
300 PHM_PerformanceLevelDesignation, uint32_t, PHM_PerformanceLevel *);
301 int (*get_current_shallow_sleep_clocks)(struct pp_hwmgr *hwmgr,
302 const struct pp_hw_power_state *state, struct pp_clock_info *clock_info);
303 int (*get_clock_by_type)(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks);
304 int (*get_clock_by_type_with_latency)(struct pp_hwmgr *hwmgr,
305 enum amd_pp_clock_type type,
306 struct pp_clock_levels_with_latency *clocks);
307 int (*get_clock_by_type_with_voltage)(struct pp_hwmgr *hwmgr,
308 enum amd_pp_clock_type type,
309 struct pp_clock_levels_with_voltage *clocks);
310 int (*set_watermarks_for_clocks_ranges)(struct pp_hwmgr *hwmgr, void *clock_ranges);
311 int (*display_clock_voltage_request)(struct pp_hwmgr *hwmgr,
312 struct pp_display_clock_request *clock);
313 int (*get_max_high_clocks)(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks);
314 int (*power_off_asic)(struct pp_hwmgr *hwmgr);
315 int (*force_clock_level)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, uint32_t mask);
316 int (*print_clock_levels)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, char *buf);
317 int (*powergate_gfx)(struct pp_hwmgr *hwmgr, bool enable);
318 int (*get_sclk_od)(struct pp_hwmgr *hwmgr);
319 int (*set_sclk_od)(struct pp_hwmgr *hwmgr, uint32_t value);
320 int (*get_mclk_od)(struct pp_hwmgr *hwmgr);
321 int (*set_mclk_od)(struct pp_hwmgr *hwmgr, uint32_t value);
322 int (*read_sensor)(struct pp_hwmgr *hwmgr, int idx, void *value, int *size);
323 int (*avfs_control)(struct pp_hwmgr *hwmgr, bool enable);
324 int (*disable_smc_firmware_ctf)(struct pp_hwmgr *hwmgr);
325 int (*set_active_display_count)(struct pp_hwmgr *hwmgr, uint32_t count);
326 int (*set_min_deep_sleep_dcefclk)(struct pp_hwmgr *hwmgr, uint32_t clock);
327 int (*start_thermal_controller)(struct pp_hwmgr *hwmgr, struct PP_TemperatureRange *range);
328 int (*notify_cac_buffer_info)(struct pp_hwmgr *hwmgr,
329 uint32_t virtual_addr_low,
330 uint32_t virtual_addr_hi,
331 uint32_t mc_addr_low,
334 int (*update_nbdpm_pstate)(struct pp_hwmgr *hwmgr,
337 int (*get_thermal_temperature_range)(struct pp_hwmgr *hwmgr,
338 struct PP_TemperatureRange *range);
339 int (*get_power_profile_mode)(struct pp_hwmgr *hwmgr, char *buf);
340 int (*set_power_profile_mode)(struct pp_hwmgr *hwmgr, long *input, uint32_t size);
341 int (*odn_edit_dpm_table)(struct pp_hwmgr *hwmgr,
342 enum PP_OD_DPM_TABLE_COMMAND type,
343 long *input, uint32_t size);
344 int (*set_fine_grain_clk_vol)(struct pp_hwmgr *hwmgr,
345 enum PP_OD_DPM_TABLE_COMMAND type,
346 long *input, uint32_t size);
347 int (*set_power_limit)(struct pp_hwmgr *hwmgr, uint32_t n);
348 int (*powergate_mmhub)(struct pp_hwmgr *hwmgr);
349 int (*smus_notify_pwe)(struct pp_hwmgr *hwmgr);
350 int (*powergate_sdma)(struct pp_hwmgr *hwmgr, bool bgate);
351 int (*enable_mgpu_fan_boost)(struct pp_hwmgr *hwmgr);
352 int (*set_hard_min_dcefclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t clock);
353 int (*set_hard_min_fclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t clock);
354 int (*set_hard_min_gfxclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t clock);
355 int (*set_soft_max_gfxclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t clock);
356 int (*get_asic_baco_capability)(struct pp_hwmgr *hwmgr, bool *cap);
357 int (*get_asic_baco_state)(struct pp_hwmgr *hwmgr, enum BACO_STATE *state);
358 int (*set_asic_baco_state)(struct pp_hwmgr *hwmgr, enum BACO_STATE state);
359 int (*get_ppfeature_status)(struct pp_hwmgr *hwmgr, char *buf);
360 int (*set_ppfeature_status)(struct pp_hwmgr *hwmgr, uint64_t ppfeature_masks);
361 int (*set_mp1_state)(struct pp_hwmgr *hwmgr, enum pp_mp1_state mp1_state);
362 int (*asic_reset)(struct pp_hwmgr *hwmgr, enum SMU_ASIC_RESET_MODE mode);
363 int (*smu_i2c_bus_access)(struct pp_hwmgr *hwmgr, bool aquire);
364 int (*set_df_cstate)(struct pp_hwmgr *hwmgr, enum pp_df_cstate state);
365 int (*set_xgmi_pstate)(struct pp_hwmgr *hwmgr, uint32_t pstate);
366 int (*disable_power_features_for_compute_performance)(struct pp_hwmgr *hwmgr,
368 ssize_t (*get_gpu_metrics)(struct pp_hwmgr *hwmgr, void **table);
371 struct pp_table_func {
372 int (*pptable_init)(struct pp_hwmgr *hw_mgr);
373 int (*pptable_fini)(struct pp_hwmgr *hw_mgr);
374 int (*pptable_get_number_of_vce_state_table_entries)(struct pp_hwmgr *hw_mgr);
375 int (*pptable_get_vce_state_table_entry)(
376 struct pp_hwmgr *hwmgr,
378 struct amd_vce_state *vce_state,
380 unsigned long *flag);
383 union phm_cac_leakage_record {
385 uint16_t Vddc; /* in CI, we use it for StdVoltageHiSidd */
386 uint32_t Leakage; /* in CI, we use it for StdVoltageLoSidd */
395 struct phm_cac_leakage_table {
397 union phm_cac_leakage_record entries[1];
400 struct phm_samu_clock_voltage_dependency_record {
406 struct phm_samu_clock_voltage_dependency_table {
408 struct phm_samu_clock_voltage_dependency_record entries[1];
411 struct phm_cac_tdp_table {
413 uint16_t usConfigurableTDP;
415 uint16_t usBatteryPowerLimit;
416 uint16_t usSmallPowerLimit;
417 uint16_t usLowCACLeakage;
418 uint16_t usHighCACLeakage;
419 uint16_t usMaximumPowerDeliveryLimit;
421 uint16_t usOperatingTempMinLimit;
422 uint16_t usOperatingTempMaxLimit;
423 uint16_t usOperatingTempStep;
424 uint16_t usOperatingTempHyst;
425 uint16_t usDefaultTargetOperatingTemp;
426 uint16_t usTargetOperatingTemp;
427 uint16_t usPowerTuneDataSetID;
428 uint16_t usSoftwareShutdownTemp;
429 uint16_t usClockStretchAmount;
430 uint16_t usTemperatureLimitHotspot;
431 uint16_t usTemperatureLimitLiquid1;
432 uint16_t usTemperatureLimitLiquid2;
433 uint16_t usTemperatureLimitVrVddc;
434 uint16_t usTemperatureLimitVrMvdd;
435 uint16_t usTemperatureLimitPlx;
436 uint8_t ucLiquid1_I2C_address;
437 uint8_t ucLiquid2_I2C_address;
438 uint8_t ucLiquid_I2C_Line;
439 uint8_t ucVr_I2C_address;
440 uint8_t ucVr_I2C_Line;
441 uint8_t ucPlx_I2C_address;
442 uint8_t ucPlx_I2C_Line;
443 uint32_t usBoostPowerLimit;
444 uint8_t ucCKS_LDO_REFSEL;
447 struct phm_tdp_table {
449 uint16_t usConfigurableTDP;
451 uint16_t usBatteryPowerLimit;
452 uint16_t usSmallPowerLimit;
453 uint16_t usLowCACLeakage;
454 uint16_t usHighCACLeakage;
455 uint16_t usMaximumPowerDeliveryLimit;
457 uint16_t usOperatingTempMinLimit;
458 uint16_t usOperatingTempMaxLimit;
459 uint16_t usOperatingTempStep;
460 uint16_t usOperatingTempHyst;
461 uint16_t usDefaultTargetOperatingTemp;
462 uint16_t usTargetOperatingTemp;
463 uint16_t usPowerTuneDataSetID;
464 uint16_t usSoftwareShutdownTemp;
465 uint16_t usClockStretchAmount;
466 uint16_t usTemperatureLimitTedge;
467 uint16_t usTemperatureLimitHotspot;
468 uint16_t usTemperatureLimitLiquid1;
469 uint16_t usTemperatureLimitLiquid2;
470 uint16_t usTemperatureLimitHBM;
471 uint16_t usTemperatureLimitVrVddc;
472 uint16_t usTemperatureLimitVrMvdd;
473 uint16_t usTemperatureLimitPlx;
474 uint8_t ucLiquid1_I2C_address;
475 uint8_t ucLiquid2_I2C_address;
476 uint8_t ucLiquid_I2C_Line;
477 uint8_t ucVr_I2C_address;
478 uint8_t ucVr_I2C_Line;
479 uint8_t ucPlx_I2C_address;
480 uint8_t ucPlx_I2C_Line;
481 uint8_t ucLiquid_I2C_LineSDA;
482 uint8_t ucVr_I2C_LineSDA;
483 uint8_t ucPlx_I2C_LineSDA;
484 uint32_t usBoostPowerLimit;
485 uint16_t usBoostStartTemperature;
486 uint16_t usBoostStopTemperature;
487 uint32_t ulBoostClock;
490 struct phm_ppm_table {
492 uint16_t cpu_core_number;
493 uint32_t platform_tdp;
494 uint32_t small_ac_platform_tdp;
495 uint32_t platform_tdc;
496 uint32_t small_ac_platform_tdc;
499 uint32_t dgpu_ulv_power;
503 struct phm_vq_budgeting_record {
505 uint32_t ulSustainableSOCPowerLimitLow;
506 uint32_t ulSustainableSOCPowerLimitHigh;
507 uint32_t ulMinSclkLow;
508 uint32_t ulMinSclkHigh;
509 uint8_t ucDispConfig;
512 uint32_t ulSustainableSclk;
513 uint32_t ulSustainableCUs;
516 struct phm_vq_budgeting_table {
518 struct phm_vq_budgeting_record entries[1];
521 struct phm_clock_and_voltage_limits {
531 /* Structure to hold PPTable information */
533 struct phm_ppt_v1_information {
534 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk;
535 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_mclk;
536 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_socclk;
537 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dcefclk;
538 struct phm_clock_array *valid_sclk_values;
539 struct phm_clock_array *valid_mclk_values;
540 struct phm_clock_array *valid_socclk_values;
541 struct phm_clock_array *valid_dcefclk_values;
542 struct phm_clock_and_voltage_limits max_clock_voltage_on_dc;
543 struct phm_clock_and_voltage_limits max_clock_voltage_on_ac;
544 struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl;
545 struct phm_ppm_table *ppm_parameter_table;
546 struct phm_cac_tdp_table *cac_dtp_table;
547 struct phm_tdp_table *tdp_table;
548 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_dep_table;
549 struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
550 struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table;
551 struct phm_ppt_v1_voltage_lookup_table *vddmem_lookup_table;
552 struct phm_ppt_v1_pcie_table *pcie_table;
553 struct phm_ppt_v1_gpio_table *gpio_table;
554 uint16_t us_ulv_voltage_offset;
555 uint16_t us_ulv_smnclk_did;
556 uint16_t us_ulv_mp1clk_did;
557 uint16_t us_ulv_gfxclk_bypass;
558 uint16_t us_gfxclk_slew_rate;
559 uint16_t us_min_gfxclk_freq_limit;
562 struct phm_ppt_v2_information {
563 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk;
564 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_mclk;
565 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_socclk;
566 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dcefclk;
567 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_pixclk;
568 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dispclk;
569 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_phyclk;
570 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_dep_table;
572 struct phm_clock_voltage_dependency_table *vddc_dep_on_dalpwrl;
574 struct phm_clock_array *valid_sclk_values;
575 struct phm_clock_array *valid_mclk_values;
576 struct phm_clock_array *valid_socclk_values;
577 struct phm_clock_array *valid_dcefclk_values;
579 struct phm_clock_and_voltage_limits max_clock_voltage_on_dc;
580 struct phm_clock_and_voltage_limits max_clock_voltage_on_ac;
582 struct phm_ppm_table *ppm_parameter_table;
583 struct phm_cac_tdp_table *cac_dtp_table;
584 struct phm_tdp_table *tdp_table;
586 struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
587 struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table;
588 struct phm_ppt_v1_voltage_lookup_table *vddmem_lookup_table;
589 struct phm_ppt_v1_voltage_lookup_table *vddci_lookup_table;
591 struct phm_ppt_v1_pcie_table *pcie_table;
593 uint16_t us_ulv_voltage_offset;
594 uint16_t us_ulv_smnclk_did;
595 uint16_t us_ulv_mp1clk_did;
596 uint16_t us_ulv_gfxclk_bypass;
597 uint16_t us_gfxclk_slew_rate;
598 uint16_t us_min_gfxclk_freq_limit;
600 uint8_t uc_gfx_dpm_voltage_mode;
601 uint8_t uc_soc_dpm_voltage_mode;
602 uint8_t uc_uclk_dpm_voltage_mode;
603 uint8_t uc_uvd_dpm_voltage_mode;
604 uint8_t uc_vce_dpm_voltage_mode;
605 uint8_t uc_mp0_dpm_voltage_mode;
606 uint8_t uc_dcef_dpm_voltage_mode;
609 struct phm_ppt_v3_information
611 uint8_t uc_thermal_controller_type;
613 uint16_t us_small_power_limit1;
614 uint16_t us_small_power_limit2;
615 uint16_t us_boost_power_limit;
617 uint16_t us_od_turbo_power_limit;
618 uint16_t us_od_powersave_power_limit;
619 uint16_t us_software_shutdown_temp;
621 uint32_t *power_saving_clock_max;
622 uint32_t *power_saving_clock_min;
624 uint8_t *od_feature_capabilities;
625 uint32_t *od_settings_max;
626 uint32_t *od_settings_min;
631 struct phm_dynamic_state_info {
632 struct phm_clock_voltage_dependency_table *vddc_dependency_on_sclk;
633 struct phm_clock_voltage_dependency_table *vddci_dependency_on_mclk;
634 struct phm_clock_voltage_dependency_table *vddc_dependency_on_mclk;
635 struct phm_clock_voltage_dependency_table *mvdd_dependency_on_mclk;
636 struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl;
637 struct phm_clock_array *valid_sclk_values;
638 struct phm_clock_array *valid_mclk_values;
639 struct phm_clock_and_voltage_limits max_clock_voltage_on_dc;
640 struct phm_clock_and_voltage_limits max_clock_voltage_on_ac;
641 uint32_t mclk_sclk_ratio;
642 uint32_t sclk_mclk_delta;
643 uint32_t vddc_vddci_delta;
644 uint32_t min_vddc_for_pcie_gen2;
645 struct phm_cac_leakage_table *cac_leakage_table;
646 struct phm_phase_shedding_limits_table *vddc_phase_shed_limits_table;
648 struct phm_vce_clock_voltage_dependency_table
649 *vce_clock_voltage_dependency_table;
650 struct phm_uvd_clock_voltage_dependency_table
651 *uvd_clock_voltage_dependency_table;
652 struct phm_acp_clock_voltage_dependency_table
653 *acp_clock_voltage_dependency_table;
654 struct phm_samu_clock_voltage_dependency_table
655 *samu_clock_voltage_dependency_table;
657 struct phm_ppm_table *ppm_parameter_table;
658 struct phm_cac_tdp_table *cac_dtp_table;
659 struct phm_clock_voltage_dependency_table *vdd_gfx_dependency_on_sclk;
664 uint8_t ucTachometerPulsesPerRevolution;
669 struct pp_advance_fan_control_parameters {
670 uint16_t usTMin; /* The temperature, in 0.01 centigrades, below which we just run at a minimal PWM. */
671 uint16_t usTMed; /* The middle temperature where we change slopes. */
672 uint16_t usTHigh; /* The high temperature for setting the second slope. */
673 uint16_t usPWMMin; /* The minimum PWM value in percent (0.01% increments). */
674 uint16_t usPWMMed; /* The PWM value (in percent) at TMed. */
675 uint16_t usPWMHigh; /* The PWM value at THigh. */
676 uint8_t ucTHyst; /* Temperature hysteresis. Integer. */
677 uint32_t ulCycleDelay; /* The time between two invocations of the fan control routine in microseconds. */
678 uint16_t usTMax; /* The max temperature */
679 uint8_t ucFanControlMode;
680 uint16_t usFanPWMMinLimit;
681 uint16_t usFanPWMMaxLimit;
682 uint16_t usFanPWMStep;
683 uint16_t usDefaultMaxFanPWM;
684 uint16_t usFanOutputSensitivity;
685 uint16_t usDefaultFanOutputSensitivity;
686 uint16_t usMaxFanPWM; /* The max Fan PWM value for Fuzzy Fan Control feature */
687 uint16_t usFanRPMMinLimit; /* Minimum limit range in percentage, need to calculate based on minRPM/MaxRpm */
688 uint16_t usFanRPMMaxLimit; /* Maximum limit range in percentage, usually set to 100% by default */
689 uint16_t usFanRPMStep; /* Step increments/decerements, in percent */
690 uint16_t usDefaultMaxFanRPM; /* The max Fan RPM value for Fuzzy Fan Control feature, default from PPTable */
691 uint16_t usMaxFanRPM; /* The max Fan RPM value for Fuzzy Fan Control feature, user defined */
692 uint16_t usFanCurrentLow; /* Low current */
693 uint16_t usFanCurrentHigh; /* High current */
694 uint16_t usFanRPMLow; /* Low RPM */
695 uint16_t usFanRPMHigh; /* High RPM */
696 uint32_t ulMinFanSCLKAcousticLimit; /* Minimum Fan Controller SCLK Frequency Acoustic Limit. */
697 uint8_t ucTargetTemperature; /* Advanced fan controller target temperature. */
698 uint8_t ucMinimumPWMLimit; /* The minimum PWM that the advanced fan controller can set. This should be set to the highest PWM that will run the fan at its lowest RPM. */
699 uint16_t usFanGainEdge; /* The following is added for Fiji */
700 uint16_t usFanGainHotspot;
701 uint16_t usFanGainLiquid;
702 uint16_t usFanGainVrVddc;
703 uint16_t usFanGainVrMvdd;
704 uint16_t usFanGainPlx;
705 uint16_t usFanGainHbm;
706 uint8_t ucEnableZeroRPM;
707 uint8_t ucFanStopTemperature;
708 uint8_t ucFanStartTemperature;
709 uint32_t ulMaxFanSCLKAcousticLimit; /* Maximum Fan Controller SCLK Frequency Acoustic Limit. */
710 uint32_t ulTargetGfxClk;
711 uint16_t usZeroRPMStartTemperature;
712 uint16_t usZeroRPMStopTemperature;
713 uint16_t usMGpuThrottlingRPMLimit;
716 struct pp_thermal_controller_info {
719 uint8_t ucI2cAddress;
720 uint8_t use_hw_fan_control;
721 struct pp_fan_info fanInfo;
722 struct pp_advance_fan_control_parameters advanceFanControlParameters;
725 struct phm_microcode_version_info {
732 enum PP_TABLE_VERSION {
740 * The main hardware manager structure.
742 #define Workload_Policy_Max 6
746 uint32_t chip_family;
748 uint32_t smu_version;
752 struct mutex smu_lock;
753 struct mutex msg_lock;
755 uint32_t pp_table_version;
757 struct pp_smumgr *smumgr;
758 const void *soft_pp_table;
759 uint32_t soft_pp_table_size;
760 void *hardcode_pp_table;
761 bool need_pp_table_upload;
763 struct amd_vce_state vce_states[AMD_MAX_VCE_LEVELS];
764 uint32_t num_vce_state_tables;
766 enum amd_dpm_forced_level dpm_level;
767 enum amd_dpm_forced_level saved_dpm_level;
768 enum amd_dpm_forced_level request_dpm_level;
769 uint32_t usec_timeout;
771 struct phm_platform_descriptor platform_descriptor;
775 const struct pp_smumgr_func *smumgr_funcs;
778 enum PP_DAL_POWERLEVEL dal_power_level;
779 struct phm_dynamic_state_info dyn_state;
780 const struct pp_hwmgr_func *hwmgr_func;
781 const struct pp_table_func *pptable_func;
783 struct pp_power_state *ps;
785 struct pp_thermal_controller_info thermal_controller;
786 bool fan_ctrl_is_in_default_mode;
787 uint32_t fan_ctrl_default_mode;
788 bool fan_ctrl_enabled;
790 struct phm_microcode_version_info microcode_version_info;
792 struct pp_power_state *current_ps;
793 struct pp_power_state *request_ps;
794 struct pp_power_state *boot_ps;
795 struct pp_power_state *uvd_ps;
796 const struct amd_pp_display_configuration *display_config;
797 uint32_t feature_mask;
801 uint32_t power_profile_mode;
802 uint32_t default_power_profile_mode;
803 uint32_t pstate_sclk;
804 uint32_t pstate_mclk;
806 uint32_t power_limit;
807 uint32_t default_power_limit;
808 uint32_t workload_mask;
809 uint32_t workload_prority[Workload_Policy_Max];
810 uint32_t workload_setting[Workload_Policy_Max];
811 bool gfxoff_state_changed_by_workload;
814 int hwmgr_early_init(struct pp_hwmgr *hwmgr);
815 int hwmgr_sw_init(struct pp_hwmgr *hwmgr);
816 int hwmgr_sw_fini(struct pp_hwmgr *hwmgr);
817 int hwmgr_hw_init(struct pp_hwmgr *hwmgr);
818 int hwmgr_hw_fini(struct pp_hwmgr *hwmgr);
819 int hwmgr_suspend(struct pp_hwmgr *hwmgr);
820 int hwmgr_resume(struct pp_hwmgr *hwmgr);
822 int hwmgr_handle_task(struct pp_hwmgr *hwmgr,
823 enum amd_pp_task task_id,
824 enum amd_pm_state_type *user_state);
827 #define PHM_ENTIRE_REGISTER_MASK 0xFFFFFFFFU
830 #endif /* _HWMGR_H_ */