2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 #ifndef __AMDGPU_SMU_H__
23 #define __AMDGPU_SMU_H__
26 #include "kgd_pp_interface.h"
27 #include "dm_pp_interface.h"
28 #include "dm_pp_smu.h"
29 #include "smu_types.h"
31 #define SMU_THERMAL_MINIMUM_ALERT_TEMP 0
32 #define SMU_THERMAL_MAXIMUM_ALERT_TEMP 255
33 #define SMU_TEMPERATURE_UNITS_PER_CENTIGRADES 1000
34 #define SMU_FW_NAME_LEN 0x24
36 struct smu_hw_power_state {
40 struct smu_power_state;
42 enum smu_state_ui_label {
43 SMU_STATE_UI_LABEL_NONE,
44 SMU_STATE_UI_LABEL_BATTERY,
45 SMU_STATE_UI_TABEL_MIDDLE_LOW,
46 SMU_STATE_UI_LABEL_BALLANCED,
47 SMU_STATE_UI_LABEL_MIDDLE_HIGHT,
48 SMU_STATE_UI_LABEL_PERFORMANCE,
49 SMU_STATE_UI_LABEL_BACO,
52 enum smu_state_classification_flag {
53 SMU_STATE_CLASSIFICATION_FLAG_BOOT = 0x0001,
54 SMU_STATE_CLASSIFICATION_FLAG_THERMAL = 0x0002,
55 SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE = 0x0004,
56 SMU_STATE_CLASSIFICATION_FLAG_RESET = 0x0008,
57 SMU_STATE_CLASSIFICATION_FLAG_FORCED = 0x0010,
58 SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE = 0x0020,
59 SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE = 0x0040,
60 SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE = 0x0080,
61 SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE = 0x0100,
62 SMU_STATE_CLASSIFICATION_FLAG_UVD = 0x0200,
63 SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW = 0x0400,
64 SMU_STATE_CLASSIFICATION_FLAG_ACPI = 0x0800,
65 SMU_STATE_CLASSIFICATION_FLAG_HD2 = 0x1000,
66 SMU_STATE_CLASSIFICATION_FLAG_UVD_HD = 0x2000,
67 SMU_STATE_CLASSIFICATION_FLAG_UVD_SD = 0x4000,
68 SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE = 0x8000,
69 SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE = 0x10000,
70 SMU_STATE_CLASSIFICATION_FLAG_BACO = 0x20000,
71 SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2 = 0x40000,
72 SMU_STATE_CLASSIFICATION_FLAG_ULV = 0x80000,
73 SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC = 0x100000,
76 struct smu_state_classification_block {
77 enum smu_state_ui_label ui_label;
78 enum smu_state_classification_flag flags;
84 struct smu_state_pcie_block {
88 enum smu_refreshrate_source {
89 SMU_REFRESHRATE_SOURCE_EDID,
90 SMU_REFRESHRATE_SOURCE_EXPLICIT
93 struct smu_state_display_block {
94 bool disable_frame_modulation;
95 bool limit_refreshrate;
96 enum smu_refreshrate_source refreshrate_source;
97 int explicit_refreshrate;
98 int edid_refreshrate_index;
99 bool enable_vari_bright;
102 struct smu_state_memroy_block {
108 struct smu_state_software_algorithm_block {
109 bool disable_load_balancing;
110 bool enable_sleep_for_timestamps;
113 struct smu_temperature_range {
116 int edge_emergency_max;
118 int hotspot_crit_max;
119 int hotspot_emergency_max;
122 int mem_emergency_max;
123 int software_shutdown_temp;
126 struct smu_state_validation_block {
127 bool single_display_only;
129 uint8_t supported_power_levels;
132 struct smu_uvd_clocks {
138 * Structure to hold a SMU Power State.
140 struct smu_power_state {
142 struct list_head ordered_list;
143 struct list_head all_states_list;
145 struct smu_state_classification_block classification;
146 struct smu_state_validation_block validation;
147 struct smu_state_pcie_block pcie;
148 struct smu_state_display_block display;
149 struct smu_state_memroy_block memory;
150 struct smu_state_software_algorithm_block software;
151 struct smu_uvd_clocks uvd_clocks;
152 struct smu_hw_power_state hardware;
155 enum smu_power_src_type
159 SMU_POWER_SOURCE_COUNT,
162 enum smu_memory_pool_size
164 SMU_MEMORY_POOL_SIZE_ZERO = 0,
165 SMU_MEMORY_POOL_SIZE_256_MB = 0x10000000,
166 SMU_MEMORY_POOL_SIZE_512_MB = 0x20000000,
167 SMU_MEMORY_POOL_SIZE_1_GB = 0x40000000,
168 SMU_MEMORY_POOL_SIZE_2_GB = 0x80000000,
171 #define SMU_TABLE_INIT(tables, table_id, s, a, d) \
173 tables[table_id].size = s; \
174 tables[table_id].align = a; \
175 tables[table_id].domain = d; \
184 struct amdgpu_bo *bo;
187 enum smu_perf_level_designation {
189 PERF_LEVEL_POWER_CONTAINMENT,
192 struct smu_performance_level {
194 uint32_t memory_clock;
197 uint32_t non_local_mem_freq;
198 uint32_t non_local_mem_width;
201 struct smu_clock_info {
202 uint32_t min_mem_clk;
203 uint32_t max_mem_clk;
204 uint32_t min_eng_clk;
205 uint32_t max_eng_clk;
206 uint32_t min_bus_bandwidth;
207 uint32_t max_bus_bandwidth;
210 struct smu_bios_boot_up_values
225 uint32_t pp_table_id;
226 uint32_t format_revision;
227 uint32_t content_revision;
234 SMU_TABLE_PPTABLE = 0,
235 SMU_TABLE_WATERMARKS,
236 SMU_TABLE_CUSTOM_DPM,
239 SMU_TABLE_AVFS_PSM_DEBUG,
240 SMU_TABLE_AVFS_FUSE_OVERRIDE,
241 SMU_TABLE_PMSTATUSLOG,
242 SMU_TABLE_SMU_METRICS,
243 SMU_TABLE_DRIVER_SMU_CONFIG,
244 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
246 SMU_TABLE_I2C_COMMANDS,
251 struct smu_table_context
253 void *power_play_table;
254 uint32_t power_play_table_size;
255 void *hardcode_pptable;
256 unsigned long metrics_time;
259 void *watermarks_table;
261 void *max_sustainable_clocks;
262 struct smu_bios_boot_up_values boot_values;
263 void *driver_pptable;
264 struct smu_table tables[SMU_TABLE_COUNT];
266 * The driver table is just a staging buffer for
267 * uploading/downloading content from the SMU.
269 * And the table_id for SMU_MSG_TransferTableSmu2Dram/
270 * SMU_MSG_TransferTableDram2Smu instructs SMU
271 * which content driver is interested.
273 struct smu_table driver_table;
274 struct smu_table memory_pool;
275 struct smu_table dummy_read_1_table;
276 uint8_t thermal_controller_type;
278 void *overdrive_table;
279 void *boot_overdrive_table;
281 uint32_t gpu_metrics_table_size;
282 void *gpu_metrics_table;
285 struct smu_dpm_context {
286 uint32_t dpm_context_size;
288 void *golden_dpm_context;
289 bool enable_umd_pstate;
290 enum amd_dpm_forced_level dpm_level;
291 enum amd_dpm_forced_level saved_dpm_level;
292 enum amd_dpm_forced_level requested_dpm_level;
293 struct smu_power_state *dpm_request_power_state;
294 struct smu_power_state *dpm_current_power_state;
295 struct mclock_latency_table *mclk_latency_table;
298 struct smu_power_gate {
303 struct mutex vcn_gate_lock;
304 struct mutex jpeg_gate_lock;
307 struct smu_power_context {
309 uint32_t power_context_size;
310 struct smu_power_gate power_gate;
314 #define SMU_FEATURE_MAX (64)
317 uint32_t feature_num;
318 DECLARE_BITMAP(supported, SMU_FEATURE_MAX);
319 DECLARE_BITMAP(allowed, SMU_FEATURE_MAX);
320 DECLARE_BITMAP(enabled, SMU_FEATURE_MAX);
325 uint32_t engine_clock;
326 uint32_t memory_clock;
327 uint32_t bus_bandwidth;
328 uint32_t engine_clock_in_sr;
330 uint32_t dcef_clock_in_sr;
333 #define MAX_REGULAR_DPM_NUM 16
334 struct mclk_latency_entries {
338 struct mclock_latency_table {
340 struct mclk_latency_entries entries[MAX_REGULAR_DPM_NUM];
352 SMU_BACO_STATE_ENTER = 0,
356 struct smu_baco_context
360 bool platform_support;
363 struct pstates_clk_freq {
369 struct smu_umd_pstate_table {
370 struct pstates_clk_freq gfxclk_pstate;
371 struct pstates_clk_freq socclk_pstate;
372 struct pstates_clk_freq uclk_pstate;
373 struct pstates_clk_freq vclk_pstate;
374 struct pstates_clk_freq dclk_pstate;
377 struct cmn2asic_msg_mapping {
383 struct cmn2asic_mapping {
388 #define WORKLOAD_POLICY_MAX 7
391 struct amdgpu_device *adev;
392 struct amdgpu_irq_src irq_source;
394 const struct pptable_funcs *ppt_funcs;
395 const struct cmn2asic_msg_mapping *message_map;
396 const struct cmn2asic_mapping *clock_map;
397 const struct cmn2asic_mapping *feature_map;
398 const struct cmn2asic_mapping *table_map;
399 const struct cmn2asic_mapping *pwr_src_map;
400 const struct cmn2asic_mapping *workload_map;
402 struct mutex sensor_lock;
403 struct mutex metrics_lock;
404 struct mutex message_lock;
407 struct smu_table_context smu_table;
408 struct smu_dpm_context smu_dpm;
409 struct smu_power_context smu_power;
410 struct smu_feature smu_feature;
411 struct amd_pp_display_configuration *display_config;
412 struct smu_baco_context smu_baco;
413 struct smu_temperature_range thermal_range;
415 #if defined(CONFIG_DEBUG_FS)
416 struct dentry *debugfs_sclk;
419 struct smu_umd_pstate_table pstate_table;
420 uint32_t pstate_sclk;
421 uint32_t pstate_mclk;
424 uint32_t current_power_limit;
425 uint32_t max_power_limit;
428 uint32_t ppt_offset_bytes;
429 uint32_t ppt_size_bytes;
430 uint8_t *ppt_start_addr;
432 bool support_power_containment;
433 bool disable_watermark;
435 #define WATERMARKS_EXIST (1 << 0)
436 #define WATERMARKS_LOADED (1 << 1)
437 uint32_t watermarks_bitmap;
438 uint32_t hard_min_uclk_req_from_dal;
439 bool disable_uclk_switch;
441 uint32_t workload_mask;
442 uint32_t workload_prority[WORKLOAD_POLICY_MAX];
443 uint32_t workload_setting[WORKLOAD_POLICY_MAX];
444 uint32_t power_profile_mode;
445 uint32_t default_power_profile_mode;
449 uint32_t smc_driver_if_version;
450 uint32_t smc_fw_if_version;
451 uint32_t smc_fw_version;
453 bool uploading_custom_pp_table;
454 bool dc_controlled_by_gpio;
456 struct work_struct throttling_logging_work;
457 atomic64_t throttle_int_counter;
458 struct work_struct interrupt_work;
460 unsigned fan_max_rpm;
461 unsigned manual_fan_speed_rpm;
463 uint32_t gfx_default_hard_min_freq;
464 uint32_t gfx_default_soft_max_freq;
465 uint32_t gfx_actual_hard_min_freq;
466 uint32_t gfx_actual_soft_max_freq;
471 struct pptable_funcs {
472 int (*run_btc)(struct smu_context *smu);
473 int (*get_allowed_feature_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
474 enum amd_pm_state_type (*get_current_power_state)(struct smu_context *smu);
475 int (*set_default_dpm_table)(struct smu_context *smu);
476 int (*set_power_state)(struct smu_context *smu);
477 int (*populate_umd_state_clk)(struct smu_context *smu);
478 int (*print_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf);
479 int (*force_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask);
480 int (*od_edit_dpm_table)(struct smu_context *smu,
481 enum PP_OD_DPM_TABLE_COMMAND type,
482 long *input, uint32_t size);
483 int (*get_clock_by_type_with_latency)(struct smu_context *smu,
484 enum smu_clk_type clk_type,
486 pp_clock_levels_with_latency
488 int (*get_power_profile_mode)(struct smu_context *smu, char *buf);
489 int (*set_power_profile_mode)(struct smu_context *smu, long *input, uint32_t size);
490 int (*dpm_set_vcn_enable)(struct smu_context *smu, bool enable);
491 int (*dpm_set_jpeg_enable)(struct smu_context *smu, bool enable);
492 int (*read_sensor)(struct smu_context *smu, enum amd_pp_sensors sensor,
493 void *data, uint32_t *size);
494 int (*pre_display_config_changed)(struct smu_context *smu);
495 int (*display_config_changed)(struct smu_context *smu);
496 int (*apply_clocks_adjust_rules)(struct smu_context *smu);
497 int (*notify_smc_display_config)(struct smu_context *smu);
498 bool (*is_dpm_running)(struct smu_context *smu);
499 int (*get_fan_speed_rpm)(struct smu_context *smu, uint32_t *speed);
500 int (*set_watermarks_table)(struct smu_context *smu,
501 struct pp_smu_wm_range_sets *clock_ranges);
502 int (*get_thermal_temperature_range)(struct smu_context *smu, struct smu_temperature_range *range);
503 int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states);
504 int (*set_default_od_settings)(struct smu_context *smu);
505 int (*set_performance_level)(struct smu_context *smu, enum amd_dpm_forced_level level);
506 int (*display_disable_memory_clock_switch)(struct smu_context *smu, bool disable_memory_clock_switch);
507 void (*dump_pptable)(struct smu_context *smu);
508 int (*get_power_limit)(struct smu_context *smu);
509 int (*set_df_cstate)(struct smu_context *smu, enum pp_df_cstate state);
510 int (*allow_xgmi_power_down)(struct smu_context *smu, bool en);
511 int (*update_pcie_parameters)(struct smu_context *smu, uint32_t pcie_gen_cap, uint32_t pcie_width_cap);
512 int (*i2c_init)(struct smu_context *smu, struct i2c_adapter *control);
513 void (*i2c_fini)(struct smu_context *smu, struct i2c_adapter *control);
514 void (*get_unique_id)(struct smu_context *smu);
515 int (*get_dpm_clock_table)(struct smu_context *smu, struct dpm_clocks *clock_table);
516 int (*init_microcode)(struct smu_context *smu);
517 int (*load_microcode)(struct smu_context *smu);
518 void (*fini_microcode)(struct smu_context *smu);
519 int (*init_smc_tables)(struct smu_context *smu);
520 int (*fini_smc_tables)(struct smu_context *smu);
521 int (*init_power)(struct smu_context *smu);
522 int (*fini_power)(struct smu_context *smu);
523 int (*check_fw_status)(struct smu_context *smu);
524 int (*setup_pptable)(struct smu_context *smu);
525 int (*get_vbios_bootup_values)(struct smu_context *smu);
526 int (*check_fw_version)(struct smu_context *smu);
527 int (*powergate_sdma)(struct smu_context *smu, bool gate);
528 int (*set_gfx_cgpg)(struct smu_context *smu, bool enable);
529 int (*write_pptable)(struct smu_context *smu);
530 int (*set_driver_table_location)(struct smu_context *smu);
531 int (*set_tool_table_location)(struct smu_context *smu);
532 int (*notify_memory_pool_location)(struct smu_context *smu);
533 int (*system_features_control)(struct smu_context *smu, bool en);
534 int (*send_smc_msg_with_param)(struct smu_context *smu,
535 enum smu_message_type msg, uint32_t param, uint32_t *read_arg);
536 int (*send_smc_msg)(struct smu_context *smu,
537 enum smu_message_type msg,
539 int (*init_display_count)(struct smu_context *smu, uint32_t count);
540 int (*set_allowed_mask)(struct smu_context *smu);
541 int (*get_enabled_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
542 int (*feature_is_enabled)(struct smu_context *smu, enum smu_feature_mask mask);
543 int (*disable_all_features_with_exception)(struct smu_context *smu, enum smu_feature_mask mask);
544 int (*notify_display_change)(struct smu_context *smu);
545 int (*set_power_limit)(struct smu_context *smu, uint32_t n);
546 int (*init_max_sustainable_clocks)(struct smu_context *smu);
547 int (*enable_thermal_alert)(struct smu_context *smu);
548 int (*disable_thermal_alert)(struct smu_context *smu);
549 int (*set_min_dcef_deep_sleep)(struct smu_context *smu, uint32_t clk);
550 int (*display_clock_voltage_request)(struct smu_context *smu, struct
551 pp_display_clock_request
553 uint32_t (*get_fan_control_mode)(struct smu_context *smu);
554 int (*set_fan_control_mode)(struct smu_context *smu, uint32_t mode);
555 int (*set_fan_speed_rpm)(struct smu_context *smu, uint32_t speed);
556 int (*set_xgmi_pstate)(struct smu_context *smu, uint32_t pstate);
557 int (*gfx_off_control)(struct smu_context *smu, bool enable);
558 uint32_t (*get_gfx_off_status)(struct smu_context *smu);
559 int (*register_irq_handler)(struct smu_context *smu);
560 int (*set_azalia_d3_pme)(struct smu_context *smu);
561 int (*get_max_sustainable_clocks_by_dc)(struct smu_context *smu, struct pp_smu_nv_clock_table *max_clocks);
562 bool (*baco_is_support)(struct smu_context *smu);
563 enum smu_baco_state (*baco_get_state)(struct smu_context *smu);
564 int (*baco_set_state)(struct smu_context *smu, enum smu_baco_state state);
565 int (*baco_enter)(struct smu_context *smu);
566 int (*baco_exit)(struct smu_context *smu);
567 bool (*mode1_reset_is_support)(struct smu_context *smu);
568 int (*mode1_reset)(struct smu_context *smu);
569 int (*mode2_reset)(struct smu_context *smu);
570 int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max);
571 int (*set_soft_freq_limited_range)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max);
572 int (*set_power_source)(struct smu_context *smu, enum smu_power_src_type power_src);
573 void (*log_thermal_throttling_event)(struct smu_context *smu);
574 size_t (*get_pp_feature_mask)(struct smu_context *smu, char *buf);
575 int (*set_pp_feature_mask)(struct smu_context *smu, uint64_t new_mask);
576 ssize_t (*get_gpu_metrics)(struct smu_context *smu, void **table);
577 int (*enable_mgpu_fan_boost)(struct smu_context *smu);
578 int (*gfx_ulv_control)(struct smu_context *smu, bool enablement);
579 int (*deep_sleep_control)(struct smu_context *smu, bool enablement);
580 int (*get_fan_parameters)(struct smu_context *smu);
581 int (*post_init)(struct smu_context *smu);
582 void (*interrupt_work)(struct smu_context *smu);
583 int (*gpo_control)(struct smu_context *smu, bool enablement);
584 int (*gfx_state_change_set)(struct smu_context *smu, uint32_t state);
585 int (*set_fine_grain_gfx_freq_parameters)(struct smu_context *smu);
597 METRICS_CURR_DCEFCLK,
598 METRICS_AVERAGE_GFXCLK,
599 METRICS_AVERAGE_SOCCLK,
600 METRICS_AVERAGE_FCLK,
601 METRICS_AVERAGE_UCLK,
602 METRICS_AVERAGE_VCLK,
603 METRICS_AVERAGE_DCLK,
604 METRICS_AVERAGE_GFXACTIVITY,
605 METRICS_AVERAGE_MEMACTIVITY,
606 METRICS_AVERAGE_VCNACTIVITY,
607 METRICS_AVERAGE_SOCKETPOWER,
608 METRICS_TEMPERATURE_EDGE,
609 METRICS_TEMPERATURE_HOTSPOT,
610 METRICS_TEMPERATURE_MEM,
611 METRICS_TEMPERATURE_VRGFX,
612 METRICS_TEMPERATURE_VRSOC,
613 METRICS_TEMPERATURE_VRMEM,
614 METRICS_THROTTLER_STATUS,
615 METRICS_CURR_FANSPEED,
618 enum smu_cmn2asic_mapping_type {
619 CMN2ASIC_MAPPING_MSG,
620 CMN2ASIC_MAPPING_CLK,
621 CMN2ASIC_MAPPING_FEATURE,
622 CMN2ASIC_MAPPING_TABLE,
623 CMN2ASIC_MAPPING_PWR,
624 CMN2ASIC_MAPPING_WORKLOAD,
627 #define MSG_MAP(msg, index, valid_in_vf) \
628 [SMU_MSG_##msg] = {1, (index), (valid_in_vf)}
630 #define CLK_MAP(clk, index) \
631 [SMU_##clk] = {1, (index)}
633 #define FEA_MAP(fea) \
634 [SMU_FEATURE_##fea##_BIT] = {1, FEATURE_##fea##_BIT}
636 #define TAB_MAP(tab) \
637 [SMU_TABLE_##tab] = {1, TABLE_##tab}
639 #define TAB_MAP_VALID(tab) \
640 [SMU_TABLE_##tab] = {1, TABLE_##tab}
642 #define TAB_MAP_INVALID(tab) \
643 [SMU_TABLE_##tab] = {0, TABLE_##tab}
645 #define PWR_MAP(tab) \
646 [SMU_POWER_SOURCE_##tab] = {1, POWER_SOURCE_##tab}
648 #define WORKLOAD_MAP(profile, workload) \
649 [profile] = {1, (workload)}
651 #if !defined(SWSMU_CODE_LAYER_L2) && !defined(SWSMU_CODE_LAYER_L3) && !defined(SWSMU_CODE_LAYER_L4)
652 int smu_load_microcode(struct smu_context *smu);
654 int smu_check_fw_status(struct smu_context *smu);
656 int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled);
658 int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed);
660 int smu_get_power_limit(struct smu_context *smu,
664 int smu_set_power_limit(struct smu_context *smu, uint32_t limit);
665 int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf);
667 int smu_od_edit_dpm_table(struct smu_context *smu,
668 enum PP_OD_DPM_TABLE_COMMAND type,
669 long *input, uint32_t size);
671 int smu_read_sensor(struct smu_context *smu,
672 enum amd_pp_sensors sensor,
673 void *data, uint32_t *size);
674 int smu_get_power_profile_mode(struct smu_context *smu, char *buf);
676 int smu_set_power_profile_mode(struct smu_context *smu,
680 int smu_get_fan_control_mode(struct smu_context *smu);
681 int smu_set_fan_control_mode(struct smu_context *smu, int value);
682 int smu_get_fan_speed_percent(struct smu_context *smu, uint32_t *speed);
683 int smu_set_fan_speed_percent(struct smu_context *smu, uint32_t speed);
684 int smu_get_fan_speed_rpm(struct smu_context *smu, uint32_t *speed);
686 int smu_set_deep_sleep_dcefclk(struct smu_context *smu, int clk);
688 int smu_get_clock_by_type_with_latency(struct smu_context *smu,
689 enum smu_clk_type clk_type,
690 struct pp_clock_levels_with_latency *clocks);
692 int smu_display_clock_voltage_request(struct smu_context *smu,
693 struct pp_display_clock_request *clock_req);
694 int smu_display_disable_memory_clock_switch(struct smu_context *smu, bool disable_memory_clock_switch);
696 int smu_set_xgmi_pstate(struct smu_context *smu,
699 int smu_set_azalia_d3_pme(struct smu_context *smu);
701 bool smu_baco_is_support(struct smu_context *smu);
703 int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state);
705 int smu_baco_enter(struct smu_context *smu);
706 int smu_baco_exit(struct smu_context *smu);
708 bool smu_mode1_reset_is_support(struct smu_context *smu);
709 int smu_mode1_reset(struct smu_context *smu);
710 int smu_mode2_reset(struct smu_context *smu);
712 extern const struct amd_ip_funcs smu_ip_funcs;
714 extern const struct amdgpu_ip_block_version smu_v11_0_ip_block;
715 extern const struct amdgpu_ip_block_version smu_v12_0_ip_block;
717 bool is_support_sw_smu(struct amdgpu_device *adev);
718 int smu_reset(struct smu_context *smu);
719 int smu_sys_get_pp_table(struct smu_context *smu, void **table);
720 int smu_sys_set_pp_table(struct smu_context *smu, void *buf, size_t size);
721 int smu_get_power_num_states(struct smu_context *smu, struct pp_states_info *state_info);
722 enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu);
723 int smu_write_watermarks_table(struct smu_context *smu);
724 int smu_set_watermarks_for_clock_ranges(
725 struct smu_context *smu,
726 struct pp_smu_wm_range_sets *clock_ranges);
728 /* smu to display interface */
729 extern int smu_display_configuration_change(struct smu_context *smu, const
730 struct amd_pp_display_configuration
732 extern int smu_dpm_set_power_gate(struct smu_context *smu,uint32_t block_type, bool gate);
733 extern int smu_handle_task(struct smu_context *smu,
734 enum amd_dpm_forced_level level,
735 enum amd_pp_task task_id,
737 int smu_switch_power_profile(struct smu_context *smu,
738 enum PP_SMC_POWER_PROFILE type,
740 int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
741 uint32_t *min, uint32_t *max);
742 int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
743 uint32_t min, uint32_t max);
744 enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu);
745 int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level);
746 int smu_set_display_count(struct smu_context *smu, uint32_t count);
747 int smu_set_ac_dc(struct smu_context *smu);
748 size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf);
749 int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask);
750 int smu_force_clk_levels(struct smu_context *smu,
751 enum smu_clk_type clk_type,
753 int smu_set_mp1_state(struct smu_context *smu,
754 enum pp_mp1_state mp1_state);
755 int smu_set_df_cstate(struct smu_context *smu,
756 enum pp_df_cstate state);
757 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en);
759 int smu_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
760 struct pp_smu_nv_clock_table *max_clocks);
762 int smu_get_uclk_dpm_states(struct smu_context *smu,
763 unsigned int *clock_values_in_khz,
764 unsigned int *num_states);
766 int smu_get_dpm_clock_table(struct smu_context *smu,
767 struct dpm_clocks *clock_table);
769 int smu_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value);
771 ssize_t smu_sys_get_gpu_metrics(struct smu_context *smu, void **table);
773 int smu_enable_mgpu_fan_boost(struct smu_context *smu);
774 int smu_gfx_state_change_set(struct smu_context *smu, uint32_t state);