drivers/gpu/drm/amd/pm/amdgpu_pm.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Rafał Miłecki <zajec5@gmail.com>
  23  *          Alex Deucher <alexdeucher@gmail.com>
  24  */
  25
  26 #include "amdgpu.h"
  27 #include "amdgpu_drv.h"
  28 #include "amdgpu_pm.h"
  29 #include "amdgpu_dpm.h"
  30 #include "atom.h"
  31 #include <linux/pci.h>
  32 #include <linux/hwmon.h>
  33 #include <linux/hwmon-sysfs.h>
  34 #include <linux/nospec.h>
  35 #include <linux/pm_runtime.h>
  36 #include <asm/processor.h>
  37 #include "hwmgr.h"
  38
  39 static const struct cg_flag_name clocks[] = {
  40         {AMD_CG_SUPPORT_GFX_FGCG, "Graphics Fine Grain Clock Gating"},
  41         {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"},
  42         {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"},
  43         {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"},
  44         {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"},
  45         {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"},
  46         {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"},
  47         {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"},
  48         {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"},
  49         {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"},
  50         {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"},
  51         {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"},
  52         {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"},
  53         {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"},
  54         {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"},
  55         {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"},
  56         {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"},
  57         {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"},
  58         {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"},
  59         {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"},
  60         {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"},
  61         {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"},
  62         {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"},
  63         {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},
  64         {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"},
  65         {AMD_CG_SUPPORT_VCN_MGCG, "VCN Medium Grain Clock Gating"},
  66         {AMD_CG_SUPPORT_HDP_DS, "Host Data Path Deep Sleep"},
  67         {AMD_CG_SUPPORT_HDP_SD, "Host Data Path Shutdown"},
  68         {AMD_CG_SUPPORT_IH_CG, "Interrupt Handler Clock Gating"},
  69         {AMD_CG_SUPPORT_JPEG_MGCG, "JPEG Medium Grain Clock Gating"},
  70
  71         {AMD_CG_SUPPORT_ATHUB_MGCG, "Address Translation Hub Medium Grain Clock Gating"},
  72         {AMD_CG_SUPPORT_ATHUB_LS, "Address Translation Hub Light Sleep"},
  73         {0, NULL},
  74 };
  75
  76 static const struct hwmon_temp_label {
  77         enum PP_HWMON_TEMP channel;
  78         const char *label;
  79 } temp_label[] = {
  80         {PP_TEMP_EDGE, "edge"},
  81         {PP_TEMP_JUNCTION, "junction"},
  82         {PP_TEMP_MEM, "mem"},
  83 };
  84
  85 /**
  86  * DOC: power_dpm_state
  87  *
  88  * The power_dpm_state file is a legacy interface and is only provided for
  89  * backwards compatibility. The amdgpu driver provides a sysfs API for adjusting
  90  * certain power related parameters.  The file power_dpm_state is used for this.
  91  * It accepts the following arguments:
  92  *
  93  * - battery
  94  *
  95  * - balanced
  96  *
  97  * - performance
  98  *
  99  * battery
 100  *
 101  * On older GPUs, the vbios provided a special power state for battery
 102  * operation.  Selecting battery switched to this state.  This is no
 103  * longer provided on newer GPUs so the option does nothing in that case.
 104  *
 105  * balanced
 106  *
 107  * On older GPUs, the vbios provided a special power state for balanced
 108  * operation.  Selecting balanced switched to this state.  This is no
 109  * longer provided on newer GPUs so the option does nothing in that case.
 110  *
 111  * performance
 112  *
 113  * On older GPUs, the vbios provided a special power state for performance
 114  * operation.  Selecting performance switched to this state.  This is no
 115  * longer provided on newer GPUs so the option does nothing in that case.
 116  *
 117  */
 118
 119 static ssize_t amdgpu_get_power_dpm_state(struct device *dev,
 120                                           struct device_attribute *attr,
 121                                           char *buf)
 122 {
 123         struct drm_device *ddev = dev_get_drvdata(dev);
 124         struct amdgpu_device *adev = drm_to_adev(ddev);
 125         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 126         enum amd_pm_state_type pm;
 127         int ret;
 128
 129         if (amdgpu_in_reset(adev))
 130                 return -EPERM;
 131         if (adev->in_suspend && !adev->in_runpm)
 132                 return -EPERM;
 133
 134         ret = pm_runtime_get_sync(ddev->dev);
 135         if (ret < 0) {
 136                 pm_runtime_put_autosuspend(ddev->dev);
 137                 return ret;
 138         }
 139
 140         if (pp_funcs->get_current_power_state) {
 141                 pm = amdgpu_dpm_get_current_power_state(adev);
 142         } else {
 143                 pm = adev->pm.dpm.user_state;
 144         }
 145
 146         pm_runtime_mark_last_busy(ddev->dev);
 147         pm_runtime_put_autosuspend(ddev->dev);
 148
 149         return sysfs_emit(buf, "%s\n",
 150                           (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
 151                           (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
 152 }
 153
 154 static ssize_t amdgpu_set_power_dpm_state(struct device *dev,
 155                                           struct device_attribute *attr,
 156                                           const char *buf,
 157                                           size_t count)
 158 {
 159         struct drm_device *ddev = dev_get_drvdata(dev);
 160         struct amdgpu_device *adev = drm_to_adev(ddev);
 161         enum amd_pm_state_type  state;
 162         int ret;
 163
 164         if (amdgpu_in_reset(adev))
 165                 return -EPERM;
 166         if (adev->in_suspend && !adev->in_runpm)
 167                 return -EPERM;
 168
 169         if (strncmp("battery", buf, strlen("battery")) == 0)
 170                 state = POWER_STATE_TYPE_BATTERY;
 171         else if (strncmp("balanced", buf, strlen("balanced")) == 0)
 172                 state = POWER_STATE_TYPE_BALANCED;
 173         else if (strncmp("performance", buf, strlen("performance")) == 0)
 174                 state = POWER_STATE_TYPE_PERFORMANCE;
 175         else
 176                 return -EINVAL;
 177
 178         ret = pm_runtime_get_sync(ddev->dev);
 179         if (ret < 0) {
 180                 pm_runtime_put_autosuspend(ddev->dev);
 181                 return ret;
 182         }
 183
 184         if (is_support_sw_smu(adev)) {
 185                 mutex_lock(&adev->pm.mutex);
 186                 adev->pm.dpm.user_state = state;
 187                 mutex_unlock(&adev->pm.mutex);
 188         } else if (adev->powerplay.pp_funcs->dispatch_tasks) {
 189                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_ENABLE_USER_STATE, &state);
 190         } else {
 191                 mutex_lock(&adev->pm.mutex);
 192                 adev->pm.dpm.user_state = state;
 193                 mutex_unlock(&adev->pm.mutex);
 194
 195                 amdgpu_pm_compute_clocks(adev);
 196         }
 197         pm_runtime_mark_last_busy(ddev->dev);
 198         pm_runtime_put_autosuspend(ddev->dev);
 199
 200         return count;
 201 }
 202
 203
 204 /**
 205  * DOC: power_dpm_force_performance_level
 206  *
 207  * The amdgpu driver provides a sysfs API for adjusting certain power
 208  * related parameters.  The file power_dpm_force_performance_level is
 209  * used for this.  It accepts the following arguments:
 210  *
 211  * - auto
 212  *
 213  * - low
 214  *
 215  * - high
 216  *
 217  * - manual
 218  *
 219  * - profile_standard
 220  *
 221  * - profile_min_sclk
 222  *
 223  * - profile_min_mclk
 224  *
 225  * - profile_peak
 226  *
 227  * auto
 228  *
 229  * When auto is selected, the driver will attempt to dynamically select
 230  * the optimal power profile for current conditions in the driver.
 231  *
 232  * low
 233  *
 234  * When low is selected, the clocks are forced to the lowest power state.
 235  *
 236  * high
 237  *
 238  * When high is selected, the clocks are forced to the highest power state.
 239  *
 240  * manual
 241  *
 242  * When manual is selected, the user can manually adjust which power states
 243  * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk,
 244  * and pp_dpm_pcie files and adjust the power state transition heuristics
 245  * via the pp_power_profile_mode sysfs file.
 246  *
 247  * profile_standard
 248  * profile_min_sclk
 249  * profile_min_mclk
 250  * profile_peak
 251  *
 252  * When the profiling modes are selected, clock and power gating are
 253  * disabled and the clocks are set for different profiling cases. This
 254  * mode is recommended for profiling specific work loads where you do
 255  * not want clock or power gating for clock fluctuation to interfere
 256  * with your results. profile_standard sets the clocks to a fixed clock
 257  * level which varies from asic to asic.  profile_min_sclk forces the sclk
 258  * to the lowest level.  profile_min_mclk forces the mclk to the lowest level.
 259  * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels.
 260  *
 261  */
 262
 263 static ssize_t amdgpu_get_power_dpm_force_performance_level(struct device *dev,
 264                                                             struct device_attribute *attr,
 265                                                             char *buf)
 266 {
 267         struct drm_device *ddev = dev_get_drvdata(dev);
 268         struct amdgpu_device *adev = drm_to_adev(ddev);
 269         enum amd_dpm_forced_level level = 0xff;
 270         int ret;
 271
 272         if (amdgpu_in_reset(adev))
 273                 return -EPERM;
 274         if (adev->in_suspend && !adev->in_runpm)
 275                 return -EPERM;
 276
 277         ret = pm_runtime_get_sync(ddev->dev);
 278         if (ret < 0) {
 279                 pm_runtime_put_autosuspend(ddev->dev);
 280                 return ret;
 281         }
 282
 283         if (adev->powerplay.pp_funcs->get_performance_level)
 284                 level = amdgpu_dpm_get_performance_level(adev);
 285         else
 286                 level = adev->pm.dpm.forced_level;
 287
 288         pm_runtime_mark_last_busy(ddev->dev);
 289         pm_runtime_put_autosuspend(ddev->dev);
 290
 291         return sysfs_emit(buf, "%s\n",
 292                           (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
 293                           (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
 294                           (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
 295                           (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" :
 296                           (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" :
 297                           (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" :
 298                           (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" :
 299                           (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" :
 300                           (level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) ? "perf_determinism" :
 301                           "unknown");
 302 }
 303
 304 static ssize_t amdgpu_set_power_dpm_force_performance_level(struct device *dev,
 305                                                             struct device_attribute *attr,
 306                                                             const char *buf,
 307                                                             size_t count)
 308 {
 309         struct drm_device *ddev = dev_get_drvdata(dev);
 310         struct amdgpu_device *adev = drm_to_adev(ddev);
 311         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 312         enum amd_dpm_forced_level level;
 313         enum amd_dpm_forced_level current_level = 0xff;
 314         int ret = 0;
 315
 316         if (amdgpu_in_reset(adev))
 317                 return -EPERM;
 318         if (adev->in_suspend && !adev->in_runpm)
 319                 return -EPERM;
 320
 321         if (strncmp("low", buf, strlen("low")) == 0) {
 322                 level = AMD_DPM_FORCED_LEVEL_LOW;
 323         } else if (strncmp("high", buf, strlen("high")) == 0) {
 324                 level = AMD_DPM_FORCED_LEVEL_HIGH;
 325         } else if (strncmp("auto", buf, strlen("auto")) == 0) {
 326                 level = AMD_DPM_FORCED_LEVEL_AUTO;
 327         } else if (strncmp("manual", buf, strlen("manual")) == 0) {
 328                 level = AMD_DPM_FORCED_LEVEL_MANUAL;
 329         } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) {
 330                 level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT;
 331         } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) {
 332                 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD;
 333         } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) {
 334                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK;
 335         } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) {
 336                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK;
 337         } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) {
 338                 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
 339         } else if (strncmp("perf_determinism", buf, strlen("perf_determinism")) == 0) {
 340                 level = AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM;
 341         }  else {
 342                 return -EINVAL;
 343         }
 344
 345         ret = pm_runtime_get_sync(ddev->dev);
 346         if (ret < 0) {
 347                 pm_runtime_put_autosuspend(ddev->dev);
 348                 return ret;
 349         }
 350
 351         if (pp_funcs->get_performance_level)
 352                 current_level = amdgpu_dpm_get_performance_level(adev);
 353
 354         if (current_level == level) {
 355                 pm_runtime_mark_last_busy(ddev->dev);
 356                 pm_runtime_put_autosuspend(ddev->dev);
 357                 return count;
 358         }
 359
 360         if (adev->asic_type == CHIP_RAVEN) {
 361                 if (!(adev->apu_flags & AMD_APU_IS_RAVEN2)) {
 362                         if (current_level != AMD_DPM_FORCED_LEVEL_MANUAL && level == AMD_DPM_FORCED_LEVEL_MANUAL)
 363                                 amdgpu_gfx_off_ctrl(adev, false);
 364                         else if (current_level == AMD_DPM_FORCED_LEVEL_MANUAL && level != AMD_DPM_FORCED_LEVEL_MANUAL)
 365                                 amdgpu_gfx_off_ctrl(adev, true);
 366                 }
 367         }
 368
 369         /* profile_exit setting is valid only when current mode is in profile mode */
 370         if (!(current_level & (AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
 371             AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
 372             AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
 373             AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)) &&
 374             (level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)) {
 375                 pr_err("Currently not in any profile mode!\n");
 376                 pm_runtime_mark_last_busy(ddev->dev);
 377                 pm_runtime_put_autosuspend(ddev->dev);
 378                 return -EINVAL;
 379         }
 380
 381         if (pp_funcs->force_performance_level) {
 382                 mutex_lock(&adev->pm.mutex);
 383                 if (adev->pm.dpm.thermal_active) {
 384                         mutex_unlock(&adev->pm.mutex);
 385                         pm_runtime_mark_last_busy(ddev->dev);
 386                         pm_runtime_put_autosuspend(ddev->dev);
 387                         return -EINVAL;
 388                 }
 389                 ret = amdgpu_dpm_force_performance_level(adev, level);
 390                 if (ret) {
 391                         mutex_unlock(&adev->pm.mutex);
 392                         pm_runtime_mark_last_busy(ddev->dev);
 393                         pm_runtime_put_autosuspend(ddev->dev);
 394                         return -EINVAL;
 395                 } else {
 396                         adev->pm.dpm.forced_level = level;
 397                 }
 398                 mutex_unlock(&adev->pm.mutex);
 399         }
 400         pm_runtime_mark_last_busy(ddev->dev);
 401         pm_runtime_put_autosuspend(ddev->dev);
 402
 403         return count;
 404 }
 405
 406 static ssize_t amdgpu_get_pp_num_states(struct device *dev,
 407                 struct device_attribute *attr,
 408                 char *buf)
 409 {
 410         struct drm_device *ddev = dev_get_drvdata(dev);
 411         struct amdgpu_device *adev = drm_to_adev(ddev);
 412         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 413         struct pp_states_info data;
 414         int i, buf_len, ret;
 415
 416         if (amdgpu_in_reset(adev))
 417                 return -EPERM;
 418         if (adev->in_suspend && !adev->in_runpm)
 419                 return -EPERM;
 420
 421         ret = pm_runtime_get_sync(ddev->dev);
 422         if (ret < 0) {
 423                 pm_runtime_put_autosuspend(ddev->dev);
 424                 return ret;
 425         }
 426
 427         if (pp_funcs->get_pp_num_states) {
 428                 amdgpu_dpm_get_pp_num_states(adev, &data);
 429         } else {
 430                 memset(&data, 0, sizeof(data));
 431         }
 432
 433         pm_runtime_mark_last_busy(ddev->dev);
 434         pm_runtime_put_autosuspend(ddev->dev);
 435
 436         buf_len = snprintf(buf, PAGE_SIZE, "states: %d\n", data.nums);
 437         for (i = 0; i < data.nums; i++)
 438                 buf_len += snprintf(buf + buf_len, PAGE_SIZE, "%d %s\n", i,
 439                                 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
 440                                 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
 441                                 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
 442                                 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default");
 443
 444         return buf_len;
 445 }
 446
 447 static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
 448                 struct device_attribute *attr,
 449                 char *buf)
 450 {
 451         struct drm_device *ddev = dev_get_drvdata(dev);
 452         struct amdgpu_device *adev = drm_to_adev(ddev);
 453         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 454         struct pp_states_info data = {0};
 455         enum amd_pm_state_type pm = 0;
 456         int i = 0, ret = 0;
 457
 458         if (amdgpu_in_reset(adev))
 459                 return -EPERM;
 460         if (adev->in_suspend && !adev->in_runpm)
 461                 return -EPERM;
 462
 463         ret = pm_runtime_get_sync(ddev->dev);
 464         if (ret < 0) {
 465                 pm_runtime_put_autosuspend(ddev->dev);
 466                 return ret;
 467         }
 468
 469         if (pp_funcs->get_current_power_state
 470                  && pp_funcs->get_pp_num_states) {
 471                 pm = amdgpu_dpm_get_current_power_state(adev);
 472                 amdgpu_dpm_get_pp_num_states(adev, &data);
 473         }
 474
 475         pm_runtime_mark_last_busy(ddev->dev);
 476         pm_runtime_put_autosuspend(ddev->dev);
 477
 478         for (i = 0; i < data.nums; i++) {
 479                 if (pm == data.states[i])
 480                         break;
 481         }
 482
 483         if (i == data.nums)
 484                 i = -EINVAL;
 485
 486         return sysfs_emit(buf, "%d\n", i);
 487 }
 488
 489 static ssize_t amdgpu_get_pp_force_state(struct device *dev,
 490                 struct device_attribute *attr,
 491                 char *buf)
 492 {
 493         struct drm_device *ddev = dev_get_drvdata(dev);
 494         struct amdgpu_device *adev = drm_to_adev(ddev);
 495
 496         if (amdgpu_in_reset(adev))
 497                 return -EPERM;
 498         if (adev->in_suspend && !adev->in_runpm)
 499                 return -EPERM;
 500
 501         if (adev->pp_force_state_enabled)
 502                 return amdgpu_get_pp_cur_state(dev, attr, buf);
 503         else
 504                 return sysfs_emit(buf, "\n");
 505 }
 506
 507 static ssize_t amdgpu_set_pp_force_state(struct device *dev,
 508                 struct device_attribute *attr,
 509                 const char *buf,
 510                 size_t count)
 511 {
 512         struct drm_device *ddev = dev_get_drvdata(dev);
 513         struct amdgpu_device *adev = drm_to_adev(ddev);
 514         enum amd_pm_state_type state = 0;
 515         unsigned long idx;
 516         int ret;
 517
 518         if (amdgpu_in_reset(adev))
 519                 return -EPERM;
 520         if (adev->in_suspend && !adev->in_runpm)
 521                 return -EPERM;
 522
 523         if (strlen(buf) == 1)
 524                 adev->pp_force_state_enabled = false;
 525         else if (is_support_sw_smu(adev))
 526                 adev->pp_force_state_enabled = false;
 527         else if (adev->powerplay.pp_funcs->dispatch_tasks &&
 528                         adev->powerplay.pp_funcs->get_pp_num_states) {
 529                 struct pp_states_info data;
 530
 531                 ret = kstrtoul(buf, 0, &idx);
 532                 if (ret || idx >= ARRAY_SIZE(data.states))
 533                         return -EINVAL;
 534
 535                 idx = array_index_nospec(idx, ARRAY_SIZE(data.states));
 536
 537                 amdgpu_dpm_get_pp_num_states(adev, &data);
 538                 state = data.states[idx];
 539
 540                 ret = pm_runtime_get_sync(ddev->dev);
 541                 if (ret < 0) {
 542                         pm_runtime_put_autosuspend(ddev->dev);
 543                         return ret;
 544                 }
 545
 546                 /* only set user selected power states */
 547                 if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
 548                     state != POWER_STATE_TYPE_DEFAULT) {
 549                         amdgpu_dpm_dispatch_task(adev,
 550                                         AMD_PP_TASK_ENABLE_USER_STATE, &state);
 551                         adev->pp_force_state_enabled = true;
 552                 }
 553                 pm_runtime_mark_last_busy(ddev->dev);
 554                 pm_runtime_put_autosuspend(ddev->dev);
 555         }
 556
 557         return count;
 558 }
 559
 560 /**
 561  * DOC: pp_table
 562  *
 563  * The amdgpu driver provides a sysfs API for uploading new powerplay
 564  * tables.  The file pp_table is used for this.  Reading the file
 565  * will dump the current power play table.  Writing to the file
 566  * will attempt to upload a new powerplay table and re-initialize
 567  * powerplay using that new table.
 568  *
 569  */
 570
 571 static ssize_t amdgpu_get_pp_table(struct device *dev,
 572                 struct device_attribute *attr,
 573                 char *buf)
 574 {
 575         struct drm_device *ddev = dev_get_drvdata(dev);
 576         struct amdgpu_device *adev = drm_to_adev(ddev);
 577         char *table = NULL;
 578         int size, ret;
 579
 580         if (amdgpu_in_reset(adev))
 581                 return -EPERM;
 582         if (adev->in_suspend && !adev->in_runpm)
 583                 return -EPERM;
 584
 585         ret = pm_runtime_get_sync(ddev->dev);
 586         if (ret < 0) {
 587                 pm_runtime_put_autosuspend(ddev->dev);
 588                 return ret;
 589         }
 590
 591         if (adev->powerplay.pp_funcs->get_pp_table) {
 592                 size = amdgpu_dpm_get_pp_table(adev, &table);
 593                 pm_runtime_mark_last_busy(ddev->dev);
 594                 pm_runtime_put_autosuspend(ddev->dev);
 595                 if (size < 0)
 596                         return size;
 597         } else {
 598                 pm_runtime_mark_last_busy(ddev->dev);
 599                 pm_runtime_put_autosuspend(ddev->dev);
 600                 return 0;
 601         }
 602
 603         if (size >= PAGE_SIZE)
 604                 size = PAGE_SIZE - 1;
 605
 606         memcpy(buf, table, size);
 607
 608         return size;
 609 }
 610
 611 static ssize_t amdgpu_set_pp_table(struct device *dev,
 612                 struct device_attribute *attr,
 613                 const char *buf,
 614                 size_t count)
 615 {
 616         struct drm_device *ddev = dev_get_drvdata(dev);
 617         struct amdgpu_device *adev = drm_to_adev(ddev);
 618         int ret = 0;
 619
 620         if (amdgpu_in_reset(adev))
 621                 return -EPERM;
 622         if (adev->in_suspend && !adev->in_runpm)
 623                 return -EPERM;
 624
 625         ret = pm_runtime_get_sync(ddev->dev);
 626         if (ret < 0) {
 627                 pm_runtime_put_autosuspend(ddev->dev);
 628                 return ret;
 629         }
 630
 631         ret = amdgpu_dpm_set_pp_table(adev, buf, count);
 632         if (ret) {
 633                 pm_runtime_mark_last_busy(ddev->dev);
 634                 pm_runtime_put_autosuspend(ddev->dev);
 635                 return ret;
 636         }
 637
 638         pm_runtime_mark_last_busy(ddev->dev);
 639         pm_runtime_put_autosuspend(ddev->dev);
 640
 641         return count;
 642 }
 643
 644 /**
 645  * DOC: pp_od_clk_voltage
 646  *
 647  * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages
 648  * in each power level within a power state.  The pp_od_clk_voltage is used for
 649  * this.
 650  *
 651  * Note that the actual memory controller clock rate are exposed, not
 652  * the effective memory clock of the DRAMs. To translate it, use the
 653  * following formula:
 654  *
 655  * Clock conversion (Mhz):
 656  *
 657  * HBM: effective_memory_clock = memory_controller_clock * 1
 658  *
 659  * G5: effective_memory_clock = memory_controller_clock * 1
 660  *
 661  * G6: effective_memory_clock = memory_controller_clock * 2
 662  *
 663  * DRAM data rate (MT/s):
 664  *
 665  * HBM: effective_memory_clock * 2 = data_rate
 666  *
 667  * G5: effective_memory_clock * 4 = data_rate
 668  *
 669  * G6: effective_memory_clock * 8 = data_rate
 670  *
 671  * Bandwidth (MB/s):
 672  *
 673  * data_rate * vram_bit_width / 8 = memory_bandwidth
 674  *
 675  * Some examples:
 676  *
 677  * G5 on RX460:
 678  *
 679  * memory_controller_clock = 1750 Mhz
 680  *
 681  * effective_memory_clock = 1750 Mhz * 1 = 1750 Mhz
 682  *
 683  * data rate = 1750 * 4 = 7000 MT/s
 684  *
 685  * memory_bandwidth = 7000 * 128 bits / 8 = 112000 MB/s
 686  *
 687  * G6 on RX5700:
 688  *
 689  * memory_controller_clock = 875 Mhz
 690  *
 691  * effective_memory_clock = 875 Mhz * 2 = 1750 Mhz
 692  *
 693  * data rate = 1750 * 8 = 14000 MT/s
 694  *
 695  * memory_bandwidth = 14000 * 256 bits / 8 = 448000 MB/s
 696  *
 697  * < For Vega10 and previous ASICs >
 698  *
 699  * Reading the file will display:
 700  *
 701  * - a list of engine clock levels and voltages labeled OD_SCLK
 702  *
 703  * - a list of memory clock levels and voltages labeled OD_MCLK
 704  *
 705  * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE
 706  *
 707  * To manually adjust these settings, first select manual using
 708  * power_dpm_force_performance_level. Enter a new value for each
 709  * level by writing a string that contains "s/m level clock voltage" to
 710  * the file.  E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz
 711  * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at
 712  * 810 mV.  When you have edited all of the states as needed, write
 713  * "c" (commit) to the file to commit your changes.  If you want to reset to the
 714  * default power levels, write "r" (reset) to the file to reset them.
 715  *
 716  *
 717  * < For Vega20 and newer ASICs >
 718  *
 719  * Reading the file will display:
 720  *
 721  * - minimum and maximum engine clock labeled OD_SCLK
 722  *
 723  * - minimum(not available for Vega20 and Navi1x) and maximum memory
 724  *   clock labeled OD_MCLK
 725  *
 726  * - three <frequency, voltage> points labeled OD_VDDC_CURVE.
 727  *   They can be used to calibrate the sclk voltage curve.
 728  *
 729  * - voltage offset(in mV) applied on target voltage calculation.
 730  *   This is available for Sienna Cichlid, Navy Flounder and Dimgrey
 731  *   Cavefish. For these ASICs, the target voltage calculation can be
 732  *   illustrated by "voltage = voltage calculated from v/f curve +
 733  *   overdrive vddgfx offset"
 734  *
 735  * - a list of valid ranges for sclk, mclk, and voltage curve points
 736  *   labeled OD_RANGE
 737  *
 738  * < For APUs >
 739  *
 740  * Reading the file will display:
 741  *
 742  * - minimum and maximum engine clock labeled OD_SCLK
 743  *
 744  * - a list of valid ranges for sclk labeled OD_RANGE
 745  *
 746  * < For VanGogh >
 747  *
 748  * Reading the file will display:
 749  *
 750  * - minimum and maximum engine clock labeled OD_SCLK
 751  * - minimum and maximum core clocks labeled OD_CCLK
 752  *
 753  * - a list of valid ranges for sclk and cclk labeled OD_RANGE
 754  *
 755  * To manually adjust these settings:
 756  *
 757  * - First select manual using power_dpm_force_performance_level
 758  *
 759  * - For clock frequency setting, enter a new value by writing a
 760  *   string that contains "s/m index clock" to the file. The index
 761  *   should be 0 if to set minimum clock. And 1 if to set maximum
 762  *   clock. E.g., "s 0 500" will update minimum sclk to be 500 MHz.
 763  *   "m 1 800" will update maximum mclk to be 800Mhz. For core
 764  *   clocks on VanGogh, the string contains "p core index clock".
 765  *   E.g., "p 2 0 800" would set the minimum core clock on core
 766  *   2 to 800Mhz.
 767  *
 768  *   For sclk voltage curve, enter the new values by writing a
 769  *   string that contains "vc point clock voltage" to the file. The
 770  *   points are indexed by 0, 1 and 2. E.g., "vc 0 300 600" will
 771  *   update point1 with clock set as 300Mhz and voltage as
 772  *   600mV. "vc 2 1000 1000" will update point3 with clock set
 773  *   as 1000Mhz and voltage 1000mV.
 774  *
 775  *   To update the voltage offset applied for gfxclk/voltage calculation,
 776  *   enter the new value by writing a string that contains "vo offset".
 777  *   This is supported by Sienna Cichlid, Navy Flounder and Dimgrey Cavefish.
 778  *   And the offset can be a positive or negative value.
 779  *
 780  * - When you have edited all of the states as needed, write "c" (commit)
 781  *   to the file to commit your changes
 782  *
 783  * - If you want to reset to the default power levels, write "r" (reset)
 784  *   to the file to reset them
 785  *
 786  */
 787
 788 static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
 789                 struct device_attribute *attr,
 790                 const char *buf,
 791                 size_t count)
 792 {
 793         struct drm_device *ddev = dev_get_drvdata(dev);
 794         struct amdgpu_device *adev = drm_to_adev(ddev);
 795         int ret;
 796         uint32_t parameter_size = 0;
 797         long parameter[64];
 798         char buf_cpy[128];
 799         char *tmp_str;
 800         char *sub_str;
 801         const char delimiter[3] = {' ', '\n', '\0'};
 802         uint32_t type;
 803
 804         if (amdgpu_in_reset(adev))
 805                 return -EPERM;
 806         if (adev->in_suspend && !adev->in_runpm)
 807                 return -EPERM;
 808
 809         if (count > 127)
 810                 return -EINVAL;
 811
 812         if (*buf == 's')
 813                 type = PP_OD_EDIT_SCLK_VDDC_TABLE;
 814         else if (*buf == 'p')
 815                 type = PP_OD_EDIT_CCLK_VDDC_TABLE;
 816         else if (*buf == 'm')
 817                 type = PP_OD_EDIT_MCLK_VDDC_TABLE;
 818         else if(*buf == 'r')
 819                 type = PP_OD_RESTORE_DEFAULT_TABLE;
 820         else if (*buf == 'c')
 821                 type = PP_OD_COMMIT_DPM_TABLE;
 822         else if (!strncmp(buf, "vc", 2))
 823                 type = PP_OD_EDIT_VDDC_CURVE;
 824         else if (!strncmp(buf, "vo", 2))
 825                 type = PP_OD_EDIT_VDDGFX_OFFSET;
 826         else
 827                 return -EINVAL;
 828
 829         memcpy(buf_cpy, buf, count+1);
 830
 831         tmp_str = buf_cpy;
 832
 833         if ((type == PP_OD_EDIT_VDDC_CURVE) ||
 834              (type == PP_OD_EDIT_VDDGFX_OFFSET))
 835                 tmp_str++;
 836         while (isspace(*++tmp_str));
 837
 838         while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) {
 839                 if (strlen(sub_str) == 0)
 840                         continue;
 841                 ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
 842                 if (ret)
 843                         return -EINVAL;
 844                 parameter_size++;
 845
 846                 while (isspace(*tmp_str))
 847                         tmp_str++;
 848         }
 849
 850         ret = pm_runtime_get_sync(ddev->dev);
 851         if (ret < 0) {
 852                 pm_runtime_put_autosuspend(ddev->dev);
 853                 return ret;
 854         }
 855
 856         if (adev->powerplay.pp_funcs->set_fine_grain_clk_vol) {
 857                 ret = amdgpu_dpm_set_fine_grain_clk_vol(adev, type,
 858                                                         parameter,
 859                                                         parameter_size);
 860                 if (ret) {
 861                         pm_runtime_mark_last_busy(ddev->dev);
 862                         pm_runtime_put_autosuspend(ddev->dev);
 863                         return -EINVAL;
 864                 }
 865         }
 866
 867         if (adev->powerplay.pp_funcs->odn_edit_dpm_table) {
 868                 ret = amdgpu_dpm_odn_edit_dpm_table(adev, type,
 869                                                     parameter, parameter_size);
 870                 if (ret) {
 871                         pm_runtime_mark_last_busy(ddev->dev);
 872                         pm_runtime_put_autosuspend(ddev->dev);
 873                         return -EINVAL;
 874                 }
 875         }
 876
 877         if (type == PP_OD_COMMIT_DPM_TABLE) {
 878                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
 879                         amdgpu_dpm_dispatch_task(adev,
 880                                                  AMD_PP_TASK_READJUST_POWER_STATE,
 881                                                  NULL);
 882                         pm_runtime_mark_last_busy(ddev->dev);
 883                         pm_runtime_put_autosuspend(ddev->dev);
 884                         return count;
 885                 } else {
 886                         pm_runtime_mark_last_busy(ddev->dev);
 887                         pm_runtime_put_autosuspend(ddev->dev);
 888                         return -EINVAL;
 889                 }
 890         }
 891
 892         pm_runtime_mark_last_busy(ddev->dev);
 893         pm_runtime_put_autosuspend(ddev->dev);
 894
 895         return count;
 896 }
 897
 898 static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
 899                 struct device_attribute *attr,
 900                 char *buf)
 901 {
 902         struct drm_device *ddev = dev_get_drvdata(dev);
 903         struct amdgpu_device *adev = drm_to_adev(ddev);
 904         ssize_t size;
 905         int ret;
 906
 907         if (amdgpu_in_reset(adev))
 908                 return -EPERM;
 909         if (adev->in_suspend && !adev->in_runpm)
 910                 return -EPERM;
 911
 912         ret = pm_runtime_get_sync(ddev->dev);
 913         if (ret < 0) {
 914                 pm_runtime_put_autosuspend(ddev->dev);
 915                 return ret;
 916         }
 917
 918         if (adev->powerplay.pp_funcs->print_clock_levels) {
 919                 size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
 920                 size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size);
 921                 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, buf+size);
 922                 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDGFX_OFFSET, buf+size);
 923                 size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf+size);
 924                 size += amdgpu_dpm_print_clock_levels(adev, OD_CCLK, buf+size);
 925         } else {
 926                 size = snprintf(buf, PAGE_SIZE, "\n");
 927         }
 928         pm_runtime_mark_last_busy(ddev->dev);
 929         pm_runtime_put_autosuspend(ddev->dev);
 930
 931         return size;
 932 }
 933
 934 /**
 935  * DOC: pp_features
 936  *
 937  * The amdgpu driver provides a sysfs API for adjusting what powerplay
 938  * features to be enabled. The file pp_features is used for this. And
 939  * this is only available for Vega10 and later dGPUs.
 940  *
 941  * Reading back the file will show you the followings:
 942  * - Current ppfeature masks
 943  * - List of the all supported powerplay features with their naming,
 944  *   bitmasks and enablement status('Y'/'N' means "enabled"/"disabled").
 945  *
 946  * To manually enable or disable a specific feature, just set or clear
 947  * the corresponding bit from original ppfeature masks and input the
 948  * new ppfeature masks.
 949  */
 950 static ssize_t amdgpu_set_pp_features(struct device *dev,
 951                                       struct device_attribute *attr,
 952                                       const char *buf,
 953                                       size_t count)
 954 {
 955         struct drm_device *ddev = dev_get_drvdata(dev);
 956         struct amdgpu_device *adev = drm_to_adev(ddev);
 957         uint64_t featuremask;
 958         int ret;
 959
 960         if (amdgpu_in_reset(adev))
 961                 return -EPERM;
 962         if (adev->in_suspend && !adev->in_runpm)
 963                 return -EPERM;
 964
 965         ret = kstrtou64(buf, 0, &featuremask);
 966         if (ret)
 967                 return -EINVAL;
 968
 969         ret = pm_runtime_get_sync(ddev->dev);
 970         if (ret < 0) {
 971                 pm_runtime_put_autosuspend(ddev->dev);
 972                 return ret;
 973         }
 974
 975         if (adev->powerplay.pp_funcs->set_ppfeature_status) {
 976                 ret = amdgpu_dpm_set_ppfeature_status(adev, featuremask);
 977                 if (ret) {
 978                         pm_runtime_mark_last_busy(ddev->dev);
 979                         pm_runtime_put_autosuspend(ddev->dev);
 980                         return -EINVAL;
 981                 }
 982         }
 983         pm_runtime_mark_last_busy(ddev->dev);
 984         pm_runtime_put_autosuspend(ddev->dev);
 985
 986         return count;
 987 }
 988
 989 static ssize_t amdgpu_get_pp_features(struct device *dev,
 990                                       struct device_attribute *attr,
 991                                       char *buf)
 992 {
 993         struct drm_device *ddev = dev_get_drvdata(dev);
 994         struct amdgpu_device *adev = drm_to_adev(ddev);
 995         ssize_t size;
 996         int ret;
 997
 998         if (amdgpu_in_reset(adev))
 999                 return -EPERM;
1000         if (adev->in_suspend && !adev->in_runpm)
1001                 return -EPERM;
1002
1003         ret = pm_runtime_get_sync(ddev->dev);
1004         if (ret < 0) {
1005                 pm_runtime_put_autosuspend(ddev->dev);
1006                 return ret;
1007         }
1008
1009         if (adev->powerplay.pp_funcs->get_ppfeature_status)
1010                 size = amdgpu_dpm_get_ppfeature_status(adev, buf);
1011         else
1012                 size = snprintf(buf, PAGE_SIZE, "\n");
1013
1014         pm_runtime_mark_last_busy(ddev->dev);
1015         pm_runtime_put_autosuspend(ddev->dev);
1016
1017         return size;
1018 }
1019
1020 /**
1021  * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk pp_dpm_pcie
1022  *
1023  * The amdgpu driver provides a sysfs API for adjusting what power levels
1024  * are enabled for a given power state.  The files pp_dpm_sclk, pp_dpm_mclk,
1025  * pp_dpm_socclk, pp_dpm_fclk, pp_dpm_dcefclk and pp_dpm_pcie are used for
1026  * this.
1027  *
1028  * pp_dpm_socclk and pp_dpm_dcefclk interfaces are only available for
1029  * Vega10 and later ASICs.
1030  * pp_dpm_fclk interface is only available for Vega20 and later ASICs.
1031  *
1032  * Reading back the files will show you the available power levels within
1033  * the power state and the clock information for those levels.
1034  *
1035  * To manually adjust these states, first select manual using
1036  * power_dpm_force_performance_level.
1037  * Secondly, enter a new value for each level by inputing a string that
1038  * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie"
1039  * E.g.,
1040  *
1041  * .. code-block:: bash
1042  *
1043  *      echo "4 5 6" > pp_dpm_sclk
1044  *
1045  * will enable sclk levels 4, 5, and 6.
1046  *
1047  * NOTE: change to the dcefclk max dpm level is not supported now
1048  */
1049
1050 static ssize_t amdgpu_get_pp_dpm_clock(struct device *dev,
1051                 enum pp_clock_type type,
1052                 char *buf)
1053 {
1054         struct drm_device *ddev = dev_get_drvdata(dev);
1055         struct amdgpu_device *adev = drm_to_adev(ddev);
1056         ssize_t size;
1057         int ret;
1058
1059         if (amdgpu_in_reset(adev))
1060                 return -EPERM;
1061         if (adev->in_suspend && !adev->in_runpm)
1062                 return -EPERM;
1063
1064         ret = pm_runtime_get_sync(ddev->dev);
1065         if (ret < 0) {
1066                 pm_runtime_put_autosuspend(ddev->dev);
1067                 return ret;
1068         }
1069
1070         if (adev->powerplay.pp_funcs->print_clock_levels)
1071                 size = amdgpu_dpm_print_clock_levels(adev, type, buf);
1072         else
1073                 size = snprintf(buf, PAGE_SIZE, "\n");
1074
1075         pm_runtime_mark_last_busy(ddev->dev);
1076         pm_runtime_put_autosuspend(ddev->dev);
1077
1078         return size;
1079 }
1080
1081 /*
1082  * Worst case: 32 bits individually specified, in octal at 12 characters
1083  * per line (+1 for \n).
1084  */
1085 #define AMDGPU_MASK_BUF_MAX     (32 * 13)
1086
1087 static ssize_t amdgpu_read_mask(const char *buf, size_t count, uint32_t *mask)
1088 {
1089         int ret;
1090         unsigned long level;
1091         char *sub_str = NULL;
1092         char *tmp;
1093         char buf_cpy[AMDGPU_MASK_BUF_MAX + 1];
1094         const char delimiter[3] = {' ', '\n', '\0'};
1095         size_t bytes;
1096
1097         *mask = 0;
1098
1099         bytes = min(count, sizeof(buf_cpy) - 1);
1100         memcpy(buf_cpy, buf, bytes);
1101         buf_cpy[bytes] = '\0';
1102         tmp = buf_cpy;
1103         while ((sub_str = strsep(&tmp, delimiter)) != NULL) {
1104                 if (strlen(sub_str)) {
1105                         ret = kstrtoul(sub_str, 0, &level);
1106                         if (ret || level > 31)
1107                                 return -EINVAL;
1108                         *mask |= 1 << level;
1109                 } else
1110                         break;
1111         }
1112
1113         return 0;
1114 }
1115
1116 static ssize_t amdgpu_set_pp_dpm_clock(struct device *dev,
1117                 enum pp_clock_type type,
1118                 const char *buf,
1119                 size_t count)
1120 {
1121         struct drm_device *ddev = dev_get_drvdata(dev);
1122         struct amdgpu_device *adev = drm_to_adev(ddev);
1123         int ret;
1124         uint32_t mask = 0;
1125
1126         if (amdgpu_in_reset(adev))
1127                 return -EPERM;
1128         if (adev->in_suspend && !adev->in_runpm)
1129                 return -EPERM;
1130
1131         ret = amdgpu_read_mask(buf, count, &mask);
1132         if (ret)
1133                 return ret;
1134
1135         ret = pm_runtime_get_sync(ddev->dev);
1136         if (ret < 0) {
1137                 pm_runtime_put_autosuspend(ddev->dev);
1138                 return ret;
1139         }
1140
1141         if (adev->powerplay.pp_funcs->force_clock_level)
1142                 ret = amdgpu_dpm_force_clock_level(adev, type, mask);
1143         else
1144                 ret = 0;
1145
1146         pm_runtime_mark_last_busy(ddev->dev);
1147         pm_runtime_put_autosuspend(ddev->dev);
1148
1149         if (ret)
1150                 return -EINVAL;
1151
1152         return count;
1153 }
1154
1155 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
1156                 struct device_attribute *attr,
1157                 char *buf)
1158 {
1159         return amdgpu_get_pp_dpm_clock(dev, PP_SCLK, buf);
1160 }
1161
1162 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
1163                 struct device_attribute *attr,
1164                 const char *buf,
1165                 size_t count)
1166 {
1167         return amdgpu_set_pp_dpm_clock(dev, PP_SCLK, buf, count);
1168 }
1169
1170 static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
1171                 struct device_attribute *attr,
1172                 char *buf)
1173 {
1174         return amdgpu_get_pp_dpm_clock(dev, PP_MCLK, buf);
1175 }
1176
1177 static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
1178                 struct device_attribute *attr,
1179                 const char *buf,
1180                 size_t count)
1181 {
1182         return amdgpu_set_pp_dpm_clock(dev, PP_MCLK, buf, count);
1183 }
1184
1185 static ssize_t amdgpu_get_pp_dpm_socclk(struct device *dev,
1186                 struct device_attribute *attr,
1187                 char *buf)
1188 {
1189         return amdgpu_get_pp_dpm_clock(dev, PP_SOCCLK, buf);
1190 }
1191
1192 static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev,
1193                 struct device_attribute *attr,
1194                 const char *buf,
1195                 size_t count)
1196 {
1197         return amdgpu_set_pp_dpm_clock(dev, PP_SOCCLK, buf, count);
1198 }
1199
1200 static ssize_t amdgpu_get_pp_dpm_fclk(struct device *dev,
1201                 struct device_attribute *attr,
1202                 char *buf)
1203 {
1204         return amdgpu_get_pp_dpm_clock(dev, PP_FCLK, buf);
1205 }
1206
1207 static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev,
1208                 struct device_attribute *attr,
1209                 const char *buf,
1210                 size_t count)
1211 {
1212         return amdgpu_set_pp_dpm_clock(dev, PP_FCLK, buf, count);
1213 }
1214
1215 static ssize_t amdgpu_get_pp_dpm_vclk(struct device *dev,
1216                 struct device_attribute *attr,
1217                 char *buf)
1218 {
1219         return amdgpu_get_pp_dpm_clock(dev, PP_VCLK, buf);
1220 }
1221
1222 static ssize_t amdgpu_set_pp_dpm_vclk(struct device *dev,
1223                 struct device_attribute *attr,
1224                 const char *buf,
1225                 size_t count)
1226 {
1227         return amdgpu_set_pp_dpm_clock(dev, PP_VCLK, buf, count);
1228 }
1229
1230 static ssize_t amdgpu_get_pp_dpm_dclk(struct device *dev,
1231                 struct device_attribute *attr,
1232                 char *buf)
1233 {
1234         return amdgpu_get_pp_dpm_clock(dev, PP_DCLK, buf);
1235 }
1236
1237 static ssize_t amdgpu_set_pp_dpm_dclk(struct device *dev,
1238                 struct device_attribute *attr,
1239                 const char *buf,
1240                 size_t count)
1241 {
1242         return amdgpu_set_pp_dpm_clock(dev, PP_DCLK, buf, count);
1243 }
1244
1245 static ssize_t amdgpu_get_pp_dpm_dcefclk(struct device *dev,
1246                 struct device_attribute *attr,
1247                 char *buf)
1248 {
1249         return amdgpu_get_pp_dpm_clock(dev, PP_DCEFCLK, buf);
1250 }
1251
1252 static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev,
1253                 struct device_attribute *attr,
1254                 const char *buf,
1255                 size_t count)
1256 {
1257         return amdgpu_set_pp_dpm_clock(dev, PP_DCEFCLK, buf, count);
1258 }
1259
1260 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
1261                 struct device_attribute *attr,
1262                 char *buf)
1263 {
1264         return amdgpu_get_pp_dpm_clock(dev, PP_PCIE, buf);
1265 }
1266
1267 static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
1268                 struct device_attribute *attr,
1269                 const char *buf,
1270                 size_t count)
1271 {
1272         return amdgpu_set_pp_dpm_clock(dev, PP_PCIE, buf, count);
1273 }
1274
1275 static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
1276                 struct device_attribute *attr,
1277                 char *buf)
1278 {
1279         struct drm_device *ddev = dev_get_drvdata(dev);
1280         struct amdgpu_device *adev = drm_to_adev(ddev);
1281         uint32_t value = 0;
1282         int ret;
1283
1284         if (amdgpu_in_reset(adev))
1285                 return -EPERM;
1286         if (adev->in_suspend && !adev->in_runpm)
1287                 return -EPERM;
1288
1289         ret = pm_runtime_get_sync(ddev->dev);
1290         if (ret < 0) {
1291                 pm_runtime_put_autosuspend(ddev->dev);
1292                 return ret;
1293         }
1294
1295         if (is_support_sw_smu(adev))
1296                 value = 0;
1297         else if (adev->powerplay.pp_funcs->get_sclk_od)
1298                 value = amdgpu_dpm_get_sclk_od(adev);
1299
1300         pm_runtime_mark_last_busy(ddev->dev);
1301         pm_runtime_put_autosuspend(ddev->dev);
1302
1303         return sysfs_emit(buf, "%d\n", value);
1304 }
1305
1306 static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
1307                 struct device_attribute *attr,
1308                 const char *buf,
1309                 size_t count)
1310 {
1311         struct drm_device *ddev = dev_get_drvdata(dev);
1312         struct amdgpu_device *adev = drm_to_adev(ddev);
1313         int ret;
1314         long int value;
1315
1316         if (amdgpu_in_reset(adev))
1317                 return -EPERM;
1318         if (adev->in_suspend && !adev->in_runpm)
1319                 return -EPERM;
1320
1321         ret = kstrtol(buf, 0, &value);
1322
1323         if (ret)
1324                 return -EINVAL;
1325
1326         ret = pm_runtime_get_sync(ddev->dev);
1327         if (ret < 0) {
1328                 pm_runtime_put_autosuspend(ddev->dev);
1329                 return ret;
1330         }
1331
1332         if (is_support_sw_smu(adev)) {
1333                 value = 0;
1334         } else {
1335                 if (adev->powerplay.pp_funcs->set_sclk_od)
1336                         amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
1337
1338                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
1339                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
1340                 } else {
1341                         adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
1342                         amdgpu_pm_compute_clocks(adev);
1343                 }
1344         }
1345
1346         pm_runtime_mark_last_busy(ddev->dev);
1347         pm_runtime_put_autosuspend(ddev->dev);
1348
1349         return count;
1350 }
1351
1352 static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
1353                 struct device_attribute *attr,
1354                 char *buf)
1355 {
1356         struct drm_device *ddev = dev_get_drvdata(dev);
1357         struct amdgpu_device *adev = drm_to_adev(ddev);
1358         uint32_t value = 0;
1359         int ret;
1360
1361         if (amdgpu_in_reset(adev))
1362                 return -EPERM;
1363         if (adev->in_suspend && !adev->in_runpm)
1364                 return -EPERM;
1365
1366         ret = pm_runtime_get_sync(ddev->dev);
1367         if (ret < 0) {
1368                 pm_runtime_put_autosuspend(ddev->dev);
1369                 return ret;
1370         }
1371
1372         if (is_support_sw_smu(adev))
1373                 value = 0;
1374         else if (adev->powerplay.pp_funcs->get_mclk_od)
1375                 value = amdgpu_dpm_get_mclk_od(adev);
1376
1377         pm_runtime_mark_last_busy(ddev->dev);
1378         pm_runtime_put_autosuspend(ddev->dev);
1379
1380         return sysfs_emit(buf, "%d\n", value);
1381 }
1382
1383 static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
1384                 struct device_attribute *attr,
1385                 const char *buf,
1386                 size_t count)
1387 {
1388         struct drm_device *ddev = dev_get_drvdata(dev);
1389         struct amdgpu_device *adev = drm_to_adev(ddev);
1390         int ret;
1391         long int value;
1392
1393         if (amdgpu_in_reset(adev))
1394                 return -EPERM;
1395         if (adev->in_suspend && !adev->in_runpm)
1396                 return -EPERM;
1397
1398         ret = kstrtol(buf, 0, &value);
1399
1400         if (ret)
1401                 return -EINVAL;
1402
1403         ret = pm_runtime_get_sync(ddev->dev);
1404         if (ret < 0) {
1405                 pm_runtime_put_autosuspend(ddev->dev);
1406                 return ret;
1407         }
1408
1409         if (is_support_sw_smu(adev)) {
1410                 value = 0;
1411         } else {
1412                 if (adev->powerplay.pp_funcs->set_mclk_od)
1413                         amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
1414
1415                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
1416                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
1417                 } else {
1418                         adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
1419                         amdgpu_pm_compute_clocks(adev);
1420                 }
1421         }
1422
1423         pm_runtime_mark_last_busy(ddev->dev);
1424         pm_runtime_put_autosuspend(ddev->dev);
1425
1426         return count;
1427 }
1428
1429 /**
1430  * DOC: pp_power_profile_mode
1431  *
1432  * The amdgpu driver provides a sysfs API for adjusting the heuristics
1433  * related to switching between power levels in a power state.  The file
1434  * pp_power_profile_mode is used for this.
1435  *
1436  * Reading this file outputs a list of all of the predefined power profiles
1437  * and the relevant heuristics settings for that profile.
1438  *
1439  * To select a profile or create a custom profile, first select manual using
1440  * power_dpm_force_performance_level.  Writing the number of a predefined
1441  * profile to pp_power_profile_mode will enable those heuristics.  To
1442  * create a custom set of heuristics, write a string of numbers to the file
1443  * starting with the number of the custom profile along with a setting
1444  * for each heuristic parameter.  Due to differences across asic families
1445  * the heuristic parameters vary from family to family.
1446  *
1447  */
1448
1449 static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,
1450                 struct device_attribute *attr,
1451                 char *buf)
1452 {
1453         struct drm_device *ddev = dev_get_drvdata(dev);
1454         struct amdgpu_device *adev = drm_to_adev(ddev);
1455         ssize_t size;
1456         int ret;
1457
1458         if (amdgpu_in_reset(adev))
1459                 return -EPERM;
1460         if (adev->in_suspend && !adev->in_runpm)
1461                 return -EPERM;
1462
1463         ret = pm_runtime_get_sync(ddev->dev);
1464         if (ret < 0) {
1465                 pm_runtime_put_autosuspend(ddev->dev);
1466                 return ret;
1467         }
1468
1469         if (adev->powerplay.pp_funcs->get_power_profile_mode)
1470                 size = amdgpu_dpm_get_power_profile_mode(adev, buf);
1471         else
1472                 size = snprintf(buf, PAGE_SIZE, "\n");
1473
1474         pm_runtime_mark_last_busy(ddev->dev);
1475         pm_runtime_put_autosuspend(ddev->dev);
1476
1477         return size;
1478 }
1479
1480
1481 static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
1482                 struct device_attribute *attr,
1483                 const char *buf,
1484                 size_t count)
1485 {
1486         int ret;
1487         struct drm_device *ddev = dev_get_drvdata(dev);
1488         struct amdgpu_device *adev = drm_to_adev(ddev);
1489         uint32_t parameter_size = 0;
1490         long parameter[64];
1491         char *sub_str, buf_cpy[128];
1492         char *tmp_str;
1493         uint32_t i = 0;
1494         char tmp[2];
1495         long int profile_mode = 0;
1496         const char delimiter[3] = {' ', '\n', '\0'};
1497
1498         if (amdgpu_in_reset(adev))
1499                 return -EPERM;
1500         if (adev->in_suspend && !adev->in_runpm)
1501                 return -EPERM;
1502
1503         tmp[0] = *(buf);
1504         tmp[1] = '\0';
1505         ret = kstrtol(tmp, 0, &profile_mode);
1506         if (ret)
1507                 return -EINVAL;
1508
1509         if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1510                 if (count < 2 || count > 127)
1511                         return -EINVAL;
1512                 while (isspace(*++buf))
1513                         i++;
1514                 memcpy(buf_cpy, buf, count-i);
1515                 tmp_str = buf_cpy;
1516                 while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) {
1517                         if (strlen(sub_str) == 0)
1518                                 continue;
1519                         ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
1520                         if (ret)
1521                                 return -EINVAL;
1522                         parameter_size++;
1523                         while (isspace(*tmp_str))
1524                                 tmp_str++;
1525                 }
1526         }
1527         parameter[parameter_size] = profile_mode;
1528
1529         ret = pm_runtime_get_sync(ddev->dev);
1530         if (ret < 0) {
1531                 pm_runtime_put_autosuspend(ddev->dev);
1532                 return ret;
1533         }
1534
1535         if (adev->powerplay.pp_funcs->set_power_profile_mode)
1536                 ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size);
1537
1538         pm_runtime_mark_last_busy(ddev->dev);
1539         pm_runtime_put_autosuspend(ddev->dev);
1540
1541         if (!ret)
1542                 return count;
1543
1544         return -EINVAL;
1545 }
1546
1547 /**
1548  * DOC: gpu_busy_percent
1549  *
1550  * The amdgpu driver provides a sysfs API for reading how busy the GPU
1551  * is as a percentage.  The file gpu_busy_percent is used for this.
1552  * The SMU firmware computes a percentage of load based on the
1553  * aggregate activity level in the IP cores.
1554  */
1555 static ssize_t amdgpu_get_gpu_busy_percent(struct device *dev,
1556                                            struct device_attribute *attr,
1557                                            char *buf)
1558 {
1559         struct drm_device *ddev = dev_get_drvdata(dev);
1560         struct amdgpu_device *adev = drm_to_adev(ddev);
1561         int r, value, size = sizeof(value);
1562
1563         if (amdgpu_in_reset(adev))
1564                 return -EPERM;
1565         if (adev->in_suspend && !adev->in_runpm)
1566                 return -EPERM;
1567
1568         r = pm_runtime_get_sync(ddev->dev);
1569         if (r < 0) {
1570                 pm_runtime_put_autosuspend(ddev->dev);
1571                 return r;
1572         }
1573
1574         /* read the IP busy sensor */
1575         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD,
1576                                    (void *)&value, &size);
1577
1578         pm_runtime_mark_last_busy(ddev->dev);
1579         pm_runtime_put_autosuspend(ddev->dev);
1580
1581         if (r)
1582                 return r;
1583
1584         return sysfs_emit(buf, "%d\n", value);
1585 }
1586
1587 /**
1588  * DOC: mem_busy_percent
1589  *
1590  * The amdgpu driver provides a sysfs API for reading how busy the VRAM
1591  * is as a percentage.  The file mem_busy_percent is used for this.
1592  * The SMU firmware computes a percentage of load based on the
1593  * aggregate activity level in the IP cores.
1594  */
1595 static ssize_t amdgpu_get_mem_busy_percent(struct device *dev,
1596                                            struct device_attribute *attr,
1597                                            char *buf)
1598 {
1599         struct drm_device *ddev = dev_get_drvdata(dev);
1600         struct amdgpu_device *adev = drm_to_adev(ddev);
1601         int r, value, size = sizeof(value);
1602
1603         if (amdgpu_in_reset(adev))
1604                 return -EPERM;
1605         if (adev->in_suspend && !adev->in_runpm)
1606                 return -EPERM;
1607
1608         r = pm_runtime_get_sync(ddev->dev);
1609         if (r < 0) {
1610                 pm_runtime_put_autosuspend(ddev->dev);
1611                 return r;
1612         }
1613
1614         /* read the IP busy sensor */
1615         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD,
1616                                    (void *)&value, &size);
1617
1618         pm_runtime_mark_last_busy(ddev->dev);
1619         pm_runtime_put_autosuspend(ddev->dev);
1620
1621         if (r)
1622                 return r;
1623
1624         return sysfs_emit(buf, "%d\n", value);
1625 }
1626
1627 /**
1628  * DOC: pcie_bw
1629  *
1630  * The amdgpu driver provides a sysfs API for estimating how much data
1631  * has been received and sent by the GPU in the last second through PCIe.
1632  * The file pcie_bw is used for this.
1633  * The Perf counters count the number of received and sent messages and return
1634  * those values, as well as the maximum payload size of a PCIe packet (mps).
1635  * Note that it is not possible to easily and quickly obtain the size of each
1636  * packet transmitted, so we output the max payload size (mps) to allow for
1637  * quick estimation of the PCIe bandwidth usage
1638  */
1639 static ssize_t amdgpu_get_pcie_bw(struct device *dev,
1640                 struct device_attribute *attr,
1641                 char *buf)
1642 {
1643         struct drm_device *ddev = dev_get_drvdata(dev);
1644         struct amdgpu_device *adev = drm_to_adev(ddev);
1645         uint64_t count0 = 0, count1 = 0;
1646         int ret;
1647
1648         if (amdgpu_in_reset(adev))
1649                 return -EPERM;
1650         if (adev->in_suspend && !adev->in_runpm)
1651                 return -EPERM;
1652
1653         if (adev->flags & AMD_IS_APU)
1654                 return -ENODATA;
1655
1656         if (!adev->asic_funcs->get_pcie_usage)
1657                 return -ENODATA;
1658
1659         ret = pm_runtime_get_sync(ddev->dev);
1660         if (ret < 0) {
1661                 pm_runtime_put_autosuspend(ddev->dev);
1662                 return ret;
1663         }
1664
1665         amdgpu_asic_get_pcie_usage(adev, &count0, &count1);
1666
1667         pm_runtime_mark_last_busy(ddev->dev);
1668         pm_runtime_put_autosuspend(ddev->dev);
1669
1670         return sysfs_emit(buf, "%llu %llu %i\n",
1671                           count0, count1, pcie_get_mps(adev->pdev));
1672 }
1673
1674 /**
1675  * DOC: unique_id
1676  *
1677  * The amdgpu driver provides a sysfs API for providing a unique ID for the GPU
1678  * The file unique_id is used for this.
1679  * This will provide a Unique ID that will persist from machine to machine
1680  *
1681  * NOTE: This will only work for GFX9 and newer. This file will be absent
1682  * on unsupported ASICs (GFX8 and older)
1683  */
1684 static ssize_t amdgpu_get_unique_id(struct device *dev,
1685                 struct device_attribute *attr,
1686                 char *buf)
1687 {
1688         struct drm_device *ddev = dev_get_drvdata(dev);
1689         struct amdgpu_device *adev = drm_to_adev(ddev);
1690
1691         if (amdgpu_in_reset(adev))
1692                 return -EPERM;
1693         if (adev->in_suspend && !adev->in_runpm)
1694                 return -EPERM;
1695
1696         if (adev->unique_id)
1697                 return sysfs_emit(buf, "%016llx\n", adev->unique_id);
1698
1699         return 0;
1700 }
1701
1702 /**
1703  * DOC: thermal_throttling_logging
1704  *
1705  * Thermal throttling pulls down the clock frequency and thus the performance.
1706  * It's an useful mechanism to protect the chip from overheating. Since it
1707  * impacts performance, the user controls whether it is enabled and if so,
1708  * the log frequency.
1709  *
1710  * Reading back the file shows you the status(enabled or disabled) and
1711  * the interval(in seconds) between each thermal logging.
1712  *
1713  * Writing an integer to the file, sets a new logging interval, in seconds.
1714  * The value should be between 1 and 3600. If the value is less than 1,
1715  * thermal logging is disabled. Values greater than 3600 are ignored.
1716  */
1717 static ssize_t amdgpu_get_thermal_throttling_logging(struct device *dev,
1718                                                      struct device_attribute *attr,
1719                                                      char *buf)
1720 {
1721         struct drm_device *ddev = dev_get_drvdata(dev);
1722         struct amdgpu_device *adev = drm_to_adev(ddev);
1723
1724         return sysfs_emit(buf, "%s: thermal throttling logging %s, with interval %d seconds\n",
1725                           adev_to_drm(adev)->unique,
1726                           atomic_read(&adev->throttling_logging_enabled) ? "enabled" : "disabled",
1727                           adev->throttling_logging_rs.interval / HZ + 1);
1728 }
1729
1730 static ssize_t amdgpu_set_thermal_throttling_logging(struct device *dev,
1731                                                      struct device_attribute *attr,
1732                                                      const char *buf,
1733                                                      size_t count)
1734 {
1735         struct drm_device *ddev = dev_get_drvdata(dev);
1736         struct amdgpu_device *adev = drm_to_adev(ddev);
1737         long throttling_logging_interval;
1738         unsigned long flags;
1739         int ret = 0;
1740
1741         ret = kstrtol(buf, 0, &throttling_logging_interval);
1742         if (ret)
1743                 return ret;
1744
1745         if (throttling_logging_interval > 3600)
1746                 return -EINVAL;
1747
1748         if (throttling_logging_interval > 0) {
1749                 raw_spin_lock_irqsave(&adev->throttling_logging_rs.lock, flags);
1750                 /*
1751                  * Reset the ratelimit timer internals.
1752                  * This can effectively restart the timer.
1753                  */
1754                 adev->throttling_logging_rs.interval =
1755                         (throttling_logging_interval - 1) * HZ;
1756                 adev->throttling_logging_rs.begin = 0;
1757                 adev->throttling_logging_rs.printed = 0;
1758                 adev->throttling_logging_rs.missed = 0;
1759                 raw_spin_unlock_irqrestore(&adev->throttling_logging_rs.lock, flags);
1760
1761                 atomic_set(&adev->throttling_logging_enabled, 1);
1762         } else {
1763                 atomic_set(&adev->throttling_logging_enabled, 0);
1764         }
1765
1766         return count;
1767 }
1768
1769 /**
1770  * DOC: gpu_metrics
1771  *
1772  * The amdgpu driver provides a sysfs API for retrieving current gpu
1773  * metrics data. The file gpu_metrics is used for this. Reading the
1774  * file will dump all the current gpu metrics data.
1775  *
1776  * These data include temperature, frequency, engines utilization,
1777  * power consume, throttler status, fan speed and cpu core statistics(
1778  * available for APU only). That's it will give a snapshot of all sensors
1779  * at the same time.
1780  */
1781 static ssize_t amdgpu_get_gpu_metrics(struct device *dev,
1782                                       struct device_attribute *attr,
1783                                       char *buf)
1784 {
1785         struct drm_device *ddev = dev_get_drvdata(dev);
1786         struct amdgpu_device *adev = drm_to_adev(ddev);
1787         void *gpu_metrics;
1788         ssize_t size = 0;
1789         int ret;
1790
1791         if (amdgpu_in_reset(adev))
1792                 return -EPERM;
1793         if (adev->in_suspend && !adev->in_runpm)
1794                 return -EPERM;
1795
1796         ret = pm_runtime_get_sync(ddev->dev);
1797         if (ret < 0) {
1798                 pm_runtime_put_autosuspend(ddev->dev);
1799                 return ret;
1800         }
1801
1802         if (adev->powerplay.pp_funcs->get_gpu_metrics)
1803                 size = amdgpu_dpm_get_gpu_metrics(adev, &gpu_metrics);
1804
1805         if (size <= 0)
1806                 goto out;
1807
1808         if (size >= PAGE_SIZE)
1809                 size = PAGE_SIZE - 1;
1810
1811         memcpy(buf, gpu_metrics, size);
1812
1813 out:
1814         pm_runtime_mark_last_busy(ddev->dev);
1815         pm_runtime_put_autosuspend(ddev->dev);
1816
1817         return size;
1818 }
1819
1820 static struct amdgpu_device_attr amdgpu_device_attrs[] = {
1821         AMDGPU_DEVICE_ATTR_RW(power_dpm_state,                          ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1822         AMDGPU_DEVICE_ATTR_RW(power_dpm_force_performance_level,        ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1823         AMDGPU_DEVICE_ATTR_RO(pp_num_states,                            ATTR_FLAG_BASIC),
1824         AMDGPU_DEVICE_ATTR_RO(pp_cur_state,                             ATTR_FLAG_BASIC),
1825         AMDGPU_DEVICE_ATTR_RW(pp_force_state,                           ATTR_FLAG_BASIC),
1826         AMDGPU_DEVICE_ATTR_RW(pp_table,                                 ATTR_FLAG_BASIC),
1827         AMDGPU_DEVICE_ATTR_RW(pp_dpm_sclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1828         AMDGPU_DEVICE_ATTR_RW(pp_dpm_mclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1829         AMDGPU_DEVICE_ATTR_RW(pp_dpm_socclk,                            ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1830         AMDGPU_DEVICE_ATTR_RW(pp_dpm_fclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1831         AMDGPU_DEVICE_ATTR_RW(pp_dpm_vclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1832         AMDGPU_DEVICE_ATTR_RW(pp_dpm_dclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1833         AMDGPU_DEVICE_ATTR_RW(pp_dpm_dcefclk,                           ATTR_FLAG_BASIC),
1834         AMDGPU_DEVICE_ATTR_RW(pp_dpm_pcie,                              ATTR_FLAG_BASIC),
1835         AMDGPU_DEVICE_ATTR_RW(pp_sclk_od,                               ATTR_FLAG_BASIC),
1836         AMDGPU_DEVICE_ATTR_RW(pp_mclk_od,                               ATTR_FLAG_BASIC),
1837         AMDGPU_DEVICE_ATTR_RW(pp_power_profile_mode,                    ATTR_FLAG_BASIC),
1838         AMDGPU_DEVICE_ATTR_RW(pp_od_clk_voltage,                        ATTR_FLAG_BASIC),
1839         AMDGPU_DEVICE_ATTR_RO(gpu_busy_percent,                         ATTR_FLAG_BASIC),
1840         AMDGPU_DEVICE_ATTR_RO(mem_busy_percent,                         ATTR_FLAG_BASIC),
1841         AMDGPU_DEVICE_ATTR_RO(pcie_bw,                                  ATTR_FLAG_BASIC),
1842         AMDGPU_DEVICE_ATTR_RW(pp_features,                              ATTR_FLAG_BASIC),
1843         AMDGPU_DEVICE_ATTR_RO(unique_id,                                ATTR_FLAG_BASIC),
1844         AMDGPU_DEVICE_ATTR_RW(thermal_throttling_logging,               ATTR_FLAG_BASIC),
1845         AMDGPU_DEVICE_ATTR_RO(gpu_metrics,                              ATTR_FLAG_BASIC),
1846 };
1847
1848 static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
1849                                uint32_t mask, enum amdgpu_device_attr_states *states)
1850 {
1851         struct device_attribute *dev_attr = &attr->dev_attr;
1852         const char *attr_name = dev_attr->attr.name;
1853         struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
1854         enum amd_asic_type asic_type = adev->asic_type;
1855
1856         if (!(attr->flags & mask)) {
1857                 *states = ATTR_STATE_UNSUPPORTED;
1858                 return 0;
1859         }
1860
1861 #define DEVICE_ATTR_IS(_name)   (!strcmp(attr_name, #_name))
1862
1863         if (DEVICE_ATTR_IS(pp_dpm_socclk)) {
1864                 if (asic_type < CHIP_VEGA10)
1865                         *states = ATTR_STATE_UNSUPPORTED;
1866         } else if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) {
1867                 if (asic_type < CHIP_VEGA10 ||
1868                     asic_type == CHIP_ARCTURUS ||
1869                     asic_type == CHIP_ALDEBARAN)
1870                         *states = ATTR_STATE_UNSUPPORTED;
1871         } else if (DEVICE_ATTR_IS(pp_dpm_fclk)) {
1872                 if (asic_type < CHIP_VEGA20)
1873                         *states = ATTR_STATE_UNSUPPORTED;
1874         } else if (DEVICE_ATTR_IS(pp_od_clk_voltage)) {
1875                 *states = ATTR_STATE_UNSUPPORTED;
1876                 if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||
1877                     (is_support_sw_smu(adev) && adev->smu.is_apu) ||
1878                         (!is_support_sw_smu(adev) && hwmgr->od_enabled))
1879                         *states = ATTR_STATE_SUPPORTED;
1880         } else if (DEVICE_ATTR_IS(mem_busy_percent)) {
1881                 if (adev->flags & AMD_IS_APU || asic_type == CHIP_VEGA10)
1882                         *states = ATTR_STATE_UNSUPPORTED;
1883         } else if (DEVICE_ATTR_IS(pcie_bw)) {
1884                 /* PCIe Perf counters won't work on APU nodes */
1885                 if (adev->flags & AMD_IS_APU)
1886                         *states = ATTR_STATE_UNSUPPORTED;
1887         } else if (DEVICE_ATTR_IS(unique_id)) {
1888                 if (asic_type != CHIP_VEGA10 &&
1889                     asic_type != CHIP_VEGA20 &&
1890                     asic_type != CHIP_ARCTURUS)
1891                         *states = ATTR_STATE_UNSUPPORTED;
1892         } else if (DEVICE_ATTR_IS(pp_features)) {
1893                 if (adev->flags & AMD_IS_APU || asic_type < CHIP_VEGA10)
1894                         *states = ATTR_STATE_UNSUPPORTED;
1895         } else if (DEVICE_ATTR_IS(gpu_metrics)) {
1896                 if (asic_type < CHIP_VEGA12)
1897                         *states = ATTR_STATE_UNSUPPORTED;
1898         } else if (DEVICE_ATTR_IS(pp_dpm_vclk)) {
1899                 if (!(asic_type == CHIP_VANGOGH))
1900                         *states = ATTR_STATE_UNSUPPORTED;
1901         } else if (DEVICE_ATTR_IS(pp_dpm_dclk)) {
1902                 if (!(asic_type == CHIP_VANGOGH))
1903                         *states = ATTR_STATE_UNSUPPORTED;
1904         }
1905
1906         if (asic_type == CHIP_ARCTURUS) {
1907                 /* Arcturus does not support standalone mclk/socclk/fclk level setting */
1908                 if (DEVICE_ATTR_IS(pp_dpm_mclk) ||
1909                     DEVICE_ATTR_IS(pp_dpm_socclk) ||
1910                     DEVICE_ATTR_IS(pp_dpm_fclk)) {
1911                         dev_attr->attr.mode &= ~S_IWUGO;
1912                         dev_attr->store = NULL;
1913                 }
1914         }
1915
1916         if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) {
1917                 /* SMU MP1 does not support dcefclk level setting */
1918                 if (asic_type >= CHIP_NAVI10) {
1919                         dev_attr->attr.mode &= ~S_IWUGO;
1920                         dev_attr->store = NULL;
1921                 }
1922         }
1923
1924 #undef DEVICE_ATTR_IS
1925
1926         return 0;
1927 }
1928
1929
1930 static int amdgpu_device_attr_create(struct amdgpu_device *adev,
1931                                      struct amdgpu_device_attr *attr,
1932                                      uint32_t mask, struct list_head *attr_list)
1933 {
1934         int ret = 0;
1935         struct device_attribute *dev_attr = &attr->dev_attr;
1936         const char *name = dev_attr->attr.name;
1937         enum amdgpu_device_attr_states attr_states = ATTR_STATE_SUPPORTED;
1938         struct amdgpu_device_attr_entry *attr_entry;
1939
1940         int (*attr_update)(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
1941                            uint32_t mask, enum amdgpu_device_attr_states *states) = default_attr_update;
1942
1943         BUG_ON(!attr);
1944
1945         attr_update = attr->attr_update ? attr->attr_update : default_attr_update;
1946
1947         ret = attr_update(adev, attr, mask, &attr_states);
1948         if (ret) {
1949                 dev_err(adev->dev, "failed to update device file %s, ret = %d\n",
1950                         name, ret);
1951                 return ret;
1952         }
1953
1954         if (attr_states == ATTR_STATE_UNSUPPORTED)
1955                 return 0;
1956
1957         ret = device_create_file(adev->dev, dev_attr);
1958         if (ret) {
1959                 dev_err(adev->dev, "failed to create device file %s, ret = %d\n",
1960                         name, ret);
1961         }
1962
1963         attr_entry = kmalloc(sizeof(*attr_entry), GFP_KERNEL);
1964         if (!attr_entry)
1965                 return -ENOMEM;
1966
1967         attr_entry->attr = attr;
1968         INIT_LIST_HEAD(&attr_entry->entry);
1969
1970         list_add_tail(&attr_entry->entry, attr_list);
1971
1972         return ret;
1973 }
1974
1975 static void amdgpu_device_attr_remove(struct amdgpu_device *adev, struct amdgpu_device_attr *attr)
1976 {
1977         struct device_attribute *dev_attr = &attr->dev_attr;
1978
1979         device_remove_file(adev->dev, dev_attr);
1980 }
1981
1982 static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev,
1983                                              struct list_head *attr_list);
1984
1985 static int amdgpu_device_attr_create_groups(struct amdgpu_device *adev,
1986                                             struct amdgpu_device_attr *attrs,
1987                                             uint32_t counts,
1988                                             uint32_t mask,
1989                                             struct list_head *attr_list)
1990 {
1991         int ret = 0;
1992         uint32_t i = 0;
1993
1994         for (i = 0; i < counts; i++) {
1995                 ret = amdgpu_device_attr_create(adev, &attrs[i], mask, attr_list);
1996                 if (ret)
1997                         goto failed;
1998         }
1999
2000         return 0;
2001
2002 failed:
2003         amdgpu_device_attr_remove_groups(adev, attr_list);
2004
2005         return ret;
2006 }
2007
2008 static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev,
2009                                              struct list_head *attr_list)
2010 {
2011         struct amdgpu_device_attr_entry *entry, *entry_tmp;
2012
2013         if (list_empty(attr_list))
2014                 return ;
2015
2016         list_for_each_entry_safe(entry, entry_tmp, attr_list, entry) {
2017                 amdgpu_device_attr_remove(adev, entry->attr);
2018                 list_del(&entry->entry);
2019                 kfree(entry);
2020         }
2021 }
2022
2023 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
2024                                       struct device_attribute *attr,
2025                                       char *buf)
2026 {
2027         struct amdgpu_device *adev = dev_get_drvdata(dev);
2028         int channel = to_sensor_dev_attr(attr)->index;
2029         int r, temp = 0, size = sizeof(temp);
2030
2031         if (amdgpu_in_reset(adev))
2032                 return -EPERM;
2033         if (adev->in_suspend && !adev->in_runpm)
2034                 return -EPERM;
2035
2036         if (channel >= PP_TEMP_MAX)
2037                 return -EINVAL;
2038
2039         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2040         if (r < 0) {
2041                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2042                 return r;
2043         }
2044
2045         switch (channel) {
2046         case PP_TEMP_JUNCTION:
2047                 /* get current junction temperature */
2048                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
2049                                            (void *)&temp, &size);
2050                 break;
2051         case PP_TEMP_EDGE:
2052                 /* get current edge temperature */
2053                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_EDGE_TEMP,
2054                                            (void *)&temp, &size);
2055                 break;
2056         case PP_TEMP_MEM:
2057                 /* get current memory temperature */
2058                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_TEMP,
2059                                            (void *)&temp, &size);
2060                 break;
2061         default:
2062                 r = -EINVAL;
2063                 break;
2064         }
2065
2066         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2067         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2068
2069         if (r)
2070                 return r;
2071
2072         return sysfs_emit(buf, "%d\n", temp);
2073 }
2074
2075 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev,
2076                                              struct device_attribute *attr,
2077                                              char *buf)
2078 {
2079         struct amdgpu_device *adev = dev_get_drvdata(dev);
2080         int hyst = to_sensor_dev_attr(attr)->index;
2081         int temp;
2082
2083         if (hyst)
2084                 temp = adev->pm.dpm.thermal.min_temp;
2085         else
2086                 temp = adev->pm.dpm.thermal.max_temp;
2087
2088         return sysfs_emit(buf, "%d\n", temp);
2089 }
2090
2091 static ssize_t amdgpu_hwmon_show_hotspot_temp_thresh(struct device *dev,
2092                                              struct device_attribute *attr,
2093                                              char *buf)
2094 {
2095         struct amdgpu_device *adev = dev_get_drvdata(dev);
2096         int hyst = to_sensor_dev_attr(attr)->index;
2097         int temp;
2098
2099         if (hyst)
2100                 temp = adev->pm.dpm.thermal.min_hotspot_temp;
2101         else
2102                 temp = adev->pm.dpm.thermal.max_hotspot_crit_temp;
2103
2104         return sysfs_emit(buf, "%d\n", temp);
2105 }
2106
2107 static ssize_t amdgpu_hwmon_show_mem_temp_thresh(struct device *dev,
2108                                              struct device_attribute *attr,
2109                                              char *buf)
2110 {
2111         struct amdgpu_device *adev = dev_get_drvdata(dev);
2112         int hyst = to_sensor_dev_attr(attr)->index;
2113         int temp;
2114
2115         if (hyst)
2116                 temp = adev->pm.dpm.thermal.min_mem_temp;
2117         else
2118                 temp = adev->pm.dpm.thermal.max_mem_crit_temp;
2119
2120         return sysfs_emit(buf, "%d\n", temp);
2121 }
2122
2123 static ssize_t amdgpu_hwmon_show_temp_label(struct device *dev,
2124                                              struct device_attribute *attr,
2125                                              char *buf)
2126 {
2127         int channel = to_sensor_dev_attr(attr)->index;
2128
2129         if (channel >= PP_TEMP_MAX)
2130                 return -EINVAL;
2131
2132         return sysfs_emit(buf, "%s\n", temp_label[channel].label);
2133 }
2134
2135 static ssize_t amdgpu_hwmon_show_temp_emergency(struct device *dev,
2136                                              struct device_attribute *attr,
2137                                              char *buf)
2138 {
2139         struct amdgpu_device *adev = dev_get_drvdata(dev);
2140         int channel = to_sensor_dev_attr(attr)->index;
2141         int temp = 0;
2142
2143         if (channel >= PP_TEMP_MAX)
2144                 return -EINVAL;
2145
2146         switch (channel) {
2147         case PP_TEMP_JUNCTION:
2148                 temp = adev->pm.dpm.thermal.max_hotspot_emergency_temp;
2149                 break;
2150         case PP_TEMP_EDGE:
2151                 temp = adev->pm.dpm.thermal.max_edge_emergency_temp;
2152                 break;
2153         case PP_TEMP_MEM:
2154                 temp = adev->pm.dpm.thermal.max_mem_emergency_temp;
2155                 break;
2156         }
2157
2158         return sysfs_emit(buf, "%d\n", temp);
2159 }
2160
2161 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
2162                                             struct device_attribute *attr,
2163                                             char *buf)
2164 {
2165         struct amdgpu_device *adev = dev_get_drvdata(dev);
2166         u32 pwm_mode = 0;
2167         int ret;
2168
2169         if (amdgpu_in_reset(adev))
2170                 return -EPERM;
2171         if (adev->in_suspend && !adev->in_runpm)
2172                 return -EPERM;
2173
2174         ret = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2175         if (ret < 0) {
2176                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2177                 return ret;
2178         }
2179
2180         if (!adev->powerplay.pp_funcs->get_fan_control_mode) {
2181                 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2182                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2183                 return -EINVAL;
2184         }
2185
2186         pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
2187
2188         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2189         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2190
2191         return sprintf(buf, "%u\n", pwm_mode);
2192 }
2193
2194 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
2195                                             struct device_attribute *attr,
2196                                             const char *buf,
2197                                             size_t count)
2198 {
2199         struct amdgpu_device *adev = dev_get_drvdata(dev);
2200         int err, ret;
2201         int value;
2202
2203         if (amdgpu_in_reset(adev))
2204                 return -EPERM;
2205         if (adev->in_suspend && !adev->in_runpm)
2206                 return -EPERM;
2207
2208         err = kstrtoint(buf, 10, &value);
2209         if (err)
2210                 return err;
2211
2212         ret = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2213         if (ret < 0) {
2214                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2215                 return ret;
2216         }
2217
2218         if (!adev->powerplay.pp_funcs->set_fan_control_mode) {
2219                 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2220                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2221                 return -EINVAL;
2222         }
2223
2224         amdgpu_dpm_set_fan_control_mode(adev, value);
2225
2226         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2227         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2228
2229         return count;
2230 }
2231
2232 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev,
2233                                          struct device_attribute *attr,
2234                                          char *buf)
2235 {
2236         return sprintf(buf, "%i\n", 0);
2237 }
2238
2239 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev,
2240                                          struct device_attribute *attr,
2241                                          char *buf)
2242 {
2243         return sprintf(buf, "%i\n", 255);
2244 }
2245
2246 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
2247                                      struct device_attribute *attr,
2248                                      const char *buf, size_t count)
2249 {
2250         struct amdgpu_device *adev = dev_get_drvdata(dev);
2251         int err;
2252         u32 value;
2253         u32 pwm_mode;
2254
2255         if (amdgpu_in_reset(adev))
2256                 return -EPERM;
2257         if (adev->in_suspend && !adev->in_runpm)
2258                 return -EPERM;
2259
2260         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2261         if (err < 0) {
2262                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2263                 return err;
2264         }
2265
2266         pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
2267         if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
2268                 pr_info("manual fan speed control should be enabled first\n");
2269                 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2270                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2271                 return -EINVAL;
2272         }
2273
2274         err = kstrtou32(buf, 10, &value);
2275         if (err) {
2276                 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2277                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2278                 return err;
2279         }
2280
2281         value = (value * 100) / 255;
2282
2283         if (adev->powerplay.pp_funcs->set_fan_speed_percent)
2284                 err = amdgpu_dpm_set_fan_speed_percent(adev, value);
2285         else
2286                 err = -EINVAL;
2287
2288         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2289         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2290
2291         if (err)
2292                 return err;
2293
2294         return count;
2295 }
2296
2297 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
2298                                      struct device_attribute *attr,
2299                                      char *buf)
2300 {
2301         struct amdgpu_device *adev = dev_get_drvdata(dev);
2302         int err;
2303         u32 speed = 0;
2304
2305         if (amdgpu_in_reset(adev))
2306                 return -EPERM;
2307         if (adev->in_suspend && !adev->in_runpm)
2308                 return -EPERM;
2309
2310         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2311         if (err < 0) {
2312                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2313                 return err;
2314         }
2315
2316         if (adev->powerplay.pp_funcs->get_fan_speed_percent)
2317                 err = amdgpu_dpm_get_fan_speed_percent(adev, &speed);
2318         else
2319                 err = -EINVAL;
2320
2321         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2322         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2323
2324         if (err)
2325                 return err;
2326
2327         speed = (speed * 255) / 100;
2328
2329         return sprintf(buf, "%i\n", speed);
2330 }
2331
2332 static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
2333                                            struct device_attribute *attr,
2334                                            char *buf)
2335 {
2336         struct amdgpu_device *adev = dev_get_drvdata(dev);
2337         int err;
2338         u32 speed = 0;
2339
2340         if (amdgpu_in_reset(adev))
2341                 return -EPERM;
2342         if (adev->in_suspend && !adev->in_runpm)
2343                 return -EPERM;
2344
2345         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2346         if (err < 0) {
2347                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2348                 return err;
2349         }
2350
2351         if (adev->powerplay.pp_funcs->get_fan_speed_rpm)
2352                 err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
2353         else
2354                 err = -EINVAL;
2355
2356         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2357         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2358
2359         if (err)
2360                 return err;
2361
2362         return sprintf(buf, "%i\n", speed);
2363 }
2364
2365 static ssize_t amdgpu_hwmon_get_fan1_min(struct device *dev,
2366                                          struct device_attribute *attr,
2367                                          char *buf)
2368 {
2369         struct amdgpu_device *adev = dev_get_drvdata(dev);
2370         u32 min_rpm = 0;
2371         u32 size = sizeof(min_rpm);
2372         int r;
2373
2374         if (amdgpu_in_reset(adev))
2375                 return -EPERM;
2376         if (adev->in_suspend && !adev->in_runpm)
2377                 return -EPERM;
2378
2379         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2380         if (r < 0) {
2381                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2382                 return r;
2383         }
2384
2385         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MIN_FAN_RPM,
2386                                    (void *)&min_rpm, &size);
2387
2388         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2389         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2390
2391         if (r)
2392                 return r;
2393
2394         return sysfs_emit(buf, "%d\n", min_rpm);
2395 }
2396
2397 static ssize_t amdgpu_hwmon_get_fan1_max(struct device *dev,
2398                                          struct device_attribute *attr,
2399                                          char *buf)
2400 {
2401         struct amdgpu_device *adev = dev_get_drvdata(dev);
2402         u32 max_rpm = 0;
2403         u32 size = sizeof(max_rpm);
2404         int r;
2405
2406         if (amdgpu_in_reset(adev))
2407                 return -EPERM;
2408         if (adev->in_suspend && !adev->in_runpm)
2409                 return -EPERM;
2410
2411         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2412         if (r < 0) {
2413                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2414                 return r;
2415         }
2416
2417         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MAX_FAN_RPM,
2418                                    (void *)&max_rpm, &size);
2419
2420         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2421         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2422
2423         if (r)
2424                 return r;
2425
2426         return sysfs_emit(buf, "%d\n", max_rpm);
2427 }
2428
2429 static ssize_t amdgpu_hwmon_get_fan1_target(struct device *dev,
2430                                            struct device_attribute *attr,
2431                                            char *buf)
2432 {
2433         struct amdgpu_device *adev = dev_get_drvdata(dev);
2434         int err;
2435         u32 rpm = 0;
2436
2437         if (amdgpu_in_reset(adev))
2438                 return -EPERM;
2439         if (adev->in_suspend && !adev->in_runpm)
2440                 return -EPERM;
2441
2442         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2443         if (err < 0) {
2444                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2445                 return err;
2446         }
2447
2448         if (adev->powerplay.pp_funcs->get_fan_speed_rpm)
2449                 err = amdgpu_dpm_get_fan_speed_rpm(adev, &rpm);
2450         else
2451                 err = -EINVAL;
2452
2453         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2454         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2455
2456         if (err)
2457                 return err;
2458
2459         return sprintf(buf, "%i\n", rpm);
2460 }
2461
2462 static ssize_t amdgpu_hwmon_set_fan1_target(struct device *dev,
2463                                      struct device_attribute *attr,
2464                                      const char *buf, size_t count)
2465 {
2466         struct amdgpu_device *adev = dev_get_drvdata(dev);
2467         int err;
2468         u32 value;
2469         u32 pwm_mode;
2470
2471         if (amdgpu_in_reset(adev))
2472                 return -EPERM;
2473         if (adev->in_suspend && !adev->in_runpm)
2474                 return -EPERM;
2475
2476         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2477         if (err < 0) {
2478                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2479                 return err;
2480         }
2481
2482         pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
2483
2484         if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
2485                 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2486                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2487                 return -ENODATA;
2488         }
2489
2490         err = kstrtou32(buf, 10, &value);
2491         if (err) {
2492                 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2493                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2494                 return err;
2495         }
2496
2497         if (adev->powerplay.pp_funcs->set_fan_speed_rpm)
2498                 err = amdgpu_dpm_set_fan_speed_rpm(adev, value);
2499         else
2500                 err = -EINVAL;
2501
2502         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2503         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2504
2505         if (err)
2506                 return err;
2507
2508         return count;
2509 }
2510
2511 static ssize_t amdgpu_hwmon_get_fan1_enable(struct device *dev,
2512                                             struct device_attribute *attr,
2513                                             char *buf)
2514 {
2515         struct amdgpu_device *adev = dev_get_drvdata(dev);
2516         u32 pwm_mode = 0;
2517         int ret;
2518
2519         if (amdgpu_in_reset(adev))
2520                 return -EPERM;
2521         if (adev->in_suspend && !adev->in_runpm)
2522                 return -EPERM;
2523
2524         ret = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2525         if (ret < 0) {
2526                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2527                 return ret;
2528         }
2529
2530         if (!adev->powerplay.pp_funcs->get_fan_control_mode) {
2531                 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2532                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2533                 return -EINVAL;
2534         }
2535
2536         pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
2537
2538         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2539         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2540
2541         return sprintf(buf, "%i\n", pwm_mode == AMD_FAN_CTRL_AUTO ? 0 : 1);
2542 }
2543
2544 static ssize_t amdgpu_hwmon_set_fan1_enable(struct device *dev,
2545                                             struct device_attribute *attr,
2546                                             const char *buf,
2547                                             size_t count)
2548 {
2549         struct amdgpu_device *adev = dev_get_drvdata(dev);
2550         int err;
2551         int value;
2552         u32 pwm_mode;
2553
2554         if (amdgpu_in_reset(adev))
2555                 return -EPERM;
2556         if (adev->in_suspend && !adev->in_runpm)
2557                 return -EPERM;
2558
2559         err = kstrtoint(buf, 10, &value);
2560         if (err)
2561                 return err;
2562
2563         if (value == 0)
2564                 pwm_mode = AMD_FAN_CTRL_AUTO;
2565         else if (value == 1)
2566                 pwm_mode = AMD_FAN_CTRL_MANUAL;
2567         else
2568                 return -EINVAL;
2569
2570         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2571         if (err < 0) {
2572                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2573                 return err;
2574         }
2575
2576         if (!adev->powerplay.pp_funcs->set_fan_control_mode) {
2577                 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2578                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2579                 return -EINVAL;
2580         }
2581         amdgpu_dpm_set_fan_control_mode(adev, pwm_mode);
2582
2583         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2584         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2585
2586         return count;
2587 }
2588
2589 static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev,
2590                                         struct device_attribute *attr,
2591                                         char *buf)
2592 {
2593         struct amdgpu_device *adev = dev_get_drvdata(dev);
2594         u32 vddgfx;
2595         int r, size = sizeof(vddgfx);
2596
2597         if (amdgpu_in_reset(adev))
2598                 return -EPERM;
2599         if (adev->in_suspend && !adev->in_runpm)
2600                 return -EPERM;
2601
2602         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2603         if (r < 0) {
2604                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2605                 return r;
2606         }
2607
2608         /* get the voltage */
2609         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX,
2610                                    (void *)&vddgfx, &size);
2611
2612         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2613         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2614
2615         if (r)
2616                 return r;
2617
2618         return sysfs_emit(buf, "%d\n", vddgfx);
2619 }
2620
2621 static ssize_t amdgpu_hwmon_show_vddgfx_label(struct device *dev,
2622                                               struct device_attribute *attr,
2623                                               char *buf)
2624 {
2625         return sysfs_emit(buf, "vddgfx\n");
2626 }
2627
2628 static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev,
2629                                        struct device_attribute *attr,
2630                                        char *buf)
2631 {
2632         struct amdgpu_device *adev = dev_get_drvdata(dev);
2633         u32 vddnb;
2634         int r, size = sizeof(vddnb);
2635
2636         if (amdgpu_in_reset(adev))
2637                 return -EPERM;
2638         if (adev->in_suspend && !adev->in_runpm)
2639                 return -EPERM;
2640
2641         /* only APUs have vddnb */
2642         if  (!(adev->flags & AMD_IS_APU))
2643                 return -EINVAL;
2644
2645         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2646         if (r < 0) {
2647                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2648                 return r;
2649         }
2650
2651         /* get the voltage */
2652         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB,
2653                                    (void *)&vddnb, &size);
2654
2655         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2656         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2657
2658         if (r)
2659                 return r;
2660
2661         return sysfs_emit(buf, "%d\n", vddnb);
2662 }
2663
2664 static ssize_t amdgpu_hwmon_show_vddnb_label(struct device *dev,
2665                                               struct device_attribute *attr,
2666                                               char *buf)
2667 {
2668         return sysfs_emit(buf, "vddnb\n");
2669 }
2670
2671 static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev,
2672                                            struct device_attribute *attr,
2673                                            char *buf)
2674 {
2675         struct amdgpu_device *adev = dev_get_drvdata(dev);
2676         u32 query = 0;
2677         int r, size = sizeof(u32);
2678         unsigned uw;
2679
2680         if (amdgpu_in_reset(adev))
2681                 return -EPERM;
2682         if (adev->in_suspend && !adev->in_runpm)
2683                 return -EPERM;
2684
2685         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2686         if (r < 0) {
2687                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2688                 return r;
2689         }
2690
2691         /* get the voltage */
2692         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER,
2693                                    (void *)&query, &size);
2694
2695         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2696         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2697
2698         if (r)
2699                 return r;
2700
2701         /* convert to microwatts */
2702         uw = (query >> 8) * 1000000 + (query & 0xff) * 1000;
2703
2704         return sysfs_emit(buf, "%u\n", uw);
2705 }
2706
2707 static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev,
2708                                          struct device_attribute *attr,
2709                                          char *buf)
2710 {
2711         return sprintf(buf, "%i\n", 0);
2712 }
2713
2714 static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
2715                                          struct device_attribute *attr,
2716                                          char *buf)
2717 {
2718         struct amdgpu_device *adev = dev_get_drvdata(dev);
2719         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
2720         int limit_type = to_sensor_dev_attr(attr)->index;
2721         uint32_t limit = limit_type << 24;
2722         uint32_t max_limit = 0;
2723         ssize_t size;
2724         int r;
2725
2726         if (amdgpu_in_reset(adev))
2727                 return -EPERM;
2728         if (adev->in_suspend && !adev->in_runpm)
2729                 return -EPERM;
2730
2731         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2732         if (r < 0) {
2733                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2734                 return r;
2735         }
2736
2737         if (is_support_sw_smu(adev)) {
2738                 smu_get_power_limit(&adev->smu, &limit, SMU_PPT_LIMIT_MAX);
2739                 size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
2740         } else if (pp_funcs && pp_funcs->get_power_limit) {
2741                 pp_funcs->get_power_limit(adev->powerplay.pp_handle,
2742                                 &limit, &max_limit, true);
2743                 size = snprintf(buf, PAGE_SIZE, "%u\n", max_limit * 1000000);
2744         } else {
2745                 size = snprintf(buf, PAGE_SIZE, "\n");
2746         }
2747
2748         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2749         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2750
2751         return size;
2752 }
2753
2754 static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
2755                                          struct device_attribute *attr,
2756                                          char *buf)
2757 {
2758         struct amdgpu_device *adev = dev_get_drvdata(dev);
2759         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
2760         int limit_type = to_sensor_dev_attr(attr)->index;
2761         uint32_t limit = limit_type << 24;
2762         ssize_t size;
2763         int r;
2764
2765         if (amdgpu_in_reset(adev))
2766                 return -EPERM;
2767         if (adev->in_suspend && !adev->in_runpm)
2768                 return -EPERM;
2769
2770         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2771         if (r < 0) {
2772                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2773                 return r;
2774         }
2775
2776         if (is_support_sw_smu(adev)) {
2777                 smu_get_power_limit(&adev->smu, &limit, SMU_PPT_LIMIT_CURRENT);
2778                 size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
2779         } else if (pp_funcs && pp_funcs->get_power_limit) {
2780                 pp_funcs->get_power_limit(adev->powerplay.pp_handle,
2781                                 &limit, NULL, false);
2782                 size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
2783         } else {
2784                 size = snprintf(buf, PAGE_SIZE, "\n");
2785         }
2786
2787         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2788         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2789
2790         return size;
2791 }
2792
2793 static ssize_t amdgpu_hwmon_show_power_cap_default(struct device *dev,
2794                                          struct device_attribute *attr,
2795                                          char *buf)
2796 {
2797         struct amdgpu_device *adev = dev_get_drvdata(dev);
2798         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
2799         int limit_type = to_sensor_dev_attr(attr)->index;
2800         uint32_t limit = limit_type << 24;
2801         ssize_t size;
2802         int r;
2803
2804         if (amdgpu_in_reset(adev))
2805                 return -EPERM;
2806         if (adev->in_suspend && !adev->in_runpm)
2807                 return -EPERM;
2808
2809         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2810         if (r < 0) {
2811                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2812                 return r;
2813         }
2814
2815         if (is_support_sw_smu(adev)) {
2816                 smu_get_power_limit(&adev->smu, &limit, SMU_PPT_LIMIT_DEFAULT);
2817                 size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
2818         } else if (pp_funcs && pp_funcs->get_power_limit) {
2819                 pp_funcs->get_power_limit(adev->powerplay.pp_handle,
2820                                 &limit, NULL, true);
2821                 size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
2822         } else {
2823                 size = snprintf(buf, PAGE_SIZE, "\n");
2824         }
2825
2826         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2827         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2828
2829         return size;
2830 }
2831 static ssize_t amdgpu_hwmon_show_power_label(struct device *dev,
2832                                          struct device_attribute *attr,
2833                                          char *buf)
2834 {
2835         int limit_type = to_sensor_dev_attr(attr)->index;
2836
2837         return sysfs_emit(buf, "%s\n",
2838                 limit_type == SMU_FAST_PPT_LIMIT ? "fastPPT" : "slowPPT");
2839 }
2840
2841 static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
2842                 struct device_attribute *attr,
2843                 const char *buf,
2844                 size_t count)
2845 {
2846         struct amdgpu_device *adev = dev_get_drvdata(dev);
2847         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
2848         int limit_type = to_sensor_dev_attr(attr)->index;
2849         int err;
2850         u32 value;
2851
2852         if (amdgpu_in_reset(adev))
2853                 return -EPERM;
2854         if (adev->in_suspend && !adev->in_runpm)
2855                 return -EPERM;
2856
2857         if (amdgpu_sriov_vf(adev))
2858                 return -EINVAL;
2859
2860         err = kstrtou32(buf, 10, &value);
2861         if (err)
2862                 return err;
2863
2864         value = value / 1000000; /* convert to Watt */
2865         value |= limit_type << 24;
2866
2867         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2868         if (err < 0) {
2869                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2870                 return err;
2871         }
2872
2873         if (pp_funcs && pp_funcs->set_power_limit)
2874                 err = pp_funcs->set_power_limit(adev->powerplay.pp_handle, value);
2875         else
2876                 err = -EINVAL;
2877
2878         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2879         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2880
2881         if (err)
2882                 return err;
2883
2884         return count;
2885 }
2886
2887 static ssize_t amdgpu_hwmon_show_sclk(struct device *dev,
2888                                       struct device_attribute *attr,
2889                                       char *buf)
2890 {
2891         struct amdgpu_device *adev = dev_get_drvdata(dev);
2892         uint32_t sclk;
2893         int r, size = sizeof(sclk);
2894
2895         if (amdgpu_in_reset(adev))
2896                 return -EPERM;
2897         if (adev->in_suspend && !adev->in_runpm)
2898                 return -EPERM;
2899
2900         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2901         if (r < 0) {
2902                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2903                 return r;
2904         }
2905
2906         /* get the sclk */
2907         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK,
2908                                    (void *)&sclk, &size);
2909
2910         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2911         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2912
2913         if (r)
2914                 return r;
2915
2916         return sysfs_emit(buf, "%u\n", sclk * 10 * 1000);
2917 }
2918
2919 static ssize_t amdgpu_hwmon_show_sclk_label(struct device *dev,
2920                                             struct device_attribute *attr,
2921                                             char *buf)
2922 {
2923         return sysfs_emit(buf, "sclk\n");
2924 }
2925
2926 static ssize_t amdgpu_hwmon_show_mclk(struct device *dev,
2927                                       struct device_attribute *attr,
2928                                       char *buf)
2929 {
2930         struct amdgpu_device *adev = dev_get_drvdata(dev);
2931         uint32_t mclk;
2932         int r, size = sizeof(mclk);
2933
2934         if (amdgpu_in_reset(adev))
2935                 return -EPERM;
2936         if (adev->in_suspend && !adev->in_runpm)
2937                 return -EPERM;
2938
2939         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2940         if (r < 0) {
2941                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2942                 return r;
2943         }
2944
2945         /* get the sclk */
2946         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK,
2947                                    (void *)&mclk, &size);
2948
2949         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2950         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2951
2952         if (r)
2953                 return r;
2954
2955         return sysfs_emit(buf, "%u\n", mclk * 10 * 1000);
2956 }
2957
2958 static ssize_t amdgpu_hwmon_show_mclk_label(struct device *dev,
2959                                             struct device_attribute *attr,
2960                                             char *buf)
2961 {
2962         return sysfs_emit(buf, "mclk\n");
2963 }
2964
2965 /**
2966  * DOC: hwmon
2967  *
2968  * The amdgpu driver exposes the following sensor interfaces:
2969  *
2970  * - GPU temperature (via the on-die sensor)
2971  *
2972  * - GPU voltage
2973  *
2974  * - Northbridge voltage (APUs only)
2975  *
2976  * - GPU power
2977  *
2978  * - GPU fan
2979  *
2980  * - GPU gfx/compute engine clock
2981  *
2982  * - GPU memory clock (dGPU only)
2983  *
2984  * hwmon interfaces for GPU temperature:
2985  *
2986  * - temp[1-3]_input: the on die GPU temperature in millidegrees Celsius
2987  *   - temp2_input and temp3_input are supported on SOC15 dGPUs only
2988  *
2989  * - temp[1-3]_label: temperature channel label
2990  *   - temp2_label and temp3_label are supported on SOC15 dGPUs only
2991  *
2992  * - temp[1-3]_crit: temperature critical max value in millidegrees Celsius
2993  *   - temp2_crit and temp3_crit are supported on SOC15 dGPUs only
2994  *
2995  * - temp[1-3]_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius
2996  *   - temp2_crit_hyst and temp3_crit_hyst are supported on SOC15 dGPUs only
2997  *
2998  * - temp[1-3]_emergency: temperature emergency max value(asic shutdown) in millidegrees Celsius
2999  *   - these are supported on SOC15 dGPUs only
3000  *
3001  * hwmon interfaces for GPU voltage:
3002  *
3003  * - in0_input: the voltage on the GPU in millivolts
3004  *
3005  * - in1_input: the voltage on the Northbridge in millivolts
3006  *
3007  * hwmon interfaces for GPU power:
3008  *
3009  * - power1_average: average power used by the GPU in microWatts
3010  *
3011  * - power1_cap_min: minimum cap supported in microWatts
3012  *
3013  * - power1_cap_max: maximum cap supported in microWatts
3014  *
3015  * - power1_cap: selected power cap in microWatts
3016  *
3017  * hwmon interfaces for GPU fan:
3018  *
3019  * - pwm1: pulse width modulation fan level (0-255)
3020  *
3021  * - pwm1_enable: pulse width modulation fan control method (0: no fan speed control, 1: manual fan speed control using pwm interface, 2: automatic fan speed control)
3022  *
3023  * - pwm1_min: pulse width modulation fan control minimum level (0)
3024  *
3025  * - pwm1_max: pulse width modulation fan control maximum level (255)
3026  *
3027  * - fan1_min: a minimum value Unit: revolution/min (RPM)
3028  *
3029  * - fan1_max: a maximum value Unit: revolution/max (RPM)
3030  *
3031  * - fan1_input: fan speed in RPM
3032  *
3033  * - fan[1-\*]_target: Desired fan speed Unit: revolution/min (RPM)
3034  *
3035  * - fan[1-\*]_enable: Enable or disable the sensors.1: Enable 0: Disable
3036  *
3037  * hwmon interfaces for GPU clocks:
3038  *
3039  * - freq1_input: the gfx/compute clock in hertz
3040  *
3041  * - freq2_input: the memory clock in hertz
3042  *
3043  * You can use hwmon tools like sensors to view this information on your system.
3044  *
3045  */
3046
3047 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_EDGE);
3048 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
3049 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
3050 static SENSOR_DEVICE_ATTR(temp1_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_EDGE);
3051 static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_JUNCTION);
3052 static SENSOR_DEVICE_ATTR(temp2_crit, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 0);
3053 static SENSOR_DEVICE_ATTR(temp2_crit_hyst, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 1);
3054 static SENSOR_DEVICE_ATTR(temp2_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_JUNCTION);
3055 static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_MEM);
3056 static SENSOR_DEVICE_ATTR(temp3_crit, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 0);
3057 static SENSOR_DEVICE_ATTR(temp3_crit_hyst, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 1);
3058 static SENSOR_DEVICE_ATTR(temp3_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_MEM);
3059 static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_EDGE);
3060 static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_JUNCTION);
3061 static SENSOR_DEVICE_ATTR(temp3_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_MEM);
3062 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);
3063 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
3064 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
3065 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
3066 static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0);
3067 static SENSOR_DEVICE_ATTR(fan1_min, S_IRUGO, amdgpu_hwmon_get_fan1_min, NULL, 0);
3068 static SENSOR_DEVICE_ATTR(fan1_max, S_IRUGO, amdgpu_hwmon_get_fan1_max, NULL, 0);
3069 static SENSOR_DEVICE_ATTR(fan1_target, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_target, amdgpu_hwmon_set_fan1_target, 0);
3070 static SENSOR_DEVICE_ATTR(fan1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_enable, amdgpu_hwmon_set_fan1_enable, 0);
3071 static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 0);
3072 static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, NULL, 0);
3073 static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0);
3074 static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0);
3075 static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0);
3076 static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0);
3077 static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0);
3078 static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0);
3079 static SENSOR_DEVICE_ATTR(power1_cap_default, S_IRUGO, amdgpu_hwmon_show_power_cap_default, NULL, 0);
3080 static SENSOR_DEVICE_ATTR(power1_label, S_IRUGO, amdgpu_hwmon_show_power_label, NULL, 0);
3081 static SENSOR_DEVICE_ATTR(power2_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 1);
3082 static SENSOR_DEVICE_ATTR(power2_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 1);
3083 static SENSOR_DEVICE_ATTR(power2_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 1);
3084 static SENSOR_DEVICE_ATTR(power2_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 1);
3085 static SENSOR_DEVICE_ATTR(power2_cap_default, S_IRUGO, amdgpu_hwmon_show_power_cap_default, NULL, 1);
3086 static SENSOR_DEVICE_ATTR(power2_label, S_IRUGO, amdgpu_hwmon_show_power_label, NULL, 1);
3087 static SENSOR_DEVICE_ATTR(freq1_input, S_IRUGO, amdgpu_hwmon_show_sclk, NULL, 0);
3088 static SENSOR_DEVICE_ATTR(freq1_label, S_IRUGO, amdgpu_hwmon_show_sclk_label, NULL, 0);
3089 static SENSOR_DEVICE_ATTR(freq2_input, S_IRUGO, amdgpu_hwmon_show_mclk, NULL, 0);
3090 static SENSOR_DEVICE_ATTR(freq2_label, S_IRUGO, amdgpu_hwmon_show_mclk_label, NULL, 0);
3091
3092 static struct attribute *hwmon_attributes[] = {
3093         &sensor_dev_attr_temp1_input.dev_attr.attr,
3094         &sensor_dev_attr_temp1_crit.dev_attr.attr,
3095         &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
3096         &sensor_dev_attr_temp2_input.dev_attr.attr,
3097         &sensor_dev_attr_temp2_crit.dev_attr.attr,
3098         &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr,
3099         &sensor_dev_attr_temp3_input.dev_attr.attr,
3100         &sensor_dev_attr_temp3_crit.dev_attr.attr,
3101         &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr,
3102         &sensor_dev_attr_temp1_emergency.dev_attr.attr,
3103         &sensor_dev_attr_temp2_emergency.dev_attr.attr,
3104         &sensor_dev_attr_temp3_emergency.dev_attr.attr,
3105         &sensor_dev_attr_temp1_label.dev_attr.attr,
3106         &sensor_dev_attr_temp2_label.dev_attr.attr,
3107         &sensor_dev_attr_temp3_label.dev_attr.attr,
3108         &sensor_dev_attr_pwm1.dev_attr.attr,
3109         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
3110         &sensor_dev_attr_pwm1_min.dev_attr.attr,
3111         &sensor_dev_attr_pwm1_max.dev_attr.attr,
3112         &sensor_dev_attr_fan1_input.dev_attr.attr,
3113         &sensor_dev_attr_fan1_min.dev_attr.attr,
3114         &sensor_dev_attr_fan1_max.dev_attr.attr,
3115         &sensor_dev_attr_fan1_target.dev_attr.attr,
3116         &sensor_dev_attr_fan1_enable.dev_attr.attr,
3117         &sensor_dev_attr_in0_input.dev_attr.attr,
3118         &sensor_dev_attr_in0_label.dev_attr.attr,
3119         &sensor_dev_attr_in1_input.dev_attr.attr,
3120         &sensor_dev_attr_in1_label.dev_attr.attr,
3121         &sensor_dev_attr_power1_average.dev_attr.attr,
3122         &sensor_dev_attr_power1_cap_max.dev_attr.attr,
3123         &sensor_dev_attr_power1_cap_min.dev_attr.attr,
3124         &sensor_dev_attr_power1_cap.dev_attr.attr,
3125         &sensor_dev_attr_power1_cap_default.dev_attr.attr,
3126         &sensor_dev_attr_power1_label.dev_attr.attr,
3127         &sensor_dev_attr_power2_average.dev_attr.attr,
3128         &sensor_dev_attr_power2_cap_max.dev_attr.attr,
3129         &sensor_dev_attr_power2_cap_min.dev_attr.attr,
3130         &sensor_dev_attr_power2_cap.dev_attr.attr,
3131         &sensor_dev_attr_power2_cap_default.dev_attr.attr,
3132         &sensor_dev_attr_power2_label.dev_attr.attr,
3133         &sensor_dev_attr_freq1_input.dev_attr.attr,
3134         &sensor_dev_attr_freq1_label.dev_attr.attr,
3135         &sensor_dev_attr_freq2_input.dev_attr.attr,
3136         &sensor_dev_attr_freq2_label.dev_attr.attr,
3137         NULL
3138 };
3139
3140 static umode_t hwmon_attributes_visible(struct kobject *kobj,
3141                                         struct attribute *attr, int index)
3142 {
3143         struct device *dev = kobj_to_dev(kobj);
3144         struct amdgpu_device *adev = dev_get_drvdata(dev);
3145         umode_t effective_mode = attr->mode;
3146
3147         /* under multi-vf mode, the hwmon attributes are all not supported */
3148         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
3149                 return 0;
3150
3151         /* there is no fan under pp one vf mode */
3152         if (amdgpu_sriov_is_pp_one_vf(adev) &&
3153             (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3154              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3155              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3156              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3157              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3158              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3159              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3160              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3161              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3162                 return 0;
3163
3164         /* Skip fan attributes if fan is not present */
3165         if (adev->pm.no_fan && (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3166             attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3167             attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3168             attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3169             attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3170             attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3171             attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3172             attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3173             attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3174                 return 0;
3175
3176         /* Skip fan attributes on APU */
3177         if ((adev->flags & AMD_IS_APU) &&
3178             (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3179              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3180              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3181              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3182              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3183              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3184              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3185              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3186              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3187                 return 0;
3188
3189         /* Skip crit temp on APU */
3190         if ((adev->flags & AMD_IS_APU) && (adev->family >= AMDGPU_FAMILY_CZ) &&
3191             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
3192              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr))
3193                 return 0;
3194
3195         /* Skip limit attributes if DPM is not enabled */
3196         if (!adev->pm.dpm_enabled &&
3197             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
3198              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
3199              attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3200              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3201              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3202              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3203              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3204              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3205              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3206              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3207              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3208                 return 0;
3209
3210         if (!is_support_sw_smu(adev)) {
3211                 /* mask fan attributes if we have no bindings for this asic to expose */
3212                 if ((!adev->powerplay.pp_funcs->get_fan_speed_percent &&
3213                      attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
3214                     (!adev->powerplay.pp_funcs->get_fan_control_mode &&
3215                      attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
3216                         effective_mode &= ~S_IRUGO;
3217
3218                 if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
3219                      attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
3220                     (!adev->powerplay.pp_funcs->set_fan_control_mode &&
3221                      attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
3222                         effective_mode &= ~S_IWUSR;
3223         }
3224
3225         if (((adev->family == AMDGPU_FAMILY_SI) ||
3226                  ((adev->flags & AMD_IS_APU) &&
3227               (adev->asic_type != CHIP_VANGOGH))) &&    /* not implemented yet */
3228             (attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||
3229              attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr||
3230              attr == &sensor_dev_attr_power1_cap.dev_attr.attr ||
3231              attr == &sensor_dev_attr_power1_cap_default.dev_attr.attr))
3232                 return 0;
3233
3234         if (((adev->family == AMDGPU_FAMILY_SI) ||
3235              ((adev->flags & AMD_IS_APU) &&
3236               (adev->asic_type < CHIP_RENOIR))) &&      /* not implemented yet */
3237             (attr == &sensor_dev_attr_power1_average.dev_attr.attr))
3238                 return 0;
3239
3240         if (!is_support_sw_smu(adev)) {
3241                 /* hide max/min values if we can't both query and manage the fan */
3242                 if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
3243                      !adev->powerplay.pp_funcs->get_fan_speed_percent) &&
3244                      (!adev->powerplay.pp_funcs->set_fan_speed_rpm &&
3245                      !adev->powerplay.pp_funcs->get_fan_speed_rpm) &&
3246                     (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3247                      attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
3248                         return 0;
3249
3250                 if ((!adev->powerplay.pp_funcs->set_fan_speed_rpm &&
3251                      !adev->powerplay.pp_funcs->get_fan_speed_rpm) &&
3252                     (attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3253                      attr == &sensor_dev_attr_fan1_min.dev_attr.attr))
3254                         return 0;
3255         }
3256
3257         if ((adev->family == AMDGPU_FAMILY_SI ||        /* not implemented yet */
3258              adev->family == AMDGPU_FAMILY_KV) &&       /* not implemented yet */
3259             (attr == &sensor_dev_attr_in0_input.dev_attr.attr ||
3260              attr == &sensor_dev_attr_in0_label.dev_attr.attr))
3261                 return 0;
3262
3263         /* only APUs have vddnb */
3264         if (!(adev->flags & AMD_IS_APU) &&
3265             (attr == &sensor_dev_attr_in1_input.dev_attr.attr ||
3266              attr == &sensor_dev_attr_in1_label.dev_attr.attr))
3267                 return 0;
3268
3269         /* no mclk on APUs */
3270         if ((adev->flags & AMD_IS_APU) &&
3271             (attr == &sensor_dev_attr_freq2_input.dev_attr.attr ||
3272              attr == &sensor_dev_attr_freq2_label.dev_attr.attr))
3273                 return 0;
3274
3275         /* only SOC15 dGPUs support hotspot and mem temperatures */
3276         if (((adev->flags & AMD_IS_APU) ||
3277              adev->asic_type < CHIP_VEGA10) &&
3278             (attr == &sensor_dev_attr_temp2_crit.dev_attr.attr ||
3279              attr == &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr ||
3280              attr == &sensor_dev_attr_temp3_crit.dev_attr.attr ||
3281              attr == &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr ||
3282              attr == &sensor_dev_attr_temp1_emergency.dev_attr.attr ||
3283              attr == &sensor_dev_attr_temp2_emergency.dev_attr.attr ||
3284              attr == &sensor_dev_attr_temp3_emergency.dev_attr.attr ||
3285              attr == &sensor_dev_attr_temp2_input.dev_attr.attr ||
3286              attr == &sensor_dev_attr_temp3_input.dev_attr.attr ||
3287              attr == &sensor_dev_attr_temp2_label.dev_attr.attr ||
3288              attr == &sensor_dev_attr_temp3_label.dev_attr.attr))
3289                 return 0;
3290
3291         /* only Vangogh has fast PPT limit and power labels */
3292         if (!(adev->asic_type == CHIP_VANGOGH) &&
3293             (attr == &sensor_dev_attr_power2_average.dev_attr.attr ||
3294                  attr == &sensor_dev_attr_power2_cap_max.dev_attr.attr ||
3295              attr == &sensor_dev_attr_power2_cap_min.dev_attr.attr ||
3296                  attr == &sensor_dev_attr_power2_cap.dev_attr.attr ||
3297                  attr == &sensor_dev_attr_power2_cap_default.dev_attr.attr ||
3298                  attr == &sensor_dev_attr_power2_label.dev_attr.attr ||
3299                  attr == &sensor_dev_attr_power1_label.dev_attr.attr))
3300                 return 0;
3301
3302         return effective_mode;
3303 }
3304
3305 static const struct attribute_group hwmon_attrgroup = {
3306         .attrs = hwmon_attributes,
3307         .is_visible = hwmon_attributes_visible,
3308 };
3309
3310 static const struct attribute_group *hwmon_groups[] = {
3311         &hwmon_attrgroup,
3312         NULL
3313 };
3314
3315 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
3316 {
3317         int ret;
3318         uint32_t mask = 0;
3319
3320         if (adev->pm.sysfs_initialized)
3321                 return 0;
3322
3323         if (adev->pm.dpm_enabled == 0)
3324                 return 0;
3325
3326         INIT_LIST_HEAD(&adev->pm.pm_attr_list);
3327
3328         adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
3329                                                                    DRIVER_NAME, adev,
3330                                                                    hwmon_groups);
3331         if (IS_ERR(adev->pm.int_hwmon_dev)) {
3332                 ret = PTR_ERR(adev->pm.int_hwmon_dev);
3333                 dev_err(adev->dev,
3334                         "Unable to register hwmon device: %d\n", ret);
3335                 return ret;
3336         }
3337
3338         switch (amdgpu_virt_get_sriov_vf_mode(adev)) {
3339         case SRIOV_VF_MODE_ONE_VF:
3340                 mask = ATTR_FLAG_ONEVF;
3341                 break;
3342         case SRIOV_VF_MODE_MULTI_VF:
3343                 mask = 0;
3344                 break;
3345         case SRIOV_VF_MODE_BARE_METAL:
3346         default:
3347                 mask = ATTR_FLAG_MASK_ALL;
3348                 break;
3349         }
3350
3351         ret = amdgpu_device_attr_create_groups(adev,
3352                                                amdgpu_device_attrs,
3353                                                ARRAY_SIZE(amdgpu_device_attrs),
3354                                                mask,
3355                                                &adev->pm.pm_attr_list);
3356         if (ret)
3357                 return ret;
3358
3359         adev->pm.sysfs_initialized = true;
3360
3361         return 0;
3362 }
3363
3364 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
3365 {
3366         if (adev->pm.dpm_enabled == 0)
3367                 return;
3368
3369         if (adev->pm.int_hwmon_dev)
3370                 hwmon_device_unregister(adev->pm.int_hwmon_dev);
3371
3372         amdgpu_device_attr_remove_groups(adev, &adev->pm.pm_attr_list);
3373 }
3374
3375 /*
3376  * Debugfs info
3377  */
3378 #if defined(CONFIG_DEBUG_FS)
3379
3380 static void amdgpu_debugfs_prints_cpu_info(struct seq_file *m,
3381                                            struct amdgpu_device *adev) {
3382         uint16_t *p_val;
3383         uint32_t size;
3384         int i;
3385
3386         if (is_support_cclk_dpm(adev)) {
3387                 p_val = kcalloc(adev->smu.cpu_core_num, sizeof(uint16_t),
3388                                 GFP_KERNEL);
3389
3390                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_CPU_CLK,
3391                                             (void *)p_val, &size)) {
3392                         for (i = 0; i < adev->smu.cpu_core_num; i++)
3393                                 seq_printf(m, "\t%u MHz (CPU%d)\n",
3394                                            *(p_val + i), i);
3395                 }
3396
3397                 kfree(p_val);
3398         }
3399 }
3400
3401 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
3402 {
3403         uint32_t value;
3404         uint64_t value64 = 0;
3405         uint32_t query = 0;
3406         int size;
3407
3408         /* GPU Clocks */
3409         size = sizeof(value);
3410         seq_printf(m, "GFX Clocks and Power:\n");
3411
3412         amdgpu_debugfs_prints_cpu_info(m, adev);
3413
3414         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size))
3415                 seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
3416         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size))
3417                 seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
3418         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size))
3419                 seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100);
3420         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size))
3421                 seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100);
3422         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size))
3423                 seq_printf(m, "\t%u mV (VDDGFX)\n", value);
3424         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size))
3425                 seq_printf(m, "\t%u mV (VDDNB)\n", value);
3426         size = sizeof(uint32_t);
3427         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, (void *)&query, &size))
3428                 seq_printf(m, "\t%u.%u W (average GPU)\n", query >> 8, query & 0xff);
3429         size = sizeof(value);
3430         seq_printf(m, "\n");
3431
3432         /* GPU Temp */
3433         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size))
3434                 seq_printf(m, "GPU Temperature: %u C\n", value/1000);
3435
3436         /* GPU Load */
3437         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size))
3438                 seq_printf(m, "GPU Load: %u %%\n", value);
3439         /* MEM Load */
3440         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD, (void *)&value, &size))
3441                 seq_printf(m, "MEM Load: %u %%\n", value);
3442
3443         seq_printf(m, "\n");
3444
3445         /* SMC feature mask */
3446         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, (void *)&value64, &size))
3447                 seq_printf(m, "SMC Feature Mask: 0x%016llx\n", value64);
3448
3449         if (adev->asic_type > CHIP_VEGA20) {
3450                 /* VCN clocks */
3451                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCN_POWER_STATE, (void *)&value, &size)) {
3452                         if (!value) {
3453                                 seq_printf(m, "VCN: Disabled\n");
3454                         } else {
3455                                 seq_printf(m, "VCN: Enabled\n");
3456                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
3457                                         seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
3458                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
3459                                         seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
3460                         }
3461                 }
3462                 seq_printf(m, "\n");
3463         } else {
3464                 /* UVD clocks */
3465                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {
3466                         if (!value) {
3467                                 seq_printf(m, "UVD: Disabled\n");
3468                         } else {
3469                                 seq_printf(m, "UVD: Enabled\n");
3470                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
3471                                         seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
3472                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
3473                                         seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
3474                         }
3475                 }
3476                 seq_printf(m, "\n");
3477
3478                 /* VCE clocks */
3479                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) {
3480                         if (!value) {
3481                                 seq_printf(m, "VCE: Disabled\n");
3482                         } else {
3483                                 seq_printf(m, "VCE: Enabled\n");
3484                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size))
3485                                         seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
3486                         }
3487                 }
3488         }
3489
3490         return 0;
3491 }
3492
3493 static void amdgpu_parse_cg_state(struct seq_file *m, u32 flags)
3494 {
3495         int i;
3496
3497         for (i = 0; clocks[i].flag; i++)
3498                 seq_printf(m, "\t%s: %s\n", clocks[i].name,
3499                            (flags & clocks[i].flag) ? "On" : "Off");
3500 }
3501
3502 static int amdgpu_debugfs_pm_info_show(struct seq_file *m, void *unused)
3503 {
3504         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
3505         struct drm_device *dev = adev_to_drm(adev);
3506         u32 flags = 0;
3507         int r;
3508
3509         if (amdgpu_in_reset(adev))
3510                 return -EPERM;
3511         if (adev->in_suspend && !adev->in_runpm)
3512                 return -EPERM;
3513
3514         r = pm_runtime_get_sync(dev->dev);
3515         if (r < 0) {
3516                 pm_runtime_put_autosuspend(dev->dev);
3517                 return r;
3518         }
3519
3520         if (!adev->pm.dpm_enabled) {
3521                 seq_printf(m, "dpm not enabled\n");
3522                 pm_runtime_mark_last_busy(dev->dev);
3523                 pm_runtime_put_autosuspend(dev->dev);
3524                 return 0;
3525         }
3526
3527         if (!is_support_sw_smu(adev) &&
3528             adev->powerplay.pp_funcs->debugfs_print_current_performance_level) {
3529                 mutex_lock(&adev->pm.mutex);
3530                 if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level)
3531                         adev->powerplay.pp_funcs->debugfs_print_current_performance_level(adev, m);
3532                 else
3533                         seq_printf(m, "Debugfs support not implemented for this asic\n");
3534                 mutex_unlock(&adev->pm.mutex);
3535                 r = 0;
3536         } else {
3537                 r = amdgpu_debugfs_pm_info_pp(m, adev);
3538         }
3539         if (r)
3540                 goto out;
3541
3542         amdgpu_device_ip_get_clockgating_state(adev, &flags);
3543
3544         seq_printf(m, "Clock Gating Flags Mask: 0x%x\n", flags);
3545         amdgpu_parse_cg_state(m, flags);
3546         seq_printf(m, "\n");
3547
3548 out:
3549         pm_runtime_mark_last_busy(dev->dev);
3550         pm_runtime_put_autosuspend(dev->dev);
3551
3552         return r;
3553 }
3554
3555 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_pm_info);
3556
3557 /*
3558  * amdgpu_pm_priv_buffer_read - Read memory region allocated to FW
3559  *
3560  * Reads debug memory region allocated to PMFW
3561  */
3562 static ssize_t amdgpu_pm_prv_buffer_read(struct file *f, char __user *buf,
3563                                          size_t size, loff_t *pos)
3564 {
3565         struct amdgpu_device *adev = file_inode(f)->i_private;
3566         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
3567         void *pp_handle = adev->powerplay.pp_handle;
3568         size_t smu_prv_buf_size;
3569         void *smu_prv_buf;
3570
3571         if (amdgpu_in_reset(adev))
3572                 return -EPERM;
3573         if (adev->in_suspend && !adev->in_runpm)
3574                 return -EPERM;
3575
3576         if (pp_funcs && pp_funcs->get_smu_prv_buf_details)
3577                 pp_funcs->get_smu_prv_buf_details(pp_handle, &smu_prv_buf,
3578                                                   &smu_prv_buf_size);
3579         else
3580                 return -ENOSYS;
3581
3582         if (!smu_prv_buf || !smu_prv_buf_size)
3583                 return -EINVAL;
3584
3585         return simple_read_from_buffer(buf, size, pos, smu_prv_buf,
3586                                        smu_prv_buf_size);
3587 }
3588
3589 static const struct file_operations amdgpu_debugfs_pm_prv_buffer_fops = {
3590         .owner = THIS_MODULE,
3591         .open = simple_open,
3592         .read = amdgpu_pm_prv_buffer_read,
3593         .llseek = default_llseek,
3594 };
3595
3596 #endif
3597
3598 void amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
3599 {
3600 #if defined(CONFIG_DEBUG_FS)
3601         struct drm_minor *minor = adev_to_drm(adev)->primary;
3602         struct dentry *root = minor->debugfs_root;
3603
3604         debugfs_create_file("amdgpu_pm_info", 0444, root, adev,
3605                             &amdgpu_debugfs_pm_info_fops);
3606
3607         if (adev->pm.smu_prv_buffer_size > 0)
3608                 debugfs_create_file_size("amdgpu_pm_prv_buffer", 0444, root,
3609                                          adev,
3610                                          &amdgpu_debugfs_pm_prv_buffer_fops,
3611                                          adev->pm.smu_prv_buffer_size);
3612 #endif
3613 }