drivers/gpu/drm/amd/pm/amdgpu_pm.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Rafał Miłecki <zajec5@gmail.com>
  23  *          Alex Deucher <alexdeucher@gmail.com>
  24  */
  25
  26 #include "amdgpu.h"
  27 #include "amdgpu_drv.h"
  28 #include "amdgpu_pm.h"
  29 #include "amdgpu_dpm.h"
  30 #include "atom.h"
  31 #include <linux/pci.h>
  32 #include <linux/hwmon.h>
  33 #include <linux/hwmon-sysfs.h>
  34 #include <linux/nospec.h>
  35 #include <linux/pm_runtime.h>
  36 #include <asm/processor.h>
  37 #include "hwmgr.h"
  38
  39 static const struct cg_flag_name clocks[] = {
  40         {AMD_CG_SUPPORT_GFX_FGCG, "Graphics Fine Grain Clock Gating"},
  41         {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"},
  42         {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"},
  43         {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"},
  44         {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"},
  45         {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"},
  46         {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"},
  47         {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"},
  48         {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"},
  49         {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"},
  50         {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"},
  51         {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"},
  52         {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"},
  53         {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"},
  54         {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"},
  55         {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"},
  56         {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"},
  57         {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"},
  58         {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"},
  59         {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"},
  60         {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"},
  61         {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"},
  62         {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"},
  63         {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},
  64         {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"},
  65         {AMD_CG_SUPPORT_VCN_MGCG, "VCN Medium Grain Clock Gating"},
  66         {AMD_CG_SUPPORT_HDP_DS, "Host Data Path Deep Sleep"},
  67         {AMD_CG_SUPPORT_HDP_SD, "Host Data Path Shutdown"},
  68         {AMD_CG_SUPPORT_IH_CG, "Interrupt Handler Clock Gating"},
  69         {AMD_CG_SUPPORT_JPEG_MGCG, "JPEG Medium Grain Clock Gating"},
  70
  71         {AMD_CG_SUPPORT_ATHUB_MGCG, "Address Translation Hub Medium Grain Clock Gating"},
  72         {AMD_CG_SUPPORT_ATHUB_LS, "Address Translation Hub Light Sleep"},
  73         {0, NULL},
  74 };
  75
  76 static const struct hwmon_temp_label {
  77         enum PP_HWMON_TEMP channel;
  78         const char *label;
  79 } temp_label[] = {
  80         {PP_TEMP_EDGE, "edge"},
  81         {PP_TEMP_JUNCTION, "junction"},
  82         {PP_TEMP_MEM, "mem"},
  83 };
  84
  85 /**
  86  * DOC: power_dpm_state
  87  *
  88  * The power_dpm_state file is a legacy interface and is only provided for
  89  * backwards compatibility. The amdgpu driver provides a sysfs API for adjusting
  90  * certain power related parameters.  The file power_dpm_state is used for this.
  91  * It accepts the following arguments:
  92  *
  93  * - battery
  94  *
  95  * - balanced
  96  *
  97  * - performance
  98  *
  99  * battery
 100  *
 101  * On older GPUs, the vbios provided a special power state for battery
 102  * operation.  Selecting battery switched to this state.  This is no
 103  * longer provided on newer GPUs so the option does nothing in that case.
 104  *
 105  * balanced
 106  *
 107  * On older GPUs, the vbios provided a special power state for balanced
 108  * operation.  Selecting balanced switched to this state.  This is no
 109  * longer provided on newer GPUs so the option does nothing in that case.
 110  *
 111  * performance
 112  *
 113  * On older GPUs, the vbios provided a special power state for performance
 114  * operation.  Selecting performance switched to this state.  This is no
 115  * longer provided on newer GPUs so the option does nothing in that case.
 116  *
 117  */
 118
 119 static ssize_t amdgpu_get_power_dpm_state(struct device *dev,
 120                                           struct device_attribute *attr,
 121                                           char *buf)
 122 {
 123         struct drm_device *ddev = dev_get_drvdata(dev);
 124         struct amdgpu_device *adev = drm_to_adev(ddev);
 125         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 126         enum amd_pm_state_type pm;
 127         int ret;
 128
 129         if (amdgpu_in_reset(adev))
 130                 return -EPERM;
 131         if (adev->in_suspend && !adev->in_runpm)
 132                 return -EPERM;
 133
 134         ret = pm_runtime_get_sync(ddev->dev);
 135         if (ret < 0) {
 136                 pm_runtime_put_autosuspend(ddev->dev);
 137                 return ret;
 138         }
 139
 140         if (pp_funcs->get_current_power_state) {
 141                 pm = amdgpu_dpm_get_current_power_state(adev);
 142         } else {
 143                 pm = adev->pm.dpm.user_state;
 144         }
 145
 146         pm_runtime_mark_last_busy(ddev->dev);
 147         pm_runtime_put_autosuspend(ddev->dev);
 148
 149         return sysfs_emit(buf, "%s\n",
 150                           (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
 151                           (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
 152 }
 153
 154 static ssize_t amdgpu_set_power_dpm_state(struct device *dev,
 155                                           struct device_attribute *attr,
 156                                           const char *buf,
 157                                           size_t count)
 158 {
 159         struct drm_device *ddev = dev_get_drvdata(dev);
 160         struct amdgpu_device *adev = drm_to_adev(ddev);
 161         enum amd_pm_state_type  state;
 162         int ret;
 163
 164         if (amdgpu_in_reset(adev))
 165                 return -EPERM;
 166         if (adev->in_suspend && !adev->in_runpm)
 167                 return -EPERM;
 168
 169         if (strncmp("battery", buf, strlen("battery")) == 0)
 170                 state = POWER_STATE_TYPE_BATTERY;
 171         else if (strncmp("balanced", buf, strlen("balanced")) == 0)
 172                 state = POWER_STATE_TYPE_BALANCED;
 173         else if (strncmp("performance", buf, strlen("performance")) == 0)
 174                 state = POWER_STATE_TYPE_PERFORMANCE;
 175         else
 176                 return -EINVAL;
 177
 178         ret = pm_runtime_get_sync(ddev->dev);
 179         if (ret < 0) {
 180                 pm_runtime_put_autosuspend(ddev->dev);
 181                 return ret;
 182         }
 183
 184         if (is_support_sw_smu(adev)) {
 185                 mutex_lock(&adev->pm.mutex);
 186                 adev->pm.dpm.user_state = state;
 187                 mutex_unlock(&adev->pm.mutex);
 188         } else if (adev->powerplay.pp_funcs->dispatch_tasks) {
 189                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_ENABLE_USER_STATE, &state);
 190         } else {
 191                 mutex_lock(&adev->pm.mutex);
 192                 adev->pm.dpm.user_state = state;
 193                 mutex_unlock(&adev->pm.mutex);
 194
 195                 amdgpu_pm_compute_clocks(adev);
 196         }
 197         pm_runtime_mark_last_busy(ddev->dev);
 198         pm_runtime_put_autosuspend(ddev->dev);
 199
 200         return count;
 201 }
 202
 203
 204 /**
 205  * DOC: power_dpm_force_performance_level
 206  *
 207  * The amdgpu driver provides a sysfs API for adjusting certain power
 208  * related parameters.  The file power_dpm_force_performance_level is
 209  * used for this.  It accepts the following arguments:
 210  *
 211  * - auto
 212  *
 213  * - low
 214  *
 215  * - high
 216  *
 217  * - manual
 218  *
 219  * - profile_standard
 220  *
 221  * - profile_min_sclk
 222  *
 223  * - profile_min_mclk
 224  *
 225  * - profile_peak
 226  *
 227  * auto
 228  *
 229  * When auto is selected, the driver will attempt to dynamically select
 230  * the optimal power profile for current conditions in the driver.
 231  *
 232  * low
 233  *
 234  * When low is selected, the clocks are forced to the lowest power state.
 235  *
 236  * high
 237  *
 238  * When high is selected, the clocks are forced to the highest power state.
 239  *
 240  * manual
 241  *
 242  * When manual is selected, the user can manually adjust which power states
 243  * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk,
 244  * and pp_dpm_pcie files and adjust the power state transition heuristics
 245  * via the pp_power_profile_mode sysfs file.
 246  *
 247  * profile_standard
 248  * profile_min_sclk
 249  * profile_min_mclk
 250  * profile_peak
 251  *
 252  * When the profiling modes are selected, clock and power gating are
 253  * disabled and the clocks are set for different profiling cases. This
 254  * mode is recommended for profiling specific work loads where you do
 255  * not want clock or power gating for clock fluctuation to interfere
 256  * with your results. profile_standard sets the clocks to a fixed clock
 257  * level which varies from asic to asic.  profile_min_sclk forces the sclk
 258  * to the lowest level.  profile_min_mclk forces the mclk to the lowest level.
 259  * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels.
 260  *
 261  */
 262
 263 static ssize_t amdgpu_get_power_dpm_force_performance_level(struct device *dev,
 264                                                             struct device_attribute *attr,
 265                                                             char *buf)
 266 {
 267         struct drm_device *ddev = dev_get_drvdata(dev);
 268         struct amdgpu_device *adev = drm_to_adev(ddev);
 269         enum amd_dpm_forced_level level = 0xff;
 270         int ret;
 271
 272         if (amdgpu_in_reset(adev))
 273                 return -EPERM;
 274         if (adev->in_suspend && !adev->in_runpm)
 275                 return -EPERM;
 276
 277         ret = pm_runtime_get_sync(ddev->dev);
 278         if (ret < 0) {
 279                 pm_runtime_put_autosuspend(ddev->dev);
 280                 return ret;
 281         }
 282
 283         if (adev->powerplay.pp_funcs->get_performance_level)
 284                 level = amdgpu_dpm_get_performance_level(adev);
 285         else
 286                 level = adev->pm.dpm.forced_level;
 287
 288         pm_runtime_mark_last_busy(ddev->dev);
 289         pm_runtime_put_autosuspend(ddev->dev);
 290
 291         return sysfs_emit(buf, "%s\n",
 292                           (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
 293                           (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
 294                           (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
 295                           (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" :
 296                           (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" :
 297                           (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" :
 298                           (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" :
 299                           (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" :
 300                           (level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) ? "perf_determinism" :
 301                           "unknown");
 302 }
 303
 304 static ssize_t amdgpu_set_power_dpm_force_performance_level(struct device *dev,
 305                                                             struct device_attribute *attr,
 306                                                             const char *buf,
 307                                                             size_t count)
 308 {
 309         struct drm_device *ddev = dev_get_drvdata(dev);
 310         struct amdgpu_device *adev = drm_to_adev(ddev);
 311         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 312         enum amd_dpm_forced_level level;
 313         enum amd_dpm_forced_level current_level = 0xff;
 314         int ret = 0;
 315
 316         if (amdgpu_in_reset(adev))
 317                 return -EPERM;
 318         if (adev->in_suspend && !adev->in_runpm)
 319                 return -EPERM;
 320
 321         if (strncmp("low", buf, strlen("low")) == 0) {
 322                 level = AMD_DPM_FORCED_LEVEL_LOW;
 323         } else if (strncmp("high", buf, strlen("high")) == 0) {
 324                 level = AMD_DPM_FORCED_LEVEL_HIGH;
 325         } else if (strncmp("auto", buf, strlen("auto")) == 0) {
 326                 level = AMD_DPM_FORCED_LEVEL_AUTO;
 327         } else if (strncmp("manual", buf, strlen("manual")) == 0) {
 328                 level = AMD_DPM_FORCED_LEVEL_MANUAL;
 329         } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) {
 330                 level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT;
 331         } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) {
 332                 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD;
 333         } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) {
 334                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK;
 335         } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) {
 336                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK;
 337         } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) {
 338                 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
 339         } else if (strncmp("perf_determinism", buf, strlen("perf_determinism")) == 0) {
 340                 level = AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM;
 341         }  else {
 342                 return -EINVAL;
 343         }
 344
 345         ret = pm_runtime_get_sync(ddev->dev);
 346         if (ret < 0) {
 347                 pm_runtime_put_autosuspend(ddev->dev);
 348                 return ret;
 349         }
 350
 351         if (pp_funcs->get_performance_level)
 352                 current_level = amdgpu_dpm_get_performance_level(adev);
 353
 354         if (current_level == level) {
 355                 pm_runtime_mark_last_busy(ddev->dev);
 356                 pm_runtime_put_autosuspend(ddev->dev);
 357                 return count;
 358         }
 359
 360         if (adev->asic_type == CHIP_RAVEN) {
 361                 if (!(adev->apu_flags & AMD_APU_IS_RAVEN2)) {
 362                         if (current_level != AMD_DPM_FORCED_LEVEL_MANUAL && level == AMD_DPM_FORCED_LEVEL_MANUAL)
 363                                 amdgpu_gfx_off_ctrl(adev, false);
 364                         else if (current_level == AMD_DPM_FORCED_LEVEL_MANUAL && level != AMD_DPM_FORCED_LEVEL_MANUAL)
 365                                 amdgpu_gfx_off_ctrl(adev, true);
 366                 }
 367         }
 368
 369         /* profile_exit setting is valid only when current mode is in profile mode */
 370         if (!(current_level & (AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
 371             AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
 372             AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
 373             AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)) &&
 374             (level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)) {
 375                 pr_err("Currently not in any profile mode!\n");
 376                 pm_runtime_mark_last_busy(ddev->dev);
 377                 pm_runtime_put_autosuspend(ddev->dev);
 378                 return -EINVAL;
 379         }
 380
 381         if (pp_funcs->force_performance_level) {
 382                 mutex_lock(&adev->pm.mutex);
 383                 if (adev->pm.dpm.thermal_active) {
 384                         mutex_unlock(&adev->pm.mutex);
 385                         pm_runtime_mark_last_busy(ddev->dev);
 386                         pm_runtime_put_autosuspend(ddev->dev);
 387                         return -EINVAL;
 388                 }
 389                 ret = amdgpu_dpm_force_performance_level(adev, level);
 390                 if (ret) {
 391                         mutex_unlock(&adev->pm.mutex);
 392                         pm_runtime_mark_last_busy(ddev->dev);
 393                         pm_runtime_put_autosuspend(ddev->dev);
 394                         return -EINVAL;
 395                 } else {
 396                         adev->pm.dpm.forced_level = level;
 397                 }
 398                 mutex_unlock(&adev->pm.mutex);
 399         }
 400         pm_runtime_mark_last_busy(ddev->dev);
 401         pm_runtime_put_autosuspend(ddev->dev);
 402
 403         return count;
 404 }
 405
 406 static ssize_t amdgpu_get_pp_num_states(struct device *dev,
 407                 struct device_attribute *attr,
 408                 char *buf)
 409 {
 410         struct drm_device *ddev = dev_get_drvdata(dev);
 411         struct amdgpu_device *adev = drm_to_adev(ddev);
 412         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 413         struct pp_states_info data;
 414         int i, buf_len, ret;
 415
 416         if (amdgpu_in_reset(adev))
 417                 return -EPERM;
 418         if (adev->in_suspend && !adev->in_runpm)
 419                 return -EPERM;
 420
 421         ret = pm_runtime_get_sync(ddev->dev);
 422         if (ret < 0) {
 423                 pm_runtime_put_autosuspend(ddev->dev);
 424                 return ret;
 425         }
 426
 427         if (pp_funcs->get_pp_num_states) {
 428                 amdgpu_dpm_get_pp_num_states(adev, &data);
 429         } else {
 430                 memset(&data, 0, sizeof(data));
 431         }
 432
 433         pm_runtime_mark_last_busy(ddev->dev);
 434         pm_runtime_put_autosuspend(ddev->dev);
 435
 436         buf_len = snprintf(buf, PAGE_SIZE, "states: %d\n", data.nums);
 437         for (i = 0; i < data.nums; i++)
 438                 buf_len += snprintf(buf + buf_len, PAGE_SIZE, "%d %s\n", i,
 439                                 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
 440                                 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
 441                                 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
 442                                 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default");
 443
 444         return buf_len;
 445 }
 446
 447 static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
 448                 struct device_attribute *attr,
 449                 char *buf)
 450 {
 451         struct drm_device *ddev = dev_get_drvdata(dev);
 452         struct amdgpu_device *adev = drm_to_adev(ddev);
 453         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 454         struct pp_states_info data = {0};
 455         enum amd_pm_state_type pm = 0;
 456         int i = 0, ret = 0;
 457
 458         if (amdgpu_in_reset(adev))
 459                 return -EPERM;
 460         if (adev->in_suspend && !adev->in_runpm)
 461                 return -EPERM;
 462
 463         ret = pm_runtime_get_sync(ddev->dev);
 464         if (ret < 0) {
 465                 pm_runtime_put_autosuspend(ddev->dev);
 466                 return ret;
 467         }
 468
 469         if (pp_funcs->get_current_power_state
 470                  && pp_funcs->get_pp_num_states) {
 471                 pm = amdgpu_dpm_get_current_power_state(adev);
 472                 amdgpu_dpm_get_pp_num_states(adev, &data);
 473         }
 474
 475         pm_runtime_mark_last_busy(ddev->dev);
 476         pm_runtime_put_autosuspend(ddev->dev);
 477
 478         for (i = 0; i < data.nums; i++) {
 479                 if (pm == data.states[i])
 480                         break;
 481         }
 482
 483         if (i == data.nums)
 484                 i = -EINVAL;
 485
 486         return sysfs_emit(buf, "%d\n", i);
 487 }
 488
 489 static ssize_t amdgpu_get_pp_force_state(struct device *dev,
 490                 struct device_attribute *attr,
 491                 char *buf)
 492 {
 493         struct drm_device *ddev = dev_get_drvdata(dev);
 494         struct amdgpu_device *adev = drm_to_adev(ddev);
 495
 496         if (amdgpu_in_reset(adev))
 497                 return -EPERM;
 498         if (adev->in_suspend && !adev->in_runpm)
 499                 return -EPERM;
 500
 501         if (adev->pp_force_state_enabled)
 502                 return amdgpu_get_pp_cur_state(dev, attr, buf);
 503         else
 504                 return sysfs_emit(buf, "\n");
 505 }
 506
 507 static ssize_t amdgpu_set_pp_force_state(struct device *dev,
 508                 struct device_attribute *attr,
 509                 const char *buf,
 510                 size_t count)
 511 {
 512         struct drm_device *ddev = dev_get_drvdata(dev);
 513         struct amdgpu_device *adev = drm_to_adev(ddev);
 514         enum amd_pm_state_type state = 0;
 515         unsigned long idx;
 516         int ret;
 517
 518         if (amdgpu_in_reset(adev))
 519                 return -EPERM;
 520         if (adev->in_suspend && !adev->in_runpm)
 521                 return -EPERM;
 522
 523         if (strlen(buf) == 1)
 524                 adev->pp_force_state_enabled = false;
 525         else if (is_support_sw_smu(adev))
 526                 adev->pp_force_state_enabled = false;
 527         else if (adev->powerplay.pp_funcs->dispatch_tasks &&
 528                         adev->powerplay.pp_funcs->get_pp_num_states) {
 529                 struct pp_states_info data;
 530
 531                 ret = kstrtoul(buf, 0, &idx);
 532                 if (ret || idx >= ARRAY_SIZE(data.states))
 533                         return -EINVAL;
 534
 535                 idx = array_index_nospec(idx, ARRAY_SIZE(data.states));
 536
 537                 amdgpu_dpm_get_pp_num_states(adev, &data);
 538                 state = data.states[idx];
 539
 540                 ret = pm_runtime_get_sync(ddev->dev);
 541                 if (ret < 0) {
 542                         pm_runtime_put_autosuspend(ddev->dev);
 543                         return ret;
 544                 }
 545
 546                 /* only set user selected power states */
 547                 if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
 548                     state != POWER_STATE_TYPE_DEFAULT) {
 549                         amdgpu_dpm_dispatch_task(adev,
 550                                         AMD_PP_TASK_ENABLE_USER_STATE, &state);
 551                         adev->pp_force_state_enabled = true;
 552                 }
 553                 pm_runtime_mark_last_busy(ddev->dev);
 554                 pm_runtime_put_autosuspend(ddev->dev);
 555         }
 556
 557         return count;
 558 }
 559
 560 /**
 561  * DOC: pp_table
 562  *
 563  * The amdgpu driver provides a sysfs API for uploading new powerplay
 564  * tables.  The file pp_table is used for this.  Reading the file
 565  * will dump the current power play table.  Writing to the file
 566  * will attempt to upload a new powerplay table and re-initialize
 567  * powerplay using that new table.
 568  *
 569  */
 570
 571 static ssize_t amdgpu_get_pp_table(struct device *dev,
 572                 struct device_attribute *attr,
 573                 char *buf)
 574 {
 575         struct drm_device *ddev = dev_get_drvdata(dev);
 576         struct amdgpu_device *adev = drm_to_adev(ddev);
 577         char *table = NULL;
 578         int size, ret;
 579
 580         if (amdgpu_in_reset(adev))
 581                 return -EPERM;
 582         if (adev->in_suspend && !adev->in_runpm)
 583                 return -EPERM;
 584
 585         ret = pm_runtime_get_sync(ddev->dev);
 586         if (ret < 0) {
 587                 pm_runtime_put_autosuspend(ddev->dev);
 588                 return ret;
 589         }
 590
 591         if (adev->powerplay.pp_funcs->get_pp_table) {
 592                 size = amdgpu_dpm_get_pp_table(adev, &table);
 593                 pm_runtime_mark_last_busy(ddev->dev);
 594                 pm_runtime_put_autosuspend(ddev->dev);
 595                 if (size < 0)
 596                         return size;
 597         } else {
 598                 pm_runtime_mark_last_busy(ddev->dev);
 599                 pm_runtime_put_autosuspend(ddev->dev);
 600                 return 0;
 601         }
 602
 603         if (size >= PAGE_SIZE)
 604                 size = PAGE_SIZE - 1;
 605
 606         memcpy(buf, table, size);
 607
 608         return size;
 609 }
 610
 611 static ssize_t amdgpu_set_pp_table(struct device *dev,
 612                 struct device_attribute *attr,
 613                 const char *buf,
 614                 size_t count)
 615 {
 616         struct drm_device *ddev = dev_get_drvdata(dev);
 617         struct amdgpu_device *adev = drm_to_adev(ddev);
 618         int ret = 0;
 619
 620         if (amdgpu_in_reset(adev))
 621                 return -EPERM;
 622         if (adev->in_suspend && !adev->in_runpm)
 623                 return -EPERM;
 624
 625         ret = pm_runtime_get_sync(ddev->dev);
 626         if (ret < 0) {
 627                 pm_runtime_put_autosuspend(ddev->dev);
 628                 return ret;
 629         }
 630
 631         ret = amdgpu_dpm_set_pp_table(adev, buf, count);
 632         if (ret) {
 633                 pm_runtime_mark_last_busy(ddev->dev);
 634                 pm_runtime_put_autosuspend(ddev->dev);
 635                 return ret;
 636         }
 637
 638         pm_runtime_mark_last_busy(ddev->dev);
 639         pm_runtime_put_autosuspend(ddev->dev);
 640
 641         return count;
 642 }
 643
 644 /**
 645  * DOC: pp_od_clk_voltage
 646  *
 647  * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages
 648  * in each power level within a power state.  The pp_od_clk_voltage is used for
 649  * this.
 650  *
 651  * Note that the actual memory controller clock rate are exposed, not
 652  * the effective memory clock of the DRAMs. To translate it, use the
 653  * following formula:
 654  *
 655  * Clock conversion (Mhz):
 656  *
 657  * HBM: effective_memory_clock = memory_controller_clock * 1
 658  *
 659  * G5: effective_memory_clock = memory_controller_clock * 1
 660  *
 661  * G6: effective_memory_clock = memory_controller_clock * 2
 662  *
 663  * DRAM data rate (MT/s):
 664  *
 665  * HBM: effective_memory_clock * 2 = data_rate
 666  *
 667  * G5: effective_memory_clock * 4 = data_rate
 668  *
 669  * G6: effective_memory_clock * 8 = data_rate
 670  *
 671  * Bandwidth (MB/s):
 672  *
 673  * data_rate * vram_bit_width / 8 = memory_bandwidth
 674  *
 675  * Some examples:
 676  *
 677  * G5 on RX460:
 678  *
 679  * memory_controller_clock = 1750 Mhz
 680  *
 681  * effective_memory_clock = 1750 Mhz * 1 = 1750 Mhz
 682  *
 683  * data rate = 1750 * 4 = 7000 MT/s
 684  *
 685  * memory_bandwidth = 7000 * 128 bits / 8 = 112000 MB/s
 686  *
 687  * G6 on RX5700:
 688  *
 689  * memory_controller_clock = 875 Mhz
 690  *
 691  * effective_memory_clock = 875 Mhz * 2 = 1750 Mhz
 692  *
 693  * data rate = 1750 * 8 = 14000 MT/s
 694  *
 695  * memory_bandwidth = 14000 * 256 bits / 8 = 448000 MB/s
 696  *
 697  * < For Vega10 and previous ASICs >
 698  *
 699  * Reading the file will display:
 700  *
 701  * - a list of engine clock levels and voltages labeled OD_SCLK
 702  *
 703  * - a list of memory clock levels and voltages labeled OD_MCLK
 704  *
 705  * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE
 706  *
 707  * To manually adjust these settings, first select manual using
 708  * power_dpm_force_performance_level. Enter a new value for each
 709  * level by writing a string that contains "s/m level clock voltage" to
 710  * the file.  E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz
 711  * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at
 712  * 810 mV.  When you have edited all of the states as needed, write
 713  * "c" (commit) to the file to commit your changes.  If you want to reset to the
 714  * default power levels, write "r" (reset) to the file to reset them.
 715  *
 716  *
 717  * < For Vega20 and newer ASICs >
 718  *
 719  * Reading the file will display:
 720  *
 721  * - minimum and maximum engine clock labeled OD_SCLK
 722  *
 723  * - minimum(not available for Vega20 and Navi1x) and maximum memory
 724  *   clock labeled OD_MCLK
 725  *
 726  * - three <frequency, voltage> points labeled OD_VDDC_CURVE.
 727  *   They can be used to calibrate the sclk voltage curve.
 728  *
 729  * - voltage offset(in mV) applied on target voltage calculation.
 730  *   This is available for Sienna Cichlid, Navy Flounder and Dimgrey
 731  *   Cavefish. For these ASICs, the target voltage calculation can be
 732  *   illustrated by "voltage = voltage calculated from v/f curve +
 733  *   overdrive vddgfx offset"
 734  *
 735  * - a list of valid ranges for sclk, mclk, and voltage curve points
 736  *   labeled OD_RANGE
 737  *
 738  * < For APUs >
 739  *
 740  * Reading the file will display:
 741  *
 742  * - minimum and maximum engine clock labeled OD_SCLK
 743  *
 744  * - a list of valid ranges for sclk labeled OD_RANGE
 745  *
 746  * To manually adjust these settings:
 747  *
 748  * - First select manual using power_dpm_force_performance_level
 749  *
 750  * - For clock frequency setting, enter a new value by writing a
 751  *   string that contains "s/m index clock" to the file. The index
 752  *   should be 0 if to set minimum clock. And 1 if to set maximum
 753  *   clock. E.g., "s 0 500" will update minimum sclk to be 500 MHz.
 754  *   "m 1 800" will update maximum mclk to be 800Mhz.
 755  *
 756  *   For sclk voltage curve, enter the new values by writing a
 757  *   string that contains "vc point clock voltage" to the file. The
 758  *   points are indexed by 0, 1 and 2. E.g., "vc 0 300 600" will
 759  *   update point1 with clock set as 300Mhz and voltage as
 760  *   600mV. "vc 2 1000 1000" will update point3 with clock set
 761  *   as 1000Mhz and voltage 1000mV.
 762  *
 763  *   To update the voltage offset applied for gfxclk/voltage calculation,
 764  *   enter the new value by writing a string that contains "vo offset".
 765  *   This is supported by Sienna Cichlid, Navy Flounder and Dimgrey Cavefish.
 766  *   And the offset can be a positive or negative value.
 767  *
 768  * - When you have edited all of the states as needed, write "c" (commit)
 769  *   to the file to commit your changes
 770  *
 771  * - If you want to reset to the default power levels, write "r" (reset)
 772  *   to the file to reset them
 773  *
 774  */
 775
 776 static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
 777                 struct device_attribute *attr,
 778                 const char *buf,
 779                 size_t count)
 780 {
 781         struct drm_device *ddev = dev_get_drvdata(dev);
 782         struct amdgpu_device *adev = drm_to_adev(ddev);
 783         int ret;
 784         uint32_t parameter_size = 0;
 785         long parameter[64];
 786         char buf_cpy[128];
 787         char *tmp_str;
 788         char *sub_str;
 789         const char delimiter[3] = {' ', '\n', '\0'};
 790         uint32_t type;
 791
 792         if (amdgpu_in_reset(adev))
 793                 return -EPERM;
 794         if (adev->in_suspend && !adev->in_runpm)
 795                 return -EPERM;
 796
 797         if (count > 127)
 798                 return -EINVAL;
 799
 800         if (*buf == 's')
 801                 type = PP_OD_EDIT_SCLK_VDDC_TABLE;
 802         else if (*buf == 'p')
 803                 type = PP_OD_EDIT_CCLK_VDDC_TABLE;
 804         else if (*buf == 'm')
 805                 type = PP_OD_EDIT_MCLK_VDDC_TABLE;
 806         else if(*buf == 'r')
 807                 type = PP_OD_RESTORE_DEFAULT_TABLE;
 808         else if (*buf == 'c')
 809                 type = PP_OD_COMMIT_DPM_TABLE;
 810         else if (!strncmp(buf, "vc", 2))
 811                 type = PP_OD_EDIT_VDDC_CURVE;
 812         else if (!strncmp(buf, "vo", 2))
 813                 type = PP_OD_EDIT_VDDGFX_OFFSET;
 814         else
 815                 return -EINVAL;
 816
 817         memcpy(buf_cpy, buf, count+1);
 818
 819         tmp_str = buf_cpy;
 820
 821         if ((type == PP_OD_EDIT_VDDC_CURVE) ||
 822              (type == PP_OD_EDIT_VDDGFX_OFFSET))
 823                 tmp_str++;
 824         while (isspace(*++tmp_str));
 825
 826         while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) {
 827                 if (strlen(sub_str) == 0)
 828                         continue;
 829                 ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
 830                 if (ret)
 831                         return -EINVAL;
 832                 parameter_size++;
 833
 834                 while (isspace(*tmp_str))
 835                         tmp_str++;
 836         }
 837
 838         ret = pm_runtime_get_sync(ddev->dev);
 839         if (ret < 0) {
 840                 pm_runtime_put_autosuspend(ddev->dev);
 841                 return ret;
 842         }
 843
 844         if (adev->powerplay.pp_funcs->set_fine_grain_clk_vol) {
 845                 ret = amdgpu_dpm_set_fine_grain_clk_vol(adev, type,
 846                                                         parameter,
 847                                                         parameter_size);
 848                 if (ret) {
 849                         pm_runtime_mark_last_busy(ddev->dev);
 850                         pm_runtime_put_autosuspend(ddev->dev);
 851                         return -EINVAL;
 852                 }
 853         }
 854
 855         if (adev->powerplay.pp_funcs->odn_edit_dpm_table) {
 856                 ret = amdgpu_dpm_odn_edit_dpm_table(adev, type,
 857                                                     parameter, parameter_size);
 858                 if (ret) {
 859                         pm_runtime_mark_last_busy(ddev->dev);
 860                         pm_runtime_put_autosuspend(ddev->dev);
 861                         return -EINVAL;
 862                 }
 863         }
 864
 865         if (type == PP_OD_COMMIT_DPM_TABLE) {
 866                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
 867                         amdgpu_dpm_dispatch_task(adev,
 868                                                  AMD_PP_TASK_READJUST_POWER_STATE,
 869                                                  NULL);
 870                         pm_runtime_mark_last_busy(ddev->dev);
 871                         pm_runtime_put_autosuspend(ddev->dev);
 872                         return count;
 873                 } else {
 874                         pm_runtime_mark_last_busy(ddev->dev);
 875                         pm_runtime_put_autosuspend(ddev->dev);
 876                         return -EINVAL;
 877                 }
 878         }
 879
 880         pm_runtime_mark_last_busy(ddev->dev);
 881         pm_runtime_put_autosuspend(ddev->dev);
 882
 883         return count;
 884 }
 885
 886 static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
 887                 struct device_attribute *attr,
 888                 char *buf)
 889 {
 890         struct drm_device *ddev = dev_get_drvdata(dev);
 891         struct amdgpu_device *adev = drm_to_adev(ddev);
 892         ssize_t size;
 893         int ret;
 894
 895         if (amdgpu_in_reset(adev))
 896                 return -EPERM;
 897         if (adev->in_suspend && !adev->in_runpm)
 898                 return -EPERM;
 899
 900         ret = pm_runtime_get_sync(ddev->dev);
 901         if (ret < 0) {
 902                 pm_runtime_put_autosuspend(ddev->dev);
 903                 return ret;
 904         }
 905
 906         if (adev->powerplay.pp_funcs->print_clock_levels) {
 907                 size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
 908                 size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size);
 909                 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, buf+size);
 910                 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDGFX_OFFSET, buf+size);
 911                 size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf+size);
 912                 size += amdgpu_dpm_print_clock_levels(adev, OD_CCLK, buf+size);
 913         } else {
 914                 size = snprintf(buf, PAGE_SIZE, "\n");
 915         }
 916         pm_runtime_mark_last_busy(ddev->dev);
 917         pm_runtime_put_autosuspend(ddev->dev);
 918
 919         return size;
 920 }
 921
 922 /**
 923  * DOC: pp_features
 924  *
 925  * The amdgpu driver provides a sysfs API for adjusting what powerplay
 926  * features to be enabled. The file pp_features is used for this. And
 927  * this is only available for Vega10 and later dGPUs.
 928  *
 929  * Reading back the file will show you the followings:
 930  * - Current ppfeature masks
 931  * - List of the all supported powerplay features with their naming,
 932  *   bitmasks and enablement status('Y'/'N' means "enabled"/"disabled").
 933  *
 934  * To manually enable or disable a specific feature, just set or clear
 935  * the corresponding bit from original ppfeature masks and input the
 936  * new ppfeature masks.
 937  */
 938 static ssize_t amdgpu_set_pp_features(struct device *dev,
 939                                       struct device_attribute *attr,
 940                                       const char *buf,
 941                                       size_t count)
 942 {
 943         struct drm_device *ddev = dev_get_drvdata(dev);
 944         struct amdgpu_device *adev = drm_to_adev(ddev);
 945         uint64_t featuremask;
 946         int ret;
 947
 948         if (amdgpu_in_reset(adev))
 949                 return -EPERM;
 950         if (adev->in_suspend && !adev->in_runpm)
 951                 return -EPERM;
 952
 953         ret = kstrtou64(buf, 0, &featuremask);
 954         if (ret)
 955                 return -EINVAL;
 956
 957         ret = pm_runtime_get_sync(ddev->dev);
 958         if (ret < 0) {
 959                 pm_runtime_put_autosuspend(ddev->dev);
 960                 return ret;
 961         }
 962
 963         if (adev->powerplay.pp_funcs->set_ppfeature_status) {
 964                 ret = amdgpu_dpm_set_ppfeature_status(adev, featuremask);
 965                 if (ret) {
 966                         pm_runtime_mark_last_busy(ddev->dev);
 967                         pm_runtime_put_autosuspend(ddev->dev);
 968                         return -EINVAL;
 969                 }
 970         }
 971         pm_runtime_mark_last_busy(ddev->dev);
 972         pm_runtime_put_autosuspend(ddev->dev);
 973
 974         return count;
 975 }
 976
 977 static ssize_t amdgpu_get_pp_features(struct device *dev,
 978                                       struct device_attribute *attr,
 979                                       char *buf)
 980 {
 981         struct drm_device *ddev = dev_get_drvdata(dev);
 982         struct amdgpu_device *adev = drm_to_adev(ddev);
 983         ssize_t size;
 984         int ret;
 985
 986         if (amdgpu_in_reset(adev))
 987                 return -EPERM;
 988         if (adev->in_suspend && !adev->in_runpm)
 989                 return -EPERM;
 990
 991         ret = pm_runtime_get_sync(ddev->dev);
 992         if (ret < 0) {
 993                 pm_runtime_put_autosuspend(ddev->dev);
 994                 return ret;
 995         }
 996
 997         if (adev->powerplay.pp_funcs->get_ppfeature_status)
 998                 size = amdgpu_dpm_get_ppfeature_status(adev, buf);
 999         else
1000                 size = snprintf(buf, PAGE_SIZE, "\n");
1001
1002         pm_runtime_mark_last_busy(ddev->dev);
1003         pm_runtime_put_autosuspend(ddev->dev);
1004
1005         return size;
1006 }
1007
1008 /**
1009  * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk pp_dpm_pcie
1010  *
1011  * The amdgpu driver provides a sysfs API for adjusting what power levels
1012  * are enabled for a given power state.  The files pp_dpm_sclk, pp_dpm_mclk,
1013  * pp_dpm_socclk, pp_dpm_fclk, pp_dpm_dcefclk and pp_dpm_pcie are used for
1014  * this.
1015  *
1016  * pp_dpm_socclk and pp_dpm_dcefclk interfaces are only available for
1017  * Vega10 and later ASICs.
1018  * pp_dpm_fclk interface is only available for Vega20 and later ASICs.
1019  *
1020  * Reading back the files will show you the available power levels within
1021  * the power state and the clock information for those levels.
1022  *
1023  * To manually adjust these states, first select manual using
1024  * power_dpm_force_performance_level.
1025  * Secondly, enter a new value for each level by inputing a string that
1026  * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie"
1027  * E.g.,
1028  *
1029  * .. code-block:: bash
1030  *
1031  *      echo "4 5 6" > pp_dpm_sclk
1032  *
1033  * will enable sclk levels 4, 5, and 6.
1034  *
1035  * NOTE: change to the dcefclk max dpm level is not supported now
1036  */
1037
1038 static ssize_t amdgpu_get_pp_dpm_clock(struct device *dev,
1039                 enum pp_clock_type type,
1040                 char *buf)
1041 {
1042         struct drm_device *ddev = dev_get_drvdata(dev);
1043         struct amdgpu_device *adev = drm_to_adev(ddev);
1044         ssize_t size;
1045         int ret;
1046
1047         if (amdgpu_in_reset(adev))
1048                 return -EPERM;
1049         if (adev->in_suspend && !adev->in_runpm)
1050                 return -EPERM;
1051
1052         ret = pm_runtime_get_sync(ddev->dev);
1053         if (ret < 0) {
1054                 pm_runtime_put_autosuspend(ddev->dev);
1055                 return ret;
1056         }
1057
1058         if (adev->powerplay.pp_funcs->print_clock_levels)
1059                 size = amdgpu_dpm_print_clock_levels(adev, type, buf);
1060         else
1061                 size = snprintf(buf, PAGE_SIZE, "\n");
1062
1063         pm_runtime_mark_last_busy(ddev->dev);
1064         pm_runtime_put_autosuspend(ddev->dev);
1065
1066         return size;
1067 }
1068
1069 /*
1070  * Worst case: 32 bits individually specified, in octal at 12 characters
1071  * per line (+1 for \n).
1072  */
1073 #define AMDGPU_MASK_BUF_MAX     (32 * 13)
1074
1075 static ssize_t amdgpu_read_mask(const char *buf, size_t count, uint32_t *mask)
1076 {
1077         int ret;
1078         unsigned long level;
1079         char *sub_str = NULL;
1080         char *tmp;
1081         char buf_cpy[AMDGPU_MASK_BUF_MAX + 1];
1082         const char delimiter[3] = {' ', '\n', '\0'};
1083         size_t bytes;
1084
1085         *mask = 0;
1086
1087         bytes = min(count, sizeof(buf_cpy) - 1);
1088         memcpy(buf_cpy, buf, bytes);
1089         buf_cpy[bytes] = '\0';
1090         tmp = buf_cpy;
1091         while ((sub_str = strsep(&tmp, delimiter)) != NULL) {
1092                 if (strlen(sub_str)) {
1093                         ret = kstrtoul(sub_str, 0, &level);
1094                         if (ret || level > 31)
1095                                 return -EINVAL;
1096                         *mask |= 1 << level;
1097                 } else
1098                         break;
1099         }
1100
1101         return 0;
1102 }
1103
1104 static ssize_t amdgpu_set_pp_dpm_clock(struct device *dev,
1105                 enum pp_clock_type type,
1106                 const char *buf,
1107                 size_t count)
1108 {
1109         struct drm_device *ddev = dev_get_drvdata(dev);
1110         struct amdgpu_device *adev = drm_to_adev(ddev);
1111         int ret;
1112         uint32_t mask = 0;
1113
1114         if (amdgpu_in_reset(adev))
1115                 return -EPERM;
1116         if (adev->in_suspend && !adev->in_runpm)
1117                 return -EPERM;
1118
1119         ret = amdgpu_read_mask(buf, count, &mask);
1120         if (ret)
1121                 return ret;
1122
1123         ret = pm_runtime_get_sync(ddev->dev);
1124         if (ret < 0) {
1125                 pm_runtime_put_autosuspend(ddev->dev);
1126                 return ret;
1127         }
1128
1129         if (adev->powerplay.pp_funcs->force_clock_level)
1130                 ret = amdgpu_dpm_force_clock_level(adev, type, mask);
1131         else
1132                 ret = 0;
1133
1134         pm_runtime_mark_last_busy(ddev->dev);
1135         pm_runtime_put_autosuspend(ddev->dev);
1136
1137         if (ret)
1138                 return -EINVAL;
1139
1140         return count;
1141 }
1142
1143 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
1144                 struct device_attribute *attr,
1145                 char *buf)
1146 {
1147         return amdgpu_get_pp_dpm_clock(dev, PP_SCLK, buf);
1148 }
1149
1150 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
1151                 struct device_attribute *attr,
1152                 const char *buf,
1153                 size_t count)
1154 {
1155         return amdgpu_set_pp_dpm_clock(dev, PP_SCLK, buf, count);
1156 }
1157
1158 static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
1159                 struct device_attribute *attr,
1160                 char *buf)
1161 {
1162         return amdgpu_get_pp_dpm_clock(dev, PP_MCLK, buf);
1163 }
1164
1165 static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
1166                 struct device_attribute *attr,
1167                 const char *buf,
1168                 size_t count)
1169 {
1170         return amdgpu_set_pp_dpm_clock(dev, PP_MCLK, buf, count);
1171 }
1172
1173 static ssize_t amdgpu_get_pp_dpm_socclk(struct device *dev,
1174                 struct device_attribute *attr,
1175                 char *buf)
1176 {
1177         return amdgpu_get_pp_dpm_clock(dev, PP_SOCCLK, buf);
1178 }
1179
1180 static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev,
1181                 struct device_attribute *attr,
1182                 const char *buf,
1183                 size_t count)
1184 {
1185         return amdgpu_set_pp_dpm_clock(dev, PP_SOCCLK, buf, count);
1186 }
1187
1188 static ssize_t amdgpu_get_pp_dpm_fclk(struct device *dev,
1189                 struct device_attribute *attr,
1190                 char *buf)
1191 {
1192         return amdgpu_get_pp_dpm_clock(dev, PP_FCLK, buf);
1193 }
1194
1195 static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev,
1196                 struct device_attribute *attr,
1197                 const char *buf,
1198                 size_t count)
1199 {
1200         return amdgpu_set_pp_dpm_clock(dev, PP_FCLK, buf, count);
1201 }
1202
1203 static ssize_t amdgpu_get_pp_dpm_vclk(struct device *dev,
1204                 struct device_attribute *attr,
1205                 char *buf)
1206 {
1207         return amdgpu_get_pp_dpm_clock(dev, PP_VCLK, buf);
1208 }
1209
1210 static ssize_t amdgpu_set_pp_dpm_vclk(struct device *dev,
1211                 struct device_attribute *attr,
1212                 const char *buf,
1213                 size_t count)
1214 {
1215         return amdgpu_set_pp_dpm_clock(dev, PP_VCLK, buf, count);
1216 }
1217
1218 static ssize_t amdgpu_get_pp_dpm_dclk(struct device *dev,
1219                 struct device_attribute *attr,
1220                 char *buf)
1221 {
1222         return amdgpu_get_pp_dpm_clock(dev, PP_DCLK, buf);
1223 }
1224
1225 static ssize_t amdgpu_set_pp_dpm_dclk(struct device *dev,
1226                 struct device_attribute *attr,
1227                 const char *buf,
1228                 size_t count)
1229 {
1230         return amdgpu_set_pp_dpm_clock(dev, PP_DCLK, buf, count);
1231 }
1232
1233 static ssize_t amdgpu_get_pp_dpm_dcefclk(struct device *dev,
1234                 struct device_attribute *attr,
1235                 char *buf)
1236 {
1237         return amdgpu_get_pp_dpm_clock(dev, PP_DCEFCLK, buf);
1238 }
1239
1240 static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev,
1241                 struct device_attribute *attr,
1242                 const char *buf,
1243                 size_t count)
1244 {
1245         return amdgpu_set_pp_dpm_clock(dev, PP_DCEFCLK, buf, count);
1246 }
1247
1248 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
1249                 struct device_attribute *attr,
1250                 char *buf)
1251 {
1252         return amdgpu_get_pp_dpm_clock(dev, PP_PCIE, buf);
1253 }
1254
1255 static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
1256                 struct device_attribute *attr,
1257                 const char *buf,
1258                 size_t count)
1259 {
1260         return amdgpu_set_pp_dpm_clock(dev, PP_PCIE, buf, count);
1261 }
1262
1263 static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
1264                 struct device_attribute *attr,
1265                 char *buf)
1266 {
1267         struct drm_device *ddev = dev_get_drvdata(dev);
1268         struct amdgpu_device *adev = drm_to_adev(ddev);
1269         uint32_t value = 0;
1270         int ret;
1271
1272         if (amdgpu_in_reset(adev))
1273                 return -EPERM;
1274         if (adev->in_suspend && !adev->in_runpm)
1275                 return -EPERM;
1276
1277         ret = pm_runtime_get_sync(ddev->dev);
1278         if (ret < 0) {
1279                 pm_runtime_put_autosuspend(ddev->dev);
1280                 return ret;
1281         }
1282
1283         if (is_support_sw_smu(adev))
1284                 value = 0;
1285         else if (adev->powerplay.pp_funcs->get_sclk_od)
1286                 value = amdgpu_dpm_get_sclk_od(adev);
1287
1288         pm_runtime_mark_last_busy(ddev->dev);
1289         pm_runtime_put_autosuspend(ddev->dev);
1290
1291         return sysfs_emit(buf, "%d\n", value);
1292 }
1293
1294 static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
1295                 struct device_attribute *attr,
1296                 const char *buf,
1297                 size_t count)
1298 {
1299         struct drm_device *ddev = dev_get_drvdata(dev);
1300         struct amdgpu_device *adev = drm_to_adev(ddev);
1301         int ret;
1302         long int value;
1303
1304         if (amdgpu_in_reset(adev))
1305                 return -EPERM;
1306         if (adev->in_suspend && !adev->in_runpm)
1307                 return -EPERM;
1308
1309         ret = kstrtol(buf, 0, &value);
1310
1311         if (ret)
1312                 return -EINVAL;
1313
1314         ret = pm_runtime_get_sync(ddev->dev);
1315         if (ret < 0) {
1316                 pm_runtime_put_autosuspend(ddev->dev);
1317                 return ret;
1318         }
1319
1320         if (is_support_sw_smu(adev)) {
1321                 value = 0;
1322         } else {
1323                 if (adev->powerplay.pp_funcs->set_sclk_od)
1324                         amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
1325
1326                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
1327                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
1328                 } else {
1329                         adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
1330                         amdgpu_pm_compute_clocks(adev);
1331                 }
1332         }
1333
1334         pm_runtime_mark_last_busy(ddev->dev);
1335         pm_runtime_put_autosuspend(ddev->dev);
1336
1337         return count;
1338 }
1339
1340 static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
1341                 struct device_attribute *attr,
1342                 char *buf)
1343 {
1344         struct drm_device *ddev = dev_get_drvdata(dev);
1345         struct amdgpu_device *adev = drm_to_adev(ddev);
1346         uint32_t value = 0;
1347         int ret;
1348
1349         if (amdgpu_in_reset(adev))
1350                 return -EPERM;
1351         if (adev->in_suspend && !adev->in_runpm)
1352                 return -EPERM;
1353
1354         ret = pm_runtime_get_sync(ddev->dev);
1355         if (ret < 0) {
1356                 pm_runtime_put_autosuspend(ddev->dev);
1357                 return ret;
1358         }
1359
1360         if (is_support_sw_smu(adev))
1361                 value = 0;
1362         else if (adev->powerplay.pp_funcs->get_mclk_od)
1363                 value = amdgpu_dpm_get_mclk_od(adev);
1364
1365         pm_runtime_mark_last_busy(ddev->dev);
1366         pm_runtime_put_autosuspend(ddev->dev);
1367
1368         return sysfs_emit(buf, "%d\n", value);
1369 }
1370
1371 static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
1372                 struct device_attribute *attr,
1373                 const char *buf,
1374                 size_t count)
1375 {
1376         struct drm_device *ddev = dev_get_drvdata(dev);
1377         struct amdgpu_device *adev = drm_to_adev(ddev);
1378         int ret;
1379         long int value;
1380
1381         if (amdgpu_in_reset(adev))
1382                 return -EPERM;
1383         if (adev->in_suspend && !adev->in_runpm)
1384                 return -EPERM;
1385
1386         ret = kstrtol(buf, 0, &value);
1387
1388         if (ret)
1389                 return -EINVAL;
1390
1391         ret = pm_runtime_get_sync(ddev->dev);
1392         if (ret < 0) {
1393                 pm_runtime_put_autosuspend(ddev->dev);
1394                 return ret;
1395         }
1396
1397         if (is_support_sw_smu(adev)) {
1398                 value = 0;
1399         } else {
1400                 if (adev->powerplay.pp_funcs->set_mclk_od)
1401                         amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
1402
1403                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
1404                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
1405                 } else {
1406                         adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
1407                         amdgpu_pm_compute_clocks(adev);
1408                 }
1409         }
1410
1411         pm_runtime_mark_last_busy(ddev->dev);
1412         pm_runtime_put_autosuspend(ddev->dev);
1413
1414         return count;
1415 }
1416
1417 /**
1418  * DOC: pp_power_profile_mode
1419  *
1420  * The amdgpu driver provides a sysfs API for adjusting the heuristics
1421  * related to switching between power levels in a power state.  The file
1422  * pp_power_profile_mode is used for this.
1423  *
1424  * Reading this file outputs a list of all of the predefined power profiles
1425  * and the relevant heuristics settings for that profile.
1426  *
1427  * To select a profile or create a custom profile, first select manual using
1428  * power_dpm_force_performance_level.  Writing the number of a predefined
1429  * profile to pp_power_profile_mode will enable those heuristics.  To
1430  * create a custom set of heuristics, write a string of numbers to the file
1431  * starting with the number of the custom profile along with a setting
1432  * for each heuristic parameter.  Due to differences across asic families
1433  * the heuristic parameters vary from family to family.
1434  *
1435  */
1436
1437 static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,
1438                 struct device_attribute *attr,
1439                 char *buf)
1440 {
1441         struct drm_device *ddev = dev_get_drvdata(dev);
1442         struct amdgpu_device *adev = drm_to_adev(ddev);
1443         ssize_t size;
1444         int ret;
1445
1446         if (amdgpu_in_reset(adev))
1447                 return -EPERM;
1448         if (adev->in_suspend && !adev->in_runpm)
1449                 return -EPERM;
1450
1451         ret = pm_runtime_get_sync(ddev->dev);
1452         if (ret < 0) {
1453                 pm_runtime_put_autosuspend(ddev->dev);
1454                 return ret;
1455         }
1456
1457         if (adev->powerplay.pp_funcs->get_power_profile_mode)
1458                 size = amdgpu_dpm_get_power_profile_mode(adev, buf);
1459         else
1460                 size = snprintf(buf, PAGE_SIZE, "\n");
1461
1462         pm_runtime_mark_last_busy(ddev->dev);
1463         pm_runtime_put_autosuspend(ddev->dev);
1464
1465         return size;
1466 }
1467
1468
1469 static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
1470                 struct device_attribute *attr,
1471                 const char *buf,
1472                 size_t count)
1473 {
1474         int ret;
1475         struct drm_device *ddev = dev_get_drvdata(dev);
1476         struct amdgpu_device *adev = drm_to_adev(ddev);
1477         uint32_t parameter_size = 0;
1478         long parameter[64];
1479         char *sub_str, buf_cpy[128];
1480         char *tmp_str;
1481         uint32_t i = 0;
1482         char tmp[2];
1483         long int profile_mode = 0;
1484         const char delimiter[3] = {' ', '\n', '\0'};
1485
1486         if (amdgpu_in_reset(adev))
1487                 return -EPERM;
1488         if (adev->in_suspend && !adev->in_runpm)
1489                 return -EPERM;
1490
1491         tmp[0] = *(buf);
1492         tmp[1] = '\0';
1493         ret = kstrtol(tmp, 0, &profile_mode);
1494         if (ret)
1495                 return -EINVAL;
1496
1497         if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1498                 if (count < 2 || count > 127)
1499                         return -EINVAL;
1500                 while (isspace(*++buf))
1501                         i++;
1502                 memcpy(buf_cpy, buf, count-i);
1503                 tmp_str = buf_cpy;
1504                 while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) {
1505                         if (strlen(sub_str) == 0)
1506                                 continue;
1507                         ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
1508                         if (ret)
1509                                 return -EINVAL;
1510                         parameter_size++;
1511                         while (isspace(*tmp_str))
1512                                 tmp_str++;
1513                 }
1514         }
1515         parameter[parameter_size] = profile_mode;
1516
1517         ret = pm_runtime_get_sync(ddev->dev);
1518         if (ret < 0) {
1519                 pm_runtime_put_autosuspend(ddev->dev);
1520                 return ret;
1521         }
1522
1523         if (adev->powerplay.pp_funcs->set_power_profile_mode)
1524                 ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size);
1525
1526         pm_runtime_mark_last_busy(ddev->dev);
1527         pm_runtime_put_autosuspend(ddev->dev);
1528
1529         if (!ret)
1530                 return count;
1531
1532         return -EINVAL;
1533 }
1534
1535 /**
1536  * DOC: gpu_busy_percent
1537  *
1538  * The amdgpu driver provides a sysfs API for reading how busy the GPU
1539  * is as a percentage.  The file gpu_busy_percent is used for this.
1540  * The SMU firmware computes a percentage of load based on the
1541  * aggregate activity level in the IP cores.
1542  */
1543 static ssize_t amdgpu_get_gpu_busy_percent(struct device *dev,
1544                                            struct device_attribute *attr,
1545                                            char *buf)
1546 {
1547         struct drm_device *ddev = dev_get_drvdata(dev);
1548         struct amdgpu_device *adev = drm_to_adev(ddev);
1549         int r, value, size = sizeof(value);
1550
1551         if (amdgpu_in_reset(adev))
1552                 return -EPERM;
1553         if (adev->in_suspend && !adev->in_runpm)
1554                 return -EPERM;
1555
1556         r = pm_runtime_get_sync(ddev->dev);
1557         if (r < 0) {
1558                 pm_runtime_put_autosuspend(ddev->dev);
1559                 return r;
1560         }
1561
1562         /* read the IP busy sensor */
1563         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD,
1564                                    (void *)&value, &size);
1565
1566         pm_runtime_mark_last_busy(ddev->dev);
1567         pm_runtime_put_autosuspend(ddev->dev);
1568
1569         if (r)
1570                 return r;
1571
1572         return sysfs_emit(buf, "%d\n", value);
1573 }
1574
1575 /**
1576  * DOC: mem_busy_percent
1577  *
1578  * The amdgpu driver provides a sysfs API for reading how busy the VRAM
1579  * is as a percentage.  The file mem_busy_percent is used for this.
1580  * The SMU firmware computes a percentage of load based on the
1581  * aggregate activity level in the IP cores.
1582  */
1583 static ssize_t amdgpu_get_mem_busy_percent(struct device *dev,
1584                                            struct device_attribute *attr,
1585                                            char *buf)
1586 {
1587         struct drm_device *ddev = dev_get_drvdata(dev);
1588         struct amdgpu_device *adev = drm_to_adev(ddev);
1589         int r, value, size = sizeof(value);
1590
1591         if (amdgpu_in_reset(adev))
1592                 return -EPERM;
1593         if (adev->in_suspend && !adev->in_runpm)
1594                 return -EPERM;
1595
1596         r = pm_runtime_get_sync(ddev->dev);
1597         if (r < 0) {
1598                 pm_runtime_put_autosuspend(ddev->dev);
1599                 return r;
1600         }
1601
1602         /* read the IP busy sensor */
1603         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD,
1604                                    (void *)&value, &size);
1605
1606         pm_runtime_mark_last_busy(ddev->dev);
1607         pm_runtime_put_autosuspend(ddev->dev);
1608
1609         if (r)
1610                 return r;
1611
1612         return sysfs_emit(buf, "%d\n", value);
1613 }
1614
1615 /**
1616  * DOC: pcie_bw
1617  *
1618  * The amdgpu driver provides a sysfs API for estimating how much data
1619  * has been received and sent by the GPU in the last second through PCIe.
1620  * The file pcie_bw is used for this.
1621  * The Perf counters count the number of received and sent messages and return
1622  * those values, as well as the maximum payload size of a PCIe packet (mps).
1623  * Note that it is not possible to easily and quickly obtain the size of each
1624  * packet transmitted, so we output the max payload size (mps) to allow for
1625  * quick estimation of the PCIe bandwidth usage
1626  */
1627 static ssize_t amdgpu_get_pcie_bw(struct device *dev,
1628                 struct device_attribute *attr,
1629                 char *buf)
1630 {
1631         struct drm_device *ddev = dev_get_drvdata(dev);
1632         struct amdgpu_device *adev = drm_to_adev(ddev);
1633         uint64_t count0 = 0, count1 = 0;
1634         int ret;
1635
1636         if (amdgpu_in_reset(adev))
1637                 return -EPERM;
1638         if (adev->in_suspend && !adev->in_runpm)
1639                 return -EPERM;
1640
1641         if (adev->flags & AMD_IS_APU)
1642                 return -ENODATA;
1643
1644         if (!adev->asic_funcs->get_pcie_usage)
1645                 return -ENODATA;
1646
1647         ret = pm_runtime_get_sync(ddev->dev);
1648         if (ret < 0) {
1649                 pm_runtime_put_autosuspend(ddev->dev);
1650                 return ret;
1651         }
1652
1653         amdgpu_asic_get_pcie_usage(adev, &count0, &count1);
1654
1655         pm_runtime_mark_last_busy(ddev->dev);
1656         pm_runtime_put_autosuspend(ddev->dev);
1657
1658         return sysfs_emit(buf, "%llu %llu %i\n",
1659                           count0, count1, pcie_get_mps(adev->pdev));
1660 }
1661
1662 /**
1663  * DOC: unique_id
1664  *
1665  * The amdgpu driver provides a sysfs API for providing a unique ID for the GPU
1666  * The file unique_id is used for this.
1667  * This will provide a Unique ID that will persist from machine to machine
1668  *
1669  * NOTE: This will only work for GFX9 and newer. This file will be absent
1670  * on unsupported ASICs (GFX8 and older)
1671  */
1672 static ssize_t amdgpu_get_unique_id(struct device *dev,
1673                 struct device_attribute *attr,
1674                 char *buf)
1675 {
1676         struct drm_device *ddev = dev_get_drvdata(dev);
1677         struct amdgpu_device *adev = drm_to_adev(ddev);
1678
1679         if (amdgpu_in_reset(adev))
1680                 return -EPERM;
1681         if (adev->in_suspend && !adev->in_runpm)
1682                 return -EPERM;
1683
1684         if (adev->unique_id)
1685                 return sysfs_emit(buf, "%016llx\n", adev->unique_id);
1686
1687         return 0;
1688 }
1689
1690 /**
1691  * DOC: thermal_throttling_logging
1692  *
1693  * Thermal throttling pulls down the clock frequency and thus the performance.
1694  * It's an useful mechanism to protect the chip from overheating. Since it
1695  * impacts performance, the user controls whether it is enabled and if so,
1696  * the log frequency.
1697  *
1698  * Reading back the file shows you the status(enabled or disabled) and
1699  * the interval(in seconds) between each thermal logging.
1700  *
1701  * Writing an integer to the file, sets a new logging interval, in seconds.
1702  * The value should be between 1 and 3600. If the value is less than 1,
1703  * thermal logging is disabled. Values greater than 3600 are ignored.
1704  */
1705 static ssize_t amdgpu_get_thermal_throttling_logging(struct device *dev,
1706                                                      struct device_attribute *attr,
1707                                                      char *buf)
1708 {
1709         struct drm_device *ddev = dev_get_drvdata(dev);
1710         struct amdgpu_device *adev = drm_to_adev(ddev);
1711
1712         return sysfs_emit(buf, "%s: thermal throttling logging %s, with interval %d seconds\n",
1713                           adev_to_drm(adev)->unique,
1714                           atomic_read(&adev->throttling_logging_enabled) ? "enabled" : "disabled",
1715                           adev->throttling_logging_rs.interval / HZ + 1);
1716 }
1717
1718 static ssize_t amdgpu_set_thermal_throttling_logging(struct device *dev,
1719                                                      struct device_attribute *attr,
1720                                                      const char *buf,
1721                                                      size_t count)
1722 {
1723         struct drm_device *ddev = dev_get_drvdata(dev);
1724         struct amdgpu_device *adev = drm_to_adev(ddev);
1725         long throttling_logging_interval;
1726         unsigned long flags;
1727         int ret = 0;
1728
1729         ret = kstrtol(buf, 0, &throttling_logging_interval);
1730         if (ret)
1731                 return ret;
1732
1733         if (throttling_logging_interval > 3600)
1734                 return -EINVAL;
1735
1736         if (throttling_logging_interval > 0) {
1737                 raw_spin_lock_irqsave(&adev->throttling_logging_rs.lock, flags);
1738                 /*
1739                  * Reset the ratelimit timer internals.
1740                  * This can effectively restart the timer.
1741                  */
1742                 adev->throttling_logging_rs.interval =
1743                         (throttling_logging_interval - 1) * HZ;
1744                 adev->throttling_logging_rs.begin = 0;
1745                 adev->throttling_logging_rs.printed = 0;
1746                 adev->throttling_logging_rs.missed = 0;
1747                 raw_spin_unlock_irqrestore(&adev->throttling_logging_rs.lock, flags);
1748
1749                 atomic_set(&adev->throttling_logging_enabled, 1);
1750         } else {
1751                 atomic_set(&adev->throttling_logging_enabled, 0);
1752         }
1753
1754         return count;
1755 }
1756
1757 /**
1758  * DOC: gpu_metrics
1759  *
1760  * The amdgpu driver provides a sysfs API for retrieving current gpu
1761  * metrics data. The file gpu_metrics is used for this. Reading the
1762  * file will dump all the current gpu metrics data.
1763  *
1764  * These data include temperature, frequency, engines utilization,
1765  * power consume, throttler status, fan speed and cpu core statistics(
1766  * available for APU only). That's it will give a snapshot of all sensors
1767  * at the same time.
1768  */
1769 static ssize_t amdgpu_get_gpu_metrics(struct device *dev,
1770                                       struct device_attribute *attr,
1771                                       char *buf)
1772 {
1773         struct drm_device *ddev = dev_get_drvdata(dev);
1774         struct amdgpu_device *adev = drm_to_adev(ddev);
1775         void *gpu_metrics;
1776         ssize_t size = 0;
1777         int ret;
1778
1779         if (amdgpu_in_reset(adev))
1780                 return -EPERM;
1781         if (adev->in_suspend && !adev->in_runpm)
1782                 return -EPERM;
1783
1784         ret = pm_runtime_get_sync(ddev->dev);
1785         if (ret < 0) {
1786                 pm_runtime_put_autosuspend(ddev->dev);
1787                 return ret;
1788         }
1789
1790         if (adev->powerplay.pp_funcs->get_gpu_metrics)
1791                 size = amdgpu_dpm_get_gpu_metrics(adev, &gpu_metrics);
1792
1793         if (size <= 0)
1794                 goto out;
1795
1796         if (size >= PAGE_SIZE)
1797                 size = PAGE_SIZE - 1;
1798
1799         memcpy(buf, gpu_metrics, size);
1800
1801 out:
1802         pm_runtime_mark_last_busy(ddev->dev);
1803         pm_runtime_put_autosuspend(ddev->dev);
1804
1805         return size;
1806 }
1807
1808 static struct amdgpu_device_attr amdgpu_device_attrs[] = {
1809         AMDGPU_DEVICE_ATTR_RW(power_dpm_state,                          ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1810         AMDGPU_DEVICE_ATTR_RW(power_dpm_force_performance_level,        ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1811         AMDGPU_DEVICE_ATTR_RO(pp_num_states,                            ATTR_FLAG_BASIC),
1812         AMDGPU_DEVICE_ATTR_RO(pp_cur_state,                             ATTR_FLAG_BASIC),
1813         AMDGPU_DEVICE_ATTR_RW(pp_force_state,                           ATTR_FLAG_BASIC),
1814         AMDGPU_DEVICE_ATTR_RW(pp_table,                                 ATTR_FLAG_BASIC),
1815         AMDGPU_DEVICE_ATTR_RW(pp_dpm_sclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1816         AMDGPU_DEVICE_ATTR_RW(pp_dpm_mclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1817         AMDGPU_DEVICE_ATTR_RW(pp_dpm_socclk,                            ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1818         AMDGPU_DEVICE_ATTR_RW(pp_dpm_fclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1819         AMDGPU_DEVICE_ATTR_RW(pp_dpm_vclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1820         AMDGPU_DEVICE_ATTR_RW(pp_dpm_dclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1821         AMDGPU_DEVICE_ATTR_RW(pp_dpm_dcefclk,                           ATTR_FLAG_BASIC),
1822         AMDGPU_DEVICE_ATTR_RW(pp_dpm_pcie,                              ATTR_FLAG_BASIC),
1823         AMDGPU_DEVICE_ATTR_RW(pp_sclk_od,                               ATTR_FLAG_BASIC),
1824         AMDGPU_DEVICE_ATTR_RW(pp_mclk_od,                               ATTR_FLAG_BASIC),
1825         AMDGPU_DEVICE_ATTR_RW(pp_power_profile_mode,                    ATTR_FLAG_BASIC),
1826         AMDGPU_DEVICE_ATTR_RW(pp_od_clk_voltage,                        ATTR_FLAG_BASIC),
1827         AMDGPU_DEVICE_ATTR_RO(gpu_busy_percent,                         ATTR_FLAG_BASIC),
1828         AMDGPU_DEVICE_ATTR_RO(mem_busy_percent,                         ATTR_FLAG_BASIC),
1829         AMDGPU_DEVICE_ATTR_RO(pcie_bw,                                  ATTR_FLAG_BASIC),
1830         AMDGPU_DEVICE_ATTR_RW(pp_features,                              ATTR_FLAG_BASIC),
1831         AMDGPU_DEVICE_ATTR_RO(unique_id,                                ATTR_FLAG_BASIC),
1832         AMDGPU_DEVICE_ATTR_RW(thermal_throttling_logging,               ATTR_FLAG_BASIC),
1833         AMDGPU_DEVICE_ATTR_RO(gpu_metrics,                              ATTR_FLAG_BASIC),
1834 };
1835
1836 static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
1837                                uint32_t mask, enum amdgpu_device_attr_states *states)
1838 {
1839         struct device_attribute *dev_attr = &attr->dev_attr;
1840         const char *attr_name = dev_attr->attr.name;
1841         struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
1842         enum amd_asic_type asic_type = adev->asic_type;
1843
1844         if (!(attr->flags & mask)) {
1845                 *states = ATTR_STATE_UNSUPPORTED;
1846                 return 0;
1847         }
1848
1849 #define DEVICE_ATTR_IS(_name)   (!strcmp(attr_name, #_name))
1850
1851         if (DEVICE_ATTR_IS(pp_dpm_socclk)) {
1852                 if (asic_type < CHIP_VEGA10)
1853                         *states = ATTR_STATE_UNSUPPORTED;
1854         } else if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) {
1855                 if (asic_type < CHIP_VEGA10 ||
1856                     asic_type == CHIP_ARCTURUS ||
1857                     asic_type == CHIP_ALDEBARAN)
1858                         *states = ATTR_STATE_UNSUPPORTED;
1859         } else if (DEVICE_ATTR_IS(pp_dpm_fclk)) {
1860                 if (asic_type < CHIP_VEGA20)
1861                         *states = ATTR_STATE_UNSUPPORTED;
1862         } else if (DEVICE_ATTR_IS(pp_od_clk_voltage)) {
1863                 *states = ATTR_STATE_UNSUPPORTED;
1864                 if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||
1865                     (is_support_sw_smu(adev) && adev->smu.is_apu) ||
1866                         (!is_support_sw_smu(adev) && hwmgr->od_enabled))
1867                         *states = ATTR_STATE_SUPPORTED;
1868         } else if (DEVICE_ATTR_IS(mem_busy_percent)) {
1869                 if (adev->flags & AMD_IS_APU || asic_type == CHIP_VEGA10)
1870                         *states = ATTR_STATE_UNSUPPORTED;
1871         } else if (DEVICE_ATTR_IS(pcie_bw)) {
1872                 /* PCIe Perf counters won't work on APU nodes */
1873                 if (adev->flags & AMD_IS_APU)
1874                         *states = ATTR_STATE_UNSUPPORTED;
1875         } else if (DEVICE_ATTR_IS(unique_id)) {
1876                 if (asic_type != CHIP_VEGA10 &&
1877                     asic_type != CHIP_VEGA20 &&
1878                     asic_type != CHIP_ARCTURUS)
1879                         *states = ATTR_STATE_UNSUPPORTED;
1880         } else if (DEVICE_ATTR_IS(pp_features)) {
1881                 if (adev->flags & AMD_IS_APU || asic_type < CHIP_VEGA10)
1882                         *states = ATTR_STATE_UNSUPPORTED;
1883         } else if (DEVICE_ATTR_IS(gpu_metrics)) {
1884                 if (asic_type < CHIP_VEGA12)
1885                         *states = ATTR_STATE_UNSUPPORTED;
1886         } else if (DEVICE_ATTR_IS(pp_dpm_vclk)) {
1887                 if (!(asic_type == CHIP_VANGOGH))
1888                         *states = ATTR_STATE_UNSUPPORTED;
1889         } else if (DEVICE_ATTR_IS(pp_dpm_dclk)) {
1890                 if (!(asic_type == CHIP_VANGOGH))
1891                         *states = ATTR_STATE_UNSUPPORTED;
1892         }
1893
1894         if (asic_type == CHIP_ARCTURUS) {
1895                 /* Arcturus does not support standalone mclk/socclk/fclk level setting */
1896                 if (DEVICE_ATTR_IS(pp_dpm_mclk) ||
1897                     DEVICE_ATTR_IS(pp_dpm_socclk) ||
1898                     DEVICE_ATTR_IS(pp_dpm_fclk)) {
1899                         dev_attr->attr.mode &= ~S_IWUGO;
1900                         dev_attr->store = NULL;
1901                 }
1902         }
1903
1904         if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) {
1905                 /* SMU MP1 does not support dcefclk level setting */
1906                 if (asic_type >= CHIP_NAVI10) {
1907                         dev_attr->attr.mode &= ~S_IWUGO;
1908                         dev_attr->store = NULL;
1909                 }
1910         }
1911
1912 #undef DEVICE_ATTR_IS
1913
1914         return 0;
1915 }
1916
1917
1918 static int amdgpu_device_attr_create(struct amdgpu_device *adev,
1919                                      struct amdgpu_device_attr *attr,
1920                                      uint32_t mask, struct list_head *attr_list)
1921 {
1922         int ret = 0;
1923         struct device_attribute *dev_attr = &attr->dev_attr;
1924         const char *name = dev_attr->attr.name;
1925         enum amdgpu_device_attr_states attr_states = ATTR_STATE_SUPPORTED;
1926         struct amdgpu_device_attr_entry *attr_entry;
1927
1928         int (*attr_update)(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
1929                            uint32_t mask, enum amdgpu_device_attr_states *states) = default_attr_update;
1930
1931         BUG_ON(!attr);
1932
1933         attr_update = attr->attr_update ? attr_update : default_attr_update;
1934
1935         ret = attr_update(adev, attr, mask, &attr_states);
1936         if (ret) {
1937                 dev_err(adev->dev, "failed to update device file %s, ret = %d\n",
1938                         name, ret);
1939                 return ret;
1940         }
1941
1942         if (attr_states == ATTR_STATE_UNSUPPORTED)
1943                 return 0;
1944
1945         ret = device_create_file(adev->dev, dev_attr);
1946         if (ret) {
1947                 dev_err(adev->dev, "failed to create device file %s, ret = %d\n",
1948                         name, ret);
1949         }
1950
1951         attr_entry = kmalloc(sizeof(*attr_entry), GFP_KERNEL);
1952         if (!attr_entry)
1953                 return -ENOMEM;
1954
1955         attr_entry->attr = attr;
1956         INIT_LIST_HEAD(&attr_entry->entry);
1957
1958         list_add_tail(&attr_entry->entry, attr_list);
1959
1960         return ret;
1961 }
1962
1963 static void amdgpu_device_attr_remove(struct amdgpu_device *adev, struct amdgpu_device_attr *attr)
1964 {
1965         struct device_attribute *dev_attr = &attr->dev_attr;
1966
1967         device_remove_file(adev->dev, dev_attr);
1968 }
1969
1970 static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev,
1971                                              struct list_head *attr_list);
1972
1973 static int amdgpu_device_attr_create_groups(struct amdgpu_device *adev,
1974                                             struct amdgpu_device_attr *attrs,
1975                                             uint32_t counts,
1976                                             uint32_t mask,
1977                                             struct list_head *attr_list)
1978 {
1979         int ret = 0;
1980         uint32_t i = 0;
1981
1982         for (i = 0; i < counts; i++) {
1983                 ret = amdgpu_device_attr_create(adev, &attrs[i], mask, attr_list);
1984                 if (ret)
1985                         goto failed;
1986         }
1987
1988         return 0;
1989
1990 failed:
1991         amdgpu_device_attr_remove_groups(adev, attr_list);
1992
1993         return ret;
1994 }
1995
1996 static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev,
1997                                              struct list_head *attr_list)
1998 {
1999         struct amdgpu_device_attr_entry *entry, *entry_tmp;
2000
2001         if (list_empty(attr_list))
2002                 return ;
2003
2004         list_for_each_entry_safe(entry, entry_tmp, attr_list, entry) {
2005                 amdgpu_device_attr_remove(adev, entry->attr);
2006                 list_del(&entry->entry);
2007                 kfree(entry);
2008         }
2009 }
2010
2011 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
2012                                       struct device_attribute *attr,
2013                                       char *buf)
2014 {
2015         struct amdgpu_device *adev = dev_get_drvdata(dev);
2016         int channel = to_sensor_dev_attr(attr)->index;
2017         int r, temp = 0, size = sizeof(temp);
2018
2019         if (amdgpu_in_reset(adev))
2020                 return -EPERM;
2021         if (adev->in_suspend && !adev->in_runpm)
2022                 return -EPERM;
2023
2024         if (channel >= PP_TEMP_MAX)
2025                 return -EINVAL;
2026
2027         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2028         if (r < 0) {
2029                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2030                 return r;
2031         }
2032
2033         switch (channel) {
2034         case PP_TEMP_JUNCTION:
2035                 /* get current junction temperature */
2036                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
2037                                            (void *)&temp, &size);
2038                 break;
2039         case PP_TEMP_EDGE:
2040                 /* get current edge temperature */
2041                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_EDGE_TEMP,
2042                                            (void *)&temp, &size);
2043                 break;
2044         case PP_TEMP_MEM:
2045                 /* get current memory temperature */
2046                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_TEMP,
2047                                            (void *)&temp, &size);
2048                 break;
2049         default:
2050                 r = -EINVAL;
2051                 break;
2052         }
2053
2054         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2055         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2056
2057         if (r)
2058                 return r;
2059
2060         return sysfs_emit(buf, "%d\n", temp);
2061 }
2062
2063 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev,
2064                                              struct device_attribute *attr,
2065                                              char *buf)
2066 {
2067         struct amdgpu_device *adev = dev_get_drvdata(dev);
2068         int hyst = to_sensor_dev_attr(attr)->index;
2069         int temp;
2070
2071         if (hyst)
2072                 temp = adev->pm.dpm.thermal.min_temp;
2073         else
2074                 temp = adev->pm.dpm.thermal.max_temp;
2075
2076         return sysfs_emit(buf, "%d\n", temp);
2077 }
2078
2079 static ssize_t amdgpu_hwmon_show_hotspot_temp_thresh(struct device *dev,
2080                                              struct device_attribute *attr,
2081                                              char *buf)
2082 {
2083         struct amdgpu_device *adev = dev_get_drvdata(dev);
2084         int hyst = to_sensor_dev_attr(attr)->index;
2085         int temp;
2086
2087         if (hyst)
2088                 temp = adev->pm.dpm.thermal.min_hotspot_temp;
2089         else
2090                 temp = adev->pm.dpm.thermal.max_hotspot_crit_temp;
2091
2092         return sysfs_emit(buf, "%d\n", temp);
2093 }
2094
2095 static ssize_t amdgpu_hwmon_show_mem_temp_thresh(struct device *dev,
2096                                              struct device_attribute *attr,
2097                                              char *buf)
2098 {
2099         struct amdgpu_device *adev = dev_get_drvdata(dev);
2100         int hyst = to_sensor_dev_attr(attr)->index;
2101         int temp;
2102
2103         if (hyst)
2104                 temp = adev->pm.dpm.thermal.min_mem_temp;
2105         else
2106                 temp = adev->pm.dpm.thermal.max_mem_crit_temp;
2107
2108         return sysfs_emit(buf, "%d\n", temp);
2109 }
2110
2111 static ssize_t amdgpu_hwmon_show_temp_label(struct device *dev,
2112                                              struct device_attribute *attr,
2113                                              char *buf)
2114 {
2115         int channel = to_sensor_dev_attr(attr)->index;
2116
2117         if (channel >= PP_TEMP_MAX)
2118                 return -EINVAL;
2119
2120         return sysfs_emit(buf, "%s\n", temp_label[channel].label);
2121 }
2122
2123 static ssize_t amdgpu_hwmon_show_temp_emergency(struct device *dev,
2124                                              struct device_attribute *attr,
2125                                              char *buf)
2126 {
2127         struct amdgpu_device *adev = dev_get_drvdata(dev);
2128         int channel = to_sensor_dev_attr(attr)->index;
2129         int temp = 0;
2130
2131         if (channel >= PP_TEMP_MAX)
2132                 return -EINVAL;
2133
2134         switch (channel) {
2135         case PP_TEMP_JUNCTION:
2136                 temp = adev->pm.dpm.thermal.max_hotspot_emergency_temp;
2137                 break;
2138         case PP_TEMP_EDGE:
2139                 temp = adev->pm.dpm.thermal.max_edge_emergency_temp;
2140                 break;
2141         case PP_TEMP_MEM:
2142                 temp = adev->pm.dpm.thermal.max_mem_emergency_temp;
2143                 break;
2144         }
2145
2146         return sysfs_emit(buf, "%d\n", temp);
2147 }
2148
2149 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
2150                                             struct device_attribute *attr,
2151                                             char *buf)
2152 {
2153         struct amdgpu_device *adev = dev_get_drvdata(dev);
2154         u32 pwm_mode = 0;
2155         int ret;
2156
2157         if (amdgpu_in_reset(adev))
2158                 return -EPERM;
2159         if (adev->in_suspend && !adev->in_runpm)
2160                 return -EPERM;
2161
2162         ret = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2163         if (ret < 0) {
2164                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2165                 return ret;
2166         }
2167
2168         if (!adev->powerplay.pp_funcs->get_fan_control_mode) {
2169                 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2170                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2171                 return -EINVAL;
2172         }
2173
2174         pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
2175
2176         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2177         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2178
2179         return sprintf(buf, "%u\n", pwm_mode);
2180 }
2181
2182 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
2183                                             struct device_attribute *attr,
2184                                             const char *buf,
2185                                             size_t count)
2186 {
2187         struct amdgpu_device *adev = dev_get_drvdata(dev);
2188         int err, ret;
2189         int value;
2190
2191         if (amdgpu_in_reset(adev))
2192                 return -EPERM;
2193         if (adev->in_suspend && !adev->in_runpm)
2194                 return -EPERM;
2195
2196         err = kstrtoint(buf, 10, &value);
2197         if (err)
2198                 return err;
2199
2200         ret = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2201         if (ret < 0) {
2202                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2203                 return ret;
2204         }
2205
2206         if (!adev->powerplay.pp_funcs->set_fan_control_mode) {
2207                 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2208                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2209                 return -EINVAL;
2210         }
2211
2212         amdgpu_dpm_set_fan_control_mode(adev, value);
2213
2214         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2215         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2216
2217         return count;
2218 }
2219
2220 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev,
2221                                          struct device_attribute *attr,
2222                                          char *buf)
2223 {
2224         return sprintf(buf, "%i\n", 0);
2225 }
2226
2227 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev,
2228                                          struct device_attribute *attr,
2229                                          char *buf)
2230 {
2231         return sprintf(buf, "%i\n", 255);
2232 }
2233
2234 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
2235                                      struct device_attribute *attr,
2236                                      const char *buf, size_t count)
2237 {
2238         struct amdgpu_device *adev = dev_get_drvdata(dev);
2239         int err;
2240         u32 value;
2241         u32 pwm_mode;
2242
2243         if (amdgpu_in_reset(adev))
2244                 return -EPERM;
2245         if (adev->in_suspend && !adev->in_runpm)
2246                 return -EPERM;
2247
2248         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2249         if (err < 0) {
2250                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2251                 return err;
2252         }
2253
2254         pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
2255         if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
2256                 pr_info("manual fan speed control should be enabled first\n");
2257                 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2258                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2259                 return -EINVAL;
2260         }
2261
2262         err = kstrtou32(buf, 10, &value);
2263         if (err) {
2264                 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2265                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2266                 return err;
2267         }
2268
2269         value = (value * 100) / 255;
2270
2271         if (adev->powerplay.pp_funcs->set_fan_speed_percent)
2272                 err = amdgpu_dpm_set_fan_speed_percent(adev, value);
2273         else
2274                 err = -EINVAL;
2275
2276         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2277         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2278
2279         if (err)
2280                 return err;
2281
2282         return count;
2283 }
2284
2285 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
2286                                      struct device_attribute *attr,
2287                                      char *buf)
2288 {
2289         struct amdgpu_device *adev = dev_get_drvdata(dev);
2290         int err;
2291         u32 speed = 0;
2292
2293         if (amdgpu_in_reset(adev))
2294                 return -EPERM;
2295         if (adev->in_suspend && !adev->in_runpm)
2296                 return -EPERM;
2297
2298         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2299         if (err < 0) {
2300                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2301                 return err;
2302         }
2303
2304         if (adev->powerplay.pp_funcs->get_fan_speed_percent)
2305                 err = amdgpu_dpm_get_fan_speed_percent(adev, &speed);
2306         else
2307                 err = -EINVAL;
2308
2309         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2310         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2311
2312         if (err)
2313                 return err;
2314
2315         speed = (speed * 255) / 100;
2316
2317         return sprintf(buf, "%i\n", speed);
2318 }
2319
2320 static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
2321                                            struct device_attribute *attr,
2322                                            char *buf)
2323 {
2324         struct amdgpu_device *adev = dev_get_drvdata(dev);
2325         int err;
2326         u32 speed = 0;
2327
2328         if (amdgpu_in_reset(adev))
2329                 return -EPERM;
2330         if (adev->in_suspend && !adev->in_runpm)
2331                 return -EPERM;
2332
2333         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2334         if (err < 0) {
2335                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2336                 return err;
2337         }
2338
2339         if (adev->powerplay.pp_funcs->get_fan_speed_rpm)
2340                 err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
2341         else
2342                 err = -EINVAL;
2343
2344         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2345         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2346
2347         if (err)
2348                 return err;
2349
2350         return sprintf(buf, "%i\n", speed);
2351 }
2352
2353 static ssize_t amdgpu_hwmon_get_fan1_min(struct device *dev,
2354                                          struct device_attribute *attr,
2355                                          char *buf)
2356 {
2357         struct amdgpu_device *adev = dev_get_drvdata(dev);
2358         u32 min_rpm = 0;
2359         u32 size = sizeof(min_rpm);
2360         int r;
2361
2362         if (amdgpu_in_reset(adev))
2363                 return -EPERM;
2364         if (adev->in_suspend && !adev->in_runpm)
2365                 return -EPERM;
2366
2367         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2368         if (r < 0) {
2369                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2370                 return r;
2371         }
2372
2373         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MIN_FAN_RPM,
2374                                    (void *)&min_rpm, &size);
2375
2376         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2377         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2378
2379         if (r)
2380                 return r;
2381
2382         return sysfs_emit(buf, "%d\n", min_rpm);
2383 }
2384
2385 static ssize_t amdgpu_hwmon_get_fan1_max(struct device *dev,
2386                                          struct device_attribute *attr,
2387                                          char *buf)
2388 {
2389         struct amdgpu_device *adev = dev_get_drvdata(dev);
2390         u32 max_rpm = 0;
2391         u32 size = sizeof(max_rpm);
2392         int r;
2393
2394         if (amdgpu_in_reset(adev))
2395                 return -EPERM;
2396         if (adev->in_suspend && !adev->in_runpm)
2397                 return -EPERM;
2398
2399         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2400         if (r < 0) {
2401                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2402                 return r;
2403         }
2404
2405         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MAX_FAN_RPM,
2406                                    (void *)&max_rpm, &size);
2407
2408         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2409         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2410
2411         if (r)
2412                 return r;
2413
2414         return sysfs_emit(buf, "%d\n", max_rpm);
2415 }
2416
2417 static ssize_t amdgpu_hwmon_get_fan1_target(struct device *dev,
2418                                            struct device_attribute *attr,
2419                                            char *buf)
2420 {
2421         struct amdgpu_device *adev = dev_get_drvdata(dev);
2422         int err;
2423         u32 rpm = 0;
2424
2425         if (amdgpu_in_reset(adev))
2426                 return -EPERM;
2427         if (adev->in_suspend && !adev->in_runpm)
2428                 return -EPERM;
2429
2430         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2431         if (err < 0) {
2432                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2433                 return err;
2434         }
2435
2436         if (adev->powerplay.pp_funcs->get_fan_speed_rpm)
2437                 err = amdgpu_dpm_get_fan_speed_rpm(adev, &rpm);
2438         else
2439                 err = -EINVAL;
2440
2441         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2442         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2443
2444         if (err)
2445                 return err;
2446
2447         return sprintf(buf, "%i\n", rpm);
2448 }
2449
2450 static ssize_t amdgpu_hwmon_set_fan1_target(struct device *dev,
2451                                      struct device_attribute *attr,
2452                                      const char *buf, size_t count)
2453 {
2454         struct amdgpu_device *adev = dev_get_drvdata(dev);
2455         int err;
2456         u32 value;
2457         u32 pwm_mode;
2458
2459         if (amdgpu_in_reset(adev))
2460                 return -EPERM;
2461         if (adev->in_suspend && !adev->in_runpm)
2462                 return -EPERM;
2463
2464         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2465         if (err < 0) {
2466                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2467                 return err;
2468         }
2469
2470         pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
2471
2472         if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
2473                 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2474                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2475                 return -ENODATA;
2476         }
2477
2478         err = kstrtou32(buf, 10, &value);
2479         if (err) {
2480                 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2481                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2482                 return err;
2483         }
2484
2485         if (adev->powerplay.pp_funcs->set_fan_speed_rpm)
2486                 err = amdgpu_dpm_set_fan_speed_rpm(adev, value);
2487         else
2488                 err = -EINVAL;
2489
2490         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2491         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2492
2493         if (err)
2494                 return err;
2495
2496         return count;
2497 }
2498
2499 static ssize_t amdgpu_hwmon_get_fan1_enable(struct device *dev,
2500                                             struct device_attribute *attr,
2501                                             char *buf)
2502 {
2503         struct amdgpu_device *adev = dev_get_drvdata(dev);
2504         u32 pwm_mode = 0;
2505         int ret;
2506
2507         if (amdgpu_in_reset(adev))
2508                 return -EPERM;
2509         if (adev->in_suspend && !adev->in_runpm)
2510                 return -EPERM;
2511
2512         ret = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2513         if (ret < 0) {
2514                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2515                 return ret;
2516         }
2517
2518         if (!adev->powerplay.pp_funcs->get_fan_control_mode) {
2519                 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2520                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2521                 return -EINVAL;
2522         }
2523
2524         pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
2525
2526         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2527         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2528
2529         return sprintf(buf, "%i\n", pwm_mode == AMD_FAN_CTRL_AUTO ? 0 : 1);
2530 }
2531
2532 static ssize_t amdgpu_hwmon_set_fan1_enable(struct device *dev,
2533                                             struct device_attribute *attr,
2534                                             const char *buf,
2535                                             size_t count)
2536 {
2537         struct amdgpu_device *adev = dev_get_drvdata(dev);
2538         int err;
2539         int value;
2540         u32 pwm_mode;
2541
2542         if (amdgpu_in_reset(adev))
2543                 return -EPERM;
2544         if (adev->in_suspend && !adev->in_runpm)
2545                 return -EPERM;
2546
2547         err = kstrtoint(buf, 10, &value);
2548         if (err)
2549                 return err;
2550
2551         if (value == 0)
2552                 pwm_mode = AMD_FAN_CTRL_AUTO;
2553         else if (value == 1)
2554                 pwm_mode = AMD_FAN_CTRL_MANUAL;
2555         else
2556                 return -EINVAL;
2557
2558         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2559         if (err < 0) {
2560                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2561                 return err;
2562         }
2563
2564         if (!adev->powerplay.pp_funcs->set_fan_control_mode) {
2565                 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2566                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2567                 return -EINVAL;
2568         }
2569         amdgpu_dpm_set_fan_control_mode(adev, pwm_mode);
2570
2571         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2572         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2573
2574         return count;
2575 }
2576
2577 static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev,
2578                                         struct device_attribute *attr,
2579                                         char *buf)
2580 {
2581         struct amdgpu_device *adev = dev_get_drvdata(dev);
2582         u32 vddgfx;
2583         int r, size = sizeof(vddgfx);
2584
2585         if (amdgpu_in_reset(adev))
2586                 return -EPERM;
2587         if (adev->in_suspend && !adev->in_runpm)
2588                 return -EPERM;
2589
2590         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2591         if (r < 0) {
2592                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2593                 return r;
2594         }
2595
2596         /* get the voltage */
2597         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX,
2598                                    (void *)&vddgfx, &size);
2599
2600         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2601         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2602
2603         if (r)
2604                 return r;
2605
2606         return sysfs_emit(buf, "%d\n", vddgfx);
2607 }
2608
2609 static ssize_t amdgpu_hwmon_show_vddgfx_label(struct device *dev,
2610                                               struct device_attribute *attr,
2611                                               char *buf)
2612 {
2613         return sysfs_emit(buf, "vddgfx\n");
2614 }
2615
2616 static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev,
2617                                        struct device_attribute *attr,
2618                                        char *buf)
2619 {
2620         struct amdgpu_device *adev = dev_get_drvdata(dev);
2621         u32 vddnb;
2622         int r, size = sizeof(vddnb);
2623
2624         if (amdgpu_in_reset(adev))
2625                 return -EPERM;
2626         if (adev->in_suspend && !adev->in_runpm)
2627                 return -EPERM;
2628
2629         /* only APUs have vddnb */
2630         if  (!(adev->flags & AMD_IS_APU))
2631                 return -EINVAL;
2632
2633         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2634         if (r < 0) {
2635                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2636                 return r;
2637         }
2638
2639         /* get the voltage */
2640         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB,
2641                                    (void *)&vddnb, &size);
2642
2643         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2644         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2645
2646         if (r)
2647                 return r;
2648
2649         return sysfs_emit(buf, "%d\n", vddnb);
2650 }
2651
2652 static ssize_t amdgpu_hwmon_show_vddnb_label(struct device *dev,
2653                                               struct device_attribute *attr,
2654                                               char *buf)
2655 {
2656         return sysfs_emit(buf, "vddnb\n");
2657 }
2658
2659 static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev,
2660                                            struct device_attribute *attr,
2661                                            char *buf)
2662 {
2663         struct amdgpu_device *adev = dev_get_drvdata(dev);
2664         u32 query = 0;
2665         int r, size = sizeof(u32);
2666         unsigned uw;
2667
2668         if (amdgpu_in_reset(adev))
2669                 return -EPERM;
2670         if (adev->in_suspend && !adev->in_runpm)
2671                 return -EPERM;
2672
2673         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2674         if (r < 0) {
2675                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2676                 return r;
2677         }
2678
2679         /* get the voltage */
2680         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER,
2681                                    (void *)&query, &size);
2682
2683         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2684         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2685
2686         if (r)
2687                 return r;
2688
2689         /* convert to microwatts */
2690         uw = (query >> 8) * 1000000 + (query & 0xff) * 1000;
2691
2692         return sysfs_emit(buf, "%u\n", uw);
2693 }
2694
2695 static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev,
2696                                          struct device_attribute *attr,
2697                                          char *buf)
2698 {
2699         return sprintf(buf, "%i\n", 0);
2700 }
2701
2702 static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
2703                                          struct device_attribute *attr,
2704                                          char *buf)
2705 {
2706         struct amdgpu_device *adev = dev_get_drvdata(dev);
2707         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
2708         int limit_type = to_sensor_dev_attr(attr)->index;
2709         uint32_t limit = limit_type << 24;
2710         uint32_t max_limit = 0;
2711         ssize_t size;
2712         int r;
2713
2714         if (amdgpu_in_reset(adev))
2715                 return -EPERM;
2716         if (adev->in_suspend && !adev->in_runpm)
2717                 return -EPERM;
2718
2719         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2720         if (r < 0) {
2721                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2722                 return r;
2723         }
2724
2725         if (is_support_sw_smu(adev)) {
2726                 smu_get_power_limit(&adev->smu, &limit, SMU_PPT_LIMIT_MAX);
2727                 size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
2728         } else if (pp_funcs && pp_funcs->get_power_limit) {
2729                 pp_funcs->get_power_limit(adev->powerplay.pp_handle,
2730                                 &limit, &max_limit, true);
2731                 size = snprintf(buf, PAGE_SIZE, "%u\n", max_limit * 1000000);
2732         } else {
2733                 size = snprintf(buf, PAGE_SIZE, "\n");
2734         }
2735
2736         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2737         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2738
2739         return size;
2740 }
2741
2742 static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
2743                                          struct device_attribute *attr,
2744                                          char *buf)
2745 {
2746         struct amdgpu_device *adev = dev_get_drvdata(dev);
2747         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
2748         int limit_type = to_sensor_dev_attr(attr)->index;
2749         uint32_t limit = limit_type << 24;
2750         ssize_t size;
2751         int r;
2752
2753         if (amdgpu_in_reset(adev))
2754                 return -EPERM;
2755         if (adev->in_suspend && !adev->in_runpm)
2756                 return -EPERM;
2757
2758         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2759         if (r < 0) {
2760                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2761                 return r;
2762         }
2763
2764         if (is_support_sw_smu(adev)) {
2765                 smu_get_power_limit(&adev->smu, &limit, SMU_PPT_LIMIT_CURRENT);
2766                 size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
2767         } else if (pp_funcs && pp_funcs->get_power_limit) {
2768                 pp_funcs->get_power_limit(adev->powerplay.pp_handle,
2769                                 &limit, NULL, false);
2770                 size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
2771         } else {
2772                 size = snprintf(buf, PAGE_SIZE, "\n");
2773         }
2774
2775         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2776         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2777
2778         return size;
2779 }
2780
2781 static ssize_t amdgpu_hwmon_show_power_cap_default(struct device *dev,
2782                                          struct device_attribute *attr,
2783                                          char *buf)
2784 {
2785         struct amdgpu_device *adev = dev_get_drvdata(dev);
2786         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
2787         int limit_type = to_sensor_dev_attr(attr)->index;
2788         uint32_t limit = limit_type << 24;
2789         ssize_t size;
2790         int r;
2791
2792         if (amdgpu_in_reset(adev))
2793                 return -EPERM;
2794         if (adev->in_suspend && !adev->in_runpm)
2795                 return -EPERM;
2796
2797         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2798         if (r < 0) {
2799                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2800                 return r;
2801         }
2802
2803         if (is_support_sw_smu(adev)) {
2804                 smu_get_power_limit(&adev->smu, &limit, SMU_PPT_LIMIT_DEFAULT);
2805                 size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
2806         } else if (pp_funcs && pp_funcs->get_power_limit) {
2807                 pp_funcs->get_power_limit(adev->powerplay.pp_handle,
2808                                 &limit, NULL, true);
2809                 size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
2810         } else {
2811                 size = snprintf(buf, PAGE_SIZE, "\n");
2812         }
2813
2814         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2815         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2816
2817         return size;
2818 }
2819 static ssize_t amdgpu_hwmon_show_power_label(struct device *dev,
2820                                          struct device_attribute *attr,
2821                                          char *buf)
2822 {
2823         int limit_type = to_sensor_dev_attr(attr)->index;
2824
2825         return sysfs_emit(buf, "%s\n",
2826                 limit_type == SMU_FAST_PPT_LIMIT ? "fastPPT" : "slowPPT");
2827 }
2828
2829 static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
2830                 struct device_attribute *attr,
2831                 const char *buf,
2832                 size_t count)
2833 {
2834         struct amdgpu_device *adev = dev_get_drvdata(dev);
2835         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
2836         int limit_type = to_sensor_dev_attr(attr)->index;
2837         int err;
2838         u32 value;
2839
2840         if (amdgpu_in_reset(adev))
2841                 return -EPERM;
2842         if (adev->in_suspend && !adev->in_runpm)
2843                 return -EPERM;
2844
2845         if (amdgpu_sriov_vf(adev))
2846                 return -EINVAL;
2847
2848         err = kstrtou32(buf, 10, &value);
2849         if (err)
2850                 return err;
2851
2852         value = value / 1000000; /* convert to Watt */
2853         value |= limit_type << 24;
2854
2855         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2856         if (err < 0) {
2857                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2858                 return err;
2859         }
2860
2861         if (pp_funcs && pp_funcs->set_power_limit)
2862                 err = pp_funcs->set_power_limit(adev->powerplay.pp_handle, value);
2863         else
2864                 err = -EINVAL;
2865
2866         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2867         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2868
2869         if (err)
2870                 return err;
2871
2872         return count;
2873 }
2874
2875 static ssize_t amdgpu_hwmon_show_sclk(struct device *dev,
2876                                       struct device_attribute *attr,
2877                                       char *buf)
2878 {
2879         struct amdgpu_device *adev = dev_get_drvdata(dev);
2880         uint32_t sclk;
2881         int r, size = sizeof(sclk);
2882
2883         if (amdgpu_in_reset(adev))
2884                 return -EPERM;
2885         if (adev->in_suspend && !adev->in_runpm)
2886                 return -EPERM;
2887
2888         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2889         if (r < 0) {
2890                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2891                 return r;
2892         }
2893
2894         /* get the sclk */
2895         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK,
2896                                    (void *)&sclk, &size);
2897
2898         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2899         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2900
2901         if (r)
2902                 return r;
2903
2904         return sysfs_emit(buf, "%u\n", sclk * 10 * 1000);
2905 }
2906
2907 static ssize_t amdgpu_hwmon_show_sclk_label(struct device *dev,
2908                                             struct device_attribute *attr,
2909                                             char *buf)
2910 {
2911         return sysfs_emit(buf, "sclk\n");
2912 }
2913
2914 static ssize_t amdgpu_hwmon_show_mclk(struct device *dev,
2915                                       struct device_attribute *attr,
2916                                       char *buf)
2917 {
2918         struct amdgpu_device *adev = dev_get_drvdata(dev);
2919         uint32_t mclk;
2920         int r, size = sizeof(mclk);
2921
2922         if (amdgpu_in_reset(adev))
2923                 return -EPERM;
2924         if (adev->in_suspend && !adev->in_runpm)
2925                 return -EPERM;
2926
2927         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2928         if (r < 0) {
2929                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2930                 return r;
2931         }
2932
2933         /* get the sclk */
2934         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK,
2935                                    (void *)&mclk, &size);
2936
2937         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2938         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2939
2940         if (r)
2941                 return r;
2942
2943         return sysfs_emit(buf, "%u\n", mclk * 10 * 1000);
2944 }
2945
2946 static ssize_t amdgpu_hwmon_show_mclk_label(struct device *dev,
2947                                             struct device_attribute *attr,
2948                                             char *buf)
2949 {
2950         return sysfs_emit(buf, "mclk\n");
2951 }
2952
2953 /**
2954  * DOC: hwmon
2955  *
2956  * The amdgpu driver exposes the following sensor interfaces:
2957  *
2958  * - GPU temperature (via the on-die sensor)
2959  *
2960  * - GPU voltage
2961  *
2962  * - Northbridge voltage (APUs only)
2963  *
2964  * - GPU power
2965  *
2966  * - GPU fan
2967  *
2968  * - GPU gfx/compute engine clock
2969  *
2970  * - GPU memory clock (dGPU only)
2971  *
2972  * hwmon interfaces for GPU temperature:
2973  *
2974  * - temp[1-3]_input: the on die GPU temperature in millidegrees Celsius
2975  *   - temp2_input and temp3_input are supported on SOC15 dGPUs only
2976  *
2977  * - temp[1-3]_label: temperature channel label
2978  *   - temp2_label and temp3_label are supported on SOC15 dGPUs only
2979  *
2980  * - temp[1-3]_crit: temperature critical max value in millidegrees Celsius
2981  *   - temp2_crit and temp3_crit are supported on SOC15 dGPUs only
2982  *
2983  * - temp[1-3]_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius
2984  *   - temp2_crit_hyst and temp3_crit_hyst are supported on SOC15 dGPUs only
2985  *
2986  * - temp[1-3]_emergency: temperature emergency max value(asic shutdown) in millidegrees Celsius
2987  *   - these are supported on SOC15 dGPUs only
2988  *
2989  * hwmon interfaces for GPU voltage:
2990  *
2991  * - in0_input: the voltage on the GPU in millivolts
2992  *
2993  * - in1_input: the voltage on the Northbridge in millivolts
2994  *
2995  * hwmon interfaces for GPU power:
2996  *
2997  * - power1_average: average power used by the GPU in microWatts
2998  *
2999  * - power1_cap_min: minimum cap supported in microWatts
3000  *
3001  * - power1_cap_max: maximum cap supported in microWatts
3002  *
3003  * - power1_cap: selected power cap in microWatts
3004  *
3005  * hwmon interfaces for GPU fan:
3006  *
3007  * - pwm1: pulse width modulation fan level (0-255)
3008  *
3009  * - pwm1_enable: pulse width modulation fan control method (0: no fan speed control, 1: manual fan speed control using pwm interface, 2: automatic fan speed control)
3010  *
3011  * - pwm1_min: pulse width modulation fan control minimum level (0)
3012  *
3013  * - pwm1_max: pulse width modulation fan control maximum level (255)
3014  *
3015  * - fan1_min: a minimum value Unit: revolution/min (RPM)
3016  *
3017  * - fan1_max: a maximum value Unit: revolution/max (RPM)
3018  *
3019  * - fan1_input: fan speed in RPM
3020  *
3021  * - fan[1-\*]_target: Desired fan speed Unit: revolution/min (RPM)
3022  *
3023  * - fan[1-\*]_enable: Enable or disable the sensors.1: Enable 0: Disable
3024  *
3025  * hwmon interfaces for GPU clocks:
3026  *
3027  * - freq1_input: the gfx/compute clock in hertz
3028  *
3029  * - freq2_input: the memory clock in hertz
3030  *
3031  * You can use hwmon tools like sensors to view this information on your system.
3032  *
3033  */
3034
3035 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_EDGE);
3036 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
3037 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
3038 static SENSOR_DEVICE_ATTR(temp1_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_EDGE);
3039 static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_JUNCTION);
3040 static SENSOR_DEVICE_ATTR(temp2_crit, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 0);
3041 static SENSOR_DEVICE_ATTR(temp2_crit_hyst, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 1);
3042 static SENSOR_DEVICE_ATTR(temp2_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_JUNCTION);
3043 static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_MEM);
3044 static SENSOR_DEVICE_ATTR(temp3_crit, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 0);
3045 static SENSOR_DEVICE_ATTR(temp3_crit_hyst, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 1);
3046 static SENSOR_DEVICE_ATTR(temp3_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_MEM);
3047 static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_EDGE);
3048 static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_JUNCTION);
3049 static SENSOR_DEVICE_ATTR(temp3_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_MEM);
3050 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);
3051 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
3052 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
3053 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
3054 static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0);
3055 static SENSOR_DEVICE_ATTR(fan1_min, S_IRUGO, amdgpu_hwmon_get_fan1_min, NULL, 0);
3056 static SENSOR_DEVICE_ATTR(fan1_max, S_IRUGO, amdgpu_hwmon_get_fan1_max, NULL, 0);
3057 static SENSOR_DEVICE_ATTR(fan1_target, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_target, amdgpu_hwmon_set_fan1_target, 0);
3058 static SENSOR_DEVICE_ATTR(fan1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_enable, amdgpu_hwmon_set_fan1_enable, 0);
3059 static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 0);
3060 static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, NULL, 0);
3061 static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0);
3062 static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0);
3063 static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0);
3064 static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0);
3065 static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0);
3066 static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0);
3067 static SENSOR_DEVICE_ATTR(power1_cap_default, S_IRUGO, amdgpu_hwmon_show_power_cap_default, NULL, 0);
3068 static SENSOR_DEVICE_ATTR(power1_label, S_IRUGO, amdgpu_hwmon_show_power_label, NULL, 0);
3069 static SENSOR_DEVICE_ATTR(power2_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 1);
3070 static SENSOR_DEVICE_ATTR(power2_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 1);
3071 static SENSOR_DEVICE_ATTR(power2_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 1);
3072 static SENSOR_DEVICE_ATTR(power2_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 1);
3073 static SENSOR_DEVICE_ATTR(power2_cap_default, S_IRUGO, amdgpu_hwmon_show_power_cap_default, NULL, 1);
3074 static SENSOR_DEVICE_ATTR(power2_label, S_IRUGO, amdgpu_hwmon_show_power_label, NULL, 1);
3075 static SENSOR_DEVICE_ATTR(freq1_input, S_IRUGO, amdgpu_hwmon_show_sclk, NULL, 0);
3076 static SENSOR_DEVICE_ATTR(freq1_label, S_IRUGO, amdgpu_hwmon_show_sclk_label, NULL, 0);
3077 static SENSOR_DEVICE_ATTR(freq2_input, S_IRUGO, amdgpu_hwmon_show_mclk, NULL, 0);
3078 static SENSOR_DEVICE_ATTR(freq2_label, S_IRUGO, amdgpu_hwmon_show_mclk_label, NULL, 0);
3079
3080 static struct attribute *hwmon_attributes[] = {
3081         &sensor_dev_attr_temp1_input.dev_attr.attr,
3082         &sensor_dev_attr_temp1_crit.dev_attr.attr,
3083         &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
3084         &sensor_dev_attr_temp2_input.dev_attr.attr,
3085         &sensor_dev_attr_temp2_crit.dev_attr.attr,
3086         &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr,
3087         &sensor_dev_attr_temp3_input.dev_attr.attr,
3088         &sensor_dev_attr_temp3_crit.dev_attr.attr,
3089         &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr,
3090         &sensor_dev_attr_temp1_emergency.dev_attr.attr,
3091         &sensor_dev_attr_temp2_emergency.dev_attr.attr,
3092         &sensor_dev_attr_temp3_emergency.dev_attr.attr,
3093         &sensor_dev_attr_temp1_label.dev_attr.attr,
3094         &sensor_dev_attr_temp2_label.dev_attr.attr,
3095         &sensor_dev_attr_temp3_label.dev_attr.attr,
3096         &sensor_dev_attr_pwm1.dev_attr.attr,
3097         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
3098         &sensor_dev_attr_pwm1_min.dev_attr.attr,
3099         &sensor_dev_attr_pwm1_max.dev_attr.attr,
3100         &sensor_dev_attr_fan1_input.dev_attr.attr,
3101         &sensor_dev_attr_fan1_min.dev_attr.attr,
3102         &sensor_dev_attr_fan1_max.dev_attr.attr,
3103         &sensor_dev_attr_fan1_target.dev_attr.attr,
3104         &sensor_dev_attr_fan1_enable.dev_attr.attr,
3105         &sensor_dev_attr_in0_input.dev_attr.attr,
3106         &sensor_dev_attr_in0_label.dev_attr.attr,
3107         &sensor_dev_attr_in1_input.dev_attr.attr,
3108         &sensor_dev_attr_in1_label.dev_attr.attr,
3109         &sensor_dev_attr_power1_average.dev_attr.attr,
3110         &sensor_dev_attr_power1_cap_max.dev_attr.attr,
3111         &sensor_dev_attr_power1_cap_min.dev_attr.attr,
3112         &sensor_dev_attr_power1_cap.dev_attr.attr,
3113         &sensor_dev_attr_power1_cap_default.dev_attr.attr,
3114         &sensor_dev_attr_power1_label.dev_attr.attr,
3115         &sensor_dev_attr_power2_average.dev_attr.attr,
3116         &sensor_dev_attr_power2_cap_max.dev_attr.attr,
3117         &sensor_dev_attr_power2_cap_min.dev_attr.attr,
3118         &sensor_dev_attr_power2_cap.dev_attr.attr,
3119         &sensor_dev_attr_power2_cap_default.dev_attr.attr,
3120         &sensor_dev_attr_power2_label.dev_attr.attr,
3121         &sensor_dev_attr_freq1_input.dev_attr.attr,
3122         &sensor_dev_attr_freq1_label.dev_attr.attr,
3123         &sensor_dev_attr_freq2_input.dev_attr.attr,
3124         &sensor_dev_attr_freq2_label.dev_attr.attr,
3125         NULL
3126 };
3127
3128 static umode_t hwmon_attributes_visible(struct kobject *kobj,
3129                                         struct attribute *attr, int index)
3130 {
3131         struct device *dev = kobj_to_dev(kobj);
3132         struct amdgpu_device *adev = dev_get_drvdata(dev);
3133         umode_t effective_mode = attr->mode;
3134
3135         /* under multi-vf mode, the hwmon attributes are all not supported */
3136         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
3137                 return 0;
3138
3139         /* there is no fan under pp one vf mode */
3140         if (amdgpu_sriov_is_pp_one_vf(adev) &&
3141             (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3142              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3143              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3144              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3145              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3146              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3147              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3148              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3149              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3150                 return 0;
3151
3152         /* Skip fan attributes if fan is not present */
3153         if (adev->pm.no_fan && (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3154             attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3155             attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3156             attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3157             attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3158             attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3159             attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3160             attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3161             attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3162                 return 0;
3163
3164         /* Skip fan attributes on APU */
3165         if ((adev->flags & AMD_IS_APU) &&
3166             (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3167              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3168              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3169              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3170              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3171              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3172              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3173              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3174              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3175                 return 0;
3176
3177         /* Skip crit temp on APU */
3178         if ((adev->flags & AMD_IS_APU) && (adev->family >= AMDGPU_FAMILY_CZ) &&
3179             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
3180              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr))
3181                 return 0;
3182
3183         /* Skip limit attributes if DPM is not enabled */
3184         if (!adev->pm.dpm_enabled &&
3185             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
3186              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
3187              attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3188              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3189              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3190              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3191              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3192              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3193              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3194              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3195              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3196                 return 0;
3197
3198         if (!is_support_sw_smu(adev)) {
3199                 /* mask fan attributes if we have no bindings for this asic to expose */
3200                 if ((!adev->powerplay.pp_funcs->get_fan_speed_percent &&
3201                      attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
3202                     (!adev->powerplay.pp_funcs->get_fan_control_mode &&
3203                      attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
3204                         effective_mode &= ~S_IRUGO;
3205
3206                 if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
3207                      attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
3208                     (!adev->powerplay.pp_funcs->set_fan_control_mode &&
3209                      attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
3210                         effective_mode &= ~S_IWUSR;
3211         }
3212
3213         if (((adev->family == AMDGPU_FAMILY_SI) ||
3214                  ((adev->flags & AMD_IS_APU) &&
3215               (adev->asic_type != CHIP_VANGOGH))) &&    /* not implemented yet */
3216             (attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||
3217              attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr||
3218              attr == &sensor_dev_attr_power1_cap.dev_attr.attr ||
3219              attr == &sensor_dev_attr_power1_cap_default.dev_attr.attr))
3220                 return 0;
3221
3222         if (((adev->family == AMDGPU_FAMILY_SI) ||
3223              ((adev->flags & AMD_IS_APU) &&
3224               (adev->asic_type < CHIP_RENOIR))) &&      /* not implemented yet */
3225             (attr == &sensor_dev_attr_power1_average.dev_attr.attr))
3226                 return 0;
3227
3228         if (!is_support_sw_smu(adev)) {
3229                 /* hide max/min values if we can't both query and manage the fan */
3230                 if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
3231                      !adev->powerplay.pp_funcs->get_fan_speed_percent) &&
3232                      (!adev->powerplay.pp_funcs->set_fan_speed_rpm &&
3233                      !adev->powerplay.pp_funcs->get_fan_speed_rpm) &&
3234                     (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3235                      attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
3236                         return 0;
3237
3238                 if ((!adev->powerplay.pp_funcs->set_fan_speed_rpm &&
3239                      !adev->powerplay.pp_funcs->get_fan_speed_rpm) &&
3240                     (attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3241                      attr == &sensor_dev_attr_fan1_min.dev_attr.attr))
3242                         return 0;
3243         }
3244
3245         if ((adev->family == AMDGPU_FAMILY_SI ||        /* not implemented yet */
3246              adev->family == AMDGPU_FAMILY_KV) &&       /* not implemented yet */
3247             (attr == &sensor_dev_attr_in0_input.dev_attr.attr ||
3248              attr == &sensor_dev_attr_in0_label.dev_attr.attr))
3249                 return 0;
3250
3251         /* only APUs have vddnb */
3252         if (!(adev->flags & AMD_IS_APU) &&
3253             (attr == &sensor_dev_attr_in1_input.dev_attr.attr ||
3254              attr == &sensor_dev_attr_in1_label.dev_attr.attr))
3255                 return 0;
3256
3257         /* no mclk on APUs */
3258         if ((adev->flags & AMD_IS_APU) &&
3259             (attr == &sensor_dev_attr_freq2_input.dev_attr.attr ||
3260              attr == &sensor_dev_attr_freq2_label.dev_attr.attr))
3261                 return 0;
3262
3263         /* only SOC15 dGPUs support hotspot and mem temperatures */
3264         if (((adev->flags & AMD_IS_APU) ||
3265              adev->asic_type < CHIP_VEGA10) &&
3266             (attr == &sensor_dev_attr_temp2_crit.dev_attr.attr ||
3267              attr == &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr ||
3268              attr == &sensor_dev_attr_temp3_crit.dev_attr.attr ||
3269              attr == &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr ||
3270              attr == &sensor_dev_attr_temp1_emergency.dev_attr.attr ||
3271              attr == &sensor_dev_attr_temp2_emergency.dev_attr.attr ||
3272              attr == &sensor_dev_attr_temp3_emergency.dev_attr.attr ||
3273              attr == &sensor_dev_attr_temp2_input.dev_attr.attr ||
3274              attr == &sensor_dev_attr_temp3_input.dev_attr.attr ||
3275              attr == &sensor_dev_attr_temp2_label.dev_attr.attr ||
3276              attr == &sensor_dev_attr_temp3_label.dev_attr.attr))
3277                 return 0;
3278
3279         /* only Vangogh has fast PPT limit and power labels */
3280         if (!(adev->asic_type == CHIP_VANGOGH) &&
3281             (attr == &sensor_dev_attr_power2_average.dev_attr.attr ||
3282                  attr == &sensor_dev_attr_power2_cap_max.dev_attr.attr ||
3283              attr == &sensor_dev_attr_power2_cap_min.dev_attr.attr ||
3284                  attr == &sensor_dev_attr_power2_cap.dev_attr.attr ||
3285                  attr == &sensor_dev_attr_power2_cap_default.dev_attr.attr ||
3286                  attr == &sensor_dev_attr_power2_label.dev_attr.attr ||
3287                  attr == &sensor_dev_attr_power1_label.dev_attr.attr))
3288                 return 0;
3289
3290         return effective_mode;
3291 }
3292
3293 static const struct attribute_group hwmon_attrgroup = {
3294         .attrs = hwmon_attributes,
3295         .is_visible = hwmon_attributes_visible,
3296 };
3297
3298 static const struct attribute_group *hwmon_groups[] = {
3299         &hwmon_attrgroup,
3300         NULL
3301 };
3302
3303 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
3304 {
3305         int ret;
3306         uint32_t mask = 0;
3307
3308         if (adev->pm.sysfs_initialized)
3309                 return 0;
3310
3311         if (adev->pm.dpm_enabled == 0)
3312                 return 0;
3313
3314         INIT_LIST_HEAD(&adev->pm.pm_attr_list);
3315
3316         adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
3317                                                                    DRIVER_NAME, adev,
3318                                                                    hwmon_groups);
3319         if (IS_ERR(adev->pm.int_hwmon_dev)) {
3320                 ret = PTR_ERR(adev->pm.int_hwmon_dev);
3321                 dev_err(adev->dev,
3322                         "Unable to register hwmon device: %d\n", ret);
3323                 return ret;
3324         }
3325
3326         switch (amdgpu_virt_get_sriov_vf_mode(adev)) {
3327         case SRIOV_VF_MODE_ONE_VF:
3328                 mask = ATTR_FLAG_ONEVF;
3329                 break;
3330         case SRIOV_VF_MODE_MULTI_VF:
3331                 mask = 0;
3332                 break;
3333         case SRIOV_VF_MODE_BARE_METAL:
3334         default:
3335                 mask = ATTR_FLAG_MASK_ALL;
3336                 break;
3337         }
3338
3339         ret = amdgpu_device_attr_create_groups(adev,
3340                                                amdgpu_device_attrs,
3341                                                ARRAY_SIZE(amdgpu_device_attrs),
3342                                                mask,
3343                                                &adev->pm.pm_attr_list);
3344         if (ret)
3345                 return ret;
3346
3347         adev->pm.sysfs_initialized = true;
3348
3349         return 0;
3350 }
3351
3352 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
3353 {
3354         if (adev->pm.dpm_enabled == 0)
3355                 return;
3356
3357         if (adev->pm.int_hwmon_dev)
3358                 hwmon_device_unregister(adev->pm.int_hwmon_dev);
3359
3360         amdgpu_device_attr_remove_groups(adev, &adev->pm.pm_attr_list);
3361 }
3362
3363 /*
3364  * Debugfs info
3365  */
3366 #if defined(CONFIG_DEBUG_FS)
3367
3368 static void amdgpu_debugfs_prints_cpu_info(struct seq_file *m,
3369                                            struct amdgpu_device *adev) {
3370         uint16_t *p_val;
3371         uint32_t size;
3372         int i;
3373
3374         if (is_support_cclk_dpm(adev)) {
3375                 p_val = kcalloc(adev->smu.cpu_core_num, sizeof(uint16_t),
3376                                 GFP_KERNEL);
3377
3378                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_CPU_CLK,
3379                                             (void *)p_val, &size)) {
3380                         for (i = 0; i < adev->smu.cpu_core_num; i++)
3381                                 seq_printf(m, "\t%u MHz (CPU%d)\n",
3382                                            *(p_val + i), i);
3383                 }
3384
3385                 kfree(p_val);
3386         }
3387 }
3388
3389 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
3390 {
3391         uint32_t value;
3392         uint64_t value64 = 0;
3393         uint32_t query = 0;
3394         int size;
3395
3396         /* GPU Clocks */
3397         size = sizeof(value);
3398         seq_printf(m, "GFX Clocks and Power:\n");
3399
3400         amdgpu_debugfs_prints_cpu_info(m, adev);
3401
3402         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size))
3403                 seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
3404         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size))
3405                 seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
3406         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size))
3407                 seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100);
3408         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size))
3409                 seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100);
3410         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size))
3411                 seq_printf(m, "\t%u mV (VDDGFX)\n", value);
3412         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size))
3413                 seq_printf(m, "\t%u mV (VDDNB)\n", value);
3414         size = sizeof(uint32_t);
3415         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, (void *)&query, &size))
3416                 seq_printf(m, "\t%u.%u W (average GPU)\n", query >> 8, query & 0xff);
3417         size = sizeof(value);
3418         seq_printf(m, "\n");
3419
3420         /* GPU Temp */
3421         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size))
3422                 seq_printf(m, "GPU Temperature: %u C\n", value/1000);
3423
3424         /* GPU Load */
3425         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size))
3426                 seq_printf(m, "GPU Load: %u %%\n", value);
3427         /* MEM Load */
3428         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD, (void *)&value, &size))
3429                 seq_printf(m, "MEM Load: %u %%\n", value);
3430
3431         seq_printf(m, "\n");
3432
3433         /* SMC feature mask */
3434         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, (void *)&value64, &size))
3435                 seq_printf(m, "SMC Feature Mask: 0x%016llx\n", value64);
3436
3437         if (adev->asic_type > CHIP_VEGA20) {
3438                 /* VCN clocks */
3439                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCN_POWER_STATE, (void *)&value, &size)) {
3440                         if (!value) {
3441                                 seq_printf(m, "VCN: Disabled\n");
3442                         } else {
3443                                 seq_printf(m, "VCN: Enabled\n");
3444                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
3445                                         seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
3446                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
3447                                         seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
3448                         }
3449                 }
3450                 seq_printf(m, "\n");
3451         } else {
3452                 /* UVD clocks */
3453                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {
3454                         if (!value) {
3455                                 seq_printf(m, "UVD: Disabled\n");
3456                         } else {
3457                                 seq_printf(m, "UVD: Enabled\n");
3458                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
3459                                         seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
3460                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
3461                                         seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
3462                         }
3463                 }
3464                 seq_printf(m, "\n");
3465
3466                 /* VCE clocks */
3467                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) {
3468                         if (!value) {
3469                                 seq_printf(m, "VCE: Disabled\n");
3470                         } else {
3471                                 seq_printf(m, "VCE: Enabled\n");
3472                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size))
3473                                         seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
3474                         }
3475                 }
3476         }
3477
3478         return 0;
3479 }
3480
3481 static void amdgpu_parse_cg_state(struct seq_file *m, u32 flags)
3482 {
3483         int i;
3484
3485         for (i = 0; clocks[i].flag; i++)
3486                 seq_printf(m, "\t%s: %s\n", clocks[i].name,
3487                            (flags & clocks[i].flag) ? "On" : "Off");
3488 }
3489
3490 static int amdgpu_debugfs_pm_info_show(struct seq_file *m, void *unused)
3491 {
3492         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
3493         struct drm_device *dev = adev_to_drm(adev);
3494         u32 flags = 0;
3495         int r;
3496
3497         if (amdgpu_in_reset(adev))
3498                 return -EPERM;
3499         if (adev->in_suspend && !adev->in_runpm)
3500                 return -EPERM;
3501
3502         r = pm_runtime_get_sync(dev->dev);
3503         if (r < 0) {
3504                 pm_runtime_put_autosuspend(dev->dev);
3505                 return r;
3506         }
3507
3508         if (!adev->pm.dpm_enabled) {
3509                 seq_printf(m, "dpm not enabled\n");
3510                 pm_runtime_mark_last_busy(dev->dev);
3511                 pm_runtime_put_autosuspend(dev->dev);
3512                 return 0;
3513         }
3514
3515         if (!is_support_sw_smu(adev) &&
3516             adev->powerplay.pp_funcs->debugfs_print_current_performance_level) {
3517                 mutex_lock(&adev->pm.mutex);
3518                 if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level)
3519                         adev->powerplay.pp_funcs->debugfs_print_current_performance_level(adev, m);
3520                 else
3521                         seq_printf(m, "Debugfs support not implemented for this asic\n");
3522                 mutex_unlock(&adev->pm.mutex);
3523                 r = 0;
3524         } else {
3525                 r = amdgpu_debugfs_pm_info_pp(m, adev);
3526         }
3527         if (r)
3528                 goto out;
3529
3530         amdgpu_device_ip_get_clockgating_state(adev, &flags);
3531
3532         seq_printf(m, "Clock Gating Flags Mask: 0x%x\n", flags);
3533         amdgpu_parse_cg_state(m, flags);
3534         seq_printf(m, "\n");
3535
3536 out:
3537         pm_runtime_mark_last_busy(dev->dev);
3538         pm_runtime_put_autosuspend(dev->dev);
3539
3540         return r;
3541 }
3542
3543 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_pm_info);
3544
3545 /*
3546  * amdgpu_pm_priv_buffer_read - Read memory region allocated to FW
3547  *
3548  * Reads debug memory region allocated to PMFW
3549  */
3550 static ssize_t amdgpu_pm_prv_buffer_read(struct file *f, char __user *buf,
3551                                          size_t size, loff_t *pos)
3552 {
3553         struct amdgpu_device *adev = file_inode(f)->i_private;
3554         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
3555         void *pp_handle = adev->powerplay.pp_handle;
3556         size_t smu_prv_buf_size;
3557         void *smu_prv_buf;
3558
3559         if (amdgpu_in_reset(adev))
3560                 return -EPERM;
3561         if (adev->in_suspend && !adev->in_runpm)
3562                 return -EPERM;
3563
3564         if (pp_funcs && pp_funcs->get_smu_prv_buf_details)
3565                 pp_funcs->get_smu_prv_buf_details(pp_handle, &smu_prv_buf,
3566                                                   &smu_prv_buf_size);
3567         else
3568                 return -ENOSYS;
3569
3570         if (!smu_prv_buf || !smu_prv_buf_size)
3571                 return -EINVAL;
3572
3573         return simple_read_from_buffer(buf, size, pos, smu_prv_buf,
3574                                        smu_prv_buf_size);
3575 }
3576
3577 static const struct file_operations amdgpu_debugfs_pm_prv_buffer_fops = {
3578         .owner = THIS_MODULE,
3579         .open = simple_open,
3580         .read = amdgpu_pm_prv_buffer_read,
3581         .llseek = default_llseek,
3582 };
3583
3584 #endif
3585
3586 void amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
3587 {
3588 #if defined(CONFIG_DEBUG_FS)
3589         struct drm_minor *minor = adev_to_drm(adev)->primary;
3590         struct dentry *root = minor->debugfs_root;
3591
3592         debugfs_create_file("amdgpu_pm_info", 0444, root, adev,
3593                             &amdgpu_debugfs_pm_info_fops);
3594
3595         if (adev->pm.smu_prv_buffer_size > 0)
3596                 debugfs_create_file_size("amdgpu_pm_prv_buffer", 0444, root,
3597                                          adev,
3598                                          &amdgpu_debugfs_pm_prv_buffer_fops,
3599                                          adev->pm.smu_prv_buffer_size);
3600 #endif
3601 }