drivers/gpu/drm/amd/pm/amdgpu_dpm.c

   1 /*
   2  * Copyright 2011 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24
  25 #include "amdgpu.h"
  26 #include "amdgpu_atombios.h"
  27 #include "amdgpu_i2c.h"
  28 #include "amdgpu_dpm.h"
  29 #include "atom.h"
  30 #include "amd_pcie.h"
  31 #include "amdgpu_display.h"
  32 #include "hwmgr.h"
  33 #include <linux/power_supply.h>
  34 #include "amdgpu_smu.h"
  35
  36 #define amdgpu_dpm_enable_bapm(adev, e) \
  37                 ((adev)->powerplay.pp_funcs->enable_bapm((adev)->powerplay.pp_handle, (e)))
  38
  39 int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low)
  40 {
  41         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
  42         int ret = 0;
  43
  44         if (!pp_funcs->get_sclk)
  45                 return 0;
  46
  47         mutex_lock(&adev->pm.mutex);
  48         ret = pp_funcs->get_sclk((adev)->powerplay.pp_handle,
  49                                  low);
  50         mutex_unlock(&adev->pm.mutex);
  51
  52         return ret;
  53 }
  54
  55 int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool low)
  56 {
  57         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
  58         int ret = 0;
  59
  60         if (!pp_funcs->get_mclk)
  61                 return 0;
  62
  63         mutex_lock(&adev->pm.mutex);
  64         ret = pp_funcs->get_mclk((adev)->powerplay.pp_handle,
  65                                  low);
  66         mutex_unlock(&adev->pm.mutex);
  67
  68         return ret;
  69 }
  70
  71 int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, uint32_t block_type, bool gate)
  72 {
  73         int ret = 0;
  74         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
  75         enum ip_power_state pwr_state = gate ? POWER_STATE_OFF : POWER_STATE_ON;
  76
  77         if (atomic_read(&adev->pm.pwr_state[block_type]) == pwr_state) {
  78                 dev_dbg(adev->dev, "IP block%d already in the target %s state!",
  79                                 block_type, gate ? "gate" : "ungate");
  80                 return 0;
  81         }
  82
  83         mutex_lock(&adev->pm.mutex);
  84
  85         switch (block_type) {
  86         case AMD_IP_BLOCK_TYPE_UVD:
  87         case AMD_IP_BLOCK_TYPE_VCE:
  88         case AMD_IP_BLOCK_TYPE_GFX:
  89         case AMD_IP_BLOCK_TYPE_VCN:
  90         case AMD_IP_BLOCK_TYPE_SDMA:
  91         case AMD_IP_BLOCK_TYPE_JPEG:
  92         case AMD_IP_BLOCK_TYPE_GMC:
  93         case AMD_IP_BLOCK_TYPE_ACP:
  94                 if (pp_funcs && pp_funcs->set_powergating_by_smu)
  95                         ret = (pp_funcs->set_powergating_by_smu(
  96                                 (adev)->powerplay.pp_handle, block_type, gate));
  97                 break;
  98         default:
  99                 break;
 100         }
 101
 102         if (!ret)
 103                 atomic_set(&adev->pm.pwr_state[block_type], pwr_state);
 104
 105         mutex_unlock(&adev->pm.mutex);
 106
 107         return ret;
 108 }
 109
 110 int amdgpu_dpm_set_gfx_power_up_by_imu(struct amdgpu_device *adev)
 111 {
 112         struct smu_context *smu = adev->powerplay.pp_handle;
 113         int ret = -EOPNOTSUPP;
 114
 115         mutex_lock(&adev->pm.mutex);
 116         ret = smu_set_gfx_power_up_by_imu(smu);
 117         mutex_unlock(&adev->pm.mutex);
 118
 119         msleep(10);
 120
 121         return ret;
 122 }
 123
 124 int amdgpu_dpm_baco_enter(struct amdgpu_device *adev)
 125 {
 126         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 127         void *pp_handle = adev->powerplay.pp_handle;
 128         int ret = 0;
 129
 130         if (!pp_funcs || !pp_funcs->set_asic_baco_state)
 131                 return -ENOENT;
 132
 133         mutex_lock(&adev->pm.mutex);
 134
 135         /* enter BACO state */
 136         ret = pp_funcs->set_asic_baco_state(pp_handle, 1);
 137
 138         mutex_unlock(&adev->pm.mutex);
 139
 140         return ret;
 141 }
 142
 143 int amdgpu_dpm_baco_exit(struct amdgpu_device *adev)
 144 {
 145         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 146         void *pp_handle = adev->powerplay.pp_handle;
 147         int ret = 0;
 148
 149         if (!pp_funcs || !pp_funcs->set_asic_baco_state)
 150                 return -ENOENT;
 151
 152         mutex_lock(&adev->pm.mutex);
 153
 154         /* exit BACO state */
 155         ret = pp_funcs->set_asic_baco_state(pp_handle, 0);
 156
 157         mutex_unlock(&adev->pm.mutex);
 158
 159         return ret;
 160 }
 161
 162 int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev,
 163                              enum pp_mp1_state mp1_state)
 164 {
 165         int ret = 0;
 166         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 167
 168         if (pp_funcs && pp_funcs->set_mp1_state) {
 169                 mutex_lock(&adev->pm.mutex);
 170
 171                 ret = pp_funcs->set_mp1_state(
 172                                 adev->powerplay.pp_handle,
 173                                 mp1_state);
 174
 175                 mutex_unlock(&adev->pm.mutex);
 176         }
 177
 178         return ret;
 179 }
 180
 181 bool amdgpu_dpm_is_baco_supported(struct amdgpu_device *adev)
 182 {
 183         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 184         void *pp_handle = adev->powerplay.pp_handle;
 185         bool baco_cap;
 186         int ret = 0;
 187
 188         if (!pp_funcs || !pp_funcs->get_asic_baco_capability)
 189                 return false;
 190         /* Don't use baco for reset in S3.
 191          * This is a workaround for some platforms
 192          * where entering BACO during suspend
 193          * seems to cause reboots or hangs.
 194          * This might be related to the fact that BACO controls
 195          * power to the whole GPU including devices like audio and USB.
 196          * Powering down/up everything may adversely affect these other
 197          * devices.  Needs more investigation.
 198          */
 199         if (adev->in_s3)
 200                 return false;
 201
 202         mutex_lock(&adev->pm.mutex);
 203
 204         ret = pp_funcs->get_asic_baco_capability(pp_handle,
 205                                                  &baco_cap);
 206
 207         mutex_unlock(&adev->pm.mutex);
 208
 209         return ret ? false : baco_cap;
 210 }
 211
 212 int amdgpu_dpm_mode2_reset(struct amdgpu_device *adev)
 213 {
 214         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 215         void *pp_handle = adev->powerplay.pp_handle;
 216         int ret = 0;
 217
 218         if (!pp_funcs || !pp_funcs->asic_reset_mode_2)
 219                 return -ENOENT;
 220
 221         mutex_lock(&adev->pm.mutex);
 222
 223         ret = pp_funcs->asic_reset_mode_2(pp_handle);
 224
 225         mutex_unlock(&adev->pm.mutex);
 226
 227         return ret;
 228 }
 229
 230 int amdgpu_dpm_baco_reset(struct amdgpu_device *adev)
 231 {
 232         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 233         void *pp_handle = adev->powerplay.pp_handle;
 234         int ret = 0;
 235
 236         if (!pp_funcs || !pp_funcs->set_asic_baco_state)
 237                 return -ENOENT;
 238
 239         mutex_lock(&adev->pm.mutex);
 240
 241         /* enter BACO state */
 242         ret = pp_funcs->set_asic_baco_state(pp_handle, 1);
 243         if (ret)
 244                 goto out;
 245
 246         /* exit BACO state */
 247         ret = pp_funcs->set_asic_baco_state(pp_handle, 0);
 248
 249 out:
 250         mutex_unlock(&adev->pm.mutex);
 251         return ret;
 252 }
 253
 254 bool amdgpu_dpm_is_mode1_reset_supported(struct amdgpu_device *adev)
 255 {
 256         struct smu_context *smu = adev->powerplay.pp_handle;
 257         bool support_mode1_reset = false;
 258
 259         if (is_support_sw_smu(adev)) {
 260                 mutex_lock(&adev->pm.mutex);
 261                 support_mode1_reset = smu_mode1_reset_is_support(smu);
 262                 mutex_unlock(&adev->pm.mutex);
 263         }
 264
 265         return support_mode1_reset;
 266 }
 267
 268 int amdgpu_dpm_mode1_reset(struct amdgpu_device *adev)
 269 {
 270         struct smu_context *smu = adev->powerplay.pp_handle;
 271         int ret = -EOPNOTSUPP;
 272
 273         if (is_support_sw_smu(adev)) {
 274                 mutex_lock(&adev->pm.mutex);
 275                 ret = smu_mode1_reset(smu);
 276                 mutex_unlock(&adev->pm.mutex);
 277         }
 278
 279         return ret;
 280 }
 281
 282 int amdgpu_dpm_switch_power_profile(struct amdgpu_device *adev,
 283                                     enum PP_SMC_POWER_PROFILE type,
 284                                     bool en)
 285 {
 286         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 287         int ret = 0;
 288
 289         if (amdgpu_sriov_vf(adev))
 290                 return 0;
 291
 292         if (pp_funcs && pp_funcs->switch_power_profile) {
 293                 mutex_lock(&adev->pm.mutex);
 294                 ret = pp_funcs->switch_power_profile(
 295                         adev->powerplay.pp_handle, type, en);
 296                 mutex_unlock(&adev->pm.mutex);
 297         }
 298
 299         return ret;
 300 }
 301
 302 int amdgpu_dpm_set_xgmi_pstate(struct amdgpu_device *adev,
 303                                uint32_t pstate)
 304 {
 305         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 306         int ret = 0;
 307
 308         if (pp_funcs && pp_funcs->set_xgmi_pstate) {
 309                 mutex_lock(&adev->pm.mutex);
 310                 ret = pp_funcs->set_xgmi_pstate(adev->powerplay.pp_handle,
 311                                                                 pstate);
 312                 mutex_unlock(&adev->pm.mutex);
 313         }
 314
 315         return ret;
 316 }
 317
 318 int amdgpu_dpm_set_df_cstate(struct amdgpu_device *adev,
 319                              uint32_t cstate)
 320 {
 321         int ret = 0;
 322         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 323         void *pp_handle = adev->powerplay.pp_handle;
 324
 325         if (pp_funcs && pp_funcs->set_df_cstate) {
 326                 mutex_lock(&adev->pm.mutex);
 327                 ret = pp_funcs->set_df_cstate(pp_handle, cstate);
 328                 mutex_unlock(&adev->pm.mutex);
 329         }
 330
 331         return ret;
 332 }
 333
 334 int amdgpu_dpm_allow_xgmi_power_down(struct amdgpu_device *adev, bool en)
 335 {
 336         struct smu_context *smu = adev->powerplay.pp_handle;
 337         int ret = 0;
 338
 339         if (is_support_sw_smu(adev)) {
 340                 mutex_lock(&adev->pm.mutex);
 341                 ret = smu_allow_xgmi_power_down(smu, en);
 342                 mutex_unlock(&adev->pm.mutex);
 343         }
 344
 345         return ret;
 346 }
 347
 348 int amdgpu_dpm_enable_mgpu_fan_boost(struct amdgpu_device *adev)
 349 {
 350         void *pp_handle = adev->powerplay.pp_handle;
 351         const struct amd_pm_funcs *pp_funcs =
 352                         adev->powerplay.pp_funcs;
 353         int ret = 0;
 354
 355         if (pp_funcs && pp_funcs->enable_mgpu_fan_boost) {
 356                 mutex_lock(&adev->pm.mutex);
 357                 ret = pp_funcs->enable_mgpu_fan_boost(pp_handle);
 358                 mutex_unlock(&adev->pm.mutex);
 359         }
 360
 361         return ret;
 362 }
 363
 364 int amdgpu_dpm_set_clockgating_by_smu(struct amdgpu_device *adev,
 365                                       uint32_t msg_id)
 366 {
 367         void *pp_handle = adev->powerplay.pp_handle;
 368         const struct amd_pm_funcs *pp_funcs =
 369                         adev->powerplay.pp_funcs;
 370         int ret = 0;
 371
 372         if (pp_funcs && pp_funcs->set_clockgating_by_smu) {
 373                 mutex_lock(&adev->pm.mutex);
 374                 ret = pp_funcs->set_clockgating_by_smu(pp_handle,
 375                                                        msg_id);
 376                 mutex_unlock(&adev->pm.mutex);
 377         }
 378
 379         return ret;
 380 }
 381
 382 int amdgpu_dpm_smu_i2c_bus_access(struct amdgpu_device *adev,
 383                                   bool acquire)
 384 {
 385         void *pp_handle = adev->powerplay.pp_handle;
 386         const struct amd_pm_funcs *pp_funcs =
 387                         adev->powerplay.pp_funcs;
 388         int ret = -EOPNOTSUPP;
 389
 390         if (pp_funcs && pp_funcs->smu_i2c_bus_access) {
 391                 mutex_lock(&adev->pm.mutex);
 392                 ret = pp_funcs->smu_i2c_bus_access(pp_handle,
 393                                                    acquire);
 394                 mutex_unlock(&adev->pm.mutex);
 395         }
 396
 397         return ret;
 398 }
 399
 400 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev)
 401 {
 402         if (adev->pm.dpm_enabled) {
 403                 mutex_lock(&adev->pm.mutex);
 404                 if (power_supply_is_system_supplied() > 0)
 405                         adev->pm.ac_power = true;
 406                 else
 407                         adev->pm.ac_power = false;
 408
 409                 if (adev->powerplay.pp_funcs &&
 410                     adev->powerplay.pp_funcs->enable_bapm)
 411                         amdgpu_dpm_enable_bapm(adev, adev->pm.ac_power);
 412
 413                 if (is_support_sw_smu(adev))
 414                         smu_set_ac_dc(adev->powerplay.pp_handle);
 415
 416                 mutex_unlock(&adev->pm.mutex);
 417         }
 418 }
 419
 420 int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors sensor,
 421                            void *data, uint32_t *size)
 422 {
 423         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 424         int ret = -EINVAL;
 425
 426         if (!data || !size)
 427                 return -EINVAL;
 428
 429         if (pp_funcs && pp_funcs->read_sensor) {
 430                 mutex_lock(&adev->pm.mutex);
 431                 ret = pp_funcs->read_sensor(adev->powerplay.pp_handle,
 432                                             sensor,
 433                                             data,
 434                                             size);
 435                 mutex_unlock(&adev->pm.mutex);
 436         }
 437
 438         return ret;
 439 }
 440
 441 void amdgpu_dpm_compute_clocks(struct amdgpu_device *adev)
 442 {
 443         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 444         int i;
 445
 446         if (!adev->pm.dpm_enabled)
 447                 return;
 448
 449         if (!pp_funcs->pm_compute_clocks)
 450                 return;
 451
 452         if (adev->mode_info.num_crtc)
 453                 amdgpu_display_bandwidth_update(adev);
 454
 455         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
 456                 struct amdgpu_ring *ring = adev->rings[i];
 457                 if (ring && ring->sched.ready)
 458                         amdgpu_fence_wait_empty(ring);
 459         }
 460
 461         mutex_lock(&adev->pm.mutex);
 462         pp_funcs->pm_compute_clocks(adev->powerplay.pp_handle);
 463         mutex_unlock(&adev->pm.mutex);
 464 }
 465
 466 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
 467 {
 468         int ret = 0;
 469
 470         if (adev->family == AMDGPU_FAMILY_SI) {
 471                 mutex_lock(&adev->pm.mutex);
 472                 if (enable) {
 473                         adev->pm.dpm.uvd_active = true;
 474                         adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD;
 475                 } else {
 476                         adev->pm.dpm.uvd_active = false;
 477                 }
 478                 mutex_unlock(&adev->pm.mutex);
 479
 480                 amdgpu_dpm_compute_clocks(adev);
 481                 return;
 482         }
 483
 484         ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable);
 485         if (ret)
 486                 DRM_ERROR("Dpm %s uvd failed, ret = %d. \n",
 487                           enable ? "enable" : "disable", ret);
 488 }
 489
 490 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
 491 {
 492         int ret = 0;
 493
 494         if (adev->family == AMDGPU_FAMILY_SI) {
 495                 mutex_lock(&adev->pm.mutex);
 496                 if (enable) {
 497                         adev->pm.dpm.vce_active = true;
 498                         /* XXX select vce level based on ring/task */
 499                         adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL;
 500                 } else {
 501                         adev->pm.dpm.vce_active = false;
 502                 }
 503                 mutex_unlock(&adev->pm.mutex);
 504
 505                 amdgpu_dpm_compute_clocks(adev);
 506                 return;
 507         }
 508
 509         ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCE, !enable);
 510         if (ret)
 511                 DRM_ERROR("Dpm %s vce failed, ret = %d. \n",
 512                           enable ? "enable" : "disable", ret);
 513 }
 514
 515 void amdgpu_dpm_enable_jpeg(struct amdgpu_device *adev, bool enable)
 516 {
 517         int ret = 0;
 518
 519         ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_JPEG, !enable);
 520         if (ret)
 521                 DRM_ERROR("Dpm %s jpeg failed, ret = %d. \n",
 522                           enable ? "enable" : "disable", ret);
 523 }
 524
 525 int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version)
 526 {
 527         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 528         int r = 0;
 529
 530         if (!pp_funcs || !pp_funcs->load_firmware)
 531                 return 0;
 532
 533         mutex_lock(&adev->pm.mutex);
 534         r = pp_funcs->load_firmware(adev->powerplay.pp_handle);
 535         if (r) {
 536                 pr_err("smu firmware loading failed\n");
 537                 goto out;
 538         }
 539
 540         if (smu_version)
 541                 *smu_version = adev->pm.fw_version;
 542
 543 out:
 544         mutex_unlock(&adev->pm.mutex);
 545         return r;
 546 }
 547
 548 int amdgpu_dpm_handle_passthrough_sbr(struct amdgpu_device *adev, bool enable)
 549 {
 550         int ret = 0;
 551
 552         if (is_support_sw_smu(adev)) {
 553                 mutex_lock(&adev->pm.mutex);
 554                 ret = smu_handle_passthrough_sbr(adev->powerplay.pp_handle,
 555                                                  enable);
 556                 mutex_unlock(&adev->pm.mutex);
 557         }
 558
 559         return ret;
 560 }
 561
 562 int amdgpu_dpm_send_hbm_bad_pages_num(struct amdgpu_device *adev, uint32_t size)
 563 {
 564         struct smu_context *smu = adev->powerplay.pp_handle;
 565         int ret = 0;
 566
 567         if (!is_support_sw_smu(adev))
 568                 return -EOPNOTSUPP;
 569
 570         mutex_lock(&adev->pm.mutex);
 571         ret = smu_send_hbm_bad_pages_num(smu, size);
 572         mutex_unlock(&adev->pm.mutex);
 573
 574         return ret;
 575 }
 576
 577 int amdgpu_dpm_send_hbm_bad_channel_flag(struct amdgpu_device *adev, uint32_t size)
 578 {
 579         struct smu_context *smu = adev->powerplay.pp_handle;
 580         int ret = 0;
 581
 582         if (!is_support_sw_smu(adev))
 583                 return -EOPNOTSUPP;
 584
 585         mutex_lock(&adev->pm.mutex);
 586         ret = smu_send_hbm_bad_channel_flag(smu, size);
 587         mutex_unlock(&adev->pm.mutex);
 588
 589         return ret;
 590 }
 591
 592 int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev,
 593                                   enum pp_clock_type type,
 594                                   uint32_t *min,
 595                                   uint32_t *max)
 596 {
 597         int ret = 0;
 598
 599         if (type != PP_SCLK)
 600                 return -EINVAL;
 601
 602         if (!is_support_sw_smu(adev))
 603                 return -EOPNOTSUPP;
 604
 605         mutex_lock(&adev->pm.mutex);
 606         ret = smu_get_dpm_freq_range(adev->powerplay.pp_handle,
 607                                      SMU_SCLK,
 608                                      min,
 609                                      max);
 610         mutex_unlock(&adev->pm.mutex);
 611
 612         return ret;
 613 }
 614
 615 int amdgpu_dpm_set_soft_freq_range(struct amdgpu_device *adev,
 616                                    enum pp_clock_type type,
 617                                    uint32_t min,
 618                                    uint32_t max)
 619 {
 620         struct smu_context *smu = adev->powerplay.pp_handle;
 621         int ret = 0;
 622
 623         if (type != PP_SCLK)
 624                 return -EINVAL;
 625
 626         if (!is_support_sw_smu(adev))
 627                 return -EOPNOTSUPP;
 628
 629         mutex_lock(&adev->pm.mutex);
 630         ret = smu_set_soft_freq_range(smu,
 631                                       SMU_SCLK,
 632                                       min,
 633                                       max);
 634         mutex_unlock(&adev->pm.mutex);
 635
 636         return ret;
 637 }
 638
 639 int amdgpu_dpm_write_watermarks_table(struct amdgpu_device *adev)
 640 {
 641         struct smu_context *smu = adev->powerplay.pp_handle;
 642         int ret = 0;
 643
 644         if (!is_support_sw_smu(adev))
 645                 return 0;
 646
 647         mutex_lock(&adev->pm.mutex);
 648         ret = smu_write_watermarks_table(smu);
 649         mutex_unlock(&adev->pm.mutex);
 650
 651         return ret;
 652 }
 653
 654 int amdgpu_dpm_wait_for_event(struct amdgpu_device *adev,
 655                               enum smu_event_type event,
 656                               uint64_t event_arg)
 657 {
 658         struct smu_context *smu = adev->powerplay.pp_handle;
 659         int ret = 0;
 660
 661         if (!is_support_sw_smu(adev))
 662                 return -EOPNOTSUPP;
 663
 664         mutex_lock(&adev->pm.mutex);
 665         ret = smu_wait_for_event(smu, event, event_arg);
 666         mutex_unlock(&adev->pm.mutex);
 667
 668         return ret;
 669 }
 670
 671 int amdgpu_dpm_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value)
 672 {
 673         struct smu_context *smu = adev->powerplay.pp_handle;
 674         int ret = 0;
 675
 676         if (!is_support_sw_smu(adev))
 677                 return -EOPNOTSUPP;
 678
 679         mutex_lock(&adev->pm.mutex);
 680         ret = smu_get_status_gfxoff(smu, value);
 681         mutex_unlock(&adev->pm.mutex);
 682
 683         return ret;
 684 }
 685
 686 uint64_t amdgpu_dpm_get_thermal_throttling_counter(struct amdgpu_device *adev)
 687 {
 688         struct smu_context *smu = adev->powerplay.pp_handle;
 689
 690         if (!is_support_sw_smu(adev))
 691                 return 0;
 692
 693         return atomic64_read(&smu->throttle_int_counter);
 694 }
 695
 696 /* amdgpu_dpm_gfx_state_change - Handle gfx power state change set
 697  * @adev: amdgpu_device pointer
 698  * @state: gfx power state(1 -sGpuChangeState_D0Entry and 2 -sGpuChangeState_D3Entry)
 699  *
 700  */
 701 void amdgpu_dpm_gfx_state_change(struct amdgpu_device *adev,
 702                                  enum gfx_change_state state)
 703 {
 704         mutex_lock(&adev->pm.mutex);
 705         if (adev->powerplay.pp_funcs &&
 706             adev->powerplay.pp_funcs->gfx_state_change_set)
 707                 ((adev)->powerplay.pp_funcs->gfx_state_change_set(
 708                         (adev)->powerplay.pp_handle, state));
 709         mutex_unlock(&adev->pm.mutex);
 710 }
 711
 712 int amdgpu_dpm_get_ecc_info(struct amdgpu_device *adev,
 713                             void *umc_ecc)
 714 {
 715         struct smu_context *smu = adev->powerplay.pp_handle;
 716         int ret = 0;
 717
 718         if (!is_support_sw_smu(adev))
 719                 return -EOPNOTSUPP;
 720
 721         mutex_lock(&adev->pm.mutex);
 722         ret = smu_get_ecc_info(smu, umc_ecc);
 723         mutex_unlock(&adev->pm.mutex);
 724
 725         return ret;
 726 }
 727
 728 struct amd_vce_state *amdgpu_dpm_get_vce_clock_state(struct amdgpu_device *adev,
 729                                                      uint32_t idx)
 730 {
 731         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 732         struct amd_vce_state *vstate = NULL;
 733
 734         if (!pp_funcs->get_vce_clock_state)
 735                 return NULL;
 736
 737         mutex_lock(&adev->pm.mutex);
 738         vstate = pp_funcs->get_vce_clock_state(adev->powerplay.pp_handle,
 739                                                idx);
 740         mutex_unlock(&adev->pm.mutex);
 741
 742         return vstate;
 743 }
 744
 745 void amdgpu_dpm_get_current_power_state(struct amdgpu_device *adev,
 746                                         enum amd_pm_state_type *state)
 747 {
 748         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 749
 750         mutex_lock(&adev->pm.mutex);
 751
 752         if (!pp_funcs->get_current_power_state) {
 753                 *state = adev->pm.dpm.user_state;
 754                 goto out;
 755         }
 756
 757         *state = pp_funcs->get_current_power_state(adev->powerplay.pp_handle);
 758         if (*state < POWER_STATE_TYPE_DEFAULT ||
 759             *state > POWER_STATE_TYPE_INTERNAL_3DPERF)
 760                 *state = adev->pm.dpm.user_state;
 761
 762 out:
 763         mutex_unlock(&adev->pm.mutex);
 764 }
 765
 766 void amdgpu_dpm_set_power_state(struct amdgpu_device *adev,
 767                                 enum amd_pm_state_type state)
 768 {
 769         mutex_lock(&adev->pm.mutex);
 770         adev->pm.dpm.user_state = state;
 771         mutex_unlock(&adev->pm.mutex);
 772
 773         if (is_support_sw_smu(adev))
 774                 return;
 775
 776         if (amdgpu_dpm_dispatch_task(adev,
 777                                      AMD_PP_TASK_ENABLE_USER_STATE,
 778                                      &state) == -EOPNOTSUPP)
 779                 amdgpu_dpm_compute_clocks(adev);
 780 }
 781
 782 enum amd_dpm_forced_level amdgpu_dpm_get_performance_level(struct amdgpu_device *adev)
 783 {
 784         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 785         enum amd_dpm_forced_level level;
 786
 787         if (!pp_funcs)
 788                 return AMD_DPM_FORCED_LEVEL_AUTO;
 789
 790         mutex_lock(&adev->pm.mutex);
 791         if (pp_funcs->get_performance_level)
 792                 level = pp_funcs->get_performance_level(adev->powerplay.pp_handle);
 793         else
 794                 level = adev->pm.dpm.forced_level;
 795         mutex_unlock(&adev->pm.mutex);
 796
 797         return level;
 798 }
 799
 800 int amdgpu_dpm_force_performance_level(struct amdgpu_device *adev,
 801                                        enum amd_dpm_forced_level level)
 802 {
 803         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 804         enum amd_dpm_forced_level current_level;
 805         uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
 806                                         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
 807                                         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
 808                                         AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
 809
 810         if (!pp_funcs || !pp_funcs->force_performance_level)
 811                 return 0;
 812
 813         if (adev->pm.dpm.thermal_active)
 814                 return -EINVAL;
 815
 816         current_level = amdgpu_dpm_get_performance_level(adev);
 817         if (current_level == level)
 818                 return 0;
 819
 820         if (adev->asic_type == CHIP_RAVEN) {
 821                 if (!(adev->apu_flags & AMD_APU_IS_RAVEN2)) {
 822                         if (current_level != AMD_DPM_FORCED_LEVEL_MANUAL &&
 823                             level == AMD_DPM_FORCED_LEVEL_MANUAL)
 824                                 amdgpu_gfx_off_ctrl(adev, false);
 825                         else if (current_level == AMD_DPM_FORCED_LEVEL_MANUAL &&
 826                                  level != AMD_DPM_FORCED_LEVEL_MANUAL)
 827                                 amdgpu_gfx_off_ctrl(adev, true);
 828                 }
 829         }
 830
 831         if (!(current_level & profile_mode_mask) &&
 832             (level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT))
 833                 return -EINVAL;
 834
 835         if (!(current_level & profile_mode_mask) &&
 836               (level & profile_mode_mask)) {
 837                 /* enter UMD Pstate */
 838                 amdgpu_device_ip_set_powergating_state(adev,
 839                                                        AMD_IP_BLOCK_TYPE_GFX,
 840                                                        AMD_PG_STATE_UNGATE);
 841                 amdgpu_device_ip_set_clockgating_state(adev,
 842                                                        AMD_IP_BLOCK_TYPE_GFX,
 843                                                        AMD_CG_STATE_UNGATE);
 844         } else if ((current_level & profile_mode_mask) &&
 845                     !(level & profile_mode_mask)) {
 846                 /* exit UMD Pstate */
 847                 amdgpu_device_ip_set_clockgating_state(adev,
 848                                                        AMD_IP_BLOCK_TYPE_GFX,
 849                                                        AMD_CG_STATE_GATE);
 850                 amdgpu_device_ip_set_powergating_state(adev,
 851                                                        AMD_IP_BLOCK_TYPE_GFX,
 852                                                        AMD_PG_STATE_GATE);
 853         }
 854
 855         mutex_lock(&adev->pm.mutex);
 856
 857         if (pp_funcs->force_performance_level(adev->powerplay.pp_handle,
 858                                               level)) {
 859                 mutex_unlock(&adev->pm.mutex);
 860                 return -EINVAL;
 861         }
 862
 863         adev->pm.dpm.forced_level = level;
 864
 865         mutex_unlock(&adev->pm.mutex);
 866
 867         return 0;
 868 }
 869
 870 int amdgpu_dpm_get_pp_num_states(struct amdgpu_device *adev,
 871                                  struct pp_states_info *states)
 872 {
 873         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 874         int ret = 0;
 875
 876         if (!pp_funcs->get_pp_num_states)
 877                 return -EOPNOTSUPP;
 878
 879         mutex_lock(&adev->pm.mutex);
 880         ret = pp_funcs->get_pp_num_states(adev->powerplay.pp_handle,
 881                                           states);
 882         mutex_unlock(&adev->pm.mutex);
 883
 884         return ret;
 885 }
 886
 887 int amdgpu_dpm_dispatch_task(struct amdgpu_device *adev,
 888                               enum amd_pp_task task_id,
 889                               enum amd_pm_state_type *user_state)
 890 {
 891         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 892         int ret = 0;
 893
 894         if (!pp_funcs->dispatch_tasks)
 895                 return -EOPNOTSUPP;
 896
 897         mutex_lock(&adev->pm.mutex);
 898         ret = pp_funcs->dispatch_tasks(adev->powerplay.pp_handle,
 899                                        task_id,
 900                                        user_state);
 901         mutex_unlock(&adev->pm.mutex);
 902
 903         return ret;
 904 }
 905
 906 int amdgpu_dpm_get_pp_table(struct amdgpu_device *adev, char **table)
 907 {
 908         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 909         int ret = 0;
 910
 911         if (!pp_funcs->get_pp_table)
 912                 return 0;
 913
 914         mutex_lock(&adev->pm.mutex);
 915         ret = pp_funcs->get_pp_table(adev->powerplay.pp_handle,
 916                                      table);
 917         mutex_unlock(&adev->pm.mutex);
 918
 919         return ret;
 920 }
 921
 922 int amdgpu_dpm_set_fine_grain_clk_vol(struct amdgpu_device *adev,
 923                                       uint32_t type,
 924                                       long *input,
 925                                       uint32_t size)
 926 {
 927         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 928         int ret = 0;
 929
 930         if (!pp_funcs->set_fine_grain_clk_vol)
 931                 return 0;
 932
 933         mutex_lock(&adev->pm.mutex);
 934         ret = pp_funcs->set_fine_grain_clk_vol(adev->powerplay.pp_handle,
 935                                                type,
 936                                                input,
 937                                                size);
 938         mutex_unlock(&adev->pm.mutex);
 939
 940         return ret;
 941 }
 942
 943 int amdgpu_dpm_odn_edit_dpm_table(struct amdgpu_device *adev,
 944                                   uint32_t type,
 945                                   long *input,
 946                                   uint32_t size)
 947 {
 948         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 949         int ret = 0;
 950
 951         if (!pp_funcs->odn_edit_dpm_table)
 952                 return 0;
 953
 954         mutex_lock(&adev->pm.mutex);
 955         ret = pp_funcs->odn_edit_dpm_table(adev->powerplay.pp_handle,
 956                                            type,
 957                                            input,
 958                                            size);
 959         mutex_unlock(&adev->pm.mutex);
 960
 961         return ret;
 962 }
 963
 964 int amdgpu_dpm_print_clock_levels(struct amdgpu_device *adev,
 965                                   enum pp_clock_type type,
 966                                   char *buf)
 967 {
 968         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 969         int ret = 0;
 970
 971         if (!pp_funcs->print_clock_levels)
 972                 return 0;
 973
 974         mutex_lock(&adev->pm.mutex);
 975         ret = pp_funcs->print_clock_levels(adev->powerplay.pp_handle,
 976                                            type,
 977                                            buf);
 978         mutex_unlock(&adev->pm.mutex);
 979
 980         return ret;
 981 }
 982
 983 int amdgpu_dpm_emit_clock_levels(struct amdgpu_device *adev,
 984                                   enum pp_clock_type type,
 985                                   char *buf,
 986                                   int *offset)
 987 {
 988         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 989         int ret = 0;
 990
 991         if (!pp_funcs->emit_clock_levels)
 992                 return -ENOENT;
 993
 994         mutex_lock(&adev->pm.mutex);
 995         ret = pp_funcs->emit_clock_levels(adev->powerplay.pp_handle,
 996                                            type,
 997                                            buf,
 998                                            offset);
 999         mutex_unlock(&adev->pm.mutex);
1000
1001         return ret;
1002 }
1003
1004 int amdgpu_dpm_set_ppfeature_status(struct amdgpu_device *adev,
1005                                     uint64_t ppfeature_masks)
1006 {
1007         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1008         int ret = 0;
1009
1010         if (!pp_funcs->set_ppfeature_status)
1011                 return 0;
1012
1013         mutex_lock(&adev->pm.mutex);
1014         ret = pp_funcs->set_ppfeature_status(adev->powerplay.pp_handle,
1015                                              ppfeature_masks);
1016         mutex_unlock(&adev->pm.mutex);
1017
1018         return ret;
1019 }
1020
1021 int amdgpu_dpm_get_ppfeature_status(struct amdgpu_device *adev, char *buf)
1022 {
1023         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1024         int ret = 0;
1025
1026         if (!pp_funcs->get_ppfeature_status)
1027                 return 0;
1028
1029         mutex_lock(&adev->pm.mutex);
1030         ret = pp_funcs->get_ppfeature_status(adev->powerplay.pp_handle,
1031                                              buf);
1032         mutex_unlock(&adev->pm.mutex);
1033
1034         return ret;
1035 }
1036
1037 int amdgpu_dpm_force_clock_level(struct amdgpu_device *adev,
1038                                  enum pp_clock_type type,
1039                                  uint32_t mask)
1040 {
1041         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1042         int ret = 0;
1043
1044         if (!pp_funcs->force_clock_level)
1045                 return 0;
1046
1047         mutex_lock(&adev->pm.mutex);
1048         ret = pp_funcs->force_clock_level(adev->powerplay.pp_handle,
1049                                           type,
1050                                           mask);
1051         mutex_unlock(&adev->pm.mutex);
1052
1053         return ret;
1054 }
1055
1056 int amdgpu_dpm_get_sclk_od(struct amdgpu_device *adev)
1057 {
1058         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1059         int ret = 0;
1060
1061         if (!pp_funcs->get_sclk_od)
1062                 return 0;
1063
1064         mutex_lock(&adev->pm.mutex);
1065         ret = pp_funcs->get_sclk_od(adev->powerplay.pp_handle);
1066         mutex_unlock(&adev->pm.mutex);
1067
1068         return ret;
1069 }
1070
1071 int amdgpu_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value)
1072 {
1073         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1074
1075         if (is_support_sw_smu(adev))
1076                 return 0;
1077
1078         mutex_lock(&adev->pm.mutex);
1079         if (pp_funcs->set_sclk_od)
1080                 pp_funcs->set_sclk_od(adev->powerplay.pp_handle, value);
1081         mutex_unlock(&adev->pm.mutex);
1082
1083         if (amdgpu_dpm_dispatch_task(adev,
1084                                      AMD_PP_TASK_READJUST_POWER_STATE,
1085                                      NULL) == -EOPNOTSUPP) {
1086                 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
1087                 amdgpu_dpm_compute_clocks(adev);
1088         }
1089
1090         return 0;
1091 }
1092
1093 int amdgpu_dpm_get_mclk_od(struct amdgpu_device *adev)
1094 {
1095         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1096         int ret = 0;
1097
1098         if (!pp_funcs->get_mclk_od)
1099                 return 0;
1100
1101         mutex_lock(&adev->pm.mutex);
1102         ret = pp_funcs->get_mclk_od(adev->powerplay.pp_handle);
1103         mutex_unlock(&adev->pm.mutex);
1104
1105         return ret;
1106 }
1107
1108 int amdgpu_dpm_set_mclk_od(struct amdgpu_device *adev, uint32_t value)
1109 {
1110         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1111
1112         if (is_support_sw_smu(adev))
1113                 return 0;
1114
1115         mutex_lock(&adev->pm.mutex);
1116         if (pp_funcs->set_mclk_od)
1117                 pp_funcs->set_mclk_od(adev->powerplay.pp_handle, value);
1118         mutex_unlock(&adev->pm.mutex);
1119
1120         if (amdgpu_dpm_dispatch_task(adev,
1121                                      AMD_PP_TASK_READJUST_POWER_STATE,
1122                                      NULL) == -EOPNOTSUPP) {
1123                 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
1124                 amdgpu_dpm_compute_clocks(adev);
1125         }
1126
1127         return 0;
1128 }
1129
1130 int amdgpu_dpm_get_power_profile_mode(struct amdgpu_device *adev,
1131                                       char *buf)
1132 {
1133         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1134         int ret = 0;
1135
1136         if (!pp_funcs->get_power_profile_mode)
1137                 return -EOPNOTSUPP;
1138
1139         mutex_lock(&adev->pm.mutex);
1140         ret = pp_funcs->get_power_profile_mode(adev->powerplay.pp_handle,
1141                                                buf);
1142         mutex_unlock(&adev->pm.mutex);
1143
1144         return ret;
1145 }
1146
1147 int amdgpu_dpm_set_power_profile_mode(struct amdgpu_device *adev,
1148                                       long *input, uint32_t size)
1149 {
1150         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1151         int ret = 0;
1152
1153         if (!pp_funcs->set_power_profile_mode)
1154                 return 0;
1155
1156         mutex_lock(&adev->pm.mutex);
1157         ret = pp_funcs->set_power_profile_mode(adev->powerplay.pp_handle,
1158                                                input,
1159                                                size);
1160         mutex_unlock(&adev->pm.mutex);
1161
1162         return ret;
1163 }
1164
1165 int amdgpu_dpm_get_gpu_metrics(struct amdgpu_device *adev, void **table)
1166 {
1167         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1168         int ret = 0;
1169
1170         if (!pp_funcs->get_gpu_metrics)
1171                 return 0;
1172
1173         mutex_lock(&adev->pm.mutex);
1174         ret = pp_funcs->get_gpu_metrics(adev->powerplay.pp_handle,
1175                                         table);
1176         mutex_unlock(&adev->pm.mutex);
1177
1178         return ret;
1179 }
1180
1181 int amdgpu_dpm_get_fan_control_mode(struct amdgpu_device *adev,
1182                                     uint32_t *fan_mode)
1183 {
1184         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1185         int ret = 0;
1186
1187         if (!pp_funcs->get_fan_control_mode)
1188                 return -EOPNOTSUPP;
1189
1190         mutex_lock(&adev->pm.mutex);
1191         ret = pp_funcs->get_fan_control_mode(adev->powerplay.pp_handle,
1192                                              fan_mode);
1193         mutex_unlock(&adev->pm.mutex);
1194
1195         return ret;
1196 }
1197
1198 int amdgpu_dpm_set_fan_speed_pwm(struct amdgpu_device *adev,
1199                                  uint32_t speed)
1200 {
1201         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1202         int ret = 0;
1203
1204         if (!pp_funcs->set_fan_speed_pwm)
1205                 return -EOPNOTSUPP;
1206
1207         mutex_lock(&adev->pm.mutex);
1208         ret = pp_funcs->set_fan_speed_pwm(adev->powerplay.pp_handle,
1209                                           speed);
1210         mutex_unlock(&adev->pm.mutex);
1211
1212         return ret;
1213 }
1214
1215 int amdgpu_dpm_get_fan_speed_pwm(struct amdgpu_device *adev,
1216                                  uint32_t *speed)
1217 {
1218         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1219         int ret = 0;
1220
1221         if (!pp_funcs->get_fan_speed_pwm)
1222                 return -EOPNOTSUPP;
1223
1224         mutex_lock(&adev->pm.mutex);
1225         ret = pp_funcs->get_fan_speed_pwm(adev->powerplay.pp_handle,
1226                                           speed);
1227         mutex_unlock(&adev->pm.mutex);
1228
1229         return ret;
1230 }
1231
1232 int amdgpu_dpm_get_fan_speed_rpm(struct amdgpu_device *adev,
1233                                  uint32_t *speed)
1234 {
1235         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1236         int ret = 0;
1237
1238         if (!pp_funcs->get_fan_speed_rpm)
1239                 return -EOPNOTSUPP;
1240
1241         mutex_lock(&adev->pm.mutex);
1242         ret = pp_funcs->get_fan_speed_rpm(adev->powerplay.pp_handle,
1243                                           speed);
1244         mutex_unlock(&adev->pm.mutex);
1245
1246         return ret;
1247 }
1248
1249 int amdgpu_dpm_set_fan_speed_rpm(struct amdgpu_device *adev,
1250                                  uint32_t speed)
1251 {
1252         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1253         int ret = 0;
1254
1255         if (!pp_funcs->set_fan_speed_rpm)
1256                 return -EOPNOTSUPP;
1257
1258         mutex_lock(&adev->pm.mutex);
1259         ret = pp_funcs->set_fan_speed_rpm(adev->powerplay.pp_handle,
1260                                           speed);
1261         mutex_unlock(&adev->pm.mutex);
1262
1263         return ret;
1264 }
1265
1266 int amdgpu_dpm_set_fan_control_mode(struct amdgpu_device *adev,
1267                                     uint32_t mode)
1268 {
1269         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1270         int ret = 0;
1271
1272         if (!pp_funcs->set_fan_control_mode)
1273                 return -EOPNOTSUPP;
1274
1275         mutex_lock(&adev->pm.mutex);
1276         ret = pp_funcs->set_fan_control_mode(adev->powerplay.pp_handle,
1277                                              mode);
1278         mutex_unlock(&adev->pm.mutex);
1279
1280         return ret;
1281 }
1282
1283 int amdgpu_dpm_get_power_limit(struct amdgpu_device *adev,
1284                                uint32_t *limit,
1285                                enum pp_power_limit_level pp_limit_level,
1286                                enum pp_power_type power_type)
1287 {
1288         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1289         int ret = 0;
1290
1291         if (!pp_funcs->get_power_limit)
1292                 return -ENODATA;
1293
1294         mutex_lock(&adev->pm.mutex);
1295         ret = pp_funcs->get_power_limit(adev->powerplay.pp_handle,
1296                                         limit,
1297                                         pp_limit_level,
1298                                         power_type);
1299         mutex_unlock(&adev->pm.mutex);
1300
1301         return ret;
1302 }
1303
1304 int amdgpu_dpm_set_power_limit(struct amdgpu_device *adev,
1305                                uint32_t limit)
1306 {
1307         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1308         int ret = 0;
1309
1310         if (!pp_funcs->set_power_limit)
1311                 return -EINVAL;
1312
1313         mutex_lock(&adev->pm.mutex);
1314         ret = pp_funcs->set_power_limit(adev->powerplay.pp_handle,
1315                                         limit);
1316         mutex_unlock(&adev->pm.mutex);
1317
1318         return ret;
1319 }
1320
1321 int amdgpu_dpm_is_cclk_dpm_supported(struct amdgpu_device *adev)
1322 {
1323         bool cclk_dpm_supported = false;
1324
1325         if (!is_support_sw_smu(adev))
1326                 return false;
1327
1328         mutex_lock(&adev->pm.mutex);
1329         cclk_dpm_supported = is_support_cclk_dpm(adev);
1330         mutex_unlock(&adev->pm.mutex);
1331
1332         return (int)cclk_dpm_supported;
1333 }
1334
1335 int amdgpu_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
1336                                                        struct seq_file *m)
1337 {
1338         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1339
1340         if (!pp_funcs->debugfs_print_current_performance_level)
1341                 return -EOPNOTSUPP;
1342
1343         mutex_lock(&adev->pm.mutex);
1344         pp_funcs->debugfs_print_current_performance_level(adev->powerplay.pp_handle,
1345                                                           m);
1346         mutex_unlock(&adev->pm.mutex);
1347
1348         return 0;
1349 }
1350
1351 int amdgpu_dpm_get_smu_prv_buf_details(struct amdgpu_device *adev,
1352                                        void **addr,
1353                                        size_t *size)
1354 {
1355         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1356         int ret = 0;
1357
1358         if (!pp_funcs->get_smu_prv_buf_details)
1359                 return -ENOSYS;
1360
1361         mutex_lock(&adev->pm.mutex);
1362         ret = pp_funcs->get_smu_prv_buf_details(adev->powerplay.pp_handle,
1363                                                 addr,
1364                                                 size);
1365         mutex_unlock(&adev->pm.mutex);
1366
1367         return ret;
1368 }
1369
1370 int amdgpu_dpm_is_overdrive_supported(struct amdgpu_device *adev)
1371 {
1372         struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
1373         struct smu_context *smu = adev->powerplay.pp_handle;
1374
1375         if ((is_support_sw_smu(adev) && smu->od_enabled) ||
1376             (is_support_sw_smu(adev) && smu->is_apu) ||
1377                 (!is_support_sw_smu(adev) && hwmgr->od_enabled))
1378                 return true;
1379
1380         return false;
1381 }
1382
1383 int amdgpu_dpm_set_pp_table(struct amdgpu_device *adev,
1384                             const char *buf,
1385                             size_t size)
1386 {
1387         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1388         int ret = 0;
1389
1390         if (!pp_funcs->set_pp_table)
1391                 return -EOPNOTSUPP;
1392
1393         mutex_lock(&adev->pm.mutex);
1394         ret = pp_funcs->set_pp_table(adev->powerplay.pp_handle,
1395                                      buf,
1396                                      size);
1397         mutex_unlock(&adev->pm.mutex);
1398
1399         return ret;
1400 }
1401
1402 int amdgpu_dpm_get_num_cpu_cores(struct amdgpu_device *adev)
1403 {
1404         struct smu_context *smu = adev->powerplay.pp_handle;
1405
1406         if (!is_support_sw_smu(adev))
1407                 return INT_MAX;
1408
1409         return smu->cpu_core_num;
1410 }
1411
1412 void amdgpu_dpm_stb_debug_fs_init(struct amdgpu_device *adev)
1413 {
1414         if (!is_support_sw_smu(adev))
1415                 return;
1416
1417         amdgpu_smu_stb_debug_fs_init(adev);
1418 }
1419
1420 int amdgpu_dpm_display_configuration_change(struct amdgpu_device *adev,
1421                                             const struct amd_pp_display_configuration *input)
1422 {
1423         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1424         int ret = 0;
1425
1426         if (!pp_funcs->display_configuration_change)
1427                 return 0;
1428
1429         mutex_lock(&adev->pm.mutex);
1430         ret = pp_funcs->display_configuration_change(adev->powerplay.pp_handle,
1431                                                      input);
1432         mutex_unlock(&adev->pm.mutex);
1433
1434         return ret;
1435 }
1436
1437 int amdgpu_dpm_get_clock_by_type(struct amdgpu_device *adev,
1438                                  enum amd_pp_clock_type type,
1439                                  struct amd_pp_clocks *clocks)
1440 {
1441         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1442         int ret = 0;
1443
1444         if (!pp_funcs->get_clock_by_type)
1445                 return 0;
1446
1447         mutex_lock(&adev->pm.mutex);
1448         ret = pp_funcs->get_clock_by_type(adev->powerplay.pp_handle,
1449                                           type,
1450                                           clocks);
1451         mutex_unlock(&adev->pm.mutex);
1452
1453         return ret;
1454 }
1455
1456 int amdgpu_dpm_get_display_mode_validation_clks(struct amdgpu_device *adev,
1457                                                 struct amd_pp_simple_clock_info *clocks)
1458 {
1459         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1460         int ret = 0;
1461
1462         if (!pp_funcs->get_display_mode_validation_clocks)
1463                 return 0;
1464
1465         mutex_lock(&adev->pm.mutex);
1466         ret = pp_funcs->get_display_mode_validation_clocks(adev->powerplay.pp_handle,
1467                                                            clocks);
1468         mutex_unlock(&adev->pm.mutex);
1469
1470         return ret;
1471 }
1472
1473 int amdgpu_dpm_get_clock_by_type_with_latency(struct amdgpu_device *adev,
1474                                               enum amd_pp_clock_type type,
1475                                               struct pp_clock_levels_with_latency *clocks)
1476 {
1477         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1478         int ret = 0;
1479
1480         if (!pp_funcs->get_clock_by_type_with_latency)
1481                 return 0;
1482
1483         mutex_lock(&adev->pm.mutex);
1484         ret = pp_funcs->get_clock_by_type_with_latency(adev->powerplay.pp_handle,
1485                                                        type,
1486                                                        clocks);
1487         mutex_unlock(&adev->pm.mutex);
1488
1489         return ret;
1490 }
1491
1492 int amdgpu_dpm_get_clock_by_type_with_voltage(struct amdgpu_device *adev,
1493                                               enum amd_pp_clock_type type,
1494                                               struct pp_clock_levels_with_voltage *clocks)
1495 {
1496         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1497         int ret = 0;
1498
1499         if (!pp_funcs->get_clock_by_type_with_voltage)
1500                 return 0;
1501
1502         mutex_lock(&adev->pm.mutex);
1503         ret = pp_funcs->get_clock_by_type_with_voltage(adev->powerplay.pp_handle,
1504                                                        type,
1505                                                        clocks);
1506         mutex_unlock(&adev->pm.mutex);
1507
1508         return ret;
1509 }
1510
1511 int amdgpu_dpm_set_watermarks_for_clocks_ranges(struct amdgpu_device *adev,
1512                                                void *clock_ranges)
1513 {
1514         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1515         int ret = 0;
1516
1517         if (!pp_funcs->set_watermarks_for_clocks_ranges)
1518                 return -EOPNOTSUPP;
1519
1520         mutex_lock(&adev->pm.mutex);
1521         ret = pp_funcs->set_watermarks_for_clocks_ranges(adev->powerplay.pp_handle,
1522                                                          clock_ranges);
1523         mutex_unlock(&adev->pm.mutex);
1524
1525         return ret;
1526 }
1527
1528 int amdgpu_dpm_display_clock_voltage_request(struct amdgpu_device *adev,
1529                                              struct pp_display_clock_request *clock)
1530 {
1531         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1532         int ret = 0;
1533
1534         if (!pp_funcs->display_clock_voltage_request)
1535                 return -EOPNOTSUPP;
1536
1537         mutex_lock(&adev->pm.mutex);
1538         ret = pp_funcs->display_clock_voltage_request(adev->powerplay.pp_handle,
1539                                                       clock);
1540         mutex_unlock(&adev->pm.mutex);
1541
1542         return ret;
1543 }
1544
1545 int amdgpu_dpm_get_current_clocks(struct amdgpu_device *adev,
1546                                   struct amd_pp_clock_info *clocks)
1547 {
1548         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1549         int ret = 0;
1550
1551         if (!pp_funcs->get_current_clocks)
1552                 return -EOPNOTSUPP;
1553
1554         mutex_lock(&adev->pm.mutex);
1555         ret = pp_funcs->get_current_clocks(adev->powerplay.pp_handle,
1556                                            clocks);
1557         mutex_unlock(&adev->pm.mutex);
1558
1559         return ret;
1560 }
1561
1562 void amdgpu_dpm_notify_smu_enable_pwe(struct amdgpu_device *adev)
1563 {
1564         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1565
1566         if (!pp_funcs->notify_smu_enable_pwe)
1567                 return;
1568
1569         mutex_lock(&adev->pm.mutex);
1570         pp_funcs->notify_smu_enable_pwe(adev->powerplay.pp_handle);
1571         mutex_unlock(&adev->pm.mutex);
1572 }
1573
1574 int amdgpu_dpm_set_active_display_count(struct amdgpu_device *adev,
1575                                         uint32_t count)
1576 {
1577         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1578         int ret = 0;
1579
1580         if (!pp_funcs->set_active_display_count)
1581                 return -EOPNOTSUPP;
1582
1583         mutex_lock(&adev->pm.mutex);
1584         ret = pp_funcs->set_active_display_count(adev->powerplay.pp_handle,
1585                                                  count);
1586         mutex_unlock(&adev->pm.mutex);
1587
1588         return ret;
1589 }
1590
1591 int amdgpu_dpm_set_min_deep_sleep_dcefclk(struct amdgpu_device *adev,
1592                                           uint32_t clock)
1593 {
1594         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1595         int ret = 0;
1596
1597         if (!pp_funcs->set_min_deep_sleep_dcefclk)
1598                 return -EOPNOTSUPP;
1599
1600         mutex_lock(&adev->pm.mutex);
1601         ret = pp_funcs->set_min_deep_sleep_dcefclk(adev->powerplay.pp_handle,
1602                                                    clock);
1603         mutex_unlock(&adev->pm.mutex);
1604
1605         return ret;
1606 }
1607
1608 void amdgpu_dpm_set_hard_min_dcefclk_by_freq(struct amdgpu_device *adev,
1609                                              uint32_t clock)
1610 {
1611         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1612
1613         if (!pp_funcs->set_hard_min_dcefclk_by_freq)
1614                 return;
1615
1616         mutex_lock(&adev->pm.mutex);
1617         pp_funcs->set_hard_min_dcefclk_by_freq(adev->powerplay.pp_handle,
1618                                                clock);
1619         mutex_unlock(&adev->pm.mutex);
1620 }
1621
1622 void amdgpu_dpm_set_hard_min_fclk_by_freq(struct amdgpu_device *adev,
1623                                           uint32_t clock)
1624 {
1625         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1626
1627         if (!pp_funcs->set_hard_min_fclk_by_freq)
1628                 return;
1629
1630         mutex_lock(&adev->pm.mutex);
1631         pp_funcs->set_hard_min_fclk_by_freq(adev->powerplay.pp_handle,
1632                                             clock);
1633         mutex_unlock(&adev->pm.mutex);
1634 }
1635
1636 int amdgpu_dpm_display_disable_memory_clock_switch(struct amdgpu_device *adev,
1637                                                    bool disable_memory_clock_switch)
1638 {
1639         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1640         int ret = 0;
1641
1642         if (!pp_funcs->display_disable_memory_clock_switch)
1643                 return 0;
1644
1645         mutex_lock(&adev->pm.mutex);
1646         ret = pp_funcs->display_disable_memory_clock_switch(adev->powerplay.pp_handle,
1647                                                             disable_memory_clock_switch);
1648         mutex_unlock(&adev->pm.mutex);
1649
1650         return ret;
1651 }
1652
1653 int amdgpu_dpm_get_max_sustainable_clocks_by_dc(struct amdgpu_device *adev,
1654                                                 struct pp_smu_nv_clock_table *max_clocks)
1655 {
1656         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1657         int ret = 0;
1658
1659         if (!pp_funcs->get_max_sustainable_clocks_by_dc)
1660                 return -EOPNOTSUPP;
1661
1662         mutex_lock(&adev->pm.mutex);
1663         ret = pp_funcs->get_max_sustainable_clocks_by_dc(adev->powerplay.pp_handle,
1664                                                          max_clocks);
1665         mutex_unlock(&adev->pm.mutex);
1666
1667         return ret;
1668 }
1669
1670 enum pp_smu_status amdgpu_dpm_get_uclk_dpm_states(struct amdgpu_device *adev,
1671                                                   unsigned int *clock_values_in_khz,
1672                                                   unsigned int *num_states)
1673 {
1674         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1675         int ret = 0;
1676
1677         if (!pp_funcs->get_uclk_dpm_states)
1678                 return -EOPNOTSUPP;
1679
1680         mutex_lock(&adev->pm.mutex);
1681         ret = pp_funcs->get_uclk_dpm_states(adev->powerplay.pp_handle,
1682                                             clock_values_in_khz,
1683                                             num_states);
1684         mutex_unlock(&adev->pm.mutex);
1685
1686         return ret;
1687 }
1688
1689 int amdgpu_dpm_get_dpm_clock_table(struct amdgpu_device *adev,
1690                                    struct dpm_clocks *clock_table)
1691 {
1692         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1693         int ret = 0;
1694
1695         if (!pp_funcs->get_dpm_clock_table)
1696                 return -EOPNOTSUPP;
1697
1698         mutex_lock(&adev->pm.mutex);
1699         ret = pp_funcs->get_dpm_clock_table(adev->powerplay.pp_handle,
1700                                             clock_table);
1701         mutex_unlock(&adev->pm.mutex);
1702
1703         return ret;
1704 }