2 * Copyright 2012-2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
28 uint32_t sdmax_rlcx_rb_cntl;
29 uint32_t sdmax_rlcx_rb_base;
30 uint32_t sdmax_rlcx_rb_base_hi;
31 uint32_t sdmax_rlcx_rb_rptr;
32 uint32_t sdmax_rlcx_rb_rptr_hi;
33 uint32_t sdmax_rlcx_rb_wptr;
34 uint32_t sdmax_rlcx_rb_wptr_hi;
35 uint32_t sdmax_rlcx_rb_wptr_poll_cntl;
36 uint32_t sdmax_rlcx_rb_rptr_addr_hi;
37 uint32_t sdmax_rlcx_rb_rptr_addr_lo;
38 uint32_t sdmax_rlcx_ib_cntl;
39 uint32_t sdmax_rlcx_ib_rptr;
40 uint32_t sdmax_rlcx_ib_offset;
41 uint32_t sdmax_rlcx_ib_base_lo;
42 uint32_t sdmax_rlcx_ib_base_hi;
43 uint32_t sdmax_rlcx_ib_size;
44 uint32_t sdmax_rlcx_skip_cntl;
45 uint32_t sdmax_rlcx_context_status;
46 uint32_t sdmax_rlcx_doorbell;
47 uint32_t sdmax_rlcx_status;
48 uint32_t sdmax_rlcx_doorbell_log;
49 uint32_t sdmax_rlcx_watermark;
50 uint32_t sdmax_rlcx_doorbell_offset;
51 uint32_t sdmax_rlcx_csa_addr_lo;
52 uint32_t sdmax_rlcx_csa_addr_hi;
53 uint32_t sdmax_rlcx_ib_sub_remain;
54 uint32_t sdmax_rlcx_preempt;
55 uint32_t sdmax_rlcx_dummy_reg;
56 uint32_t sdmax_rlcx_rb_wptr_poll_addr_hi;
57 uint32_t sdmax_rlcx_rb_wptr_poll_addr_lo;
58 uint32_t sdmax_rlcx_rb_aql_cntl;
59 uint32_t sdmax_rlcx_minor_ptr_update;
60 uint32_t sdmax_rlcx_midcmd_data0;
61 uint32_t sdmax_rlcx_midcmd_data1;
62 uint32_t sdmax_rlcx_midcmd_data2;
63 uint32_t sdmax_rlcx_midcmd_data3;
64 uint32_t sdmax_rlcx_midcmd_data4;
65 uint32_t sdmax_rlcx_midcmd_data5;
66 uint32_t sdmax_rlcx_midcmd_data6;
67 uint32_t sdmax_rlcx_midcmd_data7;
68 uint32_t sdmax_rlcx_midcmd_data8;
69 uint32_t sdmax_rlcx_midcmd_cntl;
100 uint32_t reserved_72;
101 uint32_t reserved_73;
102 uint32_t reserved_74;
103 uint32_t reserved_75;
104 uint32_t reserved_76;
105 uint32_t reserved_77;
106 uint32_t reserved_78;
107 uint32_t reserved_79;
108 uint32_t reserved_80;
109 uint32_t reserved_81;
110 uint32_t reserved_82;
111 uint32_t reserved_83;
112 uint32_t reserved_84;
113 uint32_t reserved_85;
114 uint32_t reserved_86;
115 uint32_t reserved_87;
116 uint32_t reserved_88;
117 uint32_t reserved_89;
118 uint32_t reserved_90;
119 uint32_t reserved_91;
120 uint32_t reserved_92;
121 uint32_t reserved_93;
122 uint32_t reserved_94;
123 uint32_t reserved_95;
124 uint32_t reserved_96;
125 uint32_t reserved_97;
126 uint32_t reserved_98;
127 uint32_t reserved_99;
128 uint32_t reserved_100;
129 uint32_t reserved_101;
130 uint32_t reserved_102;
131 uint32_t reserved_103;
132 uint32_t reserved_104;
133 uint32_t reserved_105;
134 uint32_t reserved_106;
135 uint32_t reserved_107;
136 uint32_t reserved_108;
137 uint32_t reserved_109;
138 uint32_t reserved_110;
139 uint32_t reserved_111;
140 uint32_t reserved_112;
141 uint32_t reserved_113;
142 uint32_t reserved_114;
143 uint32_t reserved_115;
144 uint32_t reserved_116;
145 uint32_t reserved_117;
146 uint32_t reserved_118;
147 uint32_t reserved_119;
148 uint32_t reserved_120;
149 uint32_t reserved_121;
150 uint32_t reserved_122;
151 uint32_t reserved_123;
152 uint32_t reserved_124;
153 uint32_t reserved_125;
154 /* reserved_126,127: repurposed for driver-internal use */
155 uint32_t sdma_engine_id;
156 uint32_t sdma_queue_id;
161 uint32_t compute_dispatch_initiator;
162 uint32_t compute_dim_x;
163 uint32_t compute_dim_y;
164 uint32_t compute_dim_z;
165 uint32_t compute_start_x;
166 uint32_t compute_start_y;
167 uint32_t compute_start_z;
168 uint32_t compute_num_thread_x;
169 uint32_t compute_num_thread_y;
170 uint32_t compute_num_thread_z;
171 uint32_t compute_pipelinestat_enable;
172 uint32_t compute_perfcount_enable;
173 uint32_t compute_pgm_lo;
174 uint32_t compute_pgm_hi;
175 uint32_t compute_tba_lo;
176 uint32_t compute_tba_hi;
177 uint32_t compute_tma_lo;
178 uint32_t compute_tma_hi;
179 uint32_t compute_pgm_rsrc1;
180 uint32_t compute_pgm_rsrc2;
181 uint32_t compute_vmid;
182 uint32_t compute_resource_limits;
183 uint32_t compute_static_thread_mgmt_se0;
184 uint32_t compute_static_thread_mgmt_se1;
185 uint32_t compute_tmpring_size;
186 uint32_t compute_static_thread_mgmt_se2;
187 uint32_t compute_static_thread_mgmt_se3;
188 uint32_t compute_restart_x;
189 uint32_t compute_restart_y;
190 uint32_t compute_restart_z;
191 uint32_t compute_thread_trace_enable;
192 uint32_t compute_misc_reserved;
193 uint32_t compute_dispatch_id;
194 uint32_t compute_threadgroup_id;
195 uint32_t compute_relaunch;
196 uint32_t compute_wave_restore_addr_lo;
197 uint32_t compute_wave_restore_addr_hi;
198 uint32_t compute_wave_restore_control;
199 uint32_t compute_static_thread_mgmt_se4;
200 uint32_t compute_static_thread_mgmt_se5;
201 uint32_t compute_static_thread_mgmt_se6;
202 uint32_t compute_static_thread_mgmt_se7;
203 uint32_t reserved_43;
204 uint32_t reserved_44;
205 uint32_t reserved_45;
206 uint32_t reserved_46;
207 uint32_t reserved_47;
208 uint32_t reserved_48;
209 uint32_t reserved_49;
210 uint32_t reserved_50;
211 uint32_t reserved_51;
212 uint32_t reserved_52;
213 uint32_t reserved_53;
214 uint32_t reserved_54;
215 uint32_t reserved_55;
216 uint32_t reserved_56;
217 uint32_t reserved_57;
218 uint32_t reserved_58;
219 uint32_t reserved_59;
220 uint32_t reserved_60;
221 uint32_t reserved_61;
222 uint32_t reserved_62;
223 uint32_t reserved_63;
224 uint32_t reserved_64;
225 uint32_t compute_user_data_0;
226 uint32_t compute_user_data_1;
227 uint32_t compute_user_data_2;
228 uint32_t compute_user_data_3;
229 uint32_t compute_user_data_4;
230 uint32_t compute_user_data_5;
231 uint32_t compute_user_data_6;
232 uint32_t compute_user_data_7;
233 uint32_t compute_user_data_8;
234 uint32_t compute_user_data_9;
235 uint32_t compute_user_data_10;
236 uint32_t compute_user_data_11;
237 uint32_t compute_user_data_12;
238 uint32_t compute_user_data_13;
239 uint32_t compute_user_data_14;
240 uint32_t compute_user_data_15;
241 uint32_t cp_compute_csinvoc_count_lo;
242 uint32_t cp_compute_csinvoc_count_hi;
243 uint32_t reserved_83;
244 uint32_t reserved_84;
245 uint32_t reserved_85;
246 uint32_t cp_mqd_query_time_lo;
247 uint32_t cp_mqd_query_time_hi;
248 uint32_t cp_mqd_connect_start_time_lo;
249 uint32_t cp_mqd_connect_start_time_hi;
250 uint32_t cp_mqd_connect_end_time_lo;
251 uint32_t cp_mqd_connect_end_time_hi;
252 uint32_t cp_mqd_connect_end_wf_count;
253 uint32_t cp_mqd_connect_end_pq_rptr;
254 uint32_t cp_mqd_connect_end_pq_wptr;
255 uint32_t cp_mqd_connect_end_ib_rptr;
256 uint32_t cp_mqd_readindex_lo;
257 uint32_t cp_mqd_readindex_hi;
258 uint32_t cp_mqd_save_start_time_lo;
259 uint32_t cp_mqd_save_start_time_hi;
260 uint32_t cp_mqd_save_end_time_lo;
261 uint32_t cp_mqd_save_end_time_hi;
262 uint32_t cp_mqd_restore_start_time_lo;
263 uint32_t cp_mqd_restore_start_time_hi;
264 uint32_t cp_mqd_restore_end_time_lo;
265 uint32_t cp_mqd_restore_end_time_hi;
266 uint32_t disable_queue;
267 uint32_t reserved_107;
268 uint32_t gds_cs_ctxsw_cnt0;
269 uint32_t gds_cs_ctxsw_cnt1;
270 uint32_t gds_cs_ctxsw_cnt2;
271 uint32_t gds_cs_ctxsw_cnt3;
272 uint32_t reserved_112;
273 uint32_t reserved_113;
274 uint32_t cp_pq_exe_status_lo;
275 uint32_t cp_pq_exe_status_hi;
276 uint32_t cp_packet_id_lo;
277 uint32_t cp_packet_id_hi;
278 uint32_t cp_packet_exe_status_lo;
279 uint32_t cp_packet_exe_status_hi;
280 uint32_t gds_save_base_addr_lo;
281 uint32_t gds_save_base_addr_hi;
282 uint32_t gds_save_mask_lo;
283 uint32_t gds_save_mask_hi;
284 uint32_t ctx_save_base_addr_lo;
285 uint32_t ctx_save_base_addr_hi;
286 uint32_t dynamic_cu_mask_addr_lo;
287 uint32_t dynamic_cu_mask_addr_hi;
288 uint32_t cp_mqd_base_addr_lo;
289 uint32_t cp_mqd_base_addr_hi;
290 uint32_t cp_hqd_active;
291 uint32_t cp_hqd_vmid;
292 uint32_t cp_hqd_persistent_state;
293 uint32_t cp_hqd_pipe_priority;
294 uint32_t cp_hqd_queue_priority;
295 uint32_t cp_hqd_quantum;
296 uint32_t cp_hqd_pq_base_lo;
297 uint32_t cp_hqd_pq_base_hi;
298 uint32_t cp_hqd_pq_rptr;
299 uint32_t cp_hqd_pq_rptr_report_addr_lo;
300 uint32_t cp_hqd_pq_rptr_report_addr_hi;
301 uint32_t cp_hqd_pq_wptr_poll_addr_lo;
302 uint32_t cp_hqd_pq_wptr_poll_addr_hi;
303 uint32_t cp_hqd_pq_doorbell_control;
304 uint32_t reserved_144;
305 uint32_t cp_hqd_pq_control;
306 uint32_t cp_hqd_ib_base_addr_lo;
307 uint32_t cp_hqd_ib_base_addr_hi;
308 uint32_t cp_hqd_ib_rptr;
309 uint32_t cp_hqd_ib_control;
310 uint32_t cp_hqd_iq_timer;
311 uint32_t cp_hqd_iq_rptr;
312 uint32_t cp_hqd_dequeue_request;
313 uint32_t cp_hqd_dma_offload;
314 uint32_t cp_hqd_sema_cmd;
315 uint32_t cp_hqd_msg_type;
316 uint32_t cp_hqd_atomic0_preop_lo;
317 uint32_t cp_hqd_atomic0_preop_hi;
318 uint32_t cp_hqd_atomic1_preop_lo;
319 uint32_t cp_hqd_atomic1_preop_hi;
320 uint32_t cp_hqd_hq_status0;
321 uint32_t cp_hqd_hq_control0;
322 uint32_t cp_mqd_control;
323 uint32_t cp_hqd_hq_status1;
324 uint32_t cp_hqd_hq_control1;
325 uint32_t cp_hqd_eop_base_addr_lo;
326 uint32_t cp_hqd_eop_base_addr_hi;
327 uint32_t cp_hqd_eop_control;
328 uint32_t cp_hqd_eop_rptr;
329 uint32_t cp_hqd_eop_wptr;
330 uint32_t cp_hqd_eop_done_events;
331 uint32_t cp_hqd_ctx_save_base_addr_lo;
332 uint32_t cp_hqd_ctx_save_base_addr_hi;
333 uint32_t cp_hqd_ctx_save_control;
334 uint32_t cp_hqd_cntl_stack_offset;
335 uint32_t cp_hqd_cntl_stack_size;
336 uint32_t cp_hqd_wg_state_offset;
337 uint32_t cp_hqd_ctx_save_size;
338 uint32_t cp_hqd_gds_resource_state;
339 uint32_t cp_hqd_error;
340 uint32_t cp_hqd_eop_wptr_mem;
341 uint32_t cp_hqd_aql_control;
342 uint32_t cp_hqd_pq_wptr_lo;
343 uint32_t cp_hqd_pq_wptr_hi;
344 uint32_t reserved_184;
345 uint32_t reserved_185;
346 uint32_t reserved_186;
347 uint32_t reserved_187;
348 uint32_t reserved_188;
349 uint32_t reserved_189;
350 uint32_t reserved_190;
351 uint32_t reserved_191;
352 uint32_t iqtimer_pkt_header;
353 uint32_t iqtimer_pkt_dw0;
354 uint32_t iqtimer_pkt_dw1;
355 uint32_t iqtimer_pkt_dw2;
356 uint32_t iqtimer_pkt_dw3;
357 uint32_t iqtimer_pkt_dw4;
358 uint32_t iqtimer_pkt_dw5;
359 uint32_t iqtimer_pkt_dw6;
360 uint32_t iqtimer_pkt_dw7;
361 uint32_t iqtimer_pkt_dw8;
362 uint32_t iqtimer_pkt_dw9;
363 uint32_t iqtimer_pkt_dw10;
364 uint32_t iqtimer_pkt_dw11;
365 uint32_t iqtimer_pkt_dw12;
366 uint32_t iqtimer_pkt_dw13;
367 uint32_t iqtimer_pkt_dw14;
368 uint32_t iqtimer_pkt_dw15;
369 uint32_t iqtimer_pkt_dw16;
370 uint32_t iqtimer_pkt_dw17;
371 uint32_t iqtimer_pkt_dw18;
372 uint32_t iqtimer_pkt_dw19;
373 uint32_t iqtimer_pkt_dw20;
374 uint32_t iqtimer_pkt_dw21;
375 uint32_t iqtimer_pkt_dw22;
376 uint32_t iqtimer_pkt_dw23;
377 uint32_t iqtimer_pkt_dw24;
378 uint32_t iqtimer_pkt_dw25;
379 uint32_t iqtimer_pkt_dw26;
380 uint32_t iqtimer_pkt_dw27;
381 uint32_t iqtimer_pkt_dw28;
382 uint32_t iqtimer_pkt_dw29;
383 uint32_t iqtimer_pkt_dw30;
384 uint32_t iqtimer_pkt_dw31;
385 uint32_t reserved_225;
386 uint32_t reserved_226;
387 uint32_t reserved_227;
388 uint32_t set_resources_header;
389 uint32_t set_resources_dw1;
390 uint32_t set_resources_dw2;
391 uint32_t set_resources_dw3;
392 uint32_t set_resources_dw4;
393 uint32_t set_resources_dw5;
394 uint32_t set_resources_dw6;
395 uint32_t set_resources_dw7;
396 uint32_t reserved_236;
397 uint32_t reserved_237;
398 uint32_t reserved_238;
399 uint32_t reserved_239;
400 uint32_t queue_doorbell_id0;
401 uint32_t queue_doorbell_id1;
402 uint32_t queue_doorbell_id2;
403 uint32_t queue_doorbell_id3;
404 uint32_t queue_doorbell_id4;
405 uint32_t queue_doorbell_id5;
406 uint32_t queue_doorbell_id6;
407 uint32_t queue_doorbell_id7;
408 uint32_t queue_doorbell_id8;
409 uint32_t queue_doorbell_id9;
410 uint32_t queue_doorbell_id10;
411 uint32_t queue_doorbell_id11;
412 uint32_t queue_doorbell_id12;
413 uint32_t queue_doorbell_id13;
414 uint32_t queue_doorbell_id14;
415 uint32_t queue_doorbell_id15;
416 uint32_t reserved_256;
417 uint32_t reserved_257;
418 uint32_t reserved_258;
419 uint32_t reserved_259;
420 uint32_t reserved_260;
421 uint32_t reserved_261;
422 uint32_t reserved_262;
423 uint32_t reserved_263;
424 uint32_t reserved_264;
425 uint32_t reserved_265;
426 uint32_t reserved_266;
427 uint32_t reserved_267;
428 uint32_t reserved_268;
429 uint32_t reserved_269;
430 uint32_t reserved_270;
431 uint32_t reserved_271;
432 uint32_t reserved_272;
433 uint32_t reserved_273;
434 uint32_t reserved_274;
435 uint32_t reserved_275;
436 uint32_t reserved_276;
437 uint32_t reserved_277;
438 uint32_t reserved_278;
439 uint32_t reserved_279;
440 uint32_t reserved_280;
441 uint32_t reserved_281;
442 uint32_t reserved_282;
443 uint32_t reserved_283;
444 uint32_t reserved_284;
445 uint32_t reserved_285;
446 uint32_t reserved_286;
447 uint32_t reserved_287;
448 uint32_t reserved_288;
449 uint32_t reserved_289;
450 uint32_t reserved_290;
451 uint32_t reserved_291;
452 uint32_t reserved_292;
453 uint32_t reserved_293;
454 uint32_t reserved_294;
455 uint32_t reserved_295;
456 uint32_t reserved_296;
457 uint32_t reserved_297;
458 uint32_t reserved_298;
459 uint32_t reserved_299;
460 uint32_t reserved_300;
461 uint32_t reserved_301;
462 uint32_t reserved_302;
463 uint32_t reserved_303;
464 uint32_t reserved_304;
465 uint32_t reserved_305;
466 uint32_t reserved_306;
467 uint32_t reserved_307;
468 uint32_t reserved_308;
469 uint32_t reserved_309;
470 uint32_t reserved_310;
471 uint32_t reserved_311;
472 uint32_t reserved_312;
473 uint32_t reserved_313;
474 uint32_t reserved_314;
475 uint32_t reserved_315;
476 uint32_t reserved_316;
477 uint32_t reserved_317;
478 uint32_t reserved_318;
479 uint32_t reserved_319;
480 uint32_t reserved_320;
481 uint32_t reserved_321;
482 uint32_t reserved_322;
483 uint32_t reserved_323;
484 uint32_t reserved_324;
485 uint32_t reserved_325;
486 uint32_t reserved_326;
487 uint32_t reserved_327;
488 uint32_t reserved_328;
489 uint32_t reserved_329;
490 uint32_t reserved_330;
491 uint32_t reserved_331;
492 uint32_t reserved_332;
493 uint32_t reserved_333;
494 uint32_t reserved_334;
495 uint32_t reserved_335;
496 uint32_t reserved_336;
497 uint32_t reserved_337;
498 uint32_t reserved_338;
499 uint32_t reserved_339;
500 uint32_t reserved_340;
501 uint32_t reserved_341;
502 uint32_t reserved_342;
503 uint32_t reserved_343;
504 uint32_t reserved_344;
505 uint32_t reserved_345;
506 uint32_t reserved_346;
507 uint32_t reserved_347;
508 uint32_t reserved_348;
509 uint32_t reserved_349;
510 uint32_t reserved_350;
511 uint32_t reserved_351;
512 uint32_t reserved_352;
513 uint32_t reserved_353;
514 uint32_t reserved_354;
515 uint32_t reserved_355;
516 uint32_t reserved_356;
517 uint32_t reserved_357;
518 uint32_t reserved_358;
519 uint32_t reserved_359;
520 uint32_t reserved_360;
521 uint32_t reserved_361;
522 uint32_t reserved_362;
523 uint32_t reserved_363;
524 uint32_t reserved_364;
525 uint32_t reserved_365;
526 uint32_t reserved_366;
527 uint32_t reserved_367;
528 uint32_t reserved_368;
529 uint32_t reserved_369;
530 uint32_t reserved_370;
531 uint32_t reserved_371;
532 uint32_t reserved_372;
533 uint32_t reserved_373;
534 uint32_t reserved_374;
535 uint32_t reserved_375;
536 uint32_t reserved_376;
537 uint32_t reserved_377;
538 uint32_t reserved_378;
539 uint32_t reserved_379;
540 uint32_t reserved_380;
541 uint32_t reserved_381;
542 uint32_t reserved_382;
543 uint32_t reserved_383;
544 uint32_t reserved_384;
545 uint32_t reserved_385;
546 uint32_t reserved_386;
547 uint32_t reserved_387;
548 uint32_t reserved_388;
549 uint32_t reserved_389;
550 uint32_t reserved_390;
551 uint32_t reserved_391;
552 uint32_t reserved_392;
553 uint32_t reserved_393;
554 uint32_t reserved_394;
555 uint32_t reserved_395;
556 uint32_t reserved_396;
557 uint32_t reserved_397;
558 uint32_t reserved_398;
559 uint32_t reserved_399;
560 uint32_t reserved_400;
561 uint32_t reserved_401;
562 uint32_t reserved_402;
563 uint32_t reserved_403;
564 uint32_t reserved_404;
565 uint32_t reserved_405;
566 uint32_t reserved_406;
567 uint32_t reserved_407;
568 uint32_t reserved_408;
569 uint32_t reserved_409;
570 uint32_t reserved_410;
571 uint32_t reserved_411;
572 uint32_t reserved_412;
573 uint32_t reserved_413;
574 uint32_t reserved_414;
575 uint32_t reserved_415;
576 uint32_t reserved_416;
577 uint32_t reserved_417;
578 uint32_t reserved_418;
579 uint32_t reserved_419;
580 uint32_t reserved_420;
581 uint32_t reserved_421;
582 uint32_t reserved_422;
583 uint32_t reserved_423;
584 uint32_t reserved_424;
585 uint32_t reserved_425;
586 uint32_t reserved_426;
587 uint32_t reserved_427;
588 uint32_t reserved_428;
589 uint32_t reserved_429;
590 uint32_t reserved_430;
591 uint32_t reserved_431;
592 uint32_t reserved_432;
593 uint32_t reserved_433;
594 uint32_t reserved_434;
595 uint32_t reserved_435;
596 uint32_t reserved_436;
597 uint32_t reserved_437;
598 uint32_t reserved_438;
599 uint32_t reserved_439;
600 uint32_t reserved_440;
601 uint32_t reserved_441;
602 uint32_t reserved_442;
603 uint32_t reserved_443;
604 uint32_t reserved_444;
605 uint32_t reserved_445;
606 uint32_t reserved_446;
607 uint32_t reserved_447;
608 uint32_t reserved_448;
609 uint32_t reserved_449;
610 uint32_t reserved_450;
611 uint32_t reserved_451;
612 uint32_t reserved_452;
613 uint32_t reserved_453;
614 uint32_t reserved_454;
615 uint32_t reserved_455;
616 uint32_t reserved_456;
617 uint32_t reserved_457;
618 uint32_t reserved_458;
619 uint32_t reserved_459;
620 uint32_t reserved_460;
621 uint32_t reserved_461;
622 uint32_t reserved_462;
623 uint32_t reserved_463;
624 uint32_t reserved_464;
625 uint32_t reserved_465;
626 uint32_t reserved_466;
627 uint32_t reserved_467;
628 uint32_t reserved_468;
629 uint32_t reserved_469;
630 uint32_t reserved_470;
631 uint32_t reserved_471;
632 uint32_t reserved_472;
633 uint32_t reserved_473;
634 uint32_t reserved_474;
635 uint32_t reserved_475;
636 uint32_t reserved_476;
637 uint32_t reserved_477;
638 uint32_t reserved_478;
639 uint32_t reserved_479;
640 uint32_t reserved_480;
641 uint32_t reserved_481;
642 uint32_t reserved_482;
643 uint32_t reserved_483;
644 uint32_t reserved_484;
645 uint32_t reserved_485;
646 uint32_t reserved_486;
647 uint32_t reserved_487;
648 uint32_t reserved_488;
649 uint32_t reserved_489;
650 uint32_t reserved_490;
651 uint32_t reserved_491;
652 uint32_t reserved_492;
653 uint32_t reserved_493;
654 uint32_t reserved_494;
655 uint32_t reserved_495;
656 uint32_t reserved_496;
657 uint32_t reserved_497;
658 uint32_t reserved_498;
659 uint32_t reserved_499;
660 uint32_t reserved_500;
661 uint32_t reserved_501;
662 uint32_t reserved_502;
663 uint32_t reserved_503;
664 uint32_t reserved_504;
665 uint32_t reserved_505;
666 uint32_t reserved_506;
667 uint32_t reserved_507;
668 uint32_t reserved_508;
669 uint32_t reserved_509;
670 uint32_t reserved_510;
671 uint32_t reserved_511;
674 struct v9_mqd_allocation {
676 uint32_t wptr_poll_mem;
677 uint32_t rptr_report_mem;
678 uint32_t dynamic_cu_mask;
679 uint32_t dynamic_rb_mask;
682 /* from vega10 all CSA format is shifted to chain ib compatible mode */
683 struct v9_ce_ib_state {
684 /* section of non chained ib part */
685 uint32_t ce_ib_completion_status;
686 uint32_t ce_constegnine_count;
687 uint32_t ce_ibOffset_ib1;
688 uint32_t ce_ibOffset_ib2;
690 /* section of chained ib */
691 uint32_t ce_chainib_addrlo_ib1;
692 uint32_t ce_chainib_addrlo_ib2;
693 uint32_t ce_chainib_addrhi_ib1;
694 uint32_t ce_chainib_addrhi_ib2;
695 uint32_t ce_chainib_size_ib1;
696 uint32_t ce_chainib_size_ib2;
697 }; /* total 10 DWORD */
699 struct v9_de_ib_state {
700 /* section of non chained ib part */
701 uint32_t ib_completion_status;
702 uint32_t de_constEngine_count;
703 uint32_t ib_offset_ib1;
704 uint32_t ib_offset_ib2;
706 /* section of chained ib */
707 uint32_t chain_ib_addrlo_ib1;
708 uint32_t chain_ib_addrlo_ib2;
709 uint32_t chain_ib_addrhi_ib1;
710 uint32_t chain_ib_addrhi_ib2;
711 uint32_t chain_ib_size_ib1;
712 uint32_t chain_ib_size_ib2;
714 /* section of non chained ib part */
715 uint32_t preamble_begin_ib1;
716 uint32_t preamble_begin_ib2;
717 uint32_t preamble_end_ib1;
718 uint32_t preamble_end_ib2;
720 /* section of chained ib */
721 uint32_t chain_ib_pream_addrlo_ib1;
722 uint32_t chain_ib_pream_addrlo_ib2;
723 uint32_t chain_ib_pream_addrhi_ib1;
724 uint32_t chain_ib_pream_addrhi_ib2;
726 /* section of non chained ib part */
727 uint32_t draw_indirect_baseLo;
728 uint32_t draw_indirect_baseHi;
729 uint32_t disp_indirect_baseLo;
730 uint32_t disp_indirect_baseHi;
731 uint32_t gds_backup_addrlo;
732 uint32_t gds_backup_addrhi;
733 uint32_t index_base_addrlo;
734 uint32_t index_base_addrhi;
735 uint32_t sample_cntl;
736 }; /* Total of 27 DWORD */
738 struct v9_gfx_meta_data {
739 /* 10 DWORD, address must be 4KB aligned */
740 struct v9_ce_ib_state ce_payload;
741 uint32_t reserved1[54];
742 /* 27 DWORD, address must be 64B aligned */
743 struct v9_de_ib_state de_payload;
744 /* PFP IB base address which get pre-empted */
745 uint32_t DeIbBaseAddrLo;
746 uint32_t DeIbBaseAddrHi;
747 uint32_t reserved2[931];
748 }; /* Total of 4K Bytes */
750 #endif /* V9_STRUCTS_H_ */
projects / linux-2.6-microblaze.git / blob