drivers/gpu/drm/amd/include/soc15_hw_ip.h

   1 /*
   2  * Copyright (C) 2018  Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
  18  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  19  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  */
  21 #ifndef _soc15_hw_ip_HEADER
  22 #define _soc15_hw_ip_HEADER
  23
  24 // HW ID
  25 #define MP1_HWID                                           1
  26 #define MP2_HWID                                           2
  27 #define THM_HWID                                           3
  28 #define SMUIO_HWID                                         4
  29 #define FUSE_HWID                                          5
  30 #define CLKA_HWID                                          6
  31 #define PWR_HWID                                          10
  32 #define GC_HWID                                           11
  33 #define UVD_HWID                                          12
  34 #define VCN_HWID                                          UVD_HWID
  35 #define AUDIO_AZ_HWID                                     13
  36 #define ACP_HWID                                          14
  37 #define DCI_HWID                                          15
  38 #define DMU_HWID                                         271
  39 #define DCO_HWID                                          16
  40 #define DIO_HWID                                         272
  41 #define XDMA_HWID                                         17
  42 #define DCEAZ_HWID                                        18
  43 #define DAZ_HWID                                         274
  44 #define SDPMUX_HWID                                       19
  45 #define NTB_HWID                                          20
  46 #define IOHC_HWID                                         24
  47 #define L2IMU_HWID                                        28
  48 #define VCE_HWID                                          32
  49 #define MMHUB_HWID                                        34
  50 #define ATHUB_HWID                                        35
  51 #define DBGU_NBIO_HWID                                    36
  52 #define DFX_HWID                                          37
  53 #define DBGU0_HWID                                        38
  54 #define DBGU1_HWID                                        39
  55 #define OSSSYS_HWID                                       40
  56 #define HDP_HWID                                          41
  57 #define SDMA0_HWID                                        42
  58 #define SDMA1_HWID                                        43
  59 #define ISP_HWID                                          44
  60 #define DBGU_IO_HWID                                      45
  61 #define DF_HWID                                           46
  62 #define CLKB_HWID                                         47
  63 #define FCH_HWID                                          48
  64 #define DFX_DAP_HWID                                      49
  65 #define L1IMU_PCIE_HWID                                   50
  66 #define L1IMU_NBIF_HWID                                   51
  67 #define L1IMU_IOAGR_HWID                                  52
  68 #define L1IMU3_HWID                                       53
  69 #define L1IMU4_HWID                                       54
  70 #define L1IMU5_HWID                                       55
  71 #define L1IMU6_HWID                                       56
  72 #define L1IMU7_HWID                                       57
  73 #define L1IMU8_HWID                                       58
  74 #define L1IMU9_HWID                                       59
  75 #define L1IMU10_HWID                                      60
  76 #define L1IMU11_HWID                                      61
  77 #define L1IMU12_HWID                                      62
  78 #define L1IMU13_HWID                                      63
  79 #define L1IMU14_HWID                                      64
  80 #define L1IMU15_HWID                                      65
  81 #define WAFLC_HWID                                        66
  82 #define FCH_USB_PD_HWID                                   67
  83 #define PCIE_HWID                                         70
  84 #define PCS_HWID                                          80
  85 #define DDCL_HWID                                         89
  86 #define SST_HWID                                          90
  87 #define IOAGR_HWID                                       100
  88 #define NBIF_HWID                                        108
  89 #define IOAPIC_HWID                                      124
  90 #define SYSTEMHUB_HWID                                   128
  91 #define NTBCCP_HWID                                      144
  92 #define UMC_HWID                                         150
  93 #define SATA_HWID                                        168
  94 #define USB_HWID                                         170
  95 #define CCXSEC_HWID                                      176
  96 #define XGMI_HWID                                        200
  97 #define XGBE_HWID                                        216
  98 #define MP0_HWID                                         255
  99
 100 #endif