1 /****************************************************************************\
3 * File Name atomfirmware.h
4 * Project This is an interface header file between atombios and OS GPU drivers for SoC15 products
6 * Description header file of general definitions for OS nd pre-OS video drivers
8 * Copyright 2014 Advanced Micro Devices, Inc.
10 * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
11 * and associated documentation files (the "Software"), to deal in the Software without restriction,
12 * including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so,
14 * subject to the following conditions:
16 * The above copyright notice and this permission notice shall be included in all copies or substantial
17 * portions of the Software.
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
25 * OTHER DEALINGS IN THE SOFTWARE.
27 \****************************************************************************/
30 * If a change in VBIOS/Driver/Tool's interface is only needed for SoC15 and forward products, then the change is only needed in this atomfirmware.h header file.
31 * If a change in VBIOS/Driver/Tool's interface is only needed for pre-SoC15 products, then the change is only needed in atombios.h header file.
32 * If a change is needed for both pre and post SoC15 products, then the change has to be made separately and might be differently in both atomfirmware.h and atombios.h.
35 #ifndef _ATOMFIRMWARE_H_
36 #define _ATOMFIRMWARE_H_
38 enum atom_bios_header_version_def{
39 ATOM_MAJOR_VERSION =0x0003,
40 ATOM_MINOR_VERSION =0x0003,
45 typedef unsigned long uint32_t;
49 typedef unsigned short uint16_t;
53 typedef unsigned char uint8_t;
64 ATOM_CRTC_INVALID =0xff,
72 ATOM_COMBOPHY_PLL0 =20,
73 ATOM_COMBOPHY_PLL1 =21,
74 ATOM_COMBOPHY_PLL2 =22,
75 ATOM_COMBOPHY_PLL3 =23,
76 ATOM_COMBOPHY_PLL4 =24,
77 ATOM_COMBOPHY_PLL5 =25,
78 ATOM_PPLL_INVALID =0xff,
81 // define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSel
83 ASIC_INT_DIG1_ENCODER_ID =0x03,
84 ASIC_INT_DIG2_ENCODER_ID =0x09,
85 ASIC_INT_DIG3_ENCODER_ID =0x0a,
86 ASIC_INT_DIG4_ENCODER_ID =0x0b,
87 ASIC_INT_DIG5_ENCODER_ID =0x0c,
88 ASIC_INT_DIG6_ENCODER_ID =0x0d,
89 ASIC_INT_DIG7_ENCODER_ID =0x0e,
93 enum atom_encode_mode_def
95 ATOM_ENCODER_MODE_DP =0,
96 ATOM_ENCODER_MODE_DP_SST =0,
97 ATOM_ENCODER_MODE_LVDS =1,
98 ATOM_ENCODER_MODE_DVI =2,
99 ATOM_ENCODER_MODE_HDMI =3,
100 ATOM_ENCODER_MODE_DP_AUDIO =5,
101 ATOM_ENCODER_MODE_DP_MST =5,
102 ATOM_ENCODER_MODE_CRT =15,
103 ATOM_ENCODER_MODE_DVO =16,
106 enum atom_encoder_refclk_src_def{
107 ENCODER_REFCLK_SRC_P1PLL =0,
108 ENCODER_REFCLK_SRC_P2PLL =1,
109 ENCODER_REFCLK_SRC_P3PLL =2,
110 ENCODER_REFCLK_SRC_EXTCLK =3,
111 ENCODER_REFCLK_SRC_INVALID =0xff,
114 enum atom_scaler_def{
115 ATOM_SCALER_DISABLE =0, /*scaler bypass mode, auto-center & no replication*/
116 ATOM_SCALER_CENTER =1, //For Fudo, it's bypass and auto-center & auto replication
117 ATOM_SCALER_EXPANSION =2, /*scaler expansion by 2 tap alpha blending mode*/
120 enum atom_operation_def{
127 enum atom_embedded_display_op_def{
130 ATOM_LCD_BL_BRIGHTNESS_CONTROL = 4,
131 ATOM_LCD_SELFTEST_START = 5,
132 ATOM_LCD_SELFTEST_STOP = 6,
135 enum atom_spread_spectrum_mode{
136 ATOM_SS_CENTER_OR_DOWN_MODE_MASK = 0x01,
137 ATOM_SS_DOWN_SPREAD_MODE = 0x00,
138 ATOM_SS_CENTRE_SPREAD_MODE = 0x01,
139 ATOM_INT_OR_EXT_SS_MASK = 0x02,
140 ATOM_INTERNAL_SS_MASK = 0x00,
141 ATOM_EXTERNAL_SS_MASK = 0x02,
144 /* define panel bit per color */
145 enum atom_panel_bit_per_color{
146 PANEL_BPC_UNDEFINE =0x00,
147 PANEL_6BIT_PER_COLOR =0x01,
148 PANEL_8BIT_PER_COLOR =0x02,
149 PANEL_10BIT_PER_COLOR =0x03,
150 PANEL_12BIT_PER_COLOR =0x04,
151 PANEL_16BIT_PER_COLOR =0x05,
155 enum atom_voltage_type
157 VOLTAGE_TYPE_VDDC = 1,
158 VOLTAGE_TYPE_MVDDC = 2,
159 VOLTAGE_TYPE_MVDDQ = 3,
160 VOLTAGE_TYPE_VDDCI = 4,
161 VOLTAGE_TYPE_VDDGFX = 5,
162 VOLTAGE_TYPE_PCC = 6,
163 VOLTAGE_TYPE_MVPP = 7,
164 VOLTAGE_TYPE_LEDDPM = 8,
165 VOLTAGE_TYPE_PCC_MVDD = 9,
166 VOLTAGE_TYPE_PCIE_VDDC = 10,
167 VOLTAGE_TYPE_PCIE_VDDR = 11,
168 VOLTAGE_TYPE_GENERIC_I2C_1 = 0x11,
169 VOLTAGE_TYPE_GENERIC_I2C_2 = 0x12,
170 VOLTAGE_TYPE_GENERIC_I2C_3 = 0x13,
171 VOLTAGE_TYPE_GENERIC_I2C_4 = 0x14,
172 VOLTAGE_TYPE_GENERIC_I2C_5 = 0x15,
173 VOLTAGE_TYPE_GENERIC_I2C_6 = 0x16,
174 VOLTAGE_TYPE_GENERIC_I2C_7 = 0x17,
175 VOLTAGE_TYPE_GENERIC_I2C_8 = 0x18,
176 VOLTAGE_TYPE_GENERIC_I2C_9 = 0x19,
177 VOLTAGE_TYPE_GENERIC_I2C_10 = 0x1A,
180 enum atom_dgpu_vram_type {
181 ATOM_DGPU_VRAM_TYPE_GDDR5 = 0x50,
182 ATOM_DGPU_VRAM_TYPE_HBM2 = 0x60,
183 ATOM_DGPU_VRAM_TYPE_GDDR6 = 0x70,
186 enum atom_dp_vs_preemph_def{
187 DP_VS_LEVEL0_PREEMPH_LEVEL0 = 0x00,
188 DP_VS_LEVEL1_PREEMPH_LEVEL0 = 0x01,
189 DP_VS_LEVEL2_PREEMPH_LEVEL0 = 0x02,
190 DP_VS_LEVEL3_PREEMPH_LEVEL0 = 0x03,
191 DP_VS_LEVEL0_PREEMPH_LEVEL1 = 0x08,
192 DP_VS_LEVEL1_PREEMPH_LEVEL1 = 0x09,
193 DP_VS_LEVEL2_PREEMPH_LEVEL1 = 0x0a,
194 DP_VS_LEVEL0_PREEMPH_LEVEL2 = 0x10,
195 DP_VS_LEVEL1_PREEMPH_LEVEL2 = 0x11,
196 DP_VS_LEVEL0_PREEMPH_LEVEL3 = 0x18,
201 enum atom_string_def{
202 asic_bus_type_pcie_string = "PCI_EXPRESS",
203 atom_fire_gl_string = "FGL",
204 atom_bios_string = "ATOM"
208 #pragma pack(1) /* BIOS data must use byte aligment*/
210 enum atombios_image_offset{
211 OFFSET_TO_ATOM_ROM_HEADER_POINTER =0x00000048,
212 OFFSET_TO_ATOM_ROM_IMAGE_SIZE =0x00000002,
213 OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE =0x94,
214 MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE =20, /*including the terminator 0x0!*/
215 OFFSET_TO_GET_ATOMBIOS_NUMBER_OF_STRINGS =0x2f,
216 OFFSET_TO_GET_ATOMBIOS_STRING_START =0x6e,
219 /****************************************************************************
220 * Common header for all tables (Data table, Command function).
221 * Every table pointed in _ATOM_MASTER_DATA_TABLE has this common header.
222 * And the pointer actually points to this header.
223 ****************************************************************************/
225 struct atom_common_table_header
227 uint16_t structuresize;
228 uint8_t format_revision; //mainly used for a hw function, when the parser is not backward compatible
229 uint8_t content_revision; //change it when a data table has a structure change, or a hw function has a input/output parameter change
232 /****************************************************************************
233 * Structure stores the ROM header.
234 ****************************************************************************/
235 struct atom_rom_header_v2_2
237 struct atom_common_table_header table_header;
238 uint8_t atom_bios_string[4]; //enum atom_string_def atom_bios_string; //Signature to distinguish between Atombios and non-atombios,
239 uint16_t bios_segment_address;
240 uint16_t protectedmodeoffset;
241 uint16_t configfilenameoffset;
242 uint16_t crc_block_offset;
243 uint16_t vbios_bootupmessageoffset;
244 uint16_t int10_offset;
245 uint16_t pcibusdevinitcode;
246 uint16_t iobaseaddress;
247 uint16_t subsystem_vendor_id;
248 uint16_t subsystem_id;
249 uint16_t pci_info_offset;
250 uint16_t masterhwfunction_offset; //Offest for SW to get all command function offsets, Don't change the position
251 uint16_t masterdatatable_offset; //Offest for SW to get all data table offsets, Don't change the position
253 uint32_t pspdirtableoffset;
256 /*==============================hw function portion======================================================================*/
259 /****************************************************************************
260 * Structures used in Command.mtb, each function name is not given here since those function could change from time to time
261 * The real functionality of each function is associated with the parameter structure version when defined
262 * For all internal cmd function definitions, please reference to atomstruct.h
263 ****************************************************************************/
264 struct atom_master_list_of_command_functions_v2_1{
265 uint16_t asic_init; //Function
266 uint16_t cmd_function1; //used as an internal one
267 uint16_t cmd_function2; //used as an internal one
268 uint16_t cmd_function3; //used as an internal one
269 uint16_t digxencodercontrol; //Function
270 uint16_t cmd_function5; //used as an internal one
271 uint16_t cmd_function6; //used as an internal one
272 uint16_t cmd_function7; //used as an internal one
273 uint16_t cmd_function8; //used as an internal one
274 uint16_t cmd_function9; //used as an internal one
275 uint16_t setengineclock; //Function
276 uint16_t setmemoryclock; //Function
277 uint16_t setpixelclock; //Function
278 uint16_t enabledisppowergating; //Function
279 uint16_t cmd_function14; //used as an internal one
280 uint16_t cmd_function15; //used as an internal one
281 uint16_t cmd_function16; //used as an internal one
282 uint16_t cmd_function17; //used as an internal one
283 uint16_t cmd_function18; //used as an internal one
284 uint16_t cmd_function19; //used as an internal one
285 uint16_t cmd_function20; //used as an internal one
286 uint16_t cmd_function21; //used as an internal one
287 uint16_t cmd_function22; //used as an internal one
288 uint16_t cmd_function23; //used as an internal one
289 uint16_t cmd_function24; //used as an internal one
290 uint16_t cmd_function25; //used as an internal one
291 uint16_t cmd_function26; //used as an internal one
292 uint16_t cmd_function27; //used as an internal one
293 uint16_t cmd_function28; //used as an internal one
294 uint16_t cmd_function29; //used as an internal one
295 uint16_t cmd_function30; //used as an internal one
296 uint16_t cmd_function31; //used as an internal one
297 uint16_t cmd_function32; //used as an internal one
298 uint16_t cmd_function33; //used as an internal one
299 uint16_t blankcrtc; //Function
300 uint16_t enablecrtc; //Function
301 uint16_t cmd_function36; //used as an internal one
302 uint16_t cmd_function37; //used as an internal one
303 uint16_t cmd_function38; //used as an internal one
304 uint16_t cmd_function39; //used as an internal one
305 uint16_t cmd_function40; //used as an internal one
306 uint16_t getsmuclockinfo; //Function
307 uint16_t selectcrtc_source; //Function
308 uint16_t cmd_function43; //used as an internal one
309 uint16_t cmd_function44; //used as an internal one
310 uint16_t cmd_function45; //used as an internal one
311 uint16_t setdceclock; //Function
312 uint16_t getmemoryclock; //Function
313 uint16_t getengineclock; //Function
314 uint16_t setcrtc_usingdtdtiming; //Function
315 uint16_t externalencodercontrol; //Function
316 uint16_t cmd_function51; //used as an internal one
317 uint16_t cmd_function52; //used as an internal one
318 uint16_t cmd_function53; //used as an internal one
319 uint16_t processi2cchanneltransaction;//Function
320 uint16_t cmd_function55; //used as an internal one
321 uint16_t cmd_function56; //used as an internal one
322 uint16_t cmd_function57; //used as an internal one
323 uint16_t cmd_function58; //used as an internal one
324 uint16_t cmd_function59; //used as an internal one
325 uint16_t computegpuclockparam; //Function
326 uint16_t cmd_function61; //used as an internal one
327 uint16_t cmd_function62; //used as an internal one
328 uint16_t dynamicmemorysettings; //Function function
329 uint16_t memorytraining; //Function function
330 uint16_t cmd_function65; //used as an internal one
331 uint16_t cmd_function66; //used as an internal one
332 uint16_t setvoltage; //Function
333 uint16_t cmd_function68; //used as an internal one
334 uint16_t readefusevalue; //Function
335 uint16_t cmd_function70; //used as an internal one
336 uint16_t cmd_function71; //used as an internal one
337 uint16_t cmd_function72; //used as an internal one
338 uint16_t cmd_function73; //used as an internal one
339 uint16_t cmd_function74; //used as an internal one
340 uint16_t cmd_function75; //used as an internal one
341 uint16_t dig1transmittercontrol; //Function
342 uint16_t cmd_function77; //used as an internal one
343 uint16_t processauxchanneltransaction;//Function
344 uint16_t cmd_function79; //used as an internal one
345 uint16_t getvoltageinfo; //Function
348 struct atom_master_command_function_v2_1
350 struct atom_common_table_header table_header;
351 struct atom_master_list_of_command_functions_v2_1 listofcmdfunctions;
354 /****************************************************************************
355 * Structures used in every command function
356 ****************************************************************************/
357 struct atom_function_attribute
359 uint16_t ws_in_bytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword),
360 uint16_t ps_in_bytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword),
361 uint16_t updated_by_util:1; //[15]=flag to indicate the function is updated by util
365 /****************************************************************************
366 * Common header for all hw functions.
367 * Every function pointed by _master_list_of_hw_function has this common header.
368 * And the pointer actually points to this header.
369 ****************************************************************************/
370 struct atom_rom_hw_function_header
372 struct atom_common_table_header func_header;
373 struct atom_function_attribute func_attrib;
377 /*==============================sw data table portion======================================================================*/
378 /****************************************************************************
379 * Structures used in data.mtb, each data table name is not given here since those data table could change from time to time
380 * The real name of each table is given when its data structure version is defined
381 ****************************************************************************/
382 struct atom_master_list_of_data_tables_v2_1{
383 uint16_t utilitypipeline; /* Offest for the utility to get parser info,Don't change this position!*/
384 uint16_t multimedia_info;
385 uint16_t smc_dpm_info;
386 uint16_t sw_datatable3;
387 uint16_t firmwareinfo; /* Shared by various SW components */
388 uint16_t sw_datatable5;
389 uint16_t lcd_info; /* Shared by various SW components */
390 uint16_t sw_datatable7;
392 uint16_t sw_datatable9;
393 uint16_t sw_datatable10;
394 uint16_t vram_usagebyfirmware; /* Shared by various SW components */
395 uint16_t gpio_pin_lut; /* Shared by various SW components */
396 uint16_t sw_datatable13;
398 uint16_t powerplayinfo; /* Shared by various SW components */
399 uint16_t sw_datatable16;
400 uint16_t sw_datatable17;
401 uint16_t sw_datatable18;
402 uint16_t sw_datatable19;
403 uint16_t sw_datatable20;
404 uint16_t sw_datatable21;
405 uint16_t displayobjectinfo; /* Shared by various SW components */
406 uint16_t indirectioaccess; /* used as an internal one */
407 uint16_t umc_info; /* Shared by various SW components */
408 uint16_t sw_datatable25;
409 uint16_t sw_datatable26;
410 uint16_t dce_info; /* Shared by various SW components */
411 uint16_t vram_info; /* Shared by various SW components */
412 uint16_t sw_datatable29;
413 uint16_t integratedsysteminfo; /* Shared by various SW components */
414 uint16_t asic_profiling_info; /* Shared by various SW components */
415 uint16_t voltageobject_info; /* shared by various SW components */
416 uint16_t sw_datatable33;
417 uint16_t sw_datatable34;
421 struct atom_master_data_table_v2_1
423 struct atom_common_table_header table_header;
424 struct atom_master_list_of_data_tables_v2_1 listOfdatatables;
428 struct atom_dtd_format
432 uint16_t h_blanking_time;
434 uint16_t v_blanking_time;
435 uint16_t h_sync_offset;
436 uint16_t h_sync_width;
437 uint16_t v_sync_offset;
438 uint16_t v_syncwidth;
444 uint8_t atom_mode_id;
448 /* atom_dtd_format.modemiscinfo defintion */
449 enum atom_dtd_format_modemiscinfo{
450 ATOM_HSYNC_POLARITY = 0x0002,
451 ATOM_VSYNC_POLARITY = 0x0004,
452 ATOM_H_REPLICATIONBY2 = 0x0010,
453 ATOM_V_REPLICATIONBY2 = 0x0020,
454 ATOM_INTERLACE = 0x0080,
455 ATOM_COMPOSITESYNC = 0x0040,
460 * when format_revision==1 && content_revision==1, then this an info table for atomworks to use during debug session, no structure is associated with it.
461 * the location of it can't change
466 ***************************************************************************
467 Data Table firmwareinfo structure
468 ***************************************************************************
471 struct atom_firmware_info_v3_1
473 struct atom_common_table_header table_header;
474 uint32_t firmware_revision;
475 uint32_t bootup_sclk_in10khz;
476 uint32_t bootup_mclk_in10khz;
477 uint32_t firmware_capability; // enum atombios_firmware_capability
478 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */
479 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address
480 uint16_t bootup_vddc_mv;
481 uint16_t bootup_vddci_mv;
482 uint16_t bootup_mvddc_mv;
483 uint16_t bootup_vddgfx_mv;
484 uint8_t mem_module_id;
485 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
486 uint8_t reserved1[2];
487 uint32_t mc_baseaddr_high;
488 uint32_t mc_baseaddr_low;
489 uint32_t reserved2[6];
492 /* Total 32bit cap indication */
493 enum atombios_firmware_capability
495 ATOM_FIRMWARE_CAP_FIRMWARE_POSTED = 0x00000001,
496 ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION = 0x00000002,
497 ATOM_FIRMWARE_CAP_WMI_SUPPORT = 0x00000040,
498 ATOM_FIRMWARE_CAP_HWEMU_ENABLE = 0x00000080,
499 ATOM_FIRMWARE_CAP_HWEMU_UMC_CFG = 0x00000100,
500 ATOM_FIRMWARE_CAP_SRAM_ECC = 0x00000200,
501 ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING = 0x00000400,
504 enum atom_cooling_solution_id{
506 LIQUID_COOLING = 0x01
509 struct atom_firmware_info_v3_2 {
510 struct atom_common_table_header table_header;
511 uint32_t firmware_revision;
512 uint32_t bootup_sclk_in10khz;
513 uint32_t bootup_mclk_in10khz;
514 uint32_t firmware_capability; // enum atombios_firmware_capability
515 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */
516 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address
517 uint16_t bootup_vddc_mv;
518 uint16_t bootup_vddci_mv;
519 uint16_t bootup_mvddc_mv;
520 uint16_t bootup_vddgfx_mv;
521 uint8_t mem_module_id;
522 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
523 uint8_t reserved1[2];
524 uint32_t mc_baseaddr_high;
525 uint32_t mc_baseaddr_low;
526 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def
527 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id
528 uint8_t board_i2c_feature_slave_addr;
530 uint16_t bootup_mvddq_mv;
531 uint16_t bootup_mvpp_mv;
532 uint32_t zfbstartaddrin16mb;
533 uint32_t reserved2[3];
536 struct atom_firmware_info_v3_3
538 struct atom_common_table_header table_header;
539 uint32_t firmware_revision;
540 uint32_t bootup_sclk_in10khz;
541 uint32_t bootup_mclk_in10khz;
542 uint32_t firmware_capability; // enum atombios_firmware_capability
543 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */
544 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address
545 uint16_t bootup_vddc_mv;
546 uint16_t bootup_vddci_mv;
547 uint16_t bootup_mvddc_mv;
548 uint16_t bootup_vddgfx_mv;
549 uint8_t mem_module_id;
550 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
551 uint8_t reserved1[2];
552 uint32_t mc_baseaddr_high;
553 uint32_t mc_baseaddr_low;
554 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def
555 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id
556 uint8_t board_i2c_feature_slave_addr;
558 uint16_t bootup_mvddq_mv;
559 uint16_t bootup_mvpp_mv;
560 uint32_t zfbstartaddrin16mb;
561 uint32_t pplib_pptable_id; // if pplib_pptable_id!=0, pplib get powerplay table inside driver instead of from VBIOS
562 uint32_t reserved2[2];
566 ***************************************************************************
567 Data Table lcd_info structure
568 ***************************************************************************
573 struct atom_common_table_header table_header;
574 struct atom_dtd_format lcd_timing;
575 uint16_t backlight_pwm;
576 uint16_t special_handle_cap;
578 uint16_t lvds_max_slink_pclk;
579 uint16_t lvds_ss_percentage;
580 uint16_t lvds_ss_rate_10hz;
581 uint8_t pwr_on_digon_to_de; /*all pwr sequence numbers below are in uint of 4ms*/
582 uint8_t pwr_on_de_to_vary_bl;
583 uint8_t pwr_down_vary_bloff_to_de;
584 uint8_t pwr_down_de_to_digoff;
585 uint8_t pwr_off_delay;
586 uint8_t pwr_on_vary_bl_to_blon;
587 uint8_t pwr_down_bloff_to_vary_bloff;
589 uint8_t dpcd_edp_config_cap;
590 uint8_t dpcd_max_link_rate;
591 uint8_t dpcd_max_lane_count;
592 uint8_t dpcd_max_downspread;
593 uint8_t min_allowed_bl_level;
594 uint8_t max_allowed_bl_level;
595 uint8_t bootup_bl_level;
597 uint32_t reserved1[8];
600 /* lcd_info_v2_1.panel_misc defintion */
601 enum atom_lcd_info_panel_misc{
602 ATOM_PANEL_MISC_FPDI =0x0002,
606 enum atom_lcd_info_dptolvds_rx_id
608 eDP_TO_LVDS_RX_DISABLE = 0x00, // no eDP->LVDS translator chip
609 eDP_TO_LVDS_COMMON_ID = 0x01, // common eDP->LVDS translator chip without AMD SW init
610 eDP_TO_LVDS_REALTEK_ID = 0x02, // Realtek tansaltor which require AMD SW init
615 ***************************************************************************
616 Data Table gpio_pin_lut structure
617 ***************************************************************************
620 struct atom_gpio_pin_assignment
622 uint32_t data_a_reg_index;
623 uint8_t gpio_bitshift;
624 uint8_t gpio_mask_bitshift;
629 /* atom_gpio_pin_assignment.gpio_id definition */
630 enum atom_gpio_pin_assignment_gpio_id {
631 I2C_HW_LANE_MUX =0x0f, /* only valid when bit7=1 */
632 I2C_HW_ENGINE_ID_MASK =0x70, /* only valid when bit7=1 */
633 I2C_HW_CAP =0x80, /*only when the I2C_HW_CAP is set, the pin ID is assigned to an I2C pin pair, otherwise, it's an generic GPIO pin */
635 /* gpio_id pre-define id for multiple usage */
636 /* GPIO use to control PCIE_VDDC in certain SLT board */
637 PCIE_VDDC_CONTROL_GPIO_PINID = 56,
638 /* if PP_AC_DC_SWITCH_GPIO_PINID in Gpio_Pin_LutTable, AC/DC swithing feature is enable */
639 PP_AC_DC_SWITCH_GPIO_PINID = 60,
640 /* VDDC_REGULATOR_VRHOT_GPIO_PINID in Gpio_Pin_LutTable, VRHot feature is enable */
641 VDDC_VRHOT_GPIO_PINID = 61,
642 /*if VDDC_PCC_GPIO_PINID in GPIO_LUTable, Peak Current Control feature is enabled */
643 VDDC_PCC_GPIO_PINID = 62,
644 /* Only used on certain SLT/PA board to allow utility to cut Efuse. */
645 EFUSE_CUT_ENABLE_GPIO_PINID = 63,
646 /* ucGPIO=DRAM_SELF_REFRESH_GPIO_PIND uses for memory self refresh (ucGPIO=0, DRAM self-refresh; ucGPIO= */
647 DRAM_SELF_REFRESH_GPIO_PINID = 64,
648 /* Thermal interrupt output->system thermal chip GPIO pin */
649 THERMAL_INT_OUTPUT_GPIO_PINID =65,
653 struct atom_gpio_pin_lut_v2_1
655 struct atom_common_table_header table_header;
656 /*the real number of this included in the structure is calcualted by using the (whole structure size - the header size)/size of atom_gpio_pin_lut */
657 struct atom_gpio_pin_assignment gpio_pin[8];
662 ***************************************************************************
663 Data Table vram_usagebyfirmware structure
664 ***************************************************************************
667 struct vram_usagebyfirmware_v2_1
669 struct atom_common_table_header table_header;
670 uint32_t start_address_in_kb;
671 uint16_t used_by_firmware_in_kb;
672 uint16_t used_by_driver_in_kb;
677 ***************************************************************************
678 Data Table displayobjectinfo structure
679 ***************************************************************************
682 enum atom_object_record_type_id
684 ATOM_I2C_RECORD_TYPE =1,
685 ATOM_HPD_INT_RECORD_TYPE =2,
686 ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE =9,
687 ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE =16,
688 ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE =17,
689 ATOM_ENCODER_CAP_RECORD_TYPE=20,
690 ATOM_BRACKET_LAYOUT_RECORD_TYPE=21,
691 ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD_TYPE=22,
692 ATOM_RECORD_END_TYPE =0xFF,
695 struct atom_common_record_header
697 uint8_t record_type; //An emun to indicate the record type
698 uint8_t record_size; //The size of the whole record in byte
701 struct atom_i2c_record
703 struct atom_common_record_header record_header; //record_type = ATOM_I2C_RECORD_TYPE
705 uint8_t i2c_slave_addr; //The slave address, it's 0 when the record is attached to connector for DDC
708 struct atom_hpd_int_record
710 struct atom_common_record_header record_header; //record_type = ATOM_HPD_INT_RECORD_TYPE
711 uint8_t pin_id; //Corresponding block in GPIO_PIN_INFO table gives the pin info
712 uint8_t plugin_pin_state;
715 // Bit maps for ATOM_ENCODER_CAP_RECORD.usEncoderCap
716 enum atom_encoder_caps_def
718 ATOM_ENCODER_CAP_RECORD_HBR2 =0x01, // DP1.2 HBR2 is supported by HW encoder, it is retired in NI. the real meaning from SI is MST_EN
719 ATOM_ENCODER_CAP_RECORD_MST_EN =0x01, // from SI, this bit means DP MST is enable or not.
720 ATOM_ENCODER_CAP_RECORD_HBR2_EN =0x02, // DP1.2 HBR2 setting is qualified and HBR2 can be enabled
721 ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN =0x04, // HDMI2.0 6Gbps enable or not.
722 ATOM_ENCODER_CAP_RECORD_HBR3_EN =0x08, // DP1.3 HBR3 is supported by board.
723 ATOM_ENCODER_CAP_RECORD_USB_C_TYPE =0x100, // the DP connector is a USB-C type.
726 struct atom_encoder_caps_record
728 struct atom_common_record_header record_header; //record_type = ATOM_ENCODER_CAP_RECORD_TYPE
729 uint32_t encodercaps;
732 enum atom_connector_caps_def
734 ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY = 0x01, //a cap bit to indicate that this non-embedded display connector is an internal display
735 ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL = 0x02, //a cap bit to indicate that this internal display requires BL control from GPU, refers to lcd_info for BL PWM freq
738 struct atom_disp_connector_caps_record
740 struct atom_common_record_header record_header;
741 uint32_t connectcaps;
744 //The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually
745 struct atom_gpio_pin_control_pair
747 uint8_t gpio_id; // GPIO_ID, find the corresponding ID in GPIO_LUT table
748 uint8_t gpio_pinstate; // Pin state showing how to set-up the pin
751 struct atom_object_gpio_cntl_record
753 struct atom_common_record_header record_header;
754 uint8_t flag; // Future expnadibility
755 uint8_t number_of_pins; // Number of GPIO pins used to control the object
756 struct atom_gpio_pin_control_pair gpio[1]; // the real gpio pin pair determined by number of pins ucNumberOfPins
759 //Definitions for GPIO pin state
760 enum atom_gpio_pin_control_pinstate_def
762 GPIO_PIN_TYPE_INPUT = 0x00,
763 GPIO_PIN_TYPE_OUTPUT = 0x10,
764 GPIO_PIN_TYPE_HW_CONTROL = 0x20,
766 //For GPIO_PIN_TYPE_OUTPUT the following is defined
767 GPIO_PIN_OUTPUT_STATE_MASK = 0x01,
768 GPIO_PIN_OUTPUT_STATE_SHIFT = 0,
769 GPIO_PIN_STATE_ACTIVE_LOW = 0x0,
770 GPIO_PIN_STATE_ACTIVE_HIGH = 0x1,
773 // Indexes to GPIO array in GLSync record
774 // GLSync record is for Frame Lock/Gen Lock feature.
775 enum atom_glsync_record_gpio_index_def
777 ATOM_GPIO_INDEX_GLSYNC_REFCLK = 0,
778 ATOM_GPIO_INDEX_GLSYNC_HSYNC = 1,
779 ATOM_GPIO_INDEX_GLSYNC_VSYNC = 2,
780 ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ = 3,
781 ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT = 4,
782 ATOM_GPIO_INDEX_GLSYNC_INTERRUPT = 5,
783 ATOM_GPIO_INDEX_GLSYNC_V_RESET = 6,
784 ATOM_GPIO_INDEX_GLSYNC_SWAP_CNTL = 7,
785 ATOM_GPIO_INDEX_GLSYNC_SWAP_SEL = 8,
786 ATOM_GPIO_INDEX_GLSYNC_MAX = 9,
790 struct atom_connector_hpdpin_lut_record //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE
792 struct atom_common_record_header record_header;
793 uint8_t hpd_pin_map[8];
796 struct atom_connector_auxddc_lut_record //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE
798 struct atom_common_record_header record_header;
799 uint8_t aux_ddc_map[8];
802 struct atom_connector_forced_tmds_cap_record
804 struct atom_common_record_header record_header;
805 // override TMDS capability on this connector when it operate in TMDS mode. usMaxTmdsClkRate = max TMDS Clock in Mhz/2.5
806 uint8_t maxtmdsclkrate_in2_5mhz;
810 struct atom_connector_layout_info
812 uint16_t connectorobjid;
813 uint8_t connector_type;
817 // define ATOM_CONNECTOR_LAYOUT_INFO.ucConnectorType to describe the display connector size
818 enum atom_connector_layout_info_connector_type_def
820 CONNECTOR_TYPE_DVI_D = 1,
822 CONNECTOR_TYPE_HDMI = 4,
823 CONNECTOR_TYPE_DISPLAY_PORT = 5,
824 CONNECTOR_TYPE_MINI_DISPLAY_PORT = 6,
827 struct atom_bracket_layout_record
829 struct atom_common_record_header record_header;
831 uint8_t bracketwidth;
834 struct atom_connector_layout_info conn_info[1];
837 enum atom_display_device_tag_def{
838 ATOM_DISPLAY_LCD1_SUPPORT = 0x0002, //an embedded display is either an LVDS or eDP signal type of display
839 ATOM_DISPLAY_DFP1_SUPPORT = 0x0008,
840 ATOM_DISPLAY_DFP2_SUPPORT = 0x0080,
841 ATOM_DISPLAY_DFP3_SUPPORT = 0x0200,
842 ATOM_DISPLAY_DFP4_SUPPORT = 0x0400,
843 ATOM_DISPLAY_DFP5_SUPPORT = 0x0800,
844 ATOM_DISPLAY_DFP6_SUPPORT = 0x0040,
845 ATOM_DISPLAY_DFPx_SUPPORT = 0x0ec8,
848 struct atom_display_object_path_v2
850 uint16_t display_objid; //Connector Object ID or Misc Object ID
851 uint16_t disp_recordoffset;
852 uint16_t encoderobjid; //first encoder closer to the connector, could be either an external or intenal encoder
853 uint16_t extencoderobjid; //2nd encoder after the first encoder, from the connector point of view;
854 uint16_t encoder_recordoffset;
855 uint16_t extencoder_recordoffset;
856 uint16_t device_tag; //a supported device vector, each display path starts with this.the paths are enumerated in the way of priority, a path appears first
861 struct display_object_info_table_v1_4
863 struct atom_common_table_header table_header;
864 uint16_t supporteddevices;
865 uint8_t number_of_path;
867 struct atom_display_object_path_v2 display_path[8]; //the real number of this included in the structure is calculated by using the (whole structure size - the header size- number_of_path)/size of atom_display_object_path
872 ***************************************************************************
873 Data Table dce_info structure
874 ***************************************************************************
876 struct atom_display_controller_info_v4_1
878 struct atom_common_table_header table_header;
879 uint32_t display_caps;
880 uint32_t bootup_dispclk_10khz;
881 uint16_t dce_refclk_10khz;
882 uint16_t i2c_engine_refclk_10khz;
883 uint16_t dvi_ss_percentage; // in unit of 0.001%
884 uint16_t dvi_ss_rate_10hz;
885 uint16_t hdmi_ss_percentage; // in unit of 0.001%
886 uint16_t hdmi_ss_rate_10hz;
887 uint16_t dp_ss_percentage; // in unit of 0.001%
888 uint16_t dp_ss_rate_10hz;
889 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode
890 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode
891 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode
893 uint8_t hardcode_mode_num; // a hardcode mode number defined in StandardVESA_TimingTable when a CRT or DFP EDID is not available
894 uint8_t reserved1[3];
895 uint16_t dpphy_refclk_10khz;
897 uint8_t dceip_min_ver;
898 uint8_t dceip_max_ver;
899 uint8_t max_disp_pipe_num;
900 uint8_t max_vbios_active_disp_pipe_num;
901 uint8_t max_ppll_num;
902 uint8_t max_disp_phy_num;
903 uint8_t max_aux_pairs;
904 uint8_t remotedisplayconfig;
905 uint8_t reserved3[8];
909 struct atom_display_controller_info_v4_2
911 struct atom_common_table_header table_header;
912 uint32_t display_caps;
913 uint32_t bootup_dispclk_10khz;
914 uint16_t dce_refclk_10khz;
915 uint16_t i2c_engine_refclk_10khz;
916 uint16_t dvi_ss_percentage; // in unit of 0.001%
917 uint16_t dvi_ss_rate_10hz;
918 uint16_t hdmi_ss_percentage; // in unit of 0.001%
919 uint16_t hdmi_ss_rate_10hz;
920 uint16_t dp_ss_percentage; // in unit of 0.001%
921 uint16_t dp_ss_rate_10hz;
922 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode
923 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode
924 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode
926 uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available
927 uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available
928 uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
929 uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
930 uint16_t dpphy_refclk_10khz;
932 uint8_t dcnip_min_ver;
933 uint8_t dcnip_max_ver;
934 uint8_t max_disp_pipe_num;
935 uint8_t max_vbios_active_disp_pipe_num;
936 uint8_t max_ppll_num;
937 uint8_t max_disp_phy_num;
938 uint8_t max_aux_pairs;
939 uint8_t remotedisplayconfig;
940 uint8_t reserved3[8];
944 enum dce_info_caps_def
947 DCE_INFO_CAPS_FORCE_DISPDEV_CONNECTED =0x02,
949 DCE_INFO_CAPS_DISABLE_DFP_DP_HBR2 =0x04,
951 DCE_INFO_CAPS_ENABLE_INTERLAC_TIMING =0x08,
956 ***************************************************************************
957 Data Table ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO structure
958 ***************************************************************************
960 struct atom_ext_display_path
962 uint16_t device_tag; //A bit vector to show what devices are supported
963 uint16_t device_acpi_enum; //16bit device ACPI id.
964 uint16_t connectorobjid; //A physical connector for displays to plug in, using object connector definitions
965 uint8_t auxddclut_index; //An index into external AUX/DDC channel LUT
966 uint8_t hpdlut_index; //An index into external HPD pin LUT
967 uint16_t ext_encoder_objid; //external encoder object id
968 uint8_t channelmapping; // if ucChannelMapping=0, using default one to one mapping
969 uint8_t chpninvert; // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted
975 enum ext_display_path_cap_def
977 EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE =0x0001,
978 EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN =0x0002,
979 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK =0x007C,
982 struct atom_external_display_connection_info
984 struct atom_common_table_header table_header;
985 uint8_t guid[16]; // a GUID is a 16 byte long string
986 struct atom_ext_display_path path[7]; // total of fixed 7 entries.
987 uint8_t checksum; // a simple Checksum of the sum of whole structure equal to 0x0.
988 uint8_t stereopinid; // use for eDP panel
989 uint8_t remotedisplayconfig;
990 uint8_t edptolvdsrxid;
991 uint8_t fixdpvoltageswing; // usCaps[1]=1, this indicate DP_LANE_SET value
992 uint8_t reserved[3]; // for potential expansion
996 ***************************************************************************
997 Data Table integratedsysteminfo structure
998 ***************************************************************************
1001 struct atom_camera_dphy_timing_param
1003 uint8_t profile_id; // SENSOR_PROFILES
1007 struct atom_camera_dphy_elec_param
1012 struct atom_camera_module_info
1014 uint8_t module_id; // 0: Rear, 1: Front right of user, 2: Front left of user
1015 uint8_t module_name[8];
1016 struct atom_camera_dphy_timing_param timingparam[6]; // Exact number is under estimation and confirmation from sensor vendor
1019 struct atom_camera_flashlight_info
1021 uint8_t flashlight_id; // 0: Rear, 1: Front
1025 struct atom_camera_data
1027 uint32_t versionCode;
1028 struct atom_camera_module_info cameraInfo[3]; // Assuming 3 camera sensors max
1029 struct atom_camera_flashlight_info flashInfo; // Assuming 1 flashlight max
1030 struct atom_camera_dphy_elec_param dphy_param;
1031 uint32_t crc_val; // CRC
1035 struct atom_14nm_dpphy_dvihdmi_tuningset
1037 uint32_t max_symclk_in10khz;
1038 uint8_t encoder_mode; //atom_encode_mode_def, =2: DVI, =3: HDMI mode
1039 uint8_t phy_sel; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf
1040 uint16_t margindeemph; //COMMON_MAR_DEEMPH_NOM[7:0]tx_margin_nom [15:8]deemph_gen1_nom
1041 uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4
1042 uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_en [23:22]tx_binary_ron_code_offset
1043 uint8_t tx_driver_fifty_ohms; //COMMON_ZCALCODE_CTRL[21].tx_driver_fifty_ohms
1044 uint8_t deemph_sel; //MARGIN_DEEMPH_LANE0.DEEMPH_SEL
1047 struct atom_14nm_dpphy_dp_setting{
1048 uint8_t dp_vs_pemph_level; //enum of atom_dp_vs_preemph_def
1049 uint16_t margindeemph; //COMMON_MAR_DEEMPH_NOM[7:0]tx_margin_nom [15:8]deemph_gen1_nom
1050 uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4
1051 uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_en [23:22]tx_binary_ron_code_offset
1054 struct atom_14nm_dpphy_dp_tuningset{
1055 uint8_t phy_sel; // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf
1057 uint16_t table_size; // size of atom_14nm_dpphy_dp_tuningset
1059 struct atom_14nm_dpphy_dp_setting dptuning[10];
1062 struct atom_14nm_dig_transmitter_info_header_v4_0{
1063 struct atom_common_table_header table_header;
1064 uint16_t pcie_phy_tmds_hdmi_macro_settings_offset; // offset of PCIEPhyTMDSHDMIMacroSettingsTbl
1065 uint16_t uniphy_vs_emph_lookup_table_offset; // offset of UniphyVSEmphLookUpTbl
1066 uint16_t uniphy_xbar_settings_table_offset; // offset of UniphyXbarSettingsTbl
1069 struct atom_14nm_combphy_tmds_vs_set
1074 uint16_t common_mar_deemph_nom__margin_deemph_val;
1075 uint8_t common_seldeemph60__deemph_6db_4_val;
1076 uint8_t cmd_bus_global_for_tx_lane0__boostadj_val ;
1077 uint8_t common_zcalcode_ctrl__tx_driver_fifty_ohms_val;
1078 uint8_t margin_deemph_lane0__deemph_sel_val;
1081 struct atom_i2c_reg_info {
1082 uint8_t ucI2cRegIndex;
1083 uint8_t ucI2cRegVal;
1086 struct atom_hdmi_retimer_redriver_set {
1087 uint8_t HdmiSlvAddr;
1089 uint8_t Hdmi6GRegNum;
1090 struct atom_i2c_reg_info HdmiRegSetting[9]; //For non 6G Hz use
1091 struct atom_i2c_reg_info Hdmi6GhzRegSetting[3]; //For 6G Hz use.
1094 struct atom_integrated_system_info_v1_11
1096 struct atom_common_table_header table_header;
1097 uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def
1098 uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def
1099 uint32_t system_config;
1100 uint32_t cpucapinfo;
1101 uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1%
1102 uint16_t gpuclk_ss_type;
1103 uint16_t lvds_ss_percentage; //unit of 0.001%, 1000 mean 1%
1104 uint16_t lvds_ss_rate_10hz;
1105 uint16_t hdmi_ss_percentage; //unit of 0.001%, 1000 mean 1%
1106 uint16_t hdmi_ss_rate_10hz;
1107 uint16_t dvi_ss_percentage; //unit of 0.001%, 1000 mean 1%
1108 uint16_t dvi_ss_rate_10hz;
1109 uint16_t dpphy_override; // bit vector, enum of atom_sysinfo_dpphy_override_def
1110 uint16_t lvds_misc; // enum of atom_sys_info_lvds_misc_def
1111 uint16_t backlight_pwm_hz; // pwm frequency in hz
1112 uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication.
1113 uint8_t umachannelnumber; // number of memory channels
1114 uint8_t pwr_on_digon_to_de; /* all pwr sequence numbers below are in uint of 4ms */
1115 uint8_t pwr_on_de_to_vary_bl;
1116 uint8_t pwr_down_vary_bloff_to_de;
1117 uint8_t pwr_down_de_to_digoff;
1118 uint8_t pwr_off_delay;
1119 uint8_t pwr_on_vary_bl_to_blon;
1120 uint8_t pwr_down_bloff_to_vary_bloff;
1121 uint8_t min_allowed_bl_level;
1122 uint8_t htc_hyst_limit;
1123 uint8_t htc_tmp_limit;
1126 struct atom_external_display_connection_info extdispconninfo;
1127 struct atom_14nm_dpphy_dvihdmi_tuningset dvi_tuningset;
1128 struct atom_14nm_dpphy_dvihdmi_tuningset hdmi_tuningset;
1129 struct atom_14nm_dpphy_dvihdmi_tuningset hdmi6g_tuningset;
1130 struct atom_14nm_dpphy_dp_tuningset dp_tuningset; // rbr 1.62G dp tuning set
1131 struct atom_14nm_dpphy_dp_tuningset dp_hbr3_tuningset; // HBR3 dp tuning set
1132 struct atom_camera_data camera_info;
1133 struct atom_hdmi_retimer_redriver_set dp0_retimer_set; //for DP0
1134 struct atom_hdmi_retimer_redriver_set dp1_retimer_set; //for DP1
1135 struct atom_hdmi_retimer_redriver_set dp2_retimer_set; //for DP2
1136 struct atom_hdmi_retimer_redriver_set dp3_retimer_set; //for DP3
1137 struct atom_14nm_dpphy_dp_tuningset dp_hbr_tuningset; //hbr 2.7G dp tuning set
1138 struct atom_14nm_dpphy_dp_tuningset dp_hbr2_tuningset; //hbr2 5.4G dp turnig set
1139 struct atom_14nm_dpphy_dp_tuningset edp_tuningset; //edp tuning set
1140 uint32_t reserved[66];
1145 enum atom_system_vbiosmisc_def{
1146 INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT = 0x01,
1151 enum atom_system_gpucapinf_def{
1152 SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS = 0x10,
1156 enum atom_sysinfo_dpphy_override_def{
1157 ATOM_ENABLE_DVI_TUNINGSET = 0x01,
1158 ATOM_ENABLE_HDMI_TUNINGSET = 0x02,
1159 ATOM_ENABLE_HDMI6G_TUNINGSET = 0x04,
1160 ATOM_ENABLE_DP_TUNINGSET = 0x08,
1161 ATOM_ENABLE_DP_HBR3_TUNINGSET = 0x10,
1165 enum atom_sys_info_lvds_misc_def
1167 SYS_INFO_LVDS_MISC_888_FPDI_MODE =0x01,
1168 SYS_INFO_LVDS_MISC_888_BPC_MODE =0x04,
1169 SYS_INFO_LVDS_MISC_OVERRIDE_EN =0x08,
1173 //memorytype DMI Type 17 offset 12h - Memory Type
1174 enum atom_dmi_t17_mem_type_def{
1175 OtherMemType = 0x01, ///< Assign 01 to Other
1176 UnknownMemType, ///< Assign 02 to Unknown
1177 DramMemType, ///< Assign 03 to DRAM
1178 EdramMemType, ///< Assign 04 to EDRAM
1179 VramMemType, ///< Assign 05 to VRAM
1180 SramMemType, ///< Assign 06 to SRAM
1181 RamMemType, ///< Assign 07 to RAM
1182 RomMemType, ///< Assign 08 to ROM
1183 FlashMemType, ///< Assign 09 to Flash
1184 EepromMemType, ///< Assign 10 to EEPROM
1185 FepromMemType, ///< Assign 11 to FEPROM
1186 EpromMemType, ///< Assign 12 to EPROM
1187 CdramMemType, ///< Assign 13 to CDRAM
1188 ThreeDramMemType, ///< Assign 14 to 3DRAM
1189 SdramMemType, ///< Assign 15 to SDRAM
1190 SgramMemType, ///< Assign 16 to SGRAM
1191 RdramMemType, ///< Assign 17 to RDRAM
1192 DdrMemType, ///< Assign 18 to DDR
1193 Ddr2MemType, ///< Assign 19 to DDR2
1194 Ddr2FbdimmMemType, ///< Assign 20 to DDR2 FB-DIMM
1195 Ddr3MemType = 0x18, ///< Assign 24 to DDR3
1196 Fbd2MemType, ///< Assign 25 to FBD2
1197 Ddr4MemType, ///< Assign 26 to DDR4
1198 LpDdrMemType, ///< Assign 27 to LPDDR
1199 LpDdr2MemType, ///< Assign 28 to LPDDR2
1200 LpDdr3MemType, ///< Assign 29 to LPDDR3
1201 LpDdr4MemType, ///< Assign 30 to LPDDR4
1205 // this Table is used starting from NL/AM, used by SBIOS and pass the IntegratedSystemInfoTable/PowerPlayInfoTable/SystemCameraInfoTable
1206 struct atom_fusion_system_info_v4
1208 struct atom_integrated_system_info_v1_11 sysinfo; // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition
1209 uint32_t powerplayinfo[256]; // Reserve 1024 bytes space for PowerPlayInfoTable
1214 ***************************************************************************
1215 Data Table gfx_info structure
1216 ***************************************************************************
1219 struct atom_gfx_info_v2_2
1221 struct atom_common_table_header table_header;
1222 uint8_t gfxip_min_ver;
1223 uint8_t gfxip_max_ver;
1224 uint8_t max_shader_engines;
1225 uint8_t max_tile_pipes;
1226 uint8_t max_cu_per_sh;
1227 uint8_t max_sh_per_se;
1228 uint8_t max_backends_per_se;
1229 uint8_t max_texture_channel_caches;
1230 uint32_t regaddr_cp_dma_src_addr;
1231 uint32_t regaddr_cp_dma_src_addr_hi;
1232 uint32_t regaddr_cp_dma_dst_addr;
1233 uint32_t regaddr_cp_dma_dst_addr_hi;
1234 uint32_t regaddr_cp_dma_command;
1235 uint32_t regaddr_cp_status;
1236 uint32_t regaddr_rlc_gpu_clock_32;
1237 uint32_t rlc_gpu_timer_refclk;
1240 struct atom_gfx_info_v2_3 {
1241 struct atom_common_table_header table_header;
1242 uint8_t gfxip_min_ver;
1243 uint8_t gfxip_max_ver;
1244 uint8_t max_shader_engines;
1245 uint8_t max_tile_pipes;
1246 uint8_t max_cu_per_sh;
1247 uint8_t max_sh_per_se;
1248 uint8_t max_backends_per_se;
1249 uint8_t max_texture_channel_caches;
1250 uint32_t regaddr_cp_dma_src_addr;
1251 uint32_t regaddr_cp_dma_src_addr_hi;
1252 uint32_t regaddr_cp_dma_dst_addr;
1253 uint32_t regaddr_cp_dma_dst_addr_hi;
1254 uint32_t regaddr_cp_dma_command;
1255 uint32_t regaddr_cp_status;
1256 uint32_t regaddr_rlc_gpu_clock_32;
1257 uint32_t rlc_gpu_timer_refclk;
1258 uint8_t active_cu_per_sh;
1259 uint8_t active_rb_per_se;
1260 uint16_t gcgoldenoffset;
1261 uint32_t rm21_sram_vmin_value;
1264 struct atom_gfx_info_v2_4
1266 struct atom_common_table_header table_header;
1267 uint8_t gfxip_min_ver;
1268 uint8_t gfxip_max_ver;
1269 uint8_t max_shader_engines;
1271 uint8_t max_cu_per_sh;
1272 uint8_t max_sh_per_se;
1273 uint8_t max_backends_per_se;
1274 uint8_t max_texture_channel_caches;
1275 uint32_t regaddr_cp_dma_src_addr;
1276 uint32_t regaddr_cp_dma_src_addr_hi;
1277 uint32_t regaddr_cp_dma_dst_addr;
1278 uint32_t regaddr_cp_dma_dst_addr_hi;
1279 uint32_t regaddr_cp_dma_command;
1280 uint32_t regaddr_cp_status;
1281 uint32_t regaddr_rlc_gpu_clock_32;
1282 uint32_t rlc_gpu_timer_refclk;
1283 uint8_t active_cu_per_sh;
1284 uint8_t active_rb_per_se;
1285 uint16_t gcgoldenoffset;
1286 uint16_t gc_num_gprs;
1287 uint16_t gc_gsprim_buff_depth;
1288 uint16_t gc_parameter_cache_depth;
1289 uint16_t gc_wave_size;
1290 uint16_t gc_max_waves_per_simd;
1291 uint16_t gc_lds_size;
1292 uint8_t gc_num_max_gs_thds;
1293 uint8_t gc_gs_table_depth;
1294 uint8_t gc_double_offchip_lds_buffer;
1295 uint8_t gc_max_scratch_slots_per_cu;
1296 uint32_t sram_rm_fuses_val;
1297 uint32_t sram_custom_rm_fuses_val;
1301 ***************************************************************************
1302 Data Table smu_info structure
1303 ***************************************************************************
1305 struct atom_smu_info_v3_1
1307 struct atom_common_table_header table_header;
1308 uint8_t smuip_min_ver;
1309 uint8_t smuip_max_ver;
1311 uint8_t gpuclk_ss_mode; // enum of atom_spread_spectrum_mode
1312 uint16_t sclk_ss_percentage;
1313 uint16_t sclk_ss_rate_10hz;
1314 uint16_t gpuclk_ss_percentage; // in unit of 0.001%
1315 uint16_t gpuclk_ss_rate_10hz;
1316 uint32_t core_refclk_10khz;
1317 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid
1318 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
1319 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid
1320 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
1321 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
1322 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
1323 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid
1324 uint8_t fw_ctf_polarity; // GPIO polarity for CTF
1327 struct atom_smu_info_v3_2 {
1328 struct atom_common_table_header table_header;
1329 uint8_t smuip_min_ver;
1330 uint8_t smuip_max_ver;
1332 uint8_t gpuclk_ss_mode;
1333 uint16_t sclk_ss_percentage;
1334 uint16_t sclk_ss_rate_10hz;
1335 uint16_t gpuclk_ss_percentage; // in unit of 0.001%
1336 uint16_t gpuclk_ss_rate_10hz;
1337 uint32_t core_refclk_10khz;
1338 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid
1339 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
1340 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid
1341 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
1342 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
1343 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
1344 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid
1345 uint8_t fw_ctf_polarity; // GPIO polarity for CTF
1346 uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid
1347 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF
1348 uint16_t smugoldenoffset;
1349 uint32_t gpupll_vco_freq_10khz;
1350 uint32_t bootup_smnclk_10khz;
1351 uint32_t bootup_socclk_10khz;
1352 uint32_t bootup_mp0clk_10khz;
1353 uint32_t bootup_mp1clk_10khz;
1354 uint32_t bootup_lclk_10khz;
1355 uint32_t bootup_dcefclk_10khz;
1356 uint32_t ctf_threshold_override_value;
1357 uint32_t reserved[5];
1360 struct atom_smu_info_v3_3 {
1361 struct atom_common_table_header table_header;
1362 uint8_t smuip_min_ver;
1363 uint8_t smuip_max_ver;
1364 uint8_t waflclk_ss_mode;
1365 uint8_t gpuclk_ss_mode;
1366 uint16_t sclk_ss_percentage;
1367 uint16_t sclk_ss_rate_10hz;
1368 uint16_t gpuclk_ss_percentage; // in unit of 0.001%
1369 uint16_t gpuclk_ss_rate_10hz;
1370 uint32_t core_refclk_10khz;
1371 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid
1372 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
1373 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid
1374 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
1375 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
1376 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
1377 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid
1378 uint8_t fw_ctf_polarity; // GPIO polarity for CTF
1379 uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid
1380 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF
1381 uint16_t smugoldenoffset;
1382 uint32_t gpupll_vco_freq_10khz;
1383 uint32_t bootup_smnclk_10khz;
1384 uint32_t bootup_socclk_10khz;
1385 uint32_t bootup_mp0clk_10khz;
1386 uint32_t bootup_mp1clk_10khz;
1387 uint32_t bootup_lclk_10khz;
1388 uint32_t bootup_dcefclk_10khz;
1389 uint32_t ctf_threshold_override_value;
1390 uint32_t syspll3_0_vco_freq_10khz;
1391 uint32_t syspll3_1_vco_freq_10khz;
1392 uint32_t bootup_fclk_10khz;
1393 uint32_t bootup_waflclk_10khz;
1394 uint32_t smu_info_caps;
1395 uint16_t waflclk_ss_percentage; // in unit of 0.001%
1396 uint16_t smuinitoffset;
1401 ***************************************************************************
1402 Data Table smc_dpm_info structure
1403 ***************************************************************************
1405 struct atom_smc_dpm_info_v4_1
1407 struct atom_common_table_header table_header;
1408 uint8_t liquid1_i2c_address;
1409 uint8_t liquid2_i2c_address;
1410 uint8_t vr_i2c_address;
1411 uint8_t plx_i2c_address;
1413 uint8_t liquid_i2c_linescl;
1414 uint8_t liquid_i2c_linesda;
1415 uint8_t vr_i2c_linescl;
1416 uint8_t vr_i2c_linesda;
1418 uint8_t plx_i2c_linescl;
1419 uint8_t plx_i2c_linesda;
1420 uint8_t vrsensorpresent;
1421 uint8_t liquidsensorpresent;
1423 uint16_t maxvoltagestepgfx;
1424 uint16_t maxvoltagestepsoc;
1426 uint8_t vddgfxvrmapping;
1427 uint8_t vddsocvrmapping;
1428 uint8_t vddmem0vrmapping;
1429 uint8_t vddmem1vrmapping;
1431 uint8_t gfxulvphasesheddingmask;
1432 uint8_t soculvphasesheddingmask;
1433 uint8_t padding8_v[2];
1435 uint16_t gfxmaxcurrent;
1437 uint8_t padding_telemetrygfx;
1439 uint16_t socmaxcurrent;
1441 uint8_t padding_telemetrysoc;
1443 uint16_t mem0maxcurrent;
1445 uint8_t padding_telemetrymem0;
1447 uint16_t mem1maxcurrent;
1449 uint8_t padding_telemetrymem1;
1452 uint8_t acdcpolarity;
1454 uint8_t vr0hotpolarity;
1457 uint8_t vr1hotpolarity;
1466 uint8_t pllgfxclkspreadenabled;
1467 uint8_t pllgfxclkspreadpercent;
1468 uint16_t pllgfxclkspreadfreq;
1470 uint8_t uclkspreadenabled;
1471 uint8_t uclkspreadpercent;
1472 uint16_t uclkspreadfreq;
1474 uint8_t socclkspreadenabled;
1475 uint8_t socclkspreadpercent;
1476 uint16_t socclkspreadfreq;
1478 uint8_t acggfxclkspreadenabled;
1479 uint8_t acggfxclkspreadpercent;
1480 uint16_t acggfxclkspreadfreq;
1482 uint8_t Vr2_I2C_address;
1483 uint8_t padding_vr2[3];
1485 uint32_t boardreserved[9];
1489 ***************************************************************************
1490 Data Table smc_dpm_info structure
1491 ***************************************************************************
1493 struct atom_smc_dpm_info_v4_3
1495 struct atom_common_table_header table_header;
1496 uint8_t liquid1_i2c_address;
1497 uint8_t liquid2_i2c_address;
1498 uint8_t vr_i2c_address;
1499 uint8_t plx_i2c_address;
1501 uint8_t liquid_i2c_linescl;
1502 uint8_t liquid_i2c_linesda;
1503 uint8_t vr_i2c_linescl;
1504 uint8_t vr_i2c_linesda;
1506 uint8_t plx_i2c_linescl;
1507 uint8_t plx_i2c_linesda;
1508 uint8_t vrsensorpresent;
1509 uint8_t liquidsensorpresent;
1511 uint16_t maxvoltagestepgfx;
1512 uint16_t maxvoltagestepsoc;
1514 uint8_t vddgfxvrmapping;
1515 uint8_t vddsocvrmapping;
1516 uint8_t vddmem0vrmapping;
1517 uint8_t vddmem1vrmapping;
1519 uint8_t gfxulvphasesheddingmask;
1520 uint8_t soculvphasesheddingmask;
1521 uint8_t externalsensorpresent;
1524 uint16_t gfxmaxcurrent;
1526 uint8_t padding_telemetrygfx;
1528 uint16_t socmaxcurrent;
1530 uint8_t padding_telemetrysoc;
1532 uint16_t mem0maxcurrent;
1534 uint8_t padding_telemetrymem0;
1536 uint16_t mem1maxcurrent;
1538 uint8_t padding_telemetrymem1;
1541 uint8_t acdcpolarity;
1543 uint8_t vr0hotpolarity;
1546 uint8_t vr1hotpolarity;
1555 uint8_t pllgfxclkspreadenabled;
1556 uint8_t pllgfxclkspreadpercent;
1557 uint16_t pllgfxclkspreadfreq;
1559 uint8_t uclkspreadenabled;
1560 uint8_t uclkspreadpercent;
1561 uint16_t uclkspreadfreq;
1563 uint8_t fclkspreadenabled;
1564 uint8_t fclkspreadpercent;
1565 uint16_t fclkspreadfreq;
1567 uint8_t fllgfxclkspreadenabled;
1568 uint8_t fllgfxclkspreadpercent;
1569 uint16_t fllgfxclkspreadfreq;
1571 uint32_t boardreserved[10];
1574 struct smudpm_i2ccontrollerconfig_t {
1576 uint32_t slaveaddress;
1577 uint32_t controllerport;
1578 uint32_t controllername;
1579 uint32_t thermalthrottler;
1580 uint32_t i2cprotocol;
1584 struct atom_smc_dpm_info_v4_4
1586 struct atom_common_table_header table_header;
1587 uint32_t i2c_padding[3];
1589 uint16_t maxvoltagestepgfx;
1590 uint16_t maxvoltagestepsoc;
1592 uint8_t vddgfxvrmapping;
1593 uint8_t vddsocvrmapping;
1594 uint8_t vddmem0vrmapping;
1595 uint8_t vddmem1vrmapping;
1597 uint8_t gfxulvphasesheddingmask;
1598 uint8_t soculvphasesheddingmask;
1599 uint8_t externalsensorpresent;
1602 uint16_t gfxmaxcurrent;
1604 uint8_t padding_telemetrygfx;
1606 uint16_t socmaxcurrent;
1608 uint8_t padding_telemetrysoc;
1610 uint16_t mem0maxcurrent;
1612 uint8_t padding_telemetrymem0;
1614 uint16_t mem1maxcurrent;
1616 uint8_t padding_telemetrymem1;
1620 uint8_t acdcpolarity;
1622 uint8_t vr0hotpolarity;
1625 uint8_t vr1hotpolarity;
1636 uint8_t pllgfxclkspreadenabled;
1637 uint8_t pllgfxclkspreadpercent;
1638 uint16_t pllgfxclkspreadfreq;
1641 uint8_t uclkspreadenabled;
1642 uint8_t uclkspreadpercent;
1643 uint16_t uclkspreadfreq;
1646 uint8_t fclkspreadenabled;
1647 uint8_t fclkspreadpercent;
1648 uint16_t fclkspreadfreq;
1651 uint8_t fllgfxclkspreadenabled;
1652 uint8_t fllgfxclkspreadpercent;
1653 uint16_t fllgfxclkspreadfreq;
1656 struct smudpm_i2ccontrollerconfig_t i2ccontrollers[7];
1659 uint32_t boardreserved[10];
1662 enum smudpm_v4_5_i2ccontrollername_e{
1663 SMC_V4_5_I2C_CONTROLLER_NAME_VR_GFX = 0,
1664 SMC_V4_5_I2C_CONTROLLER_NAME_VR_SOC,
1665 SMC_V4_5_I2C_CONTROLLER_NAME_VR_VDDCI,
1666 SMC_V4_5_I2C_CONTROLLER_NAME_VR_MVDD,
1667 SMC_V4_5_I2C_CONTROLLER_NAME_LIQUID0,
1668 SMC_V4_5_I2C_CONTROLLER_NAME_LIQUID1,
1669 SMC_V4_5_I2C_CONTROLLER_NAME_PLX,
1670 SMC_V4_5_I2C_CONTROLLER_NAME_SPARE,
1671 SMC_V4_5_I2C_CONTROLLER_NAME_COUNT,
1674 enum smudpm_v4_5_i2ccontrollerthrottler_e{
1675 SMC_V4_5_I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0,
1676 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_GFX,
1677 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_SOC,
1678 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_VDDCI,
1679 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_MVDD,
1680 SMC_V4_5_I2C_CONTROLLER_THROTTLER_LIQUID0,
1681 SMC_V4_5_I2C_CONTROLLER_THROTTLER_LIQUID1,
1682 SMC_V4_5_I2C_CONTROLLER_THROTTLER_PLX,
1683 SMC_V4_5_I2C_CONTROLLER_THROTTLER_COUNT,
1686 enum smudpm_v4_5_i2ccontrollerprotocol_e{
1687 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_VR_0,
1688 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_VR_1,
1689 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_TMP_0,
1690 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_TMP_1,
1691 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_SPARE_0,
1692 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_SPARE_1,
1693 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_COUNT,
1696 struct smudpm_i2c_controller_config_v2
1701 uint32_t SlaveAddress;
1702 uint8_t ControllerPort;
1703 uint8_t ControllerName;
1704 uint8_t ThermalThrotter;
1705 uint8_t I2cProtocol;
1708 struct atom_smc_dpm_info_v4_5
1710 struct atom_common_table_header table_header;
1711 // SECTION: BOARD PARAMETERS
1713 struct smudpm_i2c_controller_config_v2 I2cControllers[8];
1715 // SVI2 Board Parameters
1716 uint16_t MaxVoltageStepGfx; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value.
1717 uint16_t MaxVoltageStepSoc; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value.
1719 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields
1720 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields
1721 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields
1722 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields
1724 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
1725 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
1726 uint8_t ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN)
1729 // Telemetry Settings
1730 uint16_t GfxMaxCurrent; // in Amps
1731 uint8_t GfxOffset; // in Amps
1732 uint8_t Padding_TelemetryGfx;
1733 uint16_t SocMaxCurrent; // in Amps
1734 uint8_t SocOffset; // in Amps
1735 uint8_t Padding_TelemetrySoc;
1737 uint16_t Mem0MaxCurrent; // in Amps
1738 uint8_t Mem0Offset; // in Amps
1739 uint8_t Padding_TelemetryMem0;
1741 uint16_t Mem1MaxCurrent; // in Amps
1742 uint8_t Mem1Offset; // in Amps
1743 uint8_t Padding_TelemetryMem1;
1746 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching
1747 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching
1748 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event
1749 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event
1751 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event
1752 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event
1753 uint8_t GthrGpio; // GPIO pin configured for GTHR Event
1754 uint8_t GthrPolarity; // replace GPIO polarity for GTHR
1756 // LED Display Settings
1757 uint8_t LedPin0; // GPIO number for LedPin[0]
1758 uint8_t LedPin1; // GPIO number for LedPin[1]
1759 uint8_t LedPin2; // GPIO number for LedPin[2]
1762 // GFXCLK PLL Spread Spectrum
1763 uint8_t PllGfxclkSpreadEnabled; // on or off
1764 uint8_t PllGfxclkSpreadPercent; // Q4.4
1765 uint16_t PllGfxclkSpreadFreq; // kHz
1767 // GFXCLK DFLL Spread Spectrum
1768 uint8_t DfllGfxclkSpreadEnabled; // on or off
1769 uint8_t DfllGfxclkSpreadPercent; // Q4.4
1770 uint16_t DfllGfxclkSpreadFreq; // kHz
1772 // UCLK Spread Spectrum
1773 uint8_t UclkSpreadEnabled; // on or off
1774 uint8_t UclkSpreadPercent; // Q4.4
1775 uint16_t UclkSpreadFreq; // kHz
1777 // SOCCLK Spread Spectrum
1778 uint8_t SoclkSpreadEnabled; // on or off
1779 uint8_t SocclkSpreadPercent; // Q4.4
1780 uint16_t SocclkSpreadFreq; // kHz
1782 // Total board power
1783 uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power
1784 uint16_t BoardPadding;
1786 // Mvdd Svi2 Div Ratio Setting
1787 uint32_t MvddRatio; // This is used for MVDD Vid workaround. It has 16 fractional bits (Q16.16)
1789 uint32_t BoardReserved[9];
1793 struct atom_smc_dpm_info_v4_6
1795 struct atom_common_table_header table_header;
1796 // section: board parameters
1797 uint32_t i2c_padding[3]; // old i2c control are moved to new area
1799 uint16_t maxvoltagestepgfx; // in mv(q2) max voltage step that smu will request. multiple steps are taken if voltage change exceeds this value.
1800 uint16_t maxvoltagestepsoc; // in mv(q2) max voltage step that smu will request. multiple steps are taken if voltage change exceeds this value.
1802 uint8_t vddgfxvrmapping; // use vr_mapping* bitfields
1803 uint8_t vddsocvrmapping; // use vr_mapping* bitfields
1804 uint8_t vddmemvrmapping; // use vr_mapping* bitfields
1805 uint8_t boardvrmapping; // use vr_mapping* bitfields
1807 uint8_t gfxulvphasesheddingmask; // set this to 1 to set psi0/1 to 1 in ulv mode
1808 uint8_t externalsensorpresent; // external rdi connected to tmon (aka temp in)
1809 uint8_t padding8_v[2];
1811 // telemetry settings
1812 uint16_t gfxmaxcurrent; // in amps
1813 uint8_t gfxoffset; // in amps
1814 uint8_t padding_telemetrygfx;
1816 uint16_t socmaxcurrent; // in amps
1817 uint8_t socoffset; // in amps
1818 uint8_t padding_telemetrysoc;
1820 uint16_t memmaxcurrent; // in amps
1821 uint8_t memoffset; // in amps
1822 uint8_t padding_telemetrymem;
1824 uint16_t boardmaxcurrent; // in amps
1825 uint8_t boardoffset; // in amps
1826 uint8_t padding_telemetryboardinput;
1829 uint8_t vr0hotgpio; // gpio pin configured for vr0 hot event
1830 uint8_t vr0hotpolarity; // gpio polarity for vr0 hot event
1831 uint8_t vr1hotgpio; // gpio pin configured for vr1 hot event
1832 uint8_t vr1hotpolarity; // gpio polarity for vr1 hot event
1834 // gfxclk pll spread spectrum
1835 uint8_t pllgfxclkspreadenabled; // on or off
1836 uint8_t pllgfxclkspreadpercent; // q4.4
1837 uint16_t pllgfxclkspreadfreq; // khz
1839 // uclk spread spectrum
1840 uint8_t uclkspreadenabled; // on or off
1841 uint8_t uclkspreadpercent; // q4.4
1842 uint16_t uclkspreadfreq; // khz
1844 // fclk spread spectrum
1845 uint8_t fclkspreadenabled; // on or off
1846 uint8_t fclkspreadpercent; // q4.4
1847 uint16_t fclkspreadfreq; // khz
1850 // gfxclk fll spread spectrum
1851 uint8_t fllgfxclkspreadenabled; // on or off
1852 uint8_t fllgfxclkspreadpercent; // q4.4
1853 uint16_t fllgfxclkspreadfreq; // khz
1855 // i2c controller structure
1856 struct smudpm_i2c_controller_config_v2 i2ccontrollers[8];
1859 uint32_t memorychannelenabled; // for dram use only, max 32 channels enabled bit mask.
1861 uint8_t drambitwidth; // for dram use only. see dram bit width type defines
1862 uint8_t paddingmem[3];
1864 // total board power
1865 uint16_t totalboardpower; //only needed for tcp estimated case, where tcp = tgp+total board power
1866 uint16_t boardpadding;
1868 // section: xgmi training
1869 uint8_t xgmilinkspeed[4];
1870 uint8_t xgmilinkwidth[4];
1872 uint16_t xgmifclkfreq[4];
1873 uint16_t xgmisocvoltage[4];
1876 uint32_t boardreserved[10];
1880 ***************************************************************************
1881 Data Table asic_profiling_info structure
1882 ***************************************************************************
1884 struct atom_asic_profiling_info_v4_1
1886 struct atom_common_table_header table_header;
1889 uint32_t avfs_meannsigma_acontant0;
1890 uint32_t avfs_meannsigma_acontant1;
1891 uint32_t avfs_meannsigma_acontant2;
1892 uint16_t avfs_meannsigma_dc_tol_sigma;
1893 uint16_t avfs_meannsigma_platform_mean;
1894 uint16_t avfs_meannsigma_platform_sigma;
1895 uint32_t gb_vdroop_table_cksoff_a0;
1896 uint32_t gb_vdroop_table_cksoff_a1;
1897 uint32_t gb_vdroop_table_cksoff_a2;
1898 uint32_t gb_vdroop_table_ckson_a0;
1899 uint32_t gb_vdroop_table_ckson_a1;
1900 uint32_t gb_vdroop_table_ckson_a2;
1901 uint32_t avfsgb_fuse_table_cksoff_m1;
1902 uint32_t avfsgb_fuse_table_cksoff_m2;
1903 uint32_t avfsgb_fuse_table_cksoff_b;
1904 uint32_t avfsgb_fuse_table_ckson_m1;
1905 uint32_t avfsgb_fuse_table_ckson_m2;
1906 uint32_t avfsgb_fuse_table_ckson_b;
1907 uint16_t max_voltage_0_25mv;
1908 uint8_t enable_gb_vdroop_table_cksoff;
1909 uint8_t enable_gb_vdroop_table_ckson;
1910 uint8_t enable_gb_fuse_table_cksoff;
1911 uint8_t enable_gb_fuse_table_ckson;
1912 uint16_t psm_age_comfactor;
1913 uint8_t enable_apply_avfs_cksoff_voltage;
1915 uint32_t dispclk2gfxclk_a;
1916 uint32_t dispclk2gfxclk_b;
1917 uint32_t dispclk2gfxclk_c;
1918 uint32_t pixclk2gfxclk_a;
1919 uint32_t pixclk2gfxclk_b;
1920 uint32_t pixclk2gfxclk_c;
1921 uint32_t dcefclk2gfxclk_a;
1922 uint32_t dcefclk2gfxclk_b;
1923 uint32_t dcefclk2gfxclk_c;
1924 uint32_t phyclk2gfxclk_a;
1925 uint32_t phyclk2gfxclk_b;
1926 uint32_t phyclk2gfxclk_c;
1929 struct atom_asic_profiling_info_v4_2 {
1930 struct atom_common_table_header table_header;
1933 uint32_t avfs_meannsigma_acontant0;
1934 uint32_t avfs_meannsigma_acontant1;
1935 uint32_t avfs_meannsigma_acontant2;
1936 uint16_t avfs_meannsigma_dc_tol_sigma;
1937 uint16_t avfs_meannsigma_platform_mean;
1938 uint16_t avfs_meannsigma_platform_sigma;
1939 uint32_t gb_vdroop_table_cksoff_a0;
1940 uint32_t gb_vdroop_table_cksoff_a1;
1941 uint32_t gb_vdroop_table_cksoff_a2;
1942 uint32_t gb_vdroop_table_ckson_a0;
1943 uint32_t gb_vdroop_table_ckson_a1;
1944 uint32_t gb_vdroop_table_ckson_a2;
1945 uint32_t avfsgb_fuse_table_cksoff_m1;
1946 uint32_t avfsgb_fuse_table_cksoff_m2;
1947 uint32_t avfsgb_fuse_table_cksoff_b;
1948 uint32_t avfsgb_fuse_table_ckson_m1;
1949 uint32_t avfsgb_fuse_table_ckson_m2;
1950 uint32_t avfsgb_fuse_table_ckson_b;
1951 uint16_t max_voltage_0_25mv;
1952 uint8_t enable_gb_vdroop_table_cksoff;
1953 uint8_t enable_gb_vdroop_table_ckson;
1954 uint8_t enable_gb_fuse_table_cksoff;
1955 uint8_t enable_gb_fuse_table_ckson;
1956 uint16_t psm_age_comfactor;
1957 uint8_t enable_apply_avfs_cksoff_voltage;
1959 uint32_t dispclk2gfxclk_a;
1960 uint32_t dispclk2gfxclk_b;
1961 uint32_t dispclk2gfxclk_c;
1962 uint32_t pixclk2gfxclk_a;
1963 uint32_t pixclk2gfxclk_b;
1964 uint32_t pixclk2gfxclk_c;
1965 uint32_t dcefclk2gfxclk_a;
1966 uint32_t dcefclk2gfxclk_b;
1967 uint32_t dcefclk2gfxclk_c;
1968 uint32_t phyclk2gfxclk_a;
1969 uint32_t phyclk2gfxclk_b;
1970 uint32_t phyclk2gfxclk_c;
1971 uint32_t acg_gb_vdroop_table_a0;
1972 uint32_t acg_gb_vdroop_table_a1;
1973 uint32_t acg_gb_vdroop_table_a2;
1974 uint32_t acg_avfsgb_fuse_table_m1;
1975 uint32_t acg_avfsgb_fuse_table_m2;
1976 uint32_t acg_avfsgb_fuse_table_b;
1977 uint8_t enable_acg_gb_vdroop_table;
1978 uint8_t enable_acg_gb_fuse_table;
1979 uint32_t acg_dispclk2gfxclk_a;
1980 uint32_t acg_dispclk2gfxclk_b;
1981 uint32_t acg_dispclk2gfxclk_c;
1982 uint32_t acg_pixclk2gfxclk_a;
1983 uint32_t acg_pixclk2gfxclk_b;
1984 uint32_t acg_pixclk2gfxclk_c;
1985 uint32_t acg_dcefclk2gfxclk_a;
1986 uint32_t acg_dcefclk2gfxclk_b;
1987 uint32_t acg_dcefclk2gfxclk_c;
1988 uint32_t acg_phyclk2gfxclk_a;
1989 uint32_t acg_phyclk2gfxclk_b;
1990 uint32_t acg_phyclk2gfxclk_c;
1994 ***************************************************************************
1995 Data Table multimedia_info structure
1996 ***************************************************************************
1998 struct atom_multimedia_info_v2_1
2000 struct atom_common_table_header table_header;
2001 uint8_t uvdip_min_ver;
2002 uint8_t uvdip_max_ver;
2003 uint8_t vceip_min_ver;
2004 uint8_t vceip_max_ver;
2005 uint16_t uvd_enc_max_input_width_pixels;
2006 uint16_t uvd_enc_max_input_height_pixels;
2007 uint16_t vce_enc_max_input_width_pixels;
2008 uint16_t vce_enc_max_input_height_pixels;
2009 uint32_t uvd_enc_max_bandwidth; // 16x16 pixels/sec, codec independent
2010 uint32_t vce_enc_max_bandwidth; // 16x16 pixels/sec, codec independent
2015 ***************************************************************************
2016 Data Table umc_info structure
2017 ***************************************************************************
2019 struct atom_umc_info_v3_1
2021 struct atom_common_table_header table_header;
2022 uint32_t ucode_version;
2023 uint32_t ucode_rom_startaddr;
2024 uint32_t ucode_length;
2025 uint16_t umc_reg_init_offset;
2026 uint16_t customer_ucode_name_offset;
2027 uint16_t mclk_ss_percentage;
2028 uint16_t mclk_ss_rate_10hz;
2029 uint8_t umcip_min_ver;
2030 uint8_t umcip_max_ver;
2031 uint8_t vram_type; //enum of atom_dgpu_vram_type
2033 uint32_t mem_refclk_10khz;
2036 // umc_info.umc_config
2037 enum atom_umc_config_def {
2038 UMC_CONFIG__ENABLE_1KB_INTERLEAVE_MODE = 0x00000001,
2039 UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE = 0x00000002,
2040 UMC_CONFIG__ENABLE_HBM_LANE_REPAIR = 0x00000004,
2041 UMC_CONFIG__ENABLE_BANK_HARVESTING = 0x00000008,
2042 UMC_CONFIG__ENABLE_PHY_REINIT = 0x00000010,
2043 UMC_CONFIG__DISABLE_UCODE_CHKSTATUS = 0x00000020,
2046 struct atom_umc_info_v3_2
2048 struct atom_common_table_header table_header;
2049 uint32_t ucode_version;
2050 uint32_t ucode_rom_startaddr;
2051 uint32_t ucode_length;
2052 uint16_t umc_reg_init_offset;
2053 uint16_t customer_ucode_name_offset;
2054 uint16_t mclk_ss_percentage;
2055 uint16_t mclk_ss_rate_10hz;
2056 uint8_t umcip_min_ver;
2057 uint8_t umcip_max_ver;
2058 uint8_t vram_type; //enum of atom_dgpu_vram_type
2060 uint32_t mem_refclk_10khz;
2061 uint32_t pstate_uclk_10khz[4];
2062 uint16_t umcgoldenoffset;
2063 uint16_t densitygoldenoffset;
2066 struct atom_umc_info_v3_3
2068 struct atom_common_table_header table_header;
2069 uint32_t ucode_reserved;
2070 uint32_t ucode_rom_startaddr;
2071 uint32_t ucode_length;
2072 uint16_t umc_reg_init_offset;
2073 uint16_t customer_ucode_name_offset;
2074 uint16_t mclk_ss_percentage;
2075 uint16_t mclk_ss_rate_10hz;
2076 uint8_t umcip_min_ver;
2077 uint8_t umcip_max_ver;
2078 uint8_t vram_type; //enum of atom_dgpu_vram_type
2080 uint32_t mem_refclk_10khz;
2081 uint32_t pstate_uclk_10khz[4];
2082 uint16_t umcgoldenoffset;
2083 uint16_t densitygoldenoffset;
2084 uint32_t reserved[4];
2088 ***************************************************************************
2089 Data Table vram_info structure
2090 ***************************************************************************
2092 struct atom_vram_module_v9 {
2093 // Design Specific Values
2094 uint32_t memory_size; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros
2095 uint32_t channel_enable; // bit vector, each bit indicate specific channel enable or not
2096 uint32_t max_mem_clk; // max memory clock of this memory in unit of 10kHz, =0 means it is not defined
2097 uint16_t reserved[3];
2098 uint16_t mem_voltage; // mem_voltage
2099 uint16_t vram_module_size; // Size of atom_vram_module_v9
2100 uint8_t ext_memory_id; // Current memory module ID
2101 uint8_t memory_type; // enum of atom_dgpu_vram_type
2102 uint8_t channel_num; // Number of mem. channels supported in this module
2103 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
2104 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
2105 uint8_t tunningset_id; // MC phy registers set per.
2106 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code
2107 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
2108 uint8_t hbm_ven_rev_id; // hbm_ven_rev_id
2109 uint8_t vram_rsd2; // reserved
2110 char dram_pnstring[20]; // part number end with '0'.
2113 struct atom_vram_info_header_v2_3 {
2114 struct atom_common_table_header table_header;
2115 uint16_t mem_adjust_tbloffset; // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust setting
2116 uint16_t mem_clk_patch_tbloffset; // offset of atom_umc_init_reg_block structure for memory clock specific UMC setting
2117 uint16_t mc_adjust_pertile_tbloffset; // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings
2118 uint16_t mc_phyinit_tbloffset; // offset of atom_umc_init_reg_block structure for MC phy init set
2119 uint16_t dram_data_remap_tbloffset; // reserved for now
2120 uint16_t tmrs_seq_offset; // offset of HBM tmrs
2121 uint16_t post_ucode_init_offset; // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init
2123 uint8_t vram_module_num; // indicate number of VRAM module
2124 uint8_t umcip_min_ver;
2125 uint8_t umcip_max_ver;
2126 uint8_t mc_phy_tile_num; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset
2127 struct atom_vram_module_v9 vram_module[16]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;
2130 struct atom_umc_register_addr_info{
2131 uint32_t umc_register_addr:24;
2132 uint32_t umc_reg_type_ind:1;
2133 uint32_t umc_reg_rsvd:7;
2136 //atom_umc_register_addr_info.
2137 enum atom_umc_register_addr_info_flag{
2138 b3ATOM_UMC_REG_ADD_INFO_INDIRECT_ACCESS =0x01,
2141 union atom_umc_register_addr_info_access
2143 struct atom_umc_register_addr_info umc_reg_addr;
2144 uint32_t u32umc_reg_addr;
2147 struct atom_umc_reg_setting_id_config{
2148 uint32_t memclockrange:24;
2149 uint32_t mem_blk_id:8;
2152 union atom_umc_reg_setting_id_config_access
2154 struct atom_umc_reg_setting_id_config umc_id_access;
2155 uint32_t u32umc_id_access;
2158 struct atom_umc_reg_setting_data_block{
2159 union atom_umc_reg_setting_id_config_access block_id;
2160 uint32_t u32umc_reg_data[1];
2163 struct atom_umc_init_reg_block{
2164 uint16_t umc_reg_num;
2166 union atom_umc_register_addr_info_access umc_reg_list[1]; //for allocation purpose, the real number come from umc_reg_num;
2167 struct atom_umc_reg_setting_data_block umc_reg_setting_list[1];
2170 struct atom_vram_module_v10 {
2171 // Design Specific Values
2172 uint32_t memory_size; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros
2173 uint32_t channel_enable; // bit vector, each bit indicate specific channel enable or not
2174 uint32_t max_mem_clk; // max memory clock of this memory in unit of 10kHz, =0 means it is not defined
2175 uint16_t reserved[3];
2176 uint16_t mem_voltage; // mem_voltage
2177 uint16_t vram_module_size; // Size of atom_vram_module_v9
2178 uint8_t ext_memory_id; // Current memory module ID
2179 uint8_t memory_type; // enum of atom_dgpu_vram_type
2180 uint8_t channel_num; // Number of mem. channels supported in this module
2181 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
2182 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
2183 uint8_t tunningset_id; // MC phy registers set per
2184 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code
2185 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
2186 uint8_t vram_flags; // bit0= bankgroup enable
2187 uint8_t vram_rsd2; // reserved
2188 uint16_t gddr6_mr10; // gddr6 mode register10 value
2189 uint16_t gddr6_mr1; // gddr6 mode register1 value
2190 uint16_t gddr6_mr2; // gddr6 mode register2 value
2191 uint16_t gddr6_mr7; // gddr6 mode register7 value
2192 char dram_pnstring[20]; // part number end with '0'
2195 struct atom_vram_info_header_v2_4 {
2196 struct atom_common_table_header table_header;
2197 uint16_t mem_adjust_tbloffset; // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust setting
2198 uint16_t mem_clk_patch_tbloffset; // offset of atom_umc_init_reg_block structure for memory clock specific UMC setting
2199 uint16_t mc_adjust_pertile_tbloffset; // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings
2200 uint16_t mc_phyinit_tbloffset; // offset of atom_umc_init_reg_block structure for MC phy init set
2201 uint16_t dram_data_remap_tbloffset; // reserved for now
2202 uint16_t reserved; // offset of reserved
2203 uint16_t post_ucode_init_offset; // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init
2205 uint8_t vram_module_num; // indicate number of VRAM module
2206 uint8_t umcip_min_ver;
2207 uint8_t umcip_max_ver;
2208 uint8_t mc_phy_tile_num; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset
2209 struct atom_vram_module_v10 vram_module[16]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;
2213 ***************************************************************************
2214 Data Table voltageobject_info structure
2215 ***************************************************************************
2217 struct atom_i2c_data_entry
2219 uint16_t i2c_reg_index; // i2c register address, can be up to 16bit
2220 uint16_t i2c_reg_data; // i2c register data, can be up to 16bit
2223 struct atom_voltage_object_header_v4{
2224 uint8_t voltage_type; //enum atom_voltage_type
2225 uint8_t voltage_mode; //enum atom_voltage_object_mode
2226 uint16_t object_size; //Size of Object
2229 // atom_voltage_object_header_v4.voltage_mode
2230 enum atom_voltage_object_mode
2232 VOLTAGE_OBJ_GPIO_LUT = 0, //VOLTAGE and GPIO Lookup table ->atom_gpio_voltage_object_v4
2233 VOLTAGE_OBJ_VR_I2C_INIT_SEQ = 3, //VOLTAGE REGULATOR INIT sequece through I2C -> atom_i2c_voltage_object_v4
2234 VOLTAGE_OBJ_PHASE_LUT = 4, //Set Vregulator Phase lookup table ->atom_gpio_voltage_object_v4
2235 VOLTAGE_OBJ_SVID2 = 7, //Indicate voltage control by SVID2 ->atom_svid2_voltage_object_v4
2236 VOLTAGE_OBJ_EVV = 8,
2237 VOLTAGE_OBJ_MERGED_POWER = 9,
2240 struct atom_i2c_voltage_object_v4
2242 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_VR_I2C_INIT_SEQ
2243 uint8_t regulator_id; //Indicate Voltage Regulator Id
2245 uint8_t i2c_slave_addr;
2246 uint8_t i2c_control_offset;
2247 uint8_t i2c_flag; // Bit0: 0 - One byte data; 1 - Two byte data
2248 uint8_t i2c_speed; // =0, use default i2c speed, otherwise use it in unit of kHz.
2249 uint8_t reserved[2];
2250 struct atom_i2c_data_entry i2cdatalut[1]; // end with 0xff
2253 // ATOM_I2C_VOLTAGE_OBJECT_V3.ucVoltageControlFlag
2254 enum atom_i2c_voltage_control_flag
2256 VOLTAGE_DATA_ONE_BYTE = 0,
2257 VOLTAGE_DATA_TWO_BYTE = 1,
2261 struct atom_voltage_gpio_map_lut
2263 uint32_t voltage_gpio_reg_val; // The Voltage ID which is used to program GPIO register
2264 uint16_t voltage_level_mv; // The corresponding Voltage Value, in mV
2267 struct atom_gpio_voltage_object_v4
2269 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_GPIO_LUT or VOLTAGE_OBJ_PHASE_LUT
2270 uint8_t gpio_control_id; // default is 0 which indicate control through CG VID mode
2271 uint8_t gpio_entry_num; // indiate the entry numbers of Votlage/Gpio value Look up table
2272 uint8_t phase_delay_us; // phase delay in unit of micro second
2274 uint32_t gpio_mask_val; // GPIO Mask value
2275 struct atom_voltage_gpio_map_lut voltage_gpio_lut[1];
2278 struct atom_svid2_voltage_object_v4
2280 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_SVID2
2281 uint8_t loadline_psi1; // bit4:0= loadline setting ( Core Loadline trim and offset trim ), bit5=0:PSI1_L disable =1: PSI1_L enable
2282 uint8_t psi0_l_vid_thresd; // VR PSI0_L VID threshold
2283 uint8_t psi0_enable; //
2285 uint8_t telemetry_offset;
2286 uint8_t telemetry_gain;
2290 struct atom_merged_voltage_object_v4
2292 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_MERGED_POWER
2293 uint8_t merged_powerrail_type; //enum atom_voltage_type
2294 uint8_t reserved[3];
2297 union atom_voltage_object_v4{
2298 struct atom_gpio_voltage_object_v4 gpio_voltage_obj;
2299 struct atom_i2c_voltage_object_v4 i2c_voltage_obj;
2300 struct atom_svid2_voltage_object_v4 svid2_voltage_obj;
2301 struct atom_merged_voltage_object_v4 merged_voltage_obj;
2304 struct atom_voltage_objects_info_v4_1
2306 struct atom_common_table_header table_header;
2307 union atom_voltage_object_v4 voltage_object[1]; //Info for Voltage control
2312 ***************************************************************************
2313 All Command Function structure definition
2314 ***************************************************************************
2318 ***************************************************************************
2319 Structures used by asic_init
2320 ***************************************************************************
2323 struct asic_init_engine_parameters
2325 uint32_t sclkfreqin10khz:24;
2326 uint32_t engineflag:8; /* enum atom_asic_init_engine_flag */
2329 struct asic_init_mem_parameters
2331 uint32_t mclkfreqin10khz:24;
2332 uint32_t memflag:8; /* enum atom_asic_init_mem_flag */
2335 struct asic_init_parameters_v2_1
2337 struct asic_init_engine_parameters engineparam;
2338 struct asic_init_mem_parameters memparam;
2341 struct asic_init_ps_allocation_v2_1
2343 struct asic_init_parameters_v2_1 param;
2344 uint32_t reserved[16];
2348 enum atom_asic_init_engine_flag
2350 b3NORMAL_ENGINE_INIT = 0,
2351 b3SRIOV_SKIP_ASIC_INIT = 0x02,
2352 b3SRIOV_LOAD_UCODE = 0x40,
2355 enum atom_asic_init_mem_flag
2357 b3NORMAL_MEM_INIT = 0,
2358 b3DRAM_SELF_REFRESH_EXIT =0x20,
2362 ***************************************************************************
2363 Structures used by setengineclock
2364 ***************************************************************************
2367 struct set_engine_clock_parameters_v2_1
2369 uint32_t sclkfreqin10khz:24;
2370 uint32_t sclkflag:8; /* enum atom_set_engine_mem_clock_flag, */
2371 uint32_t reserved[10];
2374 struct set_engine_clock_ps_allocation_v2_1
2376 struct set_engine_clock_parameters_v2_1 clockinfo;
2377 uint32_t reserved[10];
2381 enum atom_set_engine_mem_clock_flag
2383 b3NORMAL_CHANGE_CLOCK = 0,
2384 b3FIRST_TIME_CHANGE_CLOCK = 0x08,
2385 b3STORE_DPM_TRAINGING = 0x40, //Applicable to memory clock change,when set, it store specific DPM mode training result
2389 ***************************************************************************
2390 Structures used by getengineclock
2391 ***************************************************************************
2393 struct get_engine_clock_parameter
2395 uint32_t sclk_10khz; // current engine speed in 10KHz unit
2400 ***************************************************************************
2401 Structures used by setmemoryclock
2402 ***************************************************************************
2404 struct set_memory_clock_parameters_v2_1
2406 uint32_t mclkfreqin10khz:24;
2407 uint32_t mclkflag:8; /* enum atom_set_engine_mem_clock_flag, */
2408 uint32_t reserved[10];
2411 struct set_memory_clock_ps_allocation_v2_1
2413 struct set_memory_clock_parameters_v2_1 clockinfo;
2414 uint32_t reserved[10];
2419 ***************************************************************************
2420 Structures used by getmemoryclock
2421 ***************************************************************************
2423 struct get_memory_clock_parameter
2425 uint32_t mclk_10khz; // current engine speed in 10KHz unit
2432 ***************************************************************************
2433 Structures used by setvoltage
2434 ***************************************************************************
2437 struct set_voltage_parameters_v1_4
2439 uint8_t voltagetype; /* enum atom_voltage_type */
2440 uint8_t command; /* Indicate action: Set voltage level, enum atom_set_voltage_command */
2441 uint16_t vlevel_mv; /* real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) */
2444 //set_voltage_parameters_v2_1.voltagemode
2445 enum atom_set_voltage_command{
2446 ATOM_SET_VOLTAGE = 0,
2447 ATOM_INIT_VOLTAGE_REGULATOR = 3,
2448 ATOM_SET_VOLTAGE_PHASE = 4,
2449 ATOM_GET_LEAKAGE_ID = 8,
2452 struct set_voltage_ps_allocation_v1_4
2454 struct set_voltage_parameters_v1_4 setvoltageparam;
2455 uint32_t reserved[10];
2460 ***************************************************************************
2461 Structures used by computegpuclockparam
2462 ***************************************************************************
2465 //ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag
2466 enum atom_gpu_clock_type
2468 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK =0x00,
2469 COMPUTE_GPUCLK_INPUT_FLAG_GFXCLK =0x01,
2470 COMPUTE_GPUCLK_INPUT_FLAG_UCLK =0x02,
2473 struct compute_gpu_clock_input_parameter_v1_8
2475 uint32_t gpuclock_10khz:24; //Input= target clock, output = actual clock
2476 uint32_t gpu_clock_type:8; //Input indicate clock type: enum atom_gpu_clock_type
2477 uint32_t reserved[5];
2481 struct compute_gpu_clock_output_parameter_v1_8
2483 uint32_t gpuclock_10khz:24; //Input= target clock, output = actual clock
2484 uint32_t dfs_did:8; //return parameter: DFS divider which is used to program to register directly
2485 uint32_t pll_fb_mult; //Feedback Multiplier, bit 8:0 int, bit 15:12 post_div, bit 31:16 frac
2486 uint32_t pll_ss_fbsmult; // Spread FB Mult: bit 8:0 int, bit 31:16 frac
2487 uint16_t pll_ss_slew_frac;
2488 uint8_t pll_ss_enable;
2490 uint32_t reserved1[2];
2496 ***************************************************************************
2497 Structures used by ReadEfuseValue
2498 ***************************************************************************
2501 struct read_efuse_input_parameters_v3_1
2503 uint16_t efuse_start_index;
2508 // ReadEfuseValue input/output parameter
2509 union read_efuse_value_parameters_v3_1
2511 struct read_efuse_input_parameters_v3_1 efuse_info;
2512 uint32_t efusevalue;
2517 ***************************************************************************
2518 Structures used by getsmuclockinfo
2519 ***************************************************************************
2521 struct atom_get_smu_clock_info_parameters_v3_1
2523 uint8_t syspll_id; // 0= syspll0, 1=syspll1, 2=syspll2
2524 uint8_t clk_id; // atom_smu9_syspll0_clock_id (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ )
2525 uint8_t command; // enum of atom_get_smu_clock_info_command
2526 uint8_t dfsdid; // =0: get DFS DID from register, >0, give DFS divider, (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ )
2529 enum atom_get_smu_clock_info_command
2531 GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ = 0,
2532 GET_SMU_CLOCK_INFO_V3_1_GET_PLLVCO_FREQ = 1,
2533 GET_SMU_CLOCK_INFO_V3_1_GET_PLLREFCLK_FREQ = 2,
2536 enum atom_smu9_syspll0_clock_id
2538 SMU9_SYSPLL0_SMNCLK_ID = 0, // SMNCLK
2539 SMU9_SYSPLL0_SOCCLK_ID = 1, // SOCCLK (FCLK)
2540 SMU9_SYSPLL0_MP0CLK_ID = 2, // MP0CLK
2541 SMU9_SYSPLL0_MP1CLK_ID = 3, // MP1CLK
2542 SMU9_SYSPLL0_LCLK_ID = 4, // LCLK
2543 SMU9_SYSPLL0_DCLK_ID = 5, // DCLK
2544 SMU9_SYSPLL0_VCLK_ID = 6, // VCLK
2545 SMU9_SYSPLL0_ECLK_ID = 7, // ECLK
2546 SMU9_SYSPLL0_DCEFCLK_ID = 8, // DCEFCLK
2547 SMU9_SYSPLL0_DPREFCLK_ID = 10, // DPREFCLK
2548 SMU9_SYSPLL0_DISPCLK_ID = 11, // DISPCLK
2551 enum atom_smu11_syspll_id {
2552 SMU11_SYSPLL0_ID = 0,
2553 SMU11_SYSPLL1_0_ID = 1,
2554 SMU11_SYSPLL1_1_ID = 2,
2555 SMU11_SYSPLL1_2_ID = 3,
2556 SMU11_SYSPLL2_ID = 4,
2557 SMU11_SYSPLL3_0_ID = 5,
2558 SMU11_SYSPLL3_1_ID = 6,
2561 enum atom_smu11_syspll0_clock_id {
2562 SMU11_SYSPLL0_ECLK_ID = 0, // ECLK
2563 SMU11_SYSPLL0_SOCCLK_ID = 1, // SOCCLK
2564 SMU11_SYSPLL0_MP0CLK_ID = 2, // MP0CLK
2565 SMU11_SYSPLL0_DCLK_ID = 3, // DCLK
2566 SMU11_SYSPLL0_VCLK_ID = 4, // VCLK
2567 SMU11_SYSPLL0_DCEFCLK_ID = 5, // DCEFCLK
2570 enum atom_smu11_syspll1_0_clock_id {
2571 SMU11_SYSPLL1_0_UCLKA_ID = 0, // UCLK_a
2574 enum atom_smu11_syspll1_1_clock_id {
2575 SMU11_SYSPLL1_0_UCLKB_ID = 0, // UCLK_b
2578 enum atom_smu11_syspll1_2_clock_id {
2579 SMU11_SYSPLL1_0_FCLK_ID = 0, // FCLK
2582 enum atom_smu11_syspll2_clock_id {
2583 SMU11_SYSPLL2_GFXCLK_ID = 0, // GFXCLK
2586 enum atom_smu11_syspll3_0_clock_id {
2587 SMU11_SYSPLL3_0_WAFCLK_ID = 0, // WAFCLK
2588 SMU11_SYSPLL3_0_DISPCLK_ID = 1, // DISPCLK
2589 SMU11_SYSPLL3_0_DPREFCLK_ID = 2, // DPREFCLK
2592 enum atom_smu11_syspll3_1_clock_id {
2593 SMU11_SYSPLL3_1_MP1CLK_ID = 0, // MP1CLK
2594 SMU11_SYSPLL3_1_SMNCLK_ID = 1, // SMNCLK
2595 SMU11_SYSPLL3_1_LCLK_ID = 2, // LCLK
2598 struct atom_get_smu_clock_info_output_parameters_v3_1
2601 uint32_t smu_clock_freq_hz;
2602 uint32_t syspllvcofreq_10khz;
2603 uint32_t sysspllrefclk_10khz;
2604 }atom_smu_outputclkfreq;
2610 ***************************************************************************
2611 Structures used by dynamicmemorysettings
2612 ***************************************************************************
2615 enum atom_dynamic_memory_setting_command
2617 COMPUTE_MEMORY_PLL_PARAM = 1,
2618 COMPUTE_ENGINE_PLL_PARAM = 2,
2619 ADJUST_MC_SETTING_PARAM = 3,
2622 /* when command = COMPUTE_MEMORY_PLL_PARAM or ADJUST_MC_SETTING_PARAM */
2623 struct dynamic_mclk_settings_parameters_v2_1
2625 uint32_t mclk_10khz:24; //Input= target mclk
2626 uint32_t command:8; //command enum of atom_dynamic_memory_setting_command
2630 /* when command = COMPUTE_ENGINE_PLL_PARAM */
2631 struct dynamic_sclk_settings_parameters_v2_1
2633 uint32_t sclk_10khz:24; //Input= target mclk
2634 uint32_t command:8; //command enum of atom_dynamic_memory_setting_command
2635 uint32_t mclk_10khz;
2639 union dynamic_memory_settings_parameters_v2_1
2641 struct dynamic_mclk_settings_parameters_v2_1 mclk_setting;
2642 struct dynamic_sclk_settings_parameters_v2_1 sclk_setting;
2648 ***************************************************************************
2649 Structures used by memorytraining
2650 ***************************************************************************
2653 enum atom_umc6_0_ucode_function_call_enum_id
2655 UMC60_UCODE_FUNC_ID_REINIT = 0,
2656 UMC60_UCODE_FUNC_ID_ENTER_SELFREFRESH = 1,
2657 UMC60_UCODE_FUNC_ID_EXIT_SELFREFRESH = 2,
2661 struct memory_training_parameters_v2_1
2663 uint8_t ucode_func_id;
2664 uint8_t ucode_reserved[3];
2665 uint32_t reserved[5];
2670 ***************************************************************************
2671 Structures used by setpixelclock
2672 ***************************************************************************
2675 struct set_pixel_clock_parameter_v1_7
2677 uint32_t pixclk_100hz; // target the pixel clock to drive the CRTC timing in unit of 100Hz.
2679 uint8_t pll_id; // ATOM_PHY_PLL0/ATOM_PHY_PLL1/ATOM_PPLL0
2680 uint8_t encoderobjid; // ASIC encoder id defined in objectId.h,
2681 // indicate which graphic encoder will be used.
2682 uint8_t encoder_mode; // Encoder mode:
2683 uint8_t miscinfo; // enum atom_set_pixel_clock_v1_7_misc_info
2684 uint8_t crtc_id; // enum of atom_crtc_def
2685 uint8_t deep_color_ratio; // HDMI panel bit depth: enum atom_set_pixel_clock_v1_7_deepcolor_ratio
2686 uint8_t reserved1[2];
2691 enum atom_set_pixel_clock_v1_7_misc_info
2693 PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL = 0x01,
2694 PIXEL_CLOCK_V7_MISC_PROG_PHYPLL = 0x02,
2695 PIXEL_CLOCK_V7_MISC_YUV420_MODE = 0x04,
2696 PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN = 0x08,
2697 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC = 0x30,
2698 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_XTALIN = 0x00,
2699 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_PCIE = 0x10,
2700 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_GENLK = 0x20,
2701 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_REFPAD = 0x30,
2702 PIXEL_CLOCK_V7_MISC_ATOMIC_UPDATE = 0x40,
2703 PIXEL_CLOCK_V7_MISC_FORCE_SS_DIS = 0x80,
2706 /* deep_color_ratio */
2707 enum atom_set_pixel_clock_v1_7_deepcolor_ratio
2709 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS = 0x00, //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO
2710 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4 = 0x01, //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4
2711 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2 = 0x02, //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2
2712 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1 = 0x03, //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1
2716 ***************************************************************************
2717 Structures used by setdceclock
2718 ***************************************************************************
2721 // SetDCEClock input parameter for DCE11.2( ELM and BF ) and above
2722 struct set_dce_clock_parameters_v2_1
2724 uint32_t dceclk_10khz; // target DCE frequency in unit of 10KHZ, return real DISPCLK/DPREFCLK frequency.
2725 uint8_t dceclktype; // =0: DISPCLK =1: DPREFCLK =2: PIXCLK
2726 uint8_t dceclksrc; // ATOM_PLL0 or ATOM_GCK_DFS or ATOM_FCH_CLK or ATOM_COMBOPHY_PLLx
2727 uint8_t dceclkflag; // Bit [1:0] = PPLL ref clock source ( when ucDCEClkSrc= ATOM_PPLL0 )
2728 uint8_t crtc_id; // ucDisp Pipe Id, ATOM_CRTC0/1/2/..., use only when ucDCEClkType = PIXCLK
2732 enum atom_set_dce_clock_clock_type
2734 DCE_CLOCK_TYPE_DISPCLK = 0,
2735 DCE_CLOCK_TYPE_DPREFCLK = 1,
2736 DCE_CLOCK_TYPE_PIXELCLK = 2, // used by VBIOS internally, called by SetPixelClock
2739 //ucDCEClkFlag when ucDCEClkType == DPREFCLK
2740 enum atom_set_dce_clock_dprefclk_flag
2742 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_MASK = 0x03,
2743 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENERICA = 0x00,
2744 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENLK = 0x01,
2745 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_PCIE = 0x02,
2746 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_XTALIN = 0x03,
2749 //ucDCEClkFlag when ucDCEClkType == PIXCLK
2750 enum atom_set_dce_clock_pixclk_flag
2752 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_MASK = 0x03,
2753 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_DIS = 0x00, //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO
2754 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_5_4 = 0x01, //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4
2755 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_3_2 = 0x02, //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2
2756 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_2_1 = 0x03, //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1
2757 DCE_CLOCK_FLAG_PIXCLK_YUV420_MODE = 0x04,
2760 struct set_dce_clock_ps_allocation_v2_1
2762 struct set_dce_clock_parameters_v2_1 param;
2763 uint32_t ulReserved[2];
2767 /****************************************************************************/
2768 // Structures used by BlankCRTC
2769 /****************************************************************************/
2770 struct blank_crtc_parameters
2772 uint8_t crtc_id; // enum atom_crtc_def
2773 uint8_t blanking; // enum atom_blank_crtc_command
2778 enum atom_blank_crtc_command
2781 ATOM_BLANKING_OFF = 0,
2784 /****************************************************************************/
2785 // Structures used by enablecrtc
2786 /****************************************************************************/
2787 struct enable_crtc_parameters
2789 uint8_t crtc_id; // enum atom_crtc_def
2790 uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE
2795 /****************************************************************************/
2796 // Structure used by EnableDispPowerGating
2797 /****************************************************************************/
2798 struct enable_disp_power_gating_parameters_v2_1
2800 uint8_t disp_pipe_id; // ATOM_CRTC1, ATOM_CRTC2, ...
2801 uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE
2805 struct enable_disp_power_gating_ps_allocation
2807 struct enable_disp_power_gating_parameters_v2_1 param;
2808 uint32_t ulReserved[4];
2811 /****************************************************************************/
2812 // Structure used in setcrtc_usingdtdtiming
2813 /****************************************************************************/
2814 struct set_crtc_using_dtd_timing_parameters
2817 uint16_t h_blanking_time;
2819 uint16_t v_blanking_time;
2820 uint16_t h_syncoffset;
2821 uint16_t h_syncwidth;
2822 uint16_t v_syncoffset;
2823 uint16_t v_syncwidth;
2824 uint16_t modemiscinfo;
2827 uint8_t crtc_id; // enum atom_crtc_def
2828 uint8_t encoder_mode; // atom_encode_mode_def
2833 /****************************************************************************/
2834 // Structures used by processi2cchanneltransaction
2835 /****************************************************************************/
2836 struct process_i2c_channel_transaction_parameters
2838 uint8_t i2cspeed_khz;
2841 uint8_t status; /* enum atom_process_i2c_flag */
2843 uint16_t i2c_data_out;
2844 uint8_t flag; /* enum atom_process_i2c_status */
2845 uint8_t trans_bytes;
2851 enum atom_process_i2c_flag
2855 I2C_2BYTE_ADDR = 0x02,
2856 HW_I2C_SMBUS_BYTE_WR = 0x04,
2860 enum atom_process_i2c_status
2862 HW_ASSISTED_I2C_STATUS_FAILURE =2,
2863 HW_ASSISTED_I2C_STATUS_SUCCESS =1,
2867 /****************************************************************************/
2868 // Structures used by processauxchanneltransaction
2869 /****************************************************************************/
2871 struct process_aux_channel_transaction_parameters_v1_2
2873 uint16_t aux_request;
2877 uint8_t reply_status;
2880 uint8_t dataout_len;
2881 uint8_t hpd_id; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6
2885 /****************************************************************************/
2886 // Structures used by selectcrtc_source
2887 /****************************************************************************/
2889 struct select_crtc_source_parameters_v2_3
2891 uint8_t crtc_id; // enum atom_crtc_def
2892 uint8_t encoder_id; // enum atom_dig_def
2893 uint8_t encode_mode; // enum atom_encode_mode_def
2894 uint8_t dst_bpc; // enum atom_panel_bit_per_color
2898 /****************************************************************************/
2899 // Structures used by digxencodercontrol
2900 /****************************************************************************/
2903 enum atom_dig_encoder_control_action
2905 ATOM_ENCODER_CMD_DISABLE_DIG = 0,
2906 ATOM_ENCODER_CMD_ENABLE_DIG = 1,
2907 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START = 0x08,
2908 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 = 0x09,
2909 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 = 0x0a,
2910 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3 = 0x13,
2911 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE = 0x0b,
2912 ATOM_ENCODER_CMD_DP_VIDEO_OFF = 0x0c,
2913 ATOM_ENCODER_CMD_DP_VIDEO_ON = 0x0d,
2914 ATOM_ENCODER_CMD_SETUP_PANEL_MODE = 0x10,
2915 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN4 = 0x14,
2916 ATOM_ENCODER_CMD_STREAM_SETUP = 0x0F,
2917 ATOM_ENCODER_CMD_LINK_SETUP = 0x11,
2918 ATOM_ENCODER_CMD_ENCODER_BLANK = 0x12,
2921 //define ucPanelMode
2922 enum atom_dig_encoder_control_panelmode
2924 DP_PANEL_MODE_DISABLE = 0x00,
2925 DP_PANEL_MODE_ENABLE_eDP_MODE = 0x01,
2926 DP_PANEL_MODE_ENABLE_LVLINK_MODE = 0x11,
2930 enum atom_dig_encoder_control_v5_digid
2932 ATOM_ENCODER_CONFIG_V5_DIG0_ENCODER = 0x00,
2933 ATOM_ENCODER_CONFIG_V5_DIG1_ENCODER = 0x01,
2934 ATOM_ENCODER_CONFIG_V5_DIG2_ENCODER = 0x02,
2935 ATOM_ENCODER_CONFIG_V5_DIG3_ENCODER = 0x03,
2936 ATOM_ENCODER_CONFIG_V5_DIG4_ENCODER = 0x04,
2937 ATOM_ENCODER_CONFIG_V5_DIG5_ENCODER = 0x05,
2938 ATOM_ENCODER_CONFIG_V5_DIG6_ENCODER = 0x06,
2939 ATOM_ENCODER_CONFIG_V5_DIG7_ENCODER = 0x07,
2942 struct dig_encoder_stream_setup_parameters_v1_5
2944 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
2945 uint8_t action; // = ATOM_ENOCODER_CMD_STREAM_SETUP
2946 uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI
2947 uint8_t lanenum; // Lane number
2948 uint32_t pclk_10khz; // Pixel Clock in 10Khz
2949 uint8_t bitpercolor;
2950 uint8_t dplinkrate_270mhz;//= DP link rate/270Mhz, =6: 1.62G = 10: 2.7G, =20: 5.4Ghz, =30: 8.1Ghz etc
2951 uint8_t reserved[2];
2954 struct dig_encoder_link_setup_parameters_v1_5
2956 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
2957 uint8_t action; // = ATOM_ENOCODER_CMD_LINK_SETUP
2958 uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI
2959 uint8_t lanenum; // Lane number
2960 uint8_t symclk_10khz; // Symbol Clock in 10Khz
2962 uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
2963 uint8_t reserved[2];
2966 struct dp_panel_mode_set_parameters_v1_5
2968 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
2969 uint8_t action; // = ATOM_ENCODER_CMD_DPLINK_SETUP
2970 uint8_t panelmode; // enum atom_dig_encoder_control_panelmode
2972 uint32_t reserved2[2];
2975 struct dig_encoder_generic_cmd_parameters_v1_5
2977 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
2978 uint8_t action; // = rest of generic encoder command which does not carry any parameters
2979 uint8_t reserved1[2];
2980 uint32_t reserved2[2];
2983 union dig_encoder_control_parameters_v1_5
2985 struct dig_encoder_generic_cmd_parameters_v1_5 cmd_param;
2986 struct dig_encoder_stream_setup_parameters_v1_5 stream_param;
2987 struct dig_encoder_link_setup_parameters_v1_5 link_param;
2988 struct dp_panel_mode_set_parameters_v1_5 dppanel_param;
2992 ***************************************************************************
2993 Structures used by dig1transmittercontrol
2994 ***************************************************************************
2996 struct dig_transmitter_control_parameters_v1_6
2998 uint8_t phyid; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF
2999 uint8_t action; // define as ATOM_TRANSMITER_ACTION_xxx
3001 uint8_t digmode; // enum atom_encode_mode_def
3002 uint8_t dplaneset; // DP voltage swing and pre-emphasis value defined in DPCD DP_LANE_SET, "DP_LANE_SET__xDB_y_zV"
3004 uint8_t lanenum; // Lane number 1, 2, 4, 8
3005 uint32_t symclk_10khz; // Symbol Clock in 10Khz
3006 uint8_t hpdsel; // =1: HPD1, =2: HPD2, .... =6: HPD6, =0: HPD is not assigned
3007 uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
3008 uint8_t connobj_id; // Connector Object Id defined in ObjectId.h
3013 struct dig_transmitter_control_ps_allocation_v1_6
3015 struct dig_transmitter_control_parameters_v1_6 param;
3016 uint32_t reserved[4];
3020 enum atom_dig_transmitter_control_action
3022 ATOM_TRANSMITTER_ACTION_DISABLE = 0,
3023 ATOM_TRANSMITTER_ACTION_ENABLE = 1,
3024 ATOM_TRANSMITTER_ACTION_LCD_BLOFF = 2,
3025 ATOM_TRANSMITTER_ACTION_LCD_BLON = 3,
3026 ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL = 4,
3027 ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START = 5,
3028 ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP = 6,
3029 ATOM_TRANSMITTER_ACTION_INIT = 7,
3030 ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT = 8,
3031 ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT = 9,
3032 ATOM_TRANSMITTER_ACTION_SETUP = 10,
3033 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH = 11,
3034 ATOM_TRANSMITTER_ACTION_POWER_ON = 12,
3035 ATOM_TRANSMITTER_ACTION_POWER_OFF = 13,
3039 enum atom_dig_transmitter_control_digfe_sel
3041 ATOM_TRANMSITTER_V6__DIGA_SEL = 0x01,
3042 ATOM_TRANMSITTER_V6__DIGB_SEL = 0x02,
3043 ATOM_TRANMSITTER_V6__DIGC_SEL = 0x04,
3044 ATOM_TRANMSITTER_V6__DIGD_SEL = 0x08,
3045 ATOM_TRANMSITTER_V6__DIGE_SEL = 0x10,
3046 ATOM_TRANMSITTER_V6__DIGF_SEL = 0x20,
3047 ATOM_TRANMSITTER_V6__DIGG_SEL = 0x40,
3052 enum atom_dig_transmitter_control_hpd_sel
3054 ATOM_TRANSMITTER_V6_NO_HPD_SEL = 0x00,
3055 ATOM_TRANSMITTER_V6_HPD1_SEL = 0x01,
3056 ATOM_TRANSMITTER_V6_HPD2_SEL = 0x02,
3057 ATOM_TRANSMITTER_V6_HPD3_SEL = 0x03,
3058 ATOM_TRANSMITTER_V6_HPD4_SEL = 0x04,
3059 ATOM_TRANSMITTER_V6_HPD5_SEL = 0x05,
3060 ATOM_TRANSMITTER_V6_HPD6_SEL = 0x06,
3064 enum atom_dig_transmitter_control_dplaneset
3066 DP_LANE_SET__0DB_0_4V = 0x00,
3067 DP_LANE_SET__0DB_0_6V = 0x01,
3068 DP_LANE_SET__0DB_0_8V = 0x02,
3069 DP_LANE_SET__0DB_1_2V = 0x03,
3070 DP_LANE_SET__3_5DB_0_4V = 0x08,
3071 DP_LANE_SET__3_5DB_0_6V = 0x09,
3072 DP_LANE_SET__3_5DB_0_8V = 0x0a,
3073 DP_LANE_SET__6DB_0_4V = 0x10,
3074 DP_LANE_SET__6DB_0_6V = 0x11,
3075 DP_LANE_SET__9_5DB_0_4V = 0x18,
3080 /****************************************************************************/
3081 // Structures used by ExternalEncoderControl V2.4
3082 /****************************************************************************/
3084 struct external_encoder_control_parameters_v2_4
3086 uint16_t pixelclock_10khz; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT
3087 uint8_t config; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT
3089 uint8_t encodermode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT
3090 uint8_t lanenum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT
3091 uint8_t bitpercolor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP
3097 enum external_encoder_control_action_def
3099 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT = 0x00,
3100 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT = 0x01,
3101 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT = 0x07,
3102 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP = 0x0f,
3103 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF = 0x10,
3104 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING = 0x11,
3105 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION = 0x12,
3106 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP = 0x14,
3110 enum external_encoder_control_v2_4_config_def
3112 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK = 0x03,
3113 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ = 0x00,
3114 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ = 0x01,
3115 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ = 0x02,
3116 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_3_24GHZ = 0x03,
3117 EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MAKS = 0x70,
3118 EXTERNAL_ENCODER_CONFIG_V3_ENCODER1 = 0x00,
3119 EXTERNAL_ENCODER_CONFIG_V3_ENCODER2 = 0x10,
3120 EXTERNAL_ENCODER_CONFIG_V3_ENCODER3 = 0x20,
3123 struct external_encoder_control_ps_allocation_v2_4
3125 struct external_encoder_control_parameters_v2_4 sExtEncoder;
3126 uint32_t reserved[2];
3131 ***************************************************************************
3134 ***************************************************************************
3137 struct amd_acpi_description_header{
3139 uint32_t tableLength; //Length
3143 uint8_t oemTableId[8]; //UINT64 OemTableId;
3144 uint32_t oemRevision;
3146 uint32_t creatorRevision;
3149 struct uefi_acpi_vfct{
3150 struct amd_acpi_description_header sheader;
3151 uint8_t tableUUID[16]; //0x24
3152 uint32_t vbiosimageoffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the stucture.
3153 uint32_t lib1Imageoffset; //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the stucture.
3154 uint32_t reserved[4]; //0x3C
3157 struct vfct_image_header{
3158 uint32_t pcibus; //0x4C
3159 uint32_t pcidevice; //0x50
3160 uint32_t pcifunction; //0x54
3161 uint16_t vendorid; //0x58
3162 uint16_t deviceid; //0x5A
3163 uint16_t ssvid; //0x5C
3164 uint16_t ssid; //0x5E
3165 uint32_t revision; //0x60
3166 uint32_t imagelength; //0x64
3170 struct gop_vbios_content {
3171 struct vfct_image_header vbiosheader;
3172 uint8_t vbioscontent[1];
3175 struct gop_lib1_content {
3176 struct vfct_image_header lib1header;
3177 uint8_t lib1content[1];
3183 ***************************************************************************
3184 Scratch Register definitions
3185 Each number below indicates which scratch regiser request, Active and
3186 Connect all share the same definitions as display_device_tag defines
3187 ***************************************************************************
3190 enum scratch_register_def{
3191 ATOM_DEVICE_CONNECT_INFO_DEF = 0,
3192 ATOM_BL_BRI_LEVEL_INFO_DEF = 2,
3193 ATOM_ACTIVE_INFO_DEF = 3,
3194 ATOM_LCD_INFO_DEF = 4,
3195 ATOM_DEVICE_REQ_INFO_DEF = 5,
3196 ATOM_ACC_CHANGE_INFO_DEF = 6,
3197 ATOM_PRE_OS_MODE_INFO_DEF = 7,
3198 ATOM_PRE_OS_ASSERTION_DEF = 8, //For GOP to record a 32bit assertion code, this is enabled by default in prodution GOP drivers.
3199 ATOM_INTERNAL_TIMER_INFO_DEF = 10,
3202 enum scratch_device_connect_info_bit_def{
3203 ATOM_DISPLAY_LCD1_CONNECT =0x0002,
3204 ATOM_DISPLAY_DFP1_CONNECT =0x0008,
3205 ATOM_DISPLAY_DFP2_CONNECT =0x0080,
3206 ATOM_DISPLAY_DFP3_CONNECT =0x0200,
3207 ATOM_DISPLAY_DFP4_CONNECT =0x0400,
3208 ATOM_DISPLAY_DFP5_CONNECT =0x0800,
3209 ATOM_DISPLAY_DFP6_CONNECT =0x0040,
3210 ATOM_DISPLAY_DFPx_CONNECT =0x0ec8,
3211 ATOM_CONNECT_INFO_DEVICE_MASK =0x0fff,
3214 enum scratch_bl_bri_level_info_bit_def{
3215 ATOM_CURRENT_BL_LEVEL_SHIFT =0x8,
3217 ATOM_CURRENT_BL_LEVEL_MASK =0x0000ff00,
3218 ATOM_DEVICE_DPMS_STATE =0x00010000,
3222 enum scratch_active_info_bits_def{
3223 ATOM_DISPLAY_LCD1_ACTIVE =0x0002,
3224 ATOM_DISPLAY_DFP1_ACTIVE =0x0008,
3225 ATOM_DISPLAY_DFP2_ACTIVE =0x0080,
3226 ATOM_DISPLAY_DFP3_ACTIVE =0x0200,
3227 ATOM_DISPLAY_DFP4_ACTIVE =0x0400,
3228 ATOM_DISPLAY_DFP5_ACTIVE =0x0800,
3229 ATOM_DISPLAY_DFP6_ACTIVE =0x0040,
3230 ATOM_ACTIVE_INFO_DEVICE_MASK =0x0fff,
3233 enum scratch_device_req_info_bits_def{
3234 ATOM_DISPLAY_LCD1_REQ =0x0002,
3235 ATOM_DISPLAY_DFP1_REQ =0x0008,
3236 ATOM_DISPLAY_DFP2_REQ =0x0080,
3237 ATOM_DISPLAY_DFP3_REQ =0x0200,
3238 ATOM_DISPLAY_DFP4_REQ =0x0400,
3239 ATOM_DISPLAY_DFP5_REQ =0x0800,
3240 ATOM_DISPLAY_DFP6_REQ =0x0040,
3241 ATOM_REQ_INFO_DEVICE_MASK =0x0fff,
3244 enum scratch_acc_change_info_bitshift_def{
3245 ATOM_ACC_CHANGE_ACC_MODE_SHIFT =4,
3246 ATOM_ACC_CHANGE_LID_STATUS_SHIFT =6,
3249 enum scratch_acc_change_info_bits_def{
3250 ATOM_ACC_CHANGE_ACC_MODE =0x00000010,
3251 ATOM_ACC_CHANGE_LID_STATUS =0x00000040,
3254 enum scratch_pre_os_mode_info_bits_def{
3255 ATOM_PRE_OS_MODE_MASK =0x00000003,
3256 ATOM_PRE_OS_MODE_VGA =0x00000000,
3257 ATOM_PRE_OS_MODE_VESA =0x00000001,
3258 ATOM_PRE_OS_MODE_GOP =0x00000002,
3259 ATOM_PRE_OS_MODE_PIXEL_DEPTH =0x0000000C,
3260 ATOM_PRE_OS_MODE_PIXEL_FORMAT_MASK=0x000000F0,
3261 ATOM_PRE_OS_MODE_8BIT_PAL_EN =0x00000100,
3262 ATOM_ASIC_INIT_COMPLETE =0x00000200,
3264 ATOM_PRE_OS_MODE_NUMBER_MASK =0xFFFF0000,
3271 ***************************************************************************
3272 ATOM firmware ID header file
3273 !! Please keep it at end of the atomfirmware.h !!
3274 ***************************************************************************
3276 #include "atomfirmwareid.h"