2 * Copyright (C) 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
21 #ifndef _smuio_11_0_0_SH_MASK_HEADER
22 #define _smuio_11_0_0_SH_MASK_HEADER
25 // addressBlock: smuio_smuio_SmuSmuioDec
27 #define SMUSVI0_TEL_PLANE0__SVI0_PLANE0_IDDCOR__SHIFT 0x0
28 #define SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT 0x10
29 #define SMUSVI0_TEL_PLANE0__SVI0_PLANE0_IDDCOR_MASK 0x000000FFL
30 #define SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK 0x01FF0000L
32 #define SMUIO_MCM_CONFIG__DIE_ID__SHIFT 0x0
33 #define SMUIO_MCM_CONFIG__PKG_TYPE__SHIFT 0x2
34 #define SMUIO_MCM_CONFIG__SOCKET_ID__SHIFT 0x5
35 #define SMUIO_MCM_CONFIG__PKG_SUBTYPE__SHIFT 0x6
36 #define SMUIO_MCM_CONFIG__DIE_ID_MASK 0x00000003L
37 #define SMUIO_MCM_CONFIG__PKG_TYPE_MASK 0x0000001CL
38 #define SMUIO_MCM_CONFIG__SOCKET_ID_MASK 0x00000020L
39 #define SMUIO_MCM_CONFIG__PKG_SUBTYPE_MASK 0x000000C0L
41 #define CKSVII2C_IC_CON__IC_MASTER_MODE__SHIFT 0x0
42 #define CKSVII2C_IC_CON__IC_MAX_SPEED_MODE__SHIFT 0x1
43 #define CKSVII2C_IC_CON__IC_10BITADDR_SLAVE__SHIFT 0x3
44 #define CKSVII2C_IC_CON__IC_10BITADDR_MASTER__SHIFT 0x4
45 #define CKSVII2C_IC_CON__IC_RESTART_EN__SHIFT 0x5
46 #define CKSVII2C_IC_CON__IC_SLAVE_DISABLE__SHIFT 0x6
47 #define CKSVII2C_IC_CON__STOP_DET_IFADDRESSED__SHIFT 0x7
48 #define CKSVII2C_IC_CON__TX_EMPTY_CTRL__SHIFT 0x8
49 #define CKSVII2C_IC_CON__RX_FIFO_FULL_HLD_CTRL__SHIFT 0x9
50 #define CKSVII2C_IC_CON__IC_MASTER_MODE_MASK 0x00000001L
51 #define CKSVII2C_IC_CON__IC_MAX_SPEED_MODE_MASK 0x00000006L
52 #define CKSVII2C_IC_CON__IC_10BITADDR_SLAVE_MASK 0x00000008L
53 #define CKSVII2C_IC_CON__IC_10BITADDR_MASTER_MASK 0x00000010L
54 #define CKSVII2C_IC_CON__IC_RESTART_EN_MASK 0x00000020L
55 #define CKSVII2C_IC_CON__IC_SLAVE_DISABLE_MASK 0x00000040L
56 #define CKSVII2C_IC_CON__STOP_DET_IFADDRESSED_MASK 0x00000080L
57 #define CKSVII2C_IC_CON__TX_EMPTY_CTRL_MASK 0x00000100L
58 #define CKSVII2C_IC_CON__RX_FIFO_FULL_HLD_CTRL_MASK 0x00000200L
60 #define CKSVII2C_IC_TAR__IC_TAR__SHIFT 0x0
61 #define CKSVII2C_IC_TAR__GC_OR_START__SHIFT 0xa
62 #define CKSVII2C_IC_TAR__SPECIAL__SHIFT 0xb
63 #define CKSVII2C_IC_TAR__IC_10BITADDR_MASTER__SHIFT 0xc
64 #define CKSVII2C_IC_TAR__IC_TAR_MASK 0x000003FFL
65 #define CKSVII2C_IC_TAR__GC_OR_START_MASK 0x00000400L
66 #define CKSVII2C_IC_TAR__SPECIAL_MASK 0x00000800L
67 #define CKSVII2C_IC_TAR__IC_10BITADDR_MASTER_MASK 0x00001000L
69 #define CKSVII2C_IC_SAR__IC_SAR__SHIFT 0x0
70 #define CKSVII2C_IC_SAR__IC_SAR_MASK 0x000003FFL
71 //CKSVII2C_IC_HS_MADDR
72 #define CKSVII2C_IC_HS_MADDR__IC_HS_MADDR__SHIFT 0x0
73 #define CKSVII2C_IC_HS_MADDR__IC_HS_MADDR_MASK 0x00000007L
74 //CKSVII2C_IC_DATA_CMD
75 #define CKSVII2C_IC_DATA_CMD__DAT__SHIFT 0x0
76 #define CKSVII2C_IC_DATA_CMD__CMD__SHIFT 0x8
77 #define CKSVII2C_IC_DATA_CMD__STOP__SHIFT 0x9
78 #define CKSVII2C_IC_DATA_CMD__RESTART__SHIFT 0xa
79 #define CKSVII2C_IC_DATA_CMD__DAT_MASK 0x000000FFL
80 #define CKSVII2C_IC_DATA_CMD__CMD_MASK 0x00000100L
81 #define CKSVII2C_IC_DATA_CMD__STOP_MASK 0x00000200L
82 #define CKSVII2C_IC_DATA_CMD__RESTART_MASK 0x00000400L
83 //CKSVII2C_IC_SS_SCL_HCNT
84 #define CKSVII2C_IC_SS_SCL_HCNT__IC_SS_SCL_HCNT__SHIFT 0x0
85 #define CKSVII2C_IC_SS_SCL_HCNT__IC_SS_SCL_HCNT_MASK 0x0000FFFFL
86 //CKSVII2C_IC_SS_SCL_LCNT
87 #define CKSVII2C_IC_SS_SCL_LCNT__IC_SS_SCL_LCNT__SHIFT 0x0
88 #define CKSVII2C_IC_SS_SCL_LCNT__IC_SS_SCL_LCNT_MASK 0x0000FFFFL
89 //CKSVII2C_IC_FS_SCL_HCNT
90 #define CKSVII2C_IC_FS_SCL_HCNT__IC_FS_SCL_HCNT__SHIFT 0x0
91 #define CKSVII2C_IC_FS_SCL_HCNT__IC_FS_SCL_HCNT_MASK 0x0000FFFFL
92 //CKSVII2C_IC_FS_SCL_LCNT
93 #define CKSVII2C_IC_FS_SCL_LCNT__IC_FS_SCL_LCNT__SHIFT 0x0
94 #define CKSVII2C_IC_FS_SCL_LCNT__IC_FS_SCL_LCNT_MASK 0x0000FFFFL
95 //CKSVII2C_IC_HS_SCL_HCNT
96 #define CKSVII2C_IC_HS_SCL_HCNT__IC_HS_SCL_HCNT__SHIFT 0x0
97 #define CKSVII2C_IC_HS_SCL_HCNT__IC_HS_SCL_HCNT_MASK 0x0000FFFFL
98 //CKSVII2C_IC_HS_SCL_LCNT
99 #define CKSVII2C_IC_HS_SCL_LCNT__IC_HS_SCL_LCNT__SHIFT 0x0
100 #define CKSVII2C_IC_HS_SCL_LCNT__IC_HS_SCL_LCNT_MASK 0x0000FFFFL
101 //CKSVII2C_IC_INTR_STAT
102 #define CKSVII2C_IC_INTR_STAT__R_RX_UNDER__SHIFT 0x0
103 #define CKSVII2C_IC_INTR_STAT__R_RX_OVER__SHIFT 0x1
104 #define CKSVII2C_IC_INTR_STAT__R_RX_FULL__SHIFT 0x2
105 #define CKSVII2C_IC_INTR_STAT__R_TX_OVER__SHIFT 0x3
106 #define CKSVII2C_IC_INTR_STAT__R_TX_EMPTY__SHIFT 0x4
107 #define CKSVII2C_IC_INTR_STAT__R_RD_REQ__SHIFT 0x5
108 #define CKSVII2C_IC_INTR_STAT__R_TX_ABRT__SHIFT 0x6
109 #define CKSVII2C_IC_INTR_STAT__R_RX_DONE__SHIFT 0x7
110 #define CKSVII2C_IC_INTR_STAT__R_ACTIVITY__SHIFT 0x8
111 #define CKSVII2C_IC_INTR_STAT__R_STOP_DET__SHIFT 0x9
112 #define CKSVII2C_IC_INTR_STAT__R_START_DET__SHIFT 0xa
113 #define CKSVII2C_IC_INTR_STAT__R_GEN_CALL__SHIFT 0xb
114 #define CKSVII2C_IC_INTR_STAT__R_RESTART_DET__SHIFT 0xc
115 #define CKSVII2C_IC_INTR_STAT__R_MST_ON_HOLD__SHIFT 0xd
116 #define CKSVII2C_IC_INTR_STAT__R_RX_UNDER_MASK 0x00000001L
117 #define CKSVII2C_IC_INTR_STAT__R_RX_OVER_MASK 0x00000002L
118 #define CKSVII2C_IC_INTR_STAT__R_RX_FULL_MASK 0x00000004L
119 #define CKSVII2C_IC_INTR_STAT__R_TX_OVER_MASK 0x00000008L
120 #define CKSVII2C_IC_INTR_STAT__R_TX_EMPTY_MASK 0x00000010L
121 #define CKSVII2C_IC_INTR_STAT__R_RD_REQ_MASK 0x00000020L
122 #define CKSVII2C_IC_INTR_STAT__R_TX_ABRT_MASK 0x00000040L
123 #define CKSVII2C_IC_INTR_STAT__R_RX_DONE_MASK 0x00000080L
124 #define CKSVII2C_IC_INTR_STAT__R_ACTIVITY_MASK 0x00000100L
125 #define CKSVII2C_IC_INTR_STAT__R_STOP_DET_MASK 0x00000200L
126 #define CKSVII2C_IC_INTR_STAT__R_START_DET_MASK 0x00000400L
127 #define CKSVII2C_IC_INTR_STAT__R_GEN_CALL_MASK 0x00000800L
128 #define CKSVII2C_IC_INTR_STAT__R_RESTART_DET_MASK 0x00001000L
129 #define CKSVII2C_IC_INTR_STAT__R_MST_ON_HOLD_MASK 0x00002000L
130 //CKSVII2C_IC_INTR_MASK
131 #define CKSVII2C_IC_INTR_MASK__M_RX_UNDER__SHIFT 0x0
132 #define CKSVII2C_IC_INTR_MASK__M_RX_OVER__SHIFT 0x1
133 #define CKSVII2C_IC_INTR_MASK__M_RX_FULL__SHIFT 0x2
134 #define CKSVII2C_IC_INTR_MASK__M_TX_OVER__SHIFT 0x3
135 #define CKSVII2C_IC_INTR_MASK__M_TX_EMPTY__SHIFT 0x4
136 #define CKSVII2C_IC_INTR_MASK__M_RD_REQ__SHIFT 0x5
137 #define CKSVII2C_IC_INTR_MASK__M_TX_ABRT__SHIFT 0x6
138 #define CKSVII2C_IC_INTR_MASK__M_RX_DONE__SHIFT 0x7
139 #define CKSVII2C_IC_INTR_MASK__M_ACTIVITY__SHIFT 0x8
140 #define CKSVII2C_IC_INTR_MASK__M_STOP_DET__SHIFT 0x9
141 #define CKSVII2C_IC_INTR_MASK__M_START_DET__SHIFT 0xa
142 #define CKSVII2C_IC_INTR_MASK__M_GEN_CALL__SHIFT 0xb
143 #define CKSVII2C_IC_INTR_MASK__M_RESTART_DET__SHIFT 0xc
144 #define CKSVII2C_IC_INTR_MASK__M_MST_ON_HOLD__SHIFT 0xd
145 #define CKSVII2C_IC_INTR_MASK__M_RX_UNDER_MASK 0x00000001L
146 #define CKSVII2C_IC_INTR_MASK__M_RX_OVER_MASK 0x00000002L
147 #define CKSVII2C_IC_INTR_MASK__M_RX_FULL_MASK 0x00000004L
148 #define CKSVII2C_IC_INTR_MASK__M_TX_OVER_MASK 0x00000008L
149 #define CKSVII2C_IC_INTR_MASK__M_TX_EMPTY_MASK 0x00000010L
150 #define CKSVII2C_IC_INTR_MASK__M_RD_REQ_MASK 0x00000020L
151 #define CKSVII2C_IC_INTR_MASK__M_TX_ABRT_MASK 0x00000040L
152 #define CKSVII2C_IC_INTR_MASK__M_RX_DONE_MASK 0x00000080L
153 #define CKSVII2C_IC_INTR_MASK__M_ACTIVITY_MASK 0x00000100L
154 #define CKSVII2C_IC_INTR_MASK__M_STOP_DET_MASK 0x00000200L
155 #define CKSVII2C_IC_INTR_MASK__M_START_DET_MASK 0x00000400L
156 #define CKSVII2C_IC_INTR_MASK__M_GEN_CALL_MASK 0x00000800L
157 #define CKSVII2C_IC_INTR_MASK__M_RESTART_DET_MASK 0x00001000L
158 #define CKSVII2C_IC_INTR_MASK__M_MST_ON_HOLD_MASK 0x00002000L
159 //CKSVII2C_IC_RAW_INTR_STAT
160 #define CKSVII2C_IC_RAW_INTR_STAT__R_RX_UNDER__SHIFT 0x0
161 #define CKSVII2C_IC_RAW_INTR_STAT__R_RX_OVER__SHIFT 0x1
162 #define CKSVII2C_IC_RAW_INTR_STAT__R_RX_FULL__SHIFT 0x2
163 #define CKSVII2C_IC_RAW_INTR_STAT__R_TX_OVER__SHIFT 0x3
164 #define CKSVII2C_IC__RAW_INTR_STAT__R_TX_EMPTY__SHIFT 0x4
165 #define CKSVII2C_IC_RAW_INTR_STAT__R_RD_REQ__SHIFT 0x5
166 #define CKSVII2C_IC_RAW_INTR_STAT__R_TX_ABRT__SHIFT 0x6
167 #define CKSVII2C_IC_RAW_INTR_STAT__R_RX_DONE__SHIFT 0x7
168 #define CKSVII2C_IC_RAW_INTR_STAT__R_ACTIVITY__SHIFT 0x8
169 #define CKSVII2C_IC_RAW_INTR_STAT__R_STOP_DET__SHIFT 0x9
170 #define CKSVII2C_IC_RAW_INTR_STAT__R_START_DET__SHIFT 0xa
171 #define CKSVII2C_IC_RAW_INTR_STAT__R_GEN_CALL__SHIFT 0xb
172 #define CKSVII2C_IC_RAW_INTR_STAT__R_RESTART_DET__SHIFT 0xc
173 #define CKSVII2C_IC_RAW_INTR_STAT__R_MST_ON_HOLD__SHIFT 0xd
174 #define CKSVII2C_IC_RAW_INTR_STAT__R_RX_UNDER_MASK 0x00000001L
175 #define CKSVII2C_IC_RAW_INTR_STAT__R_RX_OVER_MASK 0x00000002L
176 #define CKSVII2C_IC_RAW_INTR_STAT__R_RX_FULL_MASK 0x00000004L
177 #define CKSVII2C_IC_RAW_INTR_STAT__R_TX_OVER_MASK 0x00000008L
178 #define CKSVII2C_IC_RAW_INTR_STAT__R_TX_EMPTY_MASK 0x00000010L
179 #define CKSVII2C_IC_RAW_INTR_STAT__R_RD_REQ_MASK 0x00000020L
180 #define CKSVII2C_IC_RAW_INTR_STAT__R_TX_ABRT_MASK 0x00000040L
181 #define CKSVII2C_IC_RAW_INTR_STAT__R_RX_DONE_MASK 0x00000080L
182 #define CKSVII2C_IC_RAW_INTR_STAT__R_ACTIVITY_MASK 0x00000100L
183 #define CKSVII2C_IC_RAW_INTR_STAT__R_STOP_DET_MASK 0x00000200L
184 #define CKSVII2C_IC_RAW_INTR_STAT__R_START_DET_MASK 0x00000400L
185 #define CKSVII2C_IC_RAW_INTR_STAT__R_GEN_CALL_MASK 0x00000800L
186 #define CKSVII2C_IC_RAW_INTR_STAT__R_RESTART_DET_MASK 0x00001000L
187 #define CKSVII2C_IC_RAW_INTR_STAT__R_MST_ON_HOLD_MASK 0x00002000L
190 //CKSVII2C_IC_CLR_INTR
191 //CKSVII2C_IC_CLR_RX_UNDER
192 //CKSVII2C_IC_CLR_RX_OVER
193 //CKSVII2C_IC_CLR_TX_OVER
194 //CKSVII2C_IC_CLR_RD_REQ
195 //CKSVII2C_IC_CLR_TX_ABRT
196 //CKSVII2C_IC_CLR_RX_DONE
197 //CKSVII2C_IC_CLR_ACTIVITY
198 #define CKSVII2C_IC_CLR_ACTIVITY__CLR_ACTIVITY__SHIFT 0x0
199 #define CKSVII2C_IC_CLR_ACTIVITY__CLR_ACTIVITY_MASK 0x00000001L
200 //CKSVII2C_IC_CLR_STOP_DET
201 //CKSVII2C_IC_CLR_START_DET
202 //CKSVII2C_IC_CLR_GEN_CALL
204 #define CKSVII2C_IC_ENABLE__ENABLE__SHIFT 0x0
205 #define CKSVII2C_IC_ENABLE__ABORT__SHIFT 0x1
206 #define CKSVII2C_IC_ENABLE__ENABLE_MASK 0x00000001L
207 #define CKSVII2C_IC_ENABLE__ABORT_MASK 0x00000002L
209 #define CKSVII2C_IC_STATUS__ACTIVITY__SHIFT 0x0
210 #define CKSVII2C_IC_STATUS__TFNF__SHIFT 0x1
211 #define CKSVII2C_IC_STATUS__TFE__SHIFT 0x2
212 #define CKSVII2C_IC_STATUS__RFNE__SHIFT 0x3
213 #define CKSVII2C_IC_STATUS__RFF__SHIFT 0x4
214 #define CKSVII2C_IC_STATUS__MST_ACTIVITY__SHIFT 0x5
215 #define CKSVII2C_IC_STATUS__SLV_ACTIVITY__SHIFT 0x6
216 #define CKSVII2C_IC_STATUS__ACTIVITY_MASK 0x00000001L
217 #define CKSVII2C_IC_STATUS__TFNF_MASK 0x00000002L
218 #define CKSVII2C_IC_STATUS__TFE_MASK 0x00000004L
219 #define CKSVII2C_IC_STATUS__RFNE_MASK 0x00000008L
220 #define CKSVII2C_IC_STATUS__RFF_MASK 0x00000010L
221 #define CKSVII2C_IC_STATUS__MST_ACTIVITY_MASK 0x00000020L
222 #define CKSVII2C_IC_STATUS__SLV_ACTIVITY_MASK 0x00000040L
225 //CKSVII2C_IC_SDA_HOLD
226 #define CKSVII2C_IC_SDA_HOLD__IC_SDA_HOLD__SHIFT 0x0
227 #define CKSVII2C_IC_SDA_HOLD__IC_SDA_HOLD_MASK 0x00FFFFFFL
228 //CKSVII2C_IC_TX_ABRT_SOURCE
230 #define CKSVII2C_IC_TX_ABRT_SOURCE__ABRT_7B_ADDR_NOACK__SHIFT 0x0
231 #define CKSVII2C_IC_TX_ABRT_SOURCE__ABRT_10ADDR1_NOACK__SHIFT 0x1
232 #define CKSVII2C_IC_TX_ABRT_SOURCE__ABRT_10ADDR2_NOACK__SHIFT 0x2
233 #define CKSVII2C_IC_TX_ABRT_SOURCE__ABRT_TXDATA_NOACK__SHIFT 0x3
234 #define CKSVII2C_IC_TX_ABRT_SOURCE__ABRT_7B_ADDR_NOACK_MASK 0x00000001L
235 #define CKSVII2C_IC_TX_ABRT_SOURCE__ABRT_10ADDR1_NOACK_MASK 0x00000002L
236 #define CKSVII2C_IC_TX_ABRT_SOURCE__ABRT_10ADDR2_NOACK_MASK 0x00000004L
237 #define CKSVII2C_IC_TX_ABRT_SOURCE__ABRT_TXDATA_NOACK_MASK 0x00000008L
238 //CKSVII2C_IC_SLV_DATA_NACK_ONLY
240 //CKSVII2C_IC_DMA_TDLR
241 //CKSVII2C_IC_DMA_RDLR
242 //CKSVII2C_IC_SDA_SETUP
243 #define CKSVII2C_IC_SDA_SETUP__SDA_SETUP__SHIFT 0x0
244 #define CKSVII2C_IC_SDA_SETUP__SDA_SETUP_MASK 0x000000FFL
245 //CKSVII2C_IC_ACK_GENERAL_CALL
246 #define CKSVII2C_IC_ACK_GENERAL_CALL__ACK_GENERAL_CALL__SHIFT 0x0
247 #define CKSVII2C_IC_ACK_GENERAL_CALL__ACK_GENERAL_CALL_MASK 0x00000001L
248 //CKSVII2C_IC_ENABLE_STATUS
249 #define CKSVII2C_IC_ENABLE_STATUS__IC_EN__SHIFT 0x0
250 #define CKSVII2C_IC_ENABLE_STATUS__SLV_RX_ABORTED__SHIFT 0x1
251 #define CKSVII2C_IC_ENABLE_STATUS__SLV_FIFO_FILLED_AND_FLUSHED__SHIFT 0x2
252 #define CKSVII2C_IC_ENABLE_STATUS__IC_EN_MASK 0x00000001L
253 #define CKSVII2C_IC_ENABLE_STATUS__SLV_RX_ABORTED_MASK 0x00000002L
254 #define CKSVII2C_IC_ENABLE_STATUS__SLV_FIFO_FILLED_AND_FLUSHED_MASK 0x00000004L
255 //CKSVII2C_IC_FS_SPKLEN
256 #define CKSVII2C_IC_FS_SPKLEN__FS_SPKLEN__SHIFT 0x0
257 #define CKSVII2C_IC_FS_SPKLEN__FS_SPKLEN_MASK 0x000000FFL
258 //CKSVII2C_IC_HS_SPKLEN
259 #define CKSVII2C_IC_HS_SPKLEN__HS_SPKLEN__SHIFT 0x0
260 #define CKSVII2C_IC_HS_SPKLEN__HS_SPKLEN_MASK 0x000000FFL
261 //CKSVII2C_IC_CLR_RESTART_DET
262 //CKSVII2C_IC_COMP_PARAM_1
263 #define CKSVII2C_IC_COMP_PARAM_1__COMP_PARAM_1__SHIFT 0x0
264 #define CKSVII2C_IC_COMP_PARAM_1__COMP_PARAM_1_MASK 0xFFFFFFFFL
265 //CKSVII2C_IC_COMP_VERSION
266 #define CKSVII2C_IC_COMP_VERSION__COMP_VERSION__SHIFT 0x0
267 #define CKSVII2C_IC_COMP_VERSION__COMP_VERSION_MASK 0xFFFFFFFFL
268 //CKSVII2C_IC_COMP_TYPE
269 #define CKSVII2C_IC_COMP_TYPE__COMP_TYPE__SHIFT 0x0
270 #define CKSVII2C_IC_COMP_TYPE__COMP_TYPE_MASK 0xFFFFFFFFL
271 //SMUIO_MP_RESET_INTR
272 #define SMUIO_MP_RESET_INTR__SMUIO_MP_RESET_INTR__SHIFT 0x0
273 #define SMUIO_MP_RESET_INTR__SMUIO_MP_RESET_INTR_MASK 0x00000001L
275 #define SMUIO_SOC_HALT__WDT_FORCE_PWROK_EN__SHIFT 0x2
276 #define SMUIO_SOC_HALT__WDT_FORCE_RESETn_EN__SHIFT 0x3
277 #define SMUIO_SOC_HALT__WDT_FORCE_PWROK_EN_MASK 0x00000004L
278 #define SMUIO_SOC_HALT__WDT_FORCE_RESETn_EN_MASK 0x00000008L
280 #define SMUIO_PWRMGT__i2c_clk_gate_en__SHIFT 0x0
281 #define SMUIO_PWRMGT__i2c1_clk_gate_en__SHIFT 0x4
282 #define SMUIO_PWRMGT__i2c_clk_gate_en_MASK 0x00000001L
283 #define SMUIO_PWRMGT__i2c1_clk_gate_en_MASK 0x00000010L
285 #define ROM_CNTL__CLOCK_GATING_EN__SHIFT 0x0
286 #define ROM_CNTL__SPI_TIMING_RELAX__SHIFT 0x14
287 #define ROM_CNTL__SPI_TIMING_RELAX_OVERRIDE__SHIFT 0x15
288 #define ROM_CNTL__SPI_FAST_MODE__SHIFT 0x16
289 #define ROM_CNTL__SPI_FAST_MODE_OVERRIDE__SHIFT 0x17
290 #define ROM_CNTL__SCK_PRESCALE_REFCLK__SHIFT 0x18
291 #define ROM_CNTL__SCK_PRESCALE_REFCLK_OVERRIDE__SHIFT 0x1c
292 #define ROM_CNTL__CLOCK_GATING_EN_MASK 0x00000001L
293 #define ROM_CNTL__SPI_TIMING_RELAX_MASK 0x00100000L
294 #define ROM_CNTL__SPI_TIMING_RELAX_OVERRIDE_MASK 0x00200000L
295 #define ROM_CNTL__SPI_FAST_MODE_MASK 0x00400000L
296 #define ROM_CNTL__SPI_FAST_MODE_OVERRIDE_MASK 0x00800000L
297 #define ROM_CNTL__SCK_PRESCALE_REFCLK_MASK 0x0F000000L
298 #define ROM_CNTL__SCK_PRESCALE_REFCLK_OVERRIDE_MASK 0x10000000L
300 #define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR__SHIFT 0x0
301 #define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE__SHIFT 0x18
302 #define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE__SHIFT 0x19
303 #define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE__SHIFT 0x1a
304 #define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR_MASK 0x00FFFFFFL
305 #define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE_MASK 0x01000000L
306 #define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE_MASK 0x02000000L
307 #define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE_MASK 0x0C000000L
309 #define ROM_STATUS__ROM_BUSY__SHIFT 0x0
310 #define ROM_STATUS__ROM_BUSY_MASK 0x00000001L
312 #define CGTT_ROM_CLK_CTRL0__ON_DELAY__SHIFT 0x0
313 #define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4
314 #define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e
315 #define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f
316 #define CGTT_ROM_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL
317 #define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L
318 #define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000L
319 #define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000L
321 #define ROM_INDEX__ROM_INDEX__SHIFT 0x0
322 #define ROM_INDEX__ROM_INDEX_MASK 0x00FFFFFFL
324 #define ROM_DATA__ROM_DATA__SHIFT 0x0
325 #define ROM_DATA__ROM_DATA_MASK 0xFFFFFFFFL
327 #define ROM_START__ROM_START__SHIFT 0x0
328 #define ROM_START__ROM_START_MASK 0x00FFFFFFL
330 #define ROM_SW_CNTL__DATA_SIZE__SHIFT 0x0
331 #define ROM_SW_CNTL__COMMAND_SIZE__SHIFT 0x10
332 #define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE__SHIFT 0x12
333 #define ROM_SW_CNTL__DATA_SIZE_MASK 0x0000FFFFL
334 #define ROM_SW_CNTL__COMMAND_SIZE_MASK 0x00030000L
335 #define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE_MASK 0x00040000L
337 #define ROM_SW_STATUS__ROM_SW_DONE__SHIFT 0x0
338 #define ROM_SW_STATUS__ROM_SW_DONE_MASK 0x00000001L
340 #define ROM_SW_COMMAND__ROM_SW_INSTRUCTION__SHIFT 0x0
341 #define ROM_SW_COMMAND__ROM_SW_ADDRESS__SHIFT 0x8
342 #define ROM_SW_COMMAND__ROM_SW_INSTRUCTION_MASK 0x000000FFL
343 #define ROM_SW_COMMAND__ROM_SW_ADDRESS_MASK 0xFFFFFF00L
345 #define ROM_SW_DATA_1__ROM_SW_DATA__SHIFT 0x0
346 #define ROM_SW_DATA_1__ROM_SW_DATA_MASK 0xFFFFFFFFL
348 #define ROM_SW_DATA_2__ROM_SW_DATA__SHIFT 0x0
349 #define ROM_SW_DATA_2__ROM_SW_DATA_MASK 0xFFFFFFFFL
351 #define ROM_SW_DATA_3__ROM_SW_DATA__SHIFT 0x0
352 #define ROM_SW_DATA_3__ROM_SW_DATA_MASK 0xFFFFFFFFL
354 #define ROM_SW_DATA_4__ROM_SW_DATA__SHIFT 0x0
355 #define ROM_SW_DATA_4__ROM_SW_DATA_MASK 0xFFFFFFFFL
357 #define ROM_SW_DATA_5__ROM_SW_DATA__SHIFT 0x0
358 #define ROM_SW_DATA_5__ROM_SW_DATA_MASK 0xFFFFFFFFL
360 #define ROM_SW_DATA_6__ROM_SW_DATA__SHIFT 0x0
361 #define ROM_SW_DATA_6__ROM_SW_DATA_MASK 0xFFFFFFFFL
363 #define ROM_SW_DATA_7__ROM_SW_DATA__SHIFT 0x0
364 #define ROM_SW_DATA_7__ROM_SW_DATA_MASK 0xFFFFFFFFL
366 #define ROM_SW_DATA_8__ROM_SW_DATA__SHIFT 0x0
367 #define ROM_SW_DATA_8__ROM_SW_DATA_MASK 0xFFFFFFFFL
369 #define ROM_SW_DATA_9__ROM_SW_DATA__SHIFT 0x0
370 #define ROM_SW_DATA_9__ROM_SW_DATA_MASK 0xFFFFFFFFL
372 #define ROM_SW_DATA_10__ROM_SW_DATA__SHIFT 0x0
373 #define ROM_SW_DATA_10__ROM_SW_DATA_MASK 0xFFFFFFFFL
375 #define ROM_SW_DATA_11__ROM_SW_DATA__SHIFT 0x0
376 #define ROM_SW_DATA_11__ROM_SW_DATA_MASK 0xFFFFFFFFL
378 #define ROM_SW_DATA_12__ROM_SW_DATA__SHIFT 0x0
379 #define ROM_SW_DATA_12__ROM_SW_DATA_MASK 0xFFFFFFFFL
381 #define ROM_SW_DATA_13__ROM_SW_DATA__SHIFT 0x0
382 #define ROM_SW_DATA_13__ROM_SW_DATA_MASK 0xFFFFFFFFL
384 #define ROM_SW_DATA_14__ROM_SW_DATA__SHIFT 0x0
385 #define ROM_SW_DATA_14__ROM_SW_DATA_MASK 0xFFFFFFFFL
387 #define ROM_SW_DATA_15__ROM_SW_DATA__SHIFT 0x0
388 #define ROM_SW_DATA_15__ROM_SW_DATA_MASK 0xFFFFFFFFL
390 #define ROM_SW_DATA_16__ROM_SW_DATA__SHIFT 0x0
391 #define ROM_SW_DATA_16__ROM_SW_DATA_MASK 0xFFFFFFFFL
393 #define ROM_SW_DATA_17__ROM_SW_DATA__SHIFT 0x0
394 #define ROM_SW_DATA_17__ROM_SW_DATA_MASK 0xFFFFFFFFL
396 #define ROM_SW_DATA_18__ROM_SW_DATA__SHIFT 0x0
397 #define ROM_SW_DATA_18__ROM_SW_DATA_MASK 0xFFFFFFFFL
399 #define ROM_SW_DATA_19__ROM_SW_DATA__SHIFT 0x0
400 #define ROM_SW_DATA_19__ROM_SW_DATA_MASK 0xFFFFFFFFL
402 #define ROM_SW_DATA_20__ROM_SW_DATA__SHIFT 0x0
403 #define ROM_SW_DATA_20__ROM_SW_DATA_MASK 0xFFFFFFFFL
405 #define ROM_SW_DATA_21__ROM_SW_DATA__SHIFT 0x0
406 #define ROM_SW_DATA_21__ROM_SW_DATA_MASK 0xFFFFFFFFL
408 #define ROM_SW_DATA_22__ROM_SW_DATA__SHIFT 0x0
409 #define ROM_SW_DATA_22__ROM_SW_DATA_MASK 0xFFFFFFFFL
411 #define ROM_SW_DATA_23__ROM_SW_DATA__SHIFT 0x0
412 #define ROM_SW_DATA_23__ROM_SW_DATA_MASK 0xFFFFFFFFL
414 #define ROM_SW_DATA_24__ROM_SW_DATA__SHIFT 0x0
415 #define ROM_SW_DATA_24__ROM_SW_DATA_MASK 0xFFFFFFFFL
417 #define ROM_SW_DATA_25__ROM_SW_DATA__SHIFT 0x0
418 #define ROM_SW_DATA_25__ROM_SW_DATA_MASK 0xFFFFFFFFL
420 #define ROM_SW_DATA_26__ROM_SW_DATA__SHIFT 0x0
421 #define ROM_SW_DATA_26__ROM_SW_DATA_MASK 0xFFFFFFFFL
423 #define ROM_SW_DATA_27__ROM_SW_DATA__SHIFT 0x0
424 #define ROM_SW_DATA_27__ROM_SW_DATA_MASK 0xFFFFFFFFL
426 #define ROM_SW_DATA_28__ROM_SW_DATA__SHIFT 0x0
427 #define ROM_SW_DATA_28__ROM_SW_DATA_MASK 0xFFFFFFFFL
429 #define ROM_SW_DATA_29__ROM_SW_DATA__SHIFT 0x0
430 #define ROM_SW_DATA_29__ROM_SW_DATA_MASK 0xFFFFFFFFL
432 #define ROM_SW_DATA_30__ROM_SW_DATA__SHIFT 0x0
433 #define ROM_SW_DATA_30__ROM_SW_DATA_MASK 0xFFFFFFFFL
435 #define ROM_SW_DATA_31__ROM_SW_DATA__SHIFT 0x0
436 #define ROM_SW_DATA_31__ROM_SW_DATA_MASK 0xFFFFFFFFL
438 #define ROM_SW_DATA_32__ROM_SW_DATA__SHIFT 0x0
439 #define ROM_SW_DATA_32__ROM_SW_DATA_MASK 0xFFFFFFFFL
441 #define ROM_SW_DATA_33__ROM_SW_DATA__SHIFT 0x0
442 #define ROM_SW_DATA_33__ROM_SW_DATA_MASK 0xFFFFFFFFL
444 #define ROM_SW_DATA_34__ROM_SW_DATA__SHIFT 0x0
445 #define ROM_SW_DATA_34__ROM_SW_DATA_MASK 0xFFFFFFFFL
447 #define ROM_SW_DATA_35__ROM_SW_DATA__SHIFT 0x0
448 #define ROM_SW_DATA_35__ROM_SW_DATA_MASK 0xFFFFFFFFL
450 #define ROM_SW_DATA_36__ROM_SW_DATA__SHIFT 0x0
451 #define ROM_SW_DATA_36__ROM_SW_DATA_MASK 0xFFFFFFFFL
453 #define ROM_SW_DATA_37__ROM_SW_DATA__SHIFT 0x0
454 #define ROM_SW_DATA_37__ROM_SW_DATA_MASK 0xFFFFFFFFL
456 #define ROM_SW_DATA_38__ROM_SW_DATA__SHIFT 0x0
457 #define ROM_SW_DATA_38__ROM_SW_DATA_MASK 0xFFFFFFFFL
459 #define ROM_SW_DATA_39__ROM_SW_DATA__SHIFT 0x0
460 #define ROM_SW_DATA_39__ROM_SW_DATA_MASK 0xFFFFFFFFL
462 #define ROM_SW_DATA_40__ROM_SW_DATA__SHIFT 0x0
463 #define ROM_SW_DATA_40__ROM_SW_DATA_MASK 0xFFFFFFFFL
465 #define ROM_SW_DATA_41__ROM_SW_DATA__SHIFT 0x0
466 #define ROM_SW_DATA_41__ROM_SW_DATA_MASK 0xFFFFFFFFL
468 #define ROM_SW_DATA_42__ROM_SW_DATA__SHIFT 0x0
469 #define ROM_SW_DATA_42__ROM_SW_DATA_MASK 0xFFFFFFFFL
471 #define ROM_SW_DATA_43__ROM_SW_DATA__SHIFT 0x0
472 #define ROM_SW_DATA_43__ROM_SW_DATA_MASK 0xFFFFFFFFL
474 #define ROM_SW_DATA_44__ROM_SW_DATA__SHIFT 0x0
475 #define ROM_SW_DATA_44__ROM_SW_DATA_MASK 0xFFFFFFFFL
477 #define ROM_SW_DATA_45__ROM_SW_DATA__SHIFT 0x0
478 #define ROM_SW_DATA_45__ROM_SW_DATA_MASK 0xFFFFFFFFL
480 #define ROM_SW_DATA_46__ROM_SW_DATA__SHIFT 0x0
481 #define ROM_SW_DATA_46__ROM_SW_DATA_MASK 0xFFFFFFFFL
483 #define ROM_SW_DATA_47__ROM_SW_DATA__SHIFT 0x0
484 #define ROM_SW_DATA_47__ROM_SW_DATA_MASK 0xFFFFFFFFL
486 #define ROM_SW_DATA_48__ROM_SW_DATA__SHIFT 0x0
487 #define ROM_SW_DATA_48__ROM_SW_DATA_MASK 0xFFFFFFFFL
489 #define ROM_SW_DATA_49__ROM_SW_DATA__SHIFT 0x0
490 #define ROM_SW_DATA_49__ROM_SW_DATA_MASK 0xFFFFFFFFL
492 #define ROM_SW_DATA_50__ROM_SW_DATA__SHIFT 0x0
493 #define ROM_SW_DATA_50__ROM_SW_DATA_MASK 0xFFFFFFFFL
495 #define ROM_SW_DATA_51__ROM_SW_DATA__SHIFT 0x0
496 #define ROM_SW_DATA_51__ROM_SW_DATA_MASK 0xFFFFFFFFL
498 #define ROM_SW_DATA_52__ROM_SW_DATA__SHIFT 0x0
499 #define ROM_SW_DATA_52__ROM_SW_DATA_MASK 0xFFFFFFFFL
501 #define ROM_SW_DATA_53__ROM_SW_DATA__SHIFT 0x0
502 #define ROM_SW_DATA_53__ROM_SW_DATA_MASK 0xFFFFFFFFL
504 #define ROM_SW_DATA_54__ROM_SW_DATA__SHIFT 0x0
505 #define ROM_SW_DATA_54__ROM_SW_DATA_MASK 0xFFFFFFFFL
507 #define ROM_SW_DATA_55__ROM_SW_DATA__SHIFT 0x0
508 #define ROM_SW_DATA_55__ROM_SW_DATA_MASK 0xFFFFFFFFL
510 #define ROM_SW_DATA_56__ROM_SW_DATA__SHIFT 0x0
511 #define ROM_SW_DATA_56__ROM_SW_DATA_MASK 0xFFFFFFFFL
513 #define ROM_SW_DATA_57__ROM_SW_DATA__SHIFT 0x0
514 #define ROM_SW_DATA_57__ROM_SW_DATA_MASK 0xFFFFFFFFL
516 #define ROM_SW_DATA_58__ROM_SW_DATA__SHIFT 0x0
517 #define ROM_SW_DATA_58__ROM_SW_DATA_MASK 0xFFFFFFFFL
519 #define ROM_SW_DATA_59__ROM_SW_DATA__SHIFT 0x0
520 #define ROM_SW_DATA_59__ROM_SW_DATA_MASK 0xFFFFFFFFL
522 #define ROM_SW_DATA_60__ROM_SW_DATA__SHIFT 0x0
523 #define ROM_SW_DATA_60__ROM_SW_DATA_MASK 0xFFFFFFFFL
525 #define ROM_SW_DATA_61__ROM_SW_DATA__SHIFT 0x0
526 #define ROM_SW_DATA_61__ROM_SW_DATA_MASK 0xFFFFFFFFL
528 #define ROM_SW_DATA_62__ROM_SW_DATA__SHIFT 0x0
529 #define ROM_SW_DATA_62__ROM_SW_DATA_MASK 0xFFFFFFFFL
531 #define ROM_SW_DATA_63__ROM_SW_DATA__SHIFT 0x0
532 #define ROM_SW_DATA_63__ROM_SW_DATA_MASK 0xFFFFFFFFL
534 #define ROM_SW_DATA_64__ROM_SW_DATA__SHIFT 0x0
535 #define ROM_SW_DATA_64__ROM_SW_DATA_MASK 0xFFFFFFFFL
536 //SMU_GPIOPAD_SW_INT_STAT
537 #define SMU_GPIOPAD_SW_INT_STAT__SW_INT_STAT__SHIFT 0x0
538 #define SMU_GPIOPAD_SW_INT_STAT__SW_INT_STAT_MASK 0x00000001L
540 #define SMU_GPIOPAD_MASK__GPIO_MASK__SHIFT 0x0
541 #define SMU_GPIOPAD_MASK__GPIO_MASK_MASK 0x7FFFFFFFL
543 #define SMU_GPIOPAD_A__GPIO_A__SHIFT 0x0
544 #define SMU_GPIOPAD_A__GPIO_A_MASK 0x7FFFFFFFL
545 //SMU_GPIOPAD_TXIMPSEL
546 #define SMU_GPIOPAD_TXIMPSEL__GPIO_TXIMPSEL__SHIFT 0x0
547 #define SMU_GPIOPAD_TXIMPSEL__GPIO_TXIMPSEL_MASK 0x7FFFFFFFL
549 #define SMU_GPIOPAD_EN__GPIO_EN__SHIFT 0x0
550 #define SMU_GPIOPAD_EN__GPIO_EN_MASK 0x7FFFFFFFL
552 #define SMU_GPIOPAD_Y__GPIO_Y__SHIFT 0x0
553 #define SMU_GPIOPAD_Y__GPIO_Y_MASK 0x7FFFFFFFL
555 #define SMU_GPIOPAD_RXEN__GPIO_RXEN__SHIFT 0x0
556 #define SMU_GPIOPAD_RXEN__GPIO_RXEN_MASK 0x7FFFFFFFL
557 //SMU_GPIOPAD_RCVR_SEL0
558 #define SMU_GPIOPAD_RCVR_SEL0__GPIO_RCVR_SEL0__SHIFT 0x0
559 #define SMU_GPIOPAD_RCVR_SEL0__GPIO_RCVR_SEL0_MASK 0x7FFFFFFFL
560 //SMU_GPIOPAD_RCVR_SEL1
561 #define SMU_GPIOPAD_RCVR_SEL1__GPIO_RCVR_SEL1__SHIFT 0x0
562 #define SMU_GPIOPAD_RCVR_SEL1__GPIO_RCVR_SEL1_MASK 0x7FFFFFFFL
564 #define SMU_GPIOPAD_PU_EN__GPIO_PU_EN__SHIFT 0x0
565 #define SMU_GPIOPAD_PU_EN__GPIO_PU_EN_MASK 0x7FFFFFFFL
567 #define SMU_GPIOPAD_PD_EN__GPIO_PD_EN__SHIFT 0x0
568 #define SMU_GPIOPAD_PD_EN__GPIO_PD_EN_MASK 0x7FFFFFFFL
569 //SMU_GPIOPAD_PINSTRAPS
570 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0__SHIFT 0x0
571 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1__SHIFT 0x1
572 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2__SHIFT 0x2
573 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3__SHIFT 0x3
574 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4__SHIFT 0x4
575 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5__SHIFT 0x5
576 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6__SHIFT 0x6
577 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7__SHIFT 0x7
578 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8__SHIFT 0x8
579 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9__SHIFT 0x9
580 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10__SHIFT 0xa
581 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11__SHIFT 0xb
582 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12__SHIFT 0xc
583 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13__SHIFT 0xd
584 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14__SHIFT 0xe
585 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15__SHIFT 0xf
586 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16__SHIFT 0x10
587 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17__SHIFT 0x11
588 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18__SHIFT 0x12
589 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19__SHIFT 0x13
590 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20__SHIFT 0x14
591 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21__SHIFT 0x15
592 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22__SHIFT 0x16
593 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23__SHIFT 0x17
594 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24__SHIFT 0x18
595 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25__SHIFT 0x19
596 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26__SHIFT 0x1a
597 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27__SHIFT 0x1b
598 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28__SHIFT 0x1c
599 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29__SHIFT 0x1d
600 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30__SHIFT 0x1e
601 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0_MASK 0x00000001L
602 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1_MASK 0x00000002L
603 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2_MASK 0x00000004L
604 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3_MASK 0x00000008L
605 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4_MASK 0x00000010L
606 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5_MASK 0x00000020L
607 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6_MASK 0x00000040L
608 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7_MASK 0x00000080L
609 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8_MASK 0x00000100L
610 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9_MASK 0x00000200L
611 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10_MASK 0x00000400L
612 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11_MASK 0x00000800L
613 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12_MASK 0x00001000L
614 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13_MASK 0x00002000L
615 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14_MASK 0x00004000L
616 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15_MASK 0x00008000L
617 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16_MASK 0x00010000L
618 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17_MASK 0x00020000L
619 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18_MASK 0x00040000L
620 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19_MASK 0x00080000L
621 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20_MASK 0x00100000L
622 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21_MASK 0x00200000L
623 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22_MASK 0x00400000L
624 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23_MASK 0x00800000L
625 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24_MASK 0x01000000L
626 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25_MASK 0x02000000L
627 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26_MASK 0x04000000L
628 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27_MASK 0x08000000L
629 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28_MASK 0x10000000L
630 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29_MASK 0x20000000L
631 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30_MASK 0x40000000L
633 #define DFT_PINSTRAPS__DFT_PINSTRAPS__SHIFT 0x0
634 #define DFT_PINSTRAPS__DFT_PINSTRAPS_MASK 0x000000FFL
635 //SMU_GPIOPAD_INT_STAT_EN
636 #define SMU_GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN__SHIFT 0x0
637 #define SMU_GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN__SHIFT 0x1f
638 #define SMU_GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN_MASK 0x1FFFFFFFL
639 #define SMU_GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN_MASK 0x80000000L
640 //SMU_GPIOPAD_INT_STAT
641 #define SMU_GPIOPAD_INT_STAT__GPIO_INT_STAT__SHIFT 0x0
642 #define SMU_GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT__SHIFT 0x1f
643 #define SMU_GPIOPAD_INT_STAT__GPIO_INT_STAT_MASK 0x1FFFFFFFL
644 #define SMU_GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT_MASK 0x80000000L
645 //SMU_GPIOPAD_INT_STAT_AK
646 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0__SHIFT 0x0
647 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1__SHIFT 0x1
648 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2__SHIFT 0x2
649 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3__SHIFT 0x3
650 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4__SHIFT 0x4
651 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5__SHIFT 0x5
652 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6__SHIFT 0x6
653 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7__SHIFT 0x7
654 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8__SHIFT 0x8
655 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9__SHIFT 0x9
656 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10__SHIFT 0xa
657 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11__SHIFT 0xb
658 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12__SHIFT 0xc
659 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13__SHIFT 0xd
660 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14__SHIFT 0xe
661 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15__SHIFT 0xf
662 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16__SHIFT 0x10
663 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17__SHIFT 0x11
664 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18__SHIFT 0x12
665 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19__SHIFT 0x13
666 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20__SHIFT 0x14
667 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21__SHIFT 0x15
668 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22__SHIFT 0x16
669 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23__SHIFT 0x17
670 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24__SHIFT 0x18
671 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25__SHIFT 0x19
672 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26__SHIFT 0x1a
673 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27__SHIFT 0x1b
674 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28__SHIFT 0x1c
675 #define SMU_GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK__SHIFT 0x1f
676 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0_MASK 0x00000001L
677 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1_MASK 0x00000002L
678 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2_MASK 0x00000004L
679 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3_MASK 0x00000008L
680 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4_MASK 0x00000010L
681 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5_MASK 0x00000020L
682 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6_MASK 0x00000040L
683 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7_MASK 0x00000080L
684 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8_MASK 0x00000100L
685 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9_MASK 0x00000200L
686 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10_MASK 0x00000400L
687 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11_MASK 0x00000800L
688 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12_MASK 0x00001000L
689 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13_MASK 0x00002000L
690 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14_MASK 0x00004000L
691 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15_MASK 0x00008000L
692 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16_MASK 0x00010000L
693 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17_MASK 0x00020000L
694 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18_MASK 0x00040000L
695 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19_MASK 0x00080000L
696 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20_MASK 0x00100000L
697 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21_MASK 0x00200000L
698 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22_MASK 0x00400000L
699 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23_MASK 0x00800000L
700 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24_MASK 0x01000000L
701 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25_MASK 0x02000000L
702 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26_MASK 0x04000000L
703 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27_MASK 0x08000000L
704 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28_MASK 0x10000000L
705 #define SMU_GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK_MASK 0x80000000L
707 #define SMU_GPIOPAD_INT_EN__GPIO_INT_EN__SHIFT 0x0
708 #define SMU_GPIOPAD_INT_EN__SW_INITIATED_INT_EN__SHIFT 0x1f
709 #define SMU_GPIOPAD_INT_EN__GPIO_INT_EN_MASK 0x1FFFFFFFL
710 #define SMU_GPIOPAD_INT_EN__SW_INITIATED_INT_EN_MASK 0x80000000L
711 //SMU_GPIOPAD_INT_TYPE
712 #define SMU_GPIOPAD_INT_TYPE__GPIO_INT_TYPE__SHIFT 0x0
713 #define SMU_GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE__SHIFT 0x1f
714 #define SMU_GPIOPAD_INT_TYPE__GPIO_INT_TYPE_MASK 0x1FFFFFFFL
715 #define SMU_GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE_MASK 0x80000000L
716 //SMU_GPIOPAD_INT_POLARITY
717 #define SMU_GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY__SHIFT 0x0
718 #define SMU_GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY__SHIFT 0x1f
719 #define SMU_GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY_MASK 0x1FFFFFFFL
720 #define SMU_GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY_MASK 0x80000000L
721 //ROM_CC_BIF_PINSTRAP
722 #define ROM_CC_BIF_PINSTRAP__BIOS_ROM_EN__SHIFT 0x0
723 #define ROM_CC_BIF_PINSTRAP__BIF_MEM_AP_SIZE__SHIFT 0x1
724 #define ROM_CC_BIF_PINSTRAP__ROM_CONFIG__SHIFT 0x4
725 #define ROM_CC_BIF_PINSTRAP__BIF_GEN3_DIS_A__SHIFT 0x7
726 #define ROM_CC_BIF_PINSTRAP__BIF_CLK_PM_EN__SHIFT 0x8
727 #define ROM_CC_BIF_PINSTRAP__BIF_VGA_DIS__SHIFT 0x9
728 #define ROM_CC_BIF_PINSTRAP__BIF_LC_TX_SWING__SHIFT 0xa
729 #define ROM_CC_BIF_PINSTRAP__BIOS_ROM_EN_MASK 0x00000001L
730 #define ROM_CC_BIF_PINSTRAP__BIF_MEM_AP_SIZE_MASK 0x0000000EL
731 #define ROM_CC_BIF_PINSTRAP__ROM_CONFIG_MASK 0x00000070L
732 #define ROM_CC_BIF_PINSTRAP__BIF_GEN3_DIS_A_MASK 0x00000080L
733 #define ROM_CC_BIF_PINSTRAP__BIF_CLK_PM_EN_MASK 0x00000100L
734 #define ROM_CC_BIF_PINSTRAP__BIF_VGA_DIS_MASK 0x00000200L
735 #define ROM_CC_BIF_PINSTRAP__BIF_LC_TX_SWING_MASK 0x00000400L
737 #define IO_SMUIO_PINSTRAP__AUD_PORT_CONN__SHIFT 0x0
738 #define IO_SMUIO_PINSTRAP__AUD__SHIFT 0x3
739 #define IO_SMUIO_PINSTRAP__BOARD_CONFIG__SHIFT 0x5
740 #define IO_SMUIO_PINSTRAP__SMBUS_ADDR__SHIFT 0x8
741 #define IO_SMUIO_PINSTRAP__AUD_PORT_CONN_MASK 0x00000007L
742 #define IO_SMUIO_PINSTRAP__AUD_MASK 0x00000018L
743 #define IO_SMUIO_PINSTRAP__BOARD_CONFIG_MASK 0x000000E0L
744 #define IO_SMUIO_PINSTRAP__SMBUS_ADDR_MASK 0x00000100L
746 #define SMUIO_PCC_CONTROL__PCC_POLARITY__SHIFT 0x0
747 #define SMUIO_PCC_CONTROL__PCC_POLARITY_MASK 0x00000001L
748 //SMUIO_PCC_GPIO_SELECT
749 #define SMUIO_PCC_GPIO_SELECT__GPIO__SHIFT 0x0
750 #define SMUIO_PCC_GPIO_SELECT__GPIO_MASK 0xFFFFFFFFL
751 //SMUIO_GPIO_INT0_SELECT
752 #define SMUIO_GPIO_INT0_SELECT__GPIO_INT0_SELECT__SHIFT 0x0
753 #define SMUIO_GPIO_INT0_SELECT__GPIO_INT0_SELECT_MASK 0xFFFFFFFFL
754 //SMUIO_GPIO_INT1_SELECT
755 #define SMUIO_GPIO_INT1_SELECT__GPIO_INT1_SELECT__SHIFT 0x0
756 #define SMUIO_GPIO_INT1_SELECT__GPIO_INT1_SELECT_MASK 0xFFFFFFFFL
757 //SMUIO_GPIO_INT2_SELECT
758 #define SMUIO_GPIO_INT2_SELECT__GPIO_INT2_SELECT__SHIFT 0x0
759 #define SMUIO_GPIO_INT2_SELECT__GPIO_INT2_SELECT_MASK 0xFFFFFFFFL
760 //SMUIO_GPIO_INT3_SELECT
761 #define SMUIO_GPIO_INT3_SELECT__GPIO_INT3_SELECT__SHIFT 0x0
762 #define SMUIO_GPIO_INT3_SELECT__GPIO_INT3_SELECT_MASK 0xFFFFFFFFL
763 //SMU_GPIOPAD_MP_INT0_STAT
764 #define SMU_GPIOPAD_MP_INT0_STAT__GPIO_MP_INT0_STAT__SHIFT 0x0
765 #define SMU_GPIOPAD_MP_INT0_STAT__GPIO_MP_INT0_STAT_MASK 0x1FFFFFFFL
766 //SMU_GPIOPAD_MP_INT1_STAT
767 #define SMU_GPIOPAD_MP_INT1_STAT__GPIO_MP_INT1_STAT__SHIFT 0x0
768 #define SMU_GPIOPAD_MP_INT1_STAT__GPIO_MP_INT1_STAT_MASK 0x1FFFFFFFL
769 //SMU_GPIOPAD_MP_INT2_STAT
770 #define SMU_GPIOPAD_MP_INT2_STAT__GPIO_MP_INT2_STAT__SHIFT 0x0
771 #define SMU_GPIOPAD_MP_INT2_STAT__GPIO_MP_INT2_STAT_MASK 0x1FFFFFFFL
772 //SMU_GPIOPAD_MP_INT3_STAT
773 #define SMU_GPIOPAD_MP_INT3_STAT__GPIO_MP_INT3_STAT__SHIFT 0x0
774 #define SMU_GPIOPAD_MP_INT3_STAT__GPIO_MP_INT3_STAT_MASK 0x1FFFFFFFL
776 #define SMIO_INDEX__SW_SMIO_INDEX__SHIFT 0x0
777 #define SMIO_INDEX__SW_SMIO_INDEX_MASK 0x00000001L
779 #define S0_VID_SMIO_CNTL__S0_SMIO_VALUES__SHIFT 0x0
780 #define S0_VID_SMIO_CNTL__S0_SMIO_VALUES_MASK 0xFFFFFFFFL
782 #define S1_VID_SMIO_CNTL__S1_SMIO_VALUES__SHIFT 0x0
783 #define S1_VID_SMIO_CNTL__S1_SMIO_VALUES_MASK 0xFFFFFFFFL
785 #define OPEN_DRAIN_SELECT__OPEN_DRAIN_SELECT__SHIFT 0x0
786 #define OPEN_DRAIN_SELECT__RESERVED__SHIFT 0x1f
787 #define OPEN_DRAIN_SELECT__OPEN_DRAIN_SELECT_MASK 0x7FFFFFFFL
788 #define OPEN_DRAIN_SELECT__RESERVED_MASK 0x80000000L
790 #define SMIO_ENABLE__SMIO_ENABLE__SHIFT 0x0
791 #define SMIO_ENABLE__SMIO_ENABLE_MASK 0xFFFFFFFFL
793 #define SMU_GPIOPAD_S0__GPIO_S0__SHIFT 0x0
794 #define SMU_GPIOPAD_S0__GPIO_S0_MASK 0x7FFFFFFFL
796 #define SMU_GPIOPAD_S1__GPIO_S1__SHIFT 0x0
797 #define SMU_GPIOPAD_S1__GPIO_S1_MASK 0x7FFFFFFFL
799 #define SMU_GPIOPAD_SCL_EN__GPIO_SCL_EN__SHIFT 0x0
800 #define SMU_GPIOPAD_SCL_EN__GPIO_SCL_EN_MASK 0x7FFFFFFFL
802 #define SMU_GPIOPAD_SDA_EN__GPIO_SDA_EN__SHIFT 0x0
803 #define SMU_GPIOPAD_SDA_EN__GPIO_SDA_EN_MASK 0x7FFFFFFFL
805 #define SMU_GPIOPAD_SCHMEN__GPIO_SCHMEN__SHIFT 0x0
806 #define SMU_GPIOPAD_SCHMEN__GPIO_SCHMEN_MASK 0x7FFFFFFFL
809 // addressBlock: smuio_smuio_pwr_SmuSmuioDec
810 //IP_DISCOVERY_VERSION
811 #define IP_DISCOVERY_VERSION__IP_DISCOVERY_VERSION__SHIFT 0x0
812 #define IP_DISCOVERY_VERSION__IP_DISCOVERY_VERSION_MASK 0xFFFFFFFFL
814 #define SOC_GAP_PWROK__soc_gap_pwrok__SHIFT 0x0
815 #define SOC_GAP_PWROK__soc_gap_pwrok_MASK 0x00000001L
817 #define GFX_GAP_PWROK__gfx_gap_pwrok__SHIFT 0x0
818 #define GFX_GAP_PWROK__gfx_gap_pwrok_MASK 0x00000001L
819 //PWROK_REFCLK_GAP_CYCLES
820 #define PWROK_REFCLK_GAP_CYCLES__Pwrok_PreAssertion_clkgap_cycles__SHIFT 0x0
821 #define PWROK_REFCLK_GAP_CYCLES__Pwrok_PostAssertion_clkgap_cycles__SHIFT 0x8
822 #define PWROK_REFCLK_GAP_CYCLES__Pwrok_PreAssertion_clkgap_cycles_MASK 0x000000FFL
823 #define PWROK_REFCLK_GAP_CYCLES__Pwrok_PostAssertion_clkgap_cycles_MASK 0x0000FF00L
824 //GOLDEN_TSC_INCREMENT_UPPER
825 #define GOLDEN_TSC_INCREMENT_UPPER__GoldenTscIncrementUpper__SHIFT 0x0
826 #define GOLDEN_TSC_INCREMENT_UPPER__GoldenTscIncrementUpper_MASK 0x00FFFFFFL
827 //GOLDEN_TSC_INCREMENT_LOWER
828 #define GOLDEN_TSC_INCREMENT_LOWER__GoldenTscIncrementLower__SHIFT 0x0
829 #define GOLDEN_TSC_INCREMENT_LOWER__GoldenTscIncrementLower_MASK 0xFFFFFFFFL
830 //GOLDEN_TSC_COUNT_UPPER
831 #define GOLDEN_TSC_COUNT_UPPER__GoldenTscCountUpper__SHIFT 0x0
832 #define GOLDEN_TSC_COUNT_UPPER__GoldenTscCountUpper_MASK 0x00FFFFFFL
833 //GOLDEN_TSC_COUNT_LOWER
834 #define GOLDEN_TSC_COUNT_LOWER__GoldenTscCountLower__SHIFT 0x0
835 #define GOLDEN_TSC_COUNT_LOWER__GoldenTscCountLower_MASK 0xFFFFFFFFL
836 //SOC_GOLDEN_TSC_SHADOW_UPPER
837 #define SOC_GOLDEN_TSC_SHADOW_UPPER__SOCGoldenTscShadowUpper__SHIFT 0x0
838 #define SOC_GOLDEN_TSC_SHADOW_UPPER__SOCGoldenTscShadowUpper_MASK 0x00FFFFFFL
839 //SOC_GOLDEN_TSC_SHADOW_LOWER
840 #define SOC_GOLDEN_TSC_SHADOW_LOWER__SOCGoldenTscShadowLower__SHIFT 0x0
841 #define SOC_GOLDEN_TSC_SHADOW_LOWER__SOCGoldenTscShadowLower_MASK 0xFFFFFFFFL
842 //GFX_GOLDEN_TSC_SHADOW_UPPER
843 #define GFX_GOLDEN_TSC_SHADOW_UPPER__GFXGoldenTscShadowUpper__SHIFT 0x0
844 #define GFX_GOLDEN_TSC_SHADOW_UPPER__GFXGoldenTscShadowUpper_MASK 0x00FFFFFFL
845 //GFX_GOLDEN_TSC_SHADOW_LOWER
846 #define GFX_GOLDEN_TSC_SHADOW_LOWER__GFXGoldenTscShadowLower__SHIFT 0x0
847 #define GFX_GOLDEN_TSC_SHADOW_LOWER__GFXGoldenTscShadowLower_MASK 0xFFFFFFFFL
849 #define PWR_VIRT_RESET_REQ__VF_FLR__SHIFT 0x0
850 #define PWR_VIRT_RESET_REQ__PF_FLR__SHIFT 0x1f
851 #define PWR_VIRT_RESET_REQ__VF_FLR_MASK 0x7FFFFFFFL
852 #define PWR_VIRT_RESET_REQ__PF_FLR_MASK 0x80000000L
854 #define SCRATCH_REGISTER0__ScratchPad0__SHIFT 0x0
855 #define SCRATCH_REGISTER0__ScratchPad0_MASK 0xFFFFFFFFL
857 #define SCRATCH_REGISTER1__ScratchPad1__SHIFT 0x0
858 #define SCRATCH_REGISTER1__ScratchPad1_MASK 0xFFFFFFFFL
860 #define SCRATCH_REGISTER2__ScratchPad2__SHIFT 0x0
861 #define SCRATCH_REGISTER2__ScratchPad2_MASK 0xFFFFFFFFL
863 #define SCRATCH_REGISTER3__ScratchPad3__SHIFT 0x0
864 #define SCRATCH_REGISTER3__ScratchPad3_MASK 0xFFFFFFFFL
866 #define SCRATCH_REGISTER4__ScratchPad4__SHIFT 0x0
867 #define SCRATCH_REGISTER4__ScratchPad4_MASK 0xFFFFFFFFL
869 #define SCRATCH_REGISTER5__ScratchPad5__SHIFT 0x0
870 #define SCRATCH_REGISTER5__ScratchPad5_MASK 0xFFFFFFFFL
872 #define SCRATCH_REGISTER6__ScratchPad6__SHIFT 0x0
873 #define SCRATCH_REGISTER6__ScratchPad6_MASK 0xFFFFFFFFL
875 #define SCRATCH_REGISTER7__ScratchPad7__SHIFT 0x0
876 #define SCRATCH_REGISTER7__ScratchPad7_MASK 0xFFFFFFFFL
877 //PWR_DISP_TIMER_CONTROL
878 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
879 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
880 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE__SHIFT 0x1a
881 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
882 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1c
883 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_TYPE__SHIFT 0x1d
884 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MODE__SHIFT 0x1e
885 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x01FFFFFFL
886 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x02000000L
887 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE_MASK 0x04000000L
888 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK_MASK 0x08000000L
889 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x10000000L
890 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_TYPE_MASK 0x20000000L
891 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MODE_MASK 0x40000000L
892 //PWR_DISP_TIMER2_CONTROL
893 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
894 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
895 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_DISABLE__SHIFT 0x1a
896 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
897 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1c
898 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_TYPE__SHIFT 0x1d
899 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MODE__SHIFT 0x1e
900 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x01FFFFFFL
901 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x02000000L
902 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_DISABLE_MASK 0x04000000L
903 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MASK_MASK 0x08000000L
904 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x10000000L
905 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_TYPE_MASK 0x20000000L
906 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MODE_MASK 0x40000000L
907 //PWR_DISP_TIMER_GLOBAL_CONTROL
908 #define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_WIDTH__SHIFT 0x0
909 #define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_EN__SHIFT 0xa
910 #define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_WIDTH_MASK 0x000003FFL
911 #define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_EN_MASK 0x00000400L
913 #define PWR_IH_CONTROL__MAX_CREDIT__SHIFT 0x0
914 #define PWR_IH_CONTROL__DISP_TIMER_TRIGGER_MASK__SHIFT 0x5
915 #define PWR_IH_CONTROL__DISP_TIMER2_TRIGGER_MASK__SHIFT 0x6
916 #define PWR_IH_CONTROL__MAX_CREDIT_MASK 0x0000001FL
917 #define PWR_IH_CONTROL__DISP_TIMER_TRIGGER_MASK_MASK 0x00000020L
918 #define PWR_IH_CONTROL__DISP_TIMER2_TRIGGER_MASK_MASK 0x00000040L