Merge tag 'for-5.9-tag' of git://git.kernel.org/pub/scm/linux/kernel/git/kdave/linux

[linux-2.6-microblaze.git] / drivers / gpu / drm / amd / include / asic_reg / gc / gc_10_3_0_sh_mask.h

/*
 * Copyright (C) 2019  Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included
 * in all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 */

#ifndef _gc_10_3_0_SH_MASK_HEADER
#define _gc_10_3_0_SH_MASK_HEADER


// addressBlock: gc_sdma0_sdma0dec
//SDMA0_DEC_START
#define SDMA0_DEC_START__START__SHIFT                                                                         0x0
#define SDMA0_DEC_START__START_MASK                                                                           0xFFFFFFFFL
//SDMA0_GLOBAL_TIMESTAMP_LO
#define SDMA0_GLOBAL_TIMESTAMP_LO__DATA__SHIFT                                                                0x0
#define SDMA0_GLOBAL_TIMESTAMP_LO__DATA_MASK                                                                  0xFFFFFFFFL
//SDMA0_GLOBAL_TIMESTAMP_HI
#define SDMA0_GLOBAL_TIMESTAMP_HI__DATA__SHIFT                                                                0x0
#define SDMA0_GLOBAL_TIMESTAMP_HI__DATA_MASK                                                                  0xFFFFFFFFL
//SDMA0_PG_CNTL
#define SDMA0_PG_CNTL__CMD__SHIFT                                                                             0x0
#define SDMA0_PG_CNTL__STATUS__SHIFT                                                                          0x10
#define SDMA0_PG_CNTL__CMD_MASK                                                                               0x0000000FL
#define SDMA0_PG_CNTL__STATUS_MASK                                                                            0x000F0000L
//SDMA0_PG_CTX_LO
#define SDMA0_PG_CTX_LO__ADDR__SHIFT                                                                          0x0
#define SDMA0_PG_CTX_LO__ADDR_MASK                                                                            0xFFFFFFFFL
//SDMA0_PG_CTX_HI
#define SDMA0_PG_CTX_HI__ADDR__SHIFT                                                                          0x0
#define SDMA0_PG_CTX_HI__ADDR_MASK                                                                            0xFFFFFFFFL
//SDMA0_PG_CTX_CNTL
#define SDMA0_PG_CTX_CNTL__VMID__SHIFT                                                                        0x0
#define SDMA0_PG_CTX_CNTL__VMID_MASK                                                                          0x0000000FL
//SDMA0_POWER_CNTL
#define SDMA0_POWER_CNTL__PG_CNTL_ENABLE__SHIFT                                                               0x0
#define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT                                                          0x1
#define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT                                                         0x2
#define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME__SHIFT                                                   0x3
#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT                                                           0x8
#define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME__SHIFT                                                  0x1a
#define SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK                                                                 0x00000001L
#define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK                                                            0x00000002L
#define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK                                                           0x00000004L
#define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK                                                     0x000000F8L
#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK                                                             0x00000100L
#define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK                                                    0xFC000000L
//SDMA0_CLK_CTRL
#define SDMA0_CLK_CTRL__ON_DELAY__SHIFT                                                                       0x0
#define SDMA0_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                                 0x4
#define SDMA0_CLK_CTRL__RESERVED_24_12__SHIFT                                                                 0xc
#define SDMA0_CLK_CTRL__CGCG_EN_OVERRIDE__SHIFT                                                               0x19
#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4__SHIFT                                                                 0x1a
#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3__SHIFT                                                                 0x1b
#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT                                                                 0x1c
#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1__SHIFT                                                                 0x1d
#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0__SHIFT                                                                 0x1e
#define SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG__SHIFT                                                             0x1f
#define SDMA0_CLK_CTRL__ON_DELAY_MASK                                                                         0x0000000FL
#define SDMA0_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                   0x00000FF0L
#define SDMA0_CLK_CTRL__RESERVED_24_12_MASK                                                                   0x01FFF000L
#define SDMA0_CLK_CTRL__CGCG_EN_OVERRIDE_MASK                                                                 0x02000000L
#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK                                                                   0x04000000L
#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK                                                                   0x08000000L
#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK                                                                   0x10000000L
#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK                                                                   0x20000000L
#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK                                                                   0x40000000L
#define SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK                                                               0x80000000L
//SDMA0_CNTL
#define SDMA0_CNTL__TRAP_ENABLE__SHIFT                                                                        0x0
#define SDMA0_CNTL__UTC_L1_ENABLE__SHIFT                                                                      0x1
#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT                                                                0x2
#define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT                                                                   0x3
#define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT                                                                  0x4
#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                              0x5
#define SDMA0_CNTL__PAGE_INT_ENABLE__SHIFT                                                                    0x7
#define SDMA0_CNTL__CH_PERFCNT_ENABLE__SHIFT                                                                  0x10
#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT                                                          0x11
#define SDMA0_CNTL__AUTO_CTXSW_ENABLE__SHIFT                                                                  0x12
#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT                                                                0x1c
#define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT                                                                  0x1d
#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT                                                              0x1e
#define SDMA0_CNTL__TRAP_ENABLE_MASK                                                                          0x00000001L
#define SDMA0_CNTL__UTC_L1_ENABLE_MASK                                                                        0x00000002L
#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK                                                                  0x00000004L
#define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK                                                                     0x00000008L
#define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK                                                                    0x00000010L
#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                                0x00000020L
#define SDMA0_CNTL__PAGE_INT_ENABLE_MASK                                                                      0x00000080L
#define SDMA0_CNTL__CH_PERFCNT_ENABLE_MASK                                                                    0x00010000L
#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK                                                            0x00020000L
#define SDMA0_CNTL__AUTO_CTXSW_ENABLE_MASK                                                                    0x00040000L
#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK                                                                  0x10000000L
#define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK                                                                    0x20000000L
#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE_MASK                                                                0x40000000L
//SDMA0_CHICKEN_BITS
#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT                                                     0x0
#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT                                                 0x1
#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT                                        0x2
#define SDMA0_CHICKEN_BITS__SOFT_OVERRIDE_DCGE__SHIFT                                                         0x4
#define SDMA0_CHICKEN_BITS__SOFT_OVERRIDE_SDMA_GRBM_FGCG__SHIFT                                               0x5
#define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT                                                         0x8
#define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT                                                     0xa
#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT                                                        0x10
#define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT                                                           0x11
#define SDMA0_CHICKEN_BITS__T2L_256B_ENABLE__SHIFT                                                            0x12
#define SDMA0_CHICKEN_BITS__GCR_FGCG_ENABLE__SHIFT                                                            0x13
#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT                                                         0x14
#define SDMA0_CHICKEN_BITS__CH_FGCG_ENABLE__SHIFT                                                             0x15
#define SDMA0_CHICKEN_BITS__UTCL2_INVREQ_FGCG_ENABLE__SHIFT                                                   0x16
#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT                                                           0x17
#define SDMA0_CHICKEN_BITS__UTCL1_FGCG_ENABLE__SHIFT                                                          0x18
#define SDMA0_CHICKEN_BITS__TIME_BASED_QOS__SHIFT                                                             0x19
#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT                                                         0x1a
#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT                                                         0x1c
#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT                                                         0x1e
#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK                                                       0x00000001L
#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK                                                   0x00000002L
#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK                                          0x00000004L
#define SDMA0_CHICKEN_BITS__SOFT_OVERRIDE_DCGE_MASK                                                           0x00000010L
#define SDMA0_CHICKEN_BITS__SOFT_OVERRIDE_SDMA_GRBM_FGCG_MASK                                                 0x00000020L
#define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK                                                           0x00000300L
#define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK                                                       0x00001C00L
#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK                                                          0x00010000L
#define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK                                                             0x00020000L
#define SDMA0_CHICKEN_BITS__T2L_256B_ENABLE_MASK                                                              0x00040000L
#define SDMA0_CHICKEN_BITS__GCR_FGCG_ENABLE_MASK                                                              0x00080000L
#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK                                                           0x00100000L
#define SDMA0_CHICKEN_BITS__CH_FGCG_ENABLE_MASK                                                               0x00200000L
#define SDMA0_CHICKEN_BITS__UTCL2_INVREQ_FGCG_ENABLE_MASK                                                     0x00400000L
#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK                                                             0x00800000L
#define SDMA0_CHICKEN_BITS__UTCL1_FGCG_ENABLE_MASK                                                            0x01000000L
#define SDMA0_CHICKEN_BITS__TIME_BASED_QOS_MASK                                                               0x02000000L
#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK                                                           0x0C000000L
#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK                                                           0x30000000L
#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK                                                           0xC0000000L
//SDMA0_GB_ADDR_CONFIG
#define SDMA0_GB_ADDR_CONFIG__NUM_PIPES__SHIFT                                                                0x0
#define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT                                                     0x3
#define SDMA0_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                     0x6
#define SDMA0_GB_ADDR_CONFIG__NUM_PKRS__SHIFT                                                                 0x8
#define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT                                                       0x13
#define SDMA0_GB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT                                                            0x1a
#define SDMA0_GB_ADDR_CONFIG__NUM_PIPES_MASK                                                                  0x00000007L
#define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK                                                       0x00000038L
#define SDMA0_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                       0x000000C0L
#define SDMA0_GB_ADDR_CONFIG__NUM_PKRS_MASK                                                                   0x00000700L
#define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK                                                         0x00180000L
#define SDMA0_GB_ADDR_CONFIG__NUM_RB_PER_SE_MASK                                                              0x0C000000L
//SDMA0_GB_ADDR_CONFIG_READ
#define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT                                                           0x0
#define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT                                                0x3
#define SDMA0_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT                                                0x6
#define SDMA0_GB_ADDR_CONFIG_READ__NUM_PKRS__SHIFT                                                            0x8
#define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT                                                  0x13
#define SDMA0_GB_ADDR_CONFIG_READ__NUM_RB_PER_SE__SHIFT                                                       0x1a
#define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK                                                             0x00000007L
#define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK                                                  0x00000038L
#define SDMA0_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK                                                  0x000000C0L
#define SDMA0_GB_ADDR_CONFIG_READ__NUM_PKRS_MASK                                                              0x00000700L
#define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK                                                    0x00180000L
#define SDMA0_GB_ADDR_CONFIG_READ__NUM_RB_PER_SE_MASK                                                         0x0C000000L
//SDMA0_RB_RPTR_FETCH_HI
#define SDMA0_RB_RPTR_FETCH_HI__OFFSET__SHIFT                                                                 0x0
#define SDMA0_RB_RPTR_FETCH_HI__OFFSET_MASK                                                                   0xFFFFFFFFL
//SDMA0_SEM_WAIT_FAIL_TIMER_CNTL
#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT                                                          0x0
#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK                                                            0xFFFFFFFFL
//SDMA0_RB_RPTR_FETCH
#define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT                                                                    0x2
#define SDMA0_RB_RPTR_FETCH__OFFSET_MASK                                                                      0xFFFFFFFCL
//SDMA0_IB_OFFSET_FETCH
#define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT                                                                  0x2
#define SDMA0_IB_OFFSET_FETCH__OFFSET_MASK                                                                    0x003FFFFCL
//SDMA0_PROGRAM
#define SDMA0_PROGRAM__STREAM__SHIFT                                                                          0x0
#define SDMA0_PROGRAM__STREAM_MASK                                                                            0xFFFFFFFFL
//SDMA0_STATUS_REG
#define SDMA0_STATUS_REG__IDLE__SHIFT                                                                         0x0
#define SDMA0_STATUS_REG__REG_IDLE__SHIFT                                                                     0x1
#define SDMA0_STATUS_REG__RB_EMPTY__SHIFT                                                                     0x2
#define SDMA0_STATUS_REG__RB_FULL__SHIFT                                                                      0x3
#define SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT                                                                  0x4
#define SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT                                                                  0x5
#define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT                                                                  0x6
#define SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT                                                                  0x7
#define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT                                                                   0x8
#define SDMA0_STATUS_REG__INSIDE_IB__SHIFT                                                                    0x9
#define SDMA0_STATUS_REG__EX_IDLE__SHIFT                                                                      0xa
#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT                                                    0xb
#define SDMA0_STATUS_REG__PACKET_READY__SHIFT                                                                 0xc
#define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT                                                                   0xd
#define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT                                                                    0xe
#define SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT                                                                0xf
#define SDMA0_STATUS_REG__DELTA_RPTR_FULL__SHIFT                                                              0x10
#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT                                                              0x11
#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT                                                              0x12
#define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT                                                                   0x13
#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT                                                             0x14
#define SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT                                                              0x15
#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT                                                           0x16
#define SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT                                                                0x19
#define SDMA0_STATUS_REG__SEM_IDLE__SHIFT                                                                     0x1a
#define SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT                                                                0x1b
#define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT                                                               0x1c
#define SDMA0_STATUS_REG__INT_IDLE__SHIFT                                                                     0x1e
#define SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT                                                                0x1f
#define SDMA0_STATUS_REG__IDLE_MASK                                                                           0x00000001L
#define SDMA0_STATUS_REG__REG_IDLE_MASK                                                                       0x00000002L
#define SDMA0_STATUS_REG__RB_EMPTY_MASK                                                                       0x00000004L
#define SDMA0_STATUS_REG__RB_FULL_MASK                                                                        0x00000008L
#define SDMA0_STATUS_REG__RB_CMD_IDLE_MASK                                                                    0x00000010L
#define SDMA0_STATUS_REG__RB_CMD_FULL_MASK                                                                    0x00000020L
#define SDMA0_STATUS_REG__IB_CMD_IDLE_MASK                                                                    0x00000040L
#define SDMA0_STATUS_REG__IB_CMD_FULL_MASK                                                                    0x00000080L
#define SDMA0_STATUS_REG__BLOCK_IDLE_MASK                                                                     0x00000100L
#define SDMA0_STATUS_REG__INSIDE_IB_MASK                                                                      0x00000200L
#define SDMA0_STATUS_REG__EX_IDLE_MASK                                                                        0x00000400L
#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK                                                      0x00000800L
#define SDMA0_STATUS_REG__PACKET_READY_MASK                                                                   0x00001000L
#define SDMA0_STATUS_REG__MC_WR_IDLE_MASK                                                                     0x00002000L
#define SDMA0_STATUS_REG__SRBM_IDLE_MASK                                                                      0x00004000L
#define SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK                                                                  0x00008000L
#define SDMA0_STATUS_REG__DELTA_RPTR_FULL_MASK                                                                0x00010000L
#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK                                                                0x00020000L
#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK                                                                0x00040000L
#define SDMA0_STATUS_REG__MC_RD_IDLE_MASK                                                                     0x00080000L
#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY_MASK                                                               0x00100000L
#define SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK                                                                0x00200000L
#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK                                                             0x00400000L
#define SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK                                                                  0x02000000L
#define SDMA0_STATUS_REG__SEM_IDLE_MASK                                                                       0x04000000L
#define SDMA0_STATUS_REG__SEM_REQ_STALL_MASK                                                                  0x08000000L
#define SDMA0_STATUS_REG__SEM_RESP_STATE_MASK                                                                 0x30000000L
#define SDMA0_STATUS_REG__INT_IDLE_MASK                                                                       0x40000000L
#define SDMA0_STATUS_REG__INT_REQ_STALL_MASK                                                                  0x80000000L
//SDMA0_STATUS1_REG
#define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT                                                                0x0
#define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT                                                                  0x1
#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT                                                               0x2
#define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT                                                                0x3
#define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT                                                                 0x4
#define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT                                                                  0x5
#define SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT                                                                 0x6
#define SDMA0_STATUS1_REG__CE_CMD_IDLE__SHIFT                                                                 0x9
#define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT                                                               0xa
#define SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT                                                                0xd
#define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT                                                               0xe
#define SDMA0_STATUS1_REG__EX_START__SHIFT                                                                    0xf
#define SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT                                                                 0x11
#define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT                                                                 0x12
#define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK                                                                  0x00000001L
#define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK                                                                    0x00000002L
#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK                                                                 0x00000004L
#define SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK                                                                  0x00000008L
#define SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK                                                                   0x00000010L
#define SDMA0_STATUS1_REG__CE_IN_IDLE_MASK                                                                    0x00000020L
#define SDMA0_STATUS1_REG__CE_DST_IDLE_MASK                                                                   0x00000040L
#define SDMA0_STATUS1_REG__CE_CMD_IDLE_MASK                                                                   0x00000200L
#define SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK                                                                 0x00000400L
#define SDMA0_STATUS1_REG__CE_INFO_FULL_MASK                                                                  0x00002000L
#define SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK                                                                 0x00004000L
#define SDMA0_STATUS1_REG__EX_START_MASK                                                                      0x00008000L
#define SDMA0_STATUS1_REG__CE_RD_STALL_MASK                                                                   0x00020000L
#define SDMA0_STATUS1_REG__CE_WR_STALL_MASK                                                                   0x00040000L
//SDMA0_RD_BURST_CNTL
#define SDMA0_RD_BURST_CNTL__RD_BURST__SHIFT                                                                  0x0
#define SDMA0_RD_BURST_CNTL__RD_BURST_MASK                                                                    0x00000003L
//SDMA0_HBM_PAGE_CONFIG
#define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT                                                      0x0
#define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK                                                        0x00000003L
//SDMA0_UCODE_CHECKSUM
#define SDMA0_UCODE_CHECKSUM__DATA__SHIFT                                                                     0x0
#define SDMA0_UCODE_CHECKSUM__DATA_MASK                                                                       0xFFFFFFFFL
//SDMA0_F32_CNTL
#define SDMA0_F32_CNTL__HALT__SHIFT                                                                           0x0
#define SDMA0_F32_CNTL__STEP__SHIFT                                                                           0x1
#define SDMA0_F32_CNTL__CHECKSUM_CLR__SHIFT                                                                   0x8
#define SDMA0_F32_CNTL__RESET__SHIFT                                                                          0x9
#define SDMA0_F32_CNTL__HALT_MASK                                                                             0x00000001L
#define SDMA0_F32_CNTL__STEP_MASK                                                                             0x00000002L
#define SDMA0_F32_CNTL__CHECKSUM_CLR_MASK                                                                     0x00000100L
#define SDMA0_F32_CNTL__RESET_MASK                                                                            0x00000200L
//SDMA0_FREEZE
#define SDMA0_FREEZE__PREEMPT__SHIFT                                                                          0x0
#define SDMA0_FREEZE__FORCE_PREEMPT__SHIFT                                                                    0x1
#define SDMA0_FREEZE__FREEZE__SHIFT                                                                           0x4
#define SDMA0_FREEZE__FROZEN__SHIFT                                                                           0x5
#define SDMA0_FREEZE__F32_FREEZE__SHIFT                                                                       0x6
#define SDMA0_FREEZE__PREEMPT_MASK                                                                            0x00000001L
#define SDMA0_FREEZE__FORCE_PREEMPT_MASK                                                                      0x00000002L
#define SDMA0_FREEZE__FREEZE_MASK                                                                             0x00000010L
#define SDMA0_FREEZE__FROZEN_MASK                                                                             0x00000020L
#define SDMA0_FREEZE__F32_FREEZE_MASK                                                                         0x00000040L
//SDMA0_PHASE0_QUANTUM
#define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT                                                                     0x0
#define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT                                                                    0x8
#define SDMA0_PHASE0_QUANTUM__PREFER__SHIFT                                                                   0x1e
#define SDMA0_PHASE0_QUANTUM__UNIT_MASK                                                                       0x0000000FL
#define SDMA0_PHASE0_QUANTUM__VALUE_MASK                                                                      0x00FFFF00L
#define SDMA0_PHASE0_QUANTUM__PREFER_MASK                                                                     0x40000000L
//SDMA0_PHASE1_QUANTUM
#define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT                                                                     0x0
#define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT                                                                    0x8
#define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT                                                                   0x1e
#define SDMA0_PHASE1_QUANTUM__UNIT_MASK                                                                       0x0000000FL
#define SDMA0_PHASE1_QUANTUM__VALUE_MASK                                                                      0x00FFFF00L
#define SDMA0_PHASE1_QUANTUM__PREFER_MASK                                                                     0x40000000L
//SDMA0_EDC_CONFIG
#define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT                                                                      0x1
#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT                                                               0x2
#define SDMA0_EDC_CONFIG__DIS_EDC_MASK                                                                        0x00000002L
#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK                                                                 0x00000004L
//SDMA0_BA_THRESHOLD
#define SDMA0_BA_THRESHOLD__READ_THRES__SHIFT                                                                 0x0
#define SDMA0_BA_THRESHOLD__WRITE_THRES__SHIFT                                                                0x10
#define SDMA0_BA_THRESHOLD__READ_THRES_MASK                                                                   0x000003FFL
#define SDMA0_BA_THRESHOLD__WRITE_THRES_MASK                                                                  0x03FF0000L
//SDMA0_ID
#define SDMA0_ID__DEVICE_ID__SHIFT                                                                            0x0
#define SDMA0_ID__DEVICE_ID_MASK                                                                              0x000000FFL
//SDMA0_VERSION
#define SDMA0_VERSION__MINVER__SHIFT                                                                          0x0
#define SDMA0_VERSION__MAJVER__SHIFT                                                                          0x8
#define SDMA0_VERSION__REV__SHIFT                                                                             0x10
#define SDMA0_VERSION__MINVER_MASK                                                                            0x0000007FL
#define SDMA0_VERSION__MAJVER_MASK                                                                            0x00007F00L
#define SDMA0_VERSION__REV_MASK                                                                               0x003F0000L
//SDMA0_EDC_COUNTER
#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_DED__SHIFT                                                          0x0
#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SEC__SHIFT                                                          0x1
#define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT                                                         0x2
#define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT                                                         0x3
#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT                                                      0x4
#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT                                                   0x5
#define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT                                                      0x6
#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT                                                    0x7
#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT                                                    0x8
#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT                                                    0x9
#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT                                                    0xa
#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT                                                    0xb
#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT                                                    0xc
#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT                                                    0xd
#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT                                                    0xe
#define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT                                                      0xf
#define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT                                                    0x10
#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_DED_MASK                                                            0x00000001L
#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SEC_MASK                                                            0x00000002L
#define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK                                                           0x00000004L
#define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK                                                           0x00000008L
#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK                                                        0x00000010L
#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK                                                     0x00000020L
#define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK                                                        0x00000040L
#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK                                                      0x00000080L
#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK                                                      0x00000100L
#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK                                                      0x00000200L
#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK                                                      0x00000400L
#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK                                                      0x00000800L
#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK                                                      0x00001000L
#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK                                                      0x00002000L
#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK                                                      0x00004000L
#define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK                                                        0x00008000L
#define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK                                                      0x00010000L
//SDMA0_EDC_COUNTER_CLEAR
#define SDMA0_EDC_COUNTER_CLEAR__DUMMY__SHIFT                                                                 0x0
#define SDMA0_EDC_COUNTER_CLEAR__DUMMY_MASK                                                                   0x00000001L
//SDMA0_STATUS2_REG
#define SDMA0_STATUS2_REG__ID__SHIFT                                                                          0x0
#define SDMA0_STATUS2_REG__F32_INSTR_PTR__SHIFT                                                               0x2
#define SDMA0_STATUS2_REG__CMD_OP__SHIFT                                                                      0x10
#define SDMA0_STATUS2_REG__ID_MASK                                                                            0x00000003L
#define SDMA0_STATUS2_REG__F32_INSTR_PTR_MASK                                                                 0x0000FFFCL
#define SDMA0_STATUS2_REG__CMD_OP_MASK                                                                        0xFFFF0000L
//SDMA0_ATOMIC_CNTL
#define SDMA0_ATOMIC_CNTL__LOOP_TIMER__SHIFT                                                                  0x0
#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT                                                       0x1f
#define SDMA0_ATOMIC_CNTL__LOOP_TIMER_MASK                                                                    0x7FFFFFFFL
#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK                                                         0x80000000L
//SDMA0_ATOMIC_PREOP_LO
#define SDMA0_ATOMIC_PREOP_LO__DATA__SHIFT                                                                    0x0
#define SDMA0_ATOMIC_PREOP_LO__DATA_MASK                                                                      0xFFFFFFFFL
//SDMA0_ATOMIC_PREOP_HI
#define SDMA0_ATOMIC_PREOP_HI__DATA__SHIFT                                                                    0x0
#define SDMA0_ATOMIC_PREOP_HI__DATA_MASK                                                                      0xFFFFFFFFL
//SDMA0_UTCL1_CNTL
#define SDMA0_UTCL1_CNTL__REDO_ENABLE__SHIFT                                                                  0x0
#define SDMA0_UTCL1_CNTL__REDO_DELAY__SHIFT                                                                   0x1
#define SDMA0_UTCL1_CNTL__REDO_WATERMK__SHIFT                                                                 0x6
#define SDMA0_UTCL1_CNTL__RESP_MODE__SHIFT                                                                    0x9
#define SDMA0_UTCL1_CNTL__FORCE_INVALIDATION__SHIFT                                                           0xe
#define SDMA0_UTCL1_CNTL__FORCE_INVREQ_HEAVY__SHIFT                                                           0xf
#define SDMA0_UTCL1_CNTL__INVACK_DELAY__SHIFT                                                                 0x10
#define SDMA0_UTCL1_CNTL__REQL2_CREDIT__SHIFT                                                                 0x18
#define SDMA0_UTCL1_CNTL__VADDR_WATERMK__SHIFT                                                                0x1d
#define SDMA0_UTCL1_CNTL__REDO_ENABLE_MASK                                                                    0x00000001L
#define SDMA0_UTCL1_CNTL__REDO_DELAY_MASK                                                                     0x0000003EL
#define SDMA0_UTCL1_CNTL__REDO_WATERMK_MASK                                                                   0x000001C0L
#define SDMA0_UTCL1_CNTL__RESP_MODE_MASK                                                                      0x00000E00L
#define SDMA0_UTCL1_CNTL__FORCE_INVALIDATION_MASK                                                             0x00004000L
#define SDMA0_UTCL1_CNTL__FORCE_INVREQ_HEAVY_MASK                                                             0x00008000L
#define SDMA0_UTCL1_CNTL__INVACK_DELAY_MASK                                                                   0x00FF0000L
#define SDMA0_UTCL1_CNTL__REQL2_CREDIT_MASK                                                                   0x1F000000L
#define SDMA0_UTCL1_CNTL__VADDR_WATERMK_MASK                                                                  0xE0000000L
//SDMA0_UTCL1_WATERMK
#define SDMA0_UTCL1_WATERMK__REQMC_WATERMK__SHIFT                                                             0x0
#define SDMA0_UTCL1_WATERMK__REQPG_WATERMK__SHIFT                                                             0xa
#define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT                                                            0x12
#define SDMA0_UTCL1_WATERMK__XNACK_WATERMK__SHIFT                                                             0x1a
#define SDMA0_UTCL1_WATERMK__REQMC_WATERMK_MASK                                                               0x000003FFL
#define SDMA0_UTCL1_WATERMK__REQPG_WATERMK_MASK                                                               0x0003FC00L
#define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK_MASK                                                              0x03FC0000L
#define SDMA0_UTCL1_WATERMK__XNACK_WATERMK_MASK                                                               0xFC000000L
//SDMA0_UTCL1_RD_STATUS
#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT                                                0x0
#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT                                                 0x1
#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT                                                     0x2
#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT                                                      0x3
#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT                                                      0x4
#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT                                                       0x5
#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT                                                   0x6
#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT                                                    0x7
#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT                                                    0x8
#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT                                                     0x9
#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT                                                 0xa
#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT                                                  0xb
#define SDMA0_UTCL1_RD_STATUS__REDO_ARR_EMPTY__SHIFT                                                          0xc
#define SDMA0_UTCL1_RD_STATUS__REDO_ARR_FULL__SHIFT                                                           0xd
#define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT                                                              0xe
#define SDMA0_UTCL1_RD_STATUS__PAGE_NULL__SHIFT                                                               0xf
#define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT                                                              0x10
#define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT                                                          0x11
#define SDMA0_UTCL1_RD_STATUS__MERGE_STATE__SHIFT                                                             0x15
#define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT                                                             0x18
#define SDMA0_UTCL1_RD_STATUS__RD_XNACK_TIMEOUT__SHIFT                                                        0x19
#define SDMA0_UTCL1_RD_STATUS__PAGE_NULL_SW__SHIFT                                                            0x1a
#define SDMA0_UTCL1_RD_STATUS__HIT_CACHE__SHIFT                                                               0x1b
#define SDMA0_UTCL1_RD_STATUS__RD_DCC_ENABLE__SHIFT                                                           0x1c
#define SDMA0_UTCL1_RD_STATUS__NACK_TIMEOUT_SW__SHIFT                                                         0x1d
#define SDMA0_UTCL1_RD_STATUS__DCC_PAGE_FAULT__SHIFT                                                          0x1e
#define SDMA0_UTCL1_RD_STATUS__DCC_PAGE_NULL__SHIFT                                                           0x1f
#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK                                                  0x00000001L
#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK                                                   0x00000002L
#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK                                                       0x00000004L
#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK                                                        0x00000008L
#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK                                                        0x00000010L
#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK                                                         0x00000020L
#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK                                                     0x00000040L
#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK                                                      0x00000080L
#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK                                                      0x00000100L
#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK                                                       0x00000200L
#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK                                                   0x00000400L
#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK                                                    0x00000800L
#define SDMA0_UTCL1_RD_STATUS__REDO_ARR_EMPTY_MASK                                                            0x00001000L
#define SDMA0_UTCL1_RD_STATUS__REDO_ARR_FULL_MASK                                                             0x00002000L
#define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT_MASK                                                                0x00004000L
#define SDMA0_UTCL1_RD_STATUS__PAGE_NULL_MASK                                                                 0x00008000L
#define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE_MASK                                                                0x00010000L
#define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK                                                            0x001E0000L
#define SDMA0_UTCL1_RD_STATUS__MERGE_STATE_MASK                                                               0x00E00000L
#define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK                                                               0x01000000L
#define SDMA0_UTCL1_RD_STATUS__RD_XNACK_TIMEOUT_MASK                                                          0x02000000L
#define SDMA0_UTCL1_RD_STATUS__PAGE_NULL_SW_MASK                                                              0x04000000L
#define SDMA0_UTCL1_RD_STATUS__HIT_CACHE_MASK                                                                 0x08000000L
#define SDMA0_UTCL1_RD_STATUS__RD_DCC_ENABLE_MASK                                                             0x10000000L
#define SDMA0_UTCL1_RD_STATUS__NACK_TIMEOUT_SW_MASK                                                           0x20000000L
#define SDMA0_UTCL1_RD_STATUS__DCC_PAGE_FAULT_MASK                                                            0x40000000L
#define SDMA0_UTCL1_RD_STATUS__DCC_PAGE_NULL_MASK                                                             0x80000000L
//SDMA0_UTCL1_WR_STATUS
#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT                                                0x0
#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT                                                 0x1
#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT                                                     0x2
#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT                                                      0x3
#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT                                                      0x4
#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT                                                       0x5
#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT                                                   0x6
#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT                                                    0x7
#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT                                                    0x8
#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT                                                     0x9
#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT                                                 0xa
#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT                                                  0xb
#define SDMA0_UTCL1_WR_STATUS__REDO_ARR_EMPTY__SHIFT                                                          0xc
#define SDMA0_UTCL1_WR_STATUS__REDO_ARR_FULL__SHIFT                                                           0xd
#define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT                                                              0xe
#define SDMA0_UTCL1_WR_STATUS__PAGE_NULL__SHIFT                                                               0xf
#define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT                                                              0x10
#define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT                                                          0x11
#define SDMA0_UTCL1_WR_STATUS__MERGE_STATE__SHIFT                                                             0x15
#define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT                                                              0x18
#define SDMA0_UTCL1_WR_STATUS__WR_XNACK_TIMEOUT__SHIFT                                                        0x19
#define SDMA0_UTCL1_WR_STATUS__PAGE_NULL_SW__SHIFT                                                            0x1a
#define SDMA0_UTCL1_WR_STATUS__ATOMIC_OP__SHIFT                                                               0x1b
#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT                                                    0x1c
#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT                                                     0x1d
#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT                                                   0x1e
#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT                                                    0x1f
#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK                                                  0x00000001L
#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK                                                   0x00000002L
#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK                                                       0x00000004L
#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK                                                        0x00000008L
#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK                                                        0x00000010L
#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK                                                         0x00000020L
#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK                                                     0x00000040L
#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK                                                      0x00000080L
#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK                                                      0x00000100L
#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK                                                       0x00000200L
#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK                                                   0x00000400L
#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK                                                    0x00000800L
#define SDMA0_UTCL1_WR_STATUS__REDO_ARR_EMPTY_MASK                                                            0x00001000L
#define SDMA0_UTCL1_WR_STATUS__REDO_ARR_FULL_MASK                                                             0x00002000L
#define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT_MASK                                                                0x00004000L
#define SDMA0_UTCL1_WR_STATUS__PAGE_NULL_MASK                                                                 0x00008000L
#define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE_MASK                                                                0x00010000L
#define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK                                                            0x001E0000L
#define SDMA0_UTCL1_WR_STATUS__MERGE_STATE_MASK                                                               0x00E00000L
#define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR_MASK                                                                0x01000000L
#define SDMA0_UTCL1_WR_STATUS__WR_XNACK_TIMEOUT_MASK                                                          0x02000000L
#define SDMA0_UTCL1_WR_STATUS__PAGE_NULL_SW_MASK                                                              0x04000000L
#define SDMA0_UTCL1_WR_STATUS__ATOMIC_OP_MASK                                                                 0x08000000L
#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK                                                      0x10000000L
#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK                                                       0x20000000L
#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK                                                     0x40000000L
#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK                                                      0x80000000L
//SDMA0_UTCL1_INV0
#define SDMA0_UTCL1_INV0__CPF_INVREQ_EN__SHIFT                                                                0x0
#define SDMA0_UTCL1_INV0__GPUVM_INVREQ_EN__SHIFT                                                              0x1
#define SDMA0_UTCL1_INV0__CPF_GPA_INVREQ__SHIFT                                                               0x2
#define SDMA0_UTCL1_INV0__GPUVM_INVREQ_LOW__SHIFT                                                             0x3
#define SDMA0_UTCL1_INV0__GPUVM_INVREQ_HIGH__SHIFT                                                            0x4
#define SDMA0_UTCL1_INV0__INVREQ_SIZE__SHIFT                                                                  0x5
#define SDMA0_UTCL1_INV0__INVREQ_IDLE__SHIFT                                                                  0xb
#define SDMA0_UTCL1_INV0__VMINV_PEND_CNT__SHIFT                                                               0xc
#define SDMA0_UTCL1_INV0__GPUVM_LO_INV_VMID__SHIFT                                                            0x10
#define SDMA0_UTCL1_INV0__GPUVM_HI_INV_VMID__SHIFT                                                            0x14
#define SDMA0_UTCL1_INV0__GPUVM_INV_MODE__SHIFT                                                               0x18
#define SDMA0_UTCL1_INV0__INVREQ_IS_HEAVY__SHIFT                                                              0x1a
#define SDMA0_UTCL1_INV0__INVREQ_FROM_CPF__SHIFT                                                              0x1b
#define SDMA0_UTCL1_INV0__GPUVM_INVREQ_TAG__SHIFT                                                             0x1c
#define SDMA0_UTCL1_INV0__CPF_INVREQ_EN_MASK                                                                  0x00000001L
#define SDMA0_UTCL1_INV0__GPUVM_INVREQ_EN_MASK                                                                0x00000002L
#define SDMA0_UTCL1_INV0__CPF_GPA_INVREQ_MASK                                                                 0x00000004L
#define SDMA0_UTCL1_INV0__GPUVM_INVREQ_LOW_MASK                                                               0x00000008L
#define SDMA0_UTCL1_INV0__GPUVM_INVREQ_HIGH_MASK                                                              0x00000010L
#define SDMA0_UTCL1_INV0__INVREQ_SIZE_MASK                                                                    0x000007E0L
#define SDMA0_UTCL1_INV0__INVREQ_IDLE_MASK                                                                    0x00000800L
#define SDMA0_UTCL1_INV0__VMINV_PEND_CNT_MASK                                                                 0x0000F000L
#define SDMA0_UTCL1_INV0__GPUVM_LO_INV_VMID_MASK                                                              0x000F0000L
#define SDMA0_UTCL1_INV0__GPUVM_HI_INV_VMID_MASK                                                              0x00F00000L
#define SDMA0_UTCL1_INV0__GPUVM_INV_MODE_MASK                                                                 0x03000000L
#define SDMA0_UTCL1_INV0__INVREQ_IS_HEAVY_MASK                                                                0x04000000L
#define SDMA0_UTCL1_INV0__INVREQ_FROM_CPF_MASK                                                                0x08000000L
#define SDMA0_UTCL1_INV0__GPUVM_INVREQ_TAG_MASK                                                               0xF0000000L
//SDMA0_UTCL1_INV1
#define SDMA0_UTCL1_INV1__INV_ADDR_LO__SHIFT                                                                  0x0
#define SDMA0_UTCL1_INV1__INV_ADDR_LO_MASK                                                                    0xFFFFFFFFL
//SDMA0_UTCL1_INV2
#define SDMA0_UTCL1_INV2__INV_VMID_VEC__SHIFT                                                                 0x0
#define SDMA0_UTCL1_INV2__RESERVED__SHIFT                                                                     0x10
#define SDMA0_UTCL1_INV2__INV_VMID_VEC_MASK                                                                   0x0000FFFFL
#define SDMA0_UTCL1_INV2__RESERVED_MASK                                                                       0xFFFF0000L
//SDMA0_UTCL1_RD_XNACK0
#define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT                                                           0x0
#define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK                                                             0xFFFFFFFFL
//SDMA0_UTCL1_RD_XNACK1
#define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT                                                           0x0
#define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT                                                              0x4
#define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT                                                            0x8
#define SDMA0_UTCL1_RD_XNACK1__IS_XNACK__SHIFT                                                                0x1a
#define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK                                                             0x0000000FL
#define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID_MASK                                                                0x000000F0L
#define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK                                                              0x03FFFF00L
#define SDMA0_UTCL1_RD_XNACK1__IS_XNACK_MASK                                                                  0x0C000000L
//SDMA0_UTCL1_WR_XNACK0
#define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT                                                           0x0
#define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK                                                             0xFFFFFFFFL
//SDMA0_UTCL1_WR_XNACK1
#define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT                                                           0x0
#define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT                                                              0x4
#define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT                                                            0x8
#define SDMA0_UTCL1_WR_XNACK1__IS_XNACK__SHIFT                                                                0x1a
#define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK                                                             0x0000000FL
#define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID_MASK                                                                0x000000F0L
#define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK                                                              0x03FFFF00L
#define SDMA0_UTCL1_WR_XNACK1__IS_XNACK_MASK                                                                  0x0C000000L
//SDMA0_UTCL1_TIMEOUT
#define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT                                                            0x0
#define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT                                                            0x10
#define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK                                                              0x0000FFFFL
#define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK                                                              0xFFFF0000L
//SDMA0_UTCL1_PAGE
#define SDMA0_UTCL1_PAGE__VM_HOLE__SHIFT                                                                      0x0
#define SDMA0_UTCL1_PAGE__REQ_TYPE__SHIFT                                                                     0x1
#define SDMA0_UTCL1_PAGE__USE_MTYPE__SHIFT                                                                    0x6
#define SDMA0_UTCL1_PAGE__USE_PT_SNOOP__SHIFT                                                                 0xa
#define SDMA0_UTCL1_PAGE__USE_IO__SHIFT                                                                       0xb
#define SDMA0_UTCL1_PAGE__RD_L2_POLICY__SHIFT                                                                 0xc
#define SDMA0_UTCL1_PAGE__WR_L2_POLICY__SHIFT                                                                 0xe
#define SDMA0_UTCL1_PAGE__DMA_PAGE_SIZE__SHIFT                                                                0x10
#define SDMA0_UTCL1_PAGE__USE_BC__SHIFT                                                                       0x16
#define SDMA0_UTCL1_PAGE__ADDR_IS_PA__SHIFT                                                                   0x17
#define SDMA0_UTCL1_PAGE__VM_HOLE_MASK                                                                        0x00000001L
#define SDMA0_UTCL1_PAGE__REQ_TYPE_MASK                                                                       0x0000001EL
#define SDMA0_UTCL1_PAGE__USE_MTYPE_MASK                                                                      0x000003C0L
#define SDMA0_UTCL1_PAGE__USE_PT_SNOOP_MASK                                                                   0x00000400L
#define SDMA0_UTCL1_PAGE__USE_IO_MASK                                                                         0x00000800L
#define SDMA0_UTCL1_PAGE__RD_L2_POLICY_MASK                                                                   0x00003000L
#define SDMA0_UTCL1_PAGE__WR_L2_POLICY_MASK                                                                   0x0000C000L
#define SDMA0_UTCL1_PAGE__DMA_PAGE_SIZE_MASK                                                                  0x003F0000L
#define SDMA0_UTCL1_PAGE__USE_BC_MASK                                                                         0x00400000L
#define SDMA0_UTCL1_PAGE__ADDR_IS_PA_MASK                                                                     0x00800000L
//SDMA0_RELAX_ORDERING_LUT
#define SDMA0_RELAX_ORDERING_LUT__RESERVED0__SHIFT                                                            0x0
#define SDMA0_RELAX_ORDERING_LUT__COPY__SHIFT                                                                 0x1
#define SDMA0_RELAX_ORDERING_LUT__WRITE__SHIFT                                                                0x2
#define SDMA0_RELAX_ORDERING_LUT__RESERVED3__SHIFT                                                            0x3
#define SDMA0_RELAX_ORDERING_LUT__RESERVED4__SHIFT                                                            0x4
#define SDMA0_RELAX_ORDERING_LUT__FENCE__SHIFT                                                                0x5
#define SDMA0_RELAX_ORDERING_LUT__RESERVED76__SHIFT                                                           0x6
#define SDMA0_RELAX_ORDERING_LUT__POLL_MEM__SHIFT                                                             0x8
#define SDMA0_RELAX_ORDERING_LUT__COND_EXE__SHIFT                                                             0x9
#define SDMA0_RELAX_ORDERING_LUT__ATOMIC__SHIFT                                                               0xa
#define SDMA0_RELAX_ORDERING_LUT__CONST_FILL__SHIFT                                                           0xb
#define SDMA0_RELAX_ORDERING_LUT__PTEPDE__SHIFT                                                               0xc
#define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT                                                            0xd
#define SDMA0_RELAX_ORDERING_LUT__RESERVED__SHIFT                                                             0xe
#define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT                                                         0x1b
#define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT                                                             0x1c
#define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT                                                            0x1d
#define SDMA0_RELAX_ORDERING_LUT__IB_FETCH__SHIFT                                                             0x1e
#define SDMA0_RELAX_ORDERING_LUT__RB_FETCH__SHIFT                                                             0x1f
#define SDMA0_RELAX_ORDERING_LUT__RESERVED0_MASK                                                              0x00000001L
#define SDMA0_RELAX_ORDERING_LUT__COPY_MASK                                                                   0x00000002L
#define SDMA0_RELAX_ORDERING_LUT__WRITE_MASK                                                                  0x00000004L
#define SDMA0_RELAX_ORDERING_LUT__RESERVED3_MASK                                                              0x00000008L
#define SDMA0_RELAX_ORDERING_LUT__RESERVED4_MASK                                                              0x00000010L
#define SDMA0_RELAX_ORDERING_LUT__FENCE_MASK                                                                  0x00000020L
#define SDMA0_RELAX_ORDERING_LUT__RESERVED76_MASK                                                             0x000000C0L
#define SDMA0_RELAX_ORDERING_LUT__POLL_MEM_MASK                                                               0x00000100L
#define SDMA0_RELAX_ORDERING_LUT__COND_EXE_MASK                                                               0x00000200L
#define SDMA0_RELAX_ORDERING_LUT__ATOMIC_MASK                                                                 0x00000400L
#define SDMA0_RELAX_ORDERING_LUT__CONST_FILL_MASK                                                             0x00000800L
#define SDMA0_RELAX_ORDERING_LUT__PTEPDE_MASK                                                                 0x00001000L
#define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP_MASK                                                              0x00002000L
#define SDMA0_RELAX_ORDERING_LUT__RESERVED_MASK                                                               0x07FFC000L
#define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK                                                           0x08000000L
#define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB_MASK                                                               0x10000000L
#define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL_MASK                                                              0x20000000L
#define SDMA0_RELAX_ORDERING_LUT__IB_FETCH_MASK                                                               0x40000000L
#define SDMA0_RELAX_ORDERING_LUT__RB_FETCH_MASK                                                               0x80000000L
//SDMA0_CHICKEN_BITS_2
#define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT                                                       0x0
#define SDMA0_CHICKEN_BITS_2__CE_BACKWARDS_SIZE_SEL__SHIFT                                                    0x4
#define SDMA0_CHICKEN_BITS_2__CE_DCC_READ_128B_ENABLE__SHIFT                                                  0x5
#define SDMA0_CHICKEN_BITS_2__UTCL1_FORCE_INV_RET_FIFO_FULL_EN__SHIFT                                         0x6
#define SDMA0_CHICKEN_BITS_2__RESERVED0__SHIFT                                                                0x7
#define SDMA0_CHICKEN_BITS_2__LUT_FIFO_AFULL_MARGIN__SHIFT                                                    0xb
#define SDMA0_CHICKEN_BITS_2__LEGACY_WPTR_POLL_BEHAVIOR__SHIFT                                                0xf
#define SDMA0_CHICKEN_BITS_2__RB_FIFO_WATERMARK__SHIFT                                                        0x10
#define SDMA0_CHICKEN_BITS_2__IB_FIFO_WATERMARK__SHIFT                                                        0x12
#define SDMA0_CHICKEN_BITS_2__REPEATER_FGCG_EN__SHIFT                                                         0x14
#define SDMA0_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN__SHIFT                                                     0x15
#define SDMA0_CHICKEN_BITS_2__RESERVED__SHIFT                                                                 0x16
#define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK                                                         0x0000000FL
#define SDMA0_CHICKEN_BITS_2__CE_BACKWARDS_SIZE_SEL_MASK                                                      0x00000010L
#define SDMA0_CHICKEN_BITS_2__CE_DCC_READ_128B_ENABLE_MASK                                                    0x00000020L
#define SDMA0_CHICKEN_BITS_2__UTCL1_FORCE_INV_RET_FIFO_FULL_EN_MASK                                           0x00000040L
#define SDMA0_CHICKEN_BITS_2__RESERVED0_MASK                                                                  0x00000780L
#define SDMA0_CHICKEN_BITS_2__LUT_FIFO_AFULL_MARGIN_MASK                                                      0x00007800L
#define SDMA0_CHICKEN_BITS_2__LEGACY_WPTR_POLL_BEHAVIOR_MASK                                                  0x00008000L
#define SDMA0_CHICKEN_BITS_2__RB_FIFO_WATERMARK_MASK                                                          0x00030000L
#define SDMA0_CHICKEN_BITS_2__IB_FIFO_WATERMARK_MASK                                                          0x000C0000L
#define SDMA0_CHICKEN_BITS_2__REPEATER_FGCG_EN_MASK                                                           0x00100000L
#define SDMA0_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN_MASK                                                       0x00200000L
#define SDMA0_CHICKEN_BITS_2__RESERVED_MASK                                                                   0xFFC00000L
//SDMA0_STATUS3_REG
#define SDMA0_STATUS3_REG__CMD_OP_STATUS__SHIFT                                                               0x0
#define SDMA0_STATUS3_REG__PREV_VM_CMD__SHIFT                                                                 0x10
#define SDMA0_STATUS3_REG__EXCEPTION_IDLE__SHIFT                                                              0x14
#define SDMA0_STATUS3_REG__AQL_PREV_CMD_IDLE__SHIFT                                                           0x15
#define SDMA0_STATUS3_REG__TLBI_IDLE__SHIFT                                                                   0x16
#define SDMA0_STATUS3_REG__GCR_IDLE__SHIFT                                                                    0x17
#define SDMA0_STATUS3_REG__INVREQ_IDLE__SHIFT                                                                 0x18
#define SDMA0_STATUS3_REG__QUEUE_ID_MATCH__SHIFT                                                              0x19
#define SDMA0_STATUS3_REG__INT_QUEUE_ID__SHIFT                                                                0x1a
#define SDMA0_STATUS3_REG__CMD_OP_STATUS_MASK                                                                 0x0000FFFFL
#define SDMA0_STATUS3_REG__PREV_VM_CMD_MASK                                                                   0x000F0000L
#define SDMA0_STATUS3_REG__EXCEPTION_IDLE_MASK                                                                0x00100000L
#define SDMA0_STATUS3_REG__AQL_PREV_CMD_IDLE_MASK                                                             0x00200000L
#define SDMA0_STATUS3_REG__TLBI_IDLE_MASK                                                                     0x00400000L
#define SDMA0_STATUS3_REG__GCR_IDLE_MASK                                                                      0x00800000L
#define SDMA0_STATUS3_REG__INVREQ_IDLE_MASK                                                                   0x01000000L
#define SDMA0_STATUS3_REG__QUEUE_ID_MATCH_MASK                                                                0x02000000L
#define SDMA0_STATUS3_REG__INT_QUEUE_ID_MASK                                                                  0x3C000000L
//SDMA0_PHYSICAL_ADDR_LO
#define SDMA0_PHYSICAL_ADDR_LO__D_VALID__SHIFT                                                                0x0
#define SDMA0_PHYSICAL_ADDR_LO__DIRTY__SHIFT                                                                  0x1
#define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT                                                              0x2
#define SDMA0_PHYSICAL_ADDR_LO__ADDR__SHIFT                                                                   0xc
#define SDMA0_PHYSICAL_ADDR_LO__D_VALID_MASK                                                                  0x00000001L
#define SDMA0_PHYSICAL_ADDR_LO__DIRTY_MASK                                                                    0x00000002L
#define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID_MASK                                                                0x00000004L
#define SDMA0_PHYSICAL_ADDR_LO__ADDR_MASK                                                                     0xFFFFF000L
//SDMA0_PHYSICAL_ADDR_HI
#define SDMA0_PHYSICAL_ADDR_HI__ADDR__SHIFT                                                                   0x0
#define SDMA0_PHYSICAL_ADDR_HI__ADDR_MASK                                                                     0x0000FFFFL
//SDMA0_PHASE2_QUANTUM
#define SDMA0_PHASE2_QUANTUM__UNIT__SHIFT                                                                     0x0
#define SDMA0_PHASE2_QUANTUM__VALUE__SHIFT                                                                    0x8
#define SDMA0_PHASE2_QUANTUM__PREFER__SHIFT                                                                   0x1e
#define SDMA0_PHASE2_QUANTUM__UNIT_MASK                                                                       0x0000000FL
#define SDMA0_PHASE2_QUANTUM__VALUE_MASK                                                                      0x00FFFF00L
#define SDMA0_PHASE2_QUANTUM__PREFER_MASK                                                                     0x40000000L
//SDMA0_ERROR_LOG
#define SDMA0_ERROR_LOG__OVERRIDE__SHIFT                                                                      0x0
#define SDMA0_ERROR_LOG__STATUS__SHIFT                                                                        0x10
#define SDMA0_ERROR_LOG__OVERRIDE_MASK                                                                        0x0000FFFFL
#define SDMA0_ERROR_LOG__STATUS_MASK                                                                          0xFFFF0000L
//SDMA0_PUB_DUMMY_REG0
#define SDMA0_PUB_DUMMY_REG0__VALUE__SHIFT                                                                    0x0
#define SDMA0_PUB_DUMMY_REG0__VALUE_MASK                                                                      0xFFFFFFFFL
//SDMA0_PUB_DUMMY_REG1
#define SDMA0_PUB_DUMMY_REG1__VALUE__SHIFT                                                                    0x0
#define SDMA0_PUB_DUMMY_REG1__VALUE_MASK                                                                      0xFFFFFFFFL
//SDMA0_PUB_DUMMY_REG2
#define SDMA0_PUB_DUMMY_REG2__VALUE__SHIFT                                                                    0x0
#define SDMA0_PUB_DUMMY_REG2__VALUE_MASK                                                                      0xFFFFFFFFL
//SDMA0_PUB_DUMMY_REG3
#define SDMA0_PUB_DUMMY_REG3__VALUE__SHIFT                                                                    0x0
#define SDMA0_PUB_DUMMY_REG3__VALUE_MASK                                                                      0xFFFFFFFFL
//SDMA0_F32_COUNTER
#define SDMA0_F32_COUNTER__VALUE__SHIFT                                                                       0x0
#define SDMA0_F32_COUNTER__VALUE_MASK                                                                         0xFFFFFFFFL
//SDMA0_CRD_CNTL
#define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT                                                                0x7
#define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT                                                                0xd
#define SDMA0_CRD_CNTL__CH_WRREQ_CREDIT__SHIFT                                                                0x13
#define SDMA0_CRD_CNTL__CH_RDREQ_CREDIT__SHIFT                                                                0x19
#define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT_MASK                                                                  0x00001F80L
#define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT_MASK                                                                  0x0007E000L
#define SDMA0_CRD_CNTL__CH_WRREQ_CREDIT_MASK                                                                  0x01F80000L
#define SDMA0_CRD_CNTL__CH_RDREQ_CREDIT_MASK                                                                  0x7E000000L
//SDMA0_AQL_STATUS
#define SDMA0_AQL_STATUS__COMPLETE_SIGNAL_EMPTY__SHIFT                                                        0x0
#define SDMA0_AQL_STATUS__INVALID_CMD_EMPTY__SHIFT                                                            0x1
#define SDMA0_AQL_STATUS__COMPLETE_SIGNAL_EMPTY_MASK                                                          0x00000001L
#define SDMA0_AQL_STATUS__INVALID_CMD_EMPTY_MASK                                                              0x00000002L
//SDMA0_EA_DBIT_ADDR_DATA
#define SDMA0_EA_DBIT_ADDR_DATA__VALUE__SHIFT                                                                 0x0
#define SDMA0_EA_DBIT_ADDR_DATA__VALUE_MASK                                                                   0xFFFFFFFFL
//SDMA0_EA_DBIT_ADDR_INDEX
#define SDMA0_EA_DBIT_ADDR_INDEX__VALUE__SHIFT                                                                0x0
#define SDMA0_EA_DBIT_ADDR_INDEX__VALUE_MASK                                                                  0x00000007L
//SDMA0_TLBI_GCR_CNTL
#define SDMA0_TLBI_GCR_CNTL__TLBI_CMD_DW__SHIFT                                                               0x0
#define SDMA0_TLBI_GCR_CNTL__GCR_CMD_DW__SHIFT                                                                0x4
#define SDMA0_TLBI_GCR_CNTL__GCR_CLKEN_CYCLE__SHIFT                                                           0x8
#define SDMA0_TLBI_GCR_CNTL__TLBI_CREDIT__SHIFT                                                               0x10
#define SDMA0_TLBI_GCR_CNTL__GCR_CREDIT__SHIFT                                                                0x18
#define SDMA0_TLBI_GCR_CNTL__TLBI_CMD_DW_MASK                                                                 0x0000000FL
#define SDMA0_TLBI_GCR_CNTL__GCR_CMD_DW_MASK                                                                  0x000000F0L
#define SDMA0_TLBI_GCR_CNTL__GCR_CLKEN_CYCLE_MASK                                                             0x00000F00L
#define SDMA0_TLBI_GCR_CNTL__TLBI_CREDIT_MASK                                                                 0x00FF0000L
#define SDMA0_TLBI_GCR_CNTL__GCR_CREDIT_MASK                                                                  0xFF000000L
//SDMA0_TILING_CONFIG
#define SDMA0_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT                                                      0x4
#define SDMA0_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK                                                        0x00000070L
//SDMA0_INT_STATUS
#define SDMA0_INT_STATUS__DATA__SHIFT                                                                         0x0
#define SDMA0_INT_STATUS__DATA_MASK                                                                           0xFFFFFFFFL
//SDMA0_HOLE_ADDR_LO
#define SDMA0_HOLE_ADDR_LO__VALUE__SHIFT                                                                      0x0
#define SDMA0_HOLE_ADDR_LO__VALUE_MASK                                                                        0xFFFFFFFFL
//SDMA0_HOLE_ADDR_HI
#define SDMA0_HOLE_ADDR_HI__VALUE__SHIFT                                                                      0x0
#define SDMA0_HOLE_ADDR_HI__VALUE_MASK                                                                        0xFFFFFFFFL
//SDMA0_CLOCK_GATING_REG
#define SDMA0_CLOCK_GATING_REG__DYN_CLK_GATE_STATUS__SHIFT                                                    0x0
#define SDMA0_CLOCK_GATING_REG__PTR_CLK_GATE_STATUS__SHIFT                                                    0x1
#define SDMA0_CLOCK_GATING_REG__CE_CLK_GATE_STATUS__SHIFT                                                     0x2
#define SDMA0_CLOCK_GATING_REG__CE_BC_CLK_GATE_STATUS__SHIFT                                                  0x3
#define SDMA0_CLOCK_GATING_REG__CE_NBC_CLK_GATE_STATUS__SHIFT                                                 0x4
#define SDMA0_CLOCK_GATING_REG__REG_CLK_GATE_STATUS__SHIFT                                                    0x5
#define SDMA0_CLOCK_GATING_REG__DYN_CLK_GATE_STATUS_MASK                                                      0x00000001L
#define SDMA0_CLOCK_GATING_REG__PTR_CLK_GATE_STATUS_MASK                                                      0x00000002L
#define SDMA0_CLOCK_GATING_REG__CE_CLK_GATE_STATUS_MASK                                                       0x00000004L
#define SDMA0_CLOCK_GATING_REG__CE_BC_CLK_GATE_STATUS_MASK                                                    0x00000008L
#define SDMA0_CLOCK_GATING_REG__CE_NBC_CLK_GATE_STATUS_MASK                                                   0x00000010L
#define SDMA0_CLOCK_GATING_REG__REG_CLK_GATE_STATUS_MASK                                                      0x00000020L
//SDMA0_STATUS4_REG
#define SDMA0_STATUS4_REG__IDLE__SHIFT                                                                        0x0
#define SDMA0_STATUS4_REG__IH_OUTSTANDING__SHIFT                                                              0x2
#define SDMA0_STATUS4_REG__SEM_OUTSTANDING__SHIFT                                                             0x3
#define SDMA0_STATUS4_REG__CH_RD_OUTSTANDING__SHIFT                                                           0x4
#define SDMA0_STATUS4_REG__CH_WR_OUTSTANDING__SHIFT                                                           0x5
#define SDMA0_STATUS4_REG__GCR_OUTSTANDING__SHIFT                                                             0x6
#define SDMA0_STATUS4_REG__TLBI_OUTSTANDING__SHIFT                                                            0x7
#define SDMA0_STATUS4_REG__UTCL2_RD_OUTSTANDING__SHIFT                                                        0x8
#define SDMA0_STATUS4_REG__UTCL2_WR_OUTSTANDING__SHIFT                                                        0x9
#define SDMA0_STATUS4_REG__REG_POLLING__SHIFT                                                                 0xa
#define SDMA0_STATUS4_REG__MEM_POLLING__SHIFT                                                                 0xb
#define SDMA0_STATUS4_REG__UTCL2_RD_XNACK__SHIFT                                                              0xc
#define SDMA0_STATUS4_REG__UTCL2_WR_XNACK__SHIFT                                                              0xe
#define SDMA0_STATUS4_REG__ACTIVE_QUEUE_ID__SHIFT                                                             0x10
#define SDMA0_STATUS4_REG__SRIOV_WATING_RLCV_CMD__SHIFT                                                       0x14
#define SDMA0_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD__SHIFT                                                    0x15
#define SDMA0_STATUS4_REG__IDLE_MASK                                                                          0x00000001L
#define SDMA0_STATUS4_REG__IH_OUTSTANDING_MASK                                                                0x00000004L
#define SDMA0_STATUS4_REG__SEM_OUTSTANDING_MASK                                                               0x00000008L
#define SDMA0_STATUS4_REG__CH_RD_OUTSTANDING_MASK                                                             0x00000010L
#define SDMA0_STATUS4_REG__CH_WR_OUTSTANDING_MASK                                                             0x00000020L
#define SDMA0_STATUS4_REG__GCR_OUTSTANDING_MASK                                                               0x00000040L
#define SDMA0_STATUS4_REG__TLBI_OUTSTANDING_MASK                                                              0x00000080L
#define SDMA0_STATUS4_REG__UTCL2_RD_OUTSTANDING_MASK                                                          0x00000100L
#define SDMA0_STATUS4_REG__UTCL2_WR_OUTSTANDING_MASK                                                          0x00000200L
#define SDMA0_STATUS4_REG__REG_POLLING_MASK                                                                   0x00000400L
#define SDMA0_STATUS4_REG__MEM_POLLING_MASK                                                                   0x00000800L
#define SDMA0_STATUS4_REG__UTCL2_RD_XNACK_MASK                                                                0x00003000L
#define SDMA0_STATUS4_REG__UTCL2_WR_XNACK_MASK                                                                0x0000C000L
#define SDMA0_STATUS4_REG__ACTIVE_QUEUE_ID_MASK                                                               0x000F0000L
#define SDMA0_STATUS4_REG__SRIOV_WATING_RLCV_CMD_MASK                                                         0x00100000L
#define SDMA0_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD_MASK                                                      0x00200000L
//SDMA0_SCRATCH_RAM_DATA
#define SDMA0_SCRATCH_RAM_DATA__DATA__SHIFT                                                                   0x0
#define SDMA0_SCRATCH_RAM_DATA__DATA_MASK                                                                     0xFFFFFFFFL
//SDMA0_SCRATCH_RAM_ADDR
#define SDMA0_SCRATCH_RAM_ADDR__ADDR__SHIFT                                                                   0x0
#define SDMA0_SCRATCH_RAM_ADDR__ADDR_MASK                                                                     0x000003FFL
//SDMA0_TIMESTAMP_CNTL
#define SDMA0_TIMESTAMP_CNTL__CAPTURE__SHIFT                                                                  0x0
#define SDMA0_TIMESTAMP_CNTL__CAPTURE_MASK                                                                    0x00000001L
//SDMA0_STATUS5_REG
#define SDMA0_STATUS5_REG__GFX_RB_ENABLE_STATUS__SHIFT                                                        0x0
#define SDMA0_STATUS5_REG__PAGE_RB_ENABLE_STATUS__SHIFT                                                       0x1
#define SDMA0_STATUS5_REG__RLC0_RB_ENABLE_STATUS__SHIFT                                                       0x2
#define SDMA0_STATUS5_REG__RLC1_RB_ENABLE_STATUS__SHIFT                                                       0x3
#define SDMA0_STATUS5_REG__RLC2_RB_ENABLE_STATUS__SHIFT                                                       0x4
#define SDMA0_STATUS5_REG__RLC3_RB_ENABLE_STATUS__SHIFT                                                       0x5
#define SDMA0_STATUS5_REG__RLC4_RB_ENABLE_STATUS__SHIFT                                                       0x6
#define SDMA0_STATUS5_REG__RLC5_RB_ENABLE_STATUS__SHIFT                                                       0x7
#define SDMA0_STATUS5_REG__RLC6_RB_ENABLE_STATUS__SHIFT                                                       0x8
#define SDMA0_STATUS5_REG__RLC7_RB_ENABLE_STATUS__SHIFT                                                       0x9
#define SDMA0_STATUS5_REG__ACTIVE_QUEUE_ID__SHIFT                                                             0x10
#define SDMA0_STATUS5_REG__GFX_RB_ENABLE_STATUS_MASK                                                          0x00000001L
#define SDMA0_STATUS5_REG__PAGE_RB_ENABLE_STATUS_MASK                                                         0x00000002L
#define SDMA0_STATUS5_REG__RLC0_RB_ENABLE_STATUS_MASK                                                         0x00000004L
#define SDMA0_STATUS5_REG__RLC1_RB_ENABLE_STATUS_MASK                                                         0x00000008L
#define SDMA0_STATUS5_REG__RLC2_RB_ENABLE_STATUS_MASK                                                         0x00000010L
#define SDMA0_STATUS5_REG__RLC3_RB_ENABLE_STATUS_MASK                                                         0x00000020L
#define SDMA0_STATUS5_REG__RLC4_RB_ENABLE_STATUS_MASK                                                         0x00000040L
#define SDMA0_STATUS5_REG__RLC5_RB_ENABLE_STATUS_MASK                                                         0x00000080L
#define SDMA0_STATUS5_REG__RLC6_RB_ENABLE_STATUS_MASK                                                         0x00000100L
#define SDMA0_STATUS5_REG__RLC7_RB_ENABLE_STATUS_MASK                                                         0x00000200L
#define SDMA0_STATUS5_REG__ACTIVE_QUEUE_ID_MASK                                                               0x000F0000L
//SDMA0_QUEUE_RESET_REQ
#define SDMA0_QUEUE_RESET_REQ__GFX_QUEUE_RESET__SHIFT                                                         0x0
#define SDMA0_QUEUE_RESET_REQ__PAGE_QUEUE_RESET__SHIFT                                                        0x1
#define SDMA0_QUEUE_RESET_REQ__RLC0_QUEUE_RESET__SHIFT                                                        0x2
#define SDMA0_QUEUE_RESET_REQ__RLC1_QUEUE_RESET__SHIFT                                                        0x3
#define SDMA0_QUEUE_RESET_REQ__RLC2_QUEUE_RESET__SHIFT                                                        0x4
#define SDMA0_QUEUE_RESET_REQ__RLC3_QUEUE_RESET__SHIFT                                                        0x5
#define SDMA0_QUEUE_RESET_REQ__RLC4_QUEUE_RESET__SHIFT                                                        0x6
#define SDMA0_QUEUE_RESET_REQ__RLC5_QUEUE_RESET__SHIFT                                                        0x7
#define SDMA0_QUEUE_RESET_REQ__RLC6_QUEUE_RESET__SHIFT                                                        0x8
#define SDMA0_QUEUE_RESET_REQ__RLC7_QUEUE_RESET__SHIFT                                                        0x9
#define SDMA0_QUEUE_RESET_REQ__RESERVED__SHIFT                                                                0xa
#define SDMA0_QUEUE_RESET_REQ__GFX_QUEUE_RESET_MASK                                                           0x00000001L
#define SDMA0_QUEUE_RESET_REQ__PAGE_QUEUE_RESET_MASK                                                          0x00000002L
#define SDMA0_QUEUE_RESET_REQ__RLC0_QUEUE_RESET_MASK                                                          0x00000004L
#define SDMA0_QUEUE_RESET_REQ__RLC1_QUEUE_RESET_MASK                                                          0x00000008L
#define SDMA0_QUEUE_RESET_REQ__RLC2_QUEUE_RESET_MASK                                                          0x00000010L
#define SDMA0_QUEUE_RESET_REQ__RLC3_QUEUE_RESET_MASK                                                          0x00000020L
#define SDMA0_QUEUE_RESET_REQ__RLC4_QUEUE_RESET_MASK                                                          0x00000040L
#define SDMA0_QUEUE_RESET_REQ__RLC5_QUEUE_RESET_MASK                                                          0x00000080L
#define SDMA0_QUEUE_RESET_REQ__RLC6_QUEUE_RESET_MASK                                                          0x00000100L
#define SDMA0_QUEUE_RESET_REQ__RLC7_QUEUE_RESET_MASK                                                          0x00000200L
#define SDMA0_QUEUE_RESET_REQ__RESERVED_MASK                                                                  0xFFFFFC00L
//SDMA0_GFX_RB_CNTL
#define SDMA0_GFX_RB_CNTL__RB_ENABLE__SHIFT                                                                   0x0
#define SDMA0_GFX_RB_CNTL__RB_SIZE__SHIFT                                                                     0x1
#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                              0x9
#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                       0xc
#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                  0xd
#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                        0x10
#define SDMA0_GFX_RB_CNTL__RB_PRIV__SHIFT                                                                     0x17
#define SDMA0_GFX_RB_CNTL__RB_VMID__SHIFT                                                                     0x18
#define SDMA0_GFX_RB_CNTL__RPTR_WB_IDLE__SHIFT                                                                0x1f
#define SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK                                                                     0x00000001L
#define SDMA0_GFX_RB_CNTL__RB_SIZE_MASK                                                                       0x0000003EL
#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK                                                                0x00000200L
#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                         0x00001000L
#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                    0x00002000L
#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                          0x001F0000L
#define SDMA0_GFX_RB_CNTL__RB_PRIV_MASK                                                                       0x00800000L
#define SDMA0_GFX_RB_CNTL__RB_VMID_MASK                                                                       0x0F000000L
#define SDMA0_GFX_RB_CNTL__RPTR_WB_IDLE_MASK                                                                  0x80000000L
//SDMA0_GFX_RB_BASE
#define SDMA0_GFX_RB_BASE__ADDR__SHIFT                                                                        0x0
#define SDMA0_GFX_RB_BASE__ADDR_MASK                                                                          0xFFFFFFFFL
//SDMA0_GFX_RB_BASE_HI
#define SDMA0_GFX_RB_BASE_HI__ADDR__SHIFT                                                                     0x0
#define SDMA0_GFX_RB_BASE_HI__ADDR_MASK                                                                       0x00FFFFFFL
//SDMA0_GFX_RB_RPTR
#define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT                                                                      0x0
#define SDMA0_GFX_RB_RPTR__OFFSET_MASK                                                                        0xFFFFFFFFL
//SDMA0_GFX_RB_RPTR_HI
#define SDMA0_GFX_RB_RPTR_HI__OFFSET__SHIFT                                                                   0x0
#define SDMA0_GFX_RB_RPTR_HI__OFFSET_MASK                                                                     0xFFFFFFFFL
//SDMA0_GFX_RB_WPTR
#define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT                                                                      0x0
#define SDMA0_GFX_RB_WPTR__OFFSET_MASK                                                                        0xFFFFFFFFL
//SDMA0_GFX_RB_WPTR_HI
#define SDMA0_GFX_RB_WPTR_HI__OFFSET__SHIFT                                                                   0x0
#define SDMA0_GFX_RB_WPTR_HI__OFFSET_MASK                                                                     0xFFFFFFFFL
//SDMA0_GFX_RB_WPTR_POLL_CNTL
#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                            0x0
#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                       0x1
#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                   0x2
#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                         0x4
#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                   0x10
#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                              0x00000001L
#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                         0x00000002L
#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                     0x00000004L
#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                           0x0000FFF0L
#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                     0xFFFF0000L
//SDMA0_GFX_RB_RPTR_ADDR_HI
#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                                0x0
#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR_MASK                                                                  0xFFFFFFFFL
//SDMA0_GFX_RB_RPTR_ADDR_LO
#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                                0x2
#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR_MASK                                                                  0xFFFFFFFCL
//SDMA0_GFX_IB_CNTL
#define SDMA0_GFX_IB_CNTL__IB_ENABLE__SHIFT                                                                   0x0
#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                              0x4
#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                            0x8
#define SDMA0_GFX_IB_CNTL__CMD_VMID__SHIFT                                                                    0x10
#define SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK                                                                     0x00000001L
#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK                                                                0x00000010L
#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                              0x00000100L
#define SDMA0_GFX_IB_CNTL__CMD_VMID_MASK                                                                      0x000F0000L
//SDMA0_GFX_IB_RPTR
#define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT                                                                      0x2
#define SDMA0_GFX_IB_RPTR__OFFSET_MASK                                                                        0x003FFFFCL
//SDMA0_GFX_IB_OFFSET
#define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT                                                                    0x2
#define SDMA0_GFX_IB_OFFSET__OFFSET_MASK                                                                      0x003FFFFCL
//SDMA0_GFX_IB_BASE_LO
#define SDMA0_GFX_IB_BASE_LO__ADDR__SHIFT                                                                     0x5
#define SDMA0_GFX_IB_BASE_LO__ADDR_MASK                                                                       0xFFFFFFE0L
//SDMA0_GFX_IB_BASE_HI
#define SDMA0_GFX_IB_BASE_HI__ADDR__SHIFT                                                                     0x0
#define SDMA0_GFX_IB_BASE_HI__ADDR_MASK                                                                       0xFFFFFFFFL
//SDMA0_GFX_IB_SIZE
#define SDMA0_GFX_IB_SIZE__SIZE__SHIFT                                                                        0x0
#define SDMA0_GFX_IB_SIZE__SIZE_MASK                                                                          0x000FFFFFL
//SDMA0_GFX_SKIP_CNTL
#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT                                                                0x0
#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT_MASK                                                                  0x000FFFFFL
//SDMA0_GFX_CONTEXT_STATUS
#define SDMA0_GFX_CONTEXT_STATUS__SELECTED__SHIFT                                                             0x0
#define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT                                                                 0x2
#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED__SHIFT                                                              0x3
#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT                                                            0x4
#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                           0x7
#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                          0x8
#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT                                                            0x9
#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                      0xa
#define SDMA0_GFX_CONTEXT_STATUS__SELECTED_MASK                                                               0x00000001L
#define SDMA0_GFX_CONTEXT_STATUS__IDLE_MASK                                                                   0x00000004L
#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED_MASK                                                                0x00000008L
#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION_MASK                                                              0x00000070L
#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                             0x00000080L
#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY_MASK                                                            0x00000100L
#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED_MASK                                                              0x00000200L
#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                        0x00000400L
//SDMA0_GFX_DOORBELL
#define SDMA0_GFX_DOORBELL__ENABLE__SHIFT                                                                     0x1c
#define SDMA0_GFX_DOORBELL__CAPTURED__SHIFT                                                                   0x1e
#define SDMA0_GFX_DOORBELL__ENABLE_MASK                                                                       0x10000000L
#define SDMA0_GFX_DOORBELL__CAPTURED_MASK                                                                     0x40000000L
//SDMA0_GFX_CONTEXT_CNTL
#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT                                                             0x10
#define SDMA0_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT                                                            0x18
#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX_MASK                                                               0x00010000L
#define SDMA0_GFX_CONTEXT_CNTL__SESSION_SEL_MASK                                                              0x0F000000L
//SDMA0_GFX_STATUS
#define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                       0x0
#define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                          0x8
#define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                         0x000000FFL
#define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING_MASK                                                            0x00000100L
//SDMA0_GFX_DOORBELL_LOG
#define SDMA0_GFX_DOORBELL_LOG__BE_ERROR__SHIFT                                                               0x0
#define SDMA0_GFX_DOORBELL_LOG__DATA__SHIFT                                                                   0x2
#define SDMA0_GFX_DOORBELL_LOG__BE_ERROR_MASK                                                                 0x00000001L
#define SDMA0_GFX_DOORBELL_LOG__DATA_MASK                                                                     0xFFFFFFFCL
//SDMA0_GFX_WATERMARK
#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING__SHIFT                                                            0x0
#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING__SHIFT                                                            0x10
#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING_MASK                                                              0x00000FFFL
#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING_MASK                                                              0x03FF0000L
//SDMA0_GFX_DOORBELL_OFFSET
#define SDMA0_GFX_DOORBELL_OFFSET__OFFSET__SHIFT                                                              0x2
#define SDMA0_GFX_DOORBELL_OFFSET__OFFSET_MASK                                                                0x0FFFFFFCL
//SDMA0_GFX_CSA_ADDR_LO
#define SDMA0_GFX_CSA_ADDR_LO__ADDR__SHIFT                                                                    0x2
#define SDMA0_GFX_CSA_ADDR_LO__ADDR_MASK                                                                      0xFFFFFFFCL
//SDMA0_GFX_CSA_ADDR_HI
#define SDMA0_GFX_CSA_ADDR_HI__ADDR__SHIFT                                                                    0x0
#define SDMA0_GFX_CSA_ADDR_HI__ADDR_MASK                                                                      0xFFFFFFFFL
//SDMA0_GFX_IB_SUB_REMAIN
#define SDMA0_GFX_IB_SUB_REMAIN__SIZE__SHIFT                                                                  0x0
#define SDMA0_GFX_IB_SUB_REMAIN__SIZE_MASK                                                                    0x00003FFFL
//SDMA0_GFX_PREEMPT
#define SDMA0_GFX_PREEMPT__IB_PREEMPT__SHIFT                                                                  0x0
#define SDMA0_GFX_PREEMPT__IB_PREEMPT_MASK                                                                    0x00000001L
//SDMA0_GFX_DUMMY_REG
#define SDMA0_GFX_DUMMY_REG__DUMMY__SHIFT                                                                     0x0
#define SDMA0_GFX_DUMMY_REG__DUMMY_MASK                                                                       0xFFFFFFFFL
//SDMA0_GFX_RB_WPTR_POLL_ADDR_HI
#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                           0x0
#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                             0xFFFFFFFFL
//SDMA0_GFX_RB_WPTR_POLL_ADDR_LO
#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                           0x2
#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                             0xFFFFFFFCL
//SDMA0_GFX_RB_AQL_CNTL
#define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                              0x0
#define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                         0x1
#define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                             0x8
#define SDMA0_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                   0x10
#define SDMA0_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT                                             0x11
#define SDMA0_GFX_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT                                                          0x12
#define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK                                                                0x00000001L
#define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                           0x000000FEL
#define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP_MASK                                                               0x0000FF00L
#define SDMA0_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                     0x00010000L
#define SDMA0_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK                                               0x00020000L
#define SDMA0_GFX_RB_AQL_CNTL__OVERLAP_ENABLE_MASK                                                            0x00040000L
//SDMA0_GFX_MINOR_PTR_UPDATE
#define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                             0x0
#define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE_MASK                                                               0x00000001L
//SDMA0_GFX_MIDCMD_DATA0
#define SDMA0_GFX_MIDCMD_DATA0__DATA0__SHIFT                                                                  0x0
#define SDMA0_GFX_MIDCMD_DATA0__DATA0_MASK                                                                    0xFFFFFFFFL
//SDMA0_GFX_MIDCMD_DATA1
#define SDMA0_GFX_MIDCMD_DATA1__DATA1__SHIFT                                                                  0x0
#define SDMA0_GFX_MIDCMD_DATA1__DATA1_MASK                                                                    0xFFFFFFFFL
//SDMA0_GFX_MIDCMD_DATA2
#define SDMA0_GFX_MIDCMD_DATA2__DATA2__SHIFT                                                                  0x0
#define SDMA0_GFX_MIDCMD_DATA2__DATA2_MASK                                                                    0xFFFFFFFFL
//SDMA0_GFX_MIDCMD_DATA3
#define SDMA0_GFX_MIDCMD_DATA3__DATA3__SHIFT                                                                  0x0
#define SDMA0_GFX_MIDCMD_DATA3__DATA3_MASK                                                                    0xFFFFFFFFL
//SDMA0_GFX_MIDCMD_DATA4
#define SDMA0_GFX_MIDCMD_DATA4__DATA4__SHIFT                                                                  0x0
#define SDMA0_GFX_MIDCMD_DATA4__DATA4_MASK                                                                    0xFFFFFFFFL
//SDMA0_GFX_MIDCMD_DATA5
#define SDMA0_GFX_MIDCMD_DATA5__DATA5__SHIFT                                                                  0x0
#define SDMA0_GFX_MIDCMD_DATA5__DATA5_MASK                                                                    0xFFFFFFFFL
//SDMA0_GFX_MIDCMD_DATA6
#define SDMA0_GFX_MIDCMD_DATA6__DATA6__SHIFT                                                                  0x0
#define SDMA0_GFX_MIDCMD_DATA6__DATA6_MASK                                                                    0xFFFFFFFFL
//SDMA0_GFX_MIDCMD_DATA7
#define SDMA0_GFX_MIDCMD_DATA7__DATA7__SHIFT                                                                  0x0
#define SDMA0_GFX_MIDCMD_DATA7__DATA7_MASK                                                                    0xFFFFFFFFL
//SDMA0_GFX_MIDCMD_DATA8
#define SDMA0_GFX_MIDCMD_DATA8__DATA8__SHIFT                                                                  0x0
#define SDMA0_GFX_MIDCMD_DATA8__DATA8_MASK                                                                    0xFFFFFFFFL
//SDMA0_GFX_MIDCMD_DATA9
#define SDMA0_GFX_MIDCMD_DATA9__DATA9__SHIFT                                                                  0x0
#define SDMA0_GFX_MIDCMD_DATA9__DATA9_MASK                                                                    0xFFFFFFFFL
//SDMA0_GFX_MIDCMD_DATA10
#define SDMA0_GFX_MIDCMD_DATA10__DATA10__SHIFT                                                                0x0
#define SDMA0_GFX_MIDCMD_DATA10__DATA10_MASK                                                                  0xFFFFFFFFL
//SDMA0_GFX_MIDCMD_CNTL
#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT                                                              0x0
#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT                                                               0x1
#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                             0x4
#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                           0x8
#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID_MASK                                                                0x00000001L
#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE_MASK                                                                 0x00000002L
#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK                                                               0x000000F0L
#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                             0x00000100L
//SDMA0_PAGE_RB_CNTL
#define SDMA0_PAGE_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
#define SDMA0_PAGE_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
#define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
#define SDMA0_PAGE_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
#define SDMA0_PAGE_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
#define SDMA0_PAGE_RB_CNTL__RPTR_WB_IDLE__SHIFT                                                               0x1f
#define SDMA0_PAGE_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
#define SDMA0_PAGE_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
#define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
#define SDMA0_PAGE_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
#define SDMA0_PAGE_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
#define SDMA0_PAGE_RB_CNTL__RPTR_WB_IDLE_MASK                                                                 0x80000000L
//SDMA0_PAGE_RB_BASE
#define SDMA0_PAGE_RB_BASE__ADDR__SHIFT                                                                       0x0
#define SDMA0_PAGE_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
//SDMA0_PAGE_RB_BASE_HI
#define SDMA0_PAGE_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA0_PAGE_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
//SDMA0_PAGE_RB_RPTR
#define SDMA0_PAGE_RB_RPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA0_PAGE_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA0_PAGE_RB_RPTR_HI
#define SDMA0_PAGE_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA0_PAGE_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA0_PAGE_RB_WPTR
#define SDMA0_PAGE_RB_WPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA0_PAGE_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA0_PAGE_RB_WPTR_HI
#define SDMA0_PAGE_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA0_PAGE_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA0_PAGE_RB_WPTR_POLL_CNTL
#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
//SDMA0_PAGE_RB_RPTR_ADDR_HI
#define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
#define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
//SDMA0_PAGE_RB_RPTR_ADDR_LO
#define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
#define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
//SDMA0_PAGE_IB_CNTL
#define SDMA0_PAGE_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
#define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
#define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
#define SDMA0_PAGE_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
#define SDMA0_PAGE_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
#define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
#define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
#define SDMA0_PAGE_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
//SDMA0_PAGE_IB_RPTR
#define SDMA0_PAGE_IB_RPTR__OFFSET__SHIFT                                                                     0x2
#define SDMA0_PAGE_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
//SDMA0_PAGE_IB_OFFSET
#define SDMA0_PAGE_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
#define SDMA0_PAGE_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
//SDMA0_PAGE_IB_BASE_LO
#define SDMA0_PAGE_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
#define SDMA0_PAGE_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
//SDMA0_PAGE_IB_BASE_HI
#define SDMA0_PAGE_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA0_PAGE_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
//SDMA0_PAGE_IB_SIZE
#define SDMA0_PAGE_IB_SIZE__SIZE__SHIFT                                                                       0x0
#define SDMA0_PAGE_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
//SDMA0_PAGE_SKIP_CNTL
#define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
#define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
//SDMA0_PAGE_CONTEXT_STATUS
#define SDMA0_PAGE_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
#define SDMA0_PAGE_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
#define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
#define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
#define SDMA0_PAGE_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
#define SDMA0_PAGE_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
#define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
#define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
//SDMA0_PAGE_DOORBELL
#define SDMA0_PAGE_DOORBELL__ENABLE__SHIFT                                                                    0x1c
#define SDMA0_PAGE_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
#define SDMA0_PAGE_DOORBELL__ENABLE_MASK                                                                      0x10000000L
#define SDMA0_PAGE_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
//SDMA0_PAGE_STATUS
#define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
#define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
#define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
#define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
//SDMA0_PAGE_DOORBELL_LOG
#define SDMA0_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
#define SDMA0_PAGE_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
#define SDMA0_PAGE_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
#define SDMA0_PAGE_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
//SDMA0_PAGE_WATERMARK
#define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
#define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
#define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
#define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
//SDMA0_PAGE_DOORBELL_OFFSET
#define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
#define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
//SDMA0_PAGE_CSA_ADDR_LO
#define SDMA0_PAGE_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
#define SDMA0_PAGE_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
//SDMA0_PAGE_CSA_ADDR_HI
#define SDMA0_PAGE_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
#define SDMA0_PAGE_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
//SDMA0_PAGE_IB_SUB_REMAIN
#define SDMA0_PAGE_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
#define SDMA0_PAGE_IB_SUB_REMAIN__SIZE_MASK                                                                   0x00003FFFL
//SDMA0_PAGE_PREEMPT
#define SDMA0_PAGE_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
#define SDMA0_PAGE_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
//SDMA0_PAGE_DUMMY_REG
#define SDMA0_PAGE_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
#define SDMA0_PAGE_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
//SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI
#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
//SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO
#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
//SDMA0_PAGE_RB_AQL_CNTL
#define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
#define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
#define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
#define SDMA0_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                  0x10
#define SDMA0_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT                                            0x11
#define SDMA0_PAGE_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT                                                         0x12
#define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
#define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
#define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
#define SDMA0_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                    0x00010000L
#define SDMA0_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK                                              0x00020000L
#define SDMA0_PAGE_RB_AQL_CNTL__OVERLAP_ENABLE_MASK                                                           0x00040000L
//SDMA0_PAGE_MINOR_PTR_UPDATE
#define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
#define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
//SDMA0_PAGE_MIDCMD_DATA0
#define SDMA0_PAGE_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
#define SDMA0_PAGE_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
//SDMA0_PAGE_MIDCMD_DATA1
#define SDMA0_PAGE_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
#define SDMA0_PAGE_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
//SDMA0_PAGE_MIDCMD_DATA2
#define SDMA0_PAGE_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
#define SDMA0_PAGE_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
//SDMA0_PAGE_MIDCMD_DATA3
#define SDMA0_PAGE_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
#define SDMA0_PAGE_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
//SDMA0_PAGE_MIDCMD_DATA4
#define SDMA0_PAGE_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
#define SDMA0_PAGE_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
//SDMA0_PAGE_MIDCMD_DATA5
#define SDMA0_PAGE_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
#define SDMA0_PAGE_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
//SDMA0_PAGE_MIDCMD_DATA6
#define SDMA0_PAGE_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
#define SDMA0_PAGE_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
//SDMA0_PAGE_MIDCMD_DATA7
#define SDMA0_PAGE_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
#define SDMA0_PAGE_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
//SDMA0_PAGE_MIDCMD_DATA8
#define SDMA0_PAGE_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
#define SDMA0_PAGE_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
//SDMA0_PAGE_MIDCMD_DATA9
#define SDMA0_PAGE_MIDCMD_DATA9__DATA9__SHIFT                                                                 0x0
#define SDMA0_PAGE_MIDCMD_DATA9__DATA9_MASK                                                                   0xFFFFFFFFL
//SDMA0_PAGE_MIDCMD_DATA10
#define SDMA0_PAGE_MIDCMD_DATA10__DATA10__SHIFT                                                               0x0
#define SDMA0_PAGE_MIDCMD_DATA10__DATA10_MASK                                                                 0xFFFFFFFFL
//SDMA0_PAGE_MIDCMD_CNTL
#define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
#define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
#define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
#define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
#define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
#define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
#define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
#define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
//SDMA0_RLC0_RB_CNTL
#define SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
#define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
#define SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
#define SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
#define SDMA0_RLC0_RB_CNTL__RPTR_WB_IDLE__SHIFT                                                               0x1f
#define SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
#define SDMA0_RLC0_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
#define SDMA0_RLC0_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
#define SDMA0_RLC0_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
#define SDMA0_RLC0_RB_CNTL__RPTR_WB_IDLE_MASK                                                                 0x80000000L
//SDMA0_RLC0_RB_BASE
#define SDMA0_RLC0_RB_BASE__ADDR__SHIFT                                                                       0x0
#define SDMA0_RLC0_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
//SDMA0_RLC0_RB_BASE_HI
#define SDMA0_RLC0_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA0_RLC0_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
//SDMA0_RLC0_RB_RPTR
#define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA0_RLC0_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA0_RLC0_RB_RPTR_HI
#define SDMA0_RLC0_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA0_RLC0_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA0_RLC0_RB_WPTR
#define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA0_RLC0_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA0_RLC0_RB_WPTR_HI
#define SDMA0_RLC0_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA0_RLC0_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA0_RLC0_RB_WPTR_POLL_CNTL
#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
//SDMA0_RLC0_RB_RPTR_ADDR_HI
#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
//SDMA0_RLC0_RB_RPTR_ADDR_LO
#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
//SDMA0_RLC0_IB_CNTL
#define SDMA0_RLC0_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
#define SDMA0_RLC0_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
#define SDMA0_RLC0_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
#define SDMA0_RLC0_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
//SDMA0_RLC0_IB_RPTR
#define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT                                                                     0x2
#define SDMA0_RLC0_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
//SDMA0_RLC0_IB_OFFSET
#define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
#define SDMA0_RLC0_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
//SDMA0_RLC0_IB_BASE_LO
#define SDMA0_RLC0_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
#define SDMA0_RLC0_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
//SDMA0_RLC0_IB_BASE_HI
#define SDMA0_RLC0_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA0_RLC0_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
//SDMA0_RLC0_IB_SIZE
#define SDMA0_RLC0_IB_SIZE__SIZE__SHIFT                                                                       0x0
#define SDMA0_RLC0_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
//SDMA0_RLC0_SKIP_CNTL
#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
//SDMA0_RLC0_CONTEXT_STATUS
#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
#define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
#define SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
//SDMA0_RLC0_DOORBELL
#define SDMA0_RLC0_DOORBELL__ENABLE__SHIFT                                                                    0x1c
#define SDMA0_RLC0_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
#define SDMA0_RLC0_DOORBELL__ENABLE_MASK                                                                      0x10000000L
#define SDMA0_RLC0_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
//SDMA0_RLC0_STATUS
#define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
#define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
#define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
#define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
//SDMA0_RLC0_DOORBELL_LOG
#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
#define SDMA0_RLC0_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
#define SDMA0_RLC0_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
//SDMA0_RLC0_WATERMARK
#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
//SDMA0_RLC0_DOORBELL_OFFSET
#define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
#define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
//SDMA0_RLC0_CSA_ADDR_LO
#define SDMA0_RLC0_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
#define SDMA0_RLC0_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
//SDMA0_RLC0_CSA_ADDR_HI
#define SDMA0_RLC0_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
#define SDMA0_RLC0_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
//SDMA0_RLC0_IB_SUB_REMAIN
#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE_MASK                                                                   0x00003FFFL
//SDMA0_RLC0_PREEMPT
#define SDMA0_RLC0_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
#define SDMA0_RLC0_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
//SDMA0_RLC0_DUMMY_REG
#define SDMA0_RLC0_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
#define SDMA0_RLC0_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
//SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI
#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
//SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO
#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
//SDMA0_RLC0_RB_AQL_CNTL
#define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
#define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
#define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
#define SDMA0_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                  0x10
#define SDMA0_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT                                            0x11
#define SDMA0_RLC0_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT                                                         0x12
#define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
#define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
#define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
#define SDMA0_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                    0x00010000L
#define SDMA0_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK                                              0x00020000L
#define SDMA0_RLC0_RB_AQL_CNTL__OVERLAP_ENABLE_MASK                                                           0x00040000L
//SDMA0_RLC0_MINOR_PTR_UPDATE
#define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
#define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
//SDMA0_RLC0_MIDCMD_DATA0
#define SDMA0_RLC0_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
#define SDMA0_RLC0_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC0_MIDCMD_DATA1
#define SDMA0_RLC0_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
#define SDMA0_RLC0_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC0_MIDCMD_DATA2
#define SDMA0_RLC0_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
#define SDMA0_RLC0_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC0_MIDCMD_DATA3
#define SDMA0_RLC0_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
#define SDMA0_RLC0_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC0_MIDCMD_DATA4
#define SDMA0_RLC0_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
#define SDMA0_RLC0_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC0_MIDCMD_DATA5
#define SDMA0_RLC0_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
#define SDMA0_RLC0_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC0_MIDCMD_DATA6
#define SDMA0_RLC0_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
#define SDMA0_RLC0_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC0_MIDCMD_DATA7
#define SDMA0_RLC0_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
#define SDMA0_RLC0_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC0_MIDCMD_DATA8
#define SDMA0_RLC0_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
#define SDMA0_RLC0_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC0_MIDCMD_DATA9
#define SDMA0_RLC0_MIDCMD_DATA9__DATA9__SHIFT                                                                 0x0
#define SDMA0_RLC0_MIDCMD_DATA9__DATA9_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC0_MIDCMD_DATA10
#define SDMA0_RLC0_MIDCMD_DATA10__DATA10__SHIFT                                                               0x0
#define SDMA0_RLC0_MIDCMD_DATA10__DATA10_MASK                                                                 0xFFFFFFFFL
//SDMA0_RLC0_MIDCMD_CNTL
#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
//SDMA0_RLC1_RB_CNTL
#define SDMA0_RLC1_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
#define SDMA0_RLC1_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
#define SDMA0_RLC1_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
#define SDMA0_RLC1_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
#define SDMA0_RLC1_RB_CNTL__RPTR_WB_IDLE__SHIFT                                                               0x1f
#define SDMA0_RLC1_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
#define SDMA0_RLC1_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
#define SDMA0_RLC1_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
#define SDMA0_RLC1_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
#define SDMA0_RLC1_RB_CNTL__RPTR_WB_IDLE_MASK                                                                 0x80000000L
//SDMA0_RLC1_RB_BASE
#define SDMA0_RLC1_RB_BASE__ADDR__SHIFT                                                                       0x0
#define SDMA0_RLC1_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
//SDMA0_RLC1_RB_BASE_HI
#define SDMA0_RLC1_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA0_RLC1_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
//SDMA0_RLC1_RB_RPTR
#define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA0_RLC1_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA0_RLC1_RB_RPTR_HI
#define SDMA0_RLC1_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA0_RLC1_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA0_RLC1_RB_WPTR
#define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA0_RLC1_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA0_RLC1_RB_WPTR_HI
#define SDMA0_RLC1_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA0_RLC1_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA0_RLC1_RB_WPTR_POLL_CNTL
#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
//SDMA0_RLC1_RB_RPTR_ADDR_HI
#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
//SDMA0_RLC1_RB_RPTR_ADDR_LO
#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
//SDMA0_RLC1_IB_CNTL
#define SDMA0_RLC1_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
#define SDMA0_RLC1_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
#define SDMA0_RLC1_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
#define SDMA0_RLC1_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
//SDMA0_RLC1_IB_RPTR
#define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT                                                                     0x2
#define SDMA0_RLC1_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
//SDMA0_RLC1_IB_OFFSET
#define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
#define SDMA0_RLC1_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
//SDMA0_RLC1_IB_BASE_LO
#define SDMA0_RLC1_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
#define SDMA0_RLC1_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
//SDMA0_RLC1_IB_BASE_HI
#define SDMA0_RLC1_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA0_RLC1_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
//SDMA0_RLC1_IB_SIZE
#define SDMA0_RLC1_IB_SIZE__SIZE__SHIFT                                                                       0x0
#define SDMA0_RLC1_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
//SDMA0_RLC1_SKIP_CNTL
#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
//SDMA0_RLC1_CONTEXT_STATUS
#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
#define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
#define SDMA0_RLC1_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
//SDMA0_RLC1_DOORBELL
#define SDMA0_RLC1_DOORBELL__ENABLE__SHIFT                                                                    0x1c
#define SDMA0_RLC1_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
#define SDMA0_RLC1_DOORBELL__ENABLE_MASK                                                                      0x10000000L
#define SDMA0_RLC1_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
//SDMA0_RLC1_STATUS
#define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
#define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
#define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
#define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
//SDMA0_RLC1_DOORBELL_LOG
#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
#define SDMA0_RLC1_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
#define SDMA0_RLC1_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
//SDMA0_RLC1_WATERMARK
#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
//SDMA0_RLC1_DOORBELL_OFFSET
#define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
#define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
//SDMA0_RLC1_CSA_ADDR_LO
#define SDMA0_RLC1_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
#define SDMA0_RLC1_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
//SDMA0_RLC1_CSA_ADDR_HI
#define SDMA0_RLC1_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
#define SDMA0_RLC1_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
//SDMA0_RLC1_IB_SUB_REMAIN
#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE_MASK                                                                   0x00003FFFL
//SDMA0_RLC1_PREEMPT
#define SDMA0_RLC1_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
#define SDMA0_RLC1_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
//SDMA0_RLC1_DUMMY_REG
#define SDMA0_RLC1_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
#define SDMA0_RLC1_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
//SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI
#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
//SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO
#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
//SDMA0_RLC1_RB_AQL_CNTL
#define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
#define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
#define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
#define SDMA0_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                  0x10
#define SDMA0_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT                                            0x11
#define SDMA0_RLC1_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT                                                         0x12
#define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
#define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
#define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
#define SDMA0_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                    0x00010000L
#define SDMA0_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK                                              0x00020000L
#define SDMA0_RLC1_RB_AQL_CNTL__OVERLAP_ENABLE_MASK                                                           0x00040000L
//SDMA0_RLC1_MINOR_PTR_UPDATE
#define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
#define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
//SDMA0_RLC1_MIDCMD_DATA0
#define SDMA0_RLC1_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
#define SDMA0_RLC1_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC1_MIDCMD_DATA1
#define SDMA0_RLC1_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
#define SDMA0_RLC1_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC1_MIDCMD_DATA2
#define SDMA0_RLC1_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
#define SDMA0_RLC1_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC1_MIDCMD_DATA3
#define SDMA0_RLC1_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
#define SDMA0_RLC1_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC1_MIDCMD_DATA4
#define SDMA0_RLC1_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
#define SDMA0_RLC1_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC1_MIDCMD_DATA5
#define SDMA0_RLC1_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
#define SDMA0_RLC1_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC1_MIDCMD_DATA6
#define SDMA0_RLC1_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
#define SDMA0_RLC1_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC1_MIDCMD_DATA7
#define SDMA0_RLC1_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
#define SDMA0_RLC1_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC1_MIDCMD_DATA8
#define SDMA0_RLC1_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
#define SDMA0_RLC1_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC1_MIDCMD_DATA9
#define SDMA0_RLC1_MIDCMD_DATA9__DATA9__SHIFT                                                                 0x0
#define SDMA0_RLC1_MIDCMD_DATA9__DATA9_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC1_MIDCMD_DATA10
#define SDMA0_RLC1_MIDCMD_DATA10__DATA10__SHIFT                                                               0x0
#define SDMA0_RLC1_MIDCMD_DATA10__DATA10_MASK                                                                 0xFFFFFFFFL
//SDMA0_RLC1_MIDCMD_CNTL
#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
//SDMA0_RLC2_RB_CNTL
#define SDMA0_RLC2_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
#define SDMA0_RLC2_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
#define SDMA0_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
#define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
#define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
#define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
#define SDMA0_RLC2_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
#define SDMA0_RLC2_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
#define SDMA0_RLC2_RB_CNTL__RPTR_WB_IDLE__SHIFT                                                               0x1f
#define SDMA0_RLC2_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
#define SDMA0_RLC2_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
#define SDMA0_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
#define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
#define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
#define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
#define SDMA0_RLC2_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
#define SDMA0_RLC2_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
#define SDMA0_RLC2_RB_CNTL__RPTR_WB_IDLE_MASK                                                                 0x80000000L
//SDMA0_RLC2_RB_BASE
#define SDMA0_RLC2_RB_BASE__ADDR__SHIFT                                                                       0x0
#define SDMA0_RLC2_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
//SDMA0_RLC2_RB_BASE_HI
#define SDMA0_RLC2_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA0_RLC2_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
//SDMA0_RLC2_RB_RPTR
#define SDMA0_RLC2_RB_RPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA0_RLC2_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA0_RLC2_RB_RPTR_HI
#define SDMA0_RLC2_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA0_RLC2_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA0_RLC2_RB_WPTR
#define SDMA0_RLC2_RB_WPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA0_RLC2_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA0_RLC2_RB_WPTR_HI
#define SDMA0_RLC2_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA0_RLC2_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA0_RLC2_RB_WPTR_POLL_CNTL
#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
//SDMA0_RLC2_RB_RPTR_ADDR_HI
#define SDMA0_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
#define SDMA0_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
//SDMA0_RLC2_RB_RPTR_ADDR_LO
#define SDMA0_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
#define SDMA0_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
//SDMA0_RLC2_IB_CNTL
#define SDMA0_RLC2_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
#define SDMA0_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
#define SDMA0_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
#define SDMA0_RLC2_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
#define SDMA0_RLC2_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
#define SDMA0_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
#define SDMA0_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
#define SDMA0_RLC2_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
//SDMA0_RLC2_IB_RPTR
#define SDMA0_RLC2_IB_RPTR__OFFSET__SHIFT                                                                     0x2
#define SDMA0_RLC2_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
//SDMA0_RLC2_IB_OFFSET
#define SDMA0_RLC2_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
#define SDMA0_RLC2_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
//SDMA0_RLC2_IB_BASE_LO
#define SDMA0_RLC2_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
#define SDMA0_RLC2_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
//SDMA0_RLC2_IB_BASE_HI
#define SDMA0_RLC2_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA0_RLC2_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
//SDMA0_RLC2_IB_SIZE
#define SDMA0_RLC2_IB_SIZE__SIZE__SHIFT                                                                       0x0
#define SDMA0_RLC2_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
//SDMA0_RLC2_SKIP_CNTL
#define SDMA0_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
#define SDMA0_RLC2_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
//SDMA0_RLC2_CONTEXT_STATUS
#define SDMA0_RLC2_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
#define SDMA0_RLC2_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
#define SDMA0_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
#define SDMA0_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
#define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
#define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
#define SDMA0_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
#define SDMA0_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
#define SDMA0_RLC2_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
#define SDMA0_RLC2_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
#define SDMA0_RLC2_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
#define SDMA0_RLC2_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
#define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
#define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
#define SDMA0_RLC2_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
#define SDMA0_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
//SDMA0_RLC2_DOORBELL
#define SDMA0_RLC2_DOORBELL__ENABLE__SHIFT                                                                    0x1c
#define SDMA0_RLC2_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
#define SDMA0_RLC2_DOORBELL__ENABLE_MASK                                                                      0x10000000L
#define SDMA0_RLC2_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
//SDMA0_RLC2_STATUS
#define SDMA0_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
#define SDMA0_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
#define SDMA0_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
#define SDMA0_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
//SDMA0_RLC2_DOORBELL_LOG
#define SDMA0_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
#define SDMA0_RLC2_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
#define SDMA0_RLC2_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
#define SDMA0_RLC2_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
//SDMA0_RLC2_WATERMARK
#define SDMA0_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
#define SDMA0_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
#define SDMA0_RLC2_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
#define SDMA0_RLC2_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
//SDMA0_RLC2_DOORBELL_OFFSET
#define SDMA0_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
#define SDMA0_RLC2_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
//SDMA0_RLC2_CSA_ADDR_LO
#define SDMA0_RLC2_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
#define SDMA0_RLC2_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
//SDMA0_RLC2_CSA_ADDR_HI
#define SDMA0_RLC2_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
#define SDMA0_RLC2_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
//SDMA0_RLC2_IB_SUB_REMAIN
#define SDMA0_RLC2_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
#define SDMA0_RLC2_IB_SUB_REMAIN__SIZE_MASK                                                                   0x00003FFFL
//SDMA0_RLC2_PREEMPT
#define SDMA0_RLC2_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
#define SDMA0_RLC2_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
//SDMA0_RLC2_DUMMY_REG
#define SDMA0_RLC2_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
#define SDMA0_RLC2_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
//SDMA0_RLC2_RB_WPTR_POLL_ADDR_HI
#define SDMA0_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
#define SDMA0_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
//SDMA0_RLC2_RB_WPTR_POLL_ADDR_LO
#define SDMA0_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
#define SDMA0_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
//SDMA0_RLC2_RB_AQL_CNTL
#define SDMA0_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
#define SDMA0_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
#define SDMA0_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
#define SDMA0_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                  0x10
#define SDMA0_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT                                            0x11
#define SDMA0_RLC2_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT                                                         0x12
#define SDMA0_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
#define SDMA0_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
#define SDMA0_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
#define SDMA0_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                    0x00010000L
#define SDMA0_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK                                              0x00020000L
#define SDMA0_RLC2_RB_AQL_CNTL__OVERLAP_ENABLE_MASK                                                           0x00040000L
//SDMA0_RLC2_MINOR_PTR_UPDATE
#define SDMA0_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
#define SDMA0_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
//SDMA0_RLC2_MIDCMD_DATA0
#define SDMA0_RLC2_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
#define SDMA0_RLC2_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC2_MIDCMD_DATA1
#define SDMA0_RLC2_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
#define SDMA0_RLC2_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC2_MIDCMD_DATA2
#define SDMA0_RLC2_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
#define SDMA0_RLC2_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC2_MIDCMD_DATA3
#define SDMA0_RLC2_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
#define SDMA0_RLC2_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC2_MIDCMD_DATA4
#define SDMA0_RLC2_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
#define SDMA0_RLC2_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC2_MIDCMD_DATA5
#define SDMA0_RLC2_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
#define SDMA0_RLC2_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC2_MIDCMD_DATA6
#define SDMA0_RLC2_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
#define SDMA0_RLC2_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC2_MIDCMD_DATA7
#define SDMA0_RLC2_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
#define SDMA0_RLC2_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC2_MIDCMD_DATA8
#define SDMA0_RLC2_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
#define SDMA0_RLC2_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC2_MIDCMD_DATA9
#define SDMA0_RLC2_MIDCMD_DATA9__DATA9__SHIFT                                                                 0x0
#define SDMA0_RLC2_MIDCMD_DATA9__DATA9_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC2_MIDCMD_DATA10
#define SDMA0_RLC2_MIDCMD_DATA10__DATA10__SHIFT                                                               0x0
#define SDMA0_RLC2_MIDCMD_DATA10__DATA10_MASK                                                                 0xFFFFFFFFL
//SDMA0_RLC2_MIDCMD_CNTL
#define SDMA0_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
#define SDMA0_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
#define SDMA0_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
#define SDMA0_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
#define SDMA0_RLC2_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
#define SDMA0_RLC2_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
#define SDMA0_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
#define SDMA0_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
//SDMA0_RLC3_RB_CNTL
#define SDMA0_RLC3_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
#define SDMA0_RLC3_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
#define SDMA0_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
#define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
#define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
#define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
#define SDMA0_RLC3_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
#define SDMA0_RLC3_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
#define SDMA0_RLC3_RB_CNTL__RPTR_WB_IDLE__SHIFT                                                               0x1f
#define SDMA0_RLC3_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
#define SDMA0_RLC3_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
#define SDMA0_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
#define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
#define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
#define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
#define SDMA0_RLC3_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
#define SDMA0_RLC3_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
#define SDMA0_RLC3_RB_CNTL__RPTR_WB_IDLE_MASK                                                                 0x80000000L
//SDMA0_RLC3_RB_BASE
#define SDMA0_RLC3_RB_BASE__ADDR__SHIFT                                                                       0x0
#define SDMA0_RLC3_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
//SDMA0_RLC3_RB_BASE_HI
#define SDMA0_RLC3_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA0_RLC3_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
//SDMA0_RLC3_RB_RPTR
#define SDMA0_RLC3_RB_RPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA0_RLC3_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA0_RLC3_RB_RPTR_HI
#define SDMA0_RLC3_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA0_RLC3_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA0_RLC3_RB_WPTR
#define SDMA0_RLC3_RB_WPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA0_RLC3_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA0_RLC3_RB_WPTR_HI
#define SDMA0_RLC3_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA0_RLC3_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA0_RLC3_RB_WPTR_POLL_CNTL
#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
//SDMA0_RLC3_RB_RPTR_ADDR_HI
#define SDMA0_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
#define SDMA0_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
//SDMA0_RLC3_RB_RPTR_ADDR_LO
#define SDMA0_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
#define SDMA0_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
//SDMA0_RLC3_IB_CNTL
#define SDMA0_RLC3_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
#define SDMA0_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
#define SDMA0_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
#define SDMA0_RLC3_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
#define SDMA0_RLC3_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
#define SDMA0_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
#define SDMA0_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
#define SDMA0_RLC3_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
//SDMA0_RLC3_IB_RPTR
#define SDMA0_RLC3_IB_RPTR__OFFSET__SHIFT                                                                     0x2
#define SDMA0_RLC3_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
//SDMA0_RLC3_IB_OFFSET
#define SDMA0_RLC3_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
#define SDMA0_RLC3_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
//SDMA0_RLC3_IB_BASE_LO
#define SDMA0_RLC3_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
#define SDMA0_RLC3_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
//SDMA0_RLC3_IB_BASE_HI
#define SDMA0_RLC3_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA0_RLC3_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
//SDMA0_RLC3_IB_SIZE
#define SDMA0_RLC3_IB_SIZE__SIZE__SHIFT                                                                       0x0
#define SDMA0_RLC3_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
//SDMA0_RLC3_SKIP_CNTL
#define SDMA0_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
#define SDMA0_RLC3_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
//SDMA0_RLC3_CONTEXT_STATUS
#define SDMA0_RLC3_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
#define SDMA0_RLC3_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
#define SDMA0_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
#define SDMA0_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
#define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
#define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
#define SDMA0_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
#define SDMA0_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
#define SDMA0_RLC3_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
#define SDMA0_RLC3_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
#define SDMA0_RLC3_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
#define SDMA0_RLC3_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
#define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
#define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
#define SDMA0_RLC3_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
#define SDMA0_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
//SDMA0_RLC3_DOORBELL
#define SDMA0_RLC3_DOORBELL__ENABLE__SHIFT                                                                    0x1c
#define SDMA0_RLC3_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
#define SDMA0_RLC3_DOORBELL__ENABLE_MASK                                                                      0x10000000L
#define SDMA0_RLC3_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
//SDMA0_RLC3_STATUS
#define SDMA0_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
#define SDMA0_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
#define SDMA0_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
#define SDMA0_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
//SDMA0_RLC3_DOORBELL_LOG
#define SDMA0_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
#define SDMA0_RLC3_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
#define SDMA0_RLC3_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
#define SDMA0_RLC3_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
//SDMA0_RLC3_WATERMARK
#define SDMA0_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
#define SDMA0_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
#define SDMA0_RLC3_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
#define SDMA0_RLC3_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
//SDMA0_RLC3_DOORBELL_OFFSET
#define SDMA0_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
#define SDMA0_RLC3_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
//SDMA0_RLC3_CSA_ADDR_LO
#define SDMA0_RLC3_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
#define SDMA0_RLC3_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
//SDMA0_RLC3_CSA_ADDR_HI
#define SDMA0_RLC3_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
#define SDMA0_RLC3_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
//SDMA0_RLC3_IB_SUB_REMAIN
#define SDMA0_RLC3_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
#define SDMA0_RLC3_IB_SUB_REMAIN__SIZE_MASK                                                                   0x00003FFFL
//SDMA0_RLC3_PREEMPT
#define SDMA0_RLC3_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
#define SDMA0_RLC3_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
//SDMA0_RLC3_DUMMY_REG
#define SDMA0_RLC3_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
#define SDMA0_RLC3_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
//SDMA0_RLC3_RB_WPTR_POLL_ADDR_HI
#define SDMA0_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
#define SDMA0_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
//SDMA0_RLC3_RB_WPTR_POLL_ADDR_LO
#define SDMA0_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
#define SDMA0_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
//SDMA0_RLC3_RB_AQL_CNTL
#define SDMA0_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
#define SDMA0_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
#define SDMA0_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
#define SDMA0_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                  0x10
#define SDMA0_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT                                            0x11
#define SDMA0_RLC3_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT                                                         0x12
#define SDMA0_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
#define SDMA0_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
#define SDMA0_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
#define SDMA0_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                    0x00010000L
#define SDMA0_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK                                              0x00020000L
#define SDMA0_RLC3_RB_AQL_CNTL__OVERLAP_ENABLE_MASK                                                           0x00040000L
//SDMA0_RLC3_MINOR_PTR_UPDATE
#define SDMA0_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
#define SDMA0_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
//SDMA0_RLC3_MIDCMD_DATA0
#define SDMA0_RLC3_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
#define SDMA0_RLC3_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC3_MIDCMD_DATA1
#define SDMA0_RLC3_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
#define SDMA0_RLC3_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC3_MIDCMD_DATA2
#define SDMA0_RLC3_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
#define SDMA0_RLC3_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC3_MIDCMD_DATA3
#define SDMA0_RLC3_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
#define SDMA0_RLC3_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC3_MIDCMD_DATA4
#define SDMA0_RLC3_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
#define SDMA0_RLC3_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC3_MIDCMD_DATA5
#define SDMA0_RLC3_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
#define SDMA0_RLC3_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC3_MIDCMD_DATA6
#define SDMA0_RLC3_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
#define SDMA0_RLC3_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC3_MIDCMD_DATA7
#define SDMA0_RLC3_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
#define SDMA0_RLC3_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC3_MIDCMD_DATA8
#define SDMA0_RLC3_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
#define SDMA0_RLC3_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC3_MIDCMD_DATA9
#define SDMA0_RLC3_MIDCMD_DATA9__DATA9__SHIFT                                                                 0x0
#define SDMA0_RLC3_MIDCMD_DATA9__DATA9_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC3_MIDCMD_DATA10
#define SDMA0_RLC3_MIDCMD_DATA10__DATA10__SHIFT                                                               0x0
#define SDMA0_RLC3_MIDCMD_DATA10__DATA10_MASK                                                                 0xFFFFFFFFL
//SDMA0_RLC3_MIDCMD_CNTL
#define SDMA0_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
#define SDMA0_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
#define SDMA0_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
#define SDMA0_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
#define SDMA0_RLC3_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
#define SDMA0_RLC3_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
#define SDMA0_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
#define SDMA0_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
//SDMA0_RLC4_RB_CNTL
#define SDMA0_RLC4_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
#define SDMA0_RLC4_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
#define SDMA0_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
#define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
#define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
#define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
#define SDMA0_RLC4_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
#define SDMA0_RLC4_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
#define SDMA0_RLC4_RB_CNTL__RPTR_WB_IDLE__SHIFT                                                               0x1f
#define SDMA0_RLC4_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
#define SDMA0_RLC4_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
#define SDMA0_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
#define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
#define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
#define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
#define SDMA0_RLC4_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
#define SDMA0_RLC4_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
#define SDMA0_RLC4_RB_CNTL__RPTR_WB_IDLE_MASK                                                                 0x80000000L
//SDMA0_RLC4_RB_BASE
#define SDMA0_RLC4_RB_BASE__ADDR__SHIFT                                                                       0x0
#define SDMA0_RLC4_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
//SDMA0_RLC4_RB_BASE_HI
#define SDMA0_RLC4_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA0_RLC4_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
//SDMA0_RLC4_RB_RPTR
#define SDMA0_RLC4_RB_RPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA0_RLC4_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA0_RLC4_RB_RPTR_HI
#define SDMA0_RLC4_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA0_RLC4_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA0_RLC4_RB_WPTR
#define SDMA0_RLC4_RB_WPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA0_RLC4_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA0_RLC4_RB_WPTR_HI
#define SDMA0_RLC4_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA0_RLC4_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA0_RLC4_RB_WPTR_POLL_CNTL
#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
//SDMA0_RLC4_RB_RPTR_ADDR_HI
#define SDMA0_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
#define SDMA0_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
//SDMA0_RLC4_RB_RPTR_ADDR_LO
#define SDMA0_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
#define SDMA0_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
//SDMA0_RLC4_IB_CNTL
#define SDMA0_RLC4_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
#define SDMA0_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
#define SDMA0_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
#define SDMA0_RLC4_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
#define SDMA0_RLC4_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
#define SDMA0_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
#define SDMA0_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
#define SDMA0_RLC4_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
//SDMA0_RLC4_IB_RPTR
#define SDMA0_RLC4_IB_RPTR__OFFSET__SHIFT                                                                     0x2
#define SDMA0_RLC4_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
//SDMA0_RLC4_IB_OFFSET
#define SDMA0_RLC4_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
#define SDMA0_RLC4_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
//SDMA0_RLC4_IB_BASE_LO
#define SDMA0_RLC4_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
#define SDMA0_RLC4_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
//SDMA0_RLC4_IB_BASE_HI
#define SDMA0_RLC4_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA0_RLC4_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
//SDMA0_RLC4_IB_SIZE
#define SDMA0_RLC4_IB_SIZE__SIZE__SHIFT                                                                       0x0
#define SDMA0_RLC4_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
//SDMA0_RLC4_SKIP_CNTL
#define SDMA0_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
#define SDMA0_RLC4_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
//SDMA0_RLC4_CONTEXT_STATUS
#define SDMA0_RLC4_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
#define SDMA0_RLC4_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
#define SDMA0_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
#define SDMA0_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
#define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
#define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
#define SDMA0_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
#define SDMA0_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
#define SDMA0_RLC4_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
#define SDMA0_RLC4_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
#define SDMA0_RLC4_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
#define SDMA0_RLC4_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
#define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
#define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
#define SDMA0_RLC4_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
#define SDMA0_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
//SDMA0_RLC4_DOORBELL
#define SDMA0_RLC4_DOORBELL__ENABLE__SHIFT                                                                    0x1c
#define SDMA0_RLC4_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
#define SDMA0_RLC4_DOORBELL__ENABLE_MASK                                                                      0x10000000L
#define SDMA0_RLC4_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
//SDMA0_RLC4_STATUS
#define SDMA0_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
#define SDMA0_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
#define SDMA0_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
#define SDMA0_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
//SDMA0_RLC4_DOORBELL_LOG
#define SDMA0_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
#define SDMA0_RLC4_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
#define SDMA0_RLC4_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
#define SDMA0_RLC4_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
//SDMA0_RLC4_WATERMARK
#define SDMA0_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
#define SDMA0_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
#define SDMA0_RLC4_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
#define SDMA0_RLC4_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
//SDMA0_RLC4_DOORBELL_OFFSET
#define SDMA0_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
#define SDMA0_RLC4_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
//SDMA0_RLC4_CSA_ADDR_LO
#define SDMA0_RLC4_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
#define SDMA0_RLC4_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
//SDMA0_RLC4_CSA_ADDR_HI
#define SDMA0_RLC4_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
#define SDMA0_RLC4_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
//SDMA0_RLC4_IB_SUB_REMAIN
#define SDMA0_RLC4_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
#define SDMA0_RLC4_IB_SUB_REMAIN__SIZE_MASK                                                                   0x00003FFFL
//SDMA0_RLC4_PREEMPT
#define SDMA0_RLC4_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
#define SDMA0_RLC4_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
//SDMA0_RLC4_DUMMY_REG
#define SDMA0_RLC4_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
#define SDMA0_RLC4_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
//SDMA0_RLC4_RB_WPTR_POLL_ADDR_HI
#define SDMA0_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
#define SDMA0_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
//SDMA0_RLC4_RB_WPTR_POLL_ADDR_LO
#define SDMA0_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
#define SDMA0_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
//SDMA0_RLC4_RB_AQL_CNTL
#define SDMA0_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
#define SDMA0_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
#define SDMA0_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
#define SDMA0_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                  0x10
#define SDMA0_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT                                            0x11
#define SDMA0_RLC4_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT                                                         0x12
#define SDMA0_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
#define SDMA0_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
#define SDMA0_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
#define SDMA0_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                    0x00010000L
#define SDMA0_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK                                              0x00020000L
#define SDMA0_RLC4_RB_AQL_CNTL__OVERLAP_ENABLE_MASK                                                           0x00040000L
//SDMA0_RLC4_MINOR_PTR_UPDATE
#define SDMA0_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
#define SDMA0_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
//SDMA0_RLC4_MIDCMD_DATA0
#define SDMA0_RLC4_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
#define SDMA0_RLC4_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC4_MIDCMD_DATA1
#define SDMA0_RLC4_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
#define SDMA0_RLC4_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC4_MIDCMD_DATA2
#define SDMA0_RLC4_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
#define SDMA0_RLC4_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC4_MIDCMD_DATA3
#define SDMA0_RLC4_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
#define SDMA0_RLC4_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC4_MIDCMD_DATA4
#define SDMA0_RLC4_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
#define SDMA0_RLC4_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC4_MIDCMD_DATA5
#define SDMA0_RLC4_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
#define SDMA0_RLC4_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC4_MIDCMD_DATA6
#define SDMA0_RLC4_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
#define SDMA0_RLC4_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC4_MIDCMD_DATA7
#define SDMA0_RLC4_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
#define SDMA0_RLC4_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC4_MIDCMD_DATA8
#define SDMA0_RLC4_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
#define SDMA0_RLC4_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC4_MIDCMD_DATA9
#define SDMA0_RLC4_MIDCMD_DATA9__DATA9__SHIFT                                                                 0x0
#define SDMA0_RLC4_MIDCMD_DATA9__DATA9_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC4_MIDCMD_DATA10
#define SDMA0_RLC4_MIDCMD_DATA10__DATA10__SHIFT                                                               0x0
#define SDMA0_RLC4_MIDCMD_DATA10__DATA10_MASK                                                                 0xFFFFFFFFL
//SDMA0_RLC4_MIDCMD_CNTL
#define SDMA0_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
#define SDMA0_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
#define SDMA0_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
#define SDMA0_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
#define SDMA0_RLC4_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
#define SDMA0_RLC4_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
#define SDMA0_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
#define SDMA0_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
//SDMA0_RLC5_RB_CNTL
#define SDMA0_RLC5_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
#define SDMA0_RLC5_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
#define SDMA0_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
#define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
#define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
#define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
#define SDMA0_RLC5_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
#define SDMA0_RLC5_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
#define SDMA0_RLC5_RB_CNTL__RPTR_WB_IDLE__SHIFT                                                               0x1f
#define SDMA0_RLC5_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
#define SDMA0_RLC5_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
#define SDMA0_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
#define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
#define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
#define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
#define SDMA0_RLC5_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
#define SDMA0_RLC5_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
#define SDMA0_RLC5_RB_CNTL__RPTR_WB_IDLE_MASK                                                                 0x80000000L
//SDMA0_RLC5_RB_BASE
#define SDMA0_RLC5_RB_BASE__ADDR__SHIFT                                                                       0x0
#define SDMA0_RLC5_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
//SDMA0_RLC5_RB_BASE_HI
#define SDMA0_RLC5_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA0_RLC5_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
//SDMA0_RLC5_RB_RPTR
#define SDMA0_RLC5_RB_RPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA0_RLC5_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA0_RLC5_RB_RPTR_HI
#define SDMA0_RLC5_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA0_RLC5_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA0_RLC5_RB_WPTR
#define SDMA0_RLC5_RB_WPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA0_RLC5_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA0_RLC5_RB_WPTR_HI
#define SDMA0_RLC5_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA0_RLC5_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA0_RLC5_RB_WPTR_POLL_CNTL
#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
//SDMA0_RLC5_RB_RPTR_ADDR_HI
#define SDMA0_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
#define SDMA0_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
//SDMA0_RLC5_RB_RPTR_ADDR_LO
#define SDMA0_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
#define SDMA0_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
//SDMA0_RLC5_IB_CNTL
#define SDMA0_RLC5_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
#define SDMA0_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
#define SDMA0_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
#define SDMA0_RLC5_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
#define SDMA0_RLC5_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
#define SDMA0_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
#define SDMA0_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
#define SDMA0_RLC5_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
//SDMA0_RLC5_IB_RPTR
#define SDMA0_RLC5_IB_RPTR__OFFSET__SHIFT                                                                     0x2
#define SDMA0_RLC5_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
//SDMA0_RLC5_IB_OFFSET
#define SDMA0_RLC5_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
#define SDMA0_RLC5_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
//SDMA0_RLC5_IB_BASE_LO
#define SDMA0_RLC5_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
#define SDMA0_RLC5_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
//SDMA0_RLC5_IB_BASE_HI
#define SDMA0_RLC5_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA0_RLC5_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
//SDMA0_RLC5_IB_SIZE
#define SDMA0_RLC5_IB_SIZE__SIZE__SHIFT                                                                       0x0
#define SDMA0_RLC5_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
//SDMA0_RLC5_SKIP_CNTL
#define SDMA0_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
#define SDMA0_RLC5_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
//SDMA0_RLC5_CONTEXT_STATUS
#define SDMA0_RLC5_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
#define SDMA0_RLC5_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
#define SDMA0_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
#define SDMA0_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
#define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
#define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
#define SDMA0_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
#define SDMA0_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
#define SDMA0_RLC5_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
#define SDMA0_RLC5_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
#define SDMA0_RLC5_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
#define SDMA0_RLC5_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
#define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
#define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
#define SDMA0_RLC5_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
#define SDMA0_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
//SDMA0_RLC5_DOORBELL
#define SDMA0_RLC5_DOORBELL__ENABLE__SHIFT                                                                    0x1c
#define SDMA0_RLC5_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
#define SDMA0_RLC5_DOORBELL__ENABLE_MASK                                                                      0x10000000L
#define SDMA0_RLC5_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
//SDMA0_RLC5_STATUS
#define SDMA0_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
#define SDMA0_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
#define SDMA0_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
#define SDMA0_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
//SDMA0_RLC5_DOORBELL_LOG
#define SDMA0_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
#define SDMA0_RLC5_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
#define SDMA0_RLC5_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
#define SDMA0_RLC5_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
//SDMA0_RLC5_WATERMARK
#define SDMA0_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
#define SDMA0_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
#define SDMA0_RLC5_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
#define SDMA0_RLC5_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
//SDMA0_RLC5_DOORBELL_OFFSET
#define SDMA0_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
#define SDMA0_RLC5_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
//SDMA0_RLC5_CSA_ADDR_LO
#define SDMA0_RLC5_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
#define SDMA0_RLC5_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
//SDMA0_RLC5_CSA_ADDR_HI
#define SDMA0_RLC5_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
#define SDMA0_RLC5_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
//SDMA0_RLC5_IB_SUB_REMAIN
#define SDMA0_RLC5_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
#define SDMA0_RLC5_IB_SUB_REMAIN__SIZE_MASK                                                                   0x00003FFFL
//SDMA0_RLC5_PREEMPT
#define SDMA0_RLC5_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
#define SDMA0_RLC5_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
//SDMA0_RLC5_DUMMY_REG
#define SDMA0_RLC5_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
#define SDMA0_RLC5_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
//SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI
#define SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
#define SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
//SDMA0_RLC5_RB_WPTR_POLL_ADDR_LO
#define SDMA0_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
#define SDMA0_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
//SDMA0_RLC5_RB_AQL_CNTL
#define SDMA0_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
#define SDMA0_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
#define SDMA0_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
#define SDMA0_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                  0x10
#define SDMA0_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT                                            0x11
#define SDMA0_RLC5_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT                                                         0x12
#define SDMA0_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
#define SDMA0_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
#define SDMA0_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
#define SDMA0_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                    0x00010000L
#define SDMA0_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK                                              0x00020000L
#define SDMA0_RLC5_RB_AQL_CNTL__OVERLAP_ENABLE_MASK                                                           0x00040000L
//SDMA0_RLC5_MINOR_PTR_UPDATE
#define SDMA0_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
#define SDMA0_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
//SDMA0_RLC5_MIDCMD_DATA0
#define SDMA0_RLC5_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
#define SDMA0_RLC5_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC5_MIDCMD_DATA1
#define SDMA0_RLC5_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
#define SDMA0_RLC5_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC5_MIDCMD_DATA2
#define SDMA0_RLC5_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
#define SDMA0_RLC5_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC5_MIDCMD_DATA3
#define SDMA0_RLC5_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
#define SDMA0_RLC5_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC5_MIDCMD_DATA4
#define SDMA0_RLC5_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
#define SDMA0_RLC5_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC5_MIDCMD_DATA5
#define SDMA0_RLC5_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
#define SDMA0_RLC5_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC5_MIDCMD_DATA6
#define SDMA0_RLC5_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
#define SDMA0_RLC5_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC5_MIDCMD_DATA7
#define SDMA0_RLC5_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
#define SDMA0_RLC5_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC5_MIDCMD_DATA8
#define SDMA0_RLC5_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
#define SDMA0_RLC5_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC5_MIDCMD_DATA9
#define SDMA0_RLC5_MIDCMD_DATA9__DATA9__SHIFT                                                                 0x0
#define SDMA0_RLC5_MIDCMD_DATA9__DATA9_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC5_MIDCMD_DATA10
#define SDMA0_RLC5_MIDCMD_DATA10__DATA10__SHIFT                                                               0x0
#define SDMA0_RLC5_MIDCMD_DATA10__DATA10_MASK                                                                 0xFFFFFFFFL
//SDMA0_RLC5_MIDCMD_CNTL
#define SDMA0_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
#define SDMA0_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
#define SDMA0_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
#define SDMA0_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
#define SDMA0_RLC5_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
#define SDMA0_RLC5_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
#define SDMA0_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
#define SDMA0_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
//SDMA0_RLC6_RB_CNTL
#define SDMA0_RLC6_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
#define SDMA0_RLC6_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
#define SDMA0_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
#define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
#define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
#define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
#define SDMA0_RLC6_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
#define SDMA0_RLC6_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
#define SDMA0_RLC6_RB_CNTL__RPTR_WB_IDLE__SHIFT                                                               0x1f
#define SDMA0_RLC6_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
#define SDMA0_RLC6_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
#define SDMA0_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
#define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
#define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
#define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
#define SDMA0_RLC6_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
#define SDMA0_RLC6_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
#define SDMA0_RLC6_RB_CNTL__RPTR_WB_IDLE_MASK                                                                 0x80000000L
//SDMA0_RLC6_RB_BASE
#define SDMA0_RLC6_RB_BASE__ADDR__SHIFT                                                                       0x0
#define SDMA0_RLC6_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
//SDMA0_RLC6_RB_BASE_HI
#define SDMA0_RLC6_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA0_RLC6_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
//SDMA0_RLC6_RB_RPTR
#define SDMA0_RLC6_RB_RPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA0_RLC6_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA0_RLC6_RB_RPTR_HI
#define SDMA0_RLC6_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA0_RLC6_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA0_RLC6_RB_WPTR
#define SDMA0_RLC6_RB_WPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA0_RLC6_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA0_RLC6_RB_WPTR_HI
#define SDMA0_RLC6_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA0_RLC6_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA0_RLC6_RB_WPTR_POLL_CNTL
#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
//SDMA0_RLC6_RB_RPTR_ADDR_HI
#define SDMA0_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
#define SDMA0_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
//SDMA0_RLC6_RB_RPTR_ADDR_LO
#define SDMA0_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
#define SDMA0_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
//SDMA0_RLC6_IB_CNTL
#define SDMA0_RLC6_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
#define SDMA0_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
#define SDMA0_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
#define SDMA0_RLC6_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
#define SDMA0_RLC6_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
#define SDMA0_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
#define SDMA0_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
#define SDMA0_RLC6_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
//SDMA0_RLC6_IB_RPTR
#define SDMA0_RLC6_IB_RPTR__OFFSET__SHIFT                                                                     0x2
#define SDMA0_RLC6_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
//SDMA0_RLC6_IB_OFFSET
#define SDMA0_RLC6_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
#define SDMA0_RLC6_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
//SDMA0_RLC6_IB_BASE_LO
#define SDMA0_RLC6_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
#define SDMA0_RLC6_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
//SDMA0_RLC6_IB_BASE_HI
#define SDMA0_RLC6_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA0_RLC6_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
//SDMA0_RLC6_IB_SIZE
#define SDMA0_RLC6_IB_SIZE__SIZE__SHIFT                                                                       0x0
#define SDMA0_RLC6_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
//SDMA0_RLC6_SKIP_CNTL
#define SDMA0_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
#define SDMA0_RLC6_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
//SDMA0_RLC6_CONTEXT_STATUS
#define SDMA0_RLC6_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
#define SDMA0_RLC6_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
#define SDMA0_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
#define SDMA0_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
#define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
#define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
#define SDMA0_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
#define SDMA0_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
#define SDMA0_RLC6_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
#define SDMA0_RLC6_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
#define SDMA0_RLC6_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
#define SDMA0_RLC6_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
#define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
#define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
#define SDMA0_RLC6_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
#define SDMA0_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
//SDMA0_RLC6_DOORBELL
#define SDMA0_RLC6_DOORBELL__ENABLE__SHIFT                                                                    0x1c
#define SDMA0_RLC6_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
#define SDMA0_RLC6_DOORBELL__ENABLE_MASK                                                                      0x10000000L
#define SDMA0_RLC6_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
//SDMA0_RLC6_STATUS
#define SDMA0_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
#define SDMA0_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
#define SDMA0_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
#define SDMA0_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
//SDMA0_RLC6_DOORBELL_LOG
#define SDMA0_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
#define SDMA0_RLC6_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
#define SDMA0_RLC6_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
#define SDMA0_RLC6_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
//SDMA0_RLC6_WATERMARK
#define SDMA0_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
#define SDMA0_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
#define SDMA0_RLC6_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
#define SDMA0_RLC6_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
//SDMA0_RLC6_DOORBELL_OFFSET
#define SDMA0_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
#define SDMA0_RLC6_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
//SDMA0_RLC6_CSA_ADDR_LO
#define SDMA0_RLC6_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
#define SDMA0_RLC6_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
//SDMA0_RLC6_CSA_ADDR_HI
#define SDMA0_RLC6_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
#define SDMA0_RLC6_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
//SDMA0_RLC6_IB_SUB_REMAIN
#define SDMA0_RLC6_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
#define SDMA0_RLC6_IB_SUB_REMAIN__SIZE_MASK                                                                   0x00003FFFL
//SDMA0_RLC6_PREEMPT
#define SDMA0_RLC6_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
#define SDMA0_RLC6_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
//SDMA0_RLC6_DUMMY_REG
#define SDMA0_RLC6_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
#define SDMA0_RLC6_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
//SDMA0_RLC6_RB_WPTR_POLL_ADDR_HI
#define SDMA0_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
#define SDMA0_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
//SDMA0_RLC6_RB_WPTR_POLL_ADDR_LO
#define SDMA0_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
#define SDMA0_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
//SDMA0_RLC6_RB_AQL_CNTL
#define SDMA0_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
#define SDMA0_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
#define SDMA0_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
#define SDMA0_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                  0x10
#define SDMA0_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT                                            0x11
#define SDMA0_RLC6_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT                                                         0x12
#define SDMA0_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
#define SDMA0_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
#define SDMA0_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
#define SDMA0_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                    0x00010000L
#define SDMA0_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK                                              0x00020000L
#define SDMA0_RLC6_RB_AQL_CNTL__OVERLAP_ENABLE_MASK                                                           0x00040000L
//SDMA0_RLC6_MINOR_PTR_UPDATE
#define SDMA0_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
#define SDMA0_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
//SDMA0_RLC6_MIDCMD_DATA0
#define SDMA0_RLC6_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
#define SDMA0_RLC6_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC6_MIDCMD_DATA1
#define SDMA0_RLC6_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
#define SDMA0_RLC6_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC6_MIDCMD_DATA2
#define SDMA0_RLC6_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
#define SDMA0_RLC6_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC6_MIDCMD_DATA3
#define SDMA0_RLC6_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
#define SDMA0_RLC6_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC6_MIDCMD_DATA4
#define SDMA0_RLC6_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
#define SDMA0_RLC6_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC6_MIDCMD_DATA5
#define SDMA0_RLC6_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
#define SDMA0_RLC6_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC6_MIDCMD_DATA6
#define SDMA0_RLC6_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
#define SDMA0_RLC6_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC6_MIDCMD_DATA7
#define SDMA0_RLC6_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
#define SDMA0_RLC6_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC6_MIDCMD_DATA8
#define SDMA0_RLC6_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
#define SDMA0_RLC6_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC6_MIDCMD_DATA9
#define SDMA0_RLC6_MIDCMD_DATA9__DATA9__SHIFT                                                                 0x0
#define SDMA0_RLC6_MIDCMD_DATA9__DATA9_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC6_MIDCMD_DATA10
#define SDMA0_RLC6_MIDCMD_DATA10__DATA10__SHIFT                                                               0x0
#define SDMA0_RLC6_MIDCMD_DATA10__DATA10_MASK                                                                 0xFFFFFFFFL
//SDMA0_RLC6_MIDCMD_CNTL
#define SDMA0_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
#define SDMA0_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
#define SDMA0_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
#define SDMA0_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
#define SDMA0_RLC6_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
#define SDMA0_RLC6_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
#define SDMA0_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
#define SDMA0_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
//SDMA0_RLC7_RB_CNTL
#define SDMA0_RLC7_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
#define SDMA0_RLC7_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
#define SDMA0_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
#define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
#define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
#define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
#define SDMA0_RLC7_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
#define SDMA0_RLC7_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
#define SDMA0_RLC7_RB_CNTL__RPTR_WB_IDLE__SHIFT                                                               0x1f
#define SDMA0_RLC7_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
#define SDMA0_RLC7_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
#define SDMA0_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
#define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
#define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
#define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
#define SDMA0_RLC7_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
#define SDMA0_RLC7_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
#define SDMA0_RLC7_RB_CNTL__RPTR_WB_IDLE_MASK                                                                 0x80000000L
//SDMA0_RLC7_RB_BASE
#define SDMA0_RLC7_RB_BASE__ADDR__SHIFT                                                                       0x0
#define SDMA0_RLC7_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
//SDMA0_RLC7_RB_BASE_HI
#define SDMA0_RLC7_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA0_RLC7_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
//SDMA0_RLC7_RB_RPTR
#define SDMA0_RLC7_RB_RPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA0_RLC7_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA0_RLC7_RB_RPTR_HI
#define SDMA0_RLC7_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA0_RLC7_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA0_RLC7_RB_WPTR
#define SDMA0_RLC7_RB_WPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA0_RLC7_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA0_RLC7_RB_WPTR_HI
#define SDMA0_RLC7_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA0_RLC7_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA0_RLC7_RB_WPTR_POLL_CNTL
#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
//SDMA0_RLC7_RB_RPTR_ADDR_HI
#define SDMA0_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
#define SDMA0_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
//SDMA0_RLC7_RB_RPTR_ADDR_LO
#define SDMA0_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
#define SDMA0_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
//SDMA0_RLC7_IB_CNTL
#define SDMA0_RLC7_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
#define SDMA0_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
#define SDMA0_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
#define SDMA0_RLC7_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
#define SDMA0_RLC7_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
#define SDMA0_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
#define SDMA0_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
#define SDMA0_RLC7_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
//SDMA0_RLC7_IB_RPTR
#define SDMA0_RLC7_IB_RPTR__OFFSET__SHIFT                                                                     0x2
#define SDMA0_RLC7_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
//SDMA0_RLC7_IB_OFFSET
#define SDMA0_RLC7_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
#define SDMA0_RLC7_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
//SDMA0_RLC7_IB_BASE_LO
#define SDMA0_RLC7_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
#define SDMA0_RLC7_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
//SDMA0_RLC7_IB_BASE_HI
#define SDMA0_RLC7_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA0_RLC7_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
//SDMA0_RLC7_IB_SIZE
#define SDMA0_RLC7_IB_SIZE__SIZE__SHIFT                                                                       0x0
#define SDMA0_RLC7_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
//SDMA0_RLC7_SKIP_CNTL
#define SDMA0_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
#define SDMA0_RLC7_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
//SDMA0_RLC7_CONTEXT_STATUS
#define SDMA0_RLC7_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
#define SDMA0_RLC7_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
#define SDMA0_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
#define SDMA0_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
#define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
#define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
#define SDMA0_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
#define SDMA0_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
#define SDMA0_RLC7_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
#define SDMA0_RLC7_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
#define SDMA0_RLC7_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
#define SDMA0_RLC7_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
#define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
#define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
#define SDMA0_RLC7_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
#define SDMA0_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
//SDMA0_RLC7_DOORBELL
#define SDMA0_RLC7_DOORBELL__ENABLE__SHIFT                                                                    0x1c
#define SDMA0_RLC7_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
#define SDMA0_RLC7_DOORBELL__ENABLE_MASK                                                                      0x10000000L
#define SDMA0_RLC7_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
//SDMA0_RLC7_STATUS
#define SDMA0_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
#define SDMA0_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
#define SDMA0_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
#define SDMA0_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
//SDMA0_RLC7_DOORBELL_LOG
#define SDMA0_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
#define SDMA0_RLC7_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
#define SDMA0_RLC7_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
#define SDMA0_RLC7_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
//SDMA0_RLC7_WATERMARK
#define SDMA0_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
#define SDMA0_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
#define SDMA0_RLC7_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
#define SDMA0_RLC7_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
//SDMA0_RLC7_DOORBELL_OFFSET
#define SDMA0_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
#define SDMA0_RLC7_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
//SDMA0_RLC7_CSA_ADDR_LO
#define SDMA0_RLC7_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
#define SDMA0_RLC7_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
//SDMA0_RLC7_CSA_ADDR_HI
#define SDMA0_RLC7_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
#define SDMA0_RLC7_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
//SDMA0_RLC7_IB_SUB_REMAIN
#define SDMA0_RLC7_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
#define SDMA0_RLC7_IB_SUB_REMAIN__SIZE_MASK                                                                   0x00003FFFL
//SDMA0_RLC7_PREEMPT
#define SDMA0_RLC7_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
#define SDMA0_RLC7_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
//SDMA0_RLC7_DUMMY_REG
#define SDMA0_RLC7_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
#define SDMA0_RLC7_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
//SDMA0_RLC7_RB_WPTR_POLL_ADDR_HI
#define SDMA0_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
#define SDMA0_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
//SDMA0_RLC7_RB_WPTR_POLL_ADDR_LO
#define SDMA0_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
#define SDMA0_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
//SDMA0_RLC7_RB_AQL_CNTL
#define SDMA0_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
#define SDMA0_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
#define SDMA0_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
#define SDMA0_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                  0x10
#define SDMA0_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT                                            0x11
#define SDMA0_RLC7_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT                                                         0x12
#define SDMA0_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
#define SDMA0_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
#define SDMA0_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
#define SDMA0_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                    0x00010000L
#define SDMA0_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK                                              0x00020000L
#define SDMA0_RLC7_RB_AQL_CNTL__OVERLAP_ENABLE_MASK                                                           0x00040000L
//SDMA0_RLC7_MINOR_PTR_UPDATE
#define SDMA0_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
#define SDMA0_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
//SDMA0_RLC7_MIDCMD_DATA0
#define SDMA0_RLC7_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
#define SDMA0_RLC7_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC7_MIDCMD_DATA1
#define SDMA0_RLC7_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
#define SDMA0_RLC7_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC7_MIDCMD_DATA2
#define SDMA0_RLC7_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
#define SDMA0_RLC7_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC7_MIDCMD_DATA3
#define SDMA0_RLC7_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
#define SDMA0_RLC7_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC7_MIDCMD_DATA4
#define SDMA0_RLC7_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
#define SDMA0_RLC7_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC7_MIDCMD_DATA5
#define SDMA0_RLC7_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
#define SDMA0_RLC7_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC7_MIDCMD_DATA6
#define SDMA0_RLC7_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
#define SDMA0_RLC7_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC7_MIDCMD_DATA7
#define SDMA0_RLC7_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
#define SDMA0_RLC7_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC7_MIDCMD_DATA8
#define SDMA0_RLC7_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
#define SDMA0_RLC7_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC7_MIDCMD_DATA9
#define SDMA0_RLC7_MIDCMD_DATA9__DATA9__SHIFT                                                                 0x0
#define SDMA0_RLC7_MIDCMD_DATA9__DATA9_MASK                                                                   0xFFFFFFFFL
//SDMA0_RLC7_MIDCMD_DATA10
#define SDMA0_RLC7_MIDCMD_DATA10__DATA10__SHIFT                                                               0x0
#define SDMA0_RLC7_MIDCMD_DATA10__DATA10_MASK                                                                 0xFFFFFFFFL
//SDMA0_RLC7_MIDCMD_CNTL
#define SDMA0_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
#define SDMA0_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
#define SDMA0_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
#define SDMA0_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
#define SDMA0_RLC7_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
#define SDMA0_RLC7_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
#define SDMA0_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
#define SDMA0_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L


// addressBlock: gc_sdma1_sdma1dec
//SDMA1_DEC_START
#define SDMA1_DEC_START__START__SHIFT                                                                         0x0
#define SDMA1_DEC_START__START_MASK                                                                           0xFFFFFFFFL
//SDMA1_GLOBAL_TIMESTAMP_LO
#define SDMA1_GLOBAL_TIMESTAMP_LO__DATA__SHIFT                                                                0x0
#define SDMA1_GLOBAL_TIMESTAMP_LO__DATA_MASK                                                                  0xFFFFFFFFL
//SDMA1_GLOBAL_TIMESTAMP_HI
#define SDMA1_GLOBAL_TIMESTAMP_HI__DATA__SHIFT                                                                0x0
#define SDMA1_GLOBAL_TIMESTAMP_HI__DATA_MASK                                                                  0xFFFFFFFFL
//SDMA1_PG_CNTL
#define SDMA1_PG_CNTL__CMD__SHIFT                                                                             0x0
#define SDMA1_PG_CNTL__STATUS__SHIFT                                                                          0x10
#define SDMA1_PG_CNTL__CMD_MASK                                                                               0x0000000FL
#define SDMA1_PG_CNTL__STATUS_MASK                                                                            0x000F0000L
//SDMA1_PG_CTX_LO
#define SDMA1_PG_CTX_LO__ADDR__SHIFT                                                                          0x0
#define SDMA1_PG_CTX_LO__ADDR_MASK                                                                            0xFFFFFFFFL
//SDMA1_PG_CTX_HI
#define SDMA1_PG_CTX_HI__ADDR__SHIFT                                                                          0x0
#define SDMA1_PG_CTX_HI__ADDR_MASK                                                                            0xFFFFFFFFL
//SDMA1_PG_CTX_CNTL
#define SDMA1_PG_CTX_CNTL__VMID__SHIFT                                                                        0x4
#define SDMA1_PG_CTX_CNTL__VMID_MASK                                                                          0x000000F0L
//SDMA1_POWER_CNTL
#define SDMA1_POWER_CNTL__PG_CNTL_ENABLE__SHIFT                                                               0x0
#define SDMA1_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT                                                          0x1
#define SDMA1_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT                                                         0x2
#define SDMA1_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME__SHIFT                                                   0x3
#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT                                                           0x8
#define SDMA1_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME__SHIFT                                                  0x1a
#define SDMA1_POWER_CNTL__PG_CNTL_ENABLE_MASK                                                                 0x00000001L
#define SDMA1_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK                                                            0x00000002L
#define SDMA1_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK                                                           0x00000004L
#define SDMA1_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK                                                     0x000000F8L
#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK                                                             0x00000100L
#define SDMA1_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK                                                    0xFC000000L
//SDMA1_CLK_CTRL
#define SDMA1_CLK_CTRL__ON_DELAY__SHIFT                                                                       0x0
#define SDMA1_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                                 0x4
#define SDMA1_CLK_CTRL__RESERVED_24_12__SHIFT                                                                 0xc
#define SDMA1_CLK_CTRL__CGCG_EN_OVERRIDE__SHIFT                                                               0x19
#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4__SHIFT                                                                 0x1a
#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3__SHIFT                                                                 0x1b
#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2__SHIFT                                                                 0x1c
#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1__SHIFT                                                                 0x1d
#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0__SHIFT                                                                 0x1e
#define SDMA1_CLK_CTRL__SOFT_OVERRIDER_REG__SHIFT                                                             0x1f
#define SDMA1_CLK_CTRL__ON_DELAY_MASK                                                                         0x0000000FL
#define SDMA1_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                   0x00000FF0L
#define SDMA1_CLK_CTRL__RESERVED_24_12_MASK                                                                   0x01FFF000L
#define SDMA1_CLK_CTRL__CGCG_EN_OVERRIDE_MASK                                                                 0x02000000L
#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK                                                                   0x04000000L
#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK                                                                   0x08000000L
#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK                                                                   0x10000000L
#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK                                                                   0x20000000L
#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK                                                                   0x40000000L
#define SDMA1_CLK_CTRL__SOFT_OVERRIDER_REG_MASK                                                               0x80000000L
//SDMA1_CNTL
#define SDMA1_CNTL__TRAP_ENABLE__SHIFT                                                                        0x0
#define SDMA1_CNTL__UTC_L1_ENABLE__SHIFT                                                                      0x1
#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT                                                                0x2
#define SDMA1_CNTL__DATA_SWAP_ENABLE__SHIFT                                                                   0x3
#define SDMA1_CNTL__FENCE_SWAP_ENABLE__SHIFT                                                                  0x4
#define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                              0x5
#define SDMA1_CNTL__PAGE_INT_ENABLE__SHIFT                                                                    0x7
#define SDMA1_CNTL__CH_PERFCNT_ENABLE__SHIFT                                                                  0x10
#define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT                                                          0x11
#define SDMA1_CNTL__AUTO_CTXSW_ENABLE__SHIFT                                                                  0x12
#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE__SHIFT                                                                0x1c
#define SDMA1_CNTL__FROZEN_INT_ENABLE__SHIFT                                                                  0x1d
#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT                                                              0x1e
#define SDMA1_CNTL__TRAP_ENABLE_MASK                                                                          0x00000001L
#define SDMA1_CNTL__UTC_L1_ENABLE_MASK                                                                        0x00000002L
#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE_MASK                                                                  0x00000004L
#define SDMA1_CNTL__DATA_SWAP_ENABLE_MASK                                                                     0x00000008L
#define SDMA1_CNTL__FENCE_SWAP_ENABLE_MASK                                                                    0x00000010L
#define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                                0x00000020L
#define SDMA1_CNTL__PAGE_INT_ENABLE_MASK                                                                      0x00000080L
#define SDMA1_CNTL__CH_PERFCNT_ENABLE_MASK                                                                    0x00010000L
#define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK                                                            0x00020000L
#define SDMA1_CNTL__AUTO_CTXSW_ENABLE_MASK                                                                    0x00040000L
#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE_MASK                                                                  0x10000000L
#define SDMA1_CNTL__FROZEN_INT_ENABLE_MASK                                                                    0x20000000L
#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE_MASK                                                                0x40000000L
//SDMA1_CHICKEN_BITS
#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT                                                     0x0
#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT                                                 0x1
#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT                                        0x2
#define SDMA1_CHICKEN_BITS__SOFT_OVERRIDE_DCGE__SHIFT                                                         0x4
#define SDMA1_CHICKEN_BITS__SOFT_OVERRIDE_SDMA_GRBM_FGCG__SHIFT                                               0x5
#define SDMA1_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT                                                         0x8
#define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT                                                     0xa
#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT                                                        0x10
#define SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT                                                           0x11
#define SDMA1_CHICKEN_BITS__T2L_256B_ENABLE__SHIFT                                                            0x12
#define SDMA1_CHICKEN_BITS__GCR_FGCG_ENABLE__SHIFT                                                            0x13
#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT                                                         0x14
#define SDMA1_CHICKEN_BITS__CH_FGCG_ENABLE__SHIFT                                                             0x15
#define SDMA1_CHICKEN_BITS__UTCL2_INVREQ_FGCG_ENABLE__SHIFT                                                   0x16
#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT                                                           0x17
#define SDMA1_CHICKEN_BITS__UTCL1_FGCG_ENABLE__SHIFT                                                          0x18
#define SDMA1_CHICKEN_BITS__TIME_BASED_QOS__SHIFT                                                             0x19
#define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT                                                         0x1a
#define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT                                                         0x1c
#define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT                                                         0x1e
#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK                                                       0x00000001L
#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK                                                   0x00000002L
#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK                                          0x00000004L
#define SDMA1_CHICKEN_BITS__SOFT_OVERRIDE_DCGE_MASK                                                           0x00000010L
#define SDMA1_CHICKEN_BITS__SOFT_OVERRIDE_SDMA_GRBM_FGCG_MASK                                                 0x00000020L
#define SDMA1_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK                                                           0x00000300L
#define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK                                                       0x00001C00L
#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK                                                          0x00010000L
#define SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK                                                             0x00020000L
#define SDMA1_CHICKEN_BITS__T2L_256B_ENABLE_MASK                                                              0x00040000L
#define SDMA1_CHICKEN_BITS__GCR_FGCG_ENABLE_MASK                                                              0x00080000L
#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK                                                           0x00100000L
#define SDMA1_CHICKEN_BITS__CH_FGCG_ENABLE_MASK                                                               0x00200000L
#define SDMA1_CHICKEN_BITS__UTCL2_INVREQ_FGCG_ENABLE_MASK                                                     0x00400000L
#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK                                                             0x00800000L
#define SDMA1_CHICKEN_BITS__UTCL1_FGCG_ENABLE_MASK                                                            0x01000000L
#define SDMA1_CHICKEN_BITS__TIME_BASED_QOS_MASK                                                               0x02000000L
#define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK                                                           0x0C000000L
#define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK                                                           0x30000000L
#define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK                                                           0xC0000000L
//SDMA1_GB_ADDR_CONFIG
#define SDMA1_GB_ADDR_CONFIG__NUM_PIPES__SHIFT                                                                0x0
#define SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT                                                     0x3
#define SDMA1_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                     0x6
#define SDMA1_GB_ADDR_CONFIG__NUM_PKRS__SHIFT                                                                 0x8
#define SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT                                                       0x13
#define SDMA1_GB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT                                                            0x1a
#define SDMA1_GB_ADDR_CONFIG__NUM_PIPES_MASK                                                                  0x00000007L
#define SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK                                                       0x00000038L
#define SDMA1_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                       0x000000C0L
#define SDMA1_GB_ADDR_CONFIG__NUM_PKRS_MASK                                                                   0x00000700L
#define SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK                                                         0x00180000L
#define SDMA1_GB_ADDR_CONFIG__NUM_RB_PER_SE_MASK                                                              0x0C000000L
//SDMA1_GB_ADDR_CONFIG_READ
#define SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT                                                           0x0
#define SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT                                                0x3
#define SDMA1_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT                                                0x6
#define SDMA1_GB_ADDR_CONFIG_READ__NUM_PKRS__SHIFT                                                            0x8
#define SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT                                                  0x13
#define SDMA1_GB_ADDR_CONFIG_READ__NUM_RB_PER_SE__SHIFT                                                       0x1a
#define SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK                                                             0x00000007L
#define SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK                                                  0x00000038L
#define SDMA1_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK                                                  0x000000C0L
#define SDMA1_GB_ADDR_CONFIG_READ__NUM_PKRS_MASK                                                              0x00000700L
#define SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK                                                    0x00180000L
#define SDMA1_GB_ADDR_CONFIG_READ__NUM_RB_PER_SE_MASK                                                         0x0C000000L
//SDMA1_RB_RPTR_FETCH_HI
#define SDMA1_RB_RPTR_FETCH_HI__OFFSET__SHIFT                                                                 0x0
#define SDMA1_RB_RPTR_FETCH_HI__OFFSET_MASK                                                                   0xFFFFFFFFL
//SDMA1_SEM_WAIT_FAIL_TIMER_CNTL
#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT                                                          0x0
#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK                                                            0xFFFFFFFFL
//SDMA1_RB_RPTR_FETCH
#define SDMA1_RB_RPTR_FETCH__OFFSET__SHIFT                                                                    0x2
#define SDMA1_RB_RPTR_FETCH__OFFSET_MASK                                                                      0xFFFFFFFCL
//SDMA1_IB_OFFSET_FETCH
#define SDMA1_IB_OFFSET_FETCH__OFFSET__SHIFT                                                                  0x2
#define SDMA1_IB_OFFSET_FETCH__OFFSET_MASK                                                                    0x003FFFFCL
//SDMA1_PROGRAM
#define SDMA1_PROGRAM__STREAM__SHIFT                                                                          0x0
#define SDMA1_PROGRAM__STREAM_MASK                                                                            0xFFFFFFFFL
//SDMA1_STATUS_REG
#define SDMA1_STATUS_REG__IDLE__SHIFT                                                                         0x0
#define SDMA1_STATUS_REG__REG_IDLE__SHIFT                                                                     0x1
#define SDMA1_STATUS_REG__RB_EMPTY__SHIFT                                                                     0x2
#define SDMA1_STATUS_REG__RB_FULL__SHIFT                                                                      0x3
#define SDMA1_STATUS_REG__RB_CMD_IDLE__SHIFT                                                                  0x4
#define SDMA1_STATUS_REG__RB_CMD_FULL__SHIFT                                                                  0x5
#define SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT                                                                  0x6
#define SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT                                                                  0x7
#define SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT                                                                   0x8
#define SDMA1_STATUS_REG__INSIDE_IB__SHIFT                                                                    0x9
#define SDMA1_STATUS_REG__EX_IDLE__SHIFT                                                                      0xa
#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT                                                    0xb
#define SDMA1_STATUS_REG__PACKET_READY__SHIFT                                                                 0xc
#define SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT                                                                   0xd
#define SDMA1_STATUS_REG__SRBM_IDLE__SHIFT                                                                    0xe
#define SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT                                                                0xf
#define SDMA1_STATUS_REG__DELTA_RPTR_FULL__SHIFT                                                              0x10
#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT                                                              0x11
#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT                                                              0x12
#define SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT                                                                   0x13
#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT                                                             0x14
#define SDMA1_STATUS_REG__MC_RD_RET_STALL__SHIFT                                                              0x15
#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT                                                           0x16
#define SDMA1_STATUS_REG__PREV_CMD_IDLE__SHIFT                                                                0x19
#define SDMA1_STATUS_REG__SEM_IDLE__SHIFT                                                                     0x1a
#define SDMA1_STATUS_REG__SEM_REQ_STALL__SHIFT                                                                0x1b
#define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT                                                               0x1c
#define SDMA1_STATUS_REG__INT_IDLE__SHIFT                                                                     0x1e
#define SDMA1_STATUS_REG__INT_REQ_STALL__SHIFT                                                                0x1f
#define SDMA1_STATUS_REG__IDLE_MASK                                                                           0x00000001L
#define SDMA1_STATUS_REG__REG_IDLE_MASK                                                                       0x00000002L
#define SDMA1_STATUS_REG__RB_EMPTY_MASK                                                                       0x00000004L
#define SDMA1_STATUS_REG__RB_FULL_MASK                                                                        0x00000008L
#define SDMA1_STATUS_REG__RB_CMD_IDLE_MASK                                                                    0x00000010L
#define SDMA1_STATUS_REG__RB_CMD_FULL_MASK                                                                    0x00000020L
#define SDMA1_STATUS_REG__IB_CMD_IDLE_MASK                                                                    0x00000040L
#define SDMA1_STATUS_REG__IB_CMD_FULL_MASK                                                                    0x00000080L
#define SDMA1_STATUS_REG__BLOCK_IDLE_MASK                                                                     0x00000100L
#define SDMA1_STATUS_REG__INSIDE_IB_MASK                                                                      0x00000200L
#define SDMA1_STATUS_REG__EX_IDLE_MASK                                                                        0x00000400L
#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK                                                      0x00000800L
#define SDMA1_STATUS_REG__PACKET_READY_MASK                                                                   0x00001000L
#define SDMA1_STATUS_REG__MC_WR_IDLE_MASK                                                                     0x00002000L
#define SDMA1_STATUS_REG__SRBM_IDLE_MASK                                                                      0x00004000L
#define SDMA1_STATUS_REG__CONTEXT_EMPTY_MASK                                                                  0x00008000L
#define SDMA1_STATUS_REG__DELTA_RPTR_FULL_MASK                                                                0x00010000L
#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE_MASK                                                                0x00020000L
#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE_MASK                                                                0x00040000L
#define SDMA1_STATUS_REG__MC_RD_IDLE_MASK                                                                     0x00080000L
#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY_MASK                                                               0x00100000L
#define SDMA1_STATUS_REG__MC_RD_RET_STALL_MASK                                                                0x00200000L
#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK                                                             0x00400000L
#define SDMA1_STATUS_REG__PREV_CMD_IDLE_MASK                                                                  0x02000000L
#define SDMA1_STATUS_REG__SEM_IDLE_MASK                                                                       0x04000000L
#define SDMA1_STATUS_REG__SEM_REQ_STALL_MASK                                                                  0x08000000L
#define SDMA1_STATUS_REG__SEM_RESP_STATE_MASK                                                                 0x30000000L
#define SDMA1_STATUS_REG__INT_IDLE_MASK                                                                       0x40000000L
#define SDMA1_STATUS_REG__INT_REQ_STALL_MASK                                                                  0x80000000L
//SDMA1_STATUS1_REG
#define SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT                                                                0x0
#define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT                                                                  0x1
#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT                                                               0x2
#define SDMA1_STATUS1_REG__CE_RREQ_IDLE__SHIFT                                                                0x3
#define SDMA1_STATUS1_REG__CE_OUT_IDLE__SHIFT                                                                 0x4
#define SDMA1_STATUS1_REG__CE_IN_IDLE__SHIFT                                                                  0x5
#define SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT                                                                 0x6
#define SDMA1_STATUS1_REG__CE_CMD_IDLE__SHIFT                                                                 0x9
#define SDMA1_STATUS1_REG__CE_AFIFO_FULL__SHIFT                                                               0xa
#define SDMA1_STATUS1_REG__CE_INFO_FULL__SHIFT                                                                0xd
#define SDMA1_STATUS1_REG__CE_INFO1_FULL__SHIFT                                                               0xe
#define SDMA1_STATUS1_REG__EX_START__SHIFT                                                                    0xf
#define SDMA1_STATUS1_REG__CE_RD_STALL__SHIFT                                                                 0x11
#define SDMA1_STATUS1_REG__CE_WR_STALL__SHIFT                                                                 0x12
#define SDMA1_STATUS1_REG__CE_WREQ_IDLE_MASK                                                                  0x00000001L
#define SDMA1_STATUS1_REG__CE_WR_IDLE_MASK                                                                    0x00000002L
#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE_MASK                                                                 0x00000004L
#define SDMA1_STATUS1_REG__CE_RREQ_IDLE_MASK                                                                  0x00000008L
#define SDMA1_STATUS1_REG__CE_OUT_IDLE_MASK                                                                   0x00000010L
#define SDMA1_STATUS1_REG__CE_IN_IDLE_MASK                                                                    0x00000020L
#define SDMA1_STATUS1_REG__CE_DST_IDLE_MASK                                                                   0x00000040L
#define SDMA1_STATUS1_REG__CE_CMD_IDLE_MASK                                                                   0x00000200L
#define SDMA1_STATUS1_REG__CE_AFIFO_FULL_MASK                                                                 0x00000400L
#define SDMA1_STATUS1_REG__CE_INFO_FULL_MASK                                                                  0x00002000L
#define SDMA1_STATUS1_REG__CE_INFO1_FULL_MASK                                                                 0x00004000L
#define SDMA1_STATUS1_REG__EX_START_MASK                                                                      0x00008000L
#define SDMA1_STATUS1_REG__CE_RD_STALL_MASK                                                                   0x00020000L
#define SDMA1_STATUS1_REG__CE_WR_STALL_MASK                                                                   0x00040000L
//SDMA1_RD_BURST_CNTL
#define SDMA1_RD_BURST_CNTL__RD_BURST__SHIFT                                                                  0x0
#define SDMA1_RD_BURST_CNTL__RD_BURST_MASK                                                                    0x00000003L
//SDMA1_HBM_PAGE_CONFIG
#define SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT                                                      0x0
#define SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK                                                        0x00000001L
//SDMA1_UCODE_CHECKSUM
#define SDMA1_UCODE_CHECKSUM__DATA__SHIFT                                                                     0x0
#define SDMA1_UCODE_CHECKSUM__DATA_MASK                                                                       0xFFFFFFFFL
//SDMA1_F32_CNTL
#define SDMA1_F32_CNTL__HALT__SHIFT                                                                           0x0
#define SDMA1_F32_CNTL__STEP__SHIFT                                                                           0x1
#define SDMA1_F32_CNTL__CHECKSUM_CLR__SHIFT                                                                   0x8
#define SDMA1_F32_CNTL__RESET__SHIFT                                                                          0x9
#define SDMA1_F32_CNTL__HALT_MASK                                                                             0x00000001L
#define SDMA1_F32_CNTL__STEP_MASK                                                                             0x00000002L
#define SDMA1_F32_CNTL__CHECKSUM_CLR_MASK                                                                     0x00000100L
#define SDMA1_F32_CNTL__RESET_MASK                                                                            0x00000200L
//SDMA1_FREEZE
#define SDMA1_FREEZE__PREEMPT__SHIFT                                                                          0x0
#define SDMA1_FREEZE__FORCE_PREEMPT__SHIFT                                                                    0x1
#define SDMA1_FREEZE__FREEZE__SHIFT                                                                           0x4
#define SDMA1_FREEZE__FROZEN__SHIFT                                                                           0x5
#define SDMA1_FREEZE__F32_FREEZE__SHIFT                                                                       0x6
#define SDMA1_FREEZE__PREEMPT_MASK                                                                            0x00000001L
#define SDMA1_FREEZE__FORCE_PREEMPT_MASK                                                                      0x00000002L
#define SDMA1_FREEZE__FREEZE_MASK                                                                             0x00000010L
#define SDMA1_FREEZE__FROZEN_MASK                                                                             0x00000020L
#define SDMA1_FREEZE__F32_FREEZE_MASK                                                                         0x00000040L
//SDMA1_PHASE0_QUANTUM
#define SDMA1_PHASE0_QUANTUM__UNIT__SHIFT                                                                     0x0
#define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT                                                                    0x8
#define SDMA1_PHASE0_QUANTUM__PREFER__SHIFT                                                                   0x1e
#define SDMA1_PHASE0_QUANTUM__UNIT_MASK                                                                       0x0000000FL
#define SDMA1_PHASE0_QUANTUM__VALUE_MASK                                                                      0x00FFFF00L
#define SDMA1_PHASE0_QUANTUM__PREFER_MASK                                                                     0x40000000L
//SDMA1_PHASE1_QUANTUM
#define SDMA1_PHASE1_QUANTUM__UNIT__SHIFT                                                                     0x0
#define SDMA1_PHASE1_QUANTUM__VALUE__SHIFT                                                                    0x8
#define SDMA1_PHASE1_QUANTUM__PREFER__SHIFT                                                                   0x1e
#define SDMA1_PHASE1_QUANTUM__UNIT_MASK                                                                       0x0000000FL
#define SDMA1_PHASE1_QUANTUM__VALUE_MASK                                                                      0x00FFFF00L
#define SDMA1_PHASE1_QUANTUM__PREFER_MASK                                                                     0x40000000L
//SDMA1_EDC_CONFIG
#define SDMA1_EDC_CONFIG__DIS_EDC__SHIFT                                                                      0x1
#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE__SHIFT                                                               0x2
#define SDMA1_EDC_CONFIG__DIS_EDC_MASK                                                                        0x00000002L
#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE_MASK                                                                 0x00000004L
//SDMA1_BA_THRESHOLD
#define SDMA1_BA_THRESHOLD__READ_THRES__SHIFT                                                                 0x0
#define SDMA1_BA_THRESHOLD__WRITE_THRES__SHIFT                                                                0x10
#define SDMA1_BA_THRESHOLD__READ_THRES_MASK                                                                   0x000003FFL
#define SDMA1_BA_THRESHOLD__WRITE_THRES_MASK                                                                  0x03FF0000L
//SDMA1_ID
#define SDMA1_ID__DEVICE_ID__SHIFT                                                                            0x0
#define SDMA1_ID__DEVICE_ID_MASK                                                                              0x000000FFL
//SDMA1_VERSION
#define SDMA1_VERSION__MINVER__SHIFT                                                                          0x0
#define SDMA1_VERSION__MAJVER__SHIFT                                                                          0x8
#define SDMA1_VERSION__REV__SHIFT                                                                             0x10
#define SDMA1_VERSION__MINVER_MASK                                                                            0x0000007FL
#define SDMA1_VERSION__MAJVER_MASK                                                                            0x00007F00L
#define SDMA1_VERSION__REV_MASK                                                                               0x003F0000L
//SDMA1_EDC_COUNTER
#define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_DED__SHIFT                                                          0x0
#define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_SEC__SHIFT                                                          0x1
#define SDMA1_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT                                                         0x2
#define SDMA1_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT                                                         0x3
#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT                                                      0x4
#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT                                                   0x5
#define SDMA1_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT                                                      0x6
#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT                                                    0x7
#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT                                                    0x8
#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT                                                    0x9
#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT                                                    0xa
#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT                                                    0xb
#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT                                                    0xc
#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT                                                    0xd
#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT                                                    0xe
#define SDMA1_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT                                                      0xf
#define SDMA1_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT                                                    0x10
#define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_DED_MASK                                                            0x00000001L
#define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_SEC_MASK                                                            0x00000002L
#define SDMA1_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK                                                           0x00000004L
#define SDMA1_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK                                                           0x00000008L
#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK                                                        0x00000010L
#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK                                                     0x00000020L
#define SDMA1_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK                                                        0x00000040L
#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK                                                      0x00000080L
#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK                                                      0x00000100L
#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK                                                      0x00000200L
#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK                                                      0x00000400L
#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK                                                      0x00000800L
#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK                                                      0x00001000L
#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK                                                      0x00002000L
#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK                                                      0x00004000L
#define SDMA1_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK                                                        0x00008000L
#define SDMA1_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK                                                      0x00010000L
//SDMA1_EDC_COUNTER_CLEAR
#define SDMA1_EDC_COUNTER_CLEAR__DUMMY__SHIFT                                                                 0x0
#define SDMA1_EDC_COUNTER_CLEAR__DUMMY_MASK                                                                   0x00000001L
//SDMA1_STATUS2_REG
#define SDMA1_STATUS2_REG__ID__SHIFT                                                                          0x0
#define SDMA1_STATUS2_REG__F32_INSTR_PTR__SHIFT                                                               0x2
#define SDMA1_STATUS2_REG__CMD_OP__SHIFT                                                                      0x10
#define SDMA1_STATUS2_REG__ID_MASK                                                                            0x00000003L
#define SDMA1_STATUS2_REG__F32_INSTR_PTR_MASK                                                                 0x0000FFFCL
#define SDMA1_STATUS2_REG__CMD_OP_MASK                                                                        0xFFFF0000L
//SDMA1_ATOMIC_CNTL
#define SDMA1_ATOMIC_CNTL__LOOP_TIMER__SHIFT                                                                  0x0
#define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT                                                       0x1f
#define SDMA1_ATOMIC_CNTL__LOOP_TIMER_MASK                                                                    0x7FFFFFFFL
#define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK                                                         0x80000000L
//SDMA1_ATOMIC_PREOP_LO
#define SDMA1_ATOMIC_PREOP_LO__DATA__SHIFT                                                                    0x0
#define SDMA1_ATOMIC_PREOP_LO__DATA_MASK                                                                      0xFFFFFFFFL
//SDMA1_ATOMIC_PREOP_HI
#define SDMA1_ATOMIC_PREOP_HI__DATA__SHIFT                                                                    0x0
#define SDMA1_ATOMIC_PREOP_HI__DATA_MASK                                                                      0xFFFFFFFFL
//SDMA1_UTCL1_CNTL
#define SDMA1_UTCL1_CNTL__REDO_ENABLE__SHIFT                                                                  0x0
#define SDMA1_UTCL1_CNTL__REDO_DELAY__SHIFT                                                                   0x1
#define SDMA1_UTCL1_CNTL__REDO_WATERMK__SHIFT                                                                 0x6
#define SDMA1_UTCL1_CNTL__RESP_MODE__SHIFT                                                                    0x9
#define SDMA1_UTCL1_CNTL__FORCE_INVALIDATION__SHIFT                                                           0xe
#define SDMA1_UTCL1_CNTL__FORCE_INVREQ_HEAVY__SHIFT                                                           0xf
#define SDMA1_UTCL1_CNTL__INVACK_DELAY__SHIFT                                                                 0x10
#define SDMA1_UTCL1_CNTL__REQL2_CREDIT__SHIFT                                                                 0x18
#define SDMA1_UTCL1_CNTL__VADDR_WATERMK__SHIFT                                                                0x1d
#define SDMA1_UTCL1_CNTL__REDO_ENABLE_MASK                                                                    0x00000001L
#define SDMA1_UTCL1_CNTL__REDO_DELAY_MASK                                                                     0x0000003EL
#define SDMA1_UTCL1_CNTL__REDO_WATERMK_MASK                                                                   0x000001C0L
#define SDMA1_UTCL1_CNTL__RESP_MODE_MASK                                                                      0x00000E00L
#define SDMA1_UTCL1_CNTL__FORCE_INVALIDATION_MASK                                                             0x00004000L
#define SDMA1_UTCL1_CNTL__FORCE_INVREQ_HEAVY_MASK                                                             0x00008000L
#define SDMA1_UTCL1_CNTL__INVACK_DELAY_MASK                                                                   0x00FF0000L
#define SDMA1_UTCL1_CNTL__REQL2_CREDIT_MASK                                                                   0x1F000000L
#define SDMA1_UTCL1_CNTL__VADDR_WATERMK_MASK                                                                  0xE0000000L
//SDMA1_UTCL1_WATERMK
#define SDMA1_UTCL1_WATERMK__REQMC_WATERMK__SHIFT                                                             0x0
#define SDMA1_UTCL1_WATERMK__REQPG_WATERMK__SHIFT                                                             0xa
#define SDMA1_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT                                                            0x12
#define SDMA1_UTCL1_WATERMK__XNACK_WATERMK__SHIFT                                                             0x1a
#define SDMA1_UTCL1_WATERMK__REQMC_WATERMK_MASK                                                               0x000003FFL
#define SDMA1_UTCL1_WATERMK__REQPG_WATERMK_MASK                                                               0x0003FC00L
#define SDMA1_UTCL1_WATERMK__INVREQ_WATERMK_MASK                                                              0x03FC0000L
#define SDMA1_UTCL1_WATERMK__XNACK_WATERMK_MASK                                                               0xFC000000L
//SDMA1_UTCL1_RD_STATUS
#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT                                                0x0
#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT                                                 0x1
#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT                                                     0x2
#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT                                                      0x3
#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT                                                      0x4
#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT                                                       0x5
#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT                                                   0x6
#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT                                                    0x7
#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT                                                    0x8
#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT                                                     0x9
#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT                                                 0xa
#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT                                                  0xb
#define SDMA1_UTCL1_RD_STATUS__REDO_ARR_EMPTY__SHIFT                                                          0xc
#define SDMA1_UTCL1_RD_STATUS__REDO_ARR_FULL__SHIFT                                                           0xd
#define SDMA1_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT                                                              0xe
#define SDMA1_UTCL1_RD_STATUS__PAGE_NULL__SHIFT                                                               0xf
#define SDMA1_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT                                                              0x10
#define SDMA1_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT                                                          0x11
#define SDMA1_UTCL1_RD_STATUS__MERGE_STATE__SHIFT                                                             0x15
#define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT                                                             0x18
#define SDMA1_UTCL1_RD_STATUS__RD_XNACK_TIMEOUT__SHIFT                                                        0x19
#define SDMA1_UTCL1_RD_STATUS__PAGE_NULL_SW__SHIFT                                                            0x1a
#define SDMA1_UTCL1_RD_STATUS__HIT_CACHE__SHIFT                                                               0x1b
#define SDMA1_UTCL1_RD_STATUS__RD_DCC_ENABLE__SHIFT                                                           0x1c
#define SDMA1_UTCL1_RD_STATUS__NACK_TIMEOUT_SW__SHIFT                                                         0x1d
#define SDMA1_UTCL1_RD_STATUS__DCC_PAGE_FAULT__SHIFT                                                          0x1e
#define SDMA1_UTCL1_RD_STATUS__DCC_PAGE_NULL__SHIFT                                                           0x1f
#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK                                                  0x00000001L
#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK                                                   0x00000002L
#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK                                                       0x00000004L
#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK                                                        0x00000008L
#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK                                                        0x00000010L
#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK                                                         0x00000020L
#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK                                                     0x00000040L
#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK                                                      0x00000080L
#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK                                                      0x00000100L
#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK                                                       0x00000200L
#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK                                                   0x00000400L
#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK                                                    0x00000800L
#define SDMA1_UTCL1_RD_STATUS__REDO_ARR_EMPTY_MASK                                                            0x00001000L
#define SDMA1_UTCL1_RD_STATUS__REDO_ARR_FULL_MASK                                                             0x00002000L
#define SDMA1_UTCL1_RD_STATUS__PAGE_FAULT_MASK                                                                0x00004000L
#define SDMA1_UTCL1_RD_STATUS__PAGE_NULL_MASK                                                                 0x00008000L
#define SDMA1_UTCL1_RD_STATUS__REQL2_IDLE_MASK                                                                0x00010000L
#define SDMA1_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK                                                            0x001E0000L
#define SDMA1_UTCL1_RD_STATUS__MERGE_STATE_MASK                                                               0x00E00000L
#define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK                                                               0x01000000L
#define SDMA1_UTCL1_RD_STATUS__RD_XNACK_TIMEOUT_MASK                                                          0x02000000L
#define SDMA1_UTCL1_RD_STATUS__PAGE_NULL_SW_MASK                                                              0x04000000L
#define SDMA1_UTCL1_RD_STATUS__HIT_CACHE_MASK                                                                 0x08000000L
#define SDMA1_UTCL1_RD_STATUS__RD_DCC_ENABLE_MASK                                                             0x10000000L
#define SDMA1_UTCL1_RD_STATUS__NACK_TIMEOUT_SW_MASK                                                           0x20000000L
#define SDMA1_UTCL1_RD_STATUS__DCC_PAGE_FAULT_MASK                                                            0x40000000L
#define SDMA1_UTCL1_RD_STATUS__DCC_PAGE_NULL_MASK                                                             0x80000000L
//SDMA1_UTCL1_WR_STATUS
#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT                                                0x0
#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT                                                 0x1
#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT                                                     0x2
#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT                                                      0x3
#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT                                                      0x4
#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT                                                       0x5
#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT                                                   0x6
#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT                                                    0x7
#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT                                                    0x8
#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT                                                     0x9
#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT                                                 0xa
#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT                                                  0xb
#define SDMA1_UTCL1_WR_STATUS__REDO_ARR_EMPTY__SHIFT                                                          0xc
#define SDMA1_UTCL1_WR_STATUS__REDO_ARR_FULL__SHIFT                                                           0xd
#define SDMA1_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT                                                              0xe
#define SDMA1_UTCL1_WR_STATUS__PAGE_NULL__SHIFT                                                               0xf
#define SDMA1_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT                                                              0x10
#define SDMA1_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT                                                          0x11
#define SDMA1_UTCL1_WR_STATUS__MERGE_STATE__SHIFT                                                             0x15
#define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT                                                              0x18
#define SDMA1_UTCL1_WR_STATUS__WR_XNACK_TIMEOUT__SHIFT                                                        0x19
#define SDMA1_UTCL1_WR_STATUS__PAGE_NULL_SW__SHIFT                                                            0x1a
#define SDMA1_UTCL1_WR_STATUS__ATOMIC_OP__SHIFT                                                               0x1b
#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT                                                    0x1c
#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT                                                     0x1d
#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT                                                   0x1e
#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT                                                    0x1f
#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK                                                  0x00000001L
#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK                                                   0x00000002L
#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK                                                       0x00000004L
#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK                                                        0x00000008L
#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK                                                        0x00000010L
#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK                                                         0x00000020L
#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK                                                     0x00000040L
#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK                                                      0x00000080L
#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK                                                      0x00000100L
#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK                                                       0x00000200L
#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK                                                   0x00000400L
#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK                                                    0x00000800L
#define SDMA1_UTCL1_WR_STATUS__REDO_ARR_EMPTY_MASK                                                            0x00001000L
#define SDMA1_UTCL1_WR_STATUS__REDO_ARR_FULL_MASK                                                             0x00002000L
#define SDMA1_UTCL1_WR_STATUS__PAGE_FAULT_MASK                                                                0x00004000L
#define SDMA1_UTCL1_WR_STATUS__PAGE_NULL_MASK                                                                 0x00008000L
#define SDMA1_UTCL1_WR_STATUS__REQL2_IDLE_MASK                                                                0x00010000L
#define SDMA1_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK                                                            0x001E0000L
#define SDMA1_UTCL1_WR_STATUS__MERGE_STATE_MASK                                                               0x00E00000L
#define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR_MASK                                                                0x01000000L
#define SDMA1_UTCL1_WR_STATUS__WR_XNACK_TIMEOUT_MASK                                                          0x02000000L
#define SDMA1_UTCL1_WR_STATUS__PAGE_NULL_SW_MASK                                                              0x04000000L
#define SDMA1_UTCL1_WR_STATUS__ATOMIC_OP_MASK                                                                 0x08000000L
#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK                                                      0x10000000L
#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK                                                       0x20000000L
#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK                                                     0x40000000L
#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK                                                      0x80000000L
//SDMA1_UTCL1_INV0
#define SDMA1_UTCL1_INV0__CPF_INVREQ_EN__SHIFT                                                                0x0
#define SDMA1_UTCL1_INV0__GPUVM_INVREQ_EN__SHIFT                                                              0x1
#define SDMA1_UTCL1_INV0__CPF_GPA_INVREQ__SHIFT                                                               0x2
#define SDMA1_UTCL1_INV0__GPUVM_INVREQ_LOW__SHIFT                                                             0x3
#define SDMA1_UTCL1_INV0__GPUVM_INVREQ_HIGH__SHIFT                                                            0x4
#define SDMA1_UTCL1_INV0__INVREQ_SIZE__SHIFT                                                                  0x5
#define SDMA1_UTCL1_INV0__INVREQ_IDLE__SHIFT                                                                  0xb
#define SDMA1_UTCL1_INV0__VMINV_PEND_CNT__SHIFT                                                               0xc
#define SDMA1_UTCL1_INV0__GPUVM_LO_INV_VMID__SHIFT                                                            0x10
#define SDMA1_UTCL1_INV0__GPUVM_HI_INV_VMID__SHIFT                                                            0x14
#define SDMA1_UTCL1_INV0__GPUVM_INV_MODE__SHIFT                                                               0x18
#define SDMA1_UTCL1_INV0__INVREQ_IS_HEAVY__SHIFT                                                              0x1a
#define SDMA1_UTCL1_INV0__INVREQ_FROM_CPF__SHIFT                                                              0x1b
#define SDMA1_UTCL1_INV0__GPUVM_INVREQ_TAG__SHIFT                                                             0x1c
#define SDMA1_UTCL1_INV0__CPF_INVREQ_EN_MASK                                                                  0x00000001L
#define SDMA1_UTCL1_INV0__GPUVM_INVREQ_EN_MASK                                                                0x00000002L
#define SDMA1_UTCL1_INV0__CPF_GPA_INVREQ_MASK                                                                 0x00000004L
#define SDMA1_UTCL1_INV0__GPUVM_INVREQ_LOW_MASK                                                               0x00000008L
#define SDMA1_UTCL1_INV0__GPUVM_INVREQ_HIGH_MASK                                                              0x00000010L
#define SDMA1_UTCL1_INV0__INVREQ_SIZE_MASK                                                                    0x000007E0L
#define SDMA1_UTCL1_INV0__INVREQ_IDLE_MASK                                                                    0x00000800L
#define SDMA1_UTCL1_INV0__VMINV_PEND_CNT_MASK                                                                 0x0000F000L
#define SDMA1_UTCL1_INV0__GPUVM_LO_INV_VMID_MASK                                                              0x000F0000L
#define SDMA1_UTCL1_INV0__GPUVM_HI_INV_VMID_MASK                                                              0x00F00000L
#define SDMA1_UTCL1_INV0__GPUVM_INV_MODE_MASK                                                                 0x03000000L
#define SDMA1_UTCL1_INV0__INVREQ_IS_HEAVY_MASK                                                                0x04000000L
#define SDMA1_UTCL1_INV0__INVREQ_FROM_CPF_MASK                                                                0x08000000L
#define SDMA1_UTCL1_INV0__GPUVM_INVREQ_TAG_MASK                                                               0xF0000000L
//SDMA1_UTCL1_INV1
#define SDMA1_UTCL1_INV1__INV_ADDR_LO__SHIFT                                                                  0x0
#define SDMA1_UTCL1_INV1__INV_ADDR_LO_MASK                                                                    0xFFFFFFFFL
//SDMA1_UTCL1_INV2
#define SDMA1_UTCL1_INV2__INV_VMID_VEC__SHIFT                                                                 0x0
#define SDMA1_UTCL1_INV2__RESERVED__SHIFT                                                                     0x10
#define SDMA1_UTCL1_INV2__INV_VMID_VEC_MASK                                                                   0x0000FFFFL
#define SDMA1_UTCL1_INV2__RESERVED_MASK                                                                       0xFFFF0000L
//SDMA1_UTCL1_RD_XNACK0
#define SDMA1_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT                                                           0x0
#define SDMA1_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK                                                             0xFFFFFFFFL
//SDMA1_UTCL1_RD_XNACK1
#define SDMA1_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT                                                           0x0
#define SDMA1_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT                                                              0x4
#define SDMA1_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT                                                            0x8
#define SDMA1_UTCL1_RD_XNACK1__IS_XNACK__SHIFT                                                                0x1a
#define SDMA1_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK                                                             0x0000000FL
#define SDMA1_UTCL1_RD_XNACK1__XNACK_VMID_MASK                                                                0x000000F0L
#define SDMA1_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK                                                              0x03FFFF00L
#define SDMA1_UTCL1_RD_XNACK1__IS_XNACK_MASK                                                                  0x0C000000L
//SDMA1_UTCL1_WR_XNACK0
#define SDMA1_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT                                                           0x0
#define SDMA1_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK                                                             0xFFFFFFFFL
//SDMA1_UTCL1_WR_XNACK1
#define SDMA1_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT                                                           0x0
#define SDMA1_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT                                                              0x4
#define SDMA1_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT                                                            0x8
#define SDMA1_UTCL1_WR_XNACK1__IS_XNACK__SHIFT                                                                0x1a
#define SDMA1_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK                                                             0x0000000FL
#define SDMA1_UTCL1_WR_XNACK1__XNACK_VMID_MASK                                                                0x000000F0L
#define SDMA1_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK                                                              0x03FFFF00L
#define SDMA1_UTCL1_WR_XNACK1__IS_XNACK_MASK                                                                  0x0C000000L
//SDMA1_UTCL1_TIMEOUT
#define SDMA1_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT                                                            0x0
#define SDMA1_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT                                                            0x10
#define SDMA1_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK                                                              0x0000FFFFL
#define SDMA1_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK                                                              0xFFFF0000L
//SDMA1_UTCL1_PAGE
#define SDMA1_UTCL1_PAGE__VM_HOLE__SHIFT                                                                      0x0
#define SDMA1_UTCL1_PAGE__REQ_TYPE__SHIFT                                                                     0x1
#define SDMA1_UTCL1_PAGE__USE_MTYPE__SHIFT                                                                    0x6
#define SDMA1_UTCL1_PAGE__USE_PT_SNOOP__SHIFT                                                                 0xa
#define SDMA1_UTCL1_PAGE__USE_IO__SHIFT                                                                       0xb
#define SDMA1_UTCL1_PAGE__RD_L2_POLICY__SHIFT                                                                 0xc
#define SDMA1_UTCL1_PAGE__WR_L2_POLICY__SHIFT                                                                 0xe
#define SDMA1_UTCL1_PAGE__DMA_PAGE_SIZE__SHIFT                                                                0x10
#define SDMA1_UTCL1_PAGE__USE_BC__SHIFT                                                                       0x16
#define SDMA1_UTCL1_PAGE__ADDR_IS_PA__SHIFT                                                                   0x17
#define SDMA1_UTCL1_PAGE__VM_HOLE_MASK                                                                        0x00000001L
#define SDMA1_UTCL1_PAGE__REQ_TYPE_MASK                                                                       0x0000001EL
#define SDMA1_UTCL1_PAGE__USE_MTYPE_MASK                                                                      0x000003C0L
#define SDMA1_UTCL1_PAGE__USE_PT_SNOOP_MASK                                                                   0x00000400L
#define SDMA1_UTCL1_PAGE__USE_IO_MASK                                                                         0x00000800L
#define SDMA1_UTCL1_PAGE__RD_L2_POLICY_MASK                                                                   0x00003000L
#define SDMA1_UTCL1_PAGE__WR_L2_POLICY_MASK                                                                   0x0000C000L
#define SDMA1_UTCL1_PAGE__DMA_PAGE_SIZE_MASK                                                                  0x003F0000L
#define SDMA1_UTCL1_PAGE__USE_BC_MASK                                                                         0x00400000L
#define SDMA1_UTCL1_PAGE__ADDR_IS_PA_MASK                                                                     0x00800000L
//SDMA1_RELAX_ORDERING_LUT
#define SDMA1_RELAX_ORDERING_LUT__RESERVED0__SHIFT                                                            0x0
#define SDMA1_RELAX_ORDERING_LUT__COPY__SHIFT                                                                 0x1
#define SDMA1_RELAX_ORDERING_LUT__WRITE__SHIFT                                                                0x2
#define SDMA1_RELAX_ORDERING_LUT__RESERVED3__SHIFT                                                            0x3
#define SDMA1_RELAX_ORDERING_LUT__RESERVED4__SHIFT                                                            0x4
#define SDMA1_RELAX_ORDERING_LUT__FENCE__SHIFT                                                                0x5
#define SDMA1_RELAX_ORDERING_LUT__RESERVED76__SHIFT                                                           0x6
#define SDMA1_RELAX_ORDERING_LUT__POLL_MEM__SHIFT                                                             0x8
#define SDMA1_RELAX_ORDERING_LUT__COND_EXE__SHIFT                                                             0x9
#define SDMA1_RELAX_ORDERING_LUT__ATOMIC__SHIFT                                                               0xa
#define SDMA1_RELAX_ORDERING_LUT__CONST_FILL__SHIFT                                                           0xb
#define SDMA1_RELAX_ORDERING_LUT__PTEPDE__SHIFT                                                               0xc
#define SDMA1_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT                                                            0xd
#define SDMA1_RELAX_ORDERING_LUT__RESERVED__SHIFT                                                             0xe
#define SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT                                                         0x1b
#define SDMA1_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT                                                             0x1c
#define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT                                                            0x1d
#define SDMA1_RELAX_ORDERING_LUT__IB_FETCH__SHIFT                                                             0x1e
#define SDMA1_RELAX_ORDERING_LUT__RB_FETCH__SHIFT                                                             0x1f
#define SDMA1_RELAX_ORDERING_LUT__RESERVED0_MASK                                                              0x00000001L
#define SDMA1_RELAX_ORDERING_LUT__COPY_MASK                                                                   0x00000002L
#define SDMA1_RELAX_ORDERING_LUT__WRITE_MASK                                                                  0x00000004L
#define SDMA1_RELAX_ORDERING_LUT__RESERVED3_MASK                                                              0x00000008L
#define SDMA1_RELAX_ORDERING_LUT__RESERVED4_MASK                                                              0x00000010L
#define SDMA1_RELAX_ORDERING_LUT__FENCE_MASK                                                                  0x00000020L
#define SDMA1_RELAX_ORDERING_LUT__RESERVED76_MASK                                                             0x000000C0L
#define SDMA1_RELAX_ORDERING_LUT__POLL_MEM_MASK                                                               0x00000100L
#define SDMA1_RELAX_ORDERING_LUT__COND_EXE_MASK                                                               0x00000200L
#define SDMA1_RELAX_ORDERING_LUT__ATOMIC_MASK                                                                 0x00000400L
#define SDMA1_RELAX_ORDERING_LUT__CONST_FILL_MASK                                                             0x00000800L
#define SDMA1_RELAX_ORDERING_LUT__PTEPDE_MASK                                                                 0x00001000L
#define SDMA1_RELAX_ORDERING_LUT__TIMESTAMP_MASK                                                              0x00002000L
#define SDMA1_RELAX_ORDERING_LUT__RESERVED_MASK                                                               0x07FFC000L
#define SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK                                                           0x08000000L
#define SDMA1_RELAX_ORDERING_LUT__RPTR_WRB_MASK                                                               0x10000000L
#define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL_MASK                                                              0x20000000L
#define SDMA1_RELAX_ORDERING_LUT__IB_FETCH_MASK                                                               0x40000000L
#define SDMA1_RELAX_ORDERING_LUT__RB_FETCH_MASK                                                               0x80000000L
//SDMA1_CHICKEN_BITS_2
#define SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT                                                       0x0
#define SDMA1_CHICKEN_BITS_2__CE_BACKWARDS_SIZE_SEL__SHIFT                                                    0x4
#define SDMA1_CHICKEN_BITS_2__CE_DCC_READ_128B_ENABLE__SHIFT                                                  0x5
#define SDMA1_CHICKEN_BITS_2__UTCL1_FORCE_INV_RET_FIFO_FULL_EN__SHIFT                                         0x6
#define SDMA1_CHICKEN_BITS_2__RESERVED0__SHIFT                                                                0x7
#define SDMA1_CHICKEN_BITS_2__LUT_FIFO_AFULL_MARGIN__SHIFT                                                    0xb
#define SDMA1_CHICKEN_BITS_2__LEGACY_WPTR_POLL_BEHAVIOR__SHIFT                                                0xf
#define SDMA1_CHICKEN_BITS_2__RB_FIFO_WATERMARK__SHIFT                                                        0x10
#define SDMA1_CHICKEN_BITS_2__IB_FIFO_WATERMARK__SHIFT                                                        0x12
#define SDMA1_CHICKEN_BITS_2__REPEATER_FGCG_EN__SHIFT                                                         0x14
#define SDMA1_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN__SHIFT                                                     0x15
#define SDMA1_CHICKEN_BITS_2__RESERVED__SHIFT                                                                 0x16
#define SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK                                                         0x0000000FL
#define SDMA1_CHICKEN_BITS_2__CE_BACKWARDS_SIZE_SEL_MASK                                                      0x00000010L
#define SDMA1_CHICKEN_BITS_2__CE_DCC_READ_128B_ENABLE_MASK                                                    0x00000020L
#define SDMA1_CHICKEN_BITS_2__UTCL1_FORCE_INV_RET_FIFO_FULL_EN_MASK                                           0x00000040L
#define SDMA1_CHICKEN_BITS_2__RESERVED0_MASK                                                                  0x00000780L
#define SDMA1_CHICKEN_BITS_2__LUT_FIFO_AFULL_MARGIN_MASK                                                      0x00007800L
#define SDMA1_CHICKEN_BITS_2__LEGACY_WPTR_POLL_BEHAVIOR_MASK                                                  0x00008000L
#define SDMA1_CHICKEN_BITS_2__RB_FIFO_WATERMARK_MASK                                                          0x00030000L
#define SDMA1_CHICKEN_BITS_2__IB_FIFO_WATERMARK_MASK                                                          0x000C0000L
#define SDMA1_CHICKEN_BITS_2__REPEATER_FGCG_EN_MASK                                                           0x00100000L
#define SDMA1_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN_MASK                                                       0x00200000L
#define SDMA1_CHICKEN_BITS_2__RESERVED_MASK                                                                   0xFFC00000L
//SDMA1_STATUS3_REG
#define SDMA1_STATUS3_REG__CMD_OP_STATUS__SHIFT                                                               0x0
#define SDMA1_STATUS3_REG__PREV_VM_CMD__SHIFT                                                                 0x10
#define SDMA1_STATUS3_REG__EXCEPTION_IDLE__SHIFT                                                              0x14
#define SDMA1_STATUS3_REG__AQL_PREV_CMD_IDLE__SHIFT                                                           0x15
#define SDMA1_STATUS3_REG__TLBI_IDLE__SHIFT                                                                   0x16
#define SDMA1_STATUS3_REG__GCR_IDLE__SHIFT                                                                    0x17
#define SDMA1_STATUS3_REG__INVREQ_IDLE__SHIFT                                                                 0x18
#define SDMA1_STATUS3_REG__QUEUE_ID_MATCH__SHIFT                                                              0x19
#define SDMA1_STATUS3_REG__INT_QUEUE_ID__SHIFT                                                                0x1a
#define SDMA1_STATUS3_REG__CMD_OP_STATUS_MASK                                                                 0x0000FFFFL
#define SDMA1_STATUS3_REG__PREV_VM_CMD_MASK                                                                   0x000F0000L
#define SDMA1_STATUS3_REG__EXCEPTION_IDLE_MASK                                                                0x00100000L
#define SDMA1_STATUS3_REG__AQL_PREV_CMD_IDLE_MASK                                                             0x00200000L
#define SDMA1_STATUS3_REG__TLBI_IDLE_MASK                                                                     0x00400000L
#define SDMA1_STATUS3_REG__GCR_IDLE_MASK                                                                      0x00800000L
#define SDMA1_STATUS3_REG__INVREQ_IDLE_MASK                                                                   0x01000000L
#define SDMA1_STATUS3_REG__QUEUE_ID_MATCH_MASK                                                                0x02000000L
#define SDMA1_STATUS3_REG__INT_QUEUE_ID_MASK                                                                  0x3C000000L
//SDMA1_PHYSICAL_ADDR_LO
#define SDMA1_PHYSICAL_ADDR_LO__D_VALID__SHIFT                                                                0x0
#define SDMA1_PHYSICAL_ADDR_LO__DIRTY__SHIFT                                                                  0x1
#define SDMA1_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT                                                              0x2
#define SDMA1_PHYSICAL_ADDR_LO__ADDR__SHIFT                                                                   0xc
#define SDMA1_PHYSICAL_ADDR_LO__D_VALID_MASK                                                                  0x00000001L
#define SDMA1_PHYSICAL_ADDR_LO__DIRTY_MASK                                                                    0x00000002L
#define SDMA1_PHYSICAL_ADDR_LO__PHY_VALID_MASK                                                                0x00000004L
#define SDMA1_PHYSICAL_ADDR_LO__ADDR_MASK                                                                     0xFFFFF000L
//SDMA1_PHYSICAL_ADDR_HI
#define SDMA1_PHYSICAL_ADDR_HI__ADDR__SHIFT                                                                   0x0
#define SDMA1_PHYSICAL_ADDR_HI__ADDR_MASK                                                                     0x0000FFFFL
//SDMA1_PHASE2_QUANTUM
#define SDMA1_PHASE2_QUANTUM__UNIT__SHIFT                                                                     0x0
#define SDMA1_PHASE2_QUANTUM__VALUE__SHIFT                                                                    0x8
#define SDMA1_PHASE2_QUANTUM__PREFER__SHIFT                                                                   0x1e
#define SDMA1_PHASE2_QUANTUM__UNIT_MASK                                                                       0x0000000FL
#define SDMA1_PHASE2_QUANTUM__VALUE_MASK                                                                      0x00FFFF00L
#define SDMA1_PHASE2_QUANTUM__PREFER_MASK                                                                     0x40000000L
//SDMA1_ERROR_LOG
#define SDMA1_ERROR_LOG__OVERRIDE__SHIFT                                                                      0x0
#define SDMA1_ERROR_LOG__STATUS__SHIFT                                                                        0x10
#define SDMA1_ERROR_LOG__OVERRIDE_MASK                                                                        0x0000FFFFL
#define SDMA1_ERROR_LOG__STATUS_MASK                                                                          0xFFFF0000L
//SDMA1_PUB_DUMMY_REG0
#define SDMA1_PUB_DUMMY_REG0__VALUE__SHIFT                                                                    0x0
#define SDMA1_PUB_DUMMY_REG0__VALUE_MASK                                                                      0xFFFFFFFFL
//SDMA1_PUB_DUMMY_REG1
#define SDMA1_PUB_DUMMY_REG1__VALUE__SHIFT                                                                    0x0
#define SDMA1_PUB_DUMMY_REG1__VALUE_MASK                                                                      0xFFFFFFFFL
//SDMA1_PUB_DUMMY_REG2
#define SDMA1_PUB_DUMMY_REG2__VALUE__SHIFT                                                                    0x0
#define SDMA1_PUB_DUMMY_REG2__VALUE_MASK                                                                      0xFFFFFFFFL
//SDMA1_PUB_DUMMY_REG3
#define SDMA1_PUB_DUMMY_REG3__VALUE__SHIFT                                                                    0x0
#define SDMA1_PUB_DUMMY_REG3__VALUE_MASK                                                                      0xFFFFFFFFL
//SDMA1_F32_COUNTER
#define SDMA1_F32_COUNTER__VALUE__SHIFT                                                                       0x0
#define SDMA1_F32_COUNTER__VALUE_MASK                                                                         0xFFFFFFFFL
//SDMA1_CRD_CNTL
#define SDMA1_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT                                                                0x7
#define SDMA1_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT                                                                0xd
#define SDMA1_CRD_CNTL__CH_WRREQ_CREDIT__SHIFT                                                                0x13
#define SDMA1_CRD_CNTL__CH_RDREQ_CREDIT__SHIFT                                                                0x19
#define SDMA1_CRD_CNTL__MC_WRREQ_CREDIT_MASK                                                                  0x00001F80L
#define SDMA1_CRD_CNTL__MC_RDREQ_CREDIT_MASK                                                                  0x0007E000L
#define SDMA1_CRD_CNTL__CH_WRREQ_CREDIT_MASK                                                                  0x01F80000L
#define SDMA1_CRD_CNTL__CH_RDREQ_CREDIT_MASK                                                                  0x7E000000L
//SDMA1_AQL_STATUS
#define SDMA1_AQL_STATUS__COMPLETE_SIGNAL_EMPTY__SHIFT                                                        0x0
#define SDMA1_AQL_STATUS__INVALID_CMD_EMPTY__SHIFT                                                            0x1
#define SDMA1_AQL_STATUS__COMPLETE_SIGNAL_EMPTY_MASK                                                          0x00000001L
#define SDMA1_AQL_STATUS__INVALID_CMD_EMPTY_MASK                                                              0x00000002L
//SDMA1_EA_DBIT_ADDR_DATA
#define SDMA1_EA_DBIT_ADDR_DATA__VALUE__SHIFT                                                                 0x0
#define SDMA1_EA_DBIT_ADDR_DATA__VALUE_MASK                                                                   0xFFFFFFFFL
//SDMA1_EA_DBIT_ADDR_INDEX
#define SDMA1_EA_DBIT_ADDR_INDEX__VALUE__SHIFT                                                                0x0
#define SDMA1_EA_DBIT_ADDR_INDEX__VALUE_MASK                                                                  0x00000007L
//SDMA1_TLBI_GCR_CNTL
#define SDMA1_TLBI_GCR_CNTL__TLBI_CMD_DW__SHIFT                                                               0x0
#define SDMA1_TLBI_GCR_CNTL__GCR_CMD_DW__SHIFT                                                                0x4
#define SDMA1_TLBI_GCR_CNTL__GCR_CLKEN_CYCLE__SHIFT                                                           0x8
#define SDMA1_TLBI_GCR_CNTL__TLBI_CREDIT__SHIFT                                                               0x10
#define SDMA1_TLBI_GCR_CNTL__GCR_CREDIT__SHIFT                                                                0x18
#define SDMA1_TLBI_GCR_CNTL__TLBI_CMD_DW_MASK                                                                 0x0000000FL
#define SDMA1_TLBI_GCR_CNTL__GCR_CMD_DW_MASK                                                                  0x000000F0L
#define SDMA1_TLBI_GCR_CNTL__GCR_CLKEN_CYCLE_MASK                                                             0x00000F00L
#define SDMA1_TLBI_GCR_CNTL__TLBI_CREDIT_MASK                                                                 0x00FF0000L
#define SDMA1_TLBI_GCR_CNTL__GCR_CREDIT_MASK                                                                  0xFF000000L
//SDMA1_TILING_CONFIG
#define SDMA1_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT                                                      0x4
#define SDMA1_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK                                                        0x00000070L
//SDMA1_INT_STATUS
#define SDMA1_INT_STATUS__DATA__SHIFT                                                                         0x0
#define SDMA1_INT_STATUS__DATA_MASK                                                                           0xFFFFFFFFL
//SDMA1_HOLE_ADDR_LO
#define SDMA1_HOLE_ADDR_LO__VALUE__SHIFT                                                                      0x0
#define SDMA1_HOLE_ADDR_LO__VALUE_MASK                                                                        0xFFFFFFFFL
//SDMA1_HOLE_ADDR_HI
#define SDMA1_HOLE_ADDR_HI__VALUE__SHIFT                                                                      0x0
#define SDMA1_HOLE_ADDR_HI__VALUE_MASK                                                                        0xFFFFFFFFL
//SDMA1_CLOCK_GATING_REG
#define SDMA1_CLOCK_GATING_REG__DYN_CLK_GATE_STATUS__SHIFT                                                    0x0
#define SDMA1_CLOCK_GATING_REG__PTR_CLK_GATE_STATUS__SHIFT                                                    0x1
#define SDMA1_CLOCK_GATING_REG__CE_CLK_GATE_STATUS__SHIFT                                                     0x2
#define SDMA1_CLOCK_GATING_REG__CE_BC_CLK_GATE_STATUS__SHIFT                                                  0x3
#define SDMA1_CLOCK_GATING_REG__CE_NBC_CLK_GATE_STATUS__SHIFT                                                 0x4
#define SDMA1_CLOCK_GATING_REG__REG_CLK_GATE_STATUS__SHIFT                                                    0x5
#define SDMA1_CLOCK_GATING_REG__DYN_CLK_GATE_STATUS_MASK                                                      0x00000001L
#define SDMA1_CLOCK_GATING_REG__PTR_CLK_GATE_STATUS_MASK                                                      0x00000002L
#define SDMA1_CLOCK_GATING_REG__CE_CLK_GATE_STATUS_MASK                                                       0x00000004L
#define SDMA1_CLOCK_GATING_REG__CE_BC_CLK_GATE_STATUS_MASK                                                    0x00000008L
#define SDMA1_CLOCK_GATING_REG__CE_NBC_CLK_GATE_STATUS_MASK                                                   0x00000010L
#define SDMA1_CLOCK_GATING_REG__REG_CLK_GATE_STATUS_MASK                                                      0x00000020L
//SDMA1_STATUS4_REG
#define SDMA1_STATUS4_REG__IDLE__SHIFT                                                                        0x0
#define SDMA1_STATUS4_REG__IH_OUTSTANDING__SHIFT                                                              0x2
#define SDMA1_STATUS4_REG__SEM_OUTSTANDING__SHIFT                                                             0x3
#define SDMA1_STATUS4_REG__CH_RD_OUTSTANDING__SHIFT                                                           0x4
#define SDMA1_STATUS4_REG__CH_WR_OUTSTANDING__SHIFT                                                           0x5
#define SDMA1_STATUS4_REG__GCR_OUTSTANDING__SHIFT                                                             0x6
#define SDMA1_STATUS4_REG__TLBI_OUTSTANDING__SHIFT                                                            0x7
#define SDMA1_STATUS4_REG__UTCL2_RD_OUTSTANDING__SHIFT                                                        0x8
#define SDMA1_STATUS4_REG__UTCL2_WR_OUTSTANDING__SHIFT                                                        0x9
#define SDMA1_STATUS4_REG__REG_POLLING__SHIFT                                                                 0xa
#define SDMA1_STATUS4_REG__MEM_POLLING__SHIFT                                                                 0xb
#define SDMA1_STATUS4_REG__UTCL2_RD_XNACK__SHIFT                                                              0xc
#define SDMA1_STATUS4_REG__UTCL2_WR_XNACK__SHIFT                                                              0xe
#define SDMA1_STATUS4_REG__ACTIVE_QUEUE_ID__SHIFT                                                             0x10
#define SDMA1_STATUS4_REG__SRIOV_WATING_RLCV_CMD__SHIFT                                                       0x14
#define SDMA1_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD__SHIFT                                                    0x15
#define SDMA1_STATUS4_REG__IDLE_MASK                                                                          0x00000001L
#define SDMA1_STATUS4_REG__IH_OUTSTANDING_MASK                                                                0x00000004L
#define SDMA1_STATUS4_REG__SEM_OUTSTANDING_MASK                                                               0x00000008L
#define SDMA1_STATUS4_REG__CH_RD_OUTSTANDING_MASK                                                             0x00000010L
#define SDMA1_STATUS4_REG__CH_WR_OUTSTANDING_MASK                                                             0x00000020L
#define SDMA1_STATUS4_REG__GCR_OUTSTANDING_MASK                                                               0x00000040L
#define SDMA1_STATUS4_REG__TLBI_OUTSTANDING_MASK                                                              0x00000080L
#define SDMA1_STATUS4_REG__UTCL2_RD_OUTSTANDING_MASK                                                          0x00000100L
#define SDMA1_STATUS4_REG__UTCL2_WR_OUTSTANDING_MASK                                                          0x00000200L
#define SDMA1_STATUS4_REG__REG_POLLING_MASK                                                                   0x00000400L
#define SDMA1_STATUS4_REG__MEM_POLLING_MASK                                                                   0x00000800L
#define SDMA1_STATUS4_REG__UTCL2_RD_XNACK_MASK                                                                0x00003000L
#define SDMA1_STATUS4_REG__UTCL2_WR_XNACK_MASK                                                                0x0000C000L
#define SDMA1_STATUS4_REG__ACTIVE_QUEUE_ID_MASK                                                               0x000F0000L
#define SDMA1_STATUS4_REG__SRIOV_WATING_RLCV_CMD_MASK                                                         0x00100000L
#define SDMA1_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD_MASK                                                      0x00200000L
//SDMA1_SCRATCH_RAM_DATA
#define SDMA1_SCRATCH_RAM_DATA__DATA__SHIFT                                                                   0x0
#define SDMA1_SCRATCH_RAM_DATA__DATA_MASK                                                                     0xFFFFFFFFL
//SDMA1_SCRATCH_RAM_ADDR
#define SDMA1_SCRATCH_RAM_ADDR__ADDR__SHIFT                                                                   0x0
#define SDMA1_SCRATCH_RAM_ADDR__ADDR_MASK                                                                     0x000003FFL
//SDMA1_TIMESTAMP_CNTL
#define SDMA1_TIMESTAMP_CNTL__CAPTURE__SHIFT                                                                  0x0
#define SDMA1_TIMESTAMP_CNTL__CAPTURE_MASK                                                                    0x00000001L
//SDMA1_STATUS5_REG
#define SDMA1_STATUS5_REG__GFX_RB_ENABLE_STATUS__SHIFT                                                        0x0
#define SDMA1_STATUS5_REG__PAGE_RB_ENABLE_STATUS__SHIFT                                                       0x1
#define SDMA1_STATUS5_REG__RLC0_RB_ENABLE_STATUS__SHIFT                                                       0x2
#define SDMA1_STATUS5_REG__RLC1_RB_ENABLE_STATUS__SHIFT                                                       0x3
#define SDMA1_STATUS5_REG__RLC2_RB_ENABLE_STATUS__SHIFT                                                       0x4
#define SDMA1_STATUS5_REG__RLC3_RB_ENABLE_STATUS__SHIFT                                                       0x5
#define SDMA1_STATUS5_REG__RLC4_RB_ENABLE_STATUS__SHIFT                                                       0x6
#define SDMA1_STATUS5_REG__RLC5_RB_ENABLE_STATUS__SHIFT                                                       0x7
#define SDMA1_STATUS5_REG__RLC6_RB_ENABLE_STATUS__SHIFT                                                       0x8
#define SDMA1_STATUS5_REG__RLC7_RB_ENABLE_STATUS__SHIFT                                                       0x9
#define SDMA1_STATUS5_REG__ACTIVE_QUEUE_ID__SHIFT                                                             0x10
#define SDMA1_STATUS5_REG__GFX_RB_ENABLE_STATUS_MASK                                                          0x00000001L
#define SDMA1_STATUS5_REG__PAGE_RB_ENABLE_STATUS_MASK                                                         0x00000002L
#define SDMA1_STATUS5_REG__RLC0_RB_ENABLE_STATUS_MASK                                                         0x00000004L
#define SDMA1_STATUS5_REG__RLC1_RB_ENABLE_STATUS_MASK                                                         0x00000008L
#define SDMA1_STATUS5_REG__RLC2_RB_ENABLE_STATUS_MASK                                                         0x00000010L
#define SDMA1_STATUS5_REG__RLC3_RB_ENABLE_STATUS_MASK                                                         0x00000020L
#define SDMA1_STATUS5_REG__RLC4_RB_ENABLE_STATUS_MASK                                                         0x00000040L
#define SDMA1_STATUS5_REG__RLC5_RB_ENABLE_STATUS_MASK                                                         0x00000080L
#define SDMA1_STATUS5_REG__RLC6_RB_ENABLE_STATUS_MASK                                                         0x00000100L
#define SDMA1_STATUS5_REG__RLC7_RB_ENABLE_STATUS_MASK                                                         0x00000200L
#define SDMA1_STATUS5_REG__ACTIVE_QUEUE_ID_MASK                                                               0x000F0000L
//SDMA1_QUEUE_RESET_REQ
#define SDMA1_QUEUE_RESET_REQ__GFX_QUEUE_RESET__SHIFT                                                         0x0
#define SDMA1_QUEUE_RESET_REQ__PAGE_QUEUE_RESET__SHIFT                                                        0x1
#define SDMA1_QUEUE_RESET_REQ__RLC0_QUEUE_RESET__SHIFT                                                        0x2
#define SDMA1_QUEUE_RESET_REQ__RLC1_QUEUE_RESET__SHIFT                                                        0x3
#define SDMA1_QUEUE_RESET_REQ__RLC2_QUEUE_RESET__SHIFT                                                        0x4
#define SDMA1_QUEUE_RESET_REQ__RLC3_QUEUE_RESET__SHIFT                                                        0x5
#define SDMA1_QUEUE_RESET_REQ__RLC4_QUEUE_RESET__SHIFT                                                        0x6
#define SDMA1_QUEUE_RESET_REQ__RLC5_QUEUE_RESET__SHIFT                                                        0x7
#define SDMA1_QUEUE_RESET_REQ__RLC6_QUEUE_RESET__SHIFT                                                        0x8
#define SDMA1_QUEUE_RESET_REQ__RLC7_QUEUE_RESET__SHIFT                                                        0x9
#define SDMA1_QUEUE_RESET_REQ__RESERVED__SHIFT                                                                0xa
#define SDMA1_QUEUE_RESET_REQ__GFX_QUEUE_RESET_MASK                                                           0x00000001L
#define SDMA1_QUEUE_RESET_REQ__PAGE_QUEUE_RESET_MASK                                                          0x00000002L
#define SDMA1_QUEUE_RESET_REQ__RLC0_QUEUE_RESET_MASK                                                          0x00000004L
#define SDMA1_QUEUE_RESET_REQ__RLC1_QUEUE_RESET_MASK                                                          0x00000008L
#define SDMA1_QUEUE_RESET_REQ__RLC2_QUEUE_RESET_MASK                                                          0x00000010L
#define SDMA1_QUEUE_RESET_REQ__RLC3_QUEUE_RESET_MASK                                                          0x00000020L
#define SDMA1_QUEUE_RESET_REQ__RLC4_QUEUE_RESET_MASK                                                          0x00000040L
#define SDMA1_QUEUE_RESET_REQ__RLC5_QUEUE_RESET_MASK                                                          0x00000080L
#define SDMA1_QUEUE_RESET_REQ__RLC6_QUEUE_RESET_MASK                                                          0x00000100L
#define SDMA1_QUEUE_RESET_REQ__RLC7_QUEUE_RESET_MASK                                                          0x00000200L
#define SDMA1_QUEUE_RESET_REQ__RESERVED_MASK                                                                  0xFFFFFC00L
//SDMA1_GFX_RB_CNTL
#define SDMA1_GFX_RB_CNTL__RB_ENABLE__SHIFT                                                                   0x0
#define SDMA1_GFX_RB_CNTL__RB_SIZE__SHIFT                                                                     0x1
#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                              0x9
#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                       0xc
#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                  0xd
#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                        0x10
#define SDMA1_GFX_RB_CNTL__RB_PRIV__SHIFT                                                                     0x17
#define SDMA1_GFX_RB_CNTL__RB_VMID__SHIFT                                                                     0x18
#define SDMA1_GFX_RB_CNTL__RPTR_WB_IDLE__SHIFT                                                                0x1f
#define SDMA1_GFX_RB_CNTL__RB_ENABLE_MASK                                                                     0x00000001L
#define SDMA1_GFX_RB_CNTL__RB_SIZE_MASK                                                                       0x0000003EL
#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK                                                                0x00000200L
#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                         0x00001000L
#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                    0x00002000L
#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                          0x001F0000L
#define SDMA1_GFX_RB_CNTL__RB_PRIV_MASK                                                                       0x00800000L
#define SDMA1_GFX_RB_CNTL__RB_VMID_MASK                                                                       0x0F000000L
#define SDMA1_GFX_RB_CNTL__RPTR_WB_IDLE_MASK                                                                  0x80000000L
//SDMA1_GFX_RB_BASE
#define SDMA1_GFX_RB_BASE__ADDR__SHIFT                                                                        0x0
#define SDMA1_GFX_RB_BASE__ADDR_MASK                                                                          0xFFFFFFFFL
//SDMA1_GFX_RB_BASE_HI
#define SDMA1_GFX_RB_BASE_HI__ADDR__SHIFT                                                                     0x0
#define SDMA1_GFX_RB_BASE_HI__ADDR_MASK                                                                       0x00FFFFFFL
//SDMA1_GFX_RB_RPTR
#define SDMA1_GFX_RB_RPTR__OFFSET__SHIFT                                                                      0x0
#define SDMA1_GFX_RB_RPTR__OFFSET_MASK                                                                        0xFFFFFFFFL
//SDMA1_GFX_RB_RPTR_HI
#define SDMA1_GFX_RB_RPTR_HI__OFFSET__SHIFT                                                                   0x0
#define SDMA1_GFX_RB_RPTR_HI__OFFSET_MASK                                                                     0xFFFFFFFFL
//SDMA1_GFX_RB_WPTR
#define SDMA1_GFX_RB_WPTR__OFFSET__SHIFT                                                                      0x0
#define SDMA1_GFX_RB_WPTR__OFFSET_MASK                                                                        0xFFFFFFFFL
//SDMA1_GFX_RB_WPTR_HI
#define SDMA1_GFX_RB_WPTR_HI__OFFSET__SHIFT                                                                   0x0
#define SDMA1_GFX_RB_WPTR_HI__OFFSET_MASK                                                                     0xFFFFFFFFL
//SDMA1_GFX_RB_WPTR_POLL_CNTL
#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                            0x0
#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                       0x1
#define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                   0x2
#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                         0x4
#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                   0x10
#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                              0x00000001L
#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                         0x00000002L
#define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                     0x00000004L
#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                           0x0000FFF0L
#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                     0xFFFF0000L
//SDMA1_GFX_RB_RPTR_ADDR_HI
#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                                0x0
#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR_MASK                                                                  0xFFFFFFFFL
//SDMA1_GFX_RB_RPTR_ADDR_LO
#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                                0x2
#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR_MASK                                                                  0xFFFFFFFCL
//SDMA1_GFX_IB_CNTL
#define SDMA1_GFX_IB_CNTL__IB_ENABLE__SHIFT                                                                   0x0
#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                              0x4
#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                            0x8
#define SDMA1_GFX_IB_CNTL__CMD_VMID__SHIFT                                                                    0x10
#define SDMA1_GFX_IB_CNTL__IB_ENABLE_MASK                                                                     0x00000001L
#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK                                                                0x00000010L
#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                              0x00000100L
#define SDMA1_GFX_IB_CNTL__CMD_VMID_MASK                                                                      0x000F0000L
//SDMA1_GFX_IB_RPTR
#define SDMA1_GFX_IB_RPTR__OFFSET__SHIFT                                                                      0x2
#define SDMA1_GFX_IB_RPTR__OFFSET_MASK                                                                        0x003FFFFCL
//SDMA1_GFX_IB_OFFSET
#define SDMA1_GFX_IB_OFFSET__OFFSET__SHIFT                                                                    0x2
#define SDMA1_GFX_IB_OFFSET__OFFSET_MASK                                                                      0x003FFFFCL
//SDMA1_GFX_IB_BASE_LO
#define SDMA1_GFX_IB_BASE_LO__ADDR__SHIFT                                                                     0x5
#define SDMA1_GFX_IB_BASE_LO__ADDR_MASK                                                                       0xFFFFFFE0L
//SDMA1_GFX_IB_BASE_HI
#define SDMA1_GFX_IB_BASE_HI__ADDR__SHIFT                                                                     0x0
#define SDMA1_GFX_IB_BASE_HI__ADDR_MASK                                                                       0xFFFFFFFFL
//SDMA1_GFX_IB_SIZE
#define SDMA1_GFX_IB_SIZE__SIZE__SHIFT                                                                        0x0
#define SDMA1_GFX_IB_SIZE__SIZE_MASK                                                                          0x000FFFFFL
//SDMA1_GFX_SKIP_CNTL
#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT                                                                0x0
#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT_MASK                                                                  0x000FFFFFL
//SDMA1_GFX_CONTEXT_STATUS
#define SDMA1_GFX_CONTEXT_STATUS__SELECTED__SHIFT                                                             0x0
#define SDMA1_GFX_CONTEXT_STATUS__IDLE__SHIFT                                                                 0x2
#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED__SHIFT                                                              0x3
#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT                                                            0x4
#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                           0x7
#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                          0x8
#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT                                                            0x9
#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                      0xa
#define SDMA1_GFX_CONTEXT_STATUS__SELECTED_MASK                                                               0x00000001L
#define SDMA1_GFX_CONTEXT_STATUS__IDLE_MASK                                                                   0x00000004L
#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED_MASK                                                                0x00000008L
#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION_MASK                                                              0x00000070L
#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                             0x00000080L
#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY_MASK                                                            0x00000100L
#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED_MASK                                                              0x00000200L
#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                        0x00000400L
//SDMA1_GFX_DOORBELL
#define SDMA1_GFX_DOORBELL__ENABLE__SHIFT                                                                     0x1c
#define SDMA1_GFX_DOORBELL__CAPTURED__SHIFT                                                                   0x1e
#define SDMA1_GFX_DOORBELL__ENABLE_MASK                                                                       0x10000000L
#define SDMA1_GFX_DOORBELL__CAPTURED_MASK                                                                     0x40000000L
//SDMA1_GFX_CONTEXT_CNTL
#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT                                                             0x10
#define SDMA1_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT                                                            0x18
#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX_MASK                                                               0x00010000L
#define SDMA1_GFX_CONTEXT_CNTL__SESSION_SEL_MASK                                                              0x0F000000L
//SDMA1_GFX_STATUS
#define SDMA1_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                       0x0
#define SDMA1_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                          0x8
#define SDMA1_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                         0x000000FFL
#define SDMA1_GFX_STATUS__WPTR_UPDATE_PENDING_MASK                                                            0x00000100L
//SDMA1_GFX_DOORBELL_LOG
#define SDMA1_GFX_DOORBELL_LOG__BE_ERROR__SHIFT                                                               0x0
#define SDMA1_GFX_DOORBELL_LOG__DATA__SHIFT                                                                   0x2
#define SDMA1_GFX_DOORBELL_LOG__BE_ERROR_MASK                                                                 0x00000001L
#define SDMA1_GFX_DOORBELL_LOG__DATA_MASK                                                                     0xFFFFFFFCL
//SDMA1_GFX_WATERMARK
#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING__SHIFT                                                            0x0
#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING__SHIFT                                                            0x10
#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING_MASK                                                              0x00000FFFL
#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING_MASK                                                              0x03FF0000L
//SDMA1_GFX_DOORBELL_OFFSET
#define SDMA1_GFX_DOORBELL_OFFSET__OFFSET__SHIFT                                                              0x2
#define SDMA1_GFX_DOORBELL_OFFSET__OFFSET_MASK                                                                0x0FFFFFFCL
//SDMA1_GFX_CSA_ADDR_LO
#define SDMA1_GFX_CSA_ADDR_LO__ADDR__SHIFT                                                                    0x2
#define SDMA1_GFX_CSA_ADDR_LO__ADDR_MASK                                                                      0xFFFFFFFCL
//SDMA1_GFX_CSA_ADDR_HI
#define SDMA1_GFX_CSA_ADDR_HI__ADDR__SHIFT                                                                    0x0
#define SDMA1_GFX_CSA_ADDR_HI__ADDR_MASK                                                                      0xFFFFFFFFL
//SDMA1_GFX_IB_SUB_REMAIN
#define SDMA1_GFX_IB_SUB_REMAIN__SIZE__SHIFT                                                                  0x0
#define SDMA1_GFX_IB_SUB_REMAIN__SIZE_MASK                                                                    0x00003FFFL
//SDMA1_GFX_PREEMPT
#define SDMA1_GFX_PREEMPT__IB_PREEMPT__SHIFT                                                                  0x0
#define SDMA1_GFX_PREEMPT__IB_PREEMPT_MASK                                                                    0x00000001L
//SDMA1_GFX_DUMMY_REG
#define SDMA1_GFX_DUMMY_REG__DUMMY__SHIFT                                                                     0x0
#define SDMA1_GFX_DUMMY_REG__DUMMY_MASK                                                                       0xFFFFFFFFL
//SDMA1_GFX_RB_WPTR_POLL_ADDR_HI
#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                           0x0
#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                             0xFFFFFFFFL
//SDMA1_GFX_RB_WPTR_POLL_ADDR_LO
#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                           0x2
#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                             0xFFFFFFFCL
//SDMA1_GFX_RB_AQL_CNTL
#define SDMA1_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                              0x0
#define SDMA1_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                         0x1
#define SDMA1_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                             0x8
#define SDMA1_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                   0x10
#define SDMA1_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT                                             0x11
#define SDMA1_GFX_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT                                                          0x12
#define SDMA1_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK                                                                0x00000001L
#define SDMA1_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                           0x000000FEL
#define SDMA1_GFX_RB_AQL_CNTL__PACKET_STEP_MASK                                                               0x0000FF00L
#define SDMA1_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                     0x00010000L
#define SDMA1_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK                                               0x00020000L
#define SDMA1_GFX_RB_AQL_CNTL__OVERLAP_ENABLE_MASK                                                            0x00040000L
//SDMA1_GFX_MINOR_PTR_UPDATE
#define SDMA1_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                             0x0
#define SDMA1_GFX_MINOR_PTR_UPDATE__ENABLE_MASK                                                               0x00000001L
//SDMA1_GFX_MIDCMD_DATA0
#define SDMA1_GFX_MIDCMD_DATA0__DATA0__SHIFT                                                                  0x0
#define SDMA1_GFX_MIDCMD_DATA0__DATA0_MASK                                                                    0xFFFFFFFFL
//SDMA1_GFX_MIDCMD_DATA1
#define SDMA1_GFX_MIDCMD_DATA1__DATA1__SHIFT                                                                  0x0
#define SDMA1_GFX_MIDCMD_DATA1__DATA1_MASK                                                                    0xFFFFFFFFL
//SDMA1_GFX_MIDCMD_DATA2
#define SDMA1_GFX_MIDCMD_DATA2__DATA2__SHIFT                                                                  0x0
#define SDMA1_GFX_MIDCMD_DATA2__DATA2_MASK                                                                    0xFFFFFFFFL
//SDMA1_GFX_MIDCMD_DATA3
#define SDMA1_GFX_MIDCMD_DATA3__DATA3__SHIFT                                                                  0x0
#define SDMA1_GFX_MIDCMD_DATA3__DATA3_MASK                                                                    0xFFFFFFFFL
//SDMA1_GFX_MIDCMD_DATA4
#define SDMA1_GFX_MIDCMD_DATA4__DATA4__SHIFT                                                                  0x0
#define SDMA1_GFX_MIDCMD_DATA4__DATA4_MASK                                                                    0xFFFFFFFFL
//SDMA1_GFX_MIDCMD_DATA5
#define SDMA1_GFX_MIDCMD_DATA5__DATA5__SHIFT                                                                  0x0
#define SDMA1_GFX_MIDCMD_DATA5__DATA5_MASK                                                                    0xFFFFFFFFL
//SDMA1_GFX_MIDCMD_DATA6
#define SDMA1_GFX_MIDCMD_DATA6__DATA6__SHIFT                                                                  0x0
#define SDMA1_GFX_MIDCMD_DATA6__DATA6_MASK                                                                    0xFFFFFFFFL
//SDMA1_GFX_MIDCMD_DATA7
#define SDMA1_GFX_MIDCMD_DATA7__DATA7__SHIFT                                                                  0x0
#define SDMA1_GFX_MIDCMD_DATA7__DATA7_MASK                                                                    0xFFFFFFFFL
//SDMA1_GFX_MIDCMD_DATA8
#define SDMA1_GFX_MIDCMD_DATA8__DATA8__SHIFT                                                                  0x0
#define SDMA1_GFX_MIDCMD_DATA8__DATA8_MASK                                                                    0xFFFFFFFFL
//SDMA1_GFX_MIDCMD_DATA9
#define SDMA1_GFX_MIDCMD_DATA9__DATA9__SHIFT                                                                  0x0
#define SDMA1_GFX_MIDCMD_DATA9__DATA9_MASK                                                                    0xFFFFFFFFL
//SDMA1_GFX_MIDCMD_DATA10
#define SDMA1_GFX_MIDCMD_DATA10__DATA10__SHIFT                                                                0x0
#define SDMA1_GFX_MIDCMD_DATA10__DATA10_MASK                                                                  0xFFFFFFFFL
//SDMA1_GFX_MIDCMD_CNTL
#define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT                                                              0x0
#define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT                                                               0x1
#define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                             0x4
#define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                           0x8
#define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID_MASK                                                                0x00000001L
#define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE_MASK                                                                 0x00000002L
#define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK                                                               0x000000F0L
#define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                             0x00000100L
//SDMA1_PAGE_RB_CNTL
#define SDMA1_PAGE_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
#define SDMA1_PAGE_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
#define SDMA1_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
#define SDMA1_PAGE_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
#define SDMA1_PAGE_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
#define SDMA1_PAGE_RB_CNTL__RPTR_WB_IDLE__SHIFT                                                               0x1f
#define SDMA1_PAGE_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
#define SDMA1_PAGE_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
#define SDMA1_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
#define SDMA1_PAGE_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
#define SDMA1_PAGE_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
#define SDMA1_PAGE_RB_CNTL__RPTR_WB_IDLE_MASK                                                                 0x80000000L
//SDMA1_PAGE_RB_BASE
#define SDMA1_PAGE_RB_BASE__ADDR__SHIFT                                                                       0x0
#define SDMA1_PAGE_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
//SDMA1_PAGE_RB_BASE_HI
#define SDMA1_PAGE_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA1_PAGE_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
//SDMA1_PAGE_RB_RPTR
#define SDMA1_PAGE_RB_RPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA1_PAGE_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA1_PAGE_RB_RPTR_HI
#define SDMA1_PAGE_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA1_PAGE_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA1_PAGE_RB_WPTR
#define SDMA1_PAGE_RB_WPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA1_PAGE_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA1_PAGE_RB_WPTR_HI
#define SDMA1_PAGE_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA1_PAGE_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA1_PAGE_RB_WPTR_POLL_CNTL
#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
//SDMA1_PAGE_RB_RPTR_ADDR_HI
#define SDMA1_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
#define SDMA1_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
//SDMA1_PAGE_RB_RPTR_ADDR_LO
#define SDMA1_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
#define SDMA1_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
//SDMA1_PAGE_IB_CNTL
#define SDMA1_PAGE_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
#define SDMA1_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
#define SDMA1_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
#define SDMA1_PAGE_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
#define SDMA1_PAGE_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
#define SDMA1_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
#define SDMA1_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
#define SDMA1_PAGE_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
//SDMA1_PAGE_IB_RPTR
#define SDMA1_PAGE_IB_RPTR__OFFSET__SHIFT                                                                     0x2
#define SDMA1_PAGE_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
//SDMA1_PAGE_IB_OFFSET
#define SDMA1_PAGE_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
#define SDMA1_PAGE_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
//SDMA1_PAGE_IB_BASE_LO
#define SDMA1_PAGE_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
#define SDMA1_PAGE_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
//SDMA1_PAGE_IB_BASE_HI
#define SDMA1_PAGE_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA1_PAGE_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
//SDMA1_PAGE_IB_SIZE
#define SDMA1_PAGE_IB_SIZE__SIZE__SHIFT                                                                       0x0
#define SDMA1_PAGE_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
//SDMA1_PAGE_SKIP_CNTL
#define SDMA1_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
#define SDMA1_PAGE_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
//SDMA1_PAGE_CONTEXT_STATUS
#define SDMA1_PAGE_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
#define SDMA1_PAGE_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
#define SDMA1_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
#define SDMA1_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
#define SDMA1_PAGE_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
#define SDMA1_PAGE_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
#define SDMA1_PAGE_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
#define SDMA1_PAGE_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
//SDMA1_PAGE_DOORBELL
#define SDMA1_PAGE_DOORBELL__ENABLE__SHIFT                                                                    0x1c
#define SDMA1_PAGE_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
#define SDMA1_PAGE_DOORBELL__ENABLE_MASK                                                                      0x10000000L
#define SDMA1_PAGE_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
//SDMA1_PAGE_STATUS
#define SDMA1_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
#define SDMA1_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
#define SDMA1_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
#define SDMA1_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
//SDMA1_PAGE_DOORBELL_LOG
#define SDMA1_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
#define SDMA1_PAGE_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
#define SDMA1_PAGE_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
#define SDMA1_PAGE_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
//SDMA1_PAGE_WATERMARK
#define SDMA1_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
#define SDMA1_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
#define SDMA1_PAGE_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
#define SDMA1_PAGE_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
//SDMA1_PAGE_DOORBELL_OFFSET
#define SDMA1_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
#define SDMA1_PAGE_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
//SDMA1_PAGE_CSA_ADDR_LO
#define SDMA1_PAGE_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
#define SDMA1_PAGE_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
//SDMA1_PAGE_CSA_ADDR_HI
#define SDMA1_PAGE_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
#define SDMA1_PAGE_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
//SDMA1_PAGE_IB_SUB_REMAIN
#define SDMA1_PAGE_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
#define SDMA1_PAGE_IB_SUB_REMAIN__SIZE_MASK                                                                   0x00003FFFL
//SDMA1_PAGE_PREEMPT
#define SDMA1_PAGE_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
#define SDMA1_PAGE_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
//SDMA1_PAGE_DUMMY_REG
#define SDMA1_PAGE_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
#define SDMA1_PAGE_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
//SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI
#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
//SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO
#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
//SDMA1_PAGE_RB_AQL_CNTL
#define SDMA1_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
#define SDMA1_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
#define SDMA1_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
#define SDMA1_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                  0x10
#define SDMA1_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT                                            0x11
#define SDMA1_PAGE_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT                                                         0x12
#define SDMA1_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
#define SDMA1_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
#define SDMA1_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
#define SDMA1_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                    0x00010000L
#define SDMA1_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK                                              0x00020000L
#define SDMA1_PAGE_RB_AQL_CNTL__OVERLAP_ENABLE_MASK                                                           0x00040000L
//SDMA1_PAGE_MINOR_PTR_UPDATE
#define SDMA1_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
#define SDMA1_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
//SDMA1_PAGE_MIDCMD_DATA0
#define SDMA1_PAGE_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
#define SDMA1_PAGE_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
//SDMA1_PAGE_MIDCMD_DATA1
#define SDMA1_PAGE_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
#define SDMA1_PAGE_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
//SDMA1_PAGE_MIDCMD_DATA2
#define SDMA1_PAGE_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
#define SDMA1_PAGE_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
//SDMA1_PAGE_MIDCMD_DATA3
#define SDMA1_PAGE_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
#define SDMA1_PAGE_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
//SDMA1_PAGE_MIDCMD_DATA4
#define SDMA1_PAGE_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
#define SDMA1_PAGE_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
//SDMA1_PAGE_MIDCMD_DATA5
#define SDMA1_PAGE_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
#define SDMA1_PAGE_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
//SDMA1_PAGE_MIDCMD_DATA6
#define SDMA1_PAGE_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
#define SDMA1_PAGE_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
//SDMA1_PAGE_MIDCMD_DATA7
#define SDMA1_PAGE_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
#define SDMA1_PAGE_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
//SDMA1_PAGE_MIDCMD_DATA8
#define SDMA1_PAGE_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
#define SDMA1_PAGE_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
//SDMA1_PAGE_MIDCMD_DATA9
#define SDMA1_PAGE_MIDCMD_DATA9__DATA9__SHIFT                                                                 0x0
#define SDMA1_PAGE_MIDCMD_DATA9__DATA9_MASK                                                                   0xFFFFFFFFL
//SDMA1_PAGE_MIDCMD_DATA10
#define SDMA1_PAGE_MIDCMD_DATA10__DATA10__SHIFT                                                               0x0
#define SDMA1_PAGE_MIDCMD_DATA10__DATA10_MASK                                                                 0xFFFFFFFFL
//SDMA1_PAGE_MIDCMD_CNTL
#define SDMA1_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
#define SDMA1_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
#define SDMA1_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
#define SDMA1_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
#define SDMA1_PAGE_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
#define SDMA1_PAGE_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
#define SDMA1_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
#define SDMA1_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
//SDMA1_RLC0_RB_CNTL
#define SDMA1_RLC0_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
#define SDMA1_RLC0_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
#define SDMA1_RLC0_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
#define SDMA1_RLC0_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
#define SDMA1_RLC0_RB_CNTL__RPTR_WB_IDLE__SHIFT                                                               0x1f
#define SDMA1_RLC0_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
#define SDMA1_RLC0_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
#define SDMA1_RLC0_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
#define SDMA1_RLC0_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
#define SDMA1_RLC0_RB_CNTL__RPTR_WB_IDLE_MASK                                                                 0x80000000L
//SDMA1_RLC0_RB_BASE
#define SDMA1_RLC0_RB_BASE__ADDR__SHIFT                                                                       0x0
#define SDMA1_RLC0_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
//SDMA1_RLC0_RB_BASE_HI
#define SDMA1_RLC0_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA1_RLC0_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
//SDMA1_RLC0_RB_RPTR
#define SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA1_RLC0_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA1_RLC0_RB_RPTR_HI
#define SDMA1_RLC0_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA1_RLC0_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA1_RLC0_RB_WPTR
#define SDMA1_RLC0_RB_WPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA1_RLC0_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA1_RLC0_RB_WPTR_HI
#define SDMA1_RLC0_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA1_RLC0_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA1_RLC0_RB_WPTR_POLL_CNTL
#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
//SDMA1_RLC0_RB_RPTR_ADDR_HI
#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
//SDMA1_RLC0_RB_RPTR_ADDR_LO
#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
//SDMA1_RLC0_IB_CNTL
#define SDMA1_RLC0_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
#define SDMA1_RLC0_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
#define SDMA1_RLC0_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
#define SDMA1_RLC0_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
//SDMA1_RLC0_IB_RPTR
#define SDMA1_RLC0_IB_RPTR__OFFSET__SHIFT                                                                     0x2
#define SDMA1_RLC0_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
//SDMA1_RLC0_IB_OFFSET
#define SDMA1_RLC0_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
#define SDMA1_RLC0_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
//SDMA1_RLC0_IB_BASE_LO
#define SDMA1_RLC0_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
#define SDMA1_RLC0_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
//SDMA1_RLC0_IB_BASE_HI
#define SDMA1_RLC0_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA1_RLC0_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
//SDMA1_RLC0_IB_SIZE
#define SDMA1_RLC0_IB_SIZE__SIZE__SHIFT                                                                       0x0
#define SDMA1_RLC0_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
//SDMA1_RLC0_SKIP_CNTL
#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
//SDMA1_RLC0_CONTEXT_STATUS
#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
#define SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
#define SDMA1_RLC0_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
//SDMA1_RLC0_DOORBELL
#define SDMA1_RLC0_DOORBELL__ENABLE__SHIFT                                                                    0x1c
#define SDMA1_RLC0_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
#define SDMA1_RLC0_DOORBELL__ENABLE_MASK                                                                      0x10000000L
#define SDMA1_RLC0_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
//SDMA1_RLC0_STATUS
#define SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
#define SDMA1_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
#define SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
#define SDMA1_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
//SDMA1_RLC0_DOORBELL_LOG
#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
#define SDMA1_RLC0_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
#define SDMA1_RLC0_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
//SDMA1_RLC0_WATERMARK
#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
//SDMA1_RLC0_DOORBELL_OFFSET
#define SDMA1_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
#define SDMA1_RLC0_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
//SDMA1_RLC0_CSA_ADDR_LO
#define SDMA1_RLC0_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
#define SDMA1_RLC0_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
//SDMA1_RLC0_CSA_ADDR_HI
#define SDMA1_RLC0_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
#define SDMA1_RLC0_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
//SDMA1_RLC0_IB_SUB_REMAIN
#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE_MASK                                                                   0x00003FFFL
//SDMA1_RLC0_PREEMPT
#define SDMA1_RLC0_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
#define SDMA1_RLC0_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
//SDMA1_RLC0_DUMMY_REG
#define SDMA1_RLC0_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
#define SDMA1_RLC0_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
//SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI
#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
//SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO
#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
//SDMA1_RLC0_RB_AQL_CNTL
#define SDMA1_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
#define SDMA1_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
#define SDMA1_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
#define SDMA1_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                  0x10
#define SDMA1_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT                                            0x11
#define SDMA1_RLC0_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT                                                         0x12
#define SDMA1_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
#define SDMA1_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
#define SDMA1_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
#define SDMA1_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                    0x00010000L
#define SDMA1_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK                                              0x00020000L
#define SDMA1_RLC0_RB_AQL_CNTL__OVERLAP_ENABLE_MASK                                                           0x00040000L
//SDMA1_RLC0_MINOR_PTR_UPDATE
#define SDMA1_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
#define SDMA1_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
//SDMA1_RLC0_MIDCMD_DATA0
#define SDMA1_RLC0_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
#define SDMA1_RLC0_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC0_MIDCMD_DATA1
#define SDMA1_RLC0_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
#define SDMA1_RLC0_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC0_MIDCMD_DATA2
#define SDMA1_RLC0_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
#define SDMA1_RLC0_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC0_MIDCMD_DATA3
#define SDMA1_RLC0_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
#define SDMA1_RLC0_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC0_MIDCMD_DATA4
#define SDMA1_RLC0_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
#define SDMA1_RLC0_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC0_MIDCMD_DATA5
#define SDMA1_RLC0_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
#define SDMA1_RLC0_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC0_MIDCMD_DATA6
#define SDMA1_RLC0_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
#define SDMA1_RLC0_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC0_MIDCMD_DATA7
#define SDMA1_RLC0_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
#define SDMA1_RLC0_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC0_MIDCMD_DATA8
#define SDMA1_RLC0_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
#define SDMA1_RLC0_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC0_MIDCMD_DATA9
#define SDMA1_RLC0_MIDCMD_DATA9__DATA9__SHIFT                                                                 0x0
#define SDMA1_RLC0_MIDCMD_DATA9__DATA9_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC0_MIDCMD_DATA10
#define SDMA1_RLC0_MIDCMD_DATA10__DATA10__SHIFT                                                               0x0
#define SDMA1_RLC0_MIDCMD_DATA10__DATA10_MASK                                                                 0xFFFFFFFFL
//SDMA1_RLC0_MIDCMD_CNTL
#define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
#define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
#define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
#define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
#define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
#define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
#define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
#define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
//SDMA1_RLC1_RB_CNTL
#define SDMA1_RLC1_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
#define SDMA1_RLC1_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
#define SDMA1_RLC1_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
#define SDMA1_RLC1_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
#define SDMA1_RLC1_RB_CNTL__RPTR_WB_IDLE__SHIFT                                                               0x1f
#define SDMA1_RLC1_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
#define SDMA1_RLC1_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
#define SDMA1_RLC1_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
#define SDMA1_RLC1_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
#define SDMA1_RLC1_RB_CNTL__RPTR_WB_IDLE_MASK                                                                 0x80000000L
//SDMA1_RLC1_RB_BASE
#define SDMA1_RLC1_RB_BASE__ADDR__SHIFT                                                                       0x0
#define SDMA1_RLC1_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
//SDMA1_RLC1_RB_BASE_HI
#define SDMA1_RLC1_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA1_RLC1_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
//SDMA1_RLC1_RB_RPTR
#define SDMA1_RLC1_RB_RPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA1_RLC1_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA1_RLC1_RB_RPTR_HI
#define SDMA1_RLC1_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA1_RLC1_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA1_RLC1_RB_WPTR
#define SDMA1_RLC1_RB_WPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA1_RLC1_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA1_RLC1_RB_WPTR_HI
#define SDMA1_RLC1_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA1_RLC1_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA1_RLC1_RB_WPTR_POLL_CNTL
#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
//SDMA1_RLC1_RB_RPTR_ADDR_HI
#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
//SDMA1_RLC1_RB_RPTR_ADDR_LO
#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
//SDMA1_RLC1_IB_CNTL
#define SDMA1_RLC1_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
#define SDMA1_RLC1_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
#define SDMA1_RLC1_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
#define SDMA1_RLC1_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
//SDMA1_RLC1_IB_RPTR
#define SDMA1_RLC1_IB_RPTR__OFFSET__SHIFT                                                                     0x2
#define SDMA1_RLC1_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
//SDMA1_RLC1_IB_OFFSET
#define SDMA1_RLC1_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
#define SDMA1_RLC1_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
//SDMA1_RLC1_IB_BASE_LO
#define SDMA1_RLC1_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
#define SDMA1_RLC1_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
//SDMA1_RLC1_IB_BASE_HI
#define SDMA1_RLC1_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA1_RLC1_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
//SDMA1_RLC1_IB_SIZE
#define SDMA1_RLC1_IB_SIZE__SIZE__SHIFT                                                                       0x0
#define SDMA1_RLC1_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
//SDMA1_RLC1_SKIP_CNTL
#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
//SDMA1_RLC1_CONTEXT_STATUS
#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
#define SDMA1_RLC1_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
#define SDMA1_RLC1_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
//SDMA1_RLC1_DOORBELL
#define SDMA1_RLC1_DOORBELL__ENABLE__SHIFT                                                                    0x1c
#define SDMA1_RLC1_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
#define SDMA1_RLC1_DOORBELL__ENABLE_MASK                                                                      0x10000000L
#define SDMA1_RLC1_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
//SDMA1_RLC1_STATUS
#define SDMA1_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
#define SDMA1_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
#define SDMA1_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
#define SDMA1_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
//SDMA1_RLC1_DOORBELL_LOG
#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
#define SDMA1_RLC1_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
#define SDMA1_RLC1_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
//SDMA1_RLC1_WATERMARK
#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
//SDMA1_RLC1_DOORBELL_OFFSET
#define SDMA1_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
#define SDMA1_RLC1_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
//SDMA1_RLC1_CSA_ADDR_LO
#define SDMA1_RLC1_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
#define SDMA1_RLC1_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
//SDMA1_RLC1_CSA_ADDR_HI
#define SDMA1_RLC1_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
#define SDMA1_RLC1_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
//SDMA1_RLC1_IB_SUB_REMAIN
#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE_MASK                                                                   0x00003FFFL
//SDMA1_RLC1_PREEMPT
#define SDMA1_RLC1_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
#define SDMA1_RLC1_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
//SDMA1_RLC1_DUMMY_REG
#define SDMA1_RLC1_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
#define SDMA1_RLC1_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
//SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI
#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
//SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO
#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
//SDMA1_RLC1_RB_AQL_CNTL
#define SDMA1_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
#define SDMA1_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
#define SDMA1_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
#define SDMA1_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                  0x10
#define SDMA1_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT                                            0x11
#define SDMA1_RLC1_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT                                                         0x12
#define SDMA1_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
#define SDMA1_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
#define SDMA1_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
#define SDMA1_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                    0x00010000L
#define SDMA1_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK                                              0x00020000L
#define SDMA1_RLC1_RB_AQL_CNTL__OVERLAP_ENABLE_MASK                                                           0x00040000L
//SDMA1_RLC1_MINOR_PTR_UPDATE
#define SDMA1_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
#define SDMA1_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
//SDMA1_RLC1_MIDCMD_DATA0
#define SDMA1_RLC1_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
#define SDMA1_RLC1_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC1_MIDCMD_DATA1
#define SDMA1_RLC1_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
#define SDMA1_RLC1_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC1_MIDCMD_DATA2
#define SDMA1_RLC1_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
#define SDMA1_RLC1_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC1_MIDCMD_DATA3
#define SDMA1_RLC1_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
#define SDMA1_RLC1_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC1_MIDCMD_DATA4
#define SDMA1_RLC1_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
#define SDMA1_RLC1_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC1_MIDCMD_DATA5
#define SDMA1_RLC1_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
#define SDMA1_RLC1_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC1_MIDCMD_DATA6
#define SDMA1_RLC1_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
#define SDMA1_RLC1_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC1_MIDCMD_DATA7
#define SDMA1_RLC1_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
#define SDMA1_RLC1_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC1_MIDCMD_DATA8
#define SDMA1_RLC1_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
#define SDMA1_RLC1_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC1_MIDCMD_DATA9
#define SDMA1_RLC1_MIDCMD_DATA9__DATA9__SHIFT                                                                 0x0
#define SDMA1_RLC1_MIDCMD_DATA9__DATA9_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC1_MIDCMD_DATA10
#define SDMA1_RLC1_MIDCMD_DATA10__DATA10__SHIFT                                                               0x0
#define SDMA1_RLC1_MIDCMD_DATA10__DATA10_MASK                                                                 0xFFFFFFFFL
//SDMA1_RLC1_MIDCMD_CNTL
#define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
#define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
#define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
#define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
#define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
#define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
#define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
#define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
//SDMA1_RLC2_RB_CNTL
#define SDMA1_RLC2_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
#define SDMA1_RLC2_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
#define SDMA1_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
#define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
#define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
#define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
#define SDMA1_RLC2_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
#define SDMA1_RLC2_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
#define SDMA1_RLC2_RB_CNTL__RPTR_WB_IDLE__SHIFT                                                               0x1f
#define SDMA1_RLC2_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
#define SDMA1_RLC2_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
#define SDMA1_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
#define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
#define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
#define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
#define SDMA1_RLC2_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
#define SDMA1_RLC2_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
#define SDMA1_RLC2_RB_CNTL__RPTR_WB_IDLE_MASK                                                                 0x80000000L
//SDMA1_RLC2_RB_BASE
#define SDMA1_RLC2_RB_BASE__ADDR__SHIFT                                                                       0x0
#define SDMA1_RLC2_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
//SDMA1_RLC2_RB_BASE_HI
#define SDMA1_RLC2_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA1_RLC2_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
//SDMA1_RLC2_RB_RPTR
#define SDMA1_RLC2_RB_RPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA1_RLC2_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA1_RLC2_RB_RPTR_HI
#define SDMA1_RLC2_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA1_RLC2_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA1_RLC2_RB_WPTR
#define SDMA1_RLC2_RB_WPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA1_RLC2_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA1_RLC2_RB_WPTR_HI
#define SDMA1_RLC2_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA1_RLC2_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA1_RLC2_RB_WPTR_POLL_CNTL
#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
//SDMA1_RLC2_RB_RPTR_ADDR_HI
#define SDMA1_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
#define SDMA1_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
//SDMA1_RLC2_RB_RPTR_ADDR_LO
#define SDMA1_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
#define SDMA1_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
//SDMA1_RLC2_IB_CNTL
#define SDMA1_RLC2_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
#define SDMA1_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
#define SDMA1_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
#define SDMA1_RLC2_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
#define SDMA1_RLC2_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
#define SDMA1_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
#define SDMA1_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
#define SDMA1_RLC2_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
//SDMA1_RLC2_IB_RPTR
#define SDMA1_RLC2_IB_RPTR__OFFSET__SHIFT                                                                     0x2
#define SDMA1_RLC2_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
//SDMA1_RLC2_IB_OFFSET
#define SDMA1_RLC2_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
#define SDMA1_RLC2_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
//SDMA1_RLC2_IB_BASE_LO
#define SDMA1_RLC2_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
#define SDMA1_RLC2_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
//SDMA1_RLC2_IB_BASE_HI
#define SDMA1_RLC2_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA1_RLC2_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
//SDMA1_RLC2_IB_SIZE
#define SDMA1_RLC2_IB_SIZE__SIZE__SHIFT                                                                       0x0
#define SDMA1_RLC2_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
//SDMA1_RLC2_SKIP_CNTL
#define SDMA1_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
#define SDMA1_RLC2_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
//SDMA1_RLC2_CONTEXT_STATUS
#define SDMA1_RLC2_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
#define SDMA1_RLC2_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
#define SDMA1_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
#define SDMA1_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
#define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
#define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
#define SDMA1_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
#define SDMA1_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
#define SDMA1_RLC2_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
#define SDMA1_RLC2_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
#define SDMA1_RLC2_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
#define SDMA1_RLC2_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
#define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
#define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
#define SDMA1_RLC2_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
#define SDMA1_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
//SDMA1_RLC2_DOORBELL
#define SDMA1_RLC2_DOORBELL__ENABLE__SHIFT                                                                    0x1c
#define SDMA1_RLC2_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
#define SDMA1_RLC2_DOORBELL__ENABLE_MASK                                                                      0x10000000L
#define SDMA1_RLC2_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
//SDMA1_RLC2_STATUS
#define SDMA1_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
#define SDMA1_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
#define SDMA1_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
#define SDMA1_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
//SDMA1_RLC2_DOORBELL_LOG
#define SDMA1_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
#define SDMA1_RLC2_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
#define SDMA1_RLC2_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
#define SDMA1_RLC2_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
//SDMA1_RLC2_WATERMARK
#define SDMA1_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
#define SDMA1_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
#define SDMA1_RLC2_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
#define SDMA1_RLC2_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
//SDMA1_RLC2_DOORBELL_OFFSET
#define SDMA1_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
#define SDMA1_RLC2_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
//SDMA1_RLC2_CSA_ADDR_LO
#define SDMA1_RLC2_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
#define SDMA1_RLC2_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
//SDMA1_RLC2_CSA_ADDR_HI
#define SDMA1_RLC2_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
#define SDMA1_RLC2_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
//SDMA1_RLC2_IB_SUB_REMAIN
#define SDMA1_RLC2_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
#define SDMA1_RLC2_IB_SUB_REMAIN__SIZE_MASK                                                                   0x00003FFFL
//SDMA1_RLC2_PREEMPT
#define SDMA1_RLC2_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
#define SDMA1_RLC2_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
//SDMA1_RLC2_DUMMY_REG
#define SDMA1_RLC2_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
#define SDMA1_RLC2_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
//SDMA1_RLC2_RB_WPTR_POLL_ADDR_HI
#define SDMA1_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
#define SDMA1_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
//SDMA1_RLC2_RB_WPTR_POLL_ADDR_LO
#define SDMA1_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
#define SDMA1_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
//SDMA1_RLC2_RB_AQL_CNTL
#define SDMA1_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
#define SDMA1_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
#define SDMA1_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
#define SDMA1_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                  0x10
#define SDMA1_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT                                            0x11
#define SDMA1_RLC2_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT                                                         0x12
#define SDMA1_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
#define SDMA1_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
#define SDMA1_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
#define SDMA1_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                    0x00010000L
#define SDMA1_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK                                              0x00020000L
#define SDMA1_RLC2_RB_AQL_CNTL__OVERLAP_ENABLE_MASK                                                           0x00040000L
//SDMA1_RLC2_MINOR_PTR_UPDATE
#define SDMA1_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
#define SDMA1_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
//SDMA1_RLC2_MIDCMD_DATA0
#define SDMA1_RLC2_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
#define SDMA1_RLC2_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC2_MIDCMD_DATA1
#define SDMA1_RLC2_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
#define SDMA1_RLC2_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC2_MIDCMD_DATA2
#define SDMA1_RLC2_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
#define SDMA1_RLC2_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC2_MIDCMD_DATA3
#define SDMA1_RLC2_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
#define SDMA1_RLC2_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC2_MIDCMD_DATA4
#define SDMA1_RLC2_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
#define SDMA1_RLC2_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC2_MIDCMD_DATA5
#define SDMA1_RLC2_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
#define SDMA1_RLC2_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC2_MIDCMD_DATA6
#define SDMA1_RLC2_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
#define SDMA1_RLC2_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC2_MIDCMD_DATA7
#define SDMA1_RLC2_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
#define SDMA1_RLC2_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC2_MIDCMD_DATA8
#define SDMA1_RLC2_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
#define SDMA1_RLC2_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC2_MIDCMD_DATA9
#define SDMA1_RLC2_MIDCMD_DATA9__DATA9__SHIFT                                                                 0x0
#define SDMA1_RLC2_MIDCMD_DATA9__DATA9_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC2_MIDCMD_DATA10
#define SDMA1_RLC2_MIDCMD_DATA10__DATA10__SHIFT                                                               0x0
#define SDMA1_RLC2_MIDCMD_DATA10__DATA10_MASK                                                                 0xFFFFFFFFL
//SDMA1_RLC2_MIDCMD_CNTL
#define SDMA1_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
#define SDMA1_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
#define SDMA1_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
#define SDMA1_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
#define SDMA1_RLC2_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
#define SDMA1_RLC2_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
#define SDMA1_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
#define SDMA1_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
//SDMA1_RLC3_RB_CNTL
#define SDMA1_RLC3_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
#define SDMA1_RLC3_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
#define SDMA1_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
#define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
#define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
#define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
#define SDMA1_RLC3_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
#define SDMA1_RLC3_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
#define SDMA1_RLC3_RB_CNTL__RPTR_WB_IDLE__SHIFT                                                               0x1f
#define SDMA1_RLC3_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
#define SDMA1_RLC3_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
#define SDMA1_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
#define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
#define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
#define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
#define SDMA1_RLC3_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
#define SDMA1_RLC3_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
#define SDMA1_RLC3_RB_CNTL__RPTR_WB_IDLE_MASK                                                                 0x80000000L
//SDMA1_RLC3_RB_BASE
#define SDMA1_RLC3_RB_BASE__ADDR__SHIFT                                                                       0x0
#define SDMA1_RLC3_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
//SDMA1_RLC3_RB_BASE_HI
#define SDMA1_RLC3_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA1_RLC3_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
//SDMA1_RLC3_RB_RPTR
#define SDMA1_RLC3_RB_RPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA1_RLC3_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA1_RLC3_RB_RPTR_HI
#define SDMA1_RLC3_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA1_RLC3_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA1_RLC3_RB_WPTR
#define SDMA1_RLC3_RB_WPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA1_RLC3_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA1_RLC3_RB_WPTR_HI
#define SDMA1_RLC3_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA1_RLC3_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA1_RLC3_RB_WPTR_POLL_CNTL
#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
//SDMA1_RLC3_RB_RPTR_ADDR_HI
#define SDMA1_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
#define SDMA1_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
//SDMA1_RLC3_RB_RPTR_ADDR_LO
#define SDMA1_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
#define SDMA1_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
//SDMA1_RLC3_IB_CNTL
#define SDMA1_RLC3_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
#define SDMA1_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
#define SDMA1_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
#define SDMA1_RLC3_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
#define SDMA1_RLC3_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
#define SDMA1_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
#define SDMA1_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
#define SDMA1_RLC3_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
//SDMA1_RLC3_IB_RPTR
#define SDMA1_RLC3_IB_RPTR__OFFSET__SHIFT                                                                     0x2
#define SDMA1_RLC3_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
//SDMA1_RLC3_IB_OFFSET
#define SDMA1_RLC3_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
#define SDMA1_RLC3_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
//SDMA1_RLC3_IB_BASE_LO
#define SDMA1_RLC3_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
#define SDMA1_RLC3_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
//SDMA1_RLC3_IB_BASE_HI
#define SDMA1_RLC3_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA1_RLC3_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
//SDMA1_RLC3_IB_SIZE
#define SDMA1_RLC3_IB_SIZE__SIZE__SHIFT                                                                       0x0
#define SDMA1_RLC3_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
//SDMA1_RLC3_SKIP_CNTL
#define SDMA1_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
#define SDMA1_RLC3_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
//SDMA1_RLC3_CONTEXT_STATUS
#define SDMA1_RLC3_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
#define SDMA1_RLC3_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
#define SDMA1_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
#define SDMA1_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
#define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
#define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
#define SDMA1_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
#define SDMA1_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
#define SDMA1_RLC3_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
#define SDMA1_RLC3_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
#define SDMA1_RLC3_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
#define SDMA1_RLC3_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
#define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
#define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
#define SDMA1_RLC3_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
#define SDMA1_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
//SDMA1_RLC3_DOORBELL
#define SDMA1_RLC3_DOORBELL__ENABLE__SHIFT                                                                    0x1c
#define SDMA1_RLC3_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
#define SDMA1_RLC3_DOORBELL__ENABLE_MASK                                                                      0x10000000L
#define SDMA1_RLC3_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
//SDMA1_RLC3_STATUS
#define SDMA1_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
#define SDMA1_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
#define SDMA1_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
#define SDMA1_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
//SDMA1_RLC3_DOORBELL_LOG
#define SDMA1_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
#define SDMA1_RLC3_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
#define SDMA1_RLC3_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
#define SDMA1_RLC3_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
//SDMA1_RLC3_WATERMARK
#define SDMA1_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
#define SDMA1_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
#define SDMA1_RLC3_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
#define SDMA1_RLC3_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
//SDMA1_RLC3_DOORBELL_OFFSET
#define SDMA1_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
#define SDMA1_RLC3_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
//SDMA1_RLC3_CSA_ADDR_LO
#define SDMA1_RLC3_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
#define SDMA1_RLC3_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
//SDMA1_RLC3_CSA_ADDR_HI
#define SDMA1_RLC3_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
#define SDMA1_RLC3_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
//SDMA1_RLC3_IB_SUB_REMAIN
#define SDMA1_RLC3_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
#define SDMA1_RLC3_IB_SUB_REMAIN__SIZE_MASK                                                                   0x00003FFFL
//SDMA1_RLC3_PREEMPT
#define SDMA1_RLC3_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
#define SDMA1_RLC3_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
//SDMA1_RLC3_DUMMY_REG
#define SDMA1_RLC3_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
#define SDMA1_RLC3_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
//SDMA1_RLC3_RB_WPTR_POLL_ADDR_HI
#define SDMA1_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
#define SDMA1_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
//SDMA1_RLC3_RB_WPTR_POLL_ADDR_LO
#define SDMA1_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
#define SDMA1_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
//SDMA1_RLC3_RB_AQL_CNTL
#define SDMA1_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
#define SDMA1_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
#define SDMA1_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
#define SDMA1_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                  0x10
#define SDMA1_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT                                            0x11
#define SDMA1_RLC3_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT                                                         0x12
#define SDMA1_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
#define SDMA1_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
#define SDMA1_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
#define SDMA1_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                    0x00010000L
#define SDMA1_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK                                              0x00020000L
#define SDMA1_RLC3_RB_AQL_CNTL__OVERLAP_ENABLE_MASK                                                           0x00040000L
//SDMA1_RLC3_MINOR_PTR_UPDATE
#define SDMA1_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
#define SDMA1_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
//SDMA1_RLC3_MIDCMD_DATA0
#define SDMA1_RLC3_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
#define SDMA1_RLC3_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC3_MIDCMD_DATA1
#define SDMA1_RLC3_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
#define SDMA1_RLC3_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC3_MIDCMD_DATA2
#define SDMA1_RLC3_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
#define SDMA1_RLC3_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC3_MIDCMD_DATA3
#define SDMA1_RLC3_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
#define SDMA1_RLC3_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC3_MIDCMD_DATA4
#define SDMA1_RLC3_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
#define SDMA1_RLC3_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC3_MIDCMD_DATA5
#define SDMA1_RLC3_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
#define SDMA1_RLC3_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC3_MIDCMD_DATA6
#define SDMA1_RLC3_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
#define SDMA1_RLC3_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC3_MIDCMD_DATA7
#define SDMA1_RLC3_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
#define SDMA1_RLC3_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC3_MIDCMD_DATA8
#define SDMA1_RLC3_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
#define SDMA1_RLC3_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC3_MIDCMD_DATA9
#define SDMA1_RLC3_MIDCMD_DATA9__DATA9__SHIFT                                                                 0x0
#define SDMA1_RLC3_MIDCMD_DATA9__DATA9_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC3_MIDCMD_DATA10
#define SDMA1_RLC3_MIDCMD_DATA10__DATA10__SHIFT                                                               0x0
#define SDMA1_RLC3_MIDCMD_DATA10__DATA10_MASK                                                                 0xFFFFFFFFL
//SDMA1_RLC3_MIDCMD_CNTL
#define SDMA1_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
#define SDMA1_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
#define SDMA1_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
#define SDMA1_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
#define SDMA1_RLC3_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
#define SDMA1_RLC3_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
#define SDMA1_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
#define SDMA1_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
//SDMA1_RLC4_RB_CNTL
#define SDMA1_RLC4_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
#define SDMA1_RLC4_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
#define SDMA1_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
#define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
#define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
#define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
#define SDMA1_RLC4_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
#define SDMA1_RLC4_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
#define SDMA1_RLC4_RB_CNTL__RPTR_WB_IDLE__SHIFT                                                               0x1f
#define SDMA1_RLC4_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
#define SDMA1_RLC4_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
#define SDMA1_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
#define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
#define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
#define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
#define SDMA1_RLC4_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
#define SDMA1_RLC4_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
#define SDMA1_RLC4_RB_CNTL__RPTR_WB_IDLE_MASK                                                                 0x80000000L
//SDMA1_RLC4_RB_BASE
#define SDMA1_RLC4_RB_BASE__ADDR__SHIFT                                                                       0x0
#define SDMA1_RLC4_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
//SDMA1_RLC4_RB_BASE_HI
#define SDMA1_RLC4_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA1_RLC4_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
//SDMA1_RLC4_RB_RPTR
#define SDMA1_RLC4_RB_RPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA1_RLC4_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA1_RLC4_RB_RPTR_HI
#define SDMA1_RLC4_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA1_RLC4_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA1_RLC4_RB_WPTR
#define SDMA1_RLC4_RB_WPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA1_RLC4_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA1_RLC4_RB_WPTR_HI
#define SDMA1_RLC4_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA1_RLC4_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA1_RLC4_RB_WPTR_POLL_CNTL
#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
//SDMA1_RLC4_RB_RPTR_ADDR_HI
#define SDMA1_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
#define SDMA1_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
//SDMA1_RLC4_RB_RPTR_ADDR_LO
#define SDMA1_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
#define SDMA1_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
//SDMA1_RLC4_IB_CNTL
#define SDMA1_RLC4_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
#define SDMA1_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
#define SDMA1_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
#define SDMA1_RLC4_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
#define SDMA1_RLC4_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
#define SDMA1_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
#define SDMA1_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
#define SDMA1_RLC4_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
//SDMA1_RLC4_IB_RPTR
#define SDMA1_RLC4_IB_RPTR__OFFSET__SHIFT                                                                     0x2
#define SDMA1_RLC4_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
//SDMA1_RLC4_IB_OFFSET
#define SDMA1_RLC4_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
#define SDMA1_RLC4_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
//SDMA1_RLC4_IB_BASE_LO
#define SDMA1_RLC4_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
#define SDMA1_RLC4_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
//SDMA1_RLC4_IB_BASE_HI
#define SDMA1_RLC4_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA1_RLC4_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
//SDMA1_RLC4_IB_SIZE
#define SDMA1_RLC4_IB_SIZE__SIZE__SHIFT                                                                       0x0
#define SDMA1_RLC4_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
//SDMA1_RLC4_SKIP_CNTL
#define SDMA1_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
#define SDMA1_RLC4_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
//SDMA1_RLC4_CONTEXT_STATUS
#define SDMA1_RLC4_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
#define SDMA1_RLC4_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
#define SDMA1_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
#define SDMA1_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
#define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
#define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
#define SDMA1_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
#define SDMA1_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
#define SDMA1_RLC4_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
#define SDMA1_RLC4_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
#define SDMA1_RLC4_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
#define SDMA1_RLC4_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
#define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
#define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
#define SDMA1_RLC4_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
#define SDMA1_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
//SDMA1_RLC4_DOORBELL
#define SDMA1_RLC4_DOORBELL__ENABLE__SHIFT                                                                    0x1c
#define SDMA1_RLC4_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
#define SDMA1_RLC4_DOORBELL__ENABLE_MASK                                                                      0x10000000L
#define SDMA1_RLC4_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
//SDMA1_RLC4_STATUS
#define SDMA1_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
#define SDMA1_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
#define SDMA1_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
#define SDMA1_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
//SDMA1_RLC4_DOORBELL_LOG
#define SDMA1_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
#define SDMA1_RLC4_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
#define SDMA1_RLC4_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
#define SDMA1_RLC4_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
//SDMA1_RLC4_WATERMARK
#define SDMA1_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
#define SDMA1_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
#define SDMA1_RLC4_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
#define SDMA1_RLC4_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
//SDMA1_RLC4_DOORBELL_OFFSET
#define SDMA1_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
#define SDMA1_RLC4_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
//SDMA1_RLC4_CSA_ADDR_LO
#define SDMA1_RLC4_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
#define SDMA1_RLC4_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
//SDMA1_RLC4_CSA_ADDR_HI
#define SDMA1_RLC4_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
#define SDMA1_RLC4_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
//SDMA1_RLC4_IB_SUB_REMAIN
#define SDMA1_RLC4_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
#define SDMA1_RLC4_IB_SUB_REMAIN__SIZE_MASK                                                                   0x00003FFFL
//SDMA1_RLC4_PREEMPT
#define SDMA1_RLC4_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
#define SDMA1_RLC4_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
//SDMA1_RLC4_DUMMY_REG
#define SDMA1_RLC4_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
#define SDMA1_RLC4_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
//SDMA1_RLC4_RB_WPTR_POLL_ADDR_HI
#define SDMA1_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
#define SDMA1_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
//SDMA1_RLC4_RB_WPTR_POLL_ADDR_LO
#define SDMA1_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
#define SDMA1_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
//SDMA1_RLC4_RB_AQL_CNTL
#define SDMA1_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
#define SDMA1_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
#define SDMA1_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
#define SDMA1_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                  0x10
#define SDMA1_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT                                            0x11
#define SDMA1_RLC4_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT                                                         0x12
#define SDMA1_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
#define SDMA1_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
#define SDMA1_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
#define SDMA1_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                    0x00010000L
#define SDMA1_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK                                              0x00020000L
#define SDMA1_RLC4_RB_AQL_CNTL__OVERLAP_ENABLE_MASK                                                           0x00040000L
//SDMA1_RLC4_MINOR_PTR_UPDATE
#define SDMA1_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
#define SDMA1_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
//SDMA1_RLC4_MIDCMD_DATA0
#define SDMA1_RLC4_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
#define SDMA1_RLC4_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC4_MIDCMD_DATA1
#define SDMA1_RLC4_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
#define SDMA1_RLC4_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC4_MIDCMD_DATA2
#define SDMA1_RLC4_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
#define SDMA1_RLC4_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC4_MIDCMD_DATA3
#define SDMA1_RLC4_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
#define SDMA1_RLC4_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC4_MIDCMD_DATA4
#define SDMA1_RLC4_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
#define SDMA1_RLC4_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC4_MIDCMD_DATA5
#define SDMA1_RLC4_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
#define SDMA1_RLC4_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC4_MIDCMD_DATA6
#define SDMA1_RLC4_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
#define SDMA1_RLC4_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC4_MIDCMD_DATA7
#define SDMA1_RLC4_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
#define SDMA1_RLC4_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC4_MIDCMD_DATA8
#define SDMA1_RLC4_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
#define SDMA1_RLC4_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC4_MIDCMD_DATA9
#define SDMA1_RLC4_MIDCMD_DATA9__DATA9__SHIFT                                                                 0x0
#define SDMA1_RLC4_MIDCMD_DATA9__DATA9_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC4_MIDCMD_DATA10
#define SDMA1_RLC4_MIDCMD_DATA10__DATA10__SHIFT                                                               0x0
#define SDMA1_RLC4_MIDCMD_DATA10__DATA10_MASK                                                                 0xFFFFFFFFL
//SDMA1_RLC4_MIDCMD_CNTL
#define SDMA1_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
#define SDMA1_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
#define SDMA1_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
#define SDMA1_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
#define SDMA1_RLC4_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
#define SDMA1_RLC4_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
#define SDMA1_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
#define SDMA1_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
//SDMA1_RLC5_RB_CNTL
#define SDMA1_RLC5_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
#define SDMA1_RLC5_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
#define SDMA1_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
#define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
#define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
#define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
#define SDMA1_RLC5_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
#define SDMA1_RLC5_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
#define SDMA1_RLC5_RB_CNTL__RPTR_WB_IDLE__SHIFT                                                               0x1f
#define SDMA1_RLC5_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
#define SDMA1_RLC5_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
#define SDMA1_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
#define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
#define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
#define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
#define SDMA1_RLC5_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
#define SDMA1_RLC5_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
#define SDMA1_RLC5_RB_CNTL__RPTR_WB_IDLE_MASK                                                                 0x80000000L
//SDMA1_RLC5_RB_BASE
#define SDMA1_RLC5_RB_BASE__ADDR__SHIFT                                                                       0x0
#define SDMA1_RLC5_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
//SDMA1_RLC5_RB_BASE_HI
#define SDMA1_RLC5_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA1_RLC5_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
//SDMA1_RLC5_RB_RPTR
#define SDMA1_RLC5_RB_RPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA1_RLC5_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA1_RLC5_RB_RPTR_HI
#define SDMA1_RLC5_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA1_RLC5_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA1_RLC5_RB_WPTR
#define SDMA1_RLC5_RB_WPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA1_RLC5_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA1_RLC5_RB_WPTR_HI
#define SDMA1_RLC5_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA1_RLC5_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA1_RLC5_RB_WPTR_POLL_CNTL
#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
//SDMA1_RLC5_RB_RPTR_ADDR_HI
#define SDMA1_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
#define SDMA1_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
//SDMA1_RLC5_RB_RPTR_ADDR_LO
#define SDMA1_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
#define SDMA1_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
//SDMA1_RLC5_IB_CNTL
#define SDMA1_RLC5_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
#define SDMA1_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
#define SDMA1_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
#define SDMA1_RLC5_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
#define SDMA1_RLC5_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
#define SDMA1_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
#define SDMA1_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
#define SDMA1_RLC5_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
//SDMA1_RLC5_IB_RPTR
#define SDMA1_RLC5_IB_RPTR__OFFSET__SHIFT                                                                     0x2
#define SDMA1_RLC5_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
//SDMA1_RLC5_IB_OFFSET
#define SDMA1_RLC5_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
#define SDMA1_RLC5_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
//SDMA1_RLC5_IB_BASE_LO
#define SDMA1_RLC5_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
#define SDMA1_RLC5_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
//SDMA1_RLC5_IB_BASE_HI
#define SDMA1_RLC5_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA1_RLC5_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
//SDMA1_RLC5_IB_SIZE
#define SDMA1_RLC5_IB_SIZE__SIZE__SHIFT                                                                       0x0
#define SDMA1_RLC5_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
//SDMA1_RLC5_SKIP_CNTL
#define SDMA1_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
#define SDMA1_RLC5_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
//SDMA1_RLC5_CONTEXT_STATUS
#define SDMA1_RLC5_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
#define SDMA1_RLC5_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
#define SDMA1_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
#define SDMA1_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
#define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
#define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
#define SDMA1_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
#define SDMA1_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
#define SDMA1_RLC5_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
#define SDMA1_RLC5_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
#define SDMA1_RLC5_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
#define SDMA1_RLC5_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
#define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
#define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
#define SDMA1_RLC5_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
#define SDMA1_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
//SDMA1_RLC5_DOORBELL
#define SDMA1_RLC5_DOORBELL__ENABLE__SHIFT                                                                    0x1c
#define SDMA1_RLC5_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
#define SDMA1_RLC5_DOORBELL__ENABLE_MASK                                                                      0x10000000L
#define SDMA1_RLC5_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
//SDMA1_RLC5_STATUS
#define SDMA1_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
#define SDMA1_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
#define SDMA1_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
#define SDMA1_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
//SDMA1_RLC5_DOORBELL_LOG
#define SDMA1_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
#define SDMA1_RLC5_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
#define SDMA1_RLC5_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
#define SDMA1_RLC5_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
//SDMA1_RLC5_WATERMARK
#define SDMA1_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
#define SDMA1_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
#define SDMA1_RLC5_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
#define SDMA1_RLC5_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
//SDMA1_RLC5_DOORBELL_OFFSET
#define SDMA1_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
#define SDMA1_RLC5_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
//SDMA1_RLC5_CSA_ADDR_LO
#define SDMA1_RLC5_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
#define SDMA1_RLC5_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
//SDMA1_RLC5_CSA_ADDR_HI
#define SDMA1_RLC5_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
#define SDMA1_RLC5_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
//SDMA1_RLC5_IB_SUB_REMAIN
#define SDMA1_RLC5_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
#define SDMA1_RLC5_IB_SUB_REMAIN__SIZE_MASK                                                                   0x00003FFFL
//SDMA1_RLC5_PREEMPT
#define SDMA1_RLC5_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
#define SDMA1_RLC5_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
//SDMA1_RLC5_DUMMY_REG
#define SDMA1_RLC5_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
#define SDMA1_RLC5_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
//SDMA1_RLC5_RB_WPTR_POLL_ADDR_HI
#define SDMA1_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
#define SDMA1_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
//SDMA1_RLC5_RB_WPTR_POLL_ADDR_LO
#define SDMA1_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
#define SDMA1_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
//SDMA1_RLC5_RB_AQL_CNTL
#define SDMA1_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
#define SDMA1_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
#define SDMA1_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
#define SDMA1_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                  0x10
#define SDMA1_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT                                            0x11
#define SDMA1_RLC5_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT                                                         0x12
#define SDMA1_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
#define SDMA1_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
#define SDMA1_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
#define SDMA1_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                    0x00010000L
#define SDMA1_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK                                              0x00020000L
#define SDMA1_RLC5_RB_AQL_CNTL__OVERLAP_ENABLE_MASK                                                           0x00040000L
//SDMA1_RLC5_MINOR_PTR_UPDATE
#define SDMA1_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
#define SDMA1_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
//SDMA1_RLC5_MIDCMD_DATA0
#define SDMA1_RLC5_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
#define SDMA1_RLC5_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC5_MIDCMD_DATA1
#define SDMA1_RLC5_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
#define SDMA1_RLC5_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC5_MIDCMD_DATA2
#define SDMA1_RLC5_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
#define SDMA1_RLC5_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC5_MIDCMD_DATA3
#define SDMA1_RLC5_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
#define SDMA1_RLC5_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC5_MIDCMD_DATA4
#define SDMA1_RLC5_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
#define SDMA1_RLC5_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC5_MIDCMD_DATA5
#define SDMA1_RLC5_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
#define SDMA1_RLC5_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC5_MIDCMD_DATA6
#define SDMA1_RLC5_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
#define SDMA1_RLC5_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC5_MIDCMD_DATA7
#define SDMA1_RLC5_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
#define SDMA1_RLC5_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC5_MIDCMD_DATA8
#define SDMA1_RLC5_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
#define SDMA1_RLC5_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC5_MIDCMD_DATA9
#define SDMA1_RLC5_MIDCMD_DATA9__DATA9__SHIFT                                                                 0x0
#define SDMA1_RLC5_MIDCMD_DATA9__DATA9_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC5_MIDCMD_DATA10
#define SDMA1_RLC5_MIDCMD_DATA10__DATA10__SHIFT                                                               0x0
#define SDMA1_RLC5_MIDCMD_DATA10__DATA10_MASK                                                                 0xFFFFFFFFL
//SDMA1_RLC5_MIDCMD_CNTL
#define SDMA1_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
#define SDMA1_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
#define SDMA1_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
#define SDMA1_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
#define SDMA1_RLC5_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
#define SDMA1_RLC5_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
#define SDMA1_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
#define SDMA1_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
//SDMA1_RLC6_RB_CNTL
#define SDMA1_RLC6_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
#define SDMA1_RLC6_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
#define SDMA1_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
#define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
#define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
#define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
#define SDMA1_RLC6_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
#define SDMA1_RLC6_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
#define SDMA1_RLC6_RB_CNTL__RPTR_WB_IDLE__SHIFT                                                               0x1f
#define SDMA1_RLC6_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
#define SDMA1_RLC6_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
#define SDMA1_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
#define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
#define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
#define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
#define SDMA1_RLC6_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
#define SDMA1_RLC6_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
#define SDMA1_RLC6_RB_CNTL__RPTR_WB_IDLE_MASK                                                                 0x80000000L
//SDMA1_RLC6_RB_BASE
#define SDMA1_RLC6_RB_BASE__ADDR__SHIFT                                                                       0x0
#define SDMA1_RLC6_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
//SDMA1_RLC6_RB_BASE_HI
#define SDMA1_RLC6_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA1_RLC6_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
//SDMA1_RLC6_RB_RPTR
#define SDMA1_RLC6_RB_RPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA1_RLC6_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA1_RLC6_RB_RPTR_HI
#define SDMA1_RLC6_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA1_RLC6_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA1_RLC6_RB_WPTR
#define SDMA1_RLC6_RB_WPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA1_RLC6_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA1_RLC6_RB_WPTR_HI
#define SDMA1_RLC6_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA1_RLC6_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA1_RLC6_RB_WPTR_POLL_CNTL
#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
//SDMA1_RLC6_RB_RPTR_ADDR_HI
#define SDMA1_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
#define SDMA1_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
//SDMA1_RLC6_RB_RPTR_ADDR_LO
#define SDMA1_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
#define SDMA1_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
//SDMA1_RLC6_IB_CNTL
#define SDMA1_RLC6_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
#define SDMA1_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
#define SDMA1_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
#define SDMA1_RLC6_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
#define SDMA1_RLC6_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
#define SDMA1_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
#define SDMA1_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
#define SDMA1_RLC6_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
//SDMA1_RLC6_IB_RPTR
#define SDMA1_RLC6_IB_RPTR__OFFSET__SHIFT                                                                     0x2
#define SDMA1_RLC6_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
//SDMA1_RLC6_IB_OFFSET
#define SDMA1_RLC6_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
#define SDMA1_RLC6_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
//SDMA1_RLC6_IB_BASE_LO
#define SDMA1_RLC6_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
#define SDMA1_RLC6_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
//SDMA1_RLC6_IB_BASE_HI
#define SDMA1_RLC6_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA1_RLC6_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
//SDMA1_RLC6_IB_SIZE
#define SDMA1_RLC6_IB_SIZE__SIZE__SHIFT                                                                       0x0
#define SDMA1_RLC6_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
//SDMA1_RLC6_SKIP_CNTL
#define SDMA1_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
#define SDMA1_RLC6_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
//SDMA1_RLC6_CONTEXT_STATUS
#define SDMA1_RLC6_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
#define SDMA1_RLC6_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
#define SDMA1_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
#define SDMA1_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
#define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
#define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
#define SDMA1_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
#define SDMA1_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
#define SDMA1_RLC6_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
#define SDMA1_RLC6_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
#define SDMA1_RLC6_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
#define SDMA1_RLC6_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
#define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
#define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
#define SDMA1_RLC6_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
#define SDMA1_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
//SDMA1_RLC6_DOORBELL
#define SDMA1_RLC6_DOORBELL__ENABLE__SHIFT                                                                    0x1c
#define SDMA1_RLC6_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
#define SDMA1_RLC6_DOORBELL__ENABLE_MASK                                                                      0x10000000L
#define SDMA1_RLC6_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
//SDMA1_RLC6_STATUS
#define SDMA1_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
#define SDMA1_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
#define SDMA1_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
#define SDMA1_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
//SDMA1_RLC6_DOORBELL_LOG
#define SDMA1_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
#define SDMA1_RLC6_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
#define SDMA1_RLC6_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
#define SDMA1_RLC6_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
//SDMA1_RLC6_WATERMARK
#define SDMA1_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
#define SDMA1_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
#define SDMA1_RLC6_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
#define SDMA1_RLC6_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
//SDMA1_RLC6_DOORBELL_OFFSET
#define SDMA1_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
#define SDMA1_RLC6_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
//SDMA1_RLC6_CSA_ADDR_LO
#define SDMA1_RLC6_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
#define SDMA1_RLC6_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
//SDMA1_RLC6_CSA_ADDR_HI
#define SDMA1_RLC6_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
#define SDMA1_RLC6_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
//SDMA1_RLC6_IB_SUB_REMAIN
#define SDMA1_RLC6_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
#define SDMA1_RLC6_IB_SUB_REMAIN__SIZE_MASK                                                                   0x00003FFFL
//SDMA1_RLC6_PREEMPT
#define SDMA1_RLC6_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
#define SDMA1_RLC6_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
//SDMA1_RLC6_DUMMY_REG
#define SDMA1_RLC6_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
#define SDMA1_RLC6_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
//SDMA1_RLC6_RB_WPTR_POLL_ADDR_HI
#define SDMA1_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
#define SDMA1_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
//SDMA1_RLC6_RB_WPTR_POLL_ADDR_LO
#define SDMA1_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
#define SDMA1_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
//SDMA1_RLC6_RB_AQL_CNTL
#define SDMA1_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
#define SDMA1_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
#define SDMA1_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
#define SDMA1_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                  0x10
#define SDMA1_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT                                            0x11
#define SDMA1_RLC6_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT                                                         0x12
#define SDMA1_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
#define SDMA1_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
#define SDMA1_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
#define SDMA1_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                    0x00010000L
#define SDMA1_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK                                              0x00020000L
#define SDMA1_RLC6_RB_AQL_CNTL__OVERLAP_ENABLE_MASK                                                           0x00040000L
//SDMA1_RLC6_MINOR_PTR_UPDATE
#define SDMA1_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
#define SDMA1_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
//SDMA1_RLC6_MIDCMD_DATA0
#define SDMA1_RLC6_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
#define SDMA1_RLC6_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC6_MIDCMD_DATA1
#define SDMA1_RLC6_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
#define SDMA1_RLC6_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC6_MIDCMD_DATA2
#define SDMA1_RLC6_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
#define SDMA1_RLC6_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC6_MIDCMD_DATA3
#define SDMA1_RLC6_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
#define SDMA1_RLC6_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC6_MIDCMD_DATA4
#define SDMA1_RLC6_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
#define SDMA1_RLC6_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC6_MIDCMD_DATA5
#define SDMA1_RLC6_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
#define SDMA1_RLC6_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC6_MIDCMD_DATA6
#define SDMA1_RLC6_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
#define SDMA1_RLC6_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC6_MIDCMD_DATA7
#define SDMA1_RLC6_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
#define SDMA1_RLC6_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC6_MIDCMD_DATA8
#define SDMA1_RLC6_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
#define SDMA1_RLC6_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC6_MIDCMD_DATA9
#define SDMA1_RLC6_MIDCMD_DATA9__DATA9__SHIFT                                                                 0x0
#define SDMA1_RLC6_MIDCMD_DATA9__DATA9_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC6_MIDCMD_DATA10
#define SDMA1_RLC6_MIDCMD_DATA10__DATA10__SHIFT                                                               0x0
#define SDMA1_RLC6_MIDCMD_DATA10__DATA10_MASK                                                                 0xFFFFFFFFL
//SDMA1_RLC6_MIDCMD_CNTL
#define SDMA1_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
#define SDMA1_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
#define SDMA1_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
#define SDMA1_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
#define SDMA1_RLC6_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
#define SDMA1_RLC6_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
#define SDMA1_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
#define SDMA1_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
//SDMA1_RLC7_RB_CNTL
#define SDMA1_RLC7_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
#define SDMA1_RLC7_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
#define SDMA1_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
#define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
#define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
#define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
#define SDMA1_RLC7_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
#define SDMA1_RLC7_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
#define SDMA1_RLC7_RB_CNTL__RPTR_WB_IDLE__SHIFT                                                               0x1f
#define SDMA1_RLC7_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
#define SDMA1_RLC7_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
#define SDMA1_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
#define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
#define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
#define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
#define SDMA1_RLC7_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
#define SDMA1_RLC7_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
#define SDMA1_RLC7_RB_CNTL__RPTR_WB_IDLE_MASK                                                                 0x80000000L
//SDMA1_RLC7_RB_BASE
#define SDMA1_RLC7_RB_BASE__ADDR__SHIFT                                                                       0x0
#define SDMA1_RLC7_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
//SDMA1_RLC7_RB_BASE_HI
#define SDMA1_RLC7_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA1_RLC7_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
//SDMA1_RLC7_RB_RPTR
#define SDMA1_RLC7_RB_RPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA1_RLC7_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA1_RLC7_RB_RPTR_HI
#define SDMA1_RLC7_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA1_RLC7_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA1_RLC7_RB_WPTR
#define SDMA1_RLC7_RB_WPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA1_RLC7_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA1_RLC7_RB_WPTR_HI
#define SDMA1_RLC7_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA1_RLC7_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA1_RLC7_RB_WPTR_POLL_CNTL
#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
//SDMA1_RLC7_RB_RPTR_ADDR_HI
#define SDMA1_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
#define SDMA1_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
//SDMA1_RLC7_RB_RPTR_ADDR_LO
#define SDMA1_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
#define SDMA1_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
//SDMA1_RLC7_IB_CNTL
#define SDMA1_RLC7_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
#define SDMA1_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
#define SDMA1_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
#define SDMA1_RLC7_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
#define SDMA1_RLC7_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
#define SDMA1_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
#define SDMA1_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
#define SDMA1_RLC7_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
//SDMA1_RLC7_IB_RPTR
#define SDMA1_RLC7_IB_RPTR__OFFSET__SHIFT                                                                     0x2
#define SDMA1_RLC7_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
//SDMA1_RLC7_IB_OFFSET
#define SDMA1_RLC7_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
#define SDMA1_RLC7_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
//SDMA1_RLC7_IB_BASE_LO
#define SDMA1_RLC7_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
#define SDMA1_RLC7_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
//SDMA1_RLC7_IB_BASE_HI
#define SDMA1_RLC7_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA1_RLC7_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
//SDMA1_RLC7_IB_SIZE
#define SDMA1_RLC7_IB_SIZE__SIZE__SHIFT                                                                       0x0
#define SDMA1_RLC7_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
//SDMA1_RLC7_SKIP_CNTL
#define SDMA1_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
#define SDMA1_RLC7_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
//SDMA1_RLC7_CONTEXT_STATUS
#define SDMA1_RLC7_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
#define SDMA1_RLC7_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
#define SDMA1_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
#define SDMA1_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
#define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
#define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
#define SDMA1_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
#define SDMA1_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
#define SDMA1_RLC7_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
#define SDMA1_RLC7_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
#define SDMA1_RLC7_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
#define SDMA1_RLC7_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
#define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
#define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
#define SDMA1_RLC7_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
#define SDMA1_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
//SDMA1_RLC7_DOORBELL
#define SDMA1_RLC7_DOORBELL__ENABLE__SHIFT                                                                    0x1c
#define SDMA1_RLC7_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
#define SDMA1_RLC7_DOORBELL__ENABLE_MASK                                                                      0x10000000L
#define SDMA1_RLC7_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
//SDMA1_RLC7_STATUS
#define SDMA1_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
#define SDMA1_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
#define SDMA1_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
#define SDMA1_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
//SDMA1_RLC7_DOORBELL_LOG
#define SDMA1_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
#define SDMA1_RLC7_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
#define SDMA1_RLC7_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
#define SDMA1_RLC7_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
//SDMA1_RLC7_WATERMARK
#define SDMA1_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
#define SDMA1_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
#define SDMA1_RLC7_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
#define SDMA1_RLC7_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
//SDMA1_RLC7_DOORBELL_OFFSET
#define SDMA1_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
#define SDMA1_RLC7_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
//SDMA1_RLC7_CSA_ADDR_LO
#define SDMA1_RLC7_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
#define SDMA1_RLC7_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
//SDMA1_RLC7_CSA_ADDR_HI
#define SDMA1_RLC7_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
#define SDMA1_RLC7_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
//SDMA1_RLC7_IB_SUB_REMAIN
#define SDMA1_RLC7_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
#define SDMA1_RLC7_IB_SUB_REMAIN__SIZE_MASK                                                                   0x00003FFFL
//SDMA1_RLC7_PREEMPT
#define SDMA1_RLC7_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
#define SDMA1_RLC7_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
//SDMA1_RLC7_DUMMY_REG
#define SDMA1_RLC7_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
#define SDMA1_RLC7_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
//SDMA1_RLC7_RB_WPTR_POLL_ADDR_HI
#define SDMA1_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
#define SDMA1_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
//SDMA1_RLC7_RB_WPTR_POLL_ADDR_LO
#define SDMA1_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
#define SDMA1_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
//SDMA1_RLC7_RB_AQL_CNTL
#define SDMA1_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
#define SDMA1_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
#define SDMA1_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
#define SDMA1_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                  0x10
#define SDMA1_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT                                            0x11
#define SDMA1_RLC7_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT                                                         0x12
#define SDMA1_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
#define SDMA1_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
#define SDMA1_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
#define SDMA1_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                    0x00010000L
#define SDMA1_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK                                              0x00020000L
#define SDMA1_RLC7_RB_AQL_CNTL__OVERLAP_ENABLE_MASK                                                           0x00040000L
//SDMA1_RLC7_MINOR_PTR_UPDATE
#define SDMA1_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
#define SDMA1_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
//SDMA1_RLC7_MIDCMD_DATA0
#define SDMA1_RLC7_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
#define SDMA1_RLC7_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC7_MIDCMD_DATA1
#define SDMA1_RLC7_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
#define SDMA1_RLC7_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC7_MIDCMD_DATA2
#define SDMA1_RLC7_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
#define SDMA1_RLC7_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC7_MIDCMD_DATA3
#define SDMA1_RLC7_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
#define SDMA1_RLC7_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC7_MIDCMD_DATA4
#define SDMA1_RLC7_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
#define SDMA1_RLC7_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC7_MIDCMD_DATA5
#define SDMA1_RLC7_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
#define SDMA1_RLC7_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC7_MIDCMD_DATA6
#define SDMA1_RLC7_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
#define SDMA1_RLC7_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC7_MIDCMD_DATA7
#define SDMA1_RLC7_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
#define SDMA1_RLC7_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC7_MIDCMD_DATA8
#define SDMA1_RLC7_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
#define SDMA1_RLC7_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC7_MIDCMD_DATA9
#define SDMA1_RLC7_MIDCMD_DATA9__DATA9__SHIFT                                                                 0x0
#define SDMA1_RLC7_MIDCMD_DATA9__DATA9_MASK                                                                   0xFFFFFFFFL
//SDMA1_RLC7_MIDCMD_DATA10
#define SDMA1_RLC7_MIDCMD_DATA10__DATA10__SHIFT                                                               0x0
#define SDMA1_RLC7_MIDCMD_DATA10__DATA10_MASK                                                                 0xFFFFFFFFL
//SDMA1_RLC7_MIDCMD_CNTL
#define SDMA1_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
#define SDMA1_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
#define SDMA1_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
#define SDMA1_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
#define SDMA1_RLC7_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
#define SDMA1_RLC7_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
#define SDMA1_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
#define SDMA1_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L


// addressBlock: gc_grbmdec
//GRBM_CNTL
#define GRBM_CNTL__READ_TIMEOUT__SHIFT                                                                        0x0
#define GRBM_CNTL__REPORT_LAST_RDERR__SHIFT                                                                   0x1f
#define GRBM_CNTL__READ_TIMEOUT_MASK                                                                          0x000000FFL
#define GRBM_CNTL__REPORT_LAST_RDERR_MASK                                                                     0x80000000L
//GRBM_SKEW_CNTL
#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT                                                             0x0
#define GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT                                                                     0x6
#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK                                                               0x0000003FL
#define GRBM_SKEW_CNTL__SKEW_COUNT_MASK                                                                       0x00000FC0L
//GRBM_STATUS2
#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT                                                           0x0
#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT                                                           0x4
#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT                                                           0x5
#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT                                                              0x6
#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT                                                              0x7
#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT                                                              0x8
#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT                                                              0x9
#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT                                                              0xa
#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING__SHIFT                                                              0xb
#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING__SHIFT                                                              0xc
#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING__SHIFT                                                              0xd
#define GRBM_STATUS2__RLC_RQ_PENDING__SHIFT                                                                   0xe
#define GRBM_STATUS2__UTCL2_BUSY__SHIFT                                                                       0xf
#define GRBM_STATUS2__EA_BUSY__SHIFT                                                                          0x10
#define GRBM_STATUS2__RMI_BUSY__SHIFT                                                                         0x11
#define GRBM_STATUS2__UTCL2_RQ_PENDING__SHIFT                                                                 0x12
#define GRBM_STATUS2__SDMA_SCH_RQ_PENDING__SHIFT                                                              0x13
#define GRBM_STATUS2__EA_LINK_BUSY__SHIFT                                                                     0x14
#define GRBM_STATUS2__SDMA_BUSY__SHIFT                                                                        0x15
#define GRBM_STATUS2__SDMA0_RQ_PENDING__SHIFT                                                                 0x16
#define GRBM_STATUS2__SDMA1_RQ_PENDING__SHIFT                                                                 0x17
#define GRBM_STATUS2__SDMA2_RQ_PENDING__SHIFT                                                                 0x18
#define GRBM_STATUS2__SDMA3_RQ_PENDING__SHIFT                                                                 0x19
#define GRBM_STATUS2__RLC_BUSY__SHIFT                                                                         0x1a
#define GRBM_STATUS2__TCP_BUSY__SHIFT                                                                         0x1b
#define GRBM_STATUS2__CPF_BUSY__SHIFT                                                                         0x1c
#define GRBM_STATUS2__CPC_BUSY__SHIFT                                                                         0x1d
#define GRBM_STATUS2__CPG_BUSY__SHIFT                                                                         0x1e
#define GRBM_STATUS2__CPAXI_BUSY__SHIFT                                                                       0x1f
#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK                                                             0x0000000FL
#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK                                                             0x00000010L
#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK                                                             0x00000020L
#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK                                                                0x00000040L
#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK                                                                0x00000080L
#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK                                                                0x00000100L
#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK                                                                0x00000200L
#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING_MASK                                                                0x00000400L
#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING_MASK                                                                0x00000800L
#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING_MASK                                                                0x00001000L
#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING_MASK                                                                0x00002000L
#define GRBM_STATUS2__RLC_RQ_PENDING_MASK                                                                     0x00004000L
#define GRBM_STATUS2__UTCL2_BUSY_MASK                                                                         0x00008000L
#define GRBM_STATUS2__EA_BUSY_MASK                                                                            0x00010000L
#define GRBM_STATUS2__RMI_BUSY_MASK                                                                           0x00020000L
#define GRBM_STATUS2__UTCL2_RQ_PENDING_MASK                                                                   0x00040000L
#define GRBM_STATUS2__SDMA_SCH_RQ_PENDING_MASK                                                                0x00080000L
#define GRBM_STATUS2__EA_LINK_BUSY_MASK                                                                       0x00100000L
#define GRBM_STATUS2__SDMA_BUSY_MASK                                                                          0x00200000L
#define GRBM_STATUS2__SDMA0_RQ_PENDING_MASK                                                                   0x00400000L
#define GRBM_STATUS2__SDMA1_RQ_PENDING_MASK                                                                   0x00800000L
#define GRBM_STATUS2__SDMA2_RQ_PENDING_MASK                                                                   0x01000000L
#define GRBM_STATUS2__SDMA3_RQ_PENDING_MASK                                                                   0x02000000L
#define GRBM_STATUS2__RLC_BUSY_MASK                                                                           0x04000000L
#define GRBM_STATUS2__TCP_BUSY_MASK                                                                           0x08000000L
#define GRBM_STATUS2__CPF_BUSY_MASK                                                                           0x10000000L
#define GRBM_STATUS2__CPC_BUSY_MASK                                                                           0x20000000L
#define GRBM_STATUS2__CPG_BUSY_MASK                                                                           0x40000000L
#define GRBM_STATUS2__CPAXI_BUSY_MASK                                                                         0x80000000L
//GRBM_PWR_CNTL
#define GRBM_PWR_CNTL__ALL_REQ_TYPE__SHIFT                                                                    0x0
#define GRBM_PWR_CNTL__GFX_REQ_TYPE__SHIFT                                                                    0x2
#define GRBM_PWR_CNTL__ALL_RSP_TYPE__SHIFT                                                                    0x4
#define GRBM_PWR_CNTL__GFX_RSP_TYPE__SHIFT                                                                    0x6
#define GRBM_PWR_CNTL__GFX_REQ_EN__SHIFT                                                                      0xe
#define GRBM_PWR_CNTL__ALL_REQ_EN__SHIFT                                                                      0xf
#define GRBM_PWR_CNTL__ALL_REQ_TYPE_MASK                                                                      0x00000003L
#define GRBM_PWR_CNTL__GFX_REQ_TYPE_MASK                                                                      0x0000000CL
#define GRBM_PWR_CNTL__ALL_RSP_TYPE_MASK                                                                      0x00000030L
#define GRBM_PWR_CNTL__GFX_RSP_TYPE_MASK                                                                      0x000000C0L
#define GRBM_PWR_CNTL__GFX_REQ_EN_MASK                                                                        0x00004000L
#define GRBM_PWR_CNTL__ALL_REQ_EN_MASK                                                                        0x00008000L
//GRBM_STATUS
#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT                                                            0x0
#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT                                                            0x7
#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT                                                            0x8
#define GRBM_STATUS__GDS_DMA_RQ_PENDING__SHIFT                                                                0x9
#define GRBM_STATUS__DB_CLEAN__SHIFT                                                                          0xc
#define GRBM_STATUS__CB_CLEAN__SHIFT                                                                          0xd
#define GRBM_STATUS__TA_BUSY__SHIFT                                                                           0xe
#define GRBM_STATUS__GDS_BUSY__SHIFT                                                                          0xf
#define GRBM_STATUS__GE_BUSY_NO_DMA__SHIFT                                                                    0x10
#define GRBM_STATUS__SX_BUSY__SHIFT                                                                           0x14
#define GRBM_STATUS__GE_BUSY__SHIFT                                                                           0x15
#define GRBM_STATUS__SPI_BUSY__SHIFT                                                                          0x16
#define GRBM_STATUS__BCI_BUSY__SHIFT                                                                          0x17
#define GRBM_STATUS__SC_BUSY__SHIFT                                                                           0x18
#define GRBM_STATUS__PA_BUSY__SHIFT                                                                           0x19
#define GRBM_STATUS__DB_BUSY__SHIFT                                                                           0x1a
#define GRBM_STATUS__CP_COHERENCY_BUSY__SHIFT                                                                 0x1c
#define GRBM_STATUS__CP_BUSY__SHIFT                                                                           0x1d
#define GRBM_STATUS__CB_BUSY__SHIFT                                                                           0x1e
#define GRBM_STATUS__GUI_ACTIVE__SHIFT                                                                        0x1f
#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK                                                              0x0000000FL
#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK                                                              0x00000080L
#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK                                                              0x00000100L
#define GRBM_STATUS__GDS_DMA_RQ_PENDING_MASK                                                                  0x00000200L
#define GRBM_STATUS__DB_CLEAN_MASK                                                                            0x00001000L
#define GRBM_STATUS__CB_CLEAN_MASK                                                                            0x00002000L
#define GRBM_STATUS__TA_BUSY_MASK                                                                             0x00004000L
#define GRBM_STATUS__GDS_BUSY_MASK                                                                            0x00008000L
#define GRBM_STATUS__GE_BUSY_NO_DMA_MASK                                                                      0x00010000L
#define GRBM_STATUS__SX_BUSY_MASK                                                                             0x00100000L
#define GRBM_STATUS__GE_BUSY_MASK                                                                             0x00200000L
#define GRBM_STATUS__SPI_BUSY_MASK                                                                            0x00400000L
#define GRBM_STATUS__BCI_BUSY_MASK                                                                            0x00800000L
#define GRBM_STATUS__SC_BUSY_MASK                                                                             0x01000000L
#define GRBM_STATUS__PA_BUSY_MASK                                                                             0x02000000L
#define GRBM_STATUS__DB_BUSY_MASK                                                                             0x04000000L
#define GRBM_STATUS__CP_COHERENCY_BUSY_MASK                                                                   0x10000000L
#define GRBM_STATUS__CP_BUSY_MASK                                                                             0x20000000L
#define GRBM_STATUS__CB_BUSY_MASK                                                                             0x40000000L
#define GRBM_STATUS__GUI_ACTIVE_MASK                                                                          0x80000000L
//GRBM_STATUS_SE0
#define GRBM_STATUS_SE0__DB_CLEAN__SHIFT                                                                      0x1
#define GRBM_STATUS_SE0__CB_CLEAN__SHIFT                                                                      0x2
#define GRBM_STATUS_SE0__UTCL1_BUSY__SHIFT                                                                    0x3
#define GRBM_STATUS_SE0__TCP_BUSY__SHIFT                                                                      0x4
#define GRBM_STATUS_SE0__GL1CC_BUSY__SHIFT                                                                    0x5
#define GRBM_STATUS_SE0__RMI_BUSY__SHIFT                                                                      0x15
#define GRBM_STATUS_SE0__BCI_BUSY__SHIFT                                                                      0x16
#define GRBM_STATUS_SE0__PA_BUSY__SHIFT                                                                       0x18
#define GRBM_STATUS_SE0__TA_BUSY__SHIFT                                                                       0x19
#define GRBM_STATUS_SE0__SX_BUSY__SHIFT                                                                       0x1a
#define GRBM_STATUS_SE0__SPI_BUSY__SHIFT                                                                      0x1b
#define GRBM_STATUS_SE0__SC_BUSY__SHIFT                                                                       0x1d
#define GRBM_STATUS_SE0__DB_BUSY__SHIFT                                                                       0x1e
#define GRBM_STATUS_SE0__CB_BUSY__SHIFT                                                                       0x1f
#define GRBM_STATUS_SE0__DB_CLEAN_MASK                                                                        0x00000002L
#define GRBM_STATUS_SE0__CB_CLEAN_MASK                                                                        0x00000004L
#define GRBM_STATUS_SE0__UTCL1_BUSY_MASK                                                                      0x00000008L
#define GRBM_STATUS_SE0__TCP_BUSY_MASK                                                                        0x00000010L
#define GRBM_STATUS_SE0__GL1CC_BUSY_MASK                                                                      0x00000020L
#define GRBM_STATUS_SE0__RMI_BUSY_MASK                                                                        0x00200000L
#define GRBM_STATUS_SE0__BCI_BUSY_MASK                                                                        0x00400000L
#define GRBM_STATUS_SE0__PA_BUSY_MASK                                                                         0x01000000L
#define GRBM_STATUS_SE0__TA_BUSY_MASK                                                                         0x02000000L
#define GRBM_STATUS_SE0__SX_BUSY_MASK                                                                         0x04000000L
#define GRBM_STATUS_SE0__SPI_BUSY_MASK                                                                        0x08000000L
#define GRBM_STATUS_SE0__SC_BUSY_MASK                                                                         0x20000000L
#define GRBM_STATUS_SE0__DB_BUSY_MASK                                                                         0x40000000L
#define GRBM_STATUS_SE0__CB_BUSY_MASK                                                                         0x80000000L
//GRBM_STATUS_SE1
#define GRBM_STATUS_SE1__DB_CLEAN__SHIFT                                                                      0x1
#define GRBM_STATUS_SE1__CB_CLEAN__SHIFT                                                                      0x2
#define GRBM_STATUS_SE1__UTCL1_BUSY__SHIFT                                                                    0x3
#define GRBM_STATUS_SE1__TCP_BUSY__SHIFT                                                                      0x4
#define GRBM_STATUS_SE1__GL1CC_BUSY__SHIFT                                                                    0x5
#define GRBM_STATUS_SE1__RMI_BUSY__SHIFT                                                                      0x15
#define GRBM_STATUS_SE1__BCI_BUSY__SHIFT                                                                      0x16
#define GRBM_STATUS_SE1__PA_BUSY__SHIFT                                                                       0x18
#define GRBM_STATUS_SE1__TA_BUSY__SHIFT                                                                       0x19
#define GRBM_STATUS_SE1__SX_BUSY__SHIFT                                                                       0x1a
#define GRBM_STATUS_SE1__SPI_BUSY__SHIFT                                                                      0x1b
#define GRBM_STATUS_SE1__SC_BUSY__SHIFT                                                                       0x1d
#define GRBM_STATUS_SE1__DB_BUSY__SHIFT                                                                       0x1e
#define GRBM_STATUS_SE1__CB_BUSY__SHIFT                                                                       0x1f
#define GRBM_STATUS_SE1__DB_CLEAN_MASK                                                                        0x00000002L
#define GRBM_STATUS_SE1__CB_CLEAN_MASK                                                                        0x00000004L
#define GRBM_STATUS_SE1__UTCL1_BUSY_MASK                                                                      0x00000008L
#define GRBM_STATUS_SE1__TCP_BUSY_MASK                                                                        0x00000010L
#define GRBM_STATUS_SE1__GL1CC_BUSY_MASK                                                                      0x00000020L
#define GRBM_STATUS_SE1__RMI_BUSY_MASK                                                                        0x00200000L
#define GRBM_STATUS_SE1__BCI_BUSY_MASK                                                                        0x00400000L
#define GRBM_STATUS_SE1__PA_BUSY_MASK                                                                         0x01000000L
#define GRBM_STATUS_SE1__TA_BUSY_MASK                                                                         0x02000000L
#define GRBM_STATUS_SE1__SX_BUSY_MASK                                                                         0x04000000L
#define GRBM_STATUS_SE1__SPI_BUSY_MASK                                                                        0x08000000L
#define GRBM_STATUS_SE1__SC_BUSY_MASK                                                                         0x20000000L
#define GRBM_STATUS_SE1__DB_BUSY_MASK                                                                         0x40000000L
#define GRBM_STATUS_SE1__CB_BUSY_MASK                                                                         0x80000000L
//GRBM_STATUS3
#define GRBM_STATUS3__GRBM_RLC_INTR_CREDIT_PENDING__SHIFT                                                     0x5
#define GRBM_STATUS3__GRBM_UTCL2_INTR_CREDIT_PENDING__SHIFT                                                   0x6
#define GRBM_STATUS3__GRBM_CPF_INTR_CREDIT_PENDING__SHIFT                                                     0x7
#define GRBM_STATUS3__MESPIPE0_RQ_PENDING__SHIFT                                                              0x8
#define GRBM_STATUS3__MESPIPE1_RQ_PENDING__SHIFT                                                              0x9
#define GRBM_STATUS3__MESPIPE2_RQ_PENDING__SHIFT                                                              0xa
#define GRBM_STATUS3__MESPIPE3_RQ_PENDING__SHIFT                                                              0xb
#define GRBM_STATUS3__PH_BUSY__SHIFT                                                                          0xd
#define GRBM_STATUS3__CH_BUSY__SHIFT                                                                          0xe
#define GRBM_STATUS3__GL2CC_BUSY__SHIFT                                                                       0xf
#define GRBM_STATUS3__GL1CC_BUSY__SHIFT                                                                       0x10
#define GRBM_STATUS3__GUS_LINK_BUSY__SHIFT                                                                    0x1c
#define GRBM_STATUS3__GUS_BUSY__SHIFT                                                                         0x1d
#define GRBM_STATUS3__UTCL1_BUSY__SHIFT                                                                       0x1e
#define GRBM_STATUS3__PMM_BUSY__SHIFT                                                                         0x1f
#define GRBM_STATUS3__GRBM_RLC_INTR_CREDIT_PENDING_MASK                                                       0x00000020L
#define GRBM_STATUS3__GRBM_UTCL2_INTR_CREDIT_PENDING_MASK                                                     0x00000040L
#define GRBM_STATUS3__GRBM_CPF_INTR_CREDIT_PENDING_MASK                                                       0x00000080L
#define GRBM_STATUS3__MESPIPE0_RQ_PENDING_MASK                                                                0x00000100L
#define GRBM_STATUS3__MESPIPE1_RQ_PENDING_MASK                                                                0x00000200L
#define GRBM_STATUS3__MESPIPE2_RQ_PENDING_MASK                                                                0x00000400L
#define GRBM_STATUS3__MESPIPE3_RQ_PENDING_MASK                                                                0x00000800L
#define GRBM_STATUS3__PH_BUSY_MASK                                                                            0x00002000L
#define GRBM_STATUS3__CH_BUSY_MASK                                                                            0x00004000L
#define GRBM_STATUS3__GL2CC_BUSY_MASK                                                                         0x00008000L
#define GRBM_STATUS3__GL1CC_BUSY_MASK                                                                         0x00010000L
#define GRBM_STATUS3__GUS_LINK_BUSY_MASK                                                                      0x10000000L
#define GRBM_STATUS3__GUS_BUSY_MASK                                                                           0x20000000L
#define GRBM_STATUS3__UTCL1_BUSY_MASK                                                                         0x40000000L
#define GRBM_STATUS3__PMM_BUSY_MASK                                                                           0x80000000L
//GRBM_SOFT_RESET
#define GRBM_SOFT_RESET__SOFT_RESET_CP__SHIFT                                                                 0x0
#define GRBM_SOFT_RESET__SOFT_RESET_RLC__SHIFT                                                                0x2
#define GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT                                                                0x10
#define GRBM_SOFT_RESET__SOFT_RESET_CPF__SHIFT                                                                0x11
#define GRBM_SOFT_RESET__SOFT_RESET_CPC__SHIFT                                                                0x12
#define GRBM_SOFT_RESET__SOFT_RESET_CPG__SHIFT                                                                0x13
#define GRBM_SOFT_RESET__SOFT_RESET_CAC__SHIFT                                                                0x14
#define GRBM_SOFT_RESET__SOFT_RESET_CPAXI__SHIFT                                                              0x15
#define GRBM_SOFT_RESET__SOFT_RESET_EA__SHIFT                                                                 0x16
#define GRBM_SOFT_RESET__SOFT_RESET_SDMA0__SHIFT                                                              0x17
#define GRBM_SOFT_RESET__SOFT_RESET_SDMA1__SHIFT                                                              0x18
#define GRBM_SOFT_RESET__SOFT_RESET_SDMA2__SHIFT                                                              0x19
#define GRBM_SOFT_RESET__SOFT_RESET_SDMA3__SHIFT                                                              0x1a
#define GRBM_SOFT_RESET__SOFT_RESET_CP_MASK                                                                   0x00000001L
#define GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK                                                                  0x00000004L
#define GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK                                                                  0x00010000L
#define GRBM_SOFT_RESET__SOFT_RESET_CPF_MASK                                                                  0x00020000L
#define GRBM_SOFT_RESET__SOFT_RESET_CPC_MASK                                                                  0x00040000L
#define GRBM_SOFT_RESET__SOFT_RESET_CPG_MASK                                                                  0x00080000L
#define GRBM_SOFT_RESET__SOFT_RESET_CAC_MASK                                                                  0x00100000L
#define GRBM_SOFT_RESET__SOFT_RESET_CPAXI_MASK                                                                0x00200000L
#define GRBM_SOFT_RESET__SOFT_RESET_EA_MASK                                                                   0x00400000L
#define GRBM_SOFT_RESET__SOFT_RESET_SDMA0_MASK                                                                0x00800000L
#define GRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK                                                                0x01000000L
#define GRBM_SOFT_RESET__SOFT_RESET_SDMA2_MASK                                                                0x02000000L
#define GRBM_SOFT_RESET__SOFT_RESET_SDMA3_MASK                                                                0x04000000L
//GRBM_GFX_CLKEN_CNTL
#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT                                                          0x0
#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT                                                            0x8
#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK                                                            0x0000000FL
#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK                                                              0x00001F00L
//GRBM_WAIT_IDLE_CLOCKS
#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS__SHIFT                                                        0x0
#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_MASK                                                          0x000000FFL
//GRBM_STATUS_SE2
#define GRBM_STATUS_SE2__DB_CLEAN__SHIFT                                                                      0x1
#define GRBM_STATUS_SE2__CB_CLEAN__SHIFT                                                                      0x2
#define GRBM_STATUS_SE2__UTCL1_BUSY__SHIFT                                                                    0x3
#define GRBM_STATUS_SE2__TCP_BUSY__SHIFT                                                                      0x4
#define GRBM_STATUS_SE2__GL1CC_BUSY__SHIFT                                                                    0x5
#define GRBM_STATUS_SE2__RMI_BUSY__SHIFT                                                                      0x15
#define GRBM_STATUS_SE2__BCI_BUSY__SHIFT                                                                      0x16
#define GRBM_STATUS_SE2__PA_BUSY__SHIFT                                                                       0x18
#define GRBM_STATUS_SE2__TA_BUSY__SHIFT                                                                       0x19
#define GRBM_STATUS_SE2__SX_BUSY__SHIFT                                                                       0x1a
#define GRBM_STATUS_SE2__SPI_BUSY__SHIFT                                                                      0x1b
#define GRBM_STATUS_SE2__SC_BUSY__SHIFT                                                                       0x1d
#define GRBM_STATUS_SE2__DB_BUSY__SHIFT                                                                       0x1e
#define GRBM_STATUS_SE2__CB_BUSY__SHIFT                                                                       0x1f
#define GRBM_STATUS_SE2__DB_CLEAN_MASK                                                                        0x00000002L
#define GRBM_STATUS_SE2__CB_CLEAN_MASK                                                                        0x00000004L
#define GRBM_STATUS_SE2__UTCL1_BUSY_MASK                                                                      0x00000008L
#define GRBM_STATUS_SE2__TCP_BUSY_MASK                                                                        0x00000010L
#define GRBM_STATUS_SE2__GL1CC_BUSY_MASK                                                                      0x00000020L
#define GRBM_STATUS_SE2__RMI_BUSY_MASK                                                                        0x00200000L
#define GRBM_STATUS_SE2__BCI_BUSY_MASK                                                                        0x00400000L
#define GRBM_STATUS_SE2__PA_BUSY_MASK                                                                         0x01000000L
#define GRBM_STATUS_SE2__TA_BUSY_MASK                                                                         0x02000000L
#define GRBM_STATUS_SE2__SX_BUSY_MASK                                                                         0x04000000L
#define GRBM_STATUS_SE2__SPI_BUSY_MASK                                                                        0x08000000L
#define GRBM_STATUS_SE2__SC_BUSY_MASK                                                                         0x20000000L
#define GRBM_STATUS_SE2__DB_BUSY_MASK                                                                         0x40000000L
#define GRBM_STATUS_SE2__CB_BUSY_MASK                                                                         0x80000000L
//GRBM_STATUS_SE3
#define GRBM_STATUS_SE3__DB_CLEAN__SHIFT                                                                      0x1
#define GRBM_STATUS_SE3__CB_CLEAN__SHIFT                                                                      0x2
#define GRBM_STATUS_SE3__UTCL1_BUSY__SHIFT                                                                    0x3
#define GRBM_STATUS_SE3__TCP_BUSY__SHIFT                                                                      0x4
#define GRBM_STATUS_SE3__GL1CC_BUSY__SHIFT                                                                    0x5
#define GRBM_STATUS_SE3__RMI_BUSY__SHIFT                                                                      0x15
#define GRBM_STATUS_SE3__BCI_BUSY__SHIFT                                                                      0x16
#define GRBM_STATUS_SE3__PA_BUSY__SHIFT                                                                       0x18
#define GRBM_STATUS_SE3__TA_BUSY__SHIFT                                                                       0x19
#define GRBM_STATUS_SE3__SX_BUSY__SHIFT                                                                       0x1a
#define GRBM_STATUS_SE3__SPI_BUSY__SHIFT                                                                      0x1b
#define GRBM_STATUS_SE3__SC_BUSY__SHIFT                                                                       0x1d
#define GRBM_STATUS_SE3__DB_BUSY__SHIFT                                                                       0x1e
#define GRBM_STATUS_SE3__CB_BUSY__SHIFT                                                                       0x1f
#define GRBM_STATUS_SE3__DB_CLEAN_MASK                                                                        0x00000002L
#define GRBM_STATUS_SE3__CB_CLEAN_MASK                                                                        0x00000004L
#define GRBM_STATUS_SE3__UTCL1_BUSY_MASK                                                                      0x00000008L
#define GRBM_STATUS_SE3__TCP_BUSY_MASK                                                                        0x00000010L
#define GRBM_STATUS_SE3__GL1CC_BUSY_MASK                                                                      0x00000020L
#define GRBM_STATUS_SE3__RMI_BUSY_MASK                                                                        0x00200000L
#define GRBM_STATUS_SE3__BCI_BUSY_MASK                                                                        0x00400000L
#define GRBM_STATUS_SE3__PA_BUSY_MASK                                                                         0x01000000L
#define GRBM_STATUS_SE3__TA_BUSY_MASK                                                                         0x02000000L
#define GRBM_STATUS_SE3__SX_BUSY_MASK                                                                         0x04000000L
#define GRBM_STATUS_SE3__SPI_BUSY_MASK                                                                        0x08000000L
#define GRBM_STATUS_SE3__SC_BUSY_MASK                                                                         0x20000000L
#define GRBM_STATUS_SE3__DB_BUSY_MASK                                                                         0x40000000L
#define GRBM_STATUS_SE3__CB_BUSY_MASK                                                                         0x80000000L
//GRBM_READ_ERROR
#define GRBM_READ_ERROR__READ_ADDRESS__SHIFT                                                                  0x2
#define GRBM_READ_ERROR__READ_PIPEID__SHIFT                                                                   0x14
#define GRBM_READ_ERROR__READ_MEID__SHIFT                                                                     0x16
#define GRBM_READ_ERROR__READ_ERROR__SHIFT                                                                    0x1f
#define GRBM_READ_ERROR__READ_ADDRESS_MASK                                                                    0x0003FFFCL
#define GRBM_READ_ERROR__READ_PIPEID_MASK                                                                     0x00300000L
#define GRBM_READ_ERROR__READ_MEID_MASK                                                                       0x00C00000L
#define GRBM_READ_ERROR__READ_ERROR_MASK                                                                      0x80000000L
//GRBM_READ_ERROR2
#define GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE0__SHIFT                                                      0x9
#define GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE1__SHIFT                                                      0xa
#define GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE2__SHIFT                                                      0xb
#define GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE3__SHIFT                                                      0xc
#define GRBM_READ_ERROR2__READ_REQUESTER_SDMA0__SHIFT                                                         0xd
#define GRBM_READ_ERROR2__READ_REQUESTER_SDMA1__SHIFT                                                         0xe
#define GRBM_READ_ERROR2__READ_REQUESTER_SDMA2__SHIFT                                                         0xf
#define GRBM_READ_ERROR2__READ_REQUESTER_SDMA3__SHIFT                                                         0x10
#define GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT                                                           0x12
#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT                                                       0x13
#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT                                                   0x14
#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF__SHIFT                                                   0x15
#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF__SHIFT                                                   0x16
#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF__SHIFT                                                   0x17
#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0__SHIFT                                                      0x18
#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1__SHIFT                                                      0x19
#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2__SHIFT                                                      0x1a
#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3__SHIFT                                                      0x1b
#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0__SHIFT                                                      0x1c
#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT                                                      0x1d
#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT                                                      0x1e
#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT                                                      0x1f
#define GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE0_MASK                                                        0x00000200L
#define GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE1_MASK                                                        0x00000400L
#define GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE2_MASK                                                        0x00000800L
#define GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE3_MASK                                                        0x00001000L
#define GRBM_READ_ERROR2__READ_REQUESTER_SDMA0_MASK                                                           0x00002000L
#define GRBM_READ_ERROR2__READ_REQUESTER_SDMA1_MASK                                                           0x00004000L
#define GRBM_READ_ERROR2__READ_REQUESTER_SDMA2_MASK                                                           0x00008000L
#define GRBM_READ_ERROR2__READ_REQUESTER_SDMA3_MASK                                                           0x00010000L
#define GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK                                                             0x00040000L
#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK                                                         0x00080000L
#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK                                                     0x00100000L
#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF_MASK                                                     0x00200000L
#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF_MASK                                                     0x00400000L
#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF_MASK                                                     0x00800000L
#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0_MASK                                                        0x01000000L
#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1_MASK                                                        0x02000000L
#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2_MASK                                                        0x04000000L
#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3_MASK                                                        0x08000000L
#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0_MASK                                                        0x10000000L
#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1_MASK                                                        0x20000000L
#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2_MASK                                                        0x40000000L
#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3_MASK                                                        0x80000000L
//GRBM_INT_CNTL
#define GRBM_INT_CNTL__RDERR_INT_ENABLE__SHIFT                                                                0x0
#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE__SHIFT                                                             0x13
#define GRBM_INT_CNTL__RDERR_INT_ENABLE_MASK                                                                  0x00000001L
#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE_MASK                                                               0x00080000L
//GRBM_TRAP_OP
#define GRBM_TRAP_OP__RW__SHIFT                                                                               0x0
#define GRBM_TRAP_OP__RW_MASK                                                                                 0x00000001L
//GRBM_TRAP_ADDR
#define GRBM_TRAP_ADDR__DATA__SHIFT                                                                           0x0
#define GRBM_TRAP_ADDR__DATA_MASK                                                                             0x0003FFFFL
//GRBM_TRAP_ADDR_MSK
#define GRBM_TRAP_ADDR_MSK__DATA__SHIFT                                                                       0x0
#define GRBM_TRAP_ADDR_MSK__DATA_MASK                                                                         0x0003FFFFL
//GRBM_TRAP_WD
#define GRBM_TRAP_WD__DATA__SHIFT                                                                             0x0
#define GRBM_TRAP_WD__DATA_MASK                                                                               0xFFFFFFFFL
//GRBM_TRAP_WD_MSK
#define GRBM_TRAP_WD_MSK__DATA__SHIFT                                                                         0x0
#define GRBM_TRAP_WD_MSK__DATA_MASK                                                                           0xFFFFFFFFL
//GRBM_DSM_BYPASS
#define GRBM_DSM_BYPASS__BYPASS_BITS__SHIFT                                                                   0x0
#define GRBM_DSM_BYPASS__BYPASS_EN__SHIFT                                                                     0x2
#define GRBM_DSM_BYPASS__BYPASS_BITS_MASK                                                                     0x00000003L
#define GRBM_DSM_BYPASS__BYPASS_EN_MASK                                                                       0x00000004L
//GRBM_WRITE_ERROR
#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC__SHIFT                                                          0x0
#define GRBM_WRITE_ERROR__WRITE_SSRCID__SHIFT                                                                 0x2
#define GRBM_WRITE_ERROR__WRITE_VFID__SHIFT                                                                   0x5
#define GRBM_WRITE_ERROR__WRITE_VF__SHIFT                                                                     0xc
#define GRBM_WRITE_ERROR__WRITE_VMID__SHIFT                                                                   0xd
#define GRBM_WRITE_ERROR__CP_SECURE_WR_ILLEGAL__SHIFT                                                         0x12
#define GRBM_WRITE_ERROR__WRITE_PIPEID__SHIFT                                                                 0x14
#define GRBM_WRITE_ERROR__WRITE_MEID__SHIFT                                                                   0x16
#define GRBM_WRITE_ERROR__WRITE_ERROR__SHIFT                                                                  0x1f
#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC_MASK                                                            0x00000001L
#define GRBM_WRITE_ERROR__WRITE_SSRCID_MASK                                                                   0x0000001CL
#define GRBM_WRITE_ERROR__WRITE_VFID_MASK                                                                     0x000007E0L
#define GRBM_WRITE_ERROR__WRITE_VF_MASK                                                                       0x00001000L
#define GRBM_WRITE_ERROR__WRITE_VMID_MASK                                                                     0x0001E000L
#define GRBM_WRITE_ERROR__CP_SECURE_WR_ILLEGAL_MASK                                                           0x00040000L
#define GRBM_WRITE_ERROR__WRITE_PIPEID_MASK                                                                   0x00300000L
#define GRBM_WRITE_ERROR__WRITE_MEID_MASK                                                                     0x00C00000L
#define GRBM_WRITE_ERROR__WRITE_ERROR_MASK                                                                    0x80000000L
//GRBM_CHIP_REVISION
#define GRBM_CHIP_REVISION__CHIP_REVISION__SHIFT                                                              0x0
#define GRBM_CHIP_REVISION__CHIP_REVISION_MASK                                                                0x000000FFL
//GRBM_GFX_CNTL
#define GRBM_GFX_CNTL__PIPEID__SHIFT                                                                          0x0
#define GRBM_GFX_CNTL__MEID__SHIFT                                                                            0x2
#define GRBM_GFX_CNTL__VMID__SHIFT                                                                            0x4
#define GRBM_GFX_CNTL__QUEUEID__SHIFT                                                                         0x8
#define GRBM_GFX_CNTL__PIPEID_MASK                                                                            0x00000003L
#define GRBM_GFX_CNTL__MEID_MASK                                                                              0x0000000CL
#define GRBM_GFX_CNTL__VMID_MASK                                                                              0x000000F0L
#define GRBM_GFX_CNTL__QUEUEID_MASK                                                                           0x00000700L
//GRBM_IH_CREDIT
#define GRBM_IH_CREDIT__CREDIT_VALUE__SHIFT                                                                   0x0
#define GRBM_IH_CREDIT__IH_CLIENT_ID__SHIFT                                                                   0x10
#define GRBM_IH_CREDIT__CREDIT_VALUE_MASK                                                                     0x00000003L
#define GRBM_IH_CREDIT__IH_CLIENT_ID_MASK                                                                     0x00FF0000L
//GRBM_PWR_CNTL2
#define GRBM_PWR_CNTL2__PWR_REQUEST_HALT__SHIFT                                                               0x10
#define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT__SHIFT                                                         0x14
#define GRBM_PWR_CNTL2__PWR_REQUEST_HALT_MASK                                                                 0x00010000L
#define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT_MASK                                                           0x00100000L
//GRBM_UTCL2_INVAL_RANGE_START
#define GRBM_UTCL2_INVAL_RANGE_START__DATA__SHIFT                                                             0x0
#define GRBM_UTCL2_INVAL_RANGE_START__DATA_MASK                                                               0x0003FFFFL
//GRBM_UTCL2_INVAL_RANGE_END
#define GRBM_UTCL2_INVAL_RANGE_END__DATA__SHIFT                                                               0x0
#define GRBM_UTCL2_INVAL_RANGE_END__DATA_MASK                                                                 0x0003FFFFL
//GRBM_FENCE_RANGE0
#define GRBM_FENCE_RANGE0__START__SHIFT                                                                       0x0
#define GRBM_FENCE_RANGE0__END__SHIFT                                                                         0x10
#define GRBM_FENCE_RANGE0__START_MASK                                                                         0x0000FFFFL
#define GRBM_FENCE_RANGE0__END_MASK                                                                           0xFFFF0000L
//GRBM_FENCE_RANGE1
#define GRBM_FENCE_RANGE1__START__SHIFT                                                                       0x0
#define GRBM_FENCE_RANGE1__END__SHIFT                                                                         0x10
#define GRBM_FENCE_RANGE1__START_MASK                                                                         0x0000FFFFL
#define GRBM_FENCE_RANGE1__END_MASK                                                                           0xFFFF0000L
//GRBM_NOWHERE
#define GRBM_NOWHERE__DATA__SHIFT                                                                             0x0
#define GRBM_NOWHERE__DATA_MASK                                                                               0xFFFFFFFFL
//GRBM_SCRATCH_REG0
#define GRBM_SCRATCH_REG0__SCRATCH_REG0__SHIFT                                                                0x0
#define GRBM_SCRATCH_REG0__SCRATCH_REG0_MASK                                                                  0xFFFFFFFFL
//GRBM_SCRATCH_REG1
#define GRBM_SCRATCH_REG1__SCRATCH_REG1__SHIFT                                                                0x0
#define GRBM_SCRATCH_REG1__SCRATCH_REG1_MASK                                                                  0xFFFFFFFFL
//GRBM_SCRATCH_REG2
#define GRBM_SCRATCH_REG2__SCRATCH_REG2__SHIFT                                                                0x0
#define GRBM_SCRATCH_REG2__SCRATCH_REG2_MASK                                                                  0xFFFFFFFFL
//GRBM_SCRATCH_REG3
#define GRBM_SCRATCH_REG3__SCRATCH_REG3__SHIFT                                                                0x0
#define GRBM_SCRATCH_REG3__SCRATCH_REG3_MASK                                                                  0xFFFFFFFFL
//GRBM_SCRATCH_REG4
#define GRBM_SCRATCH_REG4__SCRATCH_REG4__SHIFT                                                                0x0
#define GRBM_SCRATCH_REG4__SCRATCH_REG4_MASK                                                                  0xFFFFFFFFL
//GRBM_SCRATCH_REG5
#define GRBM_SCRATCH_REG5__SCRATCH_REG5__SHIFT                                                                0x0
#define GRBM_SCRATCH_REG5__SCRATCH_REG5_MASK                                                                  0xFFFFFFFFL
//GRBM_SCRATCH_REG6
#define GRBM_SCRATCH_REG6__SCRATCH_REG6__SHIFT                                                                0x0
#define GRBM_SCRATCH_REG6__SCRATCH_REG6_MASK                                                                  0xFFFFFFFFL
//GRBM_SCRATCH_REG7
#define GRBM_SCRATCH_REG7__SCRATCH_REG7__SHIFT                                                                0x0
#define GRBM_SCRATCH_REG7__SCRATCH_REG7_MASK                                                                  0xFFFFFFFFL
//VIOLATION_DATA_ASYNC_VF_PROG
#define VIOLATION_DATA_ASYNC_VF_PROG__SSRCID__SHIFT                                                           0x0
#define VIOLATION_DATA_ASYNC_VF_PROG__VFID__SHIFT                                                             0x4
#define VIOLATION_DATA_ASYNC_VF_PROG__VIOLATION_ERROR__SHIFT                                                  0x1f
#define VIOLATION_DATA_ASYNC_VF_PROG__SSRCID_MASK                                                             0x0000000FL
#define VIOLATION_DATA_ASYNC_VF_PROG__VFID_MASK                                                               0x000003F0L
#define VIOLATION_DATA_ASYNC_VF_PROG__VIOLATION_ERROR_MASK                                                    0x80000000L


// addressBlock: gc_cpdec
//CP_CPC_STATUS
#define CP_CPC_STATUS__MEC1_BUSY__SHIFT                                                                       0x0
#define CP_CPC_STATUS__MEC2_BUSY__SHIFT                                                                       0x1
#define CP_CPC_STATUS__DC0_BUSY__SHIFT                                                                        0x2
#define CP_CPC_STATUS__DC1_BUSY__SHIFT                                                                        0x3
#define CP_CPC_STATUS__RCIU1_BUSY__SHIFT                                                                      0x4
#define CP_CPC_STATUS__RCIU2_BUSY__SHIFT                                                                      0x5
#define CP_CPC_STATUS__ROQ1_BUSY__SHIFT                                                                       0x6
#define CP_CPC_STATUS__ROQ2_BUSY__SHIFT                                                                       0x7
#define CP_CPC_STATUS__TCIU_BUSY__SHIFT                                                                       0xa
#define CP_CPC_STATUS__SCRATCH_RAM_BUSY__SHIFT                                                                0xb
#define CP_CPC_STATUS__QU_BUSY__SHIFT                                                                         0xc
#define CP_CPC_STATUS__UTCL2IU_BUSY__SHIFT                                                                    0xd
#define CP_CPC_STATUS__SAVE_RESTORE_BUSY__SHIFT                                                               0xe
#define CP_CPC_STATUS__GCRIU_BUSY__SHIFT                                                                      0xf
#define CP_CPC_STATUS__MES_BUSY__SHIFT                                                                        0x10
#define CP_CPC_STATUS__MES_SCRATCH_RAM_BUSY__SHIFT                                                            0x11
#define CP_CPC_STATUS__RCIU3_BUSY__SHIFT                                                                      0x12
#define CP_CPC_STATUS__MES_INSTRUCTION_CACHE_BUSY__SHIFT                                                      0x13
#define CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT                                                                    0x1d
#define CP_CPC_STATUS__CPF_CPC_BUSY__SHIFT                                                                    0x1e
#define CP_CPC_STATUS__CPC_BUSY__SHIFT                                                                        0x1f
#define CP_CPC_STATUS__MEC1_BUSY_MASK                                                                         0x00000001L
#define CP_CPC_STATUS__MEC2_BUSY_MASK                                                                         0x00000002L
#define CP_CPC_STATUS__DC0_BUSY_MASK                                                                          0x00000004L
#define CP_CPC_STATUS__DC1_BUSY_MASK                                                                          0x00000008L
#define CP_CPC_STATUS__RCIU1_BUSY_MASK                                                                        0x00000010L
#define CP_CPC_STATUS__RCIU2_BUSY_MASK                                                                        0x00000020L
#define CP_CPC_STATUS__ROQ1_BUSY_MASK                                                                         0x00000040L
#define CP_CPC_STATUS__ROQ2_BUSY_MASK                                                                         0x00000080L
#define CP_CPC_STATUS__TCIU_BUSY_MASK                                                                         0x00000400L
#define CP_CPC_STATUS__SCRATCH_RAM_BUSY_MASK                                                                  0x00000800L
#define CP_CPC_STATUS__QU_BUSY_MASK                                                                           0x00001000L
#define CP_CPC_STATUS__UTCL2IU_BUSY_MASK                                                                      0x00002000L
#define CP_CPC_STATUS__SAVE_RESTORE_BUSY_MASK                                                                 0x00004000L
#define CP_CPC_STATUS__GCRIU_BUSY_MASK                                                                        0x00008000L
#define CP_CPC_STATUS__MES_BUSY_MASK                                                                          0x00010000L
#define CP_CPC_STATUS__MES_SCRATCH_RAM_BUSY_MASK                                                              0x00020000L
#define CP_CPC_STATUS__RCIU3_BUSY_MASK                                                                        0x00040000L
#define CP_CPC_STATUS__MES_INSTRUCTION_CACHE_BUSY_MASK                                                        0x00080000L
#define CP_CPC_STATUS__CPG_CPC_BUSY_MASK                                                                      0x20000000L
#define CP_CPC_STATUS__CPF_CPC_BUSY_MASK                                                                      0x40000000L
#define CP_CPC_STATUS__CPC_BUSY_MASK                                                                          0x80000000L
//CP_CPC_BUSY_STAT
#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY__SHIFT                                                               0x0
#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY__SHIFT                                                          0x1
#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY__SHIFT                                                              0x2
#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY__SHIFT                                                            0x3
#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY__SHIFT                                                          0x4
#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT                                                           0x5
#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY__SHIFT                                                           0x6
#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY__SHIFT                                                                 0x7
#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY__SHIFT                                                                0x8
#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY__SHIFT                                                      0x9
#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT                                                              0xa
#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY__SHIFT                                                              0xb
#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY__SHIFT                                                              0xc
#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY__SHIFT                                                              0xd
#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY__SHIFT                                                               0x10
#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY__SHIFT                                                          0x11
#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY__SHIFT                                                              0x12
#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY__SHIFT                                                            0x13
#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT                                                          0x14
#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT                                                           0x15
#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY__SHIFT                                                           0x16
#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY__SHIFT                                                                 0x17
#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY__SHIFT                                                                0x18
#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY__SHIFT                                                      0x19
#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY__SHIFT                                                              0x1a
#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY__SHIFT                                                              0x1b
#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY__SHIFT                                                              0x1c
#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT                                                              0x1d
#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY_MASK                                                                 0x00000001L
#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY_MASK                                                            0x00000002L
#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY_MASK                                                                0x00000004L
#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY_MASK                                                              0x00000008L
#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY_MASK                                                            0x00000010L
#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK                                                             0x00000020L
#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY_MASK                                                             0x00000040L
#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY_MASK                                                                   0x00000080L
#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY_MASK                                                                  0x00000100L
#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY_MASK                                                        0x00000200L
#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK                                                                0x00000400L
#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK                                                                0x00000800L
#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY_MASK                                                                0x00001000L
#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY_MASK                                                                0x00002000L
#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY_MASK                                                                 0x00010000L
#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY_MASK                                                            0x00020000L
#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY_MASK                                                                0x00040000L
#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY_MASK                                                              0x00080000L
#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY_MASK                                                            0x00100000L
#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY_MASK                                                             0x00200000L
#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY_MASK                                                             0x00400000L
#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY_MASK                                                                   0x00800000L
#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY_MASK                                                                  0x01000000L
#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY_MASK                                                        0x02000000L
#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY_MASK                                                                0x04000000L
#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY_MASK                                                                0x08000000L
#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY_MASK                                                                0x10000000L
#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY_MASK                                                                0x20000000L
//CP_CPC_STALLED_STAT1
#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL__SHIFT                                                       0x3
#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION__SHIFT                                                      0x4
#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL__SHIFT                                                       0x6
#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET__SHIFT                                                     0x8
#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU__SHIFT                                                        0x9
#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT                                                   0xa
#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA__SHIFT                                                    0xd
#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET__SHIFT                                                     0x10
#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU__SHIFT                                                        0x11
#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ__SHIFT                                                   0x12
#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA__SHIFT                                                    0x15
#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT                                                  0x16
#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT                                                  0x17
#define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS__SHIFT                                                   0x18
#define CP_CPC_STALLED_STAT1__GCRIU_WAITING_ON_FREE__SHIFT                                                    0x19
#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL_MASK                                                         0x00000008L
#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION_MASK                                                        0x00000010L
#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL_MASK                                                         0x00000040L
#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET_MASK                                                       0x00000100L
#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_MASK                                                          0x00000200L
#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ_MASK                                                     0x00000400L
#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA_MASK                                                      0x00002000L
#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET_MASK                                                       0x00010000L
#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_MASK                                                          0x00020000L
#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ_MASK                                                     0x00040000L
#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK                                                      0x00200000L
#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK                                                    0x00400000L
#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK                                                    0x00800000L
#define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS_MASK                                                     0x01000000L
#define CP_CPC_STALLED_STAT1__GCRIU_WAITING_ON_FREE_MASK                                                      0x02000000L
//CP_CPF_STATUS
#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY__SHIFT                                                              0x0
#define CP_CPF_STATUS__CSF_BUSY__SHIFT                                                                        0x1
#define CP_CPF_STATUS__ROQ_ALIGN_BUSY__SHIFT                                                                  0x4
#define CP_CPF_STATUS__ROQ_RING_BUSY__SHIFT                                                                   0x5
#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY__SHIFT                                                              0x6
#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY__SHIFT                                                              0x7
#define CP_CPF_STATUS__ROQ_STATE_BUSY__SHIFT                                                                  0x8
#define CP_CPF_STATUS__ROQ_CE_RING_BUSY__SHIFT                                                                0x9
#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT                                                           0xa
#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY__SHIFT                                                           0xb
#define CP_CPF_STATUS__SEMAPHORE_BUSY__SHIFT                                                                  0xc
#define CP_CPF_STATUS__INTERRUPT_BUSY__SHIFT                                                                  0xd
#define CP_CPF_STATUS__TCIU_BUSY__SHIFT                                                                       0xe
#define CP_CPF_STATUS__HQD_BUSY__SHIFT                                                                        0xf
#define CP_CPF_STATUS__PRT_BUSY__SHIFT                                                                        0x10
#define CP_CPF_STATUS__UTCL2IU_BUSY__SHIFT                                                                    0x11
#define CP_CPF_STATUS__RCIU_BUSY__SHIFT                                                                       0x12
#define CP_CPF_STATUS__RCIU_GFX_BUSY__SHIFT                                                                   0x13
#define CP_CPF_STATUS__RCIU_CMP_BUSY__SHIFT                                                                   0x14
#define CP_CPF_STATUS__ROQ_DATA_BUSY__SHIFT                                                                   0x15
#define CP_CPF_STATUS__ROQ_CE_DATA_BUSY__SHIFT                                                                0x16
#define CP_CPF_STATUS__GCRIU_BUSY__SHIFT                                                                      0x17
#define CP_CPF_STATUS__MES_HQD_BUSY__SHIFT                                                                    0x18
#define CP_CPF_STATUS__CPF_GFX_BUSY__SHIFT                                                                    0x1a
#define CP_CPF_STATUS__CPF_CMP_BUSY__SHIFT                                                                    0x1b
#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY__SHIFT                                                              0x1c
#define CP_CPF_STATUS__CPC_CPF_BUSY__SHIFT                                                                    0x1e
#define CP_CPF_STATUS__CPF_BUSY__SHIFT                                                                        0x1f
#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY_MASK                                                                0x00000001L
#define CP_CPF_STATUS__CSF_BUSY_MASK                                                                          0x00000002L
#define CP_CPF_STATUS__ROQ_ALIGN_BUSY_MASK                                                                    0x00000010L
#define CP_CPF_STATUS__ROQ_RING_BUSY_MASK                                                                     0x00000020L
#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY_MASK                                                                0x00000040L
#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY_MASK                                                                0x00000080L
#define CP_CPF_STATUS__ROQ_STATE_BUSY_MASK                                                                    0x00000100L
#define CP_CPF_STATUS__ROQ_CE_RING_BUSY_MASK                                                                  0x00000200L
#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY_MASK                                                             0x00000400L
#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY_MASK                                                             0x00000800L
#define CP_CPF_STATUS__SEMAPHORE_BUSY_MASK                                                                    0x00001000L
#define CP_CPF_STATUS__INTERRUPT_BUSY_MASK                                                                    0x00002000L
#define CP_CPF_STATUS__TCIU_BUSY_MASK                                                                         0x00004000L
#define CP_CPF_STATUS__HQD_BUSY_MASK                                                                          0x00008000L
#define CP_CPF_STATUS__PRT_BUSY_MASK                                                                          0x00010000L
#define CP_CPF_STATUS__UTCL2IU_BUSY_MASK                                                                      0x00020000L
#define CP_CPF_STATUS__RCIU_BUSY_MASK                                                                         0x00040000L
#define CP_CPF_STATUS__RCIU_GFX_BUSY_MASK                                                                     0x00080000L
#define CP_CPF_STATUS__RCIU_CMP_BUSY_MASK                                                                     0x00100000L
#define CP_CPF_STATUS__ROQ_DATA_BUSY_MASK                                                                     0x00200000L
#define CP_CPF_STATUS__ROQ_CE_DATA_BUSY_MASK                                                                  0x00400000L
#define CP_CPF_STATUS__GCRIU_BUSY_MASK                                                                        0x00800000L
#define CP_CPF_STATUS__MES_HQD_BUSY_MASK                                                                      0x01000000L
#define CP_CPF_STATUS__CPF_GFX_BUSY_MASK                                                                      0x04000000L
#define CP_CPF_STATUS__CPF_CMP_BUSY_MASK                                                                      0x08000000L
#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY_MASK                                                                0x30000000L
#define CP_CPF_STATUS__CPC_CPF_BUSY_MASK                                                                      0x40000000L
#define CP_CPF_STATUS__CPF_BUSY_MASK                                                                          0x80000000L
//CP_CPF_BUSY_STAT
#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT                                                            0x0
#define CP_CPF_BUSY_STAT__CSF_RING_BUSY__SHIFT                                                                0x1
#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY__SHIFT                                                           0x2
#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY__SHIFT                                                           0x3
#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY__SHIFT                                                               0x4
#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY__SHIFT                                                            0x5
#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY__SHIFT                                                            0x6
#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY__SHIFT                                                             0x7
#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY__SHIFT                                                               0x8
#define CP_CPF_BUSY_STAT__CSF_DATA_BUSY__SHIFT                                                                0x9
#define CP_CPF_BUSY_STAT__CSF_CE_DATA_BUSY__SHIFT                                                             0xa
#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY__SHIFT                                                      0xb
#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY__SHIFT                                                            0xc
#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY__SHIFT                                                            0xd
#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY__SHIFT                                                         0xe
#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY__SHIFT                                                      0xf
#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY__SHIFT                                                    0x10
#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY__SHIFT                                                             0x11
#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY__SHIFT                                                          0x12
#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY__SHIFT                                                          0x13
#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY__SHIFT                                                          0x14
#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY__SHIFT                                                         0x15
#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY__SHIFT                                                       0x16
#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY__SHIFT                                                         0x17
#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY__SHIFT                                                           0x18
#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY__SHIFT                                                             0x19
#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY__SHIFT                                                              0x1a
#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY__SHIFT                                                              0x1b
#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY__SHIFT                                                              0x1c
#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY__SHIFT                                                           0x1d
#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY__SHIFT                                                                  0x1e
#define CP_CPF_BUSY_STAT__HQD_IB_BUSY__SHIFT                                                                  0x1f
#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK                                                              0x00000001L
#define CP_CPF_BUSY_STAT__CSF_RING_BUSY_MASK                                                                  0x00000002L
#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY_MASK                                                             0x00000004L
#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY_MASK                                                             0x00000008L
#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY_MASK                                                                 0x00000010L
#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY_MASK                                                              0x00000020L
#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY_MASK                                                              0x00000040L
#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY_MASK                                                               0x00000080L
#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY_MASK                                                                 0x00000100L
#define CP_CPF_BUSY_STAT__CSF_DATA_BUSY_MASK                                                                  0x00000200L
#define CP_CPF_BUSY_STAT__CSF_CE_DATA_BUSY_MASK                                                               0x00000400L
#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY_MASK                                                        0x00000800L
#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY_MASK                                                              0x00001000L
#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY_MASK                                                              0x00002000L
#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY_MASK                                                           0x00004000L
#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY_MASK                                                        0x00008000L
#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY_MASK                                                      0x00010000L
#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY_MASK                                                               0x00020000L
#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY_MASK                                                            0x00040000L
#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY_MASK                                                            0x00080000L
#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY_MASK                                                            0x00100000L
#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY_MASK                                                           0x00200000L
#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY_MASK                                                         0x00400000L
#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY_MASK                                                           0x00800000L
#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY_MASK                                                             0x01000000L
#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY_MASK                                                               0x02000000L
#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY_MASK                                                                0x04000000L
#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY_MASK                                                                0x08000000L
#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY_MASK                                                                0x10000000L
#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY_MASK                                                             0x20000000L
#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY_MASK                                                                    0x40000000L
#define CP_CPF_BUSY_STAT__HQD_IB_BUSY_MASK                                                                    0x80000000L
//CP_CPF_STALLED_STAT1
#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA__SHIFT                                                       0x0
#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA__SHIFT                                                      0x1
#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA__SHIFT                                                      0x2
#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA__SHIFT                                                      0x3
#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE__SHIFT                                                     0x5
#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT                                                     0x6
#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT                                                  0x7
#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT                                                  0x8
#define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS__SHIFT                                               0x9
#define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS__SHIFT                                               0xa
#define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE__SHIFT                                                     0xb
#define CP_CPF_STALLED_STAT1__DATA_FETCHING_DATA__SHIFT                                                       0xc
#define CP_CPF_STALLED_STAT1__GCRIU_WAIT_ON_FREE__SHIFT                                                       0xd
#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA_MASK                                                         0x00000001L
#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA_MASK                                                        0x00000002L
#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA_MASK                                                        0x00000004L
#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA_MASK                                                        0x00000008L
#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE_MASK                                                       0x00000020L
#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK                                                       0x00000040L
#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK                                                    0x00000080L
#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK                                                    0x00000100L
#define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS_MASK                                                 0x00000200L
#define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS_MASK                                                 0x00000400L
#define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE_MASK                                                       0x00000800L
#define CP_CPF_STALLED_STAT1__DATA_FETCHING_DATA_MASK                                                         0x00001000L
#define CP_CPF_STALLED_STAT1__GCRIU_WAIT_ON_FREE_MASK                                                         0x00002000L
//CP_CPC_BUSY_STAT2
#define CP_CPC_BUSY_STAT2__MES_LOAD_BUSY__SHIFT                                                               0x0
#define CP_CPC_BUSY_STAT2__MES_MUTEX_BUSY__SHIFT                                                              0x2
#define CP_CPC_BUSY_STAT2__MES_MESSAGE_BUSY__SHIFT                                                            0x3
#define CP_CPC_BUSY_STAT2__MES_TC_BUSY__SHIFT                                                                 0x7
#define CP_CPC_BUSY_STAT2__MES_DMA_BUSY__SHIFT                                                                0x8
#define CP_CPC_BUSY_STAT2__MES_PIPE0_BUSY__SHIFT                                                              0xa
#define CP_CPC_BUSY_STAT2__MES_PIPE1_BUSY__SHIFT                                                              0xb
#define CP_CPC_BUSY_STAT2__MES_PIPE2_BUSY__SHIFT                                                              0xc
#define CP_CPC_BUSY_STAT2__MES_PIPE3_BUSY__SHIFT                                                              0xd
#define CP_CPC_BUSY_STAT2__MES_LOAD_BUSY_MASK                                                                 0x00000001L
#define CP_CPC_BUSY_STAT2__MES_MUTEX_BUSY_MASK                                                                0x00000004L
#define CP_CPC_BUSY_STAT2__MES_MESSAGE_BUSY_MASK                                                              0x00000008L
#define CP_CPC_BUSY_STAT2__MES_TC_BUSY_MASK                                                                   0x00000080L
#define CP_CPC_BUSY_STAT2__MES_DMA_BUSY_MASK                                                                  0x00000100L
#define CP_CPC_BUSY_STAT2__MES_PIPE0_BUSY_MASK                                                                0x00000400L
#define CP_CPC_BUSY_STAT2__MES_PIPE1_BUSY_MASK                                                                0x00000800L
#define CP_CPC_BUSY_STAT2__MES_PIPE2_BUSY_MASK                                                                0x00001000L
#define CP_CPC_BUSY_STAT2__MES_PIPE3_BUSY_MASK                                                                0x00002000L
//CP_CPC_GRBM_FREE_COUNT
#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT__SHIFT                                                             0x0
#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT_MASK                                                               0x0000003FL
//CP_CPC_PRIV_VIOLATION_ADDR
#define CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR__SHIFT                                                0x0
#define CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR_MASK                                                  0x0000FFFFL
//CP_MEC_ME1_HEADER_DUMP
#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP__SHIFT                                                            0x0
#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP_MASK                                                              0xFFFFFFFFL
//CP_MEC_ME2_HEADER_DUMP
#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP__SHIFT                                                            0x0
#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP_MASK                                                              0xFFFFFFFFL
//CP_CPC_SCRATCH_INDEX
#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT                                                            0x0
#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE__SHIFT                                                 0x1f
#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_MASK                                                              0x000001FFL
#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE_MASK                                                   0x80000000L
//CP_CPC_SCRATCH_DATA
#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA__SHIFT                                                              0x0
#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA_MASK                                                                0xFFFFFFFFL
//CP_CPF_GRBM_FREE_COUNT
#define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT__SHIFT                                                             0x0
#define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT_MASK                                                               0x00000007L
//CP_CPF_BUSY_STAT2
#define CP_CPF_BUSY_STAT2__MES_HQD_DISPATCH_BUSY__SHIFT                                                       0xc
#define CP_CPF_BUSY_STAT2__MES_HQD_DMA_OFFLOAD_BUSY__SHIFT                                                    0xe
#define CP_CPF_BUSY_STAT2__MES_HQD_MESSAGE_BUSY__SHIFT                                                        0x11
#define CP_CPF_BUSY_STAT2__MES_HQD_PQ_FETCHER_BUSY__SHIFT                                                     0x12
#define CP_CPF_BUSY_STAT2__MES_HQD_CONSUMED_RPTR_BUSY__SHIFT                                                  0x16
#define CP_CPF_BUSY_STAT2__MES_HQD_FETCHER_ARB_BUSY__SHIFT                                                    0x17
#define CP_CPF_BUSY_STAT2__MES_HQD_ROQ_ALIGN_BUSY__SHIFT                                                      0x18
#define CP_CPF_BUSY_STAT2__MES_HQD_ROQ_PQ_BUSY__SHIFT                                                         0x1b
#define CP_CPF_BUSY_STAT2__MES_HQD_PQ_BUSY__SHIFT                                                             0x1e
#define CP_CPF_BUSY_STAT2__MES_HQD_DISPATCH_BUSY_MASK                                                         0x00001000L
#define CP_CPF_BUSY_STAT2__MES_HQD_DMA_OFFLOAD_BUSY_MASK                                                      0x00004000L
#define CP_CPF_BUSY_STAT2__MES_HQD_MESSAGE_BUSY_MASK                                                          0x00020000L
#define CP_CPF_BUSY_STAT2__MES_HQD_PQ_FETCHER_BUSY_MASK                                                       0x00040000L
#define CP_CPF_BUSY_STAT2__MES_HQD_CONSUMED_RPTR_BUSY_MASK                                                    0x00400000L
#define CP_CPF_BUSY_STAT2__MES_HQD_FETCHER_ARB_BUSY_MASK                                                      0x00800000L
#define CP_CPF_BUSY_STAT2__MES_HQD_ROQ_ALIGN_BUSY_MASK                                                        0x01000000L
#define CP_CPF_BUSY_STAT2__MES_HQD_ROQ_PQ_BUSY_MASK                                                           0x08000000L
#define CP_CPF_BUSY_STAT2__MES_HQD_PQ_BUSY_MASK                                                               0x40000000L
//CONFIG_RESERVED_REG0
#define CONFIG_RESERVED_REG0__DATA__SHIFT                                                                     0x0
#define CONFIG_RESERVED_REG0__DATA_MASK                                                                       0xFFFFFFFFL
//CONFIG_RESERVED_REG1
#define CONFIG_RESERVED_REG1__DATA__SHIFT                                                                     0x0
#define CONFIG_RESERVED_REG1__DATA_MASK                                                                       0xFFFFFFFFL
//CP_CPC_HALT_HYST_COUNT
#define CP_CPC_HALT_HYST_COUNT__COUNT__SHIFT                                                                  0x0
#define CP_CPC_HALT_HYST_COUNT__COUNT_MASK                                                                    0x0000000FL
//CP_CE_COMPARE_COUNT
#define CP_CE_COMPARE_COUNT__COMPARE_COUNT__SHIFT                                                             0x0
#define CP_CE_COMPARE_COUNT__COMPARE_COUNT_MASK                                                               0xFFFFFFFFL
//CP_CE_DE_COUNT
#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT                                                              0x0
#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT_MASK                                                                0xFFFFFFFFL
//CP_DE_CE_COUNT
#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT__SHIFT                                                             0x0
#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT_MASK                                                               0xFFFFFFFFL
//CP_DE_LAST_INVAL_COUNT
#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT__SHIFT                                                       0x0
#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT_MASK                                                         0xFFFFFFFFL
//CP_DE_DE_COUNT
#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT                                                              0x0
#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT_MASK                                                                0xFFFFFFFFL
//CP_STALLED_STAT3
#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT                                                     0x0
#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT                                        0x1
#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT                                     0x2
#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT                                                       0x3
#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT                                                       0x4
#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT                                                      0x5
#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT                                                0x6
#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT                                                 0x7
#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT                                                    0xa
#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT                                                 0xb
#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT                                                     0xc
#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT                                           0xd
#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT                                                         0xe
#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT                                                         0xf
#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM__SHIFT                                                  0x10
#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA__SHIFT                                                0x11
#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE__SHIFT                                                      0x12
#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS__SHIFT                                                      0x13
#define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS__SHIFT                                                       0x14
#define CP_STALLED_STAT3__GCRIU_WAITING_ON_FREE__SHIFT                                                        0x15
#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK                                                       0x00000001L
#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK                                          0x00000002L
#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK                                       0x00000004L
#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK                                                         0x00000008L
#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK                                                         0x00000010L
#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK                                                        0x00000020L
#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK                                                  0x00000040L
#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK                                                   0x00000080L
#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK                                                      0x00000400L
#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK                                                   0x00000800L
#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK                                                       0x00001000L
#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK                                             0x00002000L
#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK                                                           0x00004000L
#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK                                                           0x00008000L
#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM_MASK                                                    0x00010000L
#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA_MASK                                                  0x00020000L
#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE_MASK                                                        0x00040000L
#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS_MASK                                                        0x00080000L
#define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS_MASK                                                         0x00100000L
#define CP_STALLED_STAT3__GCRIU_WAITING_ON_FREE_MASK                                                          0x00200000L
//CP_STALLED_STAT1
#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT                                                   0x0
#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_R0__SHIFT                                                0x2
#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_R1__SHIFT                                                0x3
#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_R0__SHIFT                                              0x4
#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_R1__SHIFT                                              0x5
#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT                                                 0xa
#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT                                                 0xb
#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT                                                  0xc
#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT                                                0xd
#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA__SHIFT                                                   0xe
#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT                                                  0xf
#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT                                                     0x17
#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT                                                    0x18
#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT                                                     0x19
#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT                                                      0x1a
#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT                                                     0x1b
#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT                                                  0x1c
#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT                                                 0x1d
#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK                                                     0x00000001L
#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_R0_MASK                                                  0x00000004L
#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_R1_MASK                                                  0x00000008L
#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_R0_MASK                                                0x00000010L
#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_R1_MASK                                                0x00000020L
#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK                                                   0x00000400L
#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK                                                   0x00000800L
#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK                                                    0x00001000L
#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK                                                  0x00002000L
#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA_MASK                                                     0x00004000L
#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK                                                    0x00008000L
#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK                                                       0x00800000L
#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK                                                      0x01000000L
#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK                                                       0x02000000L
#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK                                                        0x04000000L
#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK                                                       0x08000000L
#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK                                                    0x10000000L
#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK                                                   0x20000000L
//CP_STALLED_STAT2
#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT                                                    0x0
#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT                                                    0x1
#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT                                                   0x2
#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT                                                    0x4
#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT                                                        0x5
#define CP_STALLED_STAT2__PFP_TO_MEQ_DDID_NOT_RDY_TO_RCV__SHIFT                                               0x6
#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT                                                   0x8
#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT                                                        0x9
#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT                                                      0xa
#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT                                                     0xb
#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT                                                       0xc
#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT                                                   0xd
#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT                                                     0xe
#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT                                                  0xf
#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT                                                     0x10
#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT                                                     0x11
#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT                                                     0x12
#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT                                                 0x13
#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT                                               0x14
#define CP_STALLED_STAT2__QU_STALLED_ON_EOP_DONE_PULSE__SHIFT                                                 0x15
#define CP_STALLED_STAT2__QU_STALLED_ON_EOP_DONE_WR_CONFIRM__SHIFT                                            0x16
#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT                                                0x17
#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT                                                   0x18
#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT                                                   0x19
#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT                                                   0x1a
#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT                                                    0x1b
#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT                                                      0x1c
#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT                                              0x1d
#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT                                                   0x1e
#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT                                                    0x1f
#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK                                                      0x00000001L
#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK                                                      0x00000002L
#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK                                                     0x00000004L
#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK                                                      0x00000010L
#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK                                                          0x00000020L
#define CP_STALLED_STAT2__PFP_TO_MEQ_DDID_NOT_RDY_TO_RCV_MASK                                                 0x00000040L
#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK                                                     0x00000100L
#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK                                                          0x00000200L
#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK                                                        0x00000400L
#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK                                                       0x00000800L
#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK                                                         0x00001000L
#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK                                                     0x00002000L
#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK                                                       0x00004000L
#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK                                                    0x00008000L
#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK                                                       0x00010000L
#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK                                                       0x00020000L
#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK                                                       0x00040000L
#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK                                                   0x00080000L
#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK                                                 0x00100000L
#define CP_STALLED_STAT2__QU_STALLED_ON_EOP_DONE_PULSE_MASK                                                   0x00200000L
#define CP_STALLED_STAT2__QU_STALLED_ON_EOP_DONE_WR_CONFIRM_MASK                                              0x00400000L
#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK                                                  0x00800000L
#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK                                                     0x01000000L
#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK                                                     0x02000000L
#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK                                                     0x04000000L
#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK                                                      0x08000000L
#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK                                                        0x10000000L
#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK                                                0x20000000L
#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK                                                     0x40000000L
#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK                                                      0x80000000L
//CP_BUSY_STAT
#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT                                                                0x0
#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT                                                               0x6
#define CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT                                                              0x7
#define CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT                                                               0x8
#define CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT                                                                    0x9
#define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT                                                                     0xa
#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY__SHIFT                                                            0xc
#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING__SHIFT                                                           0xd
#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT                                                             0xe
#define CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT                                                                 0xf
#define CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT                                                                   0x11
#define CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT                                                                    0x12
#define CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT                                                                    0x13
#define CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT                                                                  0x14
#define CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT                                                                     0x15
#define CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT                                                               0x16
#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK                                                                  0x00000001L
#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK                                                                 0x00000040L
#define CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK                                                                0x00000080L
#define CP_BUSY_STAT__ME_PARSING_PACKETS_MASK                                                                 0x00000100L
#define CP_BUSY_STAT__RCIU_PFP_BUSY_MASK                                                                      0x00000200L
#define CP_BUSY_STAT__RCIU_ME_BUSY_MASK                                                                       0x00000400L
#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY_MASK                                                              0x00001000L
#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING_MASK                                                             0x00002000L
#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS_MASK                                                               0x00004000L
#define CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK                                                                   0x00008000L
#define CP_BUSY_STAT__ME_PARSER_BUSY_MASK                                                                     0x00020000L
#define CP_BUSY_STAT__EOP_DONE_BUSY_MASK                                                                      0x00040000L
#define CP_BUSY_STAT__STRM_OUT_BUSY_MASK                                                                      0x00080000L
#define CP_BUSY_STAT__PIPE_STATS_BUSY_MASK                                                                    0x00100000L
#define CP_BUSY_STAT__RCIU_CE_BUSY_MASK                                                                       0x00200000L
#define CP_BUSY_STAT__CE_PARSING_PACKETS_MASK                                                                 0x00400000L
//CP_STAT
#define CP_STAT__ROQ_DB_BUSY__SHIFT                                                                           0x5
#define CP_STAT__ROQ_CE_DB_BUSY__SHIFT                                                                        0x6
#define CP_STAT__ROQ_RING_BUSY__SHIFT                                                                         0x9
#define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT                                                                    0xa
#define CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT                                                                    0xb
#define CP_STAT__ROQ_STATE_BUSY__SHIFT                                                                        0xc
#define CP_STAT__DC_BUSY__SHIFT                                                                               0xd
#define CP_STAT__UTCL2IU_BUSY__SHIFT                                                                          0xe
#define CP_STAT__PFP_BUSY__SHIFT                                                                              0xf
#define CP_STAT__MEQ_BUSY__SHIFT                                                                              0x10
#define CP_STAT__ME_BUSY__SHIFT                                                                               0x11
#define CP_STAT__QUERY_BUSY__SHIFT                                                                            0x12
#define CP_STAT__SEMAPHORE_BUSY__SHIFT                                                                        0x13
#define CP_STAT__INTERRUPT_BUSY__SHIFT                                                                        0x14
#define CP_STAT__SURFACE_SYNC_BUSY__SHIFT                                                                     0x15
#define CP_STAT__DMA_BUSY__SHIFT                                                                              0x16
#define CP_STAT__RCIU_BUSY__SHIFT                                                                             0x17
#define CP_STAT__SCRATCH_RAM_BUSY__SHIFT                                                                      0x18
#define CP_STAT__GCRIU_BUSY__SHIFT                                                                            0x19
#define CP_STAT__CE_BUSY__SHIFT                                                                               0x1a
#define CP_STAT__TCIU_BUSY__SHIFT                                                                             0x1b
#define CP_STAT__ROQ_CE_RING_BUSY__SHIFT                                                                      0x1c
#define CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT                                                                 0x1d
#define CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT                                                                 0x1e
#define CP_STAT__CP_BUSY__SHIFT                                                                               0x1f
#define CP_STAT__ROQ_DB_BUSY_MASK                                                                             0x00000020L
#define CP_STAT__ROQ_CE_DB_BUSY_MASK                                                                          0x00000040L
#define CP_STAT__ROQ_RING_BUSY_MASK                                                                           0x00000200L
#define CP_STAT__ROQ_INDIRECT1_BUSY_MASK                                                                      0x00000400L
#define CP_STAT__ROQ_INDIRECT2_BUSY_MASK                                                                      0x00000800L
#define CP_STAT__ROQ_STATE_BUSY_MASK                                                                          0x00001000L
#define CP_STAT__DC_BUSY_MASK                                                                                 0x00002000L
#define CP_STAT__UTCL2IU_BUSY_MASK                                                                            0x00004000L
#define CP_STAT__PFP_BUSY_MASK                                                                                0x00008000L
#define CP_STAT__MEQ_BUSY_MASK                                                                                0x00010000L
#define CP_STAT__ME_BUSY_MASK                                                                                 0x00020000L
#define CP_STAT__QUERY_BUSY_MASK                                                                              0x00040000L
#define CP_STAT__SEMAPHORE_BUSY_MASK                                                                          0x00080000L
#define CP_STAT__INTERRUPT_BUSY_MASK                                                                          0x00100000L
#define CP_STAT__SURFACE_SYNC_BUSY_MASK                                                                       0x00200000L
#define CP_STAT__DMA_BUSY_MASK                                                                                0x00400000L
#define CP_STAT__RCIU_BUSY_MASK                                                                               0x00800000L
#define CP_STAT__SCRATCH_RAM_BUSY_MASK                                                                        0x01000000L
#define CP_STAT__GCRIU_BUSY_MASK                                                                              0x02000000L
#define CP_STAT__CE_BUSY_MASK                                                                                 0x04000000L
#define CP_STAT__TCIU_BUSY_MASK                                                                               0x08000000L
#define CP_STAT__ROQ_CE_RING_BUSY_MASK                                                                        0x10000000L
#define CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK                                                                   0x20000000L
#define CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK                                                                   0x40000000L
#define CP_STAT__CP_BUSY_MASK                                                                                 0x80000000L
//CP_ME_HEADER_DUMP
#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP__SHIFT                                                              0x0
#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP_MASK                                                                0xFFFFFFFFL
//CP_PFP_HEADER_DUMP
#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP__SHIFT                                                            0x0
#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP_MASK                                                              0xFFFFFFFFL
//CP_GRBM_FREE_COUNT
#define CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT                                                                 0x0
#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS__SHIFT                                                             0x8
#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT                                                             0x10
#define CP_GRBM_FREE_COUNT__FREE_COUNT_MASK                                                                   0x0000003FL
#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS_MASK                                                               0x00003F00L
#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK                                                               0x003F0000L
//CP_CE_HEADER_DUMP
#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP__SHIFT                                                              0x0
#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP_MASK                                                                0xFFFFFFFFL
//CP_PFP_INSTR_PNTR
#define CP_PFP_INSTR_PNTR__INSTR_PNTR__SHIFT                                                                  0x0
#define CP_PFP_INSTR_PNTR__INSTR_PNTR_MASK                                                                    0x0000FFFFL
//CP_ME_INSTR_PNTR
#define CP_ME_INSTR_PNTR__INSTR_PNTR__SHIFT                                                                   0x0
#define CP_ME_INSTR_PNTR__INSTR_PNTR_MASK                                                                     0x0000FFFFL
//CP_CE_INSTR_PNTR
#define CP_CE_INSTR_PNTR__INSTR_PNTR__SHIFT                                                                   0x0
#define CP_CE_INSTR_PNTR__INSTR_PNTR_MASK                                                                     0x0000FFFFL
//CP_MEC1_INSTR_PNTR
#define CP_MEC1_INSTR_PNTR__INSTR_PNTR__SHIFT                                                                 0x0
#define CP_MEC1_INSTR_PNTR__INSTR_PNTR_MASK                                                                   0x0000FFFFL
//CP_MEC2_INSTR_PNTR
#define CP_MEC2_INSTR_PNTR__INSTR_PNTR__SHIFT                                                                 0x0
#define CP_MEC2_INSTR_PNTR__INSTR_PNTR_MASK                                                                   0x0000FFFFL
//CP_CSF_STAT
#define CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT                                                              0x8
#define CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK                                                                0x0001FF00L
//CP_MEC_CNTL
#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET__SHIFT                                                               0x10
#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET__SHIFT                                                               0x11
#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET__SHIFT                                                               0x12
#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET__SHIFT                                                               0x13
#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET__SHIFT                                                               0x14
#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET__SHIFT                                                               0x15
#define CP_MEC_CNTL__MEC_ME2_PIPE2_RESET__SHIFT                                                               0x16
#define CP_MEC_CNTL__MEC_ME2_PIPE3_RESET__SHIFT                                                               0x17
#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE__SHIFT                                                             0x1b
#define CP_MEC_CNTL__MEC_ME2_HALT__SHIFT                                                                      0x1c
#define CP_MEC_CNTL__MEC_ME2_STEP__SHIFT                                                                      0x1d
#define CP_MEC_CNTL__MEC_ME1_HALT__SHIFT                                                                      0x1e
#define CP_MEC_CNTL__MEC_ME1_STEP__SHIFT                                                                      0x1f
#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK                                                                 0x00010000L
#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK                                                                 0x00020000L
#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK                                                                 0x00040000L
#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK                                                                 0x00080000L
#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK                                                                 0x00100000L
#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK                                                                 0x00200000L
#define CP_MEC_CNTL__MEC_ME2_PIPE2_RESET_MASK                                                                 0x00400000L
#define CP_MEC_CNTL__MEC_ME2_PIPE3_RESET_MASK                                                                 0x00800000L
#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK                                                               0x08000000L
#define CP_MEC_CNTL__MEC_ME2_HALT_MASK                                                                        0x10000000L
#define CP_MEC_CNTL__MEC_ME2_STEP_MASK                                                                        0x20000000L
#define CP_MEC_CNTL__MEC_ME1_HALT_MASK                                                                        0x40000000L
#define CP_MEC_CNTL__MEC_ME1_STEP_MASK                                                                        0x80000000L
//CP_ME_CNTL
#define CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT                                                               0x4
#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT                                                              0x6
#define CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT                                                               0x8
#define CP_ME_CNTL__CE_PIPE0_RESET__SHIFT                                                                     0x10
#define CP_ME_CNTL__CE_PIPE1_RESET__SHIFT                                                                     0x11
#define CP_ME_CNTL__PFP_PIPE0_RESET__SHIFT                                                                    0x12
#define CP_ME_CNTL__PFP_PIPE1_RESET__SHIFT                                                                    0x13
#define CP_ME_CNTL__ME_PIPE0_RESET__SHIFT                                                                     0x14
#define CP_ME_CNTL__ME_PIPE1_RESET__SHIFT                                                                     0x15
#define CP_ME_CNTL__CE_HALT__SHIFT                                                                            0x18
#define CP_ME_CNTL__CE_STEP__SHIFT                                                                            0x19
#define CP_ME_CNTL__PFP_HALT__SHIFT                                                                           0x1a
#define CP_ME_CNTL__PFP_STEP__SHIFT                                                                           0x1b
#define CP_ME_CNTL__ME_HALT__SHIFT                                                                            0x1c
#define CP_ME_CNTL__ME_STEP__SHIFT                                                                            0x1d
#define CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK                                                                 0x00000010L
#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK                                                                0x00000040L
#define CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK                                                                 0x00000100L
#define CP_ME_CNTL__CE_PIPE0_RESET_MASK                                                                       0x00010000L
#define CP_ME_CNTL__CE_PIPE1_RESET_MASK                                                                       0x00020000L
#define CP_ME_CNTL__PFP_PIPE0_RESET_MASK                                                                      0x00040000L
#define CP_ME_CNTL__PFP_PIPE1_RESET_MASK                                                                      0x00080000L
#define CP_ME_CNTL__ME_PIPE0_RESET_MASK                                                                       0x00100000L
#define CP_ME_CNTL__ME_PIPE1_RESET_MASK                                                                       0x00200000L
#define CP_ME_CNTL__CE_HALT_MASK                                                                              0x01000000L
#define CP_ME_CNTL__CE_STEP_MASK                                                                              0x02000000L
#define CP_ME_CNTL__PFP_HALT_MASK                                                                             0x04000000L
#define CP_ME_CNTL__PFP_STEP_MASK                                                                             0x08000000L
#define CP_ME_CNTL__ME_HALT_MASK                                                                              0x10000000L
#define CP_ME_CNTL__ME_STEP_MASK                                                                              0x20000000L
//CP_CNTX_STAT
#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT                                                             0x0
#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT                                                             0x8
#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT                                                              0x14
#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT                                                              0x1c
#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK                                                               0x000000FFL
#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK                                                               0x00000700L
#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK                                                                0x0FF00000L
#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK                                                                0x70000000L
//CP_ME_PREEMPTION
#define CP_ME_PREEMPTION__OBSOLETE__SHIFT                                                                     0x0
#define CP_ME_PREEMPTION__OBSOLETE_MASK                                                                       0x00000001L
//CP_ROQ_THRESHOLDS
#define CP_ROQ_THRESHOLDS__IB1_START__SHIFT                                                                   0x0
#define CP_ROQ_THRESHOLDS__IB2_START__SHIFT                                                                   0x8
#define CP_ROQ_THRESHOLDS__IB1_START_MASK                                                                     0x000000FFL
#define CP_ROQ_THRESHOLDS__IB2_START_MASK                                                                     0x0000FF00L
//CP_MEQ_STQ_THRESHOLD
#define CP_MEQ_STQ_THRESHOLD__STQ_START__SHIFT                                                                0x0
#define CP_MEQ_STQ_THRESHOLD__STQ_START_MASK                                                                  0x000000FFL
//CP_RB2_RPTR
#define CP_RB2_RPTR__RB_RPTR__SHIFT                                                                           0x0
#define CP_RB2_RPTR__RB_RPTR_MASK                                                                             0x000FFFFFL
//CP_RB1_RPTR
#define CP_RB1_RPTR__RB_RPTR__SHIFT                                                                           0x0
#define CP_RB1_RPTR__RB_RPTR_MASK                                                                             0x000FFFFFL
//CP_RB0_RPTR
#define CP_RB0_RPTR__RB_RPTR__SHIFT                                                                           0x0
#define CP_RB0_RPTR__RB_RPTR_MASK                                                                             0x000FFFFFL
//CP_RB_RPTR
#define CP_RB_RPTR__RB_RPTR__SHIFT                                                                            0x0
#define CP_RB_RPTR__RB_RPTR_MASK                                                                              0x000FFFFFL
//CP_RB_WPTR_DELAY
#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT                                                              0x0
#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT                                                              0x1c
#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK                                                                0x0FFFFFFFL
#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK                                                                0xF0000000L
//CP_RB_WPTR_POLL_CNTL
#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT                                                           0x0
#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                          0x10
#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK                                                             0x0000FFFFL
#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                            0xFFFF0000L
//CP_ROQ1_THRESHOLDS
#define CP_ROQ1_THRESHOLDS__RB1_START__SHIFT                                                                  0x0
#define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT                                                               0xa
#define CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT                                                               0x14
#define CP_ROQ1_THRESHOLDS__RB1_START_MASK                                                                    0x000003FFL
#define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK                                                                 0x000FFC00L
#define CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK                                                                 0x3FF00000L
//CP_ROQ2_THRESHOLDS
#define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT                                                               0x0
#define CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT                                                               0xa
#define CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK                                                                 0x000003FFL
#define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK                                                                 0x000FFC00L
//CP_STQ_THRESHOLDS
#define CP_STQ_THRESHOLDS__STQ0_START__SHIFT                                                                  0x0
#define CP_STQ_THRESHOLDS__STQ1_START__SHIFT                                                                  0x8
#define CP_STQ_THRESHOLDS__STQ2_START__SHIFT                                                                  0x10
#define CP_STQ_THRESHOLDS__STQ0_START_MASK                                                                    0x000000FFL
#define CP_STQ_THRESHOLDS__STQ1_START_MASK                                                                    0x0000FF00L
#define CP_STQ_THRESHOLDS__STQ2_START_MASK                                                                    0x00FF0000L
//CP_QUEUE_THRESHOLDS
#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT                                                             0x0
#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT                                                             0x8
#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK                                                               0x0000003FL
#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK                                                               0x00003F00L
//CP_MEQ_THRESHOLDS
#define CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT                                                                  0x0
#define CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT                                                                  0x8
#define CP_MEQ_THRESHOLDS__MEQ1_START_MASK                                                                    0x000000FFL
#define CP_MEQ_THRESHOLDS__MEQ2_START_MASK                                                                    0x0000FF00L
//CP_ROQ_AVAIL
#define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT                                                                     0x0
#define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT                                                                      0x10
#define CP_ROQ_AVAIL__ROQ_CNT_RING_MASK                                                                       0x00000FFFL
#define CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK                                                                        0x0FFF0000L
//CP_STQ_AVAIL
#define CP_STQ_AVAIL__STQ_CNT__SHIFT                                                                          0x0
#define CP_STQ_AVAIL__STQ_CNT_MASK                                                                            0x000001FFL
//CP_ROQ2_AVAIL
#define CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT                                                                     0x0
#define CP_ROQ2_AVAIL__ROQ_CNT_DB__SHIFT                                                                      0x10
#define CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK                                                                       0x00000FFFL
#define CP_ROQ2_AVAIL__ROQ_CNT_DB_MASK                                                                        0x0FFF0000L
//CP_MEQ_AVAIL
#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT                                                                          0x0
#define CP_MEQ_AVAIL__MEQ_CNT_MASK                                                                            0x000003FFL
//CP_CMD_INDEX
#define CP_CMD_INDEX__CMD_INDEX__SHIFT                                                                        0x0
#define CP_CMD_INDEX__CMD_ME_SEL__SHIFT                                                                       0xc
#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT                                                                    0x10
#define CP_CMD_INDEX__CMD_INDEX_MASK                                                                          0x000007FFL
#define CP_CMD_INDEX__CMD_ME_SEL_MASK                                                                         0x00003000L
#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK                                                                      0x00070000L
//CP_CMD_DATA
#define CP_CMD_DATA__CMD_DATA__SHIFT                                                                          0x0
#define CP_CMD_DATA__CMD_DATA_MASK                                                                            0xFFFFFFFFL
//CP_ROQ_RB_STAT
#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT                                                               0x0
#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT                                                               0x10
#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK                                                                 0x00000FFFL
#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK                                                                 0x0FFF0000L
//CP_ROQ_IB1_STAT
#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT                                                            0x0
#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT                                                            0x10
#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK                                                              0x00000FFFL
#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK                                                              0x0FFF0000L
//CP_ROQ_IB2_STAT
#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT                                                            0x0
#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT                                                            0x10
#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK                                                              0x00000FFFL
#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK                                                              0x0FFF0000L
//CP_STQ_STAT
#define CP_STQ_STAT__STQ_RPTR__SHIFT                                                                          0x0
#define CP_STQ_STAT__STQ_RPTR_MASK                                                                            0x000003FFL
//CP_STQ_WR_STAT
#define CP_STQ_WR_STAT__STQ_WPTR__SHIFT                                                                       0x0
#define CP_STQ_WR_STAT__STQ_WPTR_MASK                                                                         0x000003FFL
//CP_MEQ_STAT
#define CP_MEQ_STAT__MEQ_RPTR__SHIFT                                                                          0x0
#define CP_MEQ_STAT__MEQ_WPTR__SHIFT                                                                          0x10
#define CP_MEQ_STAT__MEQ_RPTR_MASK                                                                            0x000003FFL
#define CP_MEQ_STAT__MEQ_WPTR_MASK                                                                            0x03FF0000L
//CP_CEQ1_AVAIL
#define CP_CEQ1_AVAIL__CEQ_CNT_RING__SHIFT                                                                    0x0
#define CP_CEQ1_AVAIL__CEQ_CNT_IB1__SHIFT                                                                     0x10
#define CP_CEQ1_AVAIL__CEQ_CNT_RING_MASK                                                                      0x00000FFFL
#define CP_CEQ1_AVAIL__CEQ_CNT_IB1_MASK                                                                       0x0FFF0000L
//CP_CEQ2_AVAIL
#define CP_CEQ2_AVAIL__CEQ_CNT_IB2__SHIFT                                                                     0x0
#define CP_CEQ2_AVAIL__CEQ_CNT_DB__SHIFT                                                                      0x10
#define CP_CEQ2_AVAIL__CEQ_CNT_IB2_MASK                                                                       0x00000FFFL
#define CP_CEQ2_AVAIL__CEQ_CNT_DB_MASK                                                                        0x0FFF0000L
//CP_CE_ROQ_RB_STAT
#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT                                                            0x0
#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT                                                            0x10
#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY_MASK                                                              0x00000FFFL
#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK                                                              0x0FFF0000L
//CP_CE_ROQ_IB1_STAT
#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1__SHIFT                                                         0x0
#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT                                                         0x10
#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1_MASK                                                           0x00000FFFL
#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1_MASK                                                           0x0FFF0000L
//CP_CE_ROQ_IB2_STAT
#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2__SHIFT                                                         0x0
#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2__SHIFT                                                         0x10
#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2_MASK                                                           0x00000FFFL
#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2_MASK                                                           0x0FFF0000L
//CP_CE_ROQ_DB_STAT
#define CP_CE_ROQ_DB_STAT__CEQ_RPTR_DB__SHIFT                                                                 0x0
#define CP_CE_ROQ_DB_STAT__CEQ_WPTR_DB__SHIFT                                                                 0x10
#define CP_CE_ROQ_DB_STAT__CEQ_RPTR_DB_MASK                                                                   0x00000FFFL
#define CP_CE_ROQ_DB_STAT__CEQ_WPTR_DB_MASK                                                                   0x0FFF0000L
//CP_ROQ3_THRESHOLDS
#define CP_ROQ3_THRESHOLDS__R0_DB_START__SHIFT                                                                0x0
#define CP_ROQ3_THRESHOLDS__R1_DB_START__SHIFT                                                                0xa
#define CP_ROQ3_THRESHOLDS__R0_DB_START_MASK                                                                  0x000003FFL
#define CP_ROQ3_THRESHOLDS__R1_DB_START_MASK                                                                  0x000FFC00L
//CP_ROQ_DB_STAT
#define CP_ROQ_DB_STAT__ROQ_RPTR_DB__SHIFT                                                                    0x0
#define CP_ROQ_DB_STAT__ROQ_WPTR_DB__SHIFT                                                                    0x10
#define CP_ROQ_DB_STAT__ROQ_RPTR_DB_MASK                                                                      0x00000FFFL
#define CP_ROQ_DB_STAT__ROQ_WPTR_DB_MASK                                                                      0x0FFF0000L
#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED__SHIFT                                                     0x16
#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT                                                       0x17
#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED_MASK                                                       0x00400000L
#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK                                                         0x00800000L
//CP_PRIV_VIOLATION_ADDR
#define CP_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR__SHIFT                                                    0x0
#define CP_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR_MASK                                                      0x0000FFFFL


// addressBlock: gc_padec
//VGT_CACHE_INVALIDATION
#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT                                                     0x0
#define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT__SHIFT                                                     0x4
#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER__SHIFT                                                     0x5
#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT                                                          0x6
#define VGT_CACHE_INVALIDATION__USE_GS_DONE__SHIFT                                                            0x9
#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD__SHIFT                                                   0xb
#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN__SHIFT                                                       0xc
#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH__SHIFT                                                   0xd
#define VGT_CACHE_INVALIDATION__ES_LIMIT__SHIFT                                                               0x10
#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG__SHIFT                                                       0x15
#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_1__SHIFT                                                        0x16
#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_2__SHIFT                                                        0x19
#define VGT_CACHE_INVALIDATION__EN_WAVE_MERGE__SHIFT                                                          0x1c
#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_EOI__SHIFT                                                   0x1d
#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION_MASK                                                       0x00000003L
#define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT_MASK                                                       0x00000010L
#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER_MASK                                                       0x00000020L
#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN_MASK                                                            0x000000C0L
#define VGT_CACHE_INVALIDATION__USE_GS_DONE_MASK                                                              0x00000200L
#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD_MASK                                                     0x00000800L
#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN_MASK                                                         0x00001000L
#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH_MASK                                                     0x00002000L
#define VGT_CACHE_INVALIDATION__ES_LIMIT_MASK                                                                 0x001F0000L
#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_MASK                                                         0x00200000L
#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_1_MASK                                                          0x01C00000L
#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_2_MASK                                                          0x0E000000L
#define VGT_CACHE_INVALIDATION__EN_WAVE_MERGE_MASK                                                            0x10000000L
#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_EOI_MASK                                                     0x20000000L
//VGT_ESGS_RING_SIZE
#define VGT_ESGS_RING_SIZE__MEM_SIZE__SHIFT                                                                   0x0
#define VGT_ESGS_RING_SIZE__MEM_SIZE_MASK                                                                     0xFFFFFFFFL
//VGT_GSVS_RING_SIZE
#define VGT_GSVS_RING_SIZE__MEM_SIZE__SHIFT                                                                   0x0
#define VGT_GSVS_RING_SIZE__MEM_SIZE_MASK                                                                     0xFFFFFFFFL
//VGT_TF_RING_SIZE
#define VGT_TF_RING_SIZE__SIZE__SHIFT                                                                         0x0
#define VGT_TF_RING_SIZE__SIZE_MASK                                                                           0x0000FFFFL
//VGT_HS_OFFCHIP_PARAM
#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING__SHIFT                                                        0x0
#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY__SHIFT                                                      0xa
#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING_MASK                                                          0x000003FFL
#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY_MASK                                                        0x00000C00L
//VGT_TF_MEMORY_BASE
#define VGT_TF_MEMORY_BASE__BASE__SHIFT                                                                       0x0
#define VGT_TF_MEMORY_BASE__BASE_MASK                                                                         0xFFFFFFFFL
//VGT_TF_MEMORY_BASE_HI
#define VGT_TF_MEMORY_BASE_HI__BASE_HI__SHIFT                                                                 0x0
#define VGT_TF_MEMORY_BASE_HI__BASE_HI_MASK                                                                   0x000000FFL
//VGT_VTX_VECT_EJECT_REG
#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT                                                             0x0
#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK                                                               0x000003FFL
//VGT_DMA_DATA_FIFO_DEPTH
#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH__SHIFT                                                   0x0
#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH_MASK                                                     0x000003FFL
//VGT_DMA_REQ_FIFO_DEPTH
#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH__SHIFT                                                     0x0
#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH_MASK                                                       0x0000003FL
//VGT_DRAW_INIT_FIFO_DEPTH
#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH__SHIFT                                                 0x0
#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH_MASK                                                   0x0000003FL
//VGT_LAST_COPY_STATE
#define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT                                                              0x0
#define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT                                                              0x10
#define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK                                                                0x00000007L
#define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK                                                                0x00070000L
//VGT_FIFO_DEPTHS
#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH__SHIFT                                                          0x0
#define VGT_FIFO_DEPTHS__RESERVED_0__SHIFT                                                                    0x7
#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH__SHIFT                                                              0x8
#define VGT_FIFO_DEPTHS__RESERVED_1__SHIFT                                                                    0x16
#define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH__SHIFT                                                            0x17
#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH_MASK                                                            0x0000007FL
#define VGT_FIFO_DEPTHS__RESERVED_0_MASK                                                                      0x00000080L
#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH_MASK                                                                0x003FFF00L
#define VGT_FIFO_DEPTHS__RESERVED_1_MASK                                                                      0x00400000L
#define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH_MASK                                                              0x1F800000L
//VGT_GS_VERTEX_REUSE
#define VGT_GS_VERTEX_REUSE__VERT_REUSE__SHIFT                                                                0x0
#define VGT_GS_VERTEX_REUSE__VERT_REUSE_MASK                                                                  0x0000001FL
//VGT_MC_LAT_CNTL
#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES__SHIFT                                                             0x0
#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES_MASK                                                               0x0000000FL
//IA_UTCL1_STATUS_2
#define IA_UTCL1_STATUS_2__IA_BUSY__SHIFT                                                                     0x0
#define IA_UTCL1_STATUS_2__IA_DMA_BUSY__SHIFT                                                                 0x1
#define IA_UTCL1_STATUS_2__IA_DMA_REQ_BUSY__SHIFT                                                             0x2
#define IA_UTCL1_STATUS_2__IA_GRP_BUSY__SHIFT                                                                 0x3
#define IA_UTCL1_STATUS_2__IA_ADC_BUSY__SHIFT                                                                 0x4
#define IA_UTCL1_STATUS_2__FAULT_DETECTED__SHIFT                                                              0x5
#define IA_UTCL1_STATUS_2__RETRY_DETECTED__SHIFT                                                              0x6
#define IA_UTCL1_STATUS_2__PRT_DETECTED__SHIFT                                                                0x7
#define IA_UTCL1_STATUS_2__FAULT_UTCL1ID__SHIFT                                                               0x8
#define IA_UTCL1_STATUS_2__RETRY_UTCL1ID__SHIFT                                                               0x10
#define IA_UTCL1_STATUS_2__PRT_UTCL1ID__SHIFT                                                                 0x18
#define IA_UTCL1_STATUS_2__IA_BUSY_MASK                                                                       0x00000001L
#define IA_UTCL1_STATUS_2__IA_DMA_BUSY_MASK                                                                   0x00000002L
#define IA_UTCL1_STATUS_2__IA_DMA_REQ_BUSY_MASK                                                               0x00000004L
#define IA_UTCL1_STATUS_2__IA_GRP_BUSY_MASK                                                                   0x00000008L
#define IA_UTCL1_STATUS_2__IA_ADC_BUSY_MASK                                                                   0x00000010L
#define IA_UTCL1_STATUS_2__FAULT_DETECTED_MASK                                                                0x00000020L
#define IA_UTCL1_STATUS_2__RETRY_DETECTED_MASK                                                                0x00000040L
#define IA_UTCL1_STATUS_2__PRT_DETECTED_MASK                                                                  0x00000080L
#define IA_UTCL1_STATUS_2__FAULT_UTCL1ID_MASK                                                                 0x00003F00L
#define IA_UTCL1_STATUS_2__RETRY_UTCL1ID_MASK                                                                 0x003F0000L
#define IA_UTCL1_STATUS_2__PRT_UTCL1ID_MASK                                                                   0x3F000000L
//WD_CNTL_STATUS
#define WD_CNTL_STATUS__VR3_BUSY__SHIFT                                                                       0x0
#define WD_CNTL_STATUS__VR2_BUSY__SHIFT                                                                       0x1
#define WD_CNTL_STATUS__VR1_BUSY__SHIFT                                                                       0x2
#define WD_CNTL_STATUS__VR0_BUSY__SHIFT                                                                       0x3
#define WD_CNTL_STATUS__HS3_BUSY__SHIFT                                                                       0x4
#define WD_CNTL_STATUS__HS2_BUSY__SHIFT                                                                       0x5
#define WD_CNTL_STATUS__HS1_BUSY__SHIFT                                                                       0x6
#define WD_CNTL_STATUS__HS0_BUSY__SHIFT                                                                       0x7
#define WD_CNTL_STATUS__GS3_BUSY__SHIFT                                                                       0x8
#define WD_CNTL_STATUS__GS2_BUSY__SHIFT                                                                       0x9
#define WD_CNTL_STATUS__GS1_BUSY__SHIFT                                                                       0xa
#define WD_CNTL_STATUS__GS0_BUSY__SHIFT                                                                       0xb
#define WD_CNTL_STATUS__NGG3_BUSY__SHIFT                                                                      0xc
#define WD_CNTL_STATUS__NGG2_BUSY__SHIFT                                                                      0xd
#define WD_CNTL_STATUS__NGG1_BUSY__SHIFT                                                                      0xe
#define WD_CNTL_STATUS__NGG0_BUSY__SHIFT                                                                      0xf
#define WD_CNTL_STATUS__DIST_BUSY__SHIFT                                                                      0x10
#define WD_CNTL_STATUS__DIST_BE_BUSY__SHIFT                                                                   0x11
#define WD_CNTL_STATUS__WD_TE11_BUSY__SHIFT                                                                   0x12
#define WD_CNTL_STATUS__SA3_OUTPUT_BLOCK_BUSY__SHIFT                                                          0x13
#define WD_CNTL_STATUS__SA2_OUTPUT_BLOCK_BUSY__SHIFT                                                          0x14
#define WD_CNTL_STATUS__SA1_OUTPUT_BLOCK_BUSY__SHIFT                                                          0x15
#define WD_CNTL_STATUS__SA0_OUTPUT_BLOCK_BUSY__SHIFT                                                          0x16
#define WD_CNTL_STATUS__GE_UTCL1_BUSY__SHIFT                                                                  0x17
#define WD_CNTL_STATUS__TE3_BUSY__SHIFT                                                                       0x18
#define WD_CNTL_STATUS__TE2_BUSY__SHIFT                                                                       0x19
#define WD_CNTL_STATUS__TE1_BUSY__SHIFT                                                                       0x1a
#define WD_CNTL_STATUS__TE0_BUSY__SHIFT                                                                       0x1b
#define WD_CNTL_STATUS__WLC_BUSY__SHIFT                                                                       0x1c
#define WD_CNTL_STATUS__PC_MANAGER_BUSY__SHIFT                                                                0x1d
#define WD_CNTL_STATUS__VR3_BUSY_MASK                                                                         0x00000001L
#define WD_CNTL_STATUS__VR2_BUSY_MASK                                                                         0x00000002L
#define WD_CNTL_STATUS__VR1_BUSY_MASK                                                                         0x00000004L
#define WD_CNTL_STATUS__VR0_BUSY_MASK                                                                         0x00000008L
#define WD_CNTL_STATUS__HS3_BUSY_MASK                                                                         0x00000010L
#define WD_CNTL_STATUS__HS2_BUSY_MASK                                                                         0x00000020L
#define WD_CNTL_STATUS__HS1_BUSY_MASK                                                                         0x00000040L
#define WD_CNTL_STATUS__HS0_BUSY_MASK                                                                         0x00000080L
#define WD_CNTL_STATUS__GS3_BUSY_MASK                                                                         0x00000100L
#define WD_CNTL_STATUS__GS2_BUSY_MASK                                                                         0x00000200L
#define WD_CNTL_STATUS__GS1_BUSY_MASK                                                                         0x00000400L
#define WD_CNTL_STATUS__GS0_BUSY_MASK                                                                         0x00000800L
#define WD_CNTL_STATUS__NGG3_BUSY_MASK                                                                        0x00001000L
#define WD_CNTL_STATUS__NGG2_BUSY_MASK                                                                        0x00002000L
#define WD_CNTL_STATUS__NGG1_BUSY_MASK                                                                        0x00004000L
#define WD_CNTL_STATUS__NGG0_BUSY_MASK                                                                        0x00008000L
#define WD_CNTL_STATUS__DIST_BUSY_MASK                                                                        0x00010000L
#define WD_CNTL_STATUS__DIST_BE_BUSY_MASK                                                                     0x00020000L
#define WD_CNTL_STATUS__WD_TE11_BUSY_MASK                                                                     0x00040000L
#define WD_CNTL_STATUS__SA3_OUTPUT_BLOCK_BUSY_MASK                                                            0x00080000L
#define WD_CNTL_STATUS__SA2_OUTPUT_BLOCK_BUSY_MASK                                                            0x00100000L
#define WD_CNTL_STATUS__SA1_OUTPUT_BLOCK_BUSY_MASK                                                            0x00200000L
#define WD_CNTL_STATUS__SA0_OUTPUT_BLOCK_BUSY_MASK                                                            0x00400000L
#define WD_CNTL_STATUS__GE_UTCL1_BUSY_MASK                                                                    0x00800000L
#define WD_CNTL_STATUS__TE3_BUSY_MASK                                                                         0x01000000L
#define WD_CNTL_STATUS__TE2_BUSY_MASK                                                                         0x02000000L
#define WD_CNTL_STATUS__TE1_BUSY_MASK                                                                         0x04000000L
#define WD_CNTL_STATUS__TE0_BUSY_MASK                                                                         0x08000000L
#define WD_CNTL_STATUS__WLC_BUSY_MASK                                                                         0x10000000L
#define WD_CNTL_STATUS__PC_MANAGER_BUSY_MASK                                                                  0x20000000L
//CC_GC_PRIM_CONFIG
#define CC_GC_PRIM_CONFIG__INACTIVE_PA__SHIFT                                                                 0x4
#define CC_GC_PRIM_CONFIG__INACTIVE_PA_MASK                                                                   0x000FFFF0L
//GC_USER_PRIM_CONFIG
#define GC_USER_PRIM_CONFIG__INACTIVE_PA__SHIFT                                                               0x4
#define GC_USER_PRIM_CONFIG__INACTIVE_PA_MASK                                                                 0x000FFFF0L
//WD_QOS
#define WD_QOS__DRAW_STALL__SHIFT                                                                             0x0
#define WD_QOS__DRAW_STALL_MASK                                                                               0x00000001L
//WD_UTCL1_CNTL
#define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT                                                            0x0
#define WD_UTCL1_CNTL__VMID_RESET_MODE__SHIFT                                                                 0x17
#define WD_UTCL1_CNTL__DROP_MODE__SHIFT                                                                       0x18
#define WD_UTCL1_CNTL__BYPASS__SHIFT                                                                          0x19
#define WD_UTCL1_CNTL__INVALIDATE__SHIFT                                                                      0x1a
#define WD_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT                                                                 0x1b
#define WD_UTCL1_CNTL__FORCE_SNOOP__SHIFT                                                                     0x1c
#define WD_UTCL1_CNTL__MTYPE_OVERRIDE__SHIFT                                                                  0x1d
#define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK                                                              0x000FFFFFL
#define WD_UTCL1_CNTL__VMID_RESET_MODE_MASK                                                                   0x00800000L
#define WD_UTCL1_CNTL__DROP_MODE_MASK                                                                         0x01000000L
#define WD_UTCL1_CNTL__BYPASS_MASK                                                                            0x02000000L
#define WD_UTCL1_CNTL__INVALIDATE_MASK                                                                        0x04000000L
#define WD_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK                                                                   0x08000000L
#define WD_UTCL1_CNTL__FORCE_SNOOP_MASK                                                                       0x10000000L
#define WD_UTCL1_CNTL__MTYPE_OVERRIDE_MASK                                                                    0x20000000L
//WD_UTCL1_STATUS
#define WD_UTCL1_STATUS__FAULT_DETECTED__SHIFT                                                                0x0
#define WD_UTCL1_STATUS__RETRY_DETECTED__SHIFT                                                                0x1
#define WD_UTCL1_STATUS__PRT_DETECTED__SHIFT                                                                  0x2
#define WD_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT                                                                 0x8
#define WD_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT                                                                 0x10
#define WD_UTCL1_STATUS__PRT_UTCL1ID__SHIFT                                                                   0x18
#define WD_UTCL1_STATUS__FAULT_DETECTED_MASK                                                                  0x00000001L
#define WD_UTCL1_STATUS__RETRY_DETECTED_MASK                                                                  0x00000002L
#define WD_UTCL1_STATUS__PRT_DETECTED_MASK                                                                    0x00000004L
#define WD_UTCL1_STATUS__FAULT_UTCL1ID_MASK                                                                   0x00003F00L
#define WD_UTCL1_STATUS__RETRY_UTCL1ID_MASK                                                                   0x003F0000L
#define WD_UTCL1_STATUS__PRT_UTCL1ID_MASK                                                                     0x3F000000L
//GE_PC_CNTL
#define GE_PC_CNTL__PC_SIZE__SHIFT                                                                            0x0
#define GE_PC_CNTL__NO_RESERVATION_EN__SHIFT                                                                  0x11
#define GE_PC_CNTL__WAVES_WITH_NO_GRANT__SHIFT                                                                0x12
#define GE_PC_CNTL__PC_SIZE_MASK                                                                              0x0000FFFFL
#define GE_PC_CNTL__NO_RESERVATION_EN_MASK                                                                    0x00020000L
#define GE_PC_CNTL__WAVES_WITH_NO_GRANT_MASK                                                                  0x003C0000L
//IA_UTCL1_CNTL
#define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT                                                            0x0
#define IA_UTCL1_CNTL__VMID_RESET_MODE__SHIFT                                                                 0x17
#define IA_UTCL1_CNTL__DROP_MODE__SHIFT                                                                       0x18
#define IA_UTCL1_CNTL__BYPASS__SHIFT                                                                          0x19
#define IA_UTCL1_CNTL__INVALIDATE__SHIFT                                                                      0x1a
#define IA_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT                                                                 0x1b
#define IA_UTCL1_CNTL__FORCE_SNOOP__SHIFT                                                                     0x1c
#define IA_UTCL1_CNTL__MTYPE_OVERRIDE__SHIFT                                                                  0x1d
#define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK                                                              0x000FFFFFL
#define IA_UTCL1_CNTL__VMID_RESET_MODE_MASK                                                                   0x00800000L
#define IA_UTCL1_CNTL__DROP_MODE_MASK                                                                         0x01000000L
#define IA_UTCL1_CNTL__BYPASS_MASK                                                                            0x02000000L
#define IA_UTCL1_CNTL__INVALIDATE_MASK                                                                        0x04000000L
#define IA_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK                                                                   0x08000000L
#define IA_UTCL1_CNTL__FORCE_SNOOP_MASK                                                                       0x10000000L
#define IA_UTCL1_CNTL__MTYPE_OVERRIDE_MASK                                                                    0x20000000L
//IA_UTCL1_STATUS
#define IA_UTCL1_STATUS__FAULT_DETECTED__SHIFT                                                                0x0
#define IA_UTCL1_STATUS__RETRY_DETECTED__SHIFT                                                                0x1
#define IA_UTCL1_STATUS__PRT_DETECTED__SHIFT                                                                  0x2
#define IA_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT                                                                 0x8
#define IA_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT                                                                 0x10
#define IA_UTCL1_STATUS__PRT_UTCL1ID__SHIFT                                                                   0x18
#define IA_UTCL1_STATUS__FAULT_DETECTED_MASK                                                                  0x00000001L
#define IA_UTCL1_STATUS__RETRY_DETECTED_MASK                                                                  0x00000002L
#define IA_UTCL1_STATUS__PRT_DETECTED_MASK                                                                    0x00000004L
#define IA_UTCL1_STATUS__FAULT_UTCL1ID_MASK                                                                   0x00003F00L
#define IA_UTCL1_STATUS__RETRY_UTCL1ID_MASK                                                                   0x003F0000L
#define IA_UTCL1_STATUS__PRT_UTCL1ID_MASK                                                                     0x3F000000L
//CC_GC_SA_UNIT_DISABLE
#define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT                                                              0x8
#define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK                                                                0x0000FF00L
//GC_USER_SA_UNIT_DISABLE
#define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT                                                            0x8
#define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK                                                              0x0000FF00L
//VGT_SYS_CONFIG
#define VGT_SYS_CONFIG__DUAL_CORE_EN__SHIFT                                                                   0x0
#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP__SHIFT                                                               0x1
#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE__SHIFT                                                       0x7
#define VGT_SYS_CONFIG__NUM_SUBGROUPS_IN_FLIGHT__SHIFT                                                        0x8
#define VGT_SYS_CONFIG__DUAL_CORE_EN_MASK                                                                     0x00000001L
#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP_MASK                                                                 0x0000007EL
#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE_MASK                                                         0x00000080L
#define VGT_SYS_CONFIG__NUM_SUBGROUPS_IN_FLIGHT_MASK                                                          0x0007FF00L
//GE_PRIV_CONTROL
#define GE_PRIV_CONTROL__DISCARD_LEGACY__SHIFT                                                                0x0
#define GE_PRIV_CONTROL__CLAMP_PRIMGRP_SIZE__SHIFT                                                            0x1
#define GE_PRIV_CONTROL__RESET_ON_PIPELINE_CHANGE__SHIFT                                                      0xa
#define GE_PRIV_CONTROL__FGCG_OVERRIDE__SHIFT                                                                 0xf
#define GE_PRIV_CONTROL__CLAMP_HS_OFFCHIP_PER_SE_OVERRIDE__SHIFT                                              0x10
#define GE_PRIV_CONTROL__DISCARD_LEGACY_MASK                                                                  0x00000001L
#define GE_PRIV_CONTROL__CLAMP_PRIMGRP_SIZE_MASK                                                              0x000003FEL
#define GE_PRIV_CONTROL__RESET_ON_PIPELINE_CHANGE_MASK                                                        0x00000400L
#define GE_PRIV_CONTROL__FGCG_OVERRIDE_MASK                                                                   0x00008000L
#define GE_PRIV_CONTROL__CLAMP_HS_OFFCHIP_PER_SE_OVERRIDE_MASK                                                0x00010000L
//GE_STATUS
#define GE_STATUS__PERFCOUNTER_STATUS__SHIFT                                                                  0x0
#define GE_STATUS__THREAD_TRACE_STATUS__SHIFT                                                                 0x1
#define GE_STATUS__PERFCOUNTER_STATUS_MASK                                                                    0x00000001L
#define GE_STATUS__THREAD_TRACE_STATUS_MASK                                                                   0x00000002L
//VGT_VS_MAX_WAVE_ID
#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT                                                                0x0
#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID_MASK                                                                  0x00000FFFL
//VGT_GS_MAX_WAVE_ID
#define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT                                                                0x0
#define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID_MASK                                                                  0x00000FFFL
//CC_GC_SHADER_ARRAY_CONFIG_GEN1
#define CC_GC_SHADER_ARRAY_CONFIG_GEN1__GEN1_INACTIVE_CU__SHIFT                                               0x0
#define CC_GC_SHADER_ARRAY_CONFIG_GEN1__GEN1_INACTIVE_CU_MASK                                                 0x00003FFFL
//CC_GC_SHADER_ARRAY_CONFIG_GEN0
#define CC_GC_SHADER_ARRAY_CONFIG_GEN0__GEN0_INACTIVE_CU__SHIFT                                               0x0
#define CC_GC_SHADER_ARRAY_CONFIG_GEN0__GEN0_INACTIVE_CU_MASK                                                 0x00003FFFL
//GFX_PIPE_CONTROL
#define GFX_PIPE_CONTROL__HYSTERESIS_CNT__SHIFT                                                               0x0
#define GFX_PIPE_CONTROL__RESERVED__SHIFT                                                                     0xd
#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN__SHIFT                                                           0x10
#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_STALL_EN__SHIFT                                                     0x11
#define GFX_PIPE_CONTROL__HYSTERESIS_CNT_MASK                                                                 0x00001FFFL
#define GFX_PIPE_CONTROL__RESERVED_MASK                                                                       0x0000E000L
#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN_MASK                                                             0x00010000L
#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_STALL_EN_MASK                                                       0x00020000L
//CC_GC_SHADER_ARRAY_CONFIG
#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT                                                       0x10
#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK                                                         0xFFFF0000L
//GC_USER_SHADER_ARRAY_CONFIG
#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT                                                     0x10
#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK                                                       0xFFFF0000L
//VGT_DMA_PRIMITIVE_TYPE
#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT                                                              0x0
#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE_MASK                                                                0x0000003FL
//VGT_DMA_CONTROL
#define VGT_DMA_CONTROL__PRIMGROUP_SIZE__SHIFT                                                                0x0
#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP__SHIFT                                                              0x11
#define VGT_DMA_CONTROL__SWITCH_ON_EOI__SHIFT                                                                 0x13
#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP__SHIFT                                                              0x14
#define VGT_DMA_CONTROL__PRIMGROUP_SIZE_MASK                                                                  0x0000FFFFL
#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP_MASK                                                                0x00020000L
#define VGT_DMA_CONTROL__SWITCH_ON_EOI_MASK                                                                   0x00080000L
#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP_MASK                                                                0x00100000L
//VGT_DMA_LS_HS_CONFIG
#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT                                                          0x8
#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK                                                            0x00003F00L
//VGT_STRMOUT_DELAY
#define VGT_STRMOUT_DELAY__SKIP_DELAY__SHIFT                                                                  0x0
#define VGT_STRMOUT_DELAY__SE0_WD_DELAY__SHIFT                                                                0x8
#define VGT_STRMOUT_DELAY__SE1_WD_DELAY__SHIFT                                                                0xb
#define VGT_STRMOUT_DELAY__SE2_WD_DELAY__SHIFT                                                                0xe
#define VGT_STRMOUT_DELAY__SE3_WD_DELAY__SHIFT                                                                0x11
#define VGT_STRMOUT_DELAY__SKIP_DELAY_MASK                                                                    0x000000FFL
#define VGT_STRMOUT_DELAY__SE0_WD_DELAY_MASK                                                                  0x00000700L
#define VGT_STRMOUT_DELAY__SE1_WD_DELAY_MASK                                                                  0x00003800L
#define VGT_STRMOUT_DELAY__SE2_WD_DELAY_MASK                                                                  0x0001C000L
#define VGT_STRMOUT_DELAY__SE3_WD_DELAY_MASK                                                                  0x000E0000L
//WD_BUF_RESOURCE_1
#define WD_BUF_RESOURCE_1__POS_BUF_SIZE__SHIFT                                                                0x0
#define WD_BUF_RESOURCE_1__INDEX_BUF_SIZE__SHIFT                                                              0x10
#define WD_BUF_RESOURCE_1__POS_BUF_SIZE_MASK                                                                  0x0000FFFFL
#define WD_BUF_RESOURCE_1__INDEX_BUF_SIZE_MASK                                                                0xFFFF0000L
//WD_BUF_RESOURCE_2
#define WD_BUF_RESOURCE_2__PARAM_BUF_SIZE__SHIFT                                                              0x0
#define WD_BUF_RESOURCE_2__ADDR_MODE__SHIFT                                                                   0xf
#define WD_BUF_RESOURCE_2__CNTL_SB_BUF_SIZE__SHIFT                                                            0x10
#define WD_BUF_RESOURCE_2__PARAM_BUF_SIZE_MASK                                                                0x00001FFFL
#define WD_BUF_RESOURCE_2__ADDR_MODE_MASK                                                                     0x00008000L
#define WD_BUF_RESOURCE_2__CNTL_SB_BUF_SIZE_MASK                                                              0xFFFF0000L
//PA_CL_CNTL_STATUS
#define PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED__SHIFT                                                          0x0
#define PA_CL_CNTL_STATUS__UTC_RETRY_DETECTED__SHIFT                                                          0x1
#define PA_CL_CNTL_STATUS__UTC_PRT_DETECTED__SHIFT                                                            0x2
#define PA_CL_CNTL_STATUS__CL_BUSY__SHIFT                                                                     0x1f
#define PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED_MASK                                                            0x00000001L
#define PA_CL_CNTL_STATUS__UTC_RETRY_DETECTED_MASK                                                            0x00000002L
#define PA_CL_CNTL_STATUS__UTC_PRT_DETECTED_MASK                                                              0x00000004L
#define PA_CL_CNTL_STATUS__CL_BUSY_MASK                                                                       0x80000000L
//PA_CL_ENHANCE
#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT                                                            0x0
#define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT                                                                    0x1
#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL__SHIFT                                                          0x3
#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE__SHIFT                                                             0x4
#define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET__SHIFT                                                           0x6
#define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS__SHIFT                                                           0x7
#define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC__SHIFT                                                                0x8
#define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION__SHIFT                                                0x9
#define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER__SHIFT                                                          0xb
#define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH__SHIFT                                                       0xc
#define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH__SHIFT                                                     0xe
#define PA_CL_ENHANCE__PROG_NEAR_CLIP_PLANE_ENABLE__SHIFT                                                     0x11
#define PA_CL_ENHANCE__OUTPUT_SWITCH_TO_LEGACY_EVENT__SHIFT                                                   0x12
#define PA_CL_ENHANCE__NO_SWITCH_TO_LEGACY_AFTER_VMID_RESET__SHIFT                                            0x13
#define PA_CL_ENHANCE__POLY_INNER_EDGE_FLAG_DISABLE__SHIFT                                                    0x14
#define PA_CL_ENHANCE__TC_REQUEST_PERF_CNTR_ENABLE__SHIFT                                                     0x15
#define PA_CL_ENHANCE__DISABLE_PA_PH_INTF_FINE_CLOCK_GATE__SHIFT                                              0x16
#define PA_CL_ENHANCE__CLAMP_NEGATIVE_BB_TO_ZERO__SHIFT                                                       0x18
#define PA_CL_ENHANCE__ECO_SPARE3__SHIFT                                                                      0x1c
#define PA_CL_ENHANCE__ECO_SPARE2__SHIFT                                                                      0x1d
#define PA_CL_ENHANCE__ECO_SPARE1__SHIFT                                                                      0x1e
#define PA_CL_ENHANCE__ECO_SPARE0__SHIFT                                                                      0x1f
#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK                                                              0x00000001L
#define PA_CL_ENHANCE__NUM_CLIP_SEQ_MASK                                                                      0x00000006L
#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL_MASK                                                            0x00000008L
#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE_MASK                                                               0x00000010L
#define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET_MASK                                                             0x00000040L
#define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS_MASK                                                             0x00000080L
#define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC_MASK                                                                  0x00000100L
#define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION_MASK                                                  0x00000600L
#define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER_MASK                                                            0x00000800L
#define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH_MASK                                                         0x00003000L
#define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH_MASK                                                       0x0001C000L
#define PA_CL_ENHANCE__PROG_NEAR_CLIP_PLANE_ENABLE_MASK                                                       0x00020000L
#define PA_CL_ENHANCE__OUTPUT_SWITCH_TO_LEGACY_EVENT_MASK                                                     0x00040000L
#define PA_CL_ENHANCE__NO_SWITCH_TO_LEGACY_AFTER_VMID_RESET_MASK                                              0x00080000L
#define PA_CL_ENHANCE__POLY_INNER_EDGE_FLAG_DISABLE_MASK                                                      0x00100000L
#define PA_CL_ENHANCE__TC_REQUEST_PERF_CNTR_ENABLE_MASK                                                       0x00200000L
#define PA_CL_ENHANCE__DISABLE_PA_PH_INTF_FINE_CLOCK_GATE_MASK                                                0x00400000L
#define PA_CL_ENHANCE__CLAMP_NEGATIVE_BB_TO_ZERO_MASK                                                         0x01000000L
#define PA_CL_ENHANCE__ECO_SPARE3_MASK                                                                        0x10000000L
#define PA_CL_ENHANCE__ECO_SPARE2_MASK                                                                        0x20000000L
#define PA_CL_ENHANCE__ECO_SPARE1_MASK                                                                        0x40000000L
#define PA_CL_ENHANCE__ECO_SPARE0_MASK                                                                        0x80000000L
//PA_SU_CNTL_STATUS
#define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT                                                                     0x1f
#define PA_SU_CNTL_STATUS__SU_BUSY_MASK                                                                       0x80000000L
//PA_SC_FIFO_DEPTH_CNTL
#define PA_SC_FIFO_DEPTH_CNTL__DEPTH__SHIFT                                                                   0x0
#define PA_SC_FIFO_DEPTH_CNTL__DEPTH_MASK                                                                     0x000003FFL
//PA_SC_P3D_TRAP_SCREEN_HV_LOCK
#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT                                         0x0
#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK                                           0x00000001L
//PA_SC_HP3D_TRAP_SCREEN_HV_LOCK
#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT                                        0x0
#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK                                          0x00000001L
//PA_SC_TRAP_SCREEN_HV_LOCK
#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT                                             0x0
#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK                                               0x00000001L
//PA_SC_FORCE_EOV_MAX_CNTS
#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT                                                0x0
#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT                                                0x10
#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_MASK                                                  0x0000FFFFL
#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_MASK                                                  0xFFFF0000L
//PA_SC_BINNER_EVENT_CNTL_0
#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0__SHIFT                                                          0x0
#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1__SHIFT                                              0x2
#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2__SHIFT                                              0x4
#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3__SHIFT                                              0x6
#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS__SHIFT                                                      0x8
#define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE__SHIFT                                                        0xa
#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH__SHIFT                                                         0xc
#define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH__SHIFT                                                    0xe
#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC__SHIFT                                                  0x10
#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9__SHIFT                                                          0x12
#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET__SHIFT                                                 0x14
#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE__SHIFT                                                 0x16
#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END__SHIFT                                                  0x18
#define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT__SHIFT                                                         0x1a
#define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH__SHIFT                                                         0x1c
#define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH__SHIFT                                                    0x1e
#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0_MASK                                                            0x00000003L
#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1_MASK                                                0x0000000CL
#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2_MASK                                                0x00000030L
#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3_MASK                                                0x000000C0L
#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS_MASK                                                        0x00000300L
#define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE_MASK                                                          0x00000C00L
#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_MASK                                                           0x00003000L
#define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH_MASK                                                      0x0000C000L
#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC_MASK                                                    0x00030000L
#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9_MASK                                                            0x000C0000L
#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET_MASK                                                   0x00300000L
#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE_MASK                                                   0x00C00000L
#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END_MASK                                                    0x03000000L
#define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT_MASK                                                           0x0C000000L
#define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH_MASK                                                           0x30000000L
#define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH_MASK                                                      0xC0000000L
//PA_SC_BINNER_EVENT_CNTL_1
#define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH__SHIFT                                                    0x0
#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT__SHIFT                                                     0x2
#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM__SHIFT                                                          0x4
#define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT__SHIFT                                                 0x6
#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT__SHIFT                                        0x8
#define PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE__SHIFT                                                          0xa
#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT__SHIFT                                           0xc
#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START__SHIFT                                                   0xe
#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP__SHIFT                                                    0x10
#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START__SHIFT                                                  0x12
#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP__SHIFT                                                   0x14
#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE__SHIFT                                                  0x16
#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT__SHIFT                                                     0x18
#define PA_SC_BINNER_EVENT_CNTL_1__BIN_CONF_OVERRIDE_CHECK__SHIFT                                             0x1a
#define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT__SHIFT                                                 0x1c
#define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH__SHIFT                                               0x1e
#define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH_MASK                                                      0x00000003L
#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT_MASK                                                       0x0000000CL
#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM_MASK                                                            0x00000030L
#define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT_MASK                                                   0x000000C0L
#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT_MASK                                          0x00000300L
#define PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE_MASK                                                            0x00000C00L
#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT_MASK                                             0x00003000L
#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START_MASK                                                     0x0000C000L
#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP_MASK                                                      0x00030000L
#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START_MASK                                                    0x000C0000L
#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP_MASK                                                     0x00300000L
#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE_MASK                                                    0x00C00000L
#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT_MASK                                                       0x03000000L
#define PA_SC_BINNER_EVENT_CNTL_1__BIN_CONF_OVERRIDE_CHECK_MASK                                               0x0C000000L
#define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT_MASK                                                   0x30000000L
#define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH_MASK                                                 0xC0000000L
//PA_SC_BINNER_EVENT_CNTL_2
#define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS__SHIFT                                               0x0
#define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT__SHIFT                                                       0x2
#define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE__SHIFT                                                  0x4
#define PA_SC_BINNER_EVENT_CNTL_2__RESERVED_35__SHIFT                                                         0x6
#define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH__SHIFT                                                           0x8
#define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER__SHIFT                                                       0xa
#define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT__SHIFT                                                        0xc
#define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ__SHIFT                                                      0xe
#define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS__SHIFT                                                   0x10
#define PA_SC_BINNER_EVENT_CNTL_2__RESERVED_41__SHIFT                                                         0x12
#define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV__SHIFT                                              0x14
#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS__SHIFT                                            0x16
#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META__SHIFT                                               0x18
#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS__SHIFT                                            0x1a
#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META__SHIFT                                               0x1c
#define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE__SHIFT                                                             0x1e
#define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS_MASK                                                 0x00000003L
#define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT_MASK                                                         0x0000000CL
#define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE_MASK                                                    0x00000030L
#define PA_SC_BINNER_EVENT_CNTL_2__RESERVED_35_MASK                                                           0x000000C0L
#define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH_MASK                                                             0x00000300L
#define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER_MASK                                                         0x00000C00L
#define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT_MASK                                                          0x00003000L
#define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ_MASK                                                        0x0000C000L
#define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS_MASK                                                     0x00030000L
#define PA_SC_BINNER_EVENT_CNTL_2__RESERVED_41_MASK                                                           0x000C0000L
#define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV_MASK                                                0x00300000L
#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS_MASK                                              0x00C00000L
#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META_MASK                                                 0x03000000L
#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS_MASK                                              0x0C000000L
#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META_MASK                                                 0x30000000L
#define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE_MASK                                                               0xC0000000L
//PA_SC_BINNER_EVENT_CNTL_3
#define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE__SHIFT                                                             0x0
#define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA__SHIFT                                         0x2
#define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_50__SHIFT                                                         0x4
#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START__SHIFT                                                  0x6
#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP__SHIFT                                                   0x8
#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER__SHIFT                                                 0xa
#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_DRAW__SHIFT                                                   0xc
#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH__SHIFT                                                 0xe
#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL__SHIFT                                             0x10
#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP__SHIFT                                                0x12
#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET__SHIFT                                               0x14
#define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND__SHIFT                                                     0x16
#define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC__SHIFT                                                  0x18
#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE__SHIFT                                                 0x1a
#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_LEGACY_PIPELINE__SHIFT                                              0x1c
#define PA_SC_BINNER_EVENT_CNTL_3__DRAW_DONE__SHIFT                                                           0x1e
#define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE_MASK                                                               0x00000003L
#define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA_MASK                                           0x0000000CL
#define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_50_MASK                                                           0x00000030L
#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START_MASK                                                    0x000000C0L
#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP_MASK                                                     0x00000300L
#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER_MASK                                                   0x00000C00L
#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_DRAW_MASK                                                     0x00003000L
#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH_MASK                                                   0x0000C000L
#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL_MASK                                               0x00030000L
#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP_MASK                                                  0x000C0000L
#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET_MASK                                                 0x00300000L
#define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND_MASK                                                       0x00C00000L
#define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC_MASK                                                    0x03000000L
#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE_MASK                                                   0x0C000000L
#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_LEGACY_PIPELINE_MASK                                                0x30000000L
#define PA_SC_BINNER_EVENT_CNTL_3__DRAW_DONE_MASK                                                             0xC0000000L
//PA_SC_BINNER_TIMEOUT_COUNTER
#define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD__SHIFT                                                        0x0
#define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD_MASK                                                          0xFFFFFFFFL
//PA_SC_BINNER_PERF_CNTL_0
#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD__SHIFT                                         0x0
#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD__SHIFT                                       0xa
#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD__SHIFT                                       0x14
#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD__SHIFT                                     0x17
#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD_MASK                                           0x000003FFL
#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD_MASK                                         0x000FFC00L
#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD_MASK                                         0x00700000L
#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD_MASK                                       0x03800000L
//PA_SC_BINNER_PERF_CNTL_1
#define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT                              0x0
#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT                            0x5
#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD__SHIFT                         0xa
#define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK                                0x0000001FL
#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK                              0x000003E0L
#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD_MASK                           0x03FFFC00L
//PA_SC_BINNER_PERF_CNTL_2
#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD__SHIFT                               0x0
#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD__SHIFT                             0xb
#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD_MASK                                 0x000007FFL
#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD_MASK                               0x003FF800L
//PA_SC_BINNER_PERF_CNTL_3
#define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD__SHIFT                              0x0
#define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD_MASK                                0xFFFFFFFFL
//PA_SC_ENHANCE_2
#define PA_SC_ENHANCE_2__DISABLE_SC_MEM_MACRO_FINE_CLOCK_GATE__SHIFT                                          0x0
#define PA_SC_ENHANCE_2__DISABLE_SC_DB_QUAD_INTF_FINE_CLOCK_GATE__SHIFT                                       0x1
#define PA_SC_ENHANCE_2__DISABLE_SC_BCI_QUAD_INTF_FINE_CLOCK_GATE__SHIFT                                      0x2
#define PA_SC_ENHANCE_2__DISABLE_SC_BCI_PRIM_INTF_FINE_CLOCK_GATE__SHIFT                                      0x3
#define PA_SC_ENHANCE_2__ENABLE_LPOV_WAVE_BREAK__SHIFT                                                        0x4
#define PA_SC_ENHANCE_2__ENABLE_FPOV_WAVE_BREAK__SHIFT                                                        0x5
#define PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_EN_PRIM_PAYLOAD__SHIFT                                     0x7
#define PA_SC_ENHANCE_2__DISABLE_BREAK_BATCH_ON_GFX_PIPE_SWITCH__SHIFT                                        0x8
#define PA_SC_ENHANCE_2__DISABLE_FULL_TILE_WAVE_BREAK__SHIFT                                                  0x9
#define PA_SC_ENHANCE_2__ENABLE_VPZ_INJECTION_BEFORE_NULL_PRIMS__SHIFT                                        0xa
#define PA_SC_ENHANCE_2__PBB_TIMEOUT_THRESHOLD_MODE__SHIFT                                                    0xb
#define PA_SC_ENHANCE_2__DISABLE_PACKER_GRAD_FDCE_ENHANCE__SHIFT                                              0xc
#define PA_SC_ENHANCE_2__DISABLE_SC_SPI_INTF_EARLY_WAKEUP__SHIFT                                              0xd
#define PA_SC_ENHANCE_2__DISABLE_SC_BCI_INTF_EARLY_WAKEUP__SHIFT                                              0xe
#define PA_SC_ENHANCE_2__DISABLE_EXPOSED_GT_DETAIL_RATE_TILE_COV_ADJ__SHIFT                                   0xf
#define PA_SC_ENHANCE_2__PBB_WARP_CLK_MAIN_CLK_WAKEUP__SHIFT                                                  0x10
#define PA_SC_ENHANCE_2__PBB_MAIN_CLK_REG_BUSY_WAKEUP__SHIFT                                                  0x11
#define PA_SC_ENHANCE_2__DISABLE_BREAK_BATCH_ON_GFX_PIPELINE_RESET__SHIFT                                     0x12
#define PA_SC_ENHANCE_2__ENABLE_BLOCKING_WRITES_OF_GEN1_REG__SHIFT                                            0x13
#define PA_SC_ENHANCE_2__ENABLE_BLOCKING_WRITES_OF_GEN2_REG__SHIFT                                            0x14
#define PA_SC_ENHANCE_2__DISABLE_SC_DBR_DATAPATH_FGCG__SHIFT                                                  0x15
#define PA_SC_ENHANCE_2__PROCESS_RESET_FORCE_STILE_MASK_TO_ZERO__SHIFT                                        0x17
#define PA_SC_ENHANCE_2__DISABLE_PBB_EOP_INSERTION_FOR_MIXED_BINNING_AND_IMMEDIATE__SHIFT                     0x18
#define PA_SC_ENHANCE_2__DISABLE_DFSM_FLUSH__SHIFT                                                            0x19
#define PA_SC_ENHANCE_2__BREAK_WHEN_ONE_NULL_PRIM_BATCH__SHIFT                                                0x1a
#define PA_SC_ENHANCE_2__NULL_PRIM_BREAK_BATCH_LIMIT__SHIFT                                                   0x1b
#define PA_SC_ENHANCE_2__DISABLE_MAX_DEALLOC_FORCE_EOV_RESET_N_WAVES_COUNT__SHIFT                             0x1e
#define PA_SC_ENHANCE_2__RSVD__SHIFT                                                                          0x1f
#define PA_SC_ENHANCE_2__DISABLE_SC_MEM_MACRO_FINE_CLOCK_GATE_MASK                                            0x00000001L
#define PA_SC_ENHANCE_2__DISABLE_SC_DB_QUAD_INTF_FINE_CLOCK_GATE_MASK                                         0x00000002L
#define PA_SC_ENHANCE_2__DISABLE_SC_BCI_QUAD_INTF_FINE_CLOCK_GATE_MASK                                        0x00000004L
#define PA_SC_ENHANCE_2__DISABLE_SC_BCI_PRIM_INTF_FINE_CLOCK_GATE_MASK                                        0x00000008L
#define PA_SC_ENHANCE_2__ENABLE_LPOV_WAVE_BREAK_MASK                                                          0x00000010L
#define PA_SC_ENHANCE_2__ENABLE_FPOV_WAVE_BREAK_MASK                                                          0x00000020L
#define PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_EN_PRIM_PAYLOAD_MASK                                       0x00000080L
#define PA_SC_ENHANCE_2__DISABLE_BREAK_BATCH_ON_GFX_PIPE_SWITCH_MASK                                          0x00000100L
#define PA_SC_ENHANCE_2__DISABLE_FULL_TILE_WAVE_BREAK_MASK                                                    0x00000200L
#define PA_SC_ENHANCE_2__ENABLE_VPZ_INJECTION_BEFORE_NULL_PRIMS_MASK                                          0x00000400L
#define PA_SC_ENHANCE_2__PBB_TIMEOUT_THRESHOLD_MODE_MASK                                                      0x00000800L
#define PA_SC_ENHANCE_2__DISABLE_PACKER_GRAD_FDCE_ENHANCE_MASK                                                0x00001000L
#define PA_SC_ENHANCE_2__DISABLE_SC_SPI_INTF_EARLY_WAKEUP_MASK                                                0x00002000L
#define PA_SC_ENHANCE_2__DISABLE_SC_BCI_INTF_EARLY_WAKEUP_MASK                                                0x00004000L
#define PA_SC_ENHANCE_2__DISABLE_EXPOSED_GT_DETAIL_RATE_TILE_COV_ADJ_MASK                                     0x00008000L
#define PA_SC_ENHANCE_2__PBB_WARP_CLK_MAIN_CLK_WAKEUP_MASK                                                    0x00010000L
#define PA_SC_ENHANCE_2__PBB_MAIN_CLK_REG_BUSY_WAKEUP_MASK                                                    0x00020000L
#define PA_SC_ENHANCE_2__DISABLE_BREAK_BATCH_ON_GFX_PIPELINE_RESET_MASK                                       0x00040000L
#define PA_SC_ENHANCE_2__ENABLE_BLOCKING_WRITES_OF_GEN1_REG_MASK                                              0x00080000L
#define PA_SC_ENHANCE_2__ENABLE_BLOCKING_WRITES_OF_GEN2_REG_MASK                                              0x00100000L
#define PA_SC_ENHANCE_2__DISABLE_SC_DBR_DATAPATH_FGCG_MASK                                                    0x00200000L
#define PA_SC_ENHANCE_2__PROCESS_RESET_FORCE_STILE_MASK_TO_ZERO_MASK                                          0x00800000L
#define PA_SC_ENHANCE_2__DISABLE_PBB_EOP_INSERTION_FOR_MIXED_BINNING_AND_IMMEDIATE_MASK                       0x01000000L
#define PA_SC_ENHANCE_2__DISABLE_DFSM_FLUSH_MASK                                                              0x02000000L
#define PA_SC_ENHANCE_2__BREAK_WHEN_ONE_NULL_PRIM_BATCH_MASK                                                  0x04000000L
#define PA_SC_ENHANCE_2__NULL_PRIM_BREAK_BATCH_LIMIT_MASK                                                     0x38000000L
#define PA_SC_ENHANCE_2__DISABLE_MAX_DEALLOC_FORCE_EOV_RESET_N_WAVES_COUNT_MASK                               0x40000000L
#define PA_SC_ENHANCE_2__RSVD_MASK                                                                            0x80000000L
//PA_SC_ENHANCE_INTERNAL
//PA_SC_BINNER_CNTL_OVERRIDE
#define PA_SC_BINNER_CNTL_OVERRIDE__BINNING_MODE__SHIFT                                                       0x0
#define PA_SC_BINNER_CNTL_OVERRIDE__CONTEXT_STATES_PER_BIN__SHIFT                                             0xa
#define PA_SC_BINNER_CNTL_OVERRIDE__PERSISTENT_STATES_PER_BIN__SHIFT                                          0xd
#define PA_SC_BINNER_CNTL_OVERRIDE__FPOVS_PER_BATCH__SHIFT                                                    0x13
#define PA_SC_BINNER_CNTL_OVERRIDE__DIRECT_OVERRIDE_MODE__SHIFT                                               0x1b
#define PA_SC_BINNER_CNTL_OVERRIDE__OVERRIDE__SHIFT                                                           0x1c
#define PA_SC_BINNER_CNTL_OVERRIDE__BINNING_MODE_MASK                                                         0x00000003L
#define PA_SC_BINNER_CNTL_OVERRIDE__CONTEXT_STATES_PER_BIN_MASK                                               0x00001C00L
#define PA_SC_BINNER_CNTL_OVERRIDE__PERSISTENT_STATES_PER_BIN_MASK                                            0x0003E000L
#define PA_SC_BINNER_CNTL_OVERRIDE__FPOVS_PER_BATCH_MASK                                                      0x07F80000L
#define PA_SC_BINNER_CNTL_OVERRIDE__DIRECT_OVERRIDE_MODE_MASK                                                 0x08000000L
#define PA_SC_BINNER_CNTL_OVERRIDE__OVERRIDE_MASK                                                             0xF0000000L
//PA_SC_PBB_OVERRIDE_FLAG
#define PA_SC_PBB_OVERRIDE_FLAG__OVERRIDE__SHIFT                                                              0x0
#define PA_SC_PBB_OVERRIDE_FLAG__PIPE_ID__SHIFT                                                               0x1
#define PA_SC_PBB_OVERRIDE_FLAG__OVERRIDE_MASK                                                                0x00000001L
#define PA_SC_PBB_OVERRIDE_FLAG__PIPE_ID_MASK                                                                 0x00000002L
//PA_PH_INTERFACE_FIFO_SIZE
#define PA_PH_INTERFACE_FIFO_SIZE__PA_PH_IF_FIFO_SIZE__SHIFT                                                  0x0
#define PA_PH_INTERFACE_FIFO_SIZE__PH_SC_IF_FIFO_SIZE__SHIFT                                                  0x10
#define PA_PH_INTERFACE_FIFO_SIZE__PA_PH_IF_FIFO_SIZE_MASK                                                    0x000003FFL
#define PA_PH_INTERFACE_FIFO_SIZE__PH_SC_IF_FIFO_SIZE_MASK                                                    0x003F0000L
//PA_PH_ENHANCE
#define PA_PH_ENHANCE__ECO_SPARE0__SHIFT                                                                      0x0
#define PA_PH_ENHANCE__ECO_SPARE1__SHIFT                                                                      0x1
#define PA_PH_ENHANCE__ECO_SPARE2__SHIFT                                                                      0x2
#define PA_PH_ENHANCE__ECO_SPARE3__SHIFT                                                                      0x3
#define PA_PH_ENHANCE__DISABLE_PH_SC_INTF_FINE_CLOCK_GATE__SHIFT                                              0x4
#define PA_PH_ENHANCE__DISABLE_FOPKT__SHIFT                                                                   0x5
#define PA_PH_ENHANCE__DISABLE_FOPKT_SCAN_POST_RESET__SHIFT                                                   0x6
#define PA_PH_ENHANCE__DISABLE_PH_SC_INTF_CLKEN_CLOCK_GATE__SHIFT                                             0x7
#define PA_PH_ENHANCE__DISABLE_PH_PERF_REG_FGCG__SHIFT                                                        0x9
#define PA_PH_ENHANCE__ENABLE_PH_INTF_CLKEN_STRETCH__SHIFT                                                    0xa
#define PA_PH_ENHANCE__DISABLE_USE_LAST_PH_ARBITER_PERFCOUNTER_SAMPLE_EVENT__SHIFT                            0xd
#define PA_PH_ENHANCE__ECO_SPARE0_MASK                                                                        0x00000001L
#define PA_PH_ENHANCE__ECO_SPARE1_MASK                                                                        0x00000002L
#define PA_PH_ENHANCE__ECO_SPARE2_MASK                                                                        0x00000004L
#define PA_PH_ENHANCE__ECO_SPARE3_MASK                                                                        0x00000008L
#define PA_PH_ENHANCE__DISABLE_PH_SC_INTF_FINE_CLOCK_GATE_MASK                                                0x00000010L
#define PA_PH_ENHANCE__DISABLE_FOPKT_MASK                                                                     0x00000020L
#define PA_PH_ENHANCE__DISABLE_FOPKT_SCAN_POST_RESET_MASK                                                     0x00000040L
#define PA_PH_ENHANCE__DISABLE_PH_SC_INTF_CLKEN_CLOCK_GATE_MASK                                               0x00000080L
#define PA_PH_ENHANCE__DISABLE_PH_PERF_REG_FGCG_MASK                                                          0x00000200L
#define PA_PH_ENHANCE__ENABLE_PH_INTF_CLKEN_STRETCH_MASK                                                      0x00001C00L
#define PA_PH_ENHANCE__DISABLE_USE_LAST_PH_ARBITER_PERFCOUNTER_SAMPLE_EVENT_MASK                              0x00002000L
//PA_SC_BC_WAVE_BREAK
#define PA_SC_BC_WAVE_BREAK__MAX_DEALLOCS_IN_WAVE__SHIFT                                                      0x0
#define PA_SC_BC_WAVE_BREAK__MAX_FPOVS_IN_WAVE__SHIFT                                                         0x10
#define PA_SC_BC_WAVE_BREAK__MAX_DEALLOCS_IN_WAVE_MASK                                                        0x000007FFL
#define PA_SC_BC_WAVE_BREAK__MAX_FPOVS_IN_WAVE_MASK                                                           0x00FF0000L
//PA_SC_ENHANCE_3
#define PA_SC_ENHANCE_3__FORCE_USE_OF_SC_CENTROID_DATA__SHIFT                                                 0x0
#define PA_SC_ENHANCE_3__DISABLE_RB_MASK_COPY_FOR_NONP2_SA_HARVEST__SHIFT                                     0x2
#define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT                                               0x3
#define PA_SC_ENHANCE_3__DISABLE_PKR_BCI_QUAD_NEW_PRIM_DATA_LOAD_OPTIMIZATION__SHIFT                          0x4
#define PA_SC_ENHANCE_3__DISABLE_CP_CONTEXT_DONE_PERFCOUNT_SAMPLE_EN__SHIFT                                   0x5
#define PA_SC_ENHANCE_3__RSVD__SHIFT                                                                          0x6
#define PA_SC_ENHANCE_3__FORCE_USE_OF_SC_CENTROID_DATA_MASK                                                   0x00000001L
#define PA_SC_ENHANCE_3__DISABLE_RB_MASK_COPY_FOR_NONP2_SA_HARVEST_MASK                                       0x00000004L
#define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK                                                 0x00000008L
#define PA_SC_ENHANCE_3__DISABLE_PKR_BCI_QUAD_NEW_PRIM_DATA_LOAD_OPTIMIZATION_MASK                            0x00000010L
#define PA_SC_ENHANCE_3__DISABLE_CP_CONTEXT_DONE_PERFCOUNT_SAMPLE_EN_MASK                                     0x00000020L
#define PA_SC_ENHANCE_3__RSVD_MASK                                                                            0xFFFFFFC0L
//PA_SC_FIFO_SIZE
#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT                                                    0x0
#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT                                                     0x6
#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT                                                         0xf
#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT                                                      0x15
#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE_MASK                                                      0x0000003FL
#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE_MASK                                                       0x00007FC0L
#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE_MASK                                                           0x001F8000L
#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE_MASK                                                        0xFFE00000L
//PA_SC_IF_FIFO_SIZE
#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE__SHIFT                                                    0x0
#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE__SHIFT                                                    0x6
#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE__SHIFT                                                        0xc
#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE__SHIFT                                                        0x12
#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE_MASK                                                      0x0000003FL
#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE_MASK                                                      0x00000FC0L
#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE_MASK                                                          0x0003F000L
#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE_MASK                                                          0x00FC0000L
//PA_SC_PKR_WAVE_TABLE_CNTL
#define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE__SHIFT                                                                0x0
#define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE_MASK                                                                  0x0000003FL
//PA_SIDEBAND_REQUEST_DELAYS
#define PA_SIDEBAND_REQUEST_DELAYS__RETRY_DELAY__SHIFT                                                        0x0
#define PA_SIDEBAND_REQUEST_DELAYS__INITIAL_DELAY__SHIFT                                                      0x10
#define PA_SIDEBAND_REQUEST_DELAYS__RETRY_DELAY_MASK                                                          0x0000FFFFL
#define PA_SIDEBAND_REQUEST_DELAYS__INITIAL_DELAY_MASK                                                        0xFFFF0000L
//PA_SC_ENHANCE
#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER__SHIFT                                                       0x0
#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX__SHIFT                                                          0x1
#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX__SHIFT                                                        0x2
#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS__SHIFT                                                  0x3
#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID__SHIFT                                               0x4
#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX__SHIFT                                                             0x5
#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER__SHIFT                                                     0x6
#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION__SHIFT                                              0x7
#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT                                                   0x8
#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE__SHIFT                                              0x9
#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT                                                   0xa
#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE__SHIFT                                                          0xb
#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS__SHIFT                                          0xc
#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE__SHIFT                                                 0xd
#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE__SHIFT                                             0xe
#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE__SHIFT                                                   0xf
#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST__SHIFT                                   0x10
#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING__SHIFT                                        0x11
#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY__SHIFT                               0x12
#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING__SHIFT                               0x13
#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING__SHIFT                              0x14
#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS__SHIFT                                 0x15
#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID__SHIFT                                   0x16
#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO__SHIFT                           0x17
#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT                                          0x18
#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING__SHIFT                                       0x19
#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET__SHIFT                                                  0x1a
#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET__SHIFT                                              0x1b
#define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE__SHIFT                      0x1c
#define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING__SHIFT                              0x1d
#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK                                                         0x00000001L
#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX_MASK                                                            0x00000002L
#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX_MASK                                                          0x00000004L
#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS_MASK                                                    0x00000008L
#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID_MASK                                                 0x00000010L
#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX_MASK                                                               0x00000020L
#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER_MASK                                                       0x00000040L
#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION_MASK                                                0x00000080L
#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK                                                     0x00000100L
#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE_MASK                                                0x00000200L
#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK                                                     0x00000400L
#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE_MASK                                                            0x00000800L
#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS_MASK                                            0x00001000L
#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE_MASK                                                   0x00002000L
#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE_MASK                                               0x00004000L
#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE_MASK                                                     0x00008000L
#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST_MASK                                     0x00010000L
#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING_MASK                                          0x00020000L
#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY_MASK                                 0x00040000L
#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING_MASK                                 0x00080000L
#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING_MASK                                0x00100000L
#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS_MASK                                   0x00200000L
#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID_MASK                                     0x00400000L
#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO_MASK                             0x00800000L
#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK                                            0x01000000L
#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING_MASK                                         0x02000000L
#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET_MASK                                                    0x04000000L
#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET_MASK                                                0x08000000L
#define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE_MASK                        0x10000000L
#define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING_MASK                                0x20000000L
//PA_SC_ENHANCE_1
#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE__SHIFT                                                0x0
#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE__SHIFT                                                       0x1
#define PA_SC_ENHANCE_1__DISABLE_SC_BINNING__SHIFT                                                            0x3
#define PA_SC_ENHANCE_1__BYPASS_PBB__SHIFT                                                                    0x4
#define PA_SC_ENHANCE_1__ECO_SPARE0__SHIFT                                                                    0x5
#define PA_SC_ENHANCE_1__ECO_SPARE1__SHIFT                                                                    0x6
#define PA_SC_ENHANCE_1__ECO_SPARE2__SHIFT                                                                    0x7
#define PA_SC_ENHANCE_1__ECO_SPARE3__SHIFT                                                                    0x8
#define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB__SHIFT                                                  0x9
#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT__SHIFT                                                       0xa
#define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM__SHIFT                                     0xb
#define PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE__SHIFT                                       0xe
#define PA_SC_ENHANCE_1__DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION__SHIFT                              0xf
#define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE__SHIFT                                                    0x10
#define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION__SHIFT                                                         0x12
#define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS__SHIFT                                                  0x13
#define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION__SHIFT                                                  0x14
#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION__SHIFT                                          0x15
#define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION__SHIFT                                          0x16
#define PA_SC_ENHANCE_1__DISABLE_INTF_CG__SHIFT                                                               0x17
#define PA_SC_ENHANCE_1__IOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT                                        0x18
#define PA_SC_ENHANCE_1__DISABLE_SHADER_PROFILING_FOR_POWER__SHIFT                                            0x19
#define PA_SC_ENHANCE_1__FLUSH_ON_BINNING_TRANSITION__SHIFT                                                   0x1a
#define PA_SC_ENHANCE_1__DISABLE_QUAD_PROC_FDCE_ENHANCE__SHIFT                                                0x1b
#define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX__SHIFT                                                  0x1c
#define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_1__SHIFT                                                0x1d
#define PA_SC_ENHANCE_1__PASS_VPZ_EVENT_TO_SPI__SHIFT                                                         0x1e
#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE_MASK                                                  0x00000001L
#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_MASK                                                         0x00000006L
#define PA_SC_ENHANCE_1__DISABLE_SC_BINNING_MASK                                                              0x00000008L
#define PA_SC_ENHANCE_1__BYPASS_PBB_MASK                                                                      0x00000010L
#define PA_SC_ENHANCE_1__ECO_SPARE0_MASK                                                                      0x00000020L
#define PA_SC_ENHANCE_1__ECO_SPARE1_MASK                                                                      0x00000040L
#define PA_SC_ENHANCE_1__ECO_SPARE2_MASK                                                                      0x00000080L
#define PA_SC_ENHANCE_1__ECO_SPARE3_MASK                                                                      0x00000100L
#define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB_MASK                                                    0x00000200L
#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT_MASK                                                         0x00000400L
#define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM_MASK                                       0x00000800L
#define PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE_MASK                                         0x00004000L
#define PA_SC_ENHANCE_1__DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION_MASK                                0x00008000L
#define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE_MASK                                                      0x00010000L
#define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION_MASK                                                           0x00040000L
#define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS_MASK                                                    0x00080000L
#define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION_MASK                                                    0x00100000L
#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION_MASK                                            0x00200000L
#define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION_MASK                                            0x00400000L
#define PA_SC_ENHANCE_1__DISABLE_INTF_CG_MASK                                                                 0x00800000L
#define PA_SC_ENHANCE_1__IOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK                                          0x01000000L
#define PA_SC_ENHANCE_1__DISABLE_SHADER_PROFILING_FOR_POWER_MASK                                              0x02000000L
#define PA_SC_ENHANCE_1__FLUSH_ON_BINNING_TRANSITION_MASK                                                     0x04000000L
#define PA_SC_ENHANCE_1__DISABLE_QUAD_PROC_FDCE_ENHANCE_MASK                                                  0x08000000L
#define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_MASK                                                    0x10000000L
#define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_1_MASK                                                  0x20000000L
#define PA_SC_ENHANCE_1__PASS_VPZ_EVENT_TO_SPI_MASK                                                           0x40000000L
//PA_SC_DSM_CNTL
#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT                                                                0x0
#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1__SHIFT                                                                0x1
#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0_MASK                                                                  0x00000001L
#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1_MASK                                                                  0x00000002L
//PA_SC_TILE_STEERING_CREST_OVERRIDE
#define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE__SHIFT                                         0x0
#define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT__SHIFT                                                  0x1
#define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT__SHIFT                                                  0x5
#define PA_SC_TILE_STEERING_CREST_OVERRIDE__SA_SELECT__SHIFT                                                  0x8
#define PA_SC_TILE_STEERING_CREST_OVERRIDE__FORCE_TILE_STEERING_OVERRIDE_USE__SHIFT                           0x1f
#define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE_MASK                                           0x00000001L
#define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT_MASK                                                    0x00000006L
#define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT_MASK                                                    0x00000060L
#define PA_SC_TILE_STEERING_CREST_OVERRIDE__SA_SELECT_MASK                                                    0x00000700L
#define PA_SC_TILE_STEERING_CREST_OVERRIDE__FORCE_TILE_STEERING_OVERRIDE_USE_MASK                             0x80000000L


// addressBlock: gc_sqdec
//SQ_CONFIG
#define SQ_CONFIG__UNUSED__SHIFT                                                                              0x0
#define SQ_CONFIG__CHICKEN_BIT_DEGGIGXX0_8637__SHIFT                                                          0x5
#define SQ_CONFIG__UNUSED_6__SHIFT                                                                            0x6
#define SQ_CONFIG__DISABLE_SGPR_RD_KILL__SHIFT                                                                0xa
#define SQ_CONFIG__VGPR_SWIZZLE_EN__SHIFT                                                                     0xc
#define SQ_CONFIG__LDS_BUSY_HYSTERESIS_CNT__SHIFT                                                             0xd
#define SQ_CONFIG__SP_BUSY_HYSTERESIS_CNT__SHIFT                                                              0xf
#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS__SHIFT                                                         0x12
#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS__SHIFT                                                              0x13
#define SQ_CONFIG__WCLK_HYSTERESIS_CNT__SHIFT                                                                 0x15
#define SQ_CONFIG__DISABLE_SP_REDUNDANT_THREAD_GATING__SHIFT                                                  0x1d
#define SQ_CONFIG__TA_BUSY_HYSTERESIS_CNT__SHIFT                                                              0x1e
#define SQ_CONFIG__UNUSED_MASK                                                                                0x0000001FL
#define SQ_CONFIG__VGPR_SWIZZLE_EN_MASK                                                                       0x00001000L
#define SQ_CONFIG__LDS_BUSY_HYSTERESIS_CNT_MASK                                                               0x00006000L
#define SQ_CONFIG__SP_BUSY_HYSTERESIS_CNT_MASK                                                                0x00018000L
#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS_MASK                                                           0x00040000L
#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS_MASK                                                                0x00180000L
#define SQ_CONFIG__DISABLE_SP_REDUNDANT_THREAD_GATING_MASK                                                    0x20000000L
#define SQ_CONFIG__TA_BUSY_HYSTERESIS_CNT_MASK                                                                0xC0000000L
//SQC_CONFIG
#define SQC_CONFIG__INST_CACHE_SIZE__SHIFT                                                                    0x0
#define SQC_CONFIG__DATA_CACHE_SIZE__SHIFT                                                                    0x2
#define SQC_CONFIG__MISS_FIFO_DEPTH__SHIFT                                                                    0x4
#define SQC_CONFIG__HIT_FIFO_DEPTH__SHIFT                                                                     0x6
#define SQC_CONFIG__FORCE_ALWAYS_MISS__SHIFT                                                                  0x7
#define SQC_CONFIG__FORCE_IN_ORDER__SHIFT                                                                     0x8
#define SQC_CONFIG__PER_VMID_INV_DISABLE__SHIFT                                                               0xb
#define SQC_CONFIG__EVICT_LRU__SHIFT                                                                          0xc
#define SQC_CONFIG__FORCE_2_BANK__SHIFT                                                                       0xe
#define SQC_CONFIG__FORCE_1_BANK__SHIFT                                                                       0xf
#define SQC_CONFIG__LS_DISABLE_CLOCKS__SHIFT                                                                  0x10
#define SQC_CONFIG__INST_CACHE_SIZE_MASK                                                                      0x00000003L
#define SQC_CONFIG__DATA_CACHE_SIZE_MASK                                                                      0x0000000CL
#define SQC_CONFIG__MISS_FIFO_DEPTH_MASK                                                                      0x00000030L
#define SQC_CONFIG__HIT_FIFO_DEPTH_MASK                                                                       0x00000040L
#define SQC_CONFIG__FORCE_ALWAYS_MISS_MASK                                                                    0x00000080L
#define SQC_CONFIG__FORCE_IN_ORDER_MASK                                                                       0x00000100L
#define SQC_CONFIG__PER_VMID_INV_DISABLE_MASK                                                                 0x00000800L
#define SQC_CONFIG__EVICT_LRU_MASK                                                                            0x00003000L
#define SQC_CONFIG__FORCE_2_BANK_MASK                                                                         0x00004000L
#define SQC_CONFIG__FORCE_1_BANK_MASK                                                                         0x00008000L
#define SQC_CONFIG__LS_DISABLE_CLOCKS_MASK                                                                    0x00FF0000L
//LDS_CONFIG
#define LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING__SHIFT                                                        0x0
#define LDS_CONFIG__VGPR_SWIZZLE_EN__SHIFT                                                                    0x1
#define LDS_CONFIG__WAVE32_INTERP_DUAL_ISSUE_DISABLE__SHIFT                                                   0x2
#define LDS_CONFIG__SP_TDDATA_FGCG_OVERRIDE__SHIFT                                                            0x3
#define LDS_CONFIG__SQC_PERF_FGCG_OVERRIDE__SHIFT                                                             0x4
#define LDS_CONFIG__CONF_BIT_5__SHIFT                                                                         0x5
#define LDS_CONFIG__CONF_BIT_6__SHIFT                                                                         0x6
#define LDS_CONFIG__CONF_BIT_7__SHIFT                                                                         0x7
#define LDS_CONFIG__CONF_BIT_8__SHIFT                                                                         0x8
#define LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING_MASK                                                          0x00000001L
#define LDS_CONFIG__VGPR_SWIZZLE_EN_MASK                                                                      0x00000002L
#define LDS_CONFIG__WAVE32_INTERP_DUAL_ISSUE_DISABLE_MASK                                                     0x00000004L
#define LDS_CONFIG__SP_TDDATA_FGCG_OVERRIDE_MASK                                                              0x00000008L
#define LDS_CONFIG__SQC_PERF_FGCG_OVERRIDE_MASK                                                               0x00000010L
#define LDS_CONFIG__CONF_BIT_5_MASK                                                                           0x00000020L
#define LDS_CONFIG__CONF_BIT_6_MASK                                                                           0x00000040L
#define LDS_CONFIG__CONF_BIT_7_MASK                                                                           0x00000080L
#define LDS_CONFIG__CONF_BIT_8_MASK                                                                           0x00000100L
//SQ_RANDOM_WAVE_PRI
#define SQ_RANDOM_WAVE_PRI__RET__SHIFT                                                                        0x0
#define SQ_RANDOM_WAVE_PRI__RUI__SHIFT                                                                        0x7
#define SQ_RANDOM_WAVE_PRI__RNG__SHIFT                                                                        0xa
#define SQ_RANDOM_WAVE_PRI__FORCE_IB_ARB_PRIO_MSK_VALID__SHIFT                                                0x1f
#define SQ_RANDOM_WAVE_PRI__RET_MASK                                                                          0x0000007FL
#define SQ_RANDOM_WAVE_PRI__RUI_MASK                                                                          0x00000380L
#define SQ_RANDOM_WAVE_PRI__RNG_MASK                                                                          0x00FFFC00L
#define SQ_RANDOM_WAVE_PRI__FORCE_IB_ARB_PRIO_MSK_VALID_MASK                                                  0x80000000L
//SQG_STATUS
#define SQG_STATUS__REG_BUSY__SHIFT                                                                           0x0
#define SQG_STATUS__REG_BUSY_MASK                                                                             0x00000001L
//SQ_FIFO_SIZES
#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE__SHIFT                                                             0x0
#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE__SHIFT                                                                0x8
#define SQ_FIFO_SIZES__EXPORT_BUF_VS_RESERVED__SHIFT                                                          0xc
#define SQ_FIFO_SIZES__EXPORT_BUF_PS_RESERVED__SHIFT                                                          0xe
#define SQ_FIFO_SIZES__EXPORT_BUF_REDUCE__SHIFT                                                               0x10
#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE__SHIFT                                                             0x12
#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE_MASK                                                               0x0000000FL
#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE_MASK                                                                  0x00000300L
#define SQ_FIFO_SIZES__EXPORT_BUF_VS_RESERVED_MASK                                                            0x00003000L
#define SQ_FIFO_SIZES__EXPORT_BUF_PS_RESERVED_MASK                                                            0x0000C000L
#define SQ_FIFO_SIZES__EXPORT_BUF_REDUCE_MASK                                                                 0x00030000L
#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE_MASK                                                               0x000C0000L
//SQ_DSM_CNTL
#define SQ_DSM_CNTL__WAVEFRONT_STALL_0__SHIFT                                                                 0x0
#define SQ_DSM_CNTL__WAVEFRONT_STALL_1__SHIFT                                                                 0x1
#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0__SHIFT                                                                0x2
#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1__SHIFT                                                                0x3
#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0__SHIFT                                                      0x8
#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1__SHIFT                                                      0x9
#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT                                                          0xa
#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0__SHIFT                                                       0x10
#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1__SHIFT                                                       0x11
#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01__SHIFT                                                         0x12
#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2__SHIFT                                                       0x13
#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3__SHIFT                                                       0x14
#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23__SHIFT                                                         0x15
#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0__SHIFT                                                        0x18
#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1__SHIFT                                                        0x19
#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE__SHIFT                                                            0x1a
#define SQ_DSM_CNTL__WAVEFRONT_STALL_0_MASK                                                                   0x00000001L
#define SQ_DSM_CNTL__WAVEFRONT_STALL_1_MASK                                                                   0x00000002L
#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0_MASK                                                                  0x00000004L
#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1_MASK                                                                  0x00000008L
#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0_MASK                                                        0x00000100L
#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1_MASK                                                        0x00000200L
#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE_MASK                                                            0x00000400L
#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0_MASK                                                         0x00010000L
#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1_MASK                                                         0x00020000L
#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01_MASK                                                           0x00040000L
#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2_MASK                                                         0x00080000L
#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3_MASK                                                         0x00100000L
#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23_MASK                                                           0x00200000L
#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0_MASK                                                          0x01000000L
#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1_MASK                                                          0x02000000L
#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE_MASK                                                              0x04000000L
//SQ_DSM_CNTL2
#define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT__SHIFT                                                         0x0
#define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY__SHIFT                                                         0x2
#define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT__SHIFT                                                        0x3
#define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY__SHIFT                                                        0x5
#define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT__SHIFT                                                        0x6
#define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY__SHIFT                                                        0x8
#define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT__SHIFT                                                           0x9
#define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY__SHIFT                                                           0xb
#define SQ_DSM_CNTL2__LDS_INJECT_DELAY__SHIFT                                                                 0xe
#define SQ_DSM_CNTL2__SP_INJECT_DELAY__SHIFT                                                                  0x14
#define SQ_DSM_CNTL2__SQ_INJECT_DELAY__SHIFT                                                                  0x1a
#define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT_MASK                                                           0x00000003L
#define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY_MASK                                                           0x00000004L
#define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT_MASK                                                          0x00000018L
#define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY_MASK                                                          0x00000020L
#define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT_MASK                                                          0x000000C0L
#define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY_MASK                                                          0x00000100L
#define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT_MASK                                                             0x00000600L
#define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY_MASK                                                             0x00000800L
#define SQ_DSM_CNTL2__LDS_INJECT_DELAY_MASK                                                                   0x000FC000L
#define SQ_DSM_CNTL2__SP_INJECT_DELAY_MASK                                                                    0x03F00000L
#define SQ_DSM_CNTL2__SQ_INJECT_DELAY_MASK                                                                    0xFC000000L
//SQ_RUNTIME_CONFIG
#define SQ_RUNTIME_CONFIG__UNUSED_REGISTER__SHIFT                                                             0x0
#define SQ_RUNTIME_CONFIG__UNUSED_REGISTER_MASK                                                               0x00000001L
//SH_MEM_BASES
#define SH_MEM_BASES__PRIVATE_BASE__SHIFT                                                                     0x0
#define SH_MEM_BASES__SHARED_BASE__SHIFT                                                                      0x10
#define SH_MEM_BASES__PRIVATE_BASE_MASK                                                                       0x0000FFFFL
#define SH_MEM_BASES__SHARED_BASE_MASK                                                                        0xFFFF0000L
//SP_CONFIG
#define SP_CONFIG__DEST_CACHE_EVICT_COUNTER__SHIFT                                                            0x0
#define SP_CONFIG__ALU_BUSY_MGCG_OVERRIDE__SHIFT                                                              0x2
#define SP_CONFIG__DISABLE_TRANS_COEXEC__SHIFT                                                                0x3
#define SP_CONFIG__CAC_COUNTER_OVERRIDE__SHIFT                                                                0x4
#define SP_CONFIG__SP_SX_EXPVDATA_FGCG_OVERRIDE__SHIFT                                                        0x5
#define SP_CONFIG__DEST_CACHE_EVICT_COUNTER_MASK                                                              0x00000003L
#define SP_CONFIG__ALU_BUSY_MGCG_OVERRIDE_MASK                                                                0x00000004L
#define SP_CONFIG__DISABLE_TRANS_COEXEC_MASK                                                                  0x00000008L
#define SP_CONFIG__CAC_COUNTER_OVERRIDE_MASK                                                                  0x00000010L
#define SP_CONFIG__SP_SX_EXPVDATA_FGCG_OVERRIDE_MASK                                                          0x00000020L
//SQ_ARB_CONFIG
#define SQ_ARB_CONFIG__WG_RR_INTERVAL__SHIFT                                                                  0x0
#define SQ_ARB_CONFIG__FWD_PROG_INTERVAL__SHIFT                                                               0x4
#define SQ_ARB_CONFIG__WG_RR_INTERVAL_MASK                                                                    0x00000003L
#define SQ_ARB_CONFIG__FWD_PROG_INTERVAL_MASK                                                                 0x00000030L
//SH_MEM_CONFIG
#define SH_MEM_CONFIG__ADDRESS_MODE__SHIFT                                                                    0x0
#define SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT                                                                  0x2
#define SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT                                                                   0x4
#define SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT                                                           0xe
#define SH_MEM_CONFIG__ICACHE_USE_GL1__SHIFT                                                                  0x12
#define SH_MEM_CONFIG__ADDRESS_MODE_MASK                                                                      0x00000001L
#define SH_MEM_CONFIG__ALIGNMENT_MODE_MASK                                                                    0x0000000CL
#define SH_MEM_CONFIG__DEFAULT_MTYPE_MASK                                                                     0x00000070L
#define SH_MEM_CONFIG__INITIAL_INST_PREFETCH_MASK                                                             0x0000C000L
#define SH_MEM_CONFIG__ICACHE_USE_GL1_MASK                                                                    0x00040000L
//SQ_SHADER_TBA_LO
#define SQ_SHADER_TBA_LO__ADDR_LO__SHIFT                                                                      0x0
#define SQ_SHADER_TBA_LO__ADDR_LO_MASK                                                                        0xFFFFFFFFL
//SQ_SHADER_TBA_HI
#define SQ_SHADER_TBA_HI__ADDR_HI__SHIFT                                                                      0x0
#define SQ_SHADER_TBA_HI__TRAP_EN__SHIFT                                                                      0x1f
#define SQ_SHADER_TBA_HI__ADDR_HI_MASK                                                                        0x000000FFL
#define SQ_SHADER_TBA_HI__TRAP_EN_MASK                                                                        0x80000000L
//SQ_SHADER_TMA_LO
#define SQ_SHADER_TMA_LO__ADDR_LO__SHIFT                                                                      0x0
#define SQ_SHADER_TMA_LO__ADDR_LO_MASK                                                                        0xFFFFFFFFL
//SQ_SHADER_TMA_HI
#define SQ_SHADER_TMA_HI__ADDR_HI__SHIFT                                                                      0x0
#define SQ_SHADER_TMA_HI__ADDR_HI_MASK                                                                        0x000000FFL
//SQG_UTCL0_CNTL1
#define SQG_UTCL0_CNTL1__FORCE_4K_L2_RESP__SHIFT                                                              0x0
#define SQG_UTCL0_CNTL1__GPUVM_64K_DEF__SHIFT                                                                 0x1
#define SQG_UTCL0_CNTL1__GPUVM_PERM_MODE__SHIFT                                                               0x2
#define SQG_UTCL0_CNTL1__RESP_MODE__SHIFT                                                                     0x3
#define SQG_UTCL0_CNTL1__RESP_FAULT_MODE__SHIFT                                                               0x5
#define SQG_UTCL0_CNTL1__CLIENTID__SHIFT                                                                      0x7
#define SQG_UTCL0_CNTL1__RESERVED__SHIFT                                                                      0x10
#define SQG_UTCL0_CNTL1__ENABLE_PUSH_LFIFO__SHIFT                                                             0x11
#define SQG_UTCL0_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT                                                          0x12
#define SQG_UTCL0_CNTL1__REG_INV_VMID__SHIFT                                                                  0x13
#define SQG_UTCL0_CNTL1__REG_INV_ALL_VMID__SHIFT                                                              0x17
#define SQG_UTCL0_CNTL1__REG_INV_TOGGLE__SHIFT                                                                0x18
#define SQG_UTCL0_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT                                                    0x19
#define SQG_UTCL0_CNTL1__FORCE_MISS__SHIFT                                                                    0x1a
#define SQG_UTCL0_CNTL1__FORCE_IN_ORDER__SHIFT                                                                0x1b
#define SQG_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT                                                        0x1c
#define SQG_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT                                                        0x1e
#define SQG_UTCL0_CNTL1__FORCE_4K_L2_RESP_MASK                                                                0x00000001L
#define SQG_UTCL0_CNTL1__GPUVM_64K_DEF_MASK                                                                   0x00000002L
#define SQG_UTCL0_CNTL1__GPUVM_PERM_MODE_MASK                                                                 0x00000004L
#define SQG_UTCL0_CNTL1__RESP_MODE_MASK                                                                       0x00000018L
#define SQG_UTCL0_CNTL1__RESP_FAULT_MODE_MASK                                                                 0x00000060L
#define SQG_UTCL0_CNTL1__CLIENTID_MASK                                                                        0x0000FF80L
#define SQG_UTCL0_CNTL1__RESERVED_MASK                                                                        0x00010000L
#define SQG_UTCL0_CNTL1__ENABLE_PUSH_LFIFO_MASK                                                               0x00020000L
#define SQG_UTCL0_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK                                                            0x00040000L
#define SQG_UTCL0_CNTL1__REG_INV_VMID_MASK                                                                    0x00780000L
#define SQG_UTCL0_CNTL1__REG_INV_ALL_VMID_MASK                                                                0x00800000L
#define SQG_UTCL0_CNTL1__REG_INV_TOGGLE_MASK                                                                  0x01000000L
#define SQG_UTCL0_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK                                                      0x02000000L
#define SQG_UTCL0_CNTL1__FORCE_MISS_MASK                                                                      0x04000000L
#define SQG_UTCL0_CNTL1__FORCE_IN_ORDER_MASK                                                                  0x08000000L
#define SQG_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK                                                          0x30000000L
#define SQG_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK                                                          0xC0000000L
//SQG_UTCL0_CNTL2
#define SQG_UTCL0_CNTL2__SPARE__SHIFT                                                                         0x0
#define SQG_UTCL0_CNTL2__LFIFO_SCAN_DISABLE__SHIFT                                                            0x8
#define SQG_UTCL0_CNTL2__MTYPE_OVRD_DIS__SHIFT                                                                0x9
#define SQG_UTCL0_CNTL2__LINE_VALID__SHIFT                                                                    0xa
#define SQG_UTCL0_CNTL2__DIS_EDC__SHIFT                                                                       0xb
#define SQG_UTCL0_CNTL2__GPUVM_INV_MODE__SHIFT                                                                0xc
#define SQG_UTCL0_CNTL2__SHOOTDOWN_OPT__SHIFT                                                                 0xd
#define SQG_UTCL0_CNTL2__FORCE_SNOOP__SHIFT                                                                   0xe
#define SQG_UTCL0_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT                                                           0xf
#define SQG_UTCL0_CNTL2__ARB_BURST_MODE__SHIFT                                                                0x10
#define SQG_UTCL0_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT                                                       0x12
#define SQG_UTCL0_CNTL2__PERF_EVENT_RD_WR__SHIFT                                                              0x13
#define SQG_UTCL0_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT                                                        0x14
#define SQG_UTCL0_CNTL2__PERF_EVENT_VMID__SHIFT                                                               0x15
#define SQG_UTCL0_CNTL2__DIS_DUAL_L2_REQ__SHIFT                                                               0x19
#define SQG_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT                                                          0x1a
#define SQG_UTCL0_CNTL2__PERM_MODE_OVRD__SHIFT                                                                0x1b
#define SQG_UTCL0_CNTL2__LINE_INVALIDATE_OPT__SHIFT                                                           0x1c
#define SQG_UTCL0_CNTL2__GPUVM_16K_DEF__SHIFT                                                                 0x1d
#define SQG_UTCL0_CNTL2__RESERVED__SHIFT                                                                      0x1e
#define SQG_UTCL0_CNTL2__SPARE_MASK                                                                           0x000000FFL
#define SQG_UTCL0_CNTL2__LFIFO_SCAN_DISABLE_MASK                                                              0x00000100L
#define SQG_UTCL0_CNTL2__MTYPE_OVRD_DIS_MASK                                                                  0x00000200L
#define SQG_UTCL0_CNTL2__LINE_VALID_MASK                                                                      0x00000400L
#define SQG_UTCL0_CNTL2__DIS_EDC_MASK                                                                         0x00000800L
#define SQG_UTCL0_CNTL2__GPUVM_INV_MODE_MASK                                                                  0x00001000L
#define SQG_UTCL0_CNTL2__SHOOTDOWN_OPT_MASK                                                                   0x00002000L
#define SQG_UTCL0_CNTL2__FORCE_SNOOP_MASK                                                                     0x00004000L
#define SQG_UTCL0_CNTL2__FORCE_GPUVM_INV_ACK_MASK                                                             0x00008000L
#define SQG_UTCL0_CNTL2__ARB_BURST_MODE_MASK                                                                  0x00030000L
#define SQG_UTCL0_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK                                                         0x00040000L
#define SQG_UTCL0_CNTL2__PERF_EVENT_RD_WR_MASK                                                                0x00080000L
#define SQG_UTCL0_CNTL2__ENABLE_PERF_EVENT_VMID_MASK                                                          0x00100000L
#define SQG_UTCL0_CNTL2__PERF_EVENT_VMID_MASK                                                                 0x01E00000L
#define SQG_UTCL0_CNTL2__DIS_DUAL_L2_REQ_MASK                                                                 0x02000000L
#define SQG_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K_MASK                                                            0x04000000L
#define SQG_UTCL0_CNTL2__PERM_MODE_OVRD_MASK                                                                  0x08000000L
#define SQG_UTCL0_CNTL2__LINE_INVALIDATE_OPT_MASK                                                             0x10000000L
#define SQG_UTCL0_CNTL2__GPUVM_16K_DEF_MASK                                                                   0x20000000L
#define SQG_UTCL0_CNTL2__RESERVED_MASK                                                                        0xC0000000L
//SQG_UTCL0_STATUS
#define SQG_UTCL0_STATUS__FAULT_DETECTED__SHIFT                                                               0x0
#define SQG_UTCL0_STATUS__RETRY_DETECTED__SHIFT                                                               0x1
#define SQG_UTCL0_STATUS__PRT_DETECTED__SHIFT                                                                 0x2
#define SQG_UTCL0_STATUS__RESERVED__SHIFT                                                                     0x3
#define SQG_UTCL0_STATUS__UNUSED__SHIFT                                                                       0x8
#define SQG_UTCL0_STATUS__FAULT_DETECTED_MASK                                                                 0x00000001L
#define SQG_UTCL0_STATUS__RETRY_DETECTED_MASK                                                                 0x00000002L
#define SQG_UTCL0_STATUS__PRT_DETECTED_MASK                                                                   0x00000004L
#define SQG_UTCL0_STATUS__RESERVED_MASK                                                                       0x000000F8L
#define SQG_UTCL0_STATUS__UNUSED_MASK                                                                         0xFFFFFF00L
//SQG_CONFIG
#define SQG_CONFIG__UTCL0_PREFETCH_PAGE__SHIFT                                                                0x0
#define SQG_CONFIG__UTCL0_RETRY_TIMER__SHIFT                                                                  0x4
#define SQG_CONFIG__UTCL0_PREFETCH_PAGE_MASK                                                                  0x0000000FL
#define SQG_CONFIG__UTCL0_RETRY_TIMER_MASK                                                                    0x000007F0L
//CC_GC_SHADER_RATE_CONFIG
#define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT                                                            0x1
#define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT                                                  0x3
#define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE_MASK                                                              0x00000006L
#define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK                                                    0x00000008L
//GC_USER_SHADER_RATE_CONFIG
#define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT                                                          0x1
#define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT                                                0x3
#define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE_MASK                                                            0x00000006L
#define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK                                                  0x00000008L
//SQ_INTERRUPT_AUTO_MASK
#define SQ_INTERRUPT_AUTO_MASK__MASK__SHIFT                                                                   0x0
#define SQ_INTERRUPT_AUTO_MASK__MASK_MASK                                                                     0x00FFFFFFL
//SQ_INTERRUPT_MSG_CTRL
#define SQ_INTERRUPT_MSG_CTRL__STALL__SHIFT                                                                   0x0
#define SQ_INTERRUPT_MSG_CTRL__STALL_MASK                                                                     0x00000001L
//SQ_WATCH0_ADDR_H
#define SQ_WATCH0_ADDR_H__ADDR__SHIFT                                                                         0x0
#define SQ_WATCH0_ADDR_H__ADDR_MASK                                                                           0x0000FFFFL
//SQ_WATCH0_ADDR_L
#define SQ_WATCH0_ADDR_L__ADDR__SHIFT                                                                         0x6
#define SQ_WATCH0_ADDR_L__ADDR_MASK                                                                           0xFFFFFFC0L
//SQ_WATCH0_CNTL
#define SQ_WATCH0_CNTL__MASK__SHIFT                                                                           0x0
#define SQ_WATCH0_CNTL__VMID__SHIFT                                                                           0x18
#define SQ_WATCH0_CNTL__VALID__SHIFT                                                                          0x1f
#define SQ_WATCH0_CNTL__MASK_MASK                                                                             0x00FFFFFFL
#define SQ_WATCH0_CNTL__VMID_MASK                                                                             0x0F000000L
#define SQ_WATCH0_CNTL__VALID_MASK                                                                            0x80000000L
//SQ_WATCH1_ADDR_H
#define SQ_WATCH1_ADDR_H__ADDR__SHIFT                                                                         0x0
#define SQ_WATCH1_ADDR_H__ADDR_MASK                                                                           0x0000FFFFL
//SQ_WATCH1_ADDR_L
#define SQ_WATCH1_ADDR_L__ADDR__SHIFT                                                                         0x6
#define SQ_WATCH1_ADDR_L__ADDR_MASK                                                                           0xFFFFFFC0L
//SQ_WATCH1_CNTL
#define SQ_WATCH1_CNTL__MASK__SHIFT                                                                           0x0
#define SQ_WATCH1_CNTL__VMID__SHIFT                                                                           0x18
#define SQ_WATCH1_CNTL__VALID__SHIFT                                                                          0x1f
#define SQ_WATCH1_CNTL__MASK_MASK                                                                             0x00FFFFFFL
#define SQ_WATCH1_CNTL__VMID_MASK                                                                             0x0F000000L
#define SQ_WATCH1_CNTL__VALID_MASK                                                                            0x80000000L
//SQ_WATCH2_ADDR_H
#define SQ_WATCH2_ADDR_H__ADDR__SHIFT                                                                         0x0
#define SQ_WATCH2_ADDR_H__ADDR_MASK                                                                           0x0000FFFFL
//SQ_WATCH2_ADDR_L
#define SQ_WATCH2_ADDR_L__ADDR__SHIFT                                                                         0x6
#define SQ_WATCH2_ADDR_L__ADDR_MASK                                                                           0xFFFFFFC0L
//SQ_WATCH2_CNTL
#define SQ_WATCH2_CNTL__MASK__SHIFT                                                                           0x0
#define SQ_WATCH2_CNTL__VMID__SHIFT                                                                           0x18
#define SQ_WATCH2_CNTL__VALID__SHIFT                                                                          0x1f
#define SQ_WATCH2_CNTL__MASK_MASK                                                                             0x00FFFFFFL
#define SQ_WATCH2_CNTL__VMID_MASK                                                                             0x0F000000L
#define SQ_WATCH2_CNTL__VALID_MASK                                                                            0x80000000L
//SQ_WATCH3_ADDR_H
#define SQ_WATCH3_ADDR_H__ADDR__SHIFT                                                                         0x0
#define SQ_WATCH3_ADDR_H__ADDR_MASK                                                                           0x0000FFFFL
//SQ_WATCH3_ADDR_L
#define SQ_WATCH3_ADDR_L__ADDR__SHIFT                                                                         0x6
#define SQ_WATCH3_ADDR_L__ADDR_MASK                                                                           0xFFFFFFC0L
//SQ_WATCH3_CNTL
#define SQ_WATCH3_CNTL__MASK__SHIFT                                                                           0x0
#define SQ_WATCH3_CNTL__VMID__SHIFT                                                                           0x18
#define SQ_WATCH3_CNTL__VALID__SHIFT                                                                          0x1f
#define SQ_WATCH3_CNTL__MASK_MASK                                                                             0x00FFFFFFL
#define SQ_WATCH3_CNTL__VMID_MASK                                                                             0x0F000000L
#define SQ_WATCH3_CNTL__VALID_MASK                                                                            0x80000000L
//SQ_THREAD_TRACE_BUF0_BASE
#define SQ_THREAD_TRACE_BUF0_BASE__BASE_LO__SHIFT                                                             0x0
#define SQ_THREAD_TRACE_BUF0_BASE__BASE_LO_MASK                                                               0xFFFFFFFFL
//SQ_THREAD_TRACE_BUF0_SIZE
#define SQ_THREAD_TRACE_BUF0_SIZE__BASE_HI__SHIFT                                                             0x0
#define SQ_THREAD_TRACE_BUF0_SIZE__SIZE__SHIFT                                                                0x8
#define SQ_THREAD_TRACE_BUF0_SIZE__BASE_HI_MASK                                                               0x0000000FL
#define SQ_THREAD_TRACE_BUF0_SIZE__SIZE_MASK                                                                  0x3FFFFF00L
//SQ_THREAD_TRACE_BUF1_BASE
#define SQ_THREAD_TRACE_BUF1_BASE__BASE_LO__SHIFT                                                             0x0
#define SQ_THREAD_TRACE_BUF1_BASE__BASE_LO_MASK                                                               0xFFFFFFFFL
//SQ_THREAD_TRACE_BUF1_SIZE
#define SQ_THREAD_TRACE_BUF1_SIZE__BASE_HI__SHIFT                                                             0x0
#define SQ_THREAD_TRACE_BUF1_SIZE__SIZE__SHIFT                                                                0x8
#define SQ_THREAD_TRACE_BUF1_SIZE__BASE_HI_MASK                                                               0x0000000FL
#define SQ_THREAD_TRACE_BUF1_SIZE__SIZE_MASK                                                                  0x3FFFFF00L
//SQ_THREAD_TRACE_WPTR
#define SQ_THREAD_TRACE_WPTR__OFFSET__SHIFT                                                                   0x0
#define SQ_THREAD_TRACE_WPTR__BUFFER_ID__SHIFT                                                                0x1f
#define SQ_THREAD_TRACE_WPTR__OFFSET_MASK                                                                     0x1FFFFFFFL
#define SQ_THREAD_TRACE_WPTR__BUFFER_ID_MASK                                                                  0x80000000L
//SQ_THREAD_TRACE_MASK
#define SQ_THREAD_TRACE_MASK__SIMD_SEL__SHIFT                                                                 0x0
#define SQ_THREAD_TRACE_MASK__WGP_SEL__SHIFT                                                                  0x4
#define SQ_THREAD_TRACE_MASK__SA_SEL__SHIFT                                                                   0x9
#define SQ_THREAD_TRACE_MASK__WTYPE_INCLUDE__SHIFT                                                            0xa
#define SQ_THREAD_TRACE_MASK__SIMD_SEL_MASK                                                                   0x00000003L
#define SQ_THREAD_TRACE_MASK__WGP_SEL_MASK                                                                    0x000000F0L
#define SQ_THREAD_TRACE_MASK__SA_SEL_MASK                                                                     0x00000200L
#define SQ_THREAD_TRACE_MASK__WTYPE_INCLUDE_MASK                                                              0x0001FC00L
//SQ_THREAD_TRACE_TOKEN_MASK
#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_EXCLUDE__SHIFT                                                      0x0
#define SQ_THREAD_TRACE_TOKEN_MASK__BOP_EVENTS_TOKEN_INCLUDE__SHIFT                                           0xc
#define SQ_THREAD_TRACE_TOKEN_MASK__REG_INCLUDE__SHIFT                                                        0x10
#define SQ_THREAD_TRACE_TOKEN_MASK__INST_EXCLUDE__SHIFT                                                       0x18
#define SQ_THREAD_TRACE_TOKEN_MASK__REG_EXCLUDE__SHIFT                                                        0x1a
#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DETAIL_ALL__SHIFT                                                     0x1f
#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_EXCLUDE_MASK                                                        0x000007FFL
#define SQ_THREAD_TRACE_TOKEN_MASK__BOP_EVENTS_TOKEN_INCLUDE_MASK                                             0x00001000L
#define SQ_THREAD_TRACE_TOKEN_MASK__REG_INCLUDE_MASK                                                          0x00FF0000L
#define SQ_THREAD_TRACE_TOKEN_MASK__INST_EXCLUDE_MASK                                                         0x03000000L
#define SQ_THREAD_TRACE_TOKEN_MASK__REG_EXCLUDE_MASK                                                          0x1C000000L
#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DETAIL_ALL_MASK                                                       0x80000000L
//SQ_THREAD_TRACE_CTRL
#define SQ_THREAD_TRACE_CTRL__MODE__SHIFT                                                                     0x0
#define SQ_THREAD_TRACE_CTRL__ALL_VMID__SHIFT                                                                 0x2
#define SQ_THREAD_TRACE_CTRL__CH_PERF_EN__SHIFT                                                               0x3
#define SQ_THREAD_TRACE_CTRL__INTERRUPT_EN__SHIFT                                                             0x4
#define SQ_THREAD_TRACE_CTRL__DOUBLE_BUFFER__SHIFT                                                            0x5
#define SQ_THREAD_TRACE_CTRL__HIWATER__SHIFT                                                                  0x6
#define SQ_THREAD_TRACE_CTRL__REG_STALL_EN__SHIFT                                                             0x9
#define SQ_THREAD_TRACE_CTRL__SPI_STALL_EN__SHIFT                                                             0xa
#define SQ_THREAD_TRACE_CTRL__SQ_STALL_EN__SHIFT                                                              0xb
#define SQ_THREAD_TRACE_CTRL__REG_DROP_ON_STALL__SHIFT                                                        0xc
#define SQ_THREAD_TRACE_CTRL__UTIL_TIMER__SHIFT                                                               0xd
#define SQ_THREAD_TRACE_CTRL__WAVESTART_MODE__SHIFT                                                           0xe
#define SQ_THREAD_TRACE_CTRL__RT_FREQ__SHIFT                                                                  0x10
#define SQ_THREAD_TRACE_CTRL__SYNC_COUNT_MARKERS__SHIFT                                                       0x12
#define SQ_THREAD_TRACE_CTRL__SYNC_COUNT_DRAWS__SHIFT                                                         0x13
#define SQ_THREAD_TRACE_CTRL__LOWATER_OFFSET__SHIFT                                                           0x14
#define SQ_THREAD_TRACE_CTRL__AUTO_FLUSH_PADDING_DIS__SHIFT                                                   0x1c
#define SQ_THREAD_TRACE_CTRL__AUTO_FLUSH_MODE__SHIFT                                                          0x1d
#define SQ_THREAD_TRACE_CTRL__CAPTURE_ALL__SHIFT                                                              0x1e
#define SQ_THREAD_TRACE_CTRL__DRAW_EVENT_EN__SHIFT                                                            0x1f
#define SQ_THREAD_TRACE_CTRL__MODE_MASK                                                                       0x00000003L
#define SQ_THREAD_TRACE_CTRL__ALL_VMID_MASK                                                                   0x00000004L
#define SQ_THREAD_TRACE_CTRL__CH_PERF_EN_MASK                                                                 0x00000008L
#define SQ_THREAD_TRACE_CTRL__INTERRUPT_EN_MASK                                                               0x00000010L
#define SQ_THREAD_TRACE_CTRL__DOUBLE_BUFFER_MASK                                                              0x00000020L
#define SQ_THREAD_TRACE_CTRL__HIWATER_MASK                                                                    0x000001C0L
#define SQ_THREAD_TRACE_CTRL__REG_STALL_EN_MASK                                                               0x00000200L
#define SQ_THREAD_TRACE_CTRL__SPI_STALL_EN_MASK                                                               0x00000400L
#define SQ_THREAD_TRACE_CTRL__SQ_STALL_EN_MASK                                                                0x00000800L
#define SQ_THREAD_TRACE_CTRL__REG_DROP_ON_STALL_MASK                                                          0x00001000L
#define SQ_THREAD_TRACE_CTRL__UTIL_TIMER_MASK                                                                 0x00002000L
#define SQ_THREAD_TRACE_CTRL__WAVESTART_MODE_MASK                                                             0x0000C000L
#define SQ_THREAD_TRACE_CTRL__RT_FREQ_MASK                                                                    0x00030000L
#define SQ_THREAD_TRACE_CTRL__SYNC_COUNT_MARKERS_MASK                                                         0x00040000L
#define SQ_THREAD_TRACE_CTRL__SYNC_COUNT_DRAWS_MASK                                                           0x00080000L
#define SQ_THREAD_TRACE_CTRL__LOWATER_OFFSET_MASK                                                             0x00700000L
#define SQ_THREAD_TRACE_CTRL__AUTO_FLUSH_PADDING_DIS_MASK                                                     0x10000000L
#define SQ_THREAD_TRACE_CTRL__AUTO_FLUSH_MODE_MASK                                                            0x20000000L
#define SQ_THREAD_TRACE_CTRL__CAPTURE_ALL_MASK                                                                0x40000000L
#define SQ_THREAD_TRACE_CTRL__DRAW_EVENT_EN_MASK                                                              0x80000000L
//SQ_THREAD_TRACE_STATUS
#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING__SHIFT                                                         0x0
#define SQ_THREAD_TRACE_STATUS__FINISH_DONE__SHIFT                                                            0xc
#define SQ_THREAD_TRACE_STATUS__UTC_ERR__SHIFT                                                                0x18
#define SQ_THREAD_TRACE_STATUS__BUSY__SHIFT                                                                   0x19
#define SQ_THREAD_TRACE_STATUS__EVENT_CNTR_OVERFLOW__SHIFT                                                    0x1a
#define SQ_THREAD_TRACE_STATUS__EVENT_CNTR_STALL__SHIFT                                                       0x1b
#define SQ_THREAD_TRACE_STATUS__OWNER_VMID__SHIFT                                                             0x1c
#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING_MASK                                                           0x00000FFFL
#define SQ_THREAD_TRACE_STATUS__FINISH_DONE_MASK                                                              0x00FFF000L
#define SQ_THREAD_TRACE_STATUS__UTC_ERR_MASK                                                                  0x01000000L
#define SQ_THREAD_TRACE_STATUS__BUSY_MASK                                                                     0x02000000L
#define SQ_THREAD_TRACE_STATUS__EVENT_CNTR_OVERFLOW_MASK                                                      0x04000000L
#define SQ_THREAD_TRACE_STATUS__EVENT_CNTR_STALL_MASK                                                         0x08000000L
#define SQ_THREAD_TRACE_STATUS__OWNER_VMID_MASK                                                               0xF0000000L
//SQ_THREAD_TRACE_DROPPED_CNTR
#define SQ_THREAD_TRACE_DROPPED_CNTR__CNTR__SHIFT                                                             0x0
#define SQ_THREAD_TRACE_DROPPED_CNTR__CNTR_MASK                                                               0xFFFFFFFFL
//SQ_THREAD_TRACE_GFX_DRAW_CNTR
#define SQ_THREAD_TRACE_GFX_DRAW_CNTR__CNTR__SHIFT                                                            0x0
#define SQ_THREAD_TRACE_GFX_DRAW_CNTR__CNTR_MASK                                                              0xFFFFFFFFL
//SQ_THREAD_TRACE_GFX_MARKER_CNTR
#define SQ_THREAD_TRACE_GFX_MARKER_CNTR__CNTR__SHIFT                                                          0x0
#define SQ_THREAD_TRACE_GFX_MARKER_CNTR__CNTR_MASK                                                            0xFFFFFFFFL
//SQ_THREAD_TRACE_HP3D_DRAW_CNTR
#define SQ_THREAD_TRACE_HP3D_DRAW_CNTR__CNTR__SHIFT                                                           0x0
#define SQ_THREAD_TRACE_HP3D_DRAW_CNTR__CNTR_MASK                                                             0xFFFFFFFFL
//SQ_THREAD_TRACE_HP3D_MARKER_CNTR
#define SQ_THREAD_TRACE_HP3D_MARKER_CNTR__CNTR__SHIFT                                                         0x0
#define SQ_THREAD_TRACE_HP3D_MARKER_CNTR__CNTR_MASK                                                           0xFFFFFFFFL
//SQ_THREAD_TRACE_STATUS2
#define SQ_THREAD_TRACE_STATUS2__BUF0_FULL__SHIFT                                                             0x0
#define SQ_THREAD_TRACE_STATUS2__BUF1_FULL__SHIFT                                                             0x1
#define SQ_THREAD_TRACE_STATUS2__PACKET_LOST_BUF_NO_LOCKDOWN__SHIFT                                           0x4
#define SQ_THREAD_TRACE_STATUS2__BUF0_FULL_MASK                                                               0x00000001L
#define SQ_THREAD_TRACE_STATUS2__BUF1_FULL_MASK                                                               0x00000002L
#define SQ_THREAD_TRACE_STATUS2__PACKET_LOST_BUF_NO_LOCKDOWN_MASK                                             0x00000010L
//SQ_IND_INDEX
#define SQ_IND_INDEX__WAVE_ID__SHIFT                                                                          0x0
#define SQ_IND_INDEX__WORKITEM_ID__SHIFT                                                                      0x5
#define SQ_IND_INDEX__AUTO_INCR__SHIFT                                                                        0xb
#define SQ_IND_INDEX__INDEX__SHIFT                                                                            0x10
#define SQ_IND_INDEX__WAVE_ID_MASK                                                                            0x0000001FL
#define SQ_IND_INDEX__WORKITEM_ID_MASK                                                                        0x000007E0L
#define SQ_IND_INDEX__AUTO_INCR_MASK                                                                          0x00000800L
#define SQ_IND_INDEX__INDEX_MASK                                                                              0xFFFF0000L
//SQ_IND_DATA
#define SQ_IND_DATA__DATA__SHIFT                                                                              0x0
#define SQ_IND_DATA__DATA_MASK                                                                                0xFFFFFFFFL
//SQ_CMD
#define SQ_CMD__CMD__SHIFT                                                                                    0x0
#define SQ_CMD__MODE__SHIFT                                                                                   0x4
#define SQ_CMD__CHECK_VMID__SHIFT                                                                             0x7
#define SQ_CMD__DATA__SHIFT                                                                                   0x8
#define SQ_CMD__WAVE_ID__SHIFT                                                                                0x10
#define SQ_CMD__QUEUE_ID__SHIFT                                                                               0x18
#define SQ_CMD__VM_ID__SHIFT                                                                                  0x1c
#define SQ_CMD__CMD_MASK                                                                                      0x0000000FL
#define SQ_CMD__MODE_MASK                                                                                     0x00000070L
#define SQ_CMD__CHECK_VMID_MASK                                                                               0x00000080L
#define SQ_CMD__DATA_MASK                                                                                     0x00000F00L
#define SQ_CMD__WAVE_ID_MASK                                                                                  0x001F0000L
#define SQ_CMD__QUEUE_ID_MASK                                                                                 0x07000000L
#define SQ_CMD__VM_ID_MASK                                                                                    0xF0000000L
//SQ_TIME_HI
#define SQ_TIME_HI__TIME__SHIFT                                                                               0x0
#define SQ_TIME_HI__TIME_MASK                                                                                 0xFFFFFFFFL
//SQ_TIME_LO
#define SQ_TIME_LO__TIME__SHIFT                                                                               0x0
#define SQ_TIME_LO__TIME_MASK                                                                                 0xFFFFFFFFL
//SQ_LB_CTR_CTRL
#define SQ_LB_CTR_CTRL__START__SHIFT                                                                          0x0
#define SQ_LB_CTR_CTRL__LOAD__SHIFT                                                                           0x1
#define SQ_LB_CTR_CTRL__CLEAR__SHIFT                                                                          0x2
#define SQ_LB_CTR_CTRL__START_MASK                                                                            0x00000001L
#define SQ_LB_CTR_CTRL__LOAD_MASK                                                                             0x00000002L
#define SQ_LB_CTR_CTRL__CLEAR_MASK                                                                            0x00000004L
//SQ_LB_DATA0
#define SQ_LB_DATA0__DATA__SHIFT                                                                              0x0
#define SQ_LB_DATA0__DATA_MASK                                                                                0xFFFFFFFFL
//SQ_LB_DATA1
#define SQ_LB_DATA1__DATA__SHIFT                                                                              0x0
#define SQ_LB_DATA1__DATA_MASK                                                                                0xFFFFFFFFL
//SQ_LB_DATA2
#define SQ_LB_DATA2__DATA__SHIFT                                                                              0x0
#define SQ_LB_DATA2__DATA_MASK                                                                                0xFFFFFFFFL
//SQ_LB_DATA3
#define SQ_LB_DATA3__DATA__SHIFT                                                                              0x0
#define SQ_LB_DATA3__DATA_MASK                                                                                0xFFFFFFFFL
//SQ_LB_CTR_SEL0
#define SQ_LB_CTR_SEL0__SEL0__SHIFT                                                                           0x0
#define SQ_LB_CTR_SEL0__DIV0__SHIFT                                                                           0xf
#define SQ_LB_CTR_SEL0__SEL1__SHIFT                                                                           0x10
#define SQ_LB_CTR_SEL0__DIV1__SHIFT                                                                           0x1f
#define SQ_LB_CTR_SEL0__SEL0_MASK                                                                             0x000000FFL
#define SQ_LB_CTR_SEL0__DIV0_MASK                                                                             0x00008000L
#define SQ_LB_CTR_SEL0__SEL1_MASK                                                                             0x00FF0000L
#define SQ_LB_CTR_SEL0__DIV1_MASK                                                                             0x80000000L
//SQ_LB_CTR_SEL1
#define SQ_LB_CTR_SEL1__SEL2__SHIFT                                                                           0x0
#define SQ_LB_CTR_SEL1__DIV2__SHIFT                                                                           0xf
#define SQ_LB_CTR_SEL1__SEL3__SHIFT                                                                           0x10
#define SQ_LB_CTR_SEL1__DIV3__SHIFT                                                                           0x1f
#define SQ_LB_CTR_SEL1__SEL2_MASK                                                                             0x000000FFL
#define SQ_LB_CTR_SEL1__DIV2_MASK                                                                             0x00008000L
#define SQ_LB_CTR_SEL1__SEL3_MASK                                                                             0x00FF0000L
#define SQ_LB_CTR_SEL1__DIV3_MASK                                                                             0x80000000L
//SQ_EDC_CNT
#define SQ_EDC_CNT__LDS_D_SEC_COUNT__SHIFT                                                                    0x0
#define SQ_EDC_CNT__LDS_D_DED_COUNT__SHIFT                                                                    0x2
#define SQ_EDC_CNT__LDS_I_SEC_COUNT__SHIFT                                                                    0x4
#define SQ_EDC_CNT__LDS_I_DED_COUNT__SHIFT                                                                    0x6
#define SQ_EDC_CNT__SGPR_SEC_COUNT__SHIFT                                                                     0x8
#define SQ_EDC_CNT__SGPR_DED_COUNT__SHIFT                                                                     0xa
#define SQ_EDC_CNT__VGPR0_SEC_COUNT__SHIFT                                                                    0xc
#define SQ_EDC_CNT__VGPR0_DED_COUNT__SHIFT                                                                    0xe
#define SQ_EDC_CNT__VGPR1_SEC_COUNT__SHIFT                                                                    0x10
#define SQ_EDC_CNT__VGPR1_DED_COUNT__SHIFT                                                                    0x12
#define SQ_EDC_CNT__VGPR2_SEC_COUNT__SHIFT                                                                    0x14
#define SQ_EDC_CNT__VGPR2_DED_COUNT__SHIFT                                                                    0x16
#define SQ_EDC_CNT__VGPR3_SEC_COUNT__SHIFT                                                                    0x18
#define SQ_EDC_CNT__VGPR3_DED_COUNT__SHIFT                                                                    0x1a
#define SQ_EDC_CNT__LDS_D_SEC_COUNT_MASK                                                                      0x00000003L
#define SQ_EDC_CNT__LDS_D_DED_COUNT_MASK                                                                      0x0000000CL
#define SQ_EDC_CNT__LDS_I_SEC_COUNT_MASK                                                                      0x00000030L
#define SQ_EDC_CNT__LDS_I_DED_COUNT_MASK                                                                      0x000000C0L
#define SQ_EDC_CNT__SGPR_SEC_COUNT_MASK                                                                       0x00000300L
#define SQ_EDC_CNT__SGPR_DED_COUNT_MASK                                                                       0x00000C00L
#define SQ_EDC_CNT__VGPR0_SEC_COUNT_MASK                                                                      0x00003000L
#define SQ_EDC_CNT__VGPR0_DED_COUNT_MASK                                                                      0x0000C000L
#define SQ_EDC_CNT__VGPR1_SEC_COUNT_MASK                                                                      0x00030000L
#define SQ_EDC_CNT__VGPR1_DED_COUNT_MASK                                                                      0x000C0000L
#define SQ_EDC_CNT__VGPR2_SEC_COUNT_MASK                                                                      0x00300000L
#define SQ_EDC_CNT__VGPR2_DED_COUNT_MASK                                                                      0x00C00000L
#define SQ_EDC_CNT__VGPR3_SEC_COUNT_MASK                                                                      0x03000000L
#define SQ_EDC_CNT__VGPR3_DED_COUNT_MASK                                                                      0x0C000000L
//SQ_EDC_FUE_CNTL
#define SQ_EDC_FUE_CNTL__BLOCK_FUE_FLAGS__SHIFT                                                               0x0
#define SQ_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES__SHIFT                                                         0x10
#define SQ_EDC_FUE_CNTL__BLOCK_FUE_FLAGS_MASK                                                                 0x0000FFFFL
#define SQ_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES_MASK                                                           0xFFFF0000L
//SQ_WREXEC_EXEC_HI
#define SQ_WREXEC_EXEC_HI__ADDR_HI__SHIFT                                                                     0x0
#define SQ_WREXEC_EXEC_HI__FIRST_WAVE__SHIFT                                                                  0x1a
#define SQ_WREXEC_EXEC_HI__MTYPE__SHIFT                                                                       0x1c
#define SQ_WREXEC_EXEC_HI__MSB__SHIFT                                                                         0x1f
#define SQ_WREXEC_EXEC_HI__ADDR_HI_MASK                                                                       0x0000FFFFL
#define SQ_WREXEC_EXEC_HI__FIRST_WAVE_MASK                                                                    0x04000000L
#define SQ_WREXEC_EXEC_HI__MTYPE_MASK                                                                         0x70000000L
#define SQ_WREXEC_EXEC_HI__MSB_MASK                                                                           0x80000000L
//SQ_WREXEC_EXEC_LO
#define SQ_WREXEC_EXEC_LO__ADDR_LO__SHIFT                                                                     0x0
#define SQ_WREXEC_EXEC_LO__ADDR_LO_MASK                                                                       0xFFFFFFFFL
//SQC_ICACHE_UTCL0_CNTL1
#define SQC_ICACHE_UTCL0_CNTL1__FORCE_4K_L2_RESP__SHIFT                                                       0x0
#define SQC_ICACHE_UTCL0_CNTL1__GPUVM_64K_DEF__SHIFT                                                          0x1
#define SQC_ICACHE_UTCL0_CNTL1__GPUVM_PERM_MODE__SHIFT                                                        0x2
#define SQC_ICACHE_UTCL0_CNTL1__RESP_MODE__SHIFT                                                              0x3
#define SQC_ICACHE_UTCL0_CNTL1__RESP_FAULT_MODE__SHIFT                                                        0x5
#define SQC_ICACHE_UTCL0_CNTL1__CLIENTID__SHIFT                                                               0x7
#define SQC_ICACHE_UTCL0_CNTL1__ENABLE_PUSH_LFIFO__SHIFT                                                      0x11
#define SQC_ICACHE_UTCL0_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT                                                   0x12
#define SQC_ICACHE_UTCL0_CNTL1__REG_INV_VMID__SHIFT                                                           0x13
#define SQC_ICACHE_UTCL0_CNTL1__REG_INV_ALL_VMID__SHIFT                                                       0x17
#define SQC_ICACHE_UTCL0_CNTL1__REG_INV_TOGGLE__SHIFT                                                         0x18
#define SQC_ICACHE_UTCL0_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT                                             0x19
#define SQC_ICACHE_UTCL0_CNTL1__FORCE_MISS__SHIFT                                                             0x1a
#define SQC_ICACHE_UTCL0_CNTL1__FORCE_IN_ORDER__SHIFT                                                         0x1b
#define SQC_ICACHE_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT                                                 0x1c
#define SQC_ICACHE_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT                                                 0x1e
#define SQC_ICACHE_UTCL0_CNTL1__FORCE_4K_L2_RESP_MASK                                                         0x00000001L
#define SQC_ICACHE_UTCL0_CNTL1__GPUVM_64K_DEF_MASK                                                            0x00000002L
#define SQC_ICACHE_UTCL0_CNTL1__GPUVM_PERM_MODE_MASK                                                          0x00000004L
#define SQC_ICACHE_UTCL0_CNTL1__RESP_MODE_MASK                                                                0x00000018L
#define SQC_ICACHE_UTCL0_CNTL1__RESP_FAULT_MODE_MASK                                                          0x00000060L
#define SQC_ICACHE_UTCL0_CNTL1__CLIENTID_MASK                                                                 0x0000FF80L
#define SQC_ICACHE_UTCL0_CNTL1__ENABLE_PUSH_LFIFO_MASK                                                        0x00020000L
#define SQC_ICACHE_UTCL0_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK                                                     0x00040000L
#define SQC_ICACHE_UTCL0_CNTL1__REG_INV_VMID_MASK                                                             0x00780000L
#define SQC_ICACHE_UTCL0_CNTL1__REG_INV_ALL_VMID_MASK                                                         0x00800000L
#define SQC_ICACHE_UTCL0_CNTL1__REG_INV_TOGGLE_MASK                                                           0x01000000L
#define SQC_ICACHE_UTCL0_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK                                               0x02000000L
#define SQC_ICACHE_UTCL0_CNTL1__FORCE_MISS_MASK                                                               0x04000000L
#define SQC_ICACHE_UTCL0_CNTL1__FORCE_IN_ORDER_MASK                                                           0x08000000L
#define SQC_ICACHE_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK                                                   0x30000000L
#define SQC_ICACHE_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK                                                   0xC0000000L
//SQC_ICACHE_UTCL0_CNTL2
#define SQC_ICACHE_UTCL0_CNTL2__SPARE__SHIFT                                                                  0x0
#define SQC_ICACHE_UTCL0_CNTL2__LFIFO_SCAN_DISABLE__SHIFT                                                     0x8
#define SQC_ICACHE_UTCL0_CNTL2__MTYPE_OVRD_DIS__SHIFT                                                         0x9
#define SQC_ICACHE_UTCL0_CNTL2__LINE_VALID__SHIFT                                                             0xa
#define SQC_ICACHE_UTCL0_CNTL2__DIS_EDC__SHIFT                                                                0xb
#define SQC_ICACHE_UTCL0_CNTL2__GPUVM_INV_MODE__SHIFT                                                         0xc
#define SQC_ICACHE_UTCL0_CNTL2__SHOOTDOWN_OPT__SHIFT                                                          0xd
#define SQC_ICACHE_UTCL0_CNTL2__FORCE_SNOOP__SHIFT                                                            0xe
#define SQC_ICACHE_UTCL0_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT                                                    0xf
#define SQC_ICACHE_UTCL0_CNTL2__ARB_BURST_MODE__SHIFT                                                         0x10
#define SQC_ICACHE_UTCL0_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT                                                0x12
#define SQC_ICACHE_UTCL0_CNTL2__PERF_EVENT_RD_WR__SHIFT                                                       0x13
#define SQC_ICACHE_UTCL0_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT                                                 0x14
#define SQC_ICACHE_UTCL0_CNTL2__PERF_EVENT_VMID__SHIFT                                                        0x15
#define SQC_ICACHE_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT                                                   0x1a
#define SQC_ICACHE_UTCL0_CNTL2__PERM_MODE_OVRD__SHIFT                                                         0x1b
#define SQC_ICACHE_UTCL0_CNTL2__LINE_INVALIDATE_OPT__SHIFT                                                    0x1c
#define SQC_ICACHE_UTCL0_CNTL2__GPUVM_16K_DEF__SHIFT                                                          0x1d
#define SQC_ICACHE_UTCL0_CNTL2__FGCG_DISABLE__SHIFT                                                           0x1e
#define SQC_ICACHE_UTCL0_CNTL2__SPARE_MASK                                                                    0x000000FFL
#define SQC_ICACHE_UTCL0_CNTL2__LFIFO_SCAN_DISABLE_MASK                                                       0x00000100L
#define SQC_ICACHE_UTCL0_CNTL2__MTYPE_OVRD_DIS_MASK                                                           0x00000200L
#define SQC_ICACHE_UTCL0_CNTL2__LINE_VALID_MASK                                                               0x00000400L
#define SQC_ICACHE_UTCL0_CNTL2__DIS_EDC_MASK                                                                  0x00000800L
#define SQC_ICACHE_UTCL0_CNTL2__GPUVM_INV_MODE_MASK                                                           0x00001000L
#define SQC_ICACHE_UTCL0_CNTL2__SHOOTDOWN_OPT_MASK                                                            0x00002000L
#define SQC_ICACHE_UTCL0_CNTL2__FORCE_SNOOP_MASK                                                              0x00004000L
#define SQC_ICACHE_UTCL0_CNTL2__FORCE_GPUVM_INV_ACK_MASK                                                      0x00008000L
#define SQC_ICACHE_UTCL0_CNTL2__ARB_BURST_MODE_MASK                                                           0x00030000L
#define SQC_ICACHE_UTCL0_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK                                                  0x00040000L
#define SQC_ICACHE_UTCL0_CNTL2__PERF_EVENT_RD_WR_MASK                                                         0x00080000L
#define SQC_ICACHE_UTCL0_CNTL2__ENABLE_PERF_EVENT_VMID_MASK                                                   0x00100000L
#define SQC_ICACHE_UTCL0_CNTL2__PERF_EVENT_VMID_MASK                                                          0x01E00000L
#define SQC_ICACHE_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K_MASK                                                     0x04000000L
#define SQC_ICACHE_UTCL0_CNTL2__PERM_MODE_OVRD_MASK                                                           0x08000000L
#define SQC_ICACHE_UTCL0_CNTL2__LINE_INVALIDATE_OPT_MASK                                                      0x10000000L
#define SQC_ICACHE_UTCL0_CNTL2__GPUVM_16K_DEF_MASK                                                            0x20000000L
#define SQC_ICACHE_UTCL0_CNTL2__FGCG_DISABLE_MASK                                                             0x40000000L
//SQC_DCACHE_UTCL0_CNTL1
#define SQC_DCACHE_UTCL0_CNTL1__FORCE_4K_L2_RESP__SHIFT                                                       0x0
#define SQC_DCACHE_UTCL0_CNTL1__GPUVM_64K_DEF__SHIFT                                                          0x1
#define SQC_DCACHE_UTCL0_CNTL1__GPUVM_PERM_MODE__SHIFT                                                        0x2
#define SQC_DCACHE_UTCL0_CNTL1__RESP_MODE__SHIFT                                                              0x3
#define SQC_DCACHE_UTCL0_CNTL1__RESP_FAULT_MODE__SHIFT                                                        0x5
#define SQC_DCACHE_UTCL0_CNTL1__CLIENTID__SHIFT                                                               0x7
#define SQC_DCACHE_UTCL0_CNTL1__ENABLE_PUSH_LFIFO__SHIFT                                                      0x11
#define SQC_DCACHE_UTCL0_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT                                                   0x12
#define SQC_DCACHE_UTCL0_CNTL1__REG_INV_VMID__SHIFT                                                           0x13
#define SQC_DCACHE_UTCL0_CNTL1__REG_INV_ALL_VMID__SHIFT                                                       0x17
#define SQC_DCACHE_UTCL0_CNTL1__REG_INV_TOGGLE__SHIFT                                                         0x18
#define SQC_DCACHE_UTCL0_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT                                             0x19
#define SQC_DCACHE_UTCL0_CNTL1__FORCE_MISS__SHIFT                                                             0x1a
#define SQC_DCACHE_UTCL0_CNTL1__FORCE_IN_ORDER__SHIFT                                                         0x1b
#define SQC_DCACHE_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT                                                 0x1c
#define SQC_DCACHE_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT                                                 0x1e
#define SQC_DCACHE_UTCL0_CNTL1__FORCE_4K_L2_RESP_MASK                                                         0x00000001L
#define SQC_DCACHE_UTCL0_CNTL1__GPUVM_64K_DEF_MASK                                                            0x00000002L
#define SQC_DCACHE_UTCL0_CNTL1__GPUVM_PERM_MODE_MASK                                                          0x00000004L
#define SQC_DCACHE_UTCL0_CNTL1__RESP_MODE_MASK                                                                0x00000018L
#define SQC_DCACHE_UTCL0_CNTL1__RESP_FAULT_MODE_MASK                                                          0x00000060L
#define SQC_DCACHE_UTCL0_CNTL1__CLIENTID_MASK                                                                 0x0000FF80L
#define SQC_DCACHE_UTCL0_CNTL1__ENABLE_PUSH_LFIFO_MASK                                                        0x00020000L
#define SQC_DCACHE_UTCL0_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK                                                     0x00040000L
#define SQC_DCACHE_UTCL0_CNTL1__REG_INV_VMID_MASK                                                             0x00780000L
#define SQC_DCACHE_UTCL0_CNTL1__REG_INV_ALL_VMID_MASK                                                         0x00800000L
#define SQC_DCACHE_UTCL0_CNTL1__REG_INV_TOGGLE_MASK                                                           0x01000000L
#define SQC_DCACHE_UTCL0_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK                                               0x02000000L
#define SQC_DCACHE_UTCL0_CNTL1__FORCE_MISS_MASK                                                               0x04000000L
#define SQC_DCACHE_UTCL0_CNTL1__FORCE_IN_ORDER_MASK                                                           0x08000000L
#define SQC_DCACHE_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK                                                   0x30000000L
#define SQC_DCACHE_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK                                                   0xC0000000L
//SQC_DCACHE_UTCL0_CNTL2
#define SQC_DCACHE_UTCL0_CNTL2__SPARE__SHIFT                                                                  0x0
#define SQC_DCACHE_UTCL0_CNTL2__LFIFO_SCAN_DISABLE__SHIFT                                                     0x8
#define SQC_DCACHE_UTCL0_CNTL2__MTYPE_OVRD_DIS__SHIFT                                                         0x9
#define SQC_DCACHE_UTCL0_CNTL2__LINE_VALID__SHIFT                                                             0xa
#define SQC_DCACHE_UTCL0_CNTL2__DIS_EDC__SHIFT                                                                0xb
#define SQC_DCACHE_UTCL0_CNTL2__GPUVM_INV_MODE__SHIFT                                                         0xc
#define SQC_DCACHE_UTCL0_CNTL2__SHOOTDOWN_OPT__SHIFT                                                          0xd
#define SQC_DCACHE_UTCL0_CNTL2__FORCE_SNOOP__SHIFT                                                            0xe
#define SQC_DCACHE_UTCL0_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT                                                    0xf
#define SQC_DCACHE_UTCL0_CNTL2__ARB_BURST_MODE__SHIFT                                                         0x10
#define SQC_DCACHE_UTCL0_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT                                                0x12
#define SQC_DCACHE_UTCL0_CNTL2__PERF_EVENT_RD_WR__SHIFT                                                       0x13
#define SQC_DCACHE_UTCL0_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT                                                 0x14
#define SQC_DCACHE_UTCL0_CNTL2__PERF_EVENT_VMID__SHIFT                                                        0x15
#define SQC_DCACHE_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT                                                   0x1a
#define SQC_DCACHE_UTCL0_CNTL2__PERM_MODE_OVRD__SHIFT                                                         0x1b
#define SQC_DCACHE_UTCL0_CNTL2__LINE_INVALIDATE_OPT__SHIFT                                                    0x1c
#define SQC_DCACHE_UTCL0_CNTL2__GPUVM_16K_DEF__SHIFT                                                          0x1d
#define SQC_DCACHE_UTCL0_CNTL2__FGCG_DISABLE__SHIFT                                                           0x1e
#define SQC_DCACHE_UTCL0_CNTL2__SPARE_MASK                                                                    0x000000FFL
#define SQC_DCACHE_UTCL0_CNTL2__LFIFO_SCAN_DISABLE_MASK                                                       0x00000100L
#define SQC_DCACHE_UTCL0_CNTL2__MTYPE_OVRD_DIS_MASK                                                           0x00000200L
#define SQC_DCACHE_UTCL0_CNTL2__LINE_VALID_MASK                                                               0x00000400L
#define SQC_DCACHE_UTCL0_CNTL2__DIS_EDC_MASK                                                                  0x00000800L
#define SQC_DCACHE_UTCL0_CNTL2__GPUVM_INV_MODE_MASK                                                           0x00001000L
#define SQC_DCACHE_UTCL0_CNTL2__SHOOTDOWN_OPT_MASK                                                            0x00002000L
#define SQC_DCACHE_UTCL0_CNTL2__FORCE_SNOOP_MASK                                                              0x00004000L
#define SQC_DCACHE_UTCL0_CNTL2__FORCE_GPUVM_INV_ACK_MASK                                                      0x00008000L
#define SQC_DCACHE_UTCL0_CNTL2__ARB_BURST_MODE_MASK                                                           0x00030000L
#define SQC_DCACHE_UTCL0_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK                                                  0x00040000L
#define SQC_DCACHE_UTCL0_CNTL2__PERF_EVENT_RD_WR_MASK                                                         0x00080000L
#define SQC_DCACHE_UTCL0_CNTL2__ENABLE_PERF_EVENT_VMID_MASK                                                   0x00100000L
#define SQC_DCACHE_UTCL0_CNTL2__PERF_EVENT_VMID_MASK                                                          0x01E00000L
#define SQC_DCACHE_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K_MASK                                                     0x04000000L
#define SQC_DCACHE_UTCL0_CNTL2__PERM_MODE_OVRD_MASK                                                           0x08000000L
#define SQC_DCACHE_UTCL0_CNTL2__LINE_INVALIDATE_OPT_MASK                                                      0x10000000L
#define SQC_DCACHE_UTCL0_CNTL2__GPUVM_16K_DEF_MASK                                                            0x20000000L
#define SQC_DCACHE_UTCL0_CNTL2__FGCG_DISABLE_MASK                                                             0x40000000L
//SQC_ICACHE_UTCL0_STATUS
#define SQC_ICACHE_UTCL0_STATUS__FAULT_DETECTED__SHIFT                                                        0x0
#define SQC_ICACHE_UTCL0_STATUS__RETRY_DETECTED__SHIFT                                                        0x1
#define SQC_ICACHE_UTCL0_STATUS__PRT_DETECTED__SHIFT                                                          0x2
#define SQC_ICACHE_UTCL0_STATUS__FAULT_DETECTED_MASK                                                          0x00000001L
#define SQC_ICACHE_UTCL0_STATUS__RETRY_DETECTED_MASK                                                          0x00000002L
#define SQC_ICACHE_UTCL0_STATUS__PRT_DETECTED_MASK                                                            0x00000004L
//SQC_DCACHE_UTCL0_STATUS
#define SQC_DCACHE_UTCL0_STATUS__FAULT_DETECTED__SHIFT                                                        0x0
#define SQC_DCACHE_UTCL0_STATUS__RETRY_DETECTED__SHIFT                                                        0x1
#define SQC_DCACHE_UTCL0_STATUS__PRT_DETECTED__SHIFT                                                          0x2
#define SQC_DCACHE_UTCL0_STATUS__FAULT_DETECTED_MASK                                                          0x00000001L
#define SQC_DCACHE_UTCL0_STATUS__RETRY_DETECTED_MASK                                                          0x00000002L
#define SQC_DCACHE_UTCL0_STATUS__PRT_DETECTED_MASK                                                            0x00000004L


// addressBlock: gc_shsdec
//SX_DEBUG_1
#define SX_DEBUG_1__SX_DB_QUAD_CREDIT__SHIFT                                                                  0x0
#define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT                                                      0x8
#define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS__SHIFT                                                           0x9
#define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT                                                    0xa
#define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT__SHIFT                                                              0xb
#define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT__SHIFT                                                            0xc
#define SX_DEBUG_1__DISABLE_REP_FGCG__SHIFT                                                                   0xd
#define SX_DEBUG_1__ENABLE_SAME_PC_GDS_CGTS__SHIFT                                                            0xe
#define SX_DEBUG_1__DISABLE_RAM_FGCG__SHIFT                                                                   0xf
#define SX_DEBUG_1__PC_DISABLE_SAME_ADDR_OPT__SHIFT                                                           0x10
#define SX_DEBUG_1__DISABLE_COL_VAL_READ_OPT__SHIFT                                                           0x11
#define SX_DEBUG_1__DISABLE_BC_RB_PLUS__SHIFT                                                                 0x12
#define SX_DEBUG_1__DISABLE_NATIVE_DOWNCVT_FMT_MAPPING__SHIFT                                                 0x13
#define SX_DEBUG_1__DISABLE_SCBD_READ_PWR_OPT__SHIFT                                                          0x14
#define SX_DEBUG_1__DISABLE_GDS_CGTS_OPT__SHIFT                                                               0x15
#define SX_DEBUG_1__DISABLE_DOWNCVT_PWR_OPT__SHIFT                                                            0x16
#define SX_DEBUG_1__DEBUG_DATA__SHIFT                                                                         0x17
#define SX_DEBUG_1__SX_DB_QUAD_CREDIT_MASK                                                                    0x0000007FL
#define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST_MASK                                                        0x00000100L
#define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS_MASK                                                             0x00000200L
#define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK                                                      0x00000400L
#define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT_MASK                                                                0x00000800L
#define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT_MASK                                                              0x00001000L
#define SX_DEBUG_1__DISABLE_REP_FGCG_MASK                                                                     0x00002000L
#define SX_DEBUG_1__ENABLE_SAME_PC_GDS_CGTS_MASK                                                              0x00004000L
#define SX_DEBUG_1__DISABLE_RAM_FGCG_MASK                                                                     0x00008000L
#define SX_DEBUG_1__PC_DISABLE_SAME_ADDR_OPT_MASK                                                             0x00010000L
#define SX_DEBUG_1__DISABLE_COL_VAL_READ_OPT_MASK                                                             0x00020000L
#define SX_DEBUG_1__DISABLE_BC_RB_PLUS_MASK                                                                   0x00040000L
#define SX_DEBUG_1__DISABLE_NATIVE_DOWNCVT_FMT_MAPPING_MASK                                                   0x00080000L
#define SX_DEBUG_1__DISABLE_SCBD_READ_PWR_OPT_MASK                                                            0x00100000L
#define SX_DEBUG_1__DISABLE_GDS_CGTS_OPT_MASK                                                                 0x00200000L
#define SX_DEBUG_1__DISABLE_DOWNCVT_PWR_OPT_MASK                                                              0x00400000L
#define SX_DEBUG_1__DEBUG_DATA_MASK                                                                           0xFF800000L
//SPI_PS_MAX_WAVE_ID
#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT                                                                0x0
#define SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID__SHIFT                                                      0x10
#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID_MASK                                                                  0x00000FFFL
#define SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID_MASK                                                        0x03FF0000L
//SPI_START_PHASE
#define SPI_START_PHASE__PC_X_PHASE_SE0__SHIFT                                                                0x0
#define SPI_START_PHASE__PC_X_PHASE_SE1__SHIFT                                                                0x2
#define SPI_START_PHASE__PC_X_PHASE_SE2__SHIFT                                                                0x4
#define SPI_START_PHASE__PC_X_PHASE_SE3__SHIFT                                                                0x6
#define SPI_START_PHASE__PC_X_PHASE_SE0_MASK                                                                  0x00000003L
#define SPI_START_PHASE__PC_X_PHASE_SE1_MASK                                                                  0x0000000CL
#define SPI_START_PHASE__PC_X_PHASE_SE2_MASK                                                                  0x00000030L
#define SPI_START_PHASE__PC_X_PHASE_SE3_MASK                                                                  0x000000C0L
//SPI_GFX_CNTL
#define SPI_GFX_CNTL__RESET_COUNTS__SHIFT                                                                     0x0
#define SPI_GFX_CNTL__RESET_COUNTS_MASK                                                                       0x00000001L
//SPI_DSM_CNTL
#define SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA__SHIFT                                                    0x0
#define SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE__SHIFT                                                   0x2
#define SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA_MASK                                                      0x00000003L
#define SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE_MASK                                                     0x00000004L
//SPI_DSM_CNTL2
#define SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT__SHIFT                                                  0x0
#define SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY__SHIFT                                                  0x2
#define SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY__SHIFT                                                         0x3
#define SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT_MASK                                                    0x00000003L
#define SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY_MASK                                                    0x00000004L
#define SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY_MASK                                                           0x000001F8L
//SPI_EDC_CNT
#define SPI_EDC_CNT__SPI_SR_MEM_SED_COUNT__SHIFT                                                              0x0
#define SPI_EDC_CNT__SPI_SR_MEM_SED_COUNT_MASK                                                                0x00000003L
//SPI_USER_ACCUM_VMID_CNTL
#define SPI_USER_ACCUM_VMID_CNTL__EN_USER_ACCUM__SHIFT                                                        0x0
#define SPI_USER_ACCUM_VMID_CNTL__EN_USER_ACCUM_MASK                                                          0x0000000FL
//SPI_CONFIG_CNTL
#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY__SHIFT                                                            0x0
#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER__SHIFT                                                            0x15
#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS__SHIFT                                                         0x18
#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS__SHIFT                                                         0x19
#define SPI_CONFIG_CNTL__FORCE_HALF_RATE_PC_EXP__SHIFT                                                        0x1a
#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL__SHIFT                                                              0x1b
#define SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA__SHIFT                                                             0x1c
#define SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA__SHIFT                                                               0x1d
#define SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL__SHIFT                                                          0x1e
#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY_MASK                                                              0x001FFFFFL
#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER_MASK                                                              0x00E00000L
#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS_MASK                                                           0x01000000L
#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS_MASK                                                           0x02000000L
#define SPI_CONFIG_CNTL__FORCE_HALF_RATE_PC_EXP_MASK                                                          0x04000000L
#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL_MASK                                                                0x08000000L
#define SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA_MASK                                                               0x10000000L
#define SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA_MASK                                                                 0x20000000L
#define SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL_MASK                                                            0xC0000000L
//SPI_WAVE_LIMIT_CNTL
#define SPI_WAVE_LIMIT_CNTL__PS_WAVE_GRAN__SHIFT                                                              0x0
#define SPI_WAVE_LIMIT_CNTL__VS_WAVE_GRAN__SHIFT                                                              0x2
#define SPI_WAVE_LIMIT_CNTL__GS_WAVE_GRAN__SHIFT                                                              0x4
#define SPI_WAVE_LIMIT_CNTL__HS_WAVE_GRAN__SHIFT                                                              0x6
#define SPI_WAVE_LIMIT_CNTL__PS_WAVE_GRAN_MASK                                                                0x00000003L
#define SPI_WAVE_LIMIT_CNTL__VS_WAVE_GRAN_MASK                                                                0x0000000CL
#define SPI_WAVE_LIMIT_CNTL__GS_WAVE_GRAN_MASK                                                                0x00000030L
#define SPI_WAVE_LIMIT_CNTL__HS_WAVE_GRAN_MASK                                                                0x000000C0L
//SPI_CONFIG_CNTL_2
#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD__SHIFT                                    0x0
#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD__SHIFT                                      0x4
#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD_MASK                                      0x0000000FL
#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD_MASK                                        0x000000F0L
//SPI_CONFIG_CNTL_1
#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT                                                              0x0
#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW__SHIFT                                                     0x4
#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE__SHIFT                                                             0x5
#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT__SHIFT                                                             0x7
#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE__SHIFT                                                   0x8
#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE__SHIFT                                                            0x9
#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT__SHIFT                                                             0xa
#define SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE__SHIFT                                                        0xe
#define SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE__SHIFT                                                        0xf
#define SPI_CONFIG_CNTL_1__MAX_VTX_SYNC_CNT__SHIFT                                                            0x10
#define SPI_CONFIG_CNTL_1__EN_USER_ACCUM__SHIFT                                                               0x15
#define SPI_CONFIG_CNTL_1__SA_SCREEN_MAP__SHIFT                                                               0x16
#define SPI_CONFIG_CNTL_1__RESERVED__SHIFT                                                                    0x17
#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_MASK                                                                0x0000000FL
#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW_MASK                                                       0x00000010L
#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK                                                               0x00000060L
#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT_MASK                                                               0x00000080L
#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE_MASK                                                     0x00000100L
#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE_MASK                                                              0x00000200L
#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT_MASK                                                               0x00003C00L
#define SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE_MASK                                                          0x00004000L
#define SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE_MASK                                                          0x00008000L
#define SPI_CONFIG_CNTL_1__MAX_VTX_SYNC_CNT_MASK                                                              0x001F0000L
#define SPI_CONFIG_CNTL_1__EN_USER_ACCUM_MASK                                                                 0x00200000L
#define SPI_CONFIG_CNTL_1__SA_SCREEN_MAP_MASK                                                                 0x00400000L
#define SPI_CONFIG_CNTL_1__RESERVED_MASK                                                                      0xFF800000L
//SPI_CONFIG_PS_CU_EN
#define SPI_CONFIG_PS_CU_EN__PKR_OFFSET__SHIFT                                                                0x0
#define SPI_CONFIG_PS_CU_EN__PKR_OFFSET_MASK                                                                  0x0000000FL
//SPI_WF_LIFETIME_CNTL
#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD__SHIFT                                                            0x0
#define SPI_WF_LIFETIME_CNTL__EN__SHIFT                                                                       0x4
#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD_MASK                                                              0x0000000FL
#define SPI_WF_LIFETIME_CNTL__EN_MASK                                                                         0x00000010L
//SPI_WF_LIFETIME_LIMIT_0
#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT__SHIFT                                                               0x0
#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN__SHIFT                                                               0x1f
#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT_MASK                                                                 0x7FFFFFFFL
#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN_MASK                                                                 0x80000000L
//SPI_WF_LIFETIME_LIMIT_1
#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT__SHIFT                                                               0x0
#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN__SHIFT                                                               0x1f
#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT_MASK                                                                 0x7FFFFFFFL
#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN_MASK                                                                 0x80000000L
//SPI_WF_LIFETIME_LIMIT_2
#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT__SHIFT                                                               0x0
#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN__SHIFT                                                               0x1f
#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT_MASK                                                                 0x7FFFFFFFL
#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN_MASK                                                                 0x80000000L
//SPI_WF_LIFETIME_LIMIT_3
#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT__SHIFT                                                               0x0
#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN__SHIFT                                                               0x1f
#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT_MASK                                                                 0x7FFFFFFFL
#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN_MASK                                                                 0x80000000L
//SPI_WF_LIFETIME_LIMIT_4
#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT__SHIFT                                                               0x0
#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN__SHIFT                                                               0x1f
#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT_MASK                                                                 0x7FFFFFFFL
#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN_MASK                                                                 0x80000000L
//SPI_WF_LIFETIME_LIMIT_5
#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT__SHIFT                                                               0x0
#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN__SHIFT                                                               0x1f
#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT_MASK                                                                 0x7FFFFFFFL
#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN_MASK                                                                 0x80000000L
//SPI_WF_LIFETIME_STATUS_0
#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT__SHIFT                                                              0x0
#define SPI_WF_LIFETIME_STATUS_0__INT_SENT__SHIFT                                                             0x1f
#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT_MASK                                                                0x7FFFFFFFL
#define SPI_WF_LIFETIME_STATUS_0__INT_SENT_MASK                                                               0x80000000L
//SPI_WF_LIFETIME_STATUS_1
#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT__SHIFT                                                              0x0
#define SPI_WF_LIFETIME_STATUS_1__INT_SENT__SHIFT                                                             0x1f
#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT_MASK                                                                0x7FFFFFFFL
#define SPI_WF_LIFETIME_STATUS_1__INT_SENT_MASK                                                               0x80000000L
//SPI_WF_LIFETIME_STATUS_2
#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT__SHIFT                                                              0x0
#define SPI_WF_LIFETIME_STATUS_2__INT_SENT__SHIFT                                                             0x1f
#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT_MASK                                                                0x7FFFFFFFL
#define SPI_WF_LIFETIME_STATUS_2__INT_SENT_MASK                                                               0x80000000L
//SPI_WF_LIFETIME_STATUS_4
#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT__SHIFT                                                              0x0
#define SPI_WF_LIFETIME_STATUS_4__INT_SENT__SHIFT                                                             0x1f
#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT_MASK                                                                0x7FFFFFFFL
#define SPI_WF_LIFETIME_STATUS_4__INT_SENT_MASK                                                               0x80000000L
//SPI_WF_LIFETIME_STATUS_6
#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT__SHIFT                                                              0x0
#define SPI_WF_LIFETIME_STATUS_6__INT_SENT__SHIFT                                                             0x1f
#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT_MASK                                                                0x7FFFFFFFL
#define SPI_WF_LIFETIME_STATUS_6__INT_SENT_MASK                                                               0x80000000L
//SPI_WF_LIFETIME_STATUS_7
#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT__SHIFT                                                              0x0
#define SPI_WF_LIFETIME_STATUS_7__INT_SENT__SHIFT                                                             0x1f
#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT_MASK                                                                0x7FFFFFFFL
#define SPI_WF_LIFETIME_STATUS_7__INT_SENT_MASK                                                               0x80000000L
//SPI_WF_LIFETIME_STATUS_8
#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT__SHIFT                                                              0x0
#define SPI_WF_LIFETIME_STATUS_8__INT_SENT__SHIFT                                                             0x1f
#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT_MASK                                                                0x7FFFFFFFL
#define SPI_WF_LIFETIME_STATUS_8__INT_SENT_MASK                                                               0x80000000L
//SPI_WF_LIFETIME_STATUS_9
#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT__SHIFT                                                              0x0
#define SPI_WF_LIFETIME_STATUS_9__INT_SENT__SHIFT                                                             0x1f
#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT_MASK                                                                0x7FFFFFFFL
#define SPI_WF_LIFETIME_STATUS_9__INT_SENT_MASK                                                               0x80000000L
//SPI_WF_LIFETIME_STATUS_11
#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT__SHIFT                                                             0x0
#define SPI_WF_LIFETIME_STATUS_11__INT_SENT__SHIFT                                                            0x1f
#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT_MASK                                                               0x7FFFFFFFL
#define SPI_WF_LIFETIME_STATUS_11__INT_SENT_MASK                                                              0x80000000L
//SPI_WF_LIFETIME_STATUS_13
#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT__SHIFT                                                             0x0
#define SPI_WF_LIFETIME_STATUS_13__INT_SENT__SHIFT                                                            0x1f
#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT_MASK                                                               0x7FFFFFFFL
#define SPI_WF_LIFETIME_STATUS_13__INT_SENT_MASK                                                              0x80000000L
//SPI_WF_LIFETIME_STATUS_14
#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT__SHIFT                                                             0x0
#define SPI_WF_LIFETIME_STATUS_14__INT_SENT__SHIFT                                                            0x1f
#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT_MASK                                                               0x7FFFFFFFL
#define SPI_WF_LIFETIME_STATUS_14__INT_SENT_MASK                                                              0x80000000L
//SPI_WF_LIFETIME_STATUS_15
#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT__SHIFT                                                             0x0
#define SPI_WF_LIFETIME_STATUS_15__INT_SENT__SHIFT                                                            0x1f
#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT_MASK                                                               0x7FFFFFFFL
#define SPI_WF_LIFETIME_STATUS_15__INT_SENT_MASK                                                              0x80000000L
//SPI_WF_LIFETIME_STATUS_16
#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT__SHIFT                                                             0x0
#define SPI_WF_LIFETIME_STATUS_16__INT_SENT__SHIFT                                                            0x1f
#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT_MASK                                                               0x7FFFFFFFL
#define SPI_WF_LIFETIME_STATUS_16__INT_SENT_MASK                                                              0x80000000L
//SPI_WF_LIFETIME_STATUS_17
#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT__SHIFT                                                             0x0
#define SPI_WF_LIFETIME_STATUS_17__INT_SENT__SHIFT                                                            0x1f
#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT_MASK                                                               0x7FFFFFFFL
#define SPI_WF_LIFETIME_STATUS_17__INT_SENT_MASK                                                              0x80000000L
//SPI_WF_LIFETIME_STATUS_18
#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT__SHIFT                                                             0x0
#define SPI_WF_LIFETIME_STATUS_18__INT_SENT__SHIFT                                                            0x1f
#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT_MASK                                                               0x7FFFFFFFL
#define SPI_WF_LIFETIME_STATUS_18__INT_SENT_MASK                                                              0x80000000L
//SPI_WF_LIFETIME_STATUS_19
#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT__SHIFT                                                             0x0
#define SPI_WF_LIFETIME_STATUS_19__INT_SENT__SHIFT                                                            0x1f
#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT_MASK                                                               0x7FFFFFFFL
#define SPI_WF_LIFETIME_STATUS_19__INT_SENT_MASK                                                              0x80000000L
//SPI_WF_LIFETIME_STATUS_20
#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT__SHIFT                                                             0x0
#define SPI_WF_LIFETIME_STATUS_20__INT_SENT__SHIFT                                                            0x1f
#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT_MASK                                                               0x7FFFFFFFL
#define SPI_WF_LIFETIME_STATUS_20__INT_SENT_MASK                                                              0x80000000L
//SPI_WF_LIFETIME_STATUS_21
#define SPI_WF_LIFETIME_STATUS_21__MAX_CNT__SHIFT                                                             0x0
#define SPI_WF_LIFETIME_STATUS_21__INT_SENT__SHIFT                                                            0x1f
#define SPI_WF_LIFETIME_STATUS_21__MAX_CNT_MASK                                                               0x7FFFFFFFL
#define SPI_WF_LIFETIME_STATUS_21__INT_SENT_MASK                                                              0x80000000L
//SPI_LB_CTR_CTRL
#define SPI_LB_CTR_CTRL__LOAD__SHIFT                                                                          0x0
#define SPI_LB_CTR_CTRL__WAVES_SELECT__SHIFT                                                                  0x1
#define SPI_LB_CTR_CTRL__CLEAR_ON_READ__SHIFT                                                                 0x3
#define SPI_LB_CTR_CTRL__RESET_COUNTS__SHIFT                                                                  0x4
#define SPI_LB_CTR_CTRL__LOAD_MASK                                                                            0x00000001L
#define SPI_LB_CTR_CTRL__WAVES_SELECT_MASK                                                                    0x00000006L
#define SPI_LB_CTR_CTRL__CLEAR_ON_READ_MASK                                                                   0x00000008L
#define SPI_LB_CTR_CTRL__RESET_COUNTS_MASK                                                                    0x00000010L
//SPI_LB_WGP_MASK
#define SPI_LB_WGP_MASK__WGP_MASK__SHIFT                                                                      0x0
#define SPI_LB_WGP_MASK__WGP_MASK_MASK                                                                        0xFFFFL
//SPI_LB_DATA_REG
#define SPI_LB_DATA_REG__CNT_DATA__SHIFT                                                                      0x0
#define SPI_LB_DATA_REG__CNT_DATA_MASK                                                                        0xFFFFFFFFL
//SPI_PG_ENABLE_STATIC_WGP_MASK
#define SPI_PG_ENABLE_STATIC_WGP_MASK__WGP_MASK__SHIFT                                                        0x0
#define SPI_PG_ENABLE_STATIC_WGP_MASK__WGP_MASK_MASK                                                          0xFFFFL
//SPI_GDS_CREDITS
#define SPI_GDS_CREDITS__DS_DATA_CREDITS__SHIFT                                                               0x0
#define SPI_GDS_CREDITS__DS_CMD_CREDITS__SHIFT                                                                0x8
#define SPI_GDS_CREDITS__DS_DATA_CREDITS_MASK                                                                 0x000000FFL
#define SPI_GDS_CREDITS__DS_CMD_CREDITS_MASK                                                                  0x0000FF00L
//SPI_SX_EXPORT_BUFFER_SIZES
#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE__SHIFT                                                  0x0
#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE__SHIFT                                               0x10
#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE_MASK                                                    0x0000FFFFL
#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE_MASK                                                 0xFFFF0000L
//SPI_SX_SCOREBOARD_BUFFER_SIZES
#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE__SHIFT                                          0x0
#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE__SHIFT                                       0x10
#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE_MASK                                            0x0000FFFFL
#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE_MASK                                         0xFFFF0000L
//SPI_CSQ_WF_ACTIVE_STATUS
#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE__SHIFT                                                               0x0
#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE_MASK                                                                 0xFFFFFFFFL
//SPI_CSQ_WF_ACTIVE_COUNT_0
#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT__SHIFT                                                               0x0
#define SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS__SHIFT                                                              0x10
#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK                                                                 0x000007FFL
#define SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS_MASK                                                                0x07FF0000L
//SPI_CSQ_WF_ACTIVE_COUNT_1
#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT__SHIFT                                                               0x0
#define SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS__SHIFT                                                              0x10
#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK                                                                 0x000007FFL
#define SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS_MASK                                                                0x07FF0000L
//SPI_CSQ_WF_ACTIVE_COUNT_2
#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT__SHIFT                                                               0x0
#define SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS__SHIFT                                                              0x10
#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT_MASK                                                                 0x000007FFL
#define SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS_MASK                                                                0x07FF0000L
//SPI_CSQ_WF_ACTIVE_COUNT_3
#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT__SHIFT                                                               0x0
#define SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS__SHIFT                                                              0x10
#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT_MASK                                                                 0x000007FFL
#define SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS_MASK                                                                0x07FF0000L
//SPI_LB_DATA_WAVES
#define SPI_LB_DATA_WAVES__COUNT0__SHIFT                                                                      0x0
#define SPI_LB_DATA_WAVES__COUNT1__SHIFT                                                                      0x10
#define SPI_LB_DATA_WAVES__COUNT0_MASK                                                                        0x0000FFFFL
#define SPI_LB_DATA_WAVES__COUNT1_MASK                                                                        0xFFFF0000L
//SPI_LB_DATA_PERWGP_WAVE_HSGS
#define SPI_LB_DATA_PERWGP_WAVE_HSGS__WGP_USED_HS__SHIFT                                                      0x0
#define SPI_LB_DATA_PERWGP_WAVE_HSGS__WGP_USED_GS__SHIFT                                                      0x10
#define SPI_LB_DATA_PERWGP_WAVE_HSGS__WGP_USED_HS_MASK                                                        0x0000FFFFL
#define SPI_LB_DATA_PERWGP_WAVE_HSGS__WGP_USED_GS_MASK                                                        0xFFFF0000L
//SPI_LB_DATA_PERWGP_WAVE_VSPS
#define SPI_LB_DATA_PERWGP_WAVE_VSPS__WGP_USED_VS__SHIFT                                                      0x0
#define SPI_LB_DATA_PERWGP_WAVE_VSPS__WGP_USED_PS__SHIFT                                                      0x10
#define SPI_LB_DATA_PERWGP_WAVE_VSPS__WGP_USED_VS_MASK                                                        0x0000FFFFL
#define SPI_LB_DATA_PERWGP_WAVE_VSPS__WGP_USED_PS_MASK                                                        0xFFFF0000L
//SPI_LB_DATA_PERWGP_WAVE_CS
#define SPI_LB_DATA_PERWGP_WAVE_CS__ACTIVE__SHIFT                                                             0x0
#define SPI_LB_DATA_PERWGP_WAVE_CS__ACTIVE_MASK                                                               0xFFFFL
//SPI_P0_TRAP_SCREEN_PSBA_LO
#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT                                                           0x0
#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK                                                             0xFFFFFFFFL
//SPI_P0_TRAP_SCREEN_PSBA_HI
#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT                                                           0x0
#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK                                                             0xFFL
//SPI_P0_TRAP_SCREEN_PSMA_LO
#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT                                                           0x0
#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK                                                             0xFFFFFFFFL
//SPI_P0_TRAP_SCREEN_PSMA_HI
#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT                                                           0x0
#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK                                                             0xFFL
//SPI_P0_TRAP_SCREEN_GPR_MIN
#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT                                                           0x0
#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT                                                           0x6
#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK                                                             0x003FL
#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK                                                             0x03C0L
//SPI_P1_TRAP_SCREEN_PSBA_LO
#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT                                                           0x0
#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK                                                             0xFFFFFFFFL
//SPI_P1_TRAP_SCREEN_PSBA_HI
#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT                                                           0x0
#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK                                                             0xFFL
//SPI_P1_TRAP_SCREEN_PSMA_LO
#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT                                                           0x0
#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK                                                             0xFFFFFFFFL
//SPI_P1_TRAP_SCREEN_PSMA_HI
#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT                                                           0x0
#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK                                                             0xFFL
//SPI_P1_TRAP_SCREEN_GPR_MIN
#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT                                                           0x0
#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT                                                           0x6
#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK                                                             0x003FL
#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK                                                             0x03C0L


// addressBlock: gc_tpdec
//TD_STATUS
#define TD_STATUS__BUSY__SHIFT                                                                                0x1f
#define TD_STATUS__BUSY_MASK                                                                                  0x80000000L
//TD_DSM_CNTL
#define TD_DSM_CNTL__TD_SS_FIFO_LO_DSM_IRRITATOR_DATA__SHIFT                                                  0x0
#define TD_DSM_CNTL__TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE__SHIFT                                                 0x2
#define TD_DSM_CNTL__TD_SS_FIFO_HI_DSM_IRRITATOR_DATA__SHIFT                                                  0x3
#define TD_DSM_CNTL__TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE__SHIFT                                                 0x5
#define TD_DSM_CNTL__TD_CS_FIFO_DSM_IRRITATOR_DATA__SHIFT                                                     0x6
#define TD_DSM_CNTL__TD_CS_FIFO_ENABLE_SINGLE_WRITE__SHIFT                                                    0x8
#define TD_DSM_CNTL__TD_SS_FIFO_LO_DSM_IRRITATOR_DATA_MASK                                                    0x00000003L
#define TD_DSM_CNTL__TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE_MASK                                                   0x00000004L
#define TD_DSM_CNTL__TD_SS_FIFO_HI_DSM_IRRITATOR_DATA_MASK                                                    0x00000018L
#define TD_DSM_CNTL__TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE_MASK                                                   0x00000020L
#define TD_DSM_CNTL__TD_CS_FIFO_DSM_IRRITATOR_DATA_MASK                                                       0x000000C0L
#define TD_DSM_CNTL__TD_CS_FIFO_ENABLE_SINGLE_WRITE_MASK                                                      0x00000100L
//TD_DSM_CNTL2
#define TD_DSM_CNTL2__TD_SS_FIFO_LO_ENABLE_ERROR_INJECT__SHIFT                                                0x0
#define TD_DSM_CNTL2__TD_SS_FIFO_LO_SELECT_INJECT_DELAY__SHIFT                                                0x2
#define TD_DSM_CNTL2__TD_SS_FIFO_HI_ENABLE_ERROR_INJECT__SHIFT                                                0x3
#define TD_DSM_CNTL2__TD_SS_FIFO_HI_SELECT_INJECT_DELAY__SHIFT                                                0x5
#define TD_DSM_CNTL2__TD_CS_FIFO_ENABLE_ERROR_INJECT__SHIFT                                                   0x6
#define TD_DSM_CNTL2__TD_CS_FIFO_SELECT_INJECT_DELAY__SHIFT                                                   0x8
#define TD_DSM_CNTL2__TD_INJECT_DELAY__SHIFT                                                                  0x1a
#define TD_DSM_CNTL2__TD_SS_FIFO_LO_ENABLE_ERROR_INJECT_MASK                                                  0x00000003L
#define TD_DSM_CNTL2__TD_SS_FIFO_LO_SELECT_INJECT_DELAY_MASK                                                  0x00000004L
#define TD_DSM_CNTL2__TD_SS_FIFO_HI_ENABLE_ERROR_INJECT_MASK                                                  0x00000018L
#define TD_DSM_CNTL2__TD_SS_FIFO_HI_SELECT_INJECT_DELAY_MASK                                                  0x00000020L
#define TD_DSM_CNTL2__TD_CS_FIFO_ENABLE_ERROR_INJECT_MASK                                                     0x000000C0L
#define TD_DSM_CNTL2__TD_CS_FIFO_SELECT_INJECT_DELAY_MASK                                                     0x00000100L
#define TD_DSM_CNTL2__TD_INJECT_DELAY_MASK                                                                    0xFC000000L
//TD_SCRATCH
#define TD_SCRATCH__SCRATCH__SHIFT                                                                            0x0
#define TD_SCRATCH__SCRATCH_MASK                                                                              0xFFFFFFFFL
//TA_CNTL
#define TA_CNTL__ALIGNER_CREDIT__SHIFT                                                                        0x10
#define TA_CNTL__TD_FIFO_CREDIT__SHIFT                                                                        0x16
#define TA_CNTL__ALIGNER_CREDIT_MASK                                                                          0x001F0000L
#define TA_CNTL__TD_FIFO_CREDIT_MASK                                                                          0xFFC00000L
//TA_RESERVED_010C
#define TA_RESERVED_010C__Unused__SHIFT                                                                       0x0
#define TA_RESERVED_010C__Unused_MASK                                                                         0xFFFFFFFFL
//TA_STATUS
#define TA_STATUS__FG_PFIFO_EMPTYB__SHIFT                                                                     0xc
#define TA_STATUS__FG_LFIFO_EMPTYB__SHIFT                                                                     0xd
#define TA_STATUS__FG_SFIFO_EMPTYB__SHIFT                                                                     0xe
#define TA_STATUS__FL_PFIFO_EMPTYB__SHIFT                                                                     0x10
#define TA_STATUS__FL_LFIFO_EMPTYB__SHIFT                                                                     0x11
#define TA_STATUS__FL_SFIFO_EMPTYB__SHIFT                                                                     0x12
#define TA_STATUS__FA_PFIFO_EMPTYB__SHIFT                                                                     0x14
#define TA_STATUS__FA_LFIFO_EMPTYB__SHIFT                                                                     0x15
#define TA_STATUS__FA_SFIFO_EMPTYB__SHIFT                                                                     0x16
#define TA_STATUS__IN_BUSY__SHIFT                                                                             0x18
#define TA_STATUS__FG_BUSY__SHIFT                                                                             0x19
#define TA_STATUS__LA_BUSY__SHIFT                                                                             0x1a
#define TA_STATUS__FL_BUSY__SHIFT                                                                             0x1b
#define TA_STATUS__TA_BUSY__SHIFT                                                                             0x1c
#define TA_STATUS__FA_BUSY__SHIFT                                                                             0x1d
#define TA_STATUS__AL_BUSY__SHIFT                                                                             0x1e
#define TA_STATUS__BUSY__SHIFT                                                                                0x1f
#define TA_STATUS__FG_PFIFO_EMPTYB_MASK                                                                       0x00001000L
#define TA_STATUS__FG_LFIFO_EMPTYB_MASK                                                                       0x00002000L
#define TA_STATUS__FG_SFIFO_EMPTYB_MASK                                                                       0x00004000L
#define TA_STATUS__FL_PFIFO_EMPTYB_MASK                                                                       0x00010000L
#define TA_STATUS__FL_LFIFO_EMPTYB_MASK                                                                       0x00020000L
#define TA_STATUS__FL_SFIFO_EMPTYB_MASK                                                                       0x00040000L
#define TA_STATUS__FA_PFIFO_EMPTYB_MASK                                                                       0x00100000L
#define TA_STATUS__FA_LFIFO_EMPTYB_MASK                                                                       0x00200000L
#define TA_STATUS__FA_SFIFO_EMPTYB_MASK                                                                       0x00400000L
#define TA_STATUS__IN_BUSY_MASK                                                                               0x01000000L
#define TA_STATUS__FG_BUSY_MASK                                                                               0x02000000L
#define TA_STATUS__LA_BUSY_MASK                                                                               0x04000000L
#define TA_STATUS__FL_BUSY_MASK                                                                               0x08000000L
#define TA_STATUS__TA_BUSY_MASK                                                                               0x10000000L
#define TA_STATUS__FA_BUSY_MASK                                                                               0x20000000L
#define TA_STATUS__AL_BUSY_MASK                                                                               0x40000000L
#define TA_STATUS__BUSY_MASK                                                                                  0x80000000L
//TA_SCRATCH
#define TA_SCRATCH__SCRATCH__SHIFT                                                                            0x0
#define TA_SCRATCH__SCRATCH_MASK                                                                              0xFFFFFFFFL


// addressBlock: gc_gdsdec
//GDS_CONFIG
#define GDS_CONFIG__SH0_GPR_PHASE_SEL__SHIFT                                                                  0x1
#define GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT                                                                  0x3
#define GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT                                                                  0x5
#define GDS_CONFIG__SH3_GPR_PHASE_SEL__SHIFT                                                                  0x7
#define GDS_CONFIG__UNUSED__SHIFT                                                                             0x9
#define GDS_CONFIG__SH0_GPR_PHASE_SEL_MASK                                                                    0x00000006L
#define GDS_CONFIG__SH1_GPR_PHASE_SEL_MASK                                                                    0x00000018L
#define GDS_CONFIG__SH2_GPR_PHASE_SEL_MASK                                                                    0x00000060L
#define GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK                                                                    0x00000180L
#define GDS_CONFIG__UNUSED_MASK                                                                               0xFFFFFE00L
//GDS_CNTL_STATUS
#define GDS_CNTL_STATUS__GDS_BUSY__SHIFT                                                                      0x0
#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY__SHIFT                                                                0x1
#define GDS_CNTL_STATUS__ORD_APP_BUSY__SHIFT                                                                  0x2
#define GDS_CNTL_STATUS__DS_BANK_CONFLICT__SHIFT                                                              0x3
#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT__SHIFT                                                              0x4
#define GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT                                                                   0x5
#define GDS_CNTL_STATUS__DS_RD_CLAMP__SHIFT                                                                   0x6
#define GDS_CNTL_STATUS__GRBM_RBUF_BUSY__SHIFT                                                                0x7
#define GDS_CNTL_STATUS__DS_BUSY__SHIFT                                                                       0x8
#define GDS_CNTL_STATUS__GWS_BUSY__SHIFT                                                                      0x9
#define GDS_CNTL_STATUS__ORD_FIFO_BUSY__SHIFT                                                                 0xa
#define GDS_CNTL_STATUS__CREDIT_BUSY0__SHIFT                                                                  0xb
#define GDS_CNTL_STATUS__CREDIT_BUSY1__SHIFT                                                                  0xc
#define GDS_CNTL_STATUS__CREDIT_BUSY2__SHIFT                                                                  0xd
#define GDS_CNTL_STATUS__CREDIT_BUSY3__SHIFT                                                                  0xe
#define GDS_CNTL_STATUS__UNUSED__SHIFT                                                                        0xf
#define GDS_CNTL_STATUS__GDS_BUSY_MASK                                                                        0x00000001L
#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY_MASK                                                                  0x00000002L
#define GDS_CNTL_STATUS__ORD_APP_BUSY_MASK                                                                    0x00000004L
#define GDS_CNTL_STATUS__DS_BANK_CONFLICT_MASK                                                                0x00000008L
#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT_MASK                                                                0x00000010L
#define GDS_CNTL_STATUS__DS_WR_CLAMP_MASK                                                                     0x00000020L
#define GDS_CNTL_STATUS__DS_RD_CLAMP_MASK                                                                     0x00000040L
#define GDS_CNTL_STATUS__GRBM_RBUF_BUSY_MASK                                                                  0x00000080L
#define GDS_CNTL_STATUS__DS_BUSY_MASK                                                                         0x00000100L
#define GDS_CNTL_STATUS__GWS_BUSY_MASK                                                                        0x00000200L
#define GDS_CNTL_STATUS__ORD_FIFO_BUSY_MASK                                                                   0x00000400L
#define GDS_CNTL_STATUS__CREDIT_BUSY0_MASK                                                                    0x00000800L
#define GDS_CNTL_STATUS__CREDIT_BUSY1_MASK                                                                    0x00001000L
#define GDS_CNTL_STATUS__CREDIT_BUSY2_MASK                                                                    0x00002000L
#define GDS_CNTL_STATUS__CREDIT_BUSY3_MASK                                                                    0x00004000L
#define GDS_CNTL_STATUS__UNUSED_MASK                                                                          0xFFFF8000L
//GDS_ENHANCE
#define GDS_ENHANCE__MISC__SHIFT                                                                              0x0
#define GDS_ENHANCE__AUTO_INC_INDEX__SHIFT                                                                    0x10
#define GDS_ENHANCE__CGPG_RESTORE__SHIFT                                                                      0x11
#define GDS_ENHANCE__UNUSED__SHIFT                                                                            0x12
#define GDS_ENHANCE__MISC_MASK                                                                                0x0000FFFFL
#define GDS_ENHANCE__AUTO_INC_INDEX_MASK                                                                      0x00010000L
#define GDS_ENHANCE__CGPG_RESTORE_MASK                                                                        0x00020000L
#define GDS_ENHANCE__UNUSED_MASK                                                                              0xFFFC0000L
//GDS_PROTECTION_FAULT
#define GDS_PROTECTION_FAULT__WRITE_DIS__SHIFT                                                                0x0
#define GDS_PROTECTION_FAULT__FAULT_DETECTED__SHIFT                                                           0x1
#define GDS_PROTECTION_FAULT__GRBM__SHIFT                                                                     0x2
#define GDS_PROTECTION_FAULT__SH_ID__SHIFT                                                                    0x3
#define GDS_PROTECTION_FAULT__CU_ID__SHIFT                                                                    0x6
#define GDS_PROTECTION_FAULT__SIMD_ID__SHIFT                                                                  0xa
#define GDS_PROTECTION_FAULT__WAVE_ID__SHIFT                                                                  0xc
#define GDS_PROTECTION_FAULT__ADDRESS__SHIFT                                                                  0x10
#define GDS_PROTECTION_FAULT__WRITE_DIS_MASK                                                                  0x00000001L
#define GDS_PROTECTION_FAULT__FAULT_DETECTED_MASK                                                             0x00000002L
#define GDS_PROTECTION_FAULT__GRBM_MASK                                                                       0x00000004L
#define GDS_PROTECTION_FAULT__SH_ID_MASK                                                                      0x00000038L
#define GDS_PROTECTION_FAULT__CU_ID_MASK                                                                      0x000003C0L
#define GDS_PROTECTION_FAULT__SIMD_ID_MASK                                                                    0x00000C00L
#define GDS_PROTECTION_FAULT__WAVE_ID_MASK                                                                    0x0000F000L
#define GDS_PROTECTION_FAULT__ADDRESS_MASK                                                                    0xFFFF0000L
//GDS_VM_PROTECTION_FAULT
#define GDS_VM_PROTECTION_FAULT__WRITE_DIS__SHIFT                                                             0x0
#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED__SHIFT                                                        0x1
#define GDS_VM_PROTECTION_FAULT__GWS__SHIFT                                                                   0x2
#define GDS_VM_PROTECTION_FAULT__OA__SHIFT                                                                    0x3
#define GDS_VM_PROTECTION_FAULT__GRBM__SHIFT                                                                  0x4
#define GDS_VM_PROTECTION_FAULT__TMZ__SHIFT                                                                   0x5
#define GDS_VM_PROTECTION_FAULT__UNUSED1__SHIFT                                                               0x6
#define GDS_VM_PROTECTION_FAULT__VMID__SHIFT                                                                  0x8
#define GDS_VM_PROTECTION_FAULT__UNUSED2__SHIFT                                                               0xc
#define GDS_VM_PROTECTION_FAULT__ADDRESS__SHIFT                                                               0x10
#define GDS_VM_PROTECTION_FAULT__WRITE_DIS_MASK                                                               0x00000001L
#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED_MASK                                                          0x00000002L
#define GDS_VM_PROTECTION_FAULT__GWS_MASK                                                                     0x00000004L
#define GDS_VM_PROTECTION_FAULT__OA_MASK                                                                      0x00000008L
#define GDS_VM_PROTECTION_FAULT__GRBM_MASK                                                                    0x00000010L
#define GDS_VM_PROTECTION_FAULT__TMZ_MASK                                                                     0x00000020L
#define GDS_VM_PROTECTION_FAULT__UNUSED1_MASK                                                                 0x000000C0L
#define GDS_VM_PROTECTION_FAULT__VMID_MASK                                                                    0x00000F00L
#define GDS_VM_PROTECTION_FAULT__UNUSED2_MASK                                                                 0x0000F000L
#define GDS_VM_PROTECTION_FAULT__ADDRESS_MASK                                                                 0xFFFF0000L
//GDS_EDC_CNT
#define GDS_EDC_CNT__GDS_MEM_DED__SHIFT                                                                       0x0
#define GDS_EDC_CNT__GDS_INPUT_QUEUE_SED__SHIFT                                                               0x2
#define GDS_EDC_CNT__GDS_MEM_SEC__SHIFT                                                                       0x4
#define GDS_EDC_CNT__UNUSED__SHIFT                                                                            0x6
#define GDS_EDC_CNT__GDS_MEM_DED_MASK                                                                         0x00000003L
#define GDS_EDC_CNT__GDS_INPUT_QUEUE_SED_MASK                                                                 0x0000000CL
#define GDS_EDC_CNT__GDS_MEM_SEC_MASK                                                                         0x00000030L
#define GDS_EDC_CNT__UNUSED_MASK                                                                              0xFFFFFFC0L
//GDS_EDC_GRBM_CNT
#define GDS_EDC_GRBM_CNT__DED__SHIFT                                                                          0x0
#define GDS_EDC_GRBM_CNT__SEC__SHIFT                                                                          0x2
#define GDS_EDC_GRBM_CNT__UNUSED__SHIFT                                                                       0x4
#define GDS_EDC_GRBM_CNT__DED_MASK                                                                            0x00000003L
#define GDS_EDC_GRBM_CNT__SEC_MASK                                                                            0x0000000CL
#define GDS_EDC_GRBM_CNT__UNUSED_MASK                                                                         0xFFFFFFF0L
//GDS_EDC_OA_DED
#define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED__SHIFT                                                            0x0
#define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED__SHIFT                                                            0x1
#define GDS_EDC_OA_DED__ME0_CS_DED__SHIFT                                                                     0x2
#define GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED__SHIFT                                                             0x3
#define GDS_EDC_OA_DED__ME1_PIPE0_DED__SHIFT                                                                  0x4
#define GDS_EDC_OA_DED__ME1_PIPE1_DED__SHIFT                                                                  0x5
#define GDS_EDC_OA_DED__ME1_PIPE2_DED__SHIFT                                                                  0x6
#define GDS_EDC_OA_DED__ME1_PIPE3_DED__SHIFT                                                                  0x7
#define GDS_EDC_OA_DED__ME2_PIPE0_DED__SHIFT                                                                  0x8
#define GDS_EDC_OA_DED__ME2_PIPE1_DED__SHIFT                                                                  0x9
#define GDS_EDC_OA_DED__ME2_PIPE2_DED__SHIFT                                                                  0xa
#define GDS_EDC_OA_DED__ME2_PIPE3_DED__SHIFT                                                                  0xb
#define GDS_EDC_OA_DED__ME0_PIPE1_CS_DED__SHIFT                                                               0xc
#define GDS_EDC_OA_DED__UNUSED1__SHIFT                                                                        0xd
#define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED_MASK                                                              0x00000001L
#define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED_MASK                                                              0x00000002L
#define GDS_EDC_OA_DED__ME0_CS_DED_MASK                                                                       0x00000004L
#define GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED_MASK                                                               0x00000008L
#define GDS_EDC_OA_DED__ME1_PIPE0_DED_MASK                                                                    0x00000010L
#define GDS_EDC_OA_DED__ME1_PIPE1_DED_MASK                                                                    0x00000020L
#define GDS_EDC_OA_DED__ME1_PIPE2_DED_MASK                                                                    0x00000040L
#define GDS_EDC_OA_DED__ME1_PIPE3_DED_MASK                                                                    0x00000080L
#define GDS_EDC_OA_DED__ME2_PIPE0_DED_MASK                                                                    0x00000100L
#define GDS_EDC_OA_DED__ME2_PIPE1_DED_MASK                                                                    0x00000200L
#define GDS_EDC_OA_DED__ME2_PIPE2_DED_MASK                                                                    0x00000400L
#define GDS_EDC_OA_DED__ME2_PIPE3_DED_MASK                                                                    0x00000800L
#define GDS_EDC_OA_DED__ME0_PIPE1_CS_DED_MASK                                                                 0x00001000L
#define GDS_EDC_OA_DED__UNUSED1_MASK                                                                          0xFFFFE000L
//GDS_DSM_CNTL
#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0__SHIFT                                                 0x0
#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1__SHIFT                                                 0x1
#define GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE__SHIFT                                                      0x2
#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0__SHIFT                                         0x3
#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1__SHIFT                                         0x4
#define GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE__SHIFT                                              0x5
#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0__SHIFT                                         0x6
#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1__SHIFT                                         0x7
#define GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE__SHIFT                                              0x8
#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0__SHIFT                                        0x9
#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1__SHIFT                                        0xa
#define GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE__SHIFT                                             0xb
#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0__SHIFT                                            0xc
#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1__SHIFT                                            0xd
#define GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE__SHIFT                                                 0xe
#define GDS_DSM_CNTL__UNUSED__SHIFT                                                                           0xf
#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0_MASK                                                   0x00000001L
#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1_MASK                                                   0x00000002L
#define GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE_MASK                                                        0x00000004L
#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0_MASK                                           0x00000008L
#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1_MASK                                           0x00000010L
#define GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE_MASK                                                0x00000020L
#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0_MASK                                           0x00000040L
#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1_MASK                                           0x00000080L
#define GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE_MASK                                                0x00000100L
#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0_MASK                                          0x00000200L
#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1_MASK                                          0x00000400L
#define GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE_MASK                                               0x00000800L
#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0_MASK                                              0x00001000L
#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1_MASK                                              0x00002000L
#define GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE_MASK                                                   0x00004000L
#define GDS_DSM_CNTL__UNUSED_MASK                                                                             0xFFFF8000L
//GDS_EDC_OA_PHY_CNT
#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC__SHIFT                                                        0x0
#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED__SHIFT                                                        0x2
#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC__SHIFT                                                        0x4
#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED__SHIFT                                                        0x6
#define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SED__SHIFT                                                       0x8
#define GDS_EDC_OA_PHY_CNT__UNUSED1__SHIFT                                                                    0xa
#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC_MASK                                                          0x00000003L
#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED_MASK                                                          0x0000000CL
#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC_MASK                                                          0x00000030L
#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED_MASK                                                          0x000000C0L
#define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SED_MASK                                                         0x00000300L
#define GDS_EDC_OA_PHY_CNT__UNUSED1_MASK                                                                      0xFFFFFC00L
//GDS_EDC_OA_PIPE_CNT
#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC__SHIFT                                                    0x0
#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED__SHIFT                                                    0x2
#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC__SHIFT                                                    0x4
#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED__SHIFT                                                    0x6
#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC__SHIFT                                                    0x8
#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED__SHIFT                                                    0xa
#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC__SHIFT                                                    0xc
#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED__SHIFT                                                    0xe
#define GDS_EDC_OA_PIPE_CNT__UNUSED__SHIFT                                                                    0x10
#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC_MASK                                                      0x00000003L
#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED_MASK                                                      0x0000000CL
#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC_MASK                                                      0x00000030L
#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED_MASK                                                      0x000000C0L
#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC_MASK                                                      0x00000300L
#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED_MASK                                                      0x00000C00L
#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC_MASK                                                      0x00003000L
#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED_MASK                                                      0x0000C000L
#define GDS_EDC_OA_PIPE_CNT__UNUSED_MASK                                                                      0xFFFF0000L
//GDS_DSM_CNTL2
#define GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT__SHIFT                                                     0x0
#define GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY__SHIFT                                                     0x2
#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT__SHIFT                                             0x3
#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY__SHIFT                                             0x5
#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT__SHIFT                                             0x6
#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY__SHIFT                                             0x8
#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT__SHIFT                                            0x9
#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY__SHIFT                                            0xb
#define GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT__SHIFT                                                0xc
#define GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY__SHIFT                                                0xe
#define GDS_DSM_CNTL2__UNUSED__SHIFT                                                                          0xf
#define GDS_DSM_CNTL2__GDS_INJECT_DELAY__SHIFT                                                                0x1a
#define GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT_MASK                                                       0x00000003L
#define GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY_MASK                                                       0x00000004L
#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT_MASK                                               0x00000018L
#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY_MASK                                               0x00000020L
#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT_MASK                                               0x000000C0L
#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY_MASK                                               0x00000100L
#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT_MASK                                              0x00000600L
#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY_MASK                                              0x00000800L
#define GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT_MASK                                                  0x00003000L
#define GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY_MASK                                                  0x00004000L
#define GDS_DSM_CNTL2__UNUSED_MASK                                                                            0x03FF8000L
#define GDS_DSM_CNTL2__GDS_INJECT_DELAY_MASK                                                                  0xFC000000L
//GDS_WD_GDS_CSB
#define GDS_WD_GDS_CSB__COUNTER__SHIFT                                                                        0x0
#define GDS_WD_GDS_CSB__UNUSED__SHIFT                                                                         0xd
#define GDS_WD_GDS_CSB__COUNTER_MASK                                                                          0x00001FFFL
#define GDS_WD_GDS_CSB__UNUSED_MASK                                                                           0xFFFFE000L


// addressBlock: gc_rbdec
//DB_DEBUG
#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE__SHIFT                                                       0x0
#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE__SHIFT                                                         0x1
#define DB_DEBUG__FETCH_FULL_Z_TILE__SHIFT                                                                    0x2
#define DB_DEBUG__FETCH_FULL_STENCIL_TILE__SHIFT                                                              0x3
#define DB_DEBUG__FORCE_Z_MODE__SHIFT                                                                         0x4
#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ__SHIFT                                                               0x6
#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ__SHIFT                                                             0x7
#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE__SHIFT                                                               0x8
#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT                                                              0xa
#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1__SHIFT                                                              0xc
#define DB_DEBUG__DEBUG_FAST_Z_DISABLE__SHIFT                                                                 0xe
#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE__SHIFT                                                           0xf
#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE__SHIFT                                                              0x10
#define DB_DEBUG__DISABLE_SUMM_SQUADS__SHIFT                                                                  0x11
#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS__SHIFT                                                               0x12
#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE__SHIFT                                                             0x13
#define DB_DEBUG__NEVER_FREE_Z_ONLY__SHIFT                                                                    0x15
#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS__SHIFT                                                0x16
#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT                                                    0x17
#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES__SHIFT                                                           0x18
#define DB_DEBUG__ONE_FREE_IN_FLIGHT__SHIFT                                                                   0x1c
#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT                                                           0x1d
#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC__SHIFT                                                           0x1e
#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC__SHIFT                                                           0x1f
#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE_MASK                                                         0x00000001L
#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE_MASK                                                           0x00000002L
#define DB_DEBUG__FETCH_FULL_Z_TILE_MASK                                                                      0x00000004L
#define DB_DEBUG__FETCH_FULL_STENCIL_TILE_MASK                                                                0x00000008L
#define DB_DEBUG__FORCE_Z_MODE_MASK                                                                           0x00000030L
#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ_MASK                                                                 0x00000040L
#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ_MASK                                                               0x00000080L
#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE_MASK                                                                 0x00000300L
#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0_MASK                                                                0x00000C00L
#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1_MASK                                                                0x00003000L
#define DB_DEBUG__DEBUG_FAST_Z_DISABLE_MASK                                                                   0x00004000L
#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE_MASK                                                             0x00008000L
#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE_MASK                                                                0x00010000L
#define DB_DEBUG__DISABLE_SUMM_SQUADS_MASK                                                                    0x00020000L
#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS_MASK                                                                 0x00040000L
#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE_MASK                                                               0x00180000L
#define DB_DEBUG__NEVER_FREE_Z_ONLY_MASK                                                                      0x00200000L
#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS_MASK                                                  0x00400000L
#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK                                                      0x00800000L
#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES_MASK                                                             0x0F000000L
#define DB_DEBUG__ONE_FREE_IN_FLIGHT_MASK                                                                     0x10000000L
#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT_MASK                                                             0x20000000L
#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC_MASK                                                             0x40000000L
#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC_MASK                                                             0x80000000L
//DB_DEBUG2
#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING__SHIFT                                                            0x0
#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE__SHIFT                                                          0x1
#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE__SHIFT                                                            0x2
#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB__SHIFT                                                                 0x3
#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT                                                        0x4
#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL__SHIFT                                                            0x5
#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ__SHIFT                                                        0x6
#define DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL__SHIFT                                                        0x7
#define DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE__SHIFT                                                     0x8
#define DB_DEBUG2__CLK_OFF_DELAY__SHIFT                                                                       0x9
#define DB_DEBUG2__FORCE_PERF_COUNTERS_ON__SHIFT                                                              0xe
#define DB_DEBUG2__FULL_TILE_CACHE_EVICT_ON_HALF_FULL__SHIFT                                                  0xf
#define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES__SHIFT                                                          0x10
#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING__SHIFT                                                         0x11
#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING__SHIFT                                                         0x12
#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL__SHIFT                                                        0x13
#define DB_DEBUG2__FULL_TILE_WAVE_BREAK_MODE__SHIFT                                                           0x14
#define DB_DEBUG2__DUAL_PIPE_REZ_STALL_MANUAL_CONTROL__SHIFT                                                  0x16
#define DB_DEBUG2__DUAL_PIPE_REZ_STALL_SELECT_NEW__SHIFT                                                      0x17
#define DB_DEBUG2__FORCE_ITERATE_256__SHIFT                                                                   0x18
#define DB_DEBUG2__RESERVED1__SHIFT                                                                           0x1a
#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM__SHIFT                                                             0x1c
#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT                                                        0x1d
#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM__SHIFT                                                    0x1e
#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT__SHIFT                                                0x1f
#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING_MASK                                                              0x00000001L
#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE_MASK                                                            0x00000002L
#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE_MASK                                                              0x00000004L
#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB_MASK                                                                   0x00000008L
#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK                                                          0x00000010L
#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_MASK                                                              0x00000020L
#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ_MASK                                                          0x00000040L
#define DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL_MASK                                                          0x00000080L
#define DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE_MASK                                                       0x00000100L
#define DB_DEBUG2__CLK_OFF_DELAY_MASK                                                                         0x00003E00L
#define DB_DEBUG2__FORCE_PERF_COUNTERS_ON_MASK                                                                0x00004000L
#define DB_DEBUG2__FULL_TILE_CACHE_EVICT_ON_HALF_FULL_MASK                                                    0x00008000L
#define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES_MASK                                                            0x00010000L
#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING_MASK                                                           0x00020000L
#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING_MASK                                                           0x00040000L
#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL_MASK                                                          0x00080000L
#define DB_DEBUG2__FULL_TILE_WAVE_BREAK_MODE_MASK                                                             0x00300000L
#define DB_DEBUG2__DUAL_PIPE_REZ_STALL_MANUAL_CONTROL_MASK                                                    0x00400000L
#define DB_DEBUG2__DUAL_PIPE_REZ_STALL_SELECT_NEW_MASK                                                        0x00800000L
#define DB_DEBUG2__FORCE_ITERATE_256_MASK                                                                     0x03000000L
#define DB_DEBUG2__RESERVED1_MASK                                                                             0x04000000L
#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM_MASK                                                               0x10000000L
#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL_MASK                                                          0x20000000L
#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM_MASK                                                      0x40000000L
#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT_MASK                                                  0x80000000L
//DB_DEBUG3
#define DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION__SHIFT                                                     0x0
#define DB_DEBUG3__DISABLE_RELOAD_CONTEXT_DRAW_DATA__SHIFT                                                    0x1
#define DB_DEBUG3__FORCE_DB_IS_GOOD__SHIFT                                                                    0x2
#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION__SHIFT                                                     0x3
#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP__SHIFT                                                          0x4
#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z__SHIFT                                                             0x5
#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z__SHIFT                                                              0x6
#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS__SHIFT                                                              0x7
#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION__SHIFT                                                      0x8
#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT__SHIFT                                                 0x9
#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT                                            0xa
#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS__SHIFT                                                        0xb
#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING__SHIFT                                                        0xc
#define DB_DEBUG3__DISABLE_OP_DF_BYPASS__SHIFT                                                                0xd
#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE__SHIFT                                                         0xe
#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK__SHIFT                                                       0xf
#define DB_DEBUG3__DISABLE_SLOCS_PER_CTXT_MATCH__SHIFT                                                        0x10
#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE__SHIFT                                                         0x11
#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING__SHIFT                                                        0x12
#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE__SHIFT                                                     0x13
#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE__SHIFT                                                         0x14
#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT__SHIFT                                                0x15
#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB__SHIFT                                                        0x16
#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD__SHIFT                                                  0x17
#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT__SHIFT                                                           0x18
#define DB_DEBUG3__DISABLE_DI_DT_STALL__SHIFT                                                                 0x19
#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET__SHIFT                                                             0x1a
#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX__SHIFT                                                       0x1b
#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND__SHIFT                                                         0x1c
#define DB_DEBUG3__DELETE_CONTEXT_SUSPEND__SHIFT                                                              0x1d
#define DB_DEBUG3__DISABLE_TS_WRITE_L0__SHIFT                                                                 0x1e
#define DB_DEBUG3__DISABLE_MULTIDTAG_FL_PANIC_REQUIREMENT__SHIFT                                              0x1f
#define DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION_MASK                                                       0x00000001L
#define DB_DEBUG3__DISABLE_RELOAD_CONTEXT_DRAW_DATA_MASK                                                      0x00000002L
#define DB_DEBUG3__FORCE_DB_IS_GOOD_MASK                                                                      0x00000004L
#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION_MASK                                                       0x00000008L
#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP_MASK                                                            0x00000010L
#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z_MASK                                                               0x00000020L
#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z_MASK                                                                0x00000040L
#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS_MASK                                                                0x00000080L
#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION_MASK                                                        0x00000100L
#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT_MASK                                                   0x00000200L
#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP_MASK                                              0x00000400L
#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS_MASK                                                          0x00000800L
#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING_MASK                                                          0x00001000L
#define DB_DEBUG3__DISABLE_OP_DF_BYPASS_MASK                                                                  0x00002000L
#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE_MASK                                                           0x00004000L
#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK_MASK                                                         0x00008000L
#define DB_DEBUG3__DISABLE_SLOCS_PER_CTXT_MATCH_MASK                                                          0x00010000L
#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE_MASK                                                           0x00020000L
#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING_MASK                                                          0x00040000L
#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK                                                       0x00080000L
#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK                                                           0x00100000L
#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT_MASK                                                  0x00200000L
#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB_MASK                                                          0x00400000L
#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD_MASK                                                    0x00800000L
#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT_MASK                                                             0x01000000L
#define DB_DEBUG3__DISABLE_DI_DT_STALL_MASK                                                                   0x02000000L
#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET_MASK                                                               0x04000000L
#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX_MASK                                                         0x08000000L
#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND_MASK                                                           0x10000000L
#define DB_DEBUG3__DELETE_CONTEXT_SUSPEND_MASK                                                                0x20000000L
#define DB_DEBUG3__DISABLE_TS_WRITE_L0_MASK                                                                   0x40000000L
#define DB_DEBUG3__DISABLE_MULTIDTAG_FL_PANIC_REQUIREMENT_MASK                                                0x80000000L
//DB_DEBUG4
#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION__SHIFT                                                         0x0
#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION__SHIFT                                                   0x1
#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL__SHIFT                                                    0x2
#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL__SHIFT                                             0x3
#define DB_DEBUG4__DISABLE_SEPARATE_OP_PIPE_CLK__SHIFT                                                        0x4
#define DB_DEBUG4__DISABLE_SEPARATE_DFSM_CLK__SHIFT                                                           0x5
#define DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN__SHIFT                                                                0x6
#define DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE__SHIFT                                                    0x7
#define DB_DEBUG4__DFSM_CONVERT_PASSTHROUGH_TO_BYPASS__SHIFT                                                  0x8
#define DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR__SHIFT                                                        0x9
#define DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR__SHIFT                                                        0xa
#define DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR__SHIFT                                                        0xb
#define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION__SHIFT                                                       0xc
#define DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP__SHIFT                                                   0xd
#define DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION__SHIFT                                              0xe
#define DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE__SHIFT                                                0xf
#define DB_DEBUG4__DISABLE_HIZ_TS_COLLISION_DETECT__SHIFT                                                     0x10
#define DB_DEBUG4__DISABLE_LAST_OF_BURST_ON_ACCUM_ALL_EOT__SHIFT                                              0x11
#define DB_DEBUG4__DISABLE_LAST_OF_BURST_ON_FLUSH_CHUNK0_ALL_DONE__SHIFT                                      0x12
#define DB_DEBUG4__ENABLE_CZ_OVERFLOW_TESTMODE__SHIFT                                                         0x13
#define DB_DEBUG4__DISABLE_LATEZ_NO_EXPORT_POWER_SAVING__SHIFT                                                0x14
#define DB_DEBUG4__DISABLE_MCC_BURST_FIFO__SHIFT                                                              0x15
#define DB_DEBUG4__DISABLE_MCC_BURST_FIFO_CONFLICT__SHIFT                                                     0x16
#define DB_DEBUG4__DISABLE_WR_MEM_BURST_FLF_CONSECUTIVE_CHECK__SHIFT                                          0x17
#define DB_DEBUG4__WR_MEM_BURST_CTL__SHIFT                                                                    0x18
#define DB_DEBUG4__DISABLE_WR_MEM_BURST_POOLING__SHIFT                                                        0x1b
#define DB_DEBUG4__DISABLE_RD_MEM_BURST__SHIFT                                                                0x1c
#define DB_DEBUG4__LATE_ACK_SCOREBOARD_NEW__SHIFT                                                             0x1d
#define DB_DEBUG4__LATE_ACK_SCOREBOARD_MULTIPLE_SLOT__SHIFT                                                   0x1e
#define DB_DEBUG4__LATE_ACK_PSD_EOP_GFX9_METHOD__SHIFT                                                        0x1f
#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION_MASK                                                           0x00000001L
#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION_MASK                                                     0x00000002L
#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL_MASK                                                      0x00000004L
#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL_MASK                                               0x00000008L
#define DB_DEBUG4__DISABLE_SEPARATE_OP_PIPE_CLK_MASK                                                          0x00000010L
#define DB_DEBUG4__DISABLE_SEPARATE_DFSM_CLK_MASK                                                             0x00000020L
#define DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN_MASK                                                                  0x00000040L
#define DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE_MASK                                                      0x00000080L
#define DB_DEBUG4__DFSM_CONVERT_PASSTHROUGH_TO_BYPASS_MASK                                                    0x00000100L
#define DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR_MASK                                                          0x00000200L
#define DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR_MASK                                                          0x00000400L
#define DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR_MASK                                                          0x00000800L
#define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION_MASK                                                         0x00001000L
#define DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP_MASK                                                     0x00002000L
#define DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION_MASK                                                0x00004000L
#define DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE_MASK                                                  0x00008000L
#define DB_DEBUG4__DISABLE_HIZ_TS_COLLISION_DETECT_MASK                                                       0x00010000L
#define DB_DEBUG4__DISABLE_LAST_OF_BURST_ON_ACCUM_ALL_EOT_MASK                                                0x00020000L
#define DB_DEBUG4__DISABLE_LAST_OF_BURST_ON_FLUSH_CHUNK0_ALL_DONE_MASK                                        0x00040000L
#define DB_DEBUG4__ENABLE_CZ_OVERFLOW_TESTMODE_MASK                                                           0x00080000L
#define DB_DEBUG4__DISABLE_LATEZ_NO_EXPORT_POWER_SAVING_MASK                                                  0x00100000L
#define DB_DEBUG4__DISABLE_MCC_BURST_FIFO_MASK                                                                0x00200000L
#define DB_DEBUG4__DISABLE_MCC_BURST_FIFO_CONFLICT_MASK                                                       0x00400000L
#define DB_DEBUG4__DISABLE_WR_MEM_BURST_FLF_CONSECUTIVE_CHECK_MASK                                            0x00800000L
#define DB_DEBUG4__WR_MEM_BURST_CTL_MASK                                                                      0x07000000L
#define DB_DEBUG4__DISABLE_WR_MEM_BURST_POOLING_MASK                                                          0x08000000L
#define DB_DEBUG4__DISABLE_RD_MEM_BURST_MASK                                                                  0x10000000L
#define DB_DEBUG4__LATE_ACK_SCOREBOARD_NEW_MASK                                                               0x20000000L
#define DB_DEBUG4__LATE_ACK_SCOREBOARD_MULTIPLE_SLOT_MASK                                                     0x40000000L
#define DB_DEBUG4__LATE_ACK_PSD_EOP_GFX9_METHOD_MASK                                                          0x80000000L
//DB_ETILE_STUTTER_CONTROL
#define DB_ETILE_STUTTER_CONTROL__THRESHOLD__SHIFT                                                            0x0
#define DB_ETILE_STUTTER_CONTROL__TIMEOUT__SHIFT                                                              0x10
#define DB_ETILE_STUTTER_CONTROL__THRESHOLD_MASK                                                              0x000000FFL
#define DB_ETILE_STUTTER_CONTROL__TIMEOUT_MASK                                                                0x00FF0000L
//DB_LTILE_STUTTER_CONTROL
#define DB_LTILE_STUTTER_CONTROL__THRESHOLD__SHIFT                                                            0x0
#define DB_LTILE_STUTTER_CONTROL__TIMEOUT__SHIFT                                                              0x10
#define DB_LTILE_STUTTER_CONTROL__THRESHOLD_MASK                                                              0x000000FFL
#define DB_LTILE_STUTTER_CONTROL__TIMEOUT_MASK                                                                0x00FF0000L
//DB_EQUAD_STUTTER_CONTROL
#define DB_EQUAD_STUTTER_CONTROL__THRESHOLD__SHIFT                                                            0x0
#define DB_EQUAD_STUTTER_CONTROL__TIMEOUT__SHIFT                                                              0x10
#define DB_EQUAD_STUTTER_CONTROL__THRESHOLD_MASK                                                              0x000000FFL
#define DB_EQUAD_STUTTER_CONTROL__TIMEOUT_MASK                                                                0x00FF0000L
//DB_LQUAD_STUTTER_CONTROL
#define DB_LQUAD_STUTTER_CONTROL__THRESHOLD__SHIFT                                                            0x0
#define DB_LQUAD_STUTTER_CONTROL__TIMEOUT__SHIFT                                                              0x10
#define DB_LQUAD_STUTTER_CONTROL__THRESHOLD_MASK                                                              0x000000FFL
#define DB_LQUAD_STUTTER_CONTROL__TIMEOUT_MASK                                                                0x00FF0000L
//DB_CREDIT_LIMIT
#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS__SHIFT                                                            0x0
#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS__SHIFT                                                            0x5
#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS__SHIFT                                                           0xa
#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS__SHIFT                                                            0x18
#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS_MASK                                                              0x0000001FL
#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS_MASK                                                              0x000003E0L
#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS_MASK                                                             0x00001C00L
#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS_MASK                                                              0x7F000000L
//DB_WATERMARKS
#define DB_WATERMARKS__DEPTH_FREE__SHIFT                                                                      0x0
#define DB_WATERMARKS__DEPTH_FLUSH__SHIFT                                                                     0x8
#define DB_WATERMARKS__DEPTH_PENDING_FREE__SHIFT                                                              0x10
#define DB_WATERMARKS__DEPTH_CACHELINE_FREE__SHIFT                                                            0x18
#define DB_WATERMARKS__DEPTH_FREE_MASK                                                                        0x000000FFL
#define DB_WATERMARKS__DEPTH_FLUSH_MASK                                                                       0x0000FF00L
#define DB_WATERMARKS__DEPTH_PENDING_FREE_MASK                                                                0x00FF0000L
#define DB_WATERMARKS__DEPTH_CACHELINE_FREE_MASK                                                              0xFF000000L
//DB_SUBTILE_CONTROL
#define DB_SUBTILE_CONTROL__MSAA1_X__SHIFT                                                                    0x0
#define DB_SUBTILE_CONTROL__MSAA1_Y__SHIFT                                                                    0x2
#define DB_SUBTILE_CONTROL__MSAA2_X__SHIFT                                                                    0x4
#define DB_SUBTILE_CONTROL__MSAA2_Y__SHIFT                                                                    0x6
#define DB_SUBTILE_CONTROL__MSAA4_X__SHIFT                                                                    0x8
#define DB_SUBTILE_CONTROL__MSAA4_Y__SHIFT                                                                    0xa
#define DB_SUBTILE_CONTROL__MSAA8_X__SHIFT                                                                    0xc
#define DB_SUBTILE_CONTROL__MSAA8_Y__SHIFT                                                                    0xe
#define DB_SUBTILE_CONTROL__MSAA16_X__SHIFT                                                                   0x10
#define DB_SUBTILE_CONTROL__MSAA16_Y__SHIFT                                                                   0x12
#define DB_SUBTILE_CONTROL__MSAA1_X_MASK                                                                      0x00000003L
#define DB_SUBTILE_CONTROL__MSAA1_Y_MASK                                                                      0x0000000CL
#define DB_SUBTILE_CONTROL__MSAA2_X_MASK                                                                      0x00000030L
#define DB_SUBTILE_CONTROL__MSAA2_Y_MASK                                                                      0x000000C0L
#define DB_SUBTILE_CONTROL__MSAA4_X_MASK                                                                      0x00000300L
#define DB_SUBTILE_CONTROL__MSAA4_Y_MASK                                                                      0x00000C00L
#define DB_SUBTILE_CONTROL__MSAA8_X_MASK                                                                      0x00003000L
#define DB_SUBTILE_CONTROL__MSAA8_Y_MASK                                                                      0x0000C000L
#define DB_SUBTILE_CONTROL__MSAA16_X_MASK                                                                     0x00030000L
#define DB_SUBTILE_CONTROL__MSAA16_Y_MASK                                                                     0x000C0000L
//DB_FREE_CACHELINES
#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH__SHIFT                                                           0x0
#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH__SHIFT                                                           0x8
#define DB_FREE_CACHELINES__FREE_Z_DEPTH__SHIFT                                                               0x10
#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH__SHIFT                                                           0x18
#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH_MASK                                                             0x000000FFL
#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH_MASK                                                             0x0000FF00L
#define DB_FREE_CACHELINES__FREE_Z_DEPTH_MASK                                                                 0x00FF0000L
#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH_MASK                                                             0xFF000000L
//DB_FIFO_DEPTH1
#define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH__SHIFT                                                            0x0
#define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH__SHIFT                                                            0x8
#define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT                                                                      0x10
#define DB_FIFO_DEPTH1__QC_DEPTH__SHIFT                                                                       0x18
#define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH_MASK                                                              0x000000FFL
#define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH_MASK                                                              0x0000FF00L
#define DB_FIFO_DEPTH1__MCC_DEPTH_MASK                                                                        0x00FF0000L
#define DB_FIFO_DEPTH1__QC_DEPTH_MASK                                                                         0xFF000000L
//DB_FIFO_DEPTH2
#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH__SHIFT                                                               0x0
#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH__SHIFT                                                            0x8
#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH__SHIFT                                                               0x10
#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH__SHIFT                                                            0x19
#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH_MASK                                                                 0x000000FFL
#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH_MASK                                                              0x0000FF00L
#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH_MASK                                                                 0x01FF0000L
#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH_MASK                                                              0xFE000000L
//DB_LAST_OF_BURST_CONFIG
#define DB_LAST_OF_BURST_CONFIG__MAXBURST__SHIFT                                                              0x0
#define DB_LAST_OF_BURST_CONFIG__TIMEOUT__SHIFT                                                               0x8
#define DB_LAST_OF_BURST_CONFIG__DBCB_LOB_SWITCH_TIMEOUT__SHIFT                                               0xb
#define DB_LAST_OF_BURST_CONFIG__DBCB_LOB_USES_MAXBURST__SHIFT                                                0x10
#define DB_LAST_OF_BURST_CONFIG__ENABLE_FG_DEFAULT_TIMEOUT__SHIFT                                             0x11
#define DB_LAST_OF_BURST_CONFIG__DISABLE_MCC_BURST_COUNT_RESET_ON_LOB__SHIFT                                  0x12
#define DB_LAST_OF_BURST_CONFIG__DISABLE_FLQ_LOB_EVERY_256B__SHIFT                                            0x13
#define DB_LAST_OF_BURST_CONFIG__DISABLE_ZCACHE_FL_OP_EVEN_ARB__SHIFT                                         0x14
#define DB_LAST_OF_BURST_CONFIG__DISABLE_MCC_BURST_FORCE_FLUSH_BEFORE_FIFO__SHIFT                             0x15
#define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_FL_BURST__SHIFT                                               0x19
#define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_FG_LOB_FWDR__SHIFT                                            0x1a
#define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_RD_BA_ACCUM__SHIFT                                            0x1b
#define DB_LAST_OF_BURST_CONFIG__BYPASS_SORT_RD_BA__SHIFT                                                     0x1c
#define DB_LAST_OF_BURST_CONFIG__DISABLE_256B_COALESCE__SHIFT                                                 0x1d
#define DB_LAST_OF_BURST_CONFIG__DISABLE_RD_BURST__SHIFT                                                      0x1e
#define DB_LAST_OF_BURST_CONFIG__LEGACY_LOB_INSERT_EN__SHIFT                                                  0x1f
#define DB_LAST_OF_BURST_CONFIG__MAXBURST_MASK                                                                0x000000FFL
#define DB_LAST_OF_BURST_CONFIG__TIMEOUT_MASK                                                                 0x00000700L
#define DB_LAST_OF_BURST_CONFIG__DBCB_LOB_SWITCH_TIMEOUT_MASK                                                 0x0000F800L
#define DB_LAST_OF_BURST_CONFIG__DBCB_LOB_USES_MAXBURST_MASK                                                  0x00010000L
#define DB_LAST_OF_BURST_CONFIG__ENABLE_FG_DEFAULT_TIMEOUT_MASK                                               0x00020000L
#define DB_LAST_OF_BURST_CONFIG__DISABLE_MCC_BURST_COUNT_RESET_ON_LOB_MASK                                    0x00040000L
#define DB_LAST_OF_BURST_CONFIG__DISABLE_FLQ_LOB_EVERY_256B_MASK                                              0x00080000L
#define DB_LAST_OF_BURST_CONFIG__DISABLE_ZCACHE_FL_OP_EVEN_ARB_MASK                                           0x00100000L
#define DB_LAST_OF_BURST_CONFIG__DISABLE_MCC_BURST_FORCE_FLUSH_BEFORE_FIFO_MASK                               0x00200000L
#define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_FL_BURST_MASK                                                 0x02000000L
#define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_FG_LOB_FWDR_MASK                                              0x04000000L
#define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_RD_BA_ACCUM_MASK                                              0x08000000L
#define DB_LAST_OF_BURST_CONFIG__BYPASS_SORT_RD_BA_MASK                                                       0x10000000L
#define DB_LAST_OF_BURST_CONFIG__DISABLE_256B_COALESCE_MASK                                                   0x20000000L
#define DB_LAST_OF_BURST_CONFIG__DISABLE_RD_BURST_MASK                                                        0x40000000L
#define DB_LAST_OF_BURST_CONFIG__LEGACY_LOB_INSERT_EN_MASK                                                    0x80000000L
//DB_RING_CONTROL
#define DB_RING_CONTROL__COUNTER_CONTROL__SHIFT                                                               0x0
#define DB_RING_CONTROL__COUNTER_CONTROL_MASK                                                                 0x00000003L
//DB_MEM_ARB_WATERMARKS
#define DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK__SHIFT                                                       0x0
#define DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK__SHIFT                                                       0x8
#define DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK__SHIFT                                                       0x10
#define DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK__SHIFT                                                       0x18
#define DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK_MASK                                                         0x00000007L
#define DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK_MASK                                                         0x00000700L
#define DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK_MASK                                                         0x00070000L
#define DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK_MASK                                                         0x07000000L
//DB_FIFO_DEPTH3
#define DB_FIFO_DEPTH3__LTILE_PROBE_FIFO_DEPTH__SHIFT                                                         0x0
#define DB_FIFO_DEPTH3__QUAD_READ_REQS__SHIFT                                                                 0x18
#define DB_FIFO_DEPTH3__LTILE_PROBE_FIFO_DEPTH_MASK                                                           0x000000FFL
#define DB_FIFO_DEPTH3__QUAD_READ_REQS_MASK                                                                   0xFF000000L
//DB_RMI_BC_GL2_CACHE_CONTROL
#define DB_RMI_BC_GL2_CACHE_CONTROL__Z_WR_POLICY__SHIFT                                                       0x0
#define DB_RMI_BC_GL2_CACHE_CONTROL__S_WR_POLICY__SHIFT                                                       0x2
#define DB_RMI_BC_GL2_CACHE_CONTROL__HTILE_WR_POLICY__SHIFT                                                   0x4
#define DB_RMI_BC_GL2_CACHE_CONTROL__ZPCPSD_WR_POLICY__SHIFT                                                  0x6
#define DB_RMI_BC_GL2_CACHE_CONTROL__Z_RD_POLICY__SHIFT                                                       0x10
#define DB_RMI_BC_GL2_CACHE_CONTROL__S_RD_POLICY__SHIFT                                                       0x12
#define DB_RMI_BC_GL2_CACHE_CONTROL__HTILE_RD_POLICY__SHIFT                                                   0x14
#define DB_RMI_BC_GL2_CACHE_CONTROL__VOL__SHIFT                                                               0x1f
#define DB_RMI_BC_GL2_CACHE_CONTROL__Z_WR_POLICY_MASK                                                         0x00000003L
#define DB_RMI_BC_GL2_CACHE_CONTROL__S_WR_POLICY_MASK                                                         0x0000000CL
#define DB_RMI_BC_GL2_CACHE_CONTROL__HTILE_WR_POLICY_MASK                                                     0x00000030L
#define DB_RMI_BC_GL2_CACHE_CONTROL__ZPCPSD_WR_POLICY_MASK                                                    0x000000C0L
#define DB_RMI_BC_GL2_CACHE_CONTROL__Z_RD_POLICY_MASK                                                         0x00030000L
#define DB_RMI_BC_GL2_CACHE_CONTROL__S_RD_POLICY_MASK                                                         0x000C0000L
#define DB_RMI_BC_GL2_CACHE_CONTROL__HTILE_RD_POLICY_MASK                                                     0x00300000L
#define DB_RMI_BC_GL2_CACHE_CONTROL__VOL_MASK                                                                 0x80000000L
//DB_EXCEPTION_CONTROL
#define DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE__SHIFT                                                    0x0
#define DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE__SHIFT                                                     0x1
#define DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE__SHIFT                                                       0x2
#define DB_EXCEPTION_CONTROL__AUTO_FLUSH_HTILE__SHIFT                                                         0x3
#define DB_EXCEPTION_CONTROL__AUTO_FLUSH_QUAD__SHIFT                                                          0x4
#define DB_EXCEPTION_CONTROL__FORCE_SUMMARIZE__SHIFT                                                          0x8
#define DB_EXCEPTION_CONTROL__DTAG_WATERMARK__SHIFT                                                           0x18
#define DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE_MASK                                                      0x00000001L
#define DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE_MASK                                                       0x00000002L
#define DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE_MASK                                                         0x00000004L
#define DB_EXCEPTION_CONTROL__AUTO_FLUSH_HTILE_MASK                                                           0x00000008L
#define DB_EXCEPTION_CONTROL__AUTO_FLUSH_QUAD_MASK                                                            0x00000010L
#define DB_EXCEPTION_CONTROL__FORCE_SUMMARIZE_MASK                                                            0x00000F00L
#define DB_EXCEPTION_CONTROL__DTAG_WATERMARK_MASK                                                             0x7F000000L
//DB_DFSM_CONFIG
#define DB_DFSM_CONFIG__BYPASS_DFSM__SHIFT                                                                    0x0
#define DB_DFSM_CONFIG__DISABLE_PUNCHOUT__SHIFT                                                               0x1
#define DB_DFSM_CONFIG__DISABLE_POPS__SHIFT                                                                   0x2
#define DB_DFSM_CONFIG__FORCE_FLUSH__SHIFT                                                                    0x3
#define DB_DFSM_CONFIG__SQUAD_WATERMARK__SHIFT                                                                0x4
#define DB_DFSM_CONFIG__POPS_INCREMENT_CONTROL__SHIFT                                                         0xe
#define DB_DFSM_CONFIG__CAM_WATERMARK__SHIFT                                                                  0x10
#define DB_DFSM_CONFIG__FORCE_PUNCHOUT_5BIT_MODE__SHIFT                                                       0x17
#define DB_DFSM_CONFIG__OUTPUT_WATCHDOG__SHIFT                                                                0x18
#define DB_DFSM_CONFIG__BYPASS_DFSM_MASK                                                                      0x00000001L
#define DB_DFSM_CONFIG__DISABLE_PUNCHOUT_MASK                                                                 0x00000002L
#define DB_DFSM_CONFIG__DISABLE_POPS_MASK                                                                     0x00000004L
#define DB_DFSM_CONFIG__FORCE_FLUSH_MASK                                                                      0x00000008L
#define DB_DFSM_CONFIG__SQUAD_WATERMARK_MASK                                                                  0x00003FF0L
#define DB_DFSM_CONFIG__POPS_INCREMENT_CONTROL_MASK                                                           0x0000C000L
#define DB_DFSM_CONFIG__CAM_WATERMARK_MASK                                                                    0x007F0000L
#define DB_DFSM_CONFIG__FORCE_PUNCHOUT_5BIT_MODE_MASK                                                         0x00800000L
#define DB_DFSM_CONFIG__OUTPUT_WATCHDOG_MASK                                                                  0xFF000000L
//DB_DEBUG5
#define DB_DEBUG5__DISABLE_TILE_CACHE_PRELOAD__SHIFT                                                          0x0
#define DB_DEBUG5__ENABLE_SECONDARY_MIPS_TAILS_COMPRESSION__SHIFT                                             0x1
#define DB_DEBUG5__DISABLE_CLEAR_VALUE_UPDATE_ON_TILE_CACHE_HIT__SHIFT                                        0x2
#define DB_DEBUG5__DISABLE_DB_CB_TILE_SEND_ON_CB_TILE_ONLY_MODES__SHIFT                                       0x3
#define DB_DEBUG5__DISABLE_FLQ_MCC_DTILEID_CHECK__SHIFT                                                       0x4
#define DB_DEBUG5__DISABLE_NOZ_POWER_SAVINGS__SHIFT                                                           0x5
#define DB_DEBUG5__ENABLE_DUAL_QUAD_MODE_IN_BC__SHIFT                                                         0x6
#define DB_DEBUG5__DISABLE_MGCG_GATING_ON_SHADER_WAIT__SHIFT                                                  0x7
#define DB_DEBUG5__DISABLE_DF_TILE_PANIC__SHIFT                                                               0x8
#define DB_DEBUG5__ENABLE_FULL_TILE_WAVE_BREAK_ON_COARSE__SHIFT                                               0x9
#define DB_DEBUG5__DISABLE_RTINDEX_MASKING_IN_BC__SHIFT                                                       0xa
#define DB_DEBUG5__DISABLE_ZPASS_ADDR_CLAMP_IN_BC__SHIFT                                                      0xb
#define DB_DEBUG5__DISABLE_TILE_CACHE_PREFETCH__SHIFT                                                         0xc
#define DB_DEBUG5__DISABLE_PSL_AUTO_MODE_FIX__SHIFT                                                           0xd
#define DB_DEBUG5__DISABLE_FORCE_ZMASK_EXPANDED__SHIFT                                                        0xe
#define DB_DEBUG5__SPARE_BIT_15__SHIFT                                                                        0xf
#define DB_DEBUG5__DISABLE_Z_WITHOUT_PLANES_FLQ__SHIFT                                                        0x10
#define DB_DEBUG5__PRESERVE_QMASK_FOR_POSTZ_OP_PIPE__SHIFT                                                    0x11
#define DB_DEBUG5__Z_NACK_BEHAVIOR_ONLY_WHEN_Z_IS_PRT__SHIFT                                                  0x12
#define DB_DEBUG5__S_NACK_BEHAVIOR_ONLY_WHEN_S_IS_PRT__SHIFT                                                  0x13
#define DB_DEBUG5__DISABLE_RESIDENCY_CHECK_Z__SHIFT                                                           0x14
#define DB_DEBUG5__DISABLE_RESIDENCY_CHECK_STENCIL__SHIFT                                                     0x15
#define DB_DEBUG5__DISABLE_LQO_FTCQ_DUAL_QUAD_REGION_CHECK__SHIFT                                             0x16
#define DB_DEBUG5__DISABLE_EVENT_INSERTION_AFTER_ZPC_BEFORE_CONTEXT_DONE__SHIFT                               0x17
#define DB_DEBUG5__DISABLE_HTILE_HARVESTING__SHIFT                                                            0x18
#define DB_DEBUG5__SPARE_BITS__SHIFT                                                                          0x19
#define DB_DEBUG5__DISABLE_TILE_CACHE_PRELOAD_MASK                                                            0x00000001L
#define DB_DEBUG5__ENABLE_SECONDARY_MIPS_TAILS_COMPRESSION_MASK                                               0x00000002L
#define DB_DEBUG5__DISABLE_CLEAR_VALUE_UPDATE_ON_TILE_CACHE_HIT_MASK                                          0x00000004L
#define DB_DEBUG5__DISABLE_DB_CB_TILE_SEND_ON_CB_TILE_ONLY_MODES_MASK                                         0x00000008L
#define DB_DEBUG5__DISABLE_FLQ_MCC_DTILEID_CHECK_MASK                                                         0x00000010L
#define DB_DEBUG5__DISABLE_NOZ_POWER_SAVINGS_MASK                                                             0x00000020L
#define DB_DEBUG5__ENABLE_DUAL_QUAD_MODE_IN_BC_MASK                                                           0x00000040L
#define DB_DEBUG5__DISABLE_MGCG_GATING_ON_SHADER_WAIT_MASK                                                    0x00000080L
#define DB_DEBUG5__DISABLE_DF_TILE_PANIC_MASK                                                                 0x00000100L
#define DB_DEBUG5__ENABLE_FULL_TILE_WAVE_BREAK_ON_COARSE_MASK                                                 0x00000200L
#define DB_DEBUG5__DISABLE_RTINDEX_MASKING_IN_BC_MASK                                                         0x00000400L
#define DB_DEBUG5__DISABLE_ZPASS_ADDR_CLAMP_IN_BC_MASK                                                        0x00000800L
#define DB_DEBUG5__DISABLE_TILE_CACHE_PREFETCH_MASK                                                           0x00001000L
#define DB_DEBUG5__DISABLE_PSL_AUTO_MODE_FIX_MASK                                                             0x00002000L
#define DB_DEBUG5__DISABLE_FORCE_ZMASK_EXPANDED_MASK                                                          0x00004000L
#define DB_DEBUG5__SPARE_BIT_15_MASK                                                                          0x00008000L
#define DB_DEBUG5__DISABLE_Z_WITHOUT_PLANES_FLQ_MASK                                                          0x00010000L
#define DB_DEBUG5__PRESERVE_QMASK_FOR_POSTZ_OP_PIPE_MASK                                                      0x00020000L
#define DB_DEBUG5__Z_NACK_BEHAVIOR_ONLY_WHEN_Z_IS_PRT_MASK                                                    0x00040000L
#define DB_DEBUG5__S_NACK_BEHAVIOR_ONLY_WHEN_S_IS_PRT_MASK                                                    0x00080000L
#define DB_DEBUG5__DISABLE_RESIDENCY_CHECK_Z_MASK                                                             0x00100000L
#define DB_DEBUG5__DISABLE_RESIDENCY_CHECK_STENCIL_MASK                                                       0x00200000L
#define DB_DEBUG5__DISABLE_LQO_FTCQ_DUAL_QUAD_REGION_CHECK_MASK                                               0x00400000L
#define DB_DEBUG5__DISABLE_EVENT_INSERTION_AFTER_ZPC_BEFORE_CONTEXT_DONE_MASK                                 0x00800000L
#define DB_DEBUG5__DISABLE_HTILE_HARVESTING_MASK                                                              0x01000000L
#define DB_DEBUG5__SPARE_BITS_MASK                                                                            0xFE000000L
//DB_DFSM_TILES_IN_FLIGHT
#define DB_DFSM_TILES_IN_FLIGHT__HIGH_WATERMARK__SHIFT                                                        0x0
#define DB_DFSM_TILES_IN_FLIGHT__HIGH_WATERMARK_MASK                                                          0x0000FFFFL
//DB_DFSM_PRIMS_IN_FLIGHT
#define DB_DFSM_PRIMS_IN_FLIGHT__HIGH_WATERMARK__SHIFT                                                        0x0
#define DB_DFSM_PRIMS_IN_FLIGHT__HIGH_WATERMARK_MASK                                                          0x0000FFFFL
//DB_DFSM_WATCHDOG
#define DB_DFSM_WATCHDOG__TIMER_TARGET__SHIFT                                                                 0x0
#define DB_DFSM_WATCHDOG__TIMER_TARGET_MASK                                                                   0xFFFFFFFFL
//DB_DFSM_FLUSH_ENABLE
#define DB_DFSM_FLUSH_ENABLE__PRIMARY_EVENTS__SHIFT                                                           0x0
#define DB_DFSM_FLUSH_ENABLE__AUX_FORCE_PASSTHRU__SHIFT                                                       0x18
#define DB_DFSM_FLUSH_ENABLE__AUX_EVENTS__SHIFT                                                               0x1c
#define DB_DFSM_FLUSH_ENABLE__PRIMARY_EVENTS_MASK                                                             0x000007FFL
#define DB_DFSM_FLUSH_ENABLE__AUX_FORCE_PASSTHRU_MASK                                                         0x0F000000L
#define DB_DFSM_FLUSH_ENABLE__AUX_EVENTS_MASK                                                                 0xF0000000L
//DB_DFSM_FLUSH_AUX_EVENT
#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_A__SHIFT                                                               0x0
#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_B__SHIFT                                                               0x8
#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_C__SHIFT                                                               0x10
#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_D__SHIFT                                                               0x18
#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_A_MASK                                                                 0x000000FFL
#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_B_MASK                                                                 0x0000FF00L
#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_C_MASK                                                                 0x00FF0000L
#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_D_MASK                                                                 0xFF000000L
//DB_FGCG_SRAMS_CLK_CTRL
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE0__SHIFT                                                              0x0
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE1__SHIFT                                                              0x1
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE2__SHIFT                                                              0x2
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE3__SHIFT                                                              0x3
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE4__SHIFT                                                              0x4
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE5__SHIFT                                                              0x5
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE6__SHIFT                                                              0x6
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE7__SHIFT                                                              0x7
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE8__SHIFT                                                              0x8
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE9__SHIFT                                                              0x9
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE10__SHIFT                                                             0xa
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE11__SHIFT                                                             0xb
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE12__SHIFT                                                             0xc
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE13__SHIFT                                                             0xd
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE14__SHIFT                                                             0xe
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE15__SHIFT                                                             0xf
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE16__SHIFT                                                             0x10
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE17__SHIFT                                                             0x11
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE18__SHIFT                                                             0x12
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE19__SHIFT                                                             0x13
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE20__SHIFT                                                             0x14
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE21__SHIFT                                                             0x15
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE22__SHIFT                                                             0x16
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE23__SHIFT                                                             0x17
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE24__SHIFT                                                             0x18
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE25__SHIFT                                                             0x19
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE26__SHIFT                                                             0x1a
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE0_MASK                                                                0x00000001L
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE1_MASK                                                                0x00000002L
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE2_MASK                                                                0x00000004L
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE3_MASK                                                                0x00000008L
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE4_MASK                                                                0x00000010L
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE5_MASK                                                                0x00000020L
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE6_MASK                                                                0x00000040L
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE7_MASK                                                                0x00000080L
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE8_MASK                                                                0x00000100L
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE9_MASK                                                                0x00000200L
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE10_MASK                                                               0x00000400L
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE11_MASK                                                               0x00000800L
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE12_MASK                                                               0x00001000L
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE13_MASK                                                               0x00002000L
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE14_MASK                                                               0x00004000L
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE15_MASK                                                               0x00008000L
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE16_MASK                                                               0x00010000L
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE17_MASK                                                               0x00020000L
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE18_MASK                                                               0x00040000L
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE19_MASK                                                               0x00080000L
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE20_MASK                                                               0x00100000L
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE21_MASK                                                               0x00200000L
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE22_MASK                                                               0x00400000L
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE23_MASK                                                               0x00800000L
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE24_MASK                                                               0x01000000L
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE25_MASK                                                               0x02000000L
#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE26_MASK                                                               0x04000000L
//DB_FGCG_INTERFACES_CLK_CTRL
#define DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_QUAD_OVERRIDE__SHIFT                                               0x0
#define DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_TILE_OVERRIDE__SHIFT                                               0x1
#define DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_LQUAD_OVERRIDE__SHIFT                                              0x2
#define DB_FGCG_INTERFACES_CLK_CTRL__DB_RMI_RDREQ_OVERRIDE__SHIFT                                             0x3
#define DB_FGCG_INTERFACES_CLK_CTRL__DB_RMI_WRREQ_OVERRIDE__SHIFT                                             0x4
#define DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_TILE_OVERRIDE__SHIFT                                               0x5
#define DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_RMIRET_OVERRIDE__SHIFT                                             0x6
#define DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_QUAD_OVERRIDE_MASK                                                 0x00000001L
#define DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_TILE_OVERRIDE_MASK                                                 0x00000002L
#define DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_LQUAD_OVERRIDE_MASK                                                0x00000004L
#define DB_FGCG_INTERFACES_CLK_CTRL__DB_RMI_RDREQ_OVERRIDE_MASK                                               0x00000008L
#define DB_FGCG_INTERFACES_CLK_CTRL__DB_RMI_WRREQ_OVERRIDE_MASK                                               0x00000010L
#define DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_TILE_OVERRIDE_MASK                                                 0x00000020L
#define DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_RMIRET_OVERRIDE_MASK                                               0x00000040L
//CC_RB_REDUNDANCY
#define CC_RB_REDUNDANCY__FAILED_RB0__SHIFT                                                                   0x8
#define CC_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT                                                               0xc
#define CC_RB_REDUNDANCY__FAILED_RB1__SHIFT                                                                   0x10
#define CC_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT                                                               0x14
#define CC_RB_REDUNDANCY__FAILED_RB0_MASK                                                                     0x00000F00L
#define CC_RB_REDUNDANCY__EN_REDUNDANCY0_MASK                                                                 0x00001000L
#define CC_RB_REDUNDANCY__FAILED_RB1_MASK                                                                     0x000F0000L
#define CC_RB_REDUNDANCY__EN_REDUNDANCY1_MASK                                                                 0x00100000L
//CC_RB_BACKEND_DISABLE
#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT                                                         0x10
#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK                                                           0x00FF0000L
//GB_ADDR_CONFIG
#define GB_ADDR_CONFIG__NUM_PIPES__SHIFT                                                                      0x0
#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT                                                           0x3
#define GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                           0x6
#define GB_ADDR_CONFIG__NUM_PKRS__SHIFT                                                                       0x8
#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT                                                             0x13
#define GB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT                                                                  0x1a
#define GB_ADDR_CONFIG__NUM_PIPES_MASK                                                                        0x00000007L
#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK                                                             0x00000038L
#define GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                             0x000000C0L
#define GB_ADDR_CONFIG__NUM_PKRS_MASK                                                                         0x00000700L
#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK                                                               0x00180000L
#define GB_ADDR_CONFIG__NUM_RB_PER_SE_MASK                                                                    0x0C000000L
//GB_BACKEND_MAP
#define GB_BACKEND_MAP__BACKEND_MAP__SHIFT                                                                    0x0
#define GB_BACKEND_MAP__BACKEND_MAP_MASK                                                                      0xFFFFFFFFL
//GB_GPU_ID
#define GB_GPU_ID__GPU_ID__SHIFT                                                                              0x0
#define GB_GPU_ID__GPU_ID_MASK                                                                                0x0000000FL
//CC_RB_DAISY_CHAIN
#define CC_RB_DAISY_CHAIN__RB_0__SHIFT                                                                        0x0
#define CC_RB_DAISY_CHAIN__RB_1__SHIFT                                                                        0x4
#define CC_RB_DAISY_CHAIN__RB_2__SHIFT                                                                        0x8
#define CC_RB_DAISY_CHAIN__RB_3__SHIFT                                                                        0xc
#define CC_RB_DAISY_CHAIN__RB_4__SHIFT                                                                        0x10
#define CC_RB_DAISY_CHAIN__RB_5__SHIFT                                                                        0x14
#define CC_RB_DAISY_CHAIN__RB_6__SHIFT                                                                        0x18
#define CC_RB_DAISY_CHAIN__RB_7__SHIFT                                                                        0x1c
#define CC_RB_DAISY_CHAIN__RB_0_MASK                                                                          0x0000000FL
#define CC_RB_DAISY_CHAIN__RB_1_MASK                                                                          0x000000F0L
#define CC_RB_DAISY_CHAIN__RB_2_MASK                                                                          0x00000F00L
#define CC_RB_DAISY_CHAIN__RB_3_MASK                                                                          0x0000F000L
#define CC_RB_DAISY_CHAIN__RB_4_MASK                                                                          0x000F0000L
#define CC_RB_DAISY_CHAIN__RB_5_MASK                                                                          0x00F00000L
#define CC_RB_DAISY_CHAIN__RB_6_MASK                                                                          0x0F000000L
#define CC_RB_DAISY_CHAIN__RB_7_MASK                                                                          0xF0000000L
//GB_ADDR_CONFIG_READ
#define GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT                                                                 0x0
#define GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT                                                      0x3
#define GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT                                                      0x6
#define GB_ADDR_CONFIG_READ__NUM_PKRS__SHIFT                                                                  0x8
#define GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT                                                        0x13
#define GB_ADDR_CONFIG_READ__NUM_RB_PER_SE__SHIFT                                                             0x1a
#define GB_ADDR_CONFIG_READ__NUM_PIPES_MASK                                                                   0x00000007L
#define GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK                                                        0x00000038L
#define GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK                                                        0x000000C0L
#define GB_ADDR_CONFIG_READ__NUM_PKRS_MASK                                                                    0x00000700L
#define GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK                                                          0x00180000L
#define GB_ADDR_CONFIG_READ__NUM_RB_PER_SE_MASK                                                               0x0C000000L
//CB_HW_CONTROL_4
#define CB_HW_CONTROL_4__COLOR_CACHE_FETCH_NUM_CLS_LOG2__SHIFT                                                0x0
#define CB_HW_CONTROL_4__FMASK_CACHE_FETCH_NUM_CLS_LOG2__SHIFT                                                0x3
#define CB_HW_CONTROL_4__DISABLE_USE_OF_QUAD_SCOREBOARD__SHIFT                                                0x5
#define CB_HW_CONTROL_4__DISABLE_CMASK_CLOCK_GATING__SHIFT                                                    0x6
#define CB_HW_CONTROL_4__DISABLE_FMASK_CLOCK_GATING__SHIFT                                                    0x7
#define CB_HW_CONTROL_4__DISABLE_COLOR_CLOCK_GATING__SHIFT                                                    0x8
#define CB_HW_CONTROL_4__DISABLE_QSB_AA_MODE__SHIFT                                                           0x9
#define CB_HW_CONTROL_4__DISABLE_QSB_WAIT_FOR_SCORE__SHIFT                                                    0xa
#define CB_HW_CONTROL_4__DISABLE_QSB_FRAG_GT0__SHIFT                                                          0xb
#define CB_HW_CONTROL_4__REVERSE_KEYXFR_RD_PRIORITY__SHIFT                                                    0xc
#define CB_HW_CONTROL_4__DISABLE_KEYXFR_HIT_RETURNS__SHIFT                                                    0xd
#define CB_HW_CONTROL_4__DISABLE_BC_COLOR_CACHE_PREFETCH__SHIFT                                               0xe
#define CB_HW_CONTROL_4__DISABLE_MA_WAIT_FOR_LAST__SHIFT                                                      0xf
#define CB_HW_CONTROL_4__DISABLE_QSB_SPECULATIVE__SHIFT                                                       0x10
#define CB_HW_CONTROL_4__QSB_WAIT_FOR_SCORE__SHIFT                                                            0x11
#define CB_HW_CONTROL_4__DISABLE_TILE_FGCG__SHIFT                                                             0x16
#define CB_HW_CONTROL_4__DISABLE_LQUAD_FGCG__SHIFT                                                            0x17
#define CB_HW_CONTROL_4__FC_QSB_FIFO_DEPTH__SHIFT                                                             0x18
#define CB_HW_CONTROL_4__COLOR_CACHE_FETCH_NUM_CLS_LOG2_MASK                                                  0x00000007L
#define CB_HW_CONTROL_4__FMASK_CACHE_FETCH_NUM_CLS_LOG2_MASK                                                  0x00000018L
#define CB_HW_CONTROL_4__DISABLE_USE_OF_QUAD_SCOREBOARD_MASK                                                  0x00000020L
#define CB_HW_CONTROL_4__DISABLE_CMASK_CLOCK_GATING_MASK                                                      0x00000040L
#define CB_HW_CONTROL_4__DISABLE_FMASK_CLOCK_GATING_MASK                                                      0x00000080L
#define CB_HW_CONTROL_4__DISABLE_COLOR_CLOCK_GATING_MASK                                                      0x00000100L
#define CB_HW_CONTROL_4__DISABLE_QSB_AA_MODE_MASK                                                             0x00000200L
#define CB_HW_CONTROL_4__DISABLE_QSB_WAIT_FOR_SCORE_MASK                                                      0x00000400L
#define CB_HW_CONTROL_4__DISABLE_QSB_FRAG_GT0_MASK                                                            0x00000800L
#define CB_HW_CONTROL_4__REVERSE_KEYXFR_RD_PRIORITY_MASK                                                      0x00001000L
#define CB_HW_CONTROL_4__DISABLE_KEYXFR_HIT_RETURNS_MASK                                                      0x00002000L
#define CB_HW_CONTROL_4__DISABLE_BC_COLOR_CACHE_PREFETCH_MASK                                                 0x00004000L
#define CB_HW_CONTROL_4__DISABLE_MA_WAIT_FOR_LAST_MASK                                                        0x00008000L
#define CB_HW_CONTROL_4__DISABLE_QSB_SPECULATIVE_MASK                                                         0x00010000L
#define CB_HW_CONTROL_4__QSB_WAIT_FOR_SCORE_MASK                                                              0x003E0000L
#define CB_HW_CONTROL_4__DISABLE_TILE_FGCG_MASK                                                               0x00400000L
#define CB_HW_CONTROL_4__DISABLE_LQUAD_FGCG_MASK                                                              0x00800000L
#define CB_HW_CONTROL_4__FC_QSB_FIFO_DEPTH_MASK                                                               0xFF000000L
//CB_HW_CONTROL_3
#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL__SHIFT                                        0x0
#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED__SHIFT                                              0x1
#define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT__SHIFT                                                  0x2
#define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP__SHIFT                                                 0x3
#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR__SHIFT                                            0x4
#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM__SHIFT                                            0x5
#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING__SHIFT                                                 0x7
#define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS__SHIFT                                                 0x9
#define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS__SHIFT                                                     0xa
#define CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION__SHIFT                                             0xb
#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967__SHIFT                                              0xc
#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_520657__SHIFT                                              0xd
#define CB_HW_CONTROL_3__DISABLE_OC_FIXES_OF_BUG_522542__SHIFT                                                0xe
#define CB_HW_CONTROL_3__FORCE_RMI_LAST_HIGH__SHIFT                                                           0xf
#define CB_HW_CONTROL_3__FORCE_RMI_CLKEN_HIGH__SHIFT                                                          0x10
#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CC__SHIFT                                                       0x11
#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_FC__SHIFT                                                       0x12
#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_DC__SHIFT                                                       0x13
#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CM__SHIFT                                                       0x14
#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CC__SHIFT                                                    0x15
#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_FC__SHIFT                                                    0x16
#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_DC__SHIFT                                                    0x17
#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CM__SHIFT                                                    0x18
#define CB_HW_CONTROL_3__DISABLE_NACK_COLOR_RD_WR_OPT__SHIFT                                                  0x19
#define CB_HW_CONTROL_3__DISABLE_BLENDER_CLOCK_GATING__SHIFT                                                  0x1a
#define CB_HW_CONTROL_3__DISABLE_FMASK_NOFETCH_OPT__SHIFT                                                     0x1e
#define CB_HW_CONTROL_3__DISABLE_FMASK_NOFETCH_OPT_BC__SHIFT                                                  0x1f
#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL_MASK                                          0x00000001L
#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED_MASK                                                0x00000002L
#define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT_MASK                                                    0x00000004L
#define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP_MASK                                                   0x00000008L
#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR_MASK                                              0x00000010L
#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM_MASK                                              0x00000020L
#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING_MASK                                                   0x00000080L
#define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS_MASK                                                   0x00000200L
#define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS_MASK                                                       0x00000400L
#define CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION_MASK                                               0x00000800L
#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967_MASK                                                0x00001000L
#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_520657_MASK                                                0x00002000L
#define CB_HW_CONTROL_3__DISABLE_OC_FIXES_OF_BUG_522542_MASK                                                  0x00004000L
#define CB_HW_CONTROL_3__FORCE_RMI_LAST_HIGH_MASK                                                             0x00008000L
#define CB_HW_CONTROL_3__FORCE_RMI_CLKEN_HIGH_MASK                                                            0x00010000L
#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CC_MASK                                                         0x00020000L
#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_FC_MASK                                                         0x00040000L
#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_DC_MASK                                                         0x00080000L
#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CM_MASK                                                         0x00100000L
#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CC_MASK                                                      0x00200000L
#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_FC_MASK                                                      0x00400000L
#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_DC_MASK                                                      0x00800000L
#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CM_MASK                                                      0x01000000L
#define CB_HW_CONTROL_3__DISABLE_NACK_COLOR_RD_WR_OPT_MASK                                                    0x02000000L
#define CB_HW_CONTROL_3__DISABLE_BLENDER_CLOCK_GATING_MASK                                                    0x04000000L
#define CB_HW_CONTROL_3__DISABLE_FMASK_NOFETCH_OPT_MASK                                                       0x40000000L
#define CB_HW_CONTROL_3__DISABLE_FMASK_NOFETCH_OPT_BC_MASK                                                    0x80000000L
//CB_HW_CONTROL
#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE__SHIFT                                                      0x0
#define CB_HW_CONTROL__DISABLE_FILLRATE_OPT_FIX_WITH_CFC__SHIFT                                               0x3
#define CB_HW_CONTROL__DISABLE_POST_DCC_WITH_CFC_FIX__SHIFT                                                   0x4
#define CB_HW_CONTROL__RMI_CREDITS__SHIFT                                                                     0x6
#define CB_HW_CONTROL__CHICKEN_BITS__SHIFT                                                                    0xc
#define CB_HW_CONTROL__DISABLE_FMASK_MULTI_MGCG_DOMAINS__SHIFT                                                0xf
#define CB_HW_CONTROL__DISABLE_CMASK_CACHE_BYTEMASKING__SHIFT                                                 0x10
#define CB_HW_CONTROL__DISABLE_DCC_CACHE_BYTEMASKING__SHIFT                                                   0x11
#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING__SHIFT                                                0x12
#define CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT                                                                 0x13
#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE__SHIFT                                                             0x14
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT                                                0x15
#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK__SHIFT                                                         0x16
#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG__SHIFT                                             0x17
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT                                                   0x18
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT                                                        0x19
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT                                                 0x1a
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT                                0x1b
#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT__SHIFT                                   0x1c
#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT__SHIFT                                0x1d
#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT__SHIFT                                              0x1e
#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE__SHIFT                                    0x1f
#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE_MASK                                                        0x00000001L
#define CB_HW_CONTROL__DISABLE_FILLRATE_OPT_FIX_WITH_CFC_MASK                                                 0x00000008L
#define CB_HW_CONTROL__DISABLE_POST_DCC_WITH_CFC_FIX_MASK                                                     0x00000010L
#define CB_HW_CONTROL__RMI_CREDITS_MASK                                                                       0x00000FC0L
#define CB_HW_CONTROL__CHICKEN_BITS_MASK                                                                      0x00007000L
#define CB_HW_CONTROL__DISABLE_FMASK_MULTI_MGCG_DOMAINS_MASK                                                  0x00008000L
#define CB_HW_CONTROL__DISABLE_CMASK_CACHE_BYTEMASKING_MASK                                                   0x00010000L
#define CB_HW_CONTROL__DISABLE_DCC_CACHE_BYTEMASKING_MASK                                                     0x00020000L
#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING_MASK                                                  0x00040000L
#define CB_HW_CONTROL__FORCE_NEEDS_DST_MASK                                                                   0x00080000L
#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE_MASK                                                               0x00100000L
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK                                                  0x00200000L
#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK_MASK                                                           0x00400000L
#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG_MASK                                               0x00800000L
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK                                                     0x01000000L
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK                                                          0x02000000L
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK                                                   0x04000000L
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK                                  0x08000000L
#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT_MASK                                     0x10000000L
#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT_MASK                                  0x20000000L
#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT_MASK                                                0x40000000L
#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE_MASK                                      0x80000000L
//CB_HW_CONTROL_1
#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS__SHIFT                                                             0x0
#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS__SHIFT                                                             0x5
#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT                                                             0xc
#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH__SHIFT                                                            0x12
#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS_MASK                                                               0x0000001FL
#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS_MASK                                                               0x00000FE0L
#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK                                                               0x0003F000L
#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH_MASK                                                              0x07FC0000L
//CB_HW_CONTROL_2
#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH__SHIFT                                                        0x0
#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH__SHIFT                                                      0x8
#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH__SHIFT                                                      0xf
#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8__SHIFT                                                   0x18
#define CB_HW_CONTROL_2__CHICKEN_BITS__SHIFT                                                                  0x1e
#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH_MASK                                                          0x000000FFL
#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH_MASK                                                        0x00007F00L
#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH_MASK                                                        0x007F8000L
#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8_MASK                                                     0x3F000000L
#define CB_HW_CONTROL_2__CHICKEN_BITS_MASK                                                                    0xC0000000L
//CB_DCC_CONFIG
#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH__SHIFT                                                        0x0
#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE__SHIFT                                                      0x5
#define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE__SHIFT                                               0x6
#define CB_DCC_CONFIG__DISABLE_CONSTANT_ENCODE__SHIFT                                                         0x7
#define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH__SHIFT                                                       0x8
#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH__SHIFT                                                     0x10
#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS__SHIFT                                                              0x19
#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH_MASK                                                          0x0000001FL
#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE_MASK                                                        0x00000020L
#define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE_MASK                                                 0x00000040L
#define CB_DCC_CONFIG__DISABLE_CONSTANT_ENCODE_MASK                                                           0x00000080L
#define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH_MASK                                                         0x0000FF00L
#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH_MASK                                                       0x01FF0000L
#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS_MASK                                                                0xFE000000L
//CB_HW_MEM_ARBITER_RD
#define CB_HW_MEM_ARBITER_RD__MODE__SHIFT                                                                     0x0
#define CB_HW_MEM_ARBITER_RD__IGNORE_URGENT_AGE__SHIFT                                                        0x2
#define CB_HW_MEM_ARBITER_RD__BREAK_GROUP_AGE__SHIFT                                                          0x6
#define CB_HW_MEM_ARBITER_RD__WEIGHT_CC__SHIFT                                                                0xa
#define CB_HW_MEM_ARBITER_RD__WEIGHT_FC__SHIFT                                                                0xc
#define CB_HW_MEM_ARBITER_RD__WEIGHT_CM__SHIFT                                                                0xe
#define CB_HW_MEM_ARBITER_RD__WEIGHT_DC__SHIFT                                                                0x10
#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_REQS__SHIFT                                                        0x12
#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_NOREQS__SHIFT                                                      0x14
#define CB_HW_MEM_ARBITER_RD__WEIGHT_IGNORE_NUM_TIDS__SHIFT                                                   0x16
#define CB_HW_MEM_ARBITER_RD__SCALE_AGE__SHIFT                                                                0x17
#define CB_HW_MEM_ARBITER_RD__SCALE_WEIGHT__SHIFT                                                             0x1a
#define CB_HW_MEM_ARBITER_RD__SEND_LASTS_WITHIN_GROUPS__SHIFT                                                 0x1d
#define CB_HW_MEM_ARBITER_RD__MODE_MASK                                                                       0x00000003L
#define CB_HW_MEM_ARBITER_RD__IGNORE_URGENT_AGE_MASK                                                          0x0000003CL
#define CB_HW_MEM_ARBITER_RD__BREAK_GROUP_AGE_MASK                                                            0x000003C0L
#define CB_HW_MEM_ARBITER_RD__WEIGHT_CC_MASK                                                                  0x00000C00L
#define CB_HW_MEM_ARBITER_RD__WEIGHT_FC_MASK                                                                  0x00003000L
#define CB_HW_MEM_ARBITER_RD__WEIGHT_CM_MASK                                                                  0x0000C000L
#define CB_HW_MEM_ARBITER_RD__WEIGHT_DC_MASK                                                                  0x00030000L
#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_REQS_MASK                                                          0x000C0000L
#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_NOREQS_MASK                                                        0x00300000L
#define CB_HW_MEM_ARBITER_RD__WEIGHT_IGNORE_NUM_TIDS_MASK                                                     0x00400000L
#define CB_HW_MEM_ARBITER_RD__SCALE_AGE_MASK                                                                  0x03800000L
#define CB_HW_MEM_ARBITER_RD__SCALE_WEIGHT_MASK                                                               0x1C000000L
#define CB_HW_MEM_ARBITER_RD__SEND_LASTS_WITHIN_GROUPS_MASK                                                   0x20000000L
//CB_HW_MEM_ARBITER_WR
#define CB_HW_MEM_ARBITER_WR__MODE__SHIFT                                                                     0x0
#define CB_HW_MEM_ARBITER_WR__IGNORE_URGENT_AGE__SHIFT                                                        0x2
#define CB_HW_MEM_ARBITER_WR__BREAK_GROUP_AGE__SHIFT                                                          0x6
#define CB_HW_MEM_ARBITER_WR__WEIGHT_CC__SHIFT                                                                0xa
#define CB_HW_MEM_ARBITER_WR__WEIGHT_FC__SHIFT                                                                0xc
#define CB_HW_MEM_ARBITER_WR__WEIGHT_CM__SHIFT                                                                0xe
#define CB_HW_MEM_ARBITER_WR__WEIGHT_DC__SHIFT                                                                0x10
#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_REQS__SHIFT                                                        0x12
#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_NOREQS__SHIFT                                                      0x14
#define CB_HW_MEM_ARBITER_WR__WEIGHT_IGNORE_BYTE_MASK__SHIFT                                                  0x16
#define CB_HW_MEM_ARBITER_WR__SCALE_AGE__SHIFT                                                                0x17
#define CB_HW_MEM_ARBITER_WR__SCALE_WEIGHT__SHIFT                                                             0x1a
#define CB_HW_MEM_ARBITER_WR__SEND_LASTS_WITHIN_GROUPS__SHIFT                                                 0x1d
#define CB_HW_MEM_ARBITER_WR__MODE_MASK                                                                       0x00000003L
#define CB_HW_MEM_ARBITER_WR__IGNORE_URGENT_AGE_MASK                                                          0x0000003CL
#define CB_HW_MEM_ARBITER_WR__BREAK_GROUP_AGE_MASK                                                            0x000003C0L
#define CB_HW_MEM_ARBITER_WR__WEIGHT_CC_MASK                                                                  0x00000C00L
#define CB_HW_MEM_ARBITER_WR__WEIGHT_FC_MASK                                                                  0x00003000L
#define CB_HW_MEM_ARBITER_WR__WEIGHT_CM_MASK                                                                  0x0000C000L
#define CB_HW_MEM_ARBITER_WR__WEIGHT_DC_MASK                                                                  0x00030000L
#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_REQS_MASK                                                          0x000C0000L
#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_NOREQS_MASK                                                        0x00300000L
#define CB_HW_MEM_ARBITER_WR__WEIGHT_IGNORE_BYTE_MASK_MASK                                                    0x00400000L
#define CB_HW_MEM_ARBITER_WR__SCALE_AGE_MASK                                                                  0x03800000L
#define CB_HW_MEM_ARBITER_WR__SCALE_WEIGHT_MASK                                                               0x1C000000L
#define CB_HW_MEM_ARBITER_WR__SEND_LASTS_WITHIN_GROUPS_MASK                                                   0x20000000L
//CB_RMI_BC_GL2_CACHE_CONTROL
#define CB_RMI_BC_GL2_CACHE_CONTROL__CMASK_WR_POLICY__SHIFT                                                   0x0
#define CB_RMI_BC_GL2_CACHE_CONTROL__FMASK_WR_POLICY__SHIFT                                                   0x2
#define CB_RMI_BC_GL2_CACHE_CONTROL__DCC_WR_POLICY__SHIFT                                                     0x4
#define CB_RMI_BC_GL2_CACHE_CONTROL__COLOR_WR_POLICY__SHIFT                                                   0x6
#define CB_RMI_BC_GL2_CACHE_CONTROL__CMASK_RD_POLICY__SHIFT                                                   0x10
#define CB_RMI_BC_GL2_CACHE_CONTROL__FMASK_RD_POLICY__SHIFT                                                   0x12
#define CB_RMI_BC_GL2_CACHE_CONTROL__DCC_RD_POLICY__SHIFT                                                     0x14
#define CB_RMI_BC_GL2_CACHE_CONTROL__COLOR_RD_POLICY__SHIFT                                                   0x16
#define CB_RMI_BC_GL2_CACHE_CONTROL__VOLAT__SHIFT                                                             0x1f
#define CB_RMI_BC_GL2_CACHE_CONTROL__CMASK_WR_POLICY_MASK                                                     0x00000003L
#define CB_RMI_BC_GL2_CACHE_CONTROL__FMASK_WR_POLICY_MASK                                                     0x0000000CL
#define CB_RMI_BC_GL2_CACHE_CONTROL__DCC_WR_POLICY_MASK                                                       0x00000030L
#define CB_RMI_BC_GL2_CACHE_CONTROL__COLOR_WR_POLICY_MASK                                                     0x000000C0L
#define CB_RMI_BC_GL2_CACHE_CONTROL__CMASK_RD_POLICY_MASK                                                     0x00030000L
#define CB_RMI_BC_GL2_CACHE_CONTROL__FMASK_RD_POLICY_MASK                                                     0x000C0000L
#define CB_RMI_BC_GL2_CACHE_CONTROL__DCC_RD_POLICY_MASK                                                       0x00300000L
#define CB_RMI_BC_GL2_CACHE_CONTROL__COLOR_RD_POLICY_MASK                                                     0x00C00000L
#define CB_RMI_BC_GL2_CACHE_CONTROL__VOLAT_MASK                                                               0x80000000L
//CB_STUTTER_CONTROL_CMASK_RDLAT
#define CB_STUTTER_CONTROL_CMASK_RDLAT__THRESHOLD__SHIFT                                                      0x0
#define CB_STUTTER_CONTROL_CMASK_RDLAT__TIMEOUT__SHIFT                                                        0x8
#define CB_STUTTER_CONTROL_CMASK_RDLAT__THRESHOLD_MASK                                                        0x000000FFL
#define CB_STUTTER_CONTROL_CMASK_RDLAT__TIMEOUT_MASK                                                          0x0000FF00L
//CB_STUTTER_CONTROL_FMASK_RDLAT
#define CB_STUTTER_CONTROL_FMASK_RDLAT__THRESHOLD__SHIFT                                                      0x0
#define CB_STUTTER_CONTROL_FMASK_RDLAT__TIMEOUT__SHIFT                                                        0x8
#define CB_STUTTER_CONTROL_FMASK_RDLAT__THRESHOLD_MASK                                                        0x000000FFL
#define CB_STUTTER_CONTROL_FMASK_RDLAT__TIMEOUT_MASK                                                          0x0000FF00L
//CB_STUTTER_CONTROL_COLOR_RDLAT
#define CB_STUTTER_CONTROL_COLOR_RDLAT__THRESHOLD__SHIFT                                                      0x0
#define CB_STUTTER_CONTROL_COLOR_RDLAT__TIMEOUT__SHIFT                                                        0x8
#define CB_STUTTER_CONTROL_COLOR_RDLAT__THRESHOLD_MASK                                                        0x000000FFL
#define CB_STUTTER_CONTROL_COLOR_RDLAT__TIMEOUT_MASK                                                          0x0000FF00L
//CB_CACHE_EVICT_POINTS
#define CB_CACHE_EVICT_POINTS__CM_CACHE_EVICT_POINT__SHIFT                                                    0x0
#define CB_CACHE_EVICT_POINTS__FC_CACHE_EVICT_POINT__SHIFT                                                    0x8
#define CB_CACHE_EVICT_POINTS__DCC_CACHE_EVICT_POINT__SHIFT                                                   0x10
#define CB_CACHE_EVICT_POINTS__CC_CACHE_EVICT_POINT__SHIFT                                                    0x18
#define CB_CACHE_EVICT_POINTS__CM_CACHE_EVICT_POINT_MASK                                                      0x000000FFL
#define CB_CACHE_EVICT_POINTS__FC_CACHE_EVICT_POINT_MASK                                                      0x0000FF00L
#define CB_CACHE_EVICT_POINTS__DCC_CACHE_EVICT_POINT_MASK                                                     0x00FF0000L
#define CB_CACHE_EVICT_POINTS__CC_CACHE_EVICT_POINT_MASK                                                      0xFF000000L
//GC_USER_RB_REDUNDANCY
#define GC_USER_RB_REDUNDANCY__FAILED_RB0__SHIFT                                                              0x8
#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT                                                          0xc
#define GC_USER_RB_REDUNDANCY__FAILED_RB1__SHIFT                                                              0x10
#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT                                                          0x14
#define GC_USER_RB_REDUNDANCY__FAILED_RB0_MASK                                                                0x00000F00L
#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0_MASK                                                            0x00001000L
#define GC_USER_RB_REDUNDANCY__FAILED_RB1_MASK                                                                0x000F0000L
#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1_MASK                                                            0x00100000L
//GC_USER_RB_BACKEND_DISABLE
#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT                                                    0x10
#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK                                                      0x00FF0000L


// addressBlock: gc_gceadec2
//GCEA_MISC
#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT                                                         0x0
#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT                                                         0x1
#define GCEA_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT                                                          0x2
#define GCEA_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT                                                          0x3
#define GCEA_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT                                                           0x4
#define GCEA_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT                                                           0x5
#define GCEA_MISC__EARLYWRRET_ENABLE_VC0__SHIFT                                                               0x6
#define GCEA_MISC__EARLYWRRET_ENABLE_VC1__SHIFT                                                               0x7
#define GCEA_MISC__EARLYWRRET_ENABLE_VC2__SHIFT                                                               0x8
#define GCEA_MISC__EARLYWRRET_ENABLE_VC3__SHIFT                                                               0x9
#define GCEA_MISC__EARLYWRRET_ENABLE_VC4__SHIFT                                                               0xa
#define GCEA_MISC__EARLYWRRET_ENABLE_VC5__SHIFT                                                               0xb
#define GCEA_MISC__EARLYWRRET_ENABLE_VC6__SHIFT                                                               0xc
#define GCEA_MISC__EARLYWRRET_ENABLE_VC7__SHIFT                                                               0xd
#define GCEA_MISC__EARLY_SDP_ORIGDATA__SHIFT                                                                  0xe
#define GCEA_MISC__LINKMGR_DYNAMIC_MODE__SHIFT                                                                0xf
#define GCEA_MISC__LINKMGR_HALT_THRESHOLD__SHIFT                                                              0x11
#define GCEA_MISC__LINKMGR_RECONNECT_DELAY__SHIFT                                                             0x13
#define GCEA_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT                                                              0x15
#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT                                                      0x1a
#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT                                                       0x1b
#define GCEA_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT                                                          0x1c
#define GCEA_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT                                                           0x1d
#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT                                                        0x1e
#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT                                                         0x1f
#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK                                                           0x00000001L
#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK                                                           0x00000002L
#define GCEA_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK                                                            0x00000004L
#define GCEA_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK                                                            0x00000008L
#define GCEA_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK                                                             0x00000010L
#define GCEA_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK                                                             0x00000020L
#define GCEA_MISC__EARLYWRRET_ENABLE_VC0_MASK                                                                 0x00000040L
#define GCEA_MISC__EARLYWRRET_ENABLE_VC1_MASK                                                                 0x00000080L
#define GCEA_MISC__EARLYWRRET_ENABLE_VC2_MASK                                                                 0x00000100L
#define GCEA_MISC__EARLYWRRET_ENABLE_VC3_MASK                                                                 0x00000200L
#define GCEA_MISC__EARLYWRRET_ENABLE_VC4_MASK                                                                 0x00000400L
#define GCEA_MISC__EARLYWRRET_ENABLE_VC5_MASK                                                                 0x00000800L
#define GCEA_MISC__EARLYWRRET_ENABLE_VC6_MASK                                                                 0x00001000L
#define GCEA_MISC__EARLYWRRET_ENABLE_VC7_MASK                                                                 0x00002000L
#define GCEA_MISC__EARLY_SDP_ORIGDATA_MASK                                                                    0x00004000L
#define GCEA_MISC__LINKMGR_DYNAMIC_MODE_MASK                                                                  0x00018000L
#define GCEA_MISC__LINKMGR_HALT_THRESHOLD_MASK                                                                0x00060000L
#define GCEA_MISC__LINKMGR_RECONNECT_DELAY_MASK                                                               0x00180000L
#define GCEA_MISC__LINKMGR_IDLE_THRESHOLD_MASK                                                                0x03E00000L
#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK                                                        0x04000000L
#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK                                                         0x08000000L
#define GCEA_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK                                                            0x10000000L
#define GCEA_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK                                                             0x20000000L
#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK                                                          0x40000000L
#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK                                                           0x80000000L
//GCEA_LATENCY_SAMPLING
#define GCEA_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT                                                           0x0
#define GCEA_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT                                                           0x1
#define GCEA_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT                                                            0x2
#define GCEA_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT                                                            0x3
#define GCEA_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT                                                             0x4
#define GCEA_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT                                                             0x5
#define GCEA_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT                                                           0x6
#define GCEA_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT                                                           0x7
#define GCEA_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT                                                          0x8
#define GCEA_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT                                                          0x9
#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT                                                     0xa
#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT                                                     0xb
#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT                                                   0xc
#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT                                                   0xd
#define GCEA_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT                                                             0xe
#define GCEA_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT                                                             0x16
#define GCEA_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK                                                             0x00000001L
#define GCEA_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK                                                             0x00000002L
#define GCEA_LATENCY_SAMPLING__SAMPLER0_GMI_MASK                                                              0x00000004L
#define GCEA_LATENCY_SAMPLING__SAMPLER1_GMI_MASK                                                              0x00000008L
#define GCEA_LATENCY_SAMPLING__SAMPLER0_IO_MASK                                                               0x00000010L
#define GCEA_LATENCY_SAMPLING__SAMPLER1_IO_MASK                                                               0x00000020L
#define GCEA_LATENCY_SAMPLING__SAMPLER0_READ_MASK                                                             0x00000040L
#define GCEA_LATENCY_SAMPLING__SAMPLER1_READ_MASK                                                             0x00000080L
#define GCEA_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK                                                            0x00000100L
#define GCEA_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK                                                            0x00000200L
#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK                                                       0x00000400L
#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK                                                       0x00000800L
#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK                                                     0x00001000L
#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK                                                     0x00002000L
#define GCEA_LATENCY_SAMPLING__SAMPLER0_VC_MASK                                                               0x003FC000L
#define GCEA_LATENCY_SAMPLING__SAMPLER1_VC_MASK                                                               0x3FC00000L
//GCEA_DSM_CNTL
#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x0
#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x2
#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x3
#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x5
#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x6
#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x8
#define GCEA_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT                                                  0x9
#define GCEA_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT                                                 0xb
#define GCEA_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT                                                  0xc
#define GCEA_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT                                                 0xe
#define GCEA_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                 0xf
#define GCEA_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                                0x11
#define GCEA_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                 0x12
#define GCEA_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                                0x14
#define GCEA_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x15
#define GCEA_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x17
#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x00000003L
#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00000004L
#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x00000018L
#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00000020L
#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                 0x000000C0L
#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00000100L
#define GCEA_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK                                                    0x00000600L
#define GCEA_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK                                                   0x00000800L
#define GCEA_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK                                                    0x00003000L
#define GCEA_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK                                                   0x00004000L
#define GCEA_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                   0x00018000L
#define GCEA_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                  0x00020000L
#define GCEA_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                   0x000C0000L
#define GCEA_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                  0x00100000L
#define GCEA_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                  0x00600000L
#define GCEA_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00800000L
//GCEA_DSM_CNTLA
#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                              0x0
#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x2
#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                              0x3
#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x5
#define GCEA_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                 0x6
#define GCEA_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                                0x8
#define GCEA_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                 0x9
#define GCEA_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                                0xb
#define GCEA_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                                0xc
#define GCEA_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0xe
#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                               0xf
#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x11
#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x12
#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x14
#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                                0x00000003L
#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00000004L
#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                                0x00000018L
#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00000020L
#define GCEA_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                   0x000000C0L
#define GCEA_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                  0x00000100L
#define GCEA_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                   0x00000600L
#define GCEA_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                  0x00000800L
#define GCEA_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                  0x00003000L
#define GCEA_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00004000L
#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00018000L
#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00020000L
#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                                 0x000C0000L
#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00100000L
//GCEA_DSM_CNTLB
//GCEA_DSM_CNTL2
#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x0
#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x2
#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x3
#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x5
#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x6
#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                             0x8
#define GCEA_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT                                                0x9
#define GCEA_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT                                                0xb
#define GCEA_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT                                                0xc
#define GCEA_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT                                                0xe
#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                               0xf
#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                               0x11
#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                               0x12
#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                               0x14
#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x15
#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                              0x17
#define GCEA_DSM_CNTL2__INJECT_DELAY__SHIFT                                                                   0x1a
#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x00000003L
#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00000004L
#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x00000018L
#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00000020L
#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                               0x000000C0L
#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                               0x00000100L
#define GCEA_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK                                                  0x00000600L
#define GCEA_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK                                                  0x00000800L
#define GCEA_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK                                                  0x00003000L
#define GCEA_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK                                                  0x00004000L
#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                 0x00018000L
#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK                                                 0x00020000L
#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                 0x000C0000L
#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                                 0x00100000L
#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                                0x00600000L
#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                                0x00800000L
#define GCEA_DSM_CNTL2__INJECT_DELAY_MASK                                                                     0xFC000000L
//GCEA_DSM_CNTL2A
#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                            0x0
#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                            0x2
#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                            0x3
#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                            0x5
#define GCEA_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                               0x6
#define GCEA_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                               0x8
#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                               0x9
#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                               0xb
#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                              0xc
#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                              0xe
#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                             0xf
#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                             0x11
#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x12
#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                             0x14
#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                              0x00000003L
#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK                                              0x00000004L
#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                              0x00000018L
#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK                                              0x00000020L
#define GCEA_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                 0x000000C0L
#define GCEA_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK                                                 0x00000100L
#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                 0x00000600L
#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                                 0x00000800L
#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                                0x00003000L
#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                                0x00004000L
#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                               0x00018000L
#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK                                               0x00020000L
#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                               0x000C0000L
#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK                                               0x00100000L
//GCEA_DSM_CNTL2B
//GCEA_GL2C_XBR_CREDITS
#define GCEA_GL2C_XBR_CREDITS__DRAM_RD_LIMIT__SHIFT                                                           0x0
#define GCEA_GL2C_XBR_CREDITS__DRAM_RD_RESERVE__SHIFT                                                         0x6
#define GCEA_GL2C_XBR_CREDITS__IO_RD_LIMIT__SHIFT                                                             0x8
#define GCEA_GL2C_XBR_CREDITS__IO_RD_RESERVE__SHIFT                                                           0xe
#define GCEA_GL2C_XBR_CREDITS__DRAM_WR_LIMIT__SHIFT                                                           0x10
#define GCEA_GL2C_XBR_CREDITS__DRAM_WR_RESERVE__SHIFT                                                         0x16
#define GCEA_GL2C_XBR_CREDITS__IO_WR_LIMIT__SHIFT                                                             0x18
#define GCEA_GL2C_XBR_CREDITS__IO_WR_RESERVE__SHIFT                                                           0x1e
#define GCEA_GL2C_XBR_CREDITS__DRAM_RD_LIMIT_MASK                                                             0x0000003FL
#define GCEA_GL2C_XBR_CREDITS__DRAM_RD_RESERVE_MASK                                                           0x000000C0L
#define GCEA_GL2C_XBR_CREDITS__IO_RD_LIMIT_MASK                                                               0x00003F00L
#define GCEA_GL2C_XBR_CREDITS__IO_RD_RESERVE_MASK                                                             0x0000C000L
#define GCEA_GL2C_XBR_CREDITS__DRAM_WR_LIMIT_MASK                                                             0x003F0000L
#define GCEA_GL2C_XBR_CREDITS__DRAM_WR_RESERVE_MASK                                                           0x00C00000L
#define GCEA_GL2C_XBR_CREDITS__IO_WR_LIMIT_MASK                                                               0x3F000000L
#define GCEA_GL2C_XBR_CREDITS__IO_WR_RESERVE_MASK                                                             0xC0000000L
//GCEA_GL2C_XBR_MAXBURST
#define GCEA_GL2C_XBR_MAXBURST__DRAM_RD__SHIFT                                                                0x0
#define GCEA_GL2C_XBR_MAXBURST__IO_RD__SHIFT                                                                  0x4
#define GCEA_GL2C_XBR_MAXBURST__DRAM_WR__SHIFT                                                                0x8
#define GCEA_GL2C_XBR_MAXBURST__IO_WR__SHIFT                                                                  0xc
#define GCEA_GL2C_XBR_MAXBURST__DRAM_RD_COMB_FLUSH_TIMER__SHIFT                                               0x10
#define GCEA_GL2C_XBR_MAXBURST__DRAM_RD_COMB_SAME64B_ONLY__SHIFT                                              0x13
#define GCEA_GL2C_XBR_MAXBURST__DRAM_WR_COMB_FLUSH_TIMER__SHIFT                                               0x14
#define GCEA_GL2C_XBR_MAXBURST__DRAM_WR_COMB_SAME64B_ONLY__SHIFT                                              0x17
#define GCEA_GL2C_XBR_MAXBURST__DRAM_RD_MASK                                                                  0x0000000FL
#define GCEA_GL2C_XBR_MAXBURST__IO_RD_MASK                                                                    0x000000F0L
#define GCEA_GL2C_XBR_MAXBURST__DRAM_WR_MASK                                                                  0x00000F00L
#define GCEA_GL2C_XBR_MAXBURST__IO_WR_MASK                                                                    0x0000F000L
#define GCEA_GL2C_XBR_MAXBURST__DRAM_RD_COMB_FLUSH_TIMER_MASK                                                 0x00070000L
#define GCEA_GL2C_XBR_MAXBURST__DRAM_RD_COMB_SAME64B_ONLY_MASK                                                0x00080000L
#define GCEA_GL2C_XBR_MAXBURST__DRAM_WR_COMB_FLUSH_TIMER_MASK                                                 0x00700000L
#define GCEA_GL2C_XBR_MAXBURST__DRAM_WR_COMB_SAME64B_ONLY_MASK                                                0x00800000L
//GCEA_PROBE_CNTL
#define GCEA_PROBE_CNTL__REQ2RSP_DELAY__SHIFT                                                                 0x0
#define GCEA_PROBE_CNTL__PRB_FILTER_DISABLE__SHIFT                                                            0x5
#define GCEA_PROBE_CNTL__REQ2RSP_DELAY_MASK                                                                   0x0000001FL
#define GCEA_PROBE_CNTL__PRB_FILTER_DISABLE_MASK                                                              0x00000020L
//GCEA_PROBE_MAP
#define GCEA_PROBE_MAP__CHADDR0_TO_RIGHTGL2C__SHIFT                                                           0x0
#define GCEA_PROBE_MAP__CHADDR1_TO_RIGHTGL2C__SHIFT                                                           0x1
#define GCEA_PROBE_MAP__CHADDR2_TO_RIGHTGL2C__SHIFT                                                           0x2
#define GCEA_PROBE_MAP__CHADDR3_TO_RIGHTGL2C__SHIFT                                                           0x3
#define GCEA_PROBE_MAP__CHADDR4_TO_RIGHTGL2C__SHIFT                                                           0x4
#define GCEA_PROBE_MAP__CHADDR5_TO_RIGHTGL2C__SHIFT                                                           0x5
#define GCEA_PROBE_MAP__CHADDR6_TO_RIGHTGL2C__SHIFT                                                           0x6
#define GCEA_PROBE_MAP__CHADDR7_TO_RIGHTGL2C__SHIFT                                                           0x7
#define GCEA_PROBE_MAP__CHADDR8_TO_RIGHTGL2C__SHIFT                                                           0x8
#define GCEA_PROBE_MAP__CHADDR9_TO_RIGHTGL2C__SHIFT                                                           0x9
#define GCEA_PROBE_MAP__CHADDR10_TO_RIGHTGL2C__SHIFT                                                          0xa
#define GCEA_PROBE_MAP__CHADDR11_TO_RIGHTGL2C__SHIFT                                                          0xb
#define GCEA_PROBE_MAP__CHADDR12_TO_RIGHTGL2C__SHIFT                                                          0xc
#define GCEA_PROBE_MAP__CHADDR13_TO_RIGHTGL2C__SHIFT                                                          0xd
#define GCEA_PROBE_MAP__CHADDR14_TO_RIGHTGL2C__SHIFT                                                          0xe
#define GCEA_PROBE_MAP__CHADDR15_TO_RIGHTGL2C__SHIFT                                                          0xf
#define GCEA_PROBE_MAP__INTLV_SIZE__SHIFT                                                                     0x10
#define GCEA_PROBE_MAP__CHADDR0_TO_RIGHTGL2C_MASK                                                             0x00000001L
#define GCEA_PROBE_MAP__CHADDR1_TO_RIGHTGL2C_MASK                                                             0x00000002L
#define GCEA_PROBE_MAP__CHADDR2_TO_RIGHTGL2C_MASK                                                             0x00000004L
#define GCEA_PROBE_MAP__CHADDR3_TO_RIGHTGL2C_MASK                                                             0x00000008L
#define GCEA_PROBE_MAP__CHADDR4_TO_RIGHTGL2C_MASK                                                             0x00000010L
#define GCEA_PROBE_MAP__CHADDR5_TO_RIGHTGL2C_MASK                                                             0x00000020L
#define GCEA_PROBE_MAP__CHADDR6_TO_RIGHTGL2C_MASK                                                             0x00000040L
#define GCEA_PROBE_MAP__CHADDR7_TO_RIGHTGL2C_MASK                                                             0x00000080L
#define GCEA_PROBE_MAP__CHADDR8_TO_RIGHTGL2C_MASK                                                             0x00000100L
#define GCEA_PROBE_MAP__CHADDR9_TO_RIGHTGL2C_MASK                                                             0x00000200L
#define GCEA_PROBE_MAP__CHADDR10_TO_RIGHTGL2C_MASK                                                            0x00000400L
#define GCEA_PROBE_MAP__CHADDR11_TO_RIGHTGL2C_MASK                                                            0x00000800L
#define GCEA_PROBE_MAP__CHADDR12_TO_RIGHTGL2C_MASK                                                            0x00001000L
#define GCEA_PROBE_MAP__CHADDR13_TO_RIGHTGL2C_MASK                                                            0x00002000L
#define GCEA_PROBE_MAP__CHADDR14_TO_RIGHTGL2C_MASK                                                            0x00004000L
#define GCEA_PROBE_MAP__CHADDR15_TO_RIGHTGL2C_MASK                                                            0x00008000L
#define GCEA_PROBE_MAP__INTLV_SIZE_MASK                                                                       0x00030000L
//GCEA_ERR_STATUS
#define GCEA_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT                                                              0x0
#define GCEA_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT                                                              0x4
#define GCEA_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT                                                          0x8
#define GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT                                                    0xa
#define GCEA_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT                                                            0xb
#define GCEA_ERR_STATUS__BUSY_ON_ERROR__SHIFT                                                                 0xc
#define GCEA_ERR_STATUS__FUE_FLAG__SHIFT                                                                      0xd
#define GCEA_ERR_STATUS__SDP_RDRSP_STATUS_MASK                                                                0x0000000FL
#define GCEA_ERR_STATUS__SDP_WRRSP_STATUS_MASK                                                                0x000000F0L
#define GCEA_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK                                                            0x00000300L
#define GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK                                                      0x00000400L
#define GCEA_ERR_STATUS__CLEAR_ERROR_STATUS_MASK                                                              0x00000800L
#define GCEA_ERR_STATUS__BUSY_ON_ERROR_MASK                                                                   0x00001000L
#define GCEA_ERR_STATUS__FUE_FLAG_MASK                                                                        0x00002000L
//GCEA_MISC2
#define GCEA_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT                                                           0x0
#define GCEA_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT                                                            0x1
#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT                                                        0x2
#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT                                                         0x7
#define GCEA_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT                                                            0xc
#define GCEA_MISC2__BLOCK_REQUESTS__SHIFT                                                                     0xd
#define GCEA_MISC2__REQUESTS_BLOCKED__SHIFT                                                                   0xe
#define GCEA_MISC2__FGCLKEN_OVERRIDE__SHIFT                                                                   0xf
#define GCEA_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK                                                             0x00000001L
#define GCEA_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK                                                              0x00000002L
#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK                                                          0x0000007CL
#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK                                                           0x00000F80L
#define GCEA_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK                                                              0x00001000L
#define GCEA_MISC2__BLOCK_REQUESTS_MASK                                                                       0x00002000L
#define GCEA_MISC2__REQUESTS_BLOCKED_MASK                                                                     0x00004000L
#define GCEA_MISC2__FGCLKEN_OVERRIDE_MASK                                                                     0x00008000L


// addressBlock: gc_spipdec2
//SPI_PQEV_CTRL
#define SPI_PQEV_CTRL__SCAN_PERIOD__SHIFT                                                                     0x0
#define SPI_PQEV_CTRL__QUEUE_DURATION__SHIFT                                                                  0xa
#define SPI_PQEV_CTRL__COMPUTE_PIPE_EN__SHIFT                                                                 0x10
#define SPI_PQEV_CTRL__SCAN_PERIOD_MASK                                                                       0x000003FFL
#define SPI_PQEV_CTRL__QUEUE_DURATION_MASK                                                                    0x0000FC00L
#define SPI_PQEV_CTRL__COMPUTE_PIPE_EN_MASK                                                                   0x00FF0000L
//SPI_EXP_THROTTLE_CTRL
#define SPI_EXP_THROTTLE_CTRL__ENABLE__SHIFT                                                                  0x0
#define SPI_EXP_THROTTLE_CTRL__PERIOD__SHIFT                                                                  0x1
#define SPI_EXP_THROTTLE_CTRL__UPSTEP__SHIFT                                                                  0x5
#define SPI_EXP_THROTTLE_CTRL__DOWNSTEP__SHIFT                                                                0x9
#define SPI_EXP_THROTTLE_CTRL__LOW_STALL_MON_HIST_COUNT__SHIFT                                                0xd
#define SPI_EXP_THROTTLE_CTRL__HIGH_STALL_MON_HIST_COUNT__SHIFT                                               0x10
#define SPI_EXP_THROTTLE_CTRL__EXP_STALL_THRESHOLD__SHIFT                                                     0x13
#define SPI_EXP_THROTTLE_CTRL__SKEW_COUNT__SHIFT                                                              0x1a
#define SPI_EXP_THROTTLE_CTRL__THROTTLE_RESET__SHIFT                                                          0x1d
#define SPI_EXP_THROTTLE_CTRL__ENABLE_MASK                                                                    0x00000001L
#define SPI_EXP_THROTTLE_CTRL__PERIOD_MASK                                                                    0x0000001EL
#define SPI_EXP_THROTTLE_CTRL__UPSTEP_MASK                                                                    0x000001E0L
#define SPI_EXP_THROTTLE_CTRL__DOWNSTEP_MASK                                                                  0x00001E00L
#define SPI_EXP_THROTTLE_CTRL__LOW_STALL_MON_HIST_COUNT_MASK                                                  0x0000E000L
#define SPI_EXP_THROTTLE_CTRL__HIGH_STALL_MON_HIST_COUNT_MASK                                                 0x00070000L
#define SPI_EXP_THROTTLE_CTRL__EXP_STALL_THRESHOLD_MASK                                                       0x03F80000L
#define SPI_EXP_THROTTLE_CTRL__SKEW_COUNT_MASK                                                                0x1C000000L
#define SPI_EXP_THROTTLE_CTRL__THROTTLE_RESET_MASK                                                            0x20000000L


// addressBlock: gc_gceadec3
//GCEA_RRET_MEM_RESERVE
#define GCEA_RRET_MEM_RESERVE__VC0__SHIFT                                                                     0x0
#define GCEA_RRET_MEM_RESERVE__VC1__SHIFT                                                                     0x4
#define GCEA_RRET_MEM_RESERVE__VC2__SHIFT                                                                     0x8
#define GCEA_RRET_MEM_RESERVE__VC3__SHIFT                                                                     0xc
#define GCEA_RRET_MEM_RESERVE__VC4__SHIFT                                                                     0x10
#define GCEA_RRET_MEM_RESERVE__VC5__SHIFT                                                                     0x14
#define GCEA_RRET_MEM_RESERVE__VC6__SHIFT                                                                     0x18
#define GCEA_RRET_MEM_RESERVE__VC7__SHIFT                                                                     0x1c
#define GCEA_RRET_MEM_RESERVE__VC0_MASK                                                                       0x0000000FL
#define GCEA_RRET_MEM_RESERVE__VC1_MASK                                                                       0x000000F0L
#define GCEA_RRET_MEM_RESERVE__VC2_MASK                                                                       0x00000F00L
#define GCEA_RRET_MEM_RESERVE__VC3_MASK                                                                       0x0000F000L
#define GCEA_RRET_MEM_RESERVE__VC4_MASK                                                                       0x000F0000L
#define GCEA_RRET_MEM_RESERVE__VC5_MASK                                                                       0x00F00000L
#define GCEA_RRET_MEM_RESERVE__VC6_MASK                                                                       0x0F000000L
#define GCEA_RRET_MEM_RESERVE__VC7_MASK                                                                       0xF0000000L


// addressBlock: gc_rmi_rmidec
//RMI_GENERAL_CNTL
#define RMI_GENERAL_CNTL__BURST_DISABLE__SHIFT                                                                0x0
#define RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE__SHIFT                                                           0x1
#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG__SHIFT                                                              0x11
#define RMI_GENERAL_CNTL__RB0_HARVEST_EN__SHIFT                                                               0x13
#define RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE__SHIFT                                                     0x15
#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_UPDATE__SHIFT                                                       0x19
#define RMI_GENERAL_CNTL__SKID_FIFO_0_OVERFLOW_ERROR_MASK__SHIFT                                              0x1a
#define RMI_GENERAL_CNTL__SKID_FIFO_0_UNDERFLOW_ERROR_MASK__SHIFT                                             0x1b
#define RMI_GENERAL_CNTL__SKID_FIFO_1_OVERFLOW_ERROR_MASK__SHIFT                                              0x1c
#define RMI_GENERAL_CNTL__SKID_FIFO_1_UNDERFLOW_ERROR_MASK__SHIFT                                             0x1d
#define RMI_GENERAL_CNTL__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK__SHIFT                                       0x1e
#define RMI_GENERAL_CNTL__BURST_DISABLE_MASK                                                                  0x00000001L
#define RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE_MASK                                                             0x0001FFFEL
#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_MASK                                                                0x00060000L
#define RMI_GENERAL_CNTL__RB0_HARVEST_EN_MASK                                                                 0x00080000L
#define RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE_MASK                                                       0x01E00000L
#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_UPDATE_MASK                                                         0x02000000L
#define RMI_GENERAL_CNTL__SKID_FIFO_0_OVERFLOW_ERROR_MASK_MASK                                                0x04000000L
#define RMI_GENERAL_CNTL__SKID_FIFO_0_UNDERFLOW_ERROR_MASK_MASK                                               0x08000000L
#define RMI_GENERAL_CNTL__SKID_FIFO_1_OVERFLOW_ERROR_MASK_MASK                                                0x10000000L
#define RMI_GENERAL_CNTL__SKID_FIFO_1_UNDERFLOW_ERROR_MASK_MASK                                               0x20000000L
#define RMI_GENERAL_CNTL__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK_MASK                                         0x40000000L
//RMI_GENERAL_CNTL1
#define RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE__SHIFT                                                0x0
#define RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE__SHIFT                                                     0x4
#define RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE__SHIFT                                                     0x6
#define RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK__SHIFT                                            0x8
#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE__SHIFT                                                       0x9
#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE__SHIFT                                                             0xb
#define RMI_GENERAL_CNTL1__UTCL1_PROBE0_RR_ARB_BURST_HINT_EN__SHIFT                                           0xc
#define RMI_GENERAL_CNTL1__UTCL1_PROBE1_RR_ARB_BURST_HINT_EN__SHIFT                                           0xd
#define RMI_GENERAL_CNTL1__ARBITER_ADDRESS_CHANGE_ENABLE__SHIFT                                               0xe
#define RMI_GENERAL_CNTL1__LAST_OF_BURST_INSERTION_DISABLE__SHIFT                                             0xf
#define RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE_MASK                                                  0x0000000FL
#define RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE_MASK                                                       0x00000030L
#define RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE_MASK                                                       0x000000C0L
#define RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK_MASK                                              0x00000100L
#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE_MASK                                                         0x00000600L
#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_MASK                                                               0x00000800L
#define RMI_GENERAL_CNTL1__UTCL1_PROBE0_RR_ARB_BURST_HINT_EN_MASK                                             0x00001000L
#define RMI_GENERAL_CNTL1__UTCL1_PROBE1_RR_ARB_BURST_HINT_EN_MASK                                             0x00002000L
#define RMI_GENERAL_CNTL1__ARBITER_ADDRESS_CHANGE_ENABLE_MASK                                                 0x00004000L
#define RMI_GENERAL_CNTL1__LAST_OF_BURST_INSERTION_DISABLE_MASK                                               0x00008000L
//RMI_GENERAL_STATUS
#define RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED__SHIFT                                                0x0
#define RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR__SHIFT                                                 0x1
#define RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR__SHIFT                                                0x2
#define RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR__SHIFT                                                 0x3
#define RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR__SHIFT                                                0x4
#define RMI_GENERAL_STATUS__RMI_XBAR_BUSY__SHIFT                                                              0x5
#define RMI_GENERAL_STATUS__RMI_UTCL1_BUSY__SHIFT                                                             0x6
#define RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY__SHIFT                                                        0x7
#define RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY__SHIFT                                                        0x8
#define RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY__SHIFT                                                           0x9
#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY__SHIFT                                                       0xa
#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY__SHIFT                                                 0xb
#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY__SHIFT                                                 0xc
#define RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY__SHIFT                                                        0xd
#define RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY__SHIFT                                                           0xe
#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY__SHIFT                                                       0xf
#define RMI_GENERAL_STATUS__UTC_PROBE1_BUSY__SHIFT                                                            0x12
#define RMI_GENERAL_STATUS__UTC_PROBE0_BUSY__SHIFT                                                            0x13
#define RMI_GENERAL_STATUS__RMI_XNACK_BUSY__SHIFT                                                             0x14
#define RMI_GENERAL_STATUS__XNACK_FIFO_NUM_USED__SHIFT                                                        0x15
#define RMI_GENERAL_STATUS__XNACK_FIFO_EMPTY__SHIFT                                                           0x1d
#define RMI_GENERAL_STATUS__XNACK_FIFO_FULL__SHIFT                                                            0x1e
#define RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR__SHIFT                                          0x1f
#define RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED_MASK                                                  0x00000001L
#define RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR_MASK                                                   0x00000002L
#define RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR_MASK                                                  0x00000004L
#define RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR_MASK                                                   0x00000008L
#define RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR_MASK                                                  0x00000010L
#define RMI_GENERAL_STATUS__RMI_XBAR_BUSY_MASK                                                                0x00000020L
#define RMI_GENERAL_STATUS__RMI_UTCL1_BUSY_MASK                                                               0x00000040L
#define RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY_MASK                                                          0x00000080L
#define RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY_MASK                                                          0x00000100L
#define RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY_MASK                                                             0x00000200L
#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY_MASK                                                         0x00000400L
#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY_MASK                                                   0x00000800L
#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY_MASK                                                   0x00001000L
#define RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY_MASK                                                          0x00002000L
#define RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY_MASK                                                             0x00004000L
#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY_MASK                                                         0x00008000L
#define RMI_GENERAL_STATUS__UTC_PROBE1_BUSY_MASK                                                              0x00040000L
#define RMI_GENERAL_STATUS__UTC_PROBE0_BUSY_MASK                                                              0x00080000L
#define RMI_GENERAL_STATUS__RMI_XNACK_BUSY_MASK                                                               0x00100000L
#define RMI_GENERAL_STATUS__XNACK_FIFO_NUM_USED_MASK                                                          0x1FE00000L
#define RMI_GENERAL_STATUS__XNACK_FIFO_EMPTY_MASK                                                             0x20000000L
#define RMI_GENERAL_STATUS__XNACK_FIFO_FULL_MASK                                                              0x40000000L
#define RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK                                            0x80000000L
//RMI_SUBBLOCK_STATUS0
#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0__SHIFT                                     0x0
#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0__SHIFT                                         0x7
#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0__SHIFT                                        0x8
#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1__SHIFT                                     0x9
#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1__SHIFT                                         0x10
#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1__SHIFT                                        0x11
#define RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT__SHIFT                                                       0x12
#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0_MASK                                       0x0000007FL
#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0_MASK                                           0x00000080L
#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0_MASK                                          0x00000100L
#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1_MASK                                       0x0000FE00L
#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1_MASK                                           0x00010000L
#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1_MASK                                          0x00020000L
#define RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT_MASK                                                         0x0FFC0000L
//RMI_SUBBLOCK_STATUS1
#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE__SHIFT                                                   0x0
#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE__SHIFT                                                   0xa
#define RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT__SHIFT                                                       0x14
#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE_MASK                                                     0x000003FFL
#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE_MASK                                                     0x000FFC00L
#define RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT_MASK                                                         0x3FF00000L
//RMI_SUBBLOCK_STATUS2
#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED__SHIFT                                                      0x0
#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED__SHIFT                                                      0x9
#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED_MASK                                                        0x000001FFL
#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED_MASK                                                        0x0003FE00L
//RMI_SUBBLOCK_STATUS3
#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL__SHIFT                                             0x0
#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL__SHIFT                                             0xa
#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL_MASK                                               0x000003FFL
#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL_MASK                                               0x000FFC00L
//RMI_XBAR_CONFIG
#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE__SHIFT                                                      0x0
#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE__SHIFT                                             0x2
#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE__SHIFT                                                0x6
#define RMI_XBAR_CONFIG__ARBITER_DIS__SHIFT                                                                   0x7
#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ__SHIFT                                                                0x8
#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE__SHIFT                                                       0xc
#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB0__SHIFT                                                                0xd
#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE_MASK                                                        0x00000003L
#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE_MASK                                               0x0000003CL
#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE_MASK                                                  0x00000040L
#define RMI_XBAR_CONFIG__ARBITER_DIS_MASK                                                                     0x00000080L
#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_MASK                                                                  0x00000F00L
#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE_MASK                                                         0x00001000L
#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB0_MASK                                                                  0x00002000L
//RMI_PROBE_POP_LOGIC_CNTL
#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH__SHIFT                                             0x0
#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS__SHIFT                                                    0x7
#define RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2__SHIFT                                      0x8
#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH__SHIFT                                             0xa
#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS__SHIFT                                                    0x11
#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH_MASK                                               0x0000007FL
#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS_MASK                                                      0x00000080L
#define RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2_MASK                                        0x00000300L
#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH_MASK                                               0x0001FC00L
#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS_MASK                                                      0x00020000L
//RMI_UTC_XNACK_N_MISC_CNTL
#define RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC__SHIFT                                              0x0
#define RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE__SHIFT                                         0x8
#define RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE__SHIFT                                                     0xc
#define RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE__SHIFT                                       0xd
#define RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC_MASK                                                0x000000FFL
#define RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE_MASK                                           0x00000F00L
#define RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE_MASK                                                       0x00001000L
#define RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE_MASK                                         0x00002000L
//RMI_DEMUX_CNTL
#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL__SHIFT                                                               0x0
#define RMI_DEMUX_CNTL__DEMUX_ARB0_BREAK_LOB_ON_IDLEIN__SHIFT                                                 0x1
#define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE_OVERRIDE_EN__SHIFT                                                    0x2
#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_OVERRIDE__SHIFT                                                0x4
#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE__SHIFT                                             0x6
#define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE__SHIFT                                                                0xe
#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL__SHIFT                                                               0x10
#define RMI_DEMUX_CNTL__DEMUX_ARB1_BREAK_LOB_ON_IDLEIN__SHIFT                                                 0x11
#define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE_OVERRIDE_EN__SHIFT                                                    0x12
#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_OVERRIDE__SHIFT                                                0x14
#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE__SHIFT                                             0x16
#define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE__SHIFT                                                                0x1e
#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_MASK                                                                 0x00000001L
#define RMI_DEMUX_CNTL__DEMUX_ARB0_BREAK_LOB_ON_IDLEIN_MASK                                                   0x00000002L
#define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE_OVERRIDE_EN_MASK                                                      0x00000004L
#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_OVERRIDE_MASK                                                  0x00000030L
#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE_MASK                                               0x00003FC0L
#define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE_MASK                                                                  0x0000C000L
#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_MASK                                                                 0x00010000L
#define RMI_DEMUX_CNTL__DEMUX_ARB1_BREAK_LOB_ON_IDLEIN_MASK                                                   0x00020000L
#define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE_OVERRIDE_EN_MASK                                                      0x00040000L
#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_OVERRIDE_MASK                                                  0x00300000L
#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE_MASK                                               0x3FC00000L
#define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE_MASK                                                                  0xC0000000L
//RMI_UTCL1_CNTL1
#define RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT                                                              0x0
#define RMI_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT                                                                 0x1
#define RMI_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT                                                               0x2
#define RMI_UTCL1_CNTL1__RESP_MODE__SHIFT                                                                     0x3
#define RMI_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT                                                               0x5
#define RMI_UTCL1_CNTL1__CLIENTID__SHIFT                                                                      0x7
#define RMI_UTCL1_CNTL1__USERVM_DIS__SHIFT                                                                    0x10
#define RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT                                                             0x11
#define RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT                                                          0x12
#define RMI_UTCL1_CNTL1__REG_INV_VMID__SHIFT                                                                  0x13
#define RMI_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT                                                              0x17
#define RMI_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT                                                                0x18
#define RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT                                                    0x19
#define RMI_UTCL1_CNTL1__FORCE_MISS__SHIFT                                                                    0x1a
#define RMI_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT                                                                0x1b
#define RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT                                                        0x1c
#define RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT                                                        0x1e
#define RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK                                                                0x00000001L
#define RMI_UTCL1_CNTL1__GPUVM_64K_DEF_MASK                                                                   0x00000002L
#define RMI_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK                                                                 0x00000004L
#define RMI_UTCL1_CNTL1__RESP_MODE_MASK                                                                       0x00000018L
#define RMI_UTCL1_CNTL1__RESP_FAULT_MODE_MASK                                                                 0x00000060L
#define RMI_UTCL1_CNTL1__CLIENTID_MASK                                                                        0x0000FF80L
#define RMI_UTCL1_CNTL1__USERVM_DIS_MASK                                                                      0x00010000L
#define RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK                                                               0x00020000L
#define RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK                                                            0x00040000L
#define RMI_UTCL1_CNTL1__REG_INV_VMID_MASK                                                                    0x00780000L
#define RMI_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK                                                                0x00800000L
#define RMI_UTCL1_CNTL1__REG_INV_TOGGLE_MASK                                                                  0x01000000L
#define RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK                                                      0x02000000L
#define RMI_UTCL1_CNTL1__FORCE_MISS_MASK                                                                      0x04000000L
#define RMI_UTCL1_CNTL1__FORCE_IN_ORDER_MASK                                                                  0x08000000L
#define RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK                                                          0x30000000L
#define RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK                                                          0xC0000000L
//RMI_UTCL1_CNTL2
#define RMI_UTCL1_CNTL2__UTC_SPARE__SHIFT                                                                     0x0
#define RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT                                                                0x9
#define RMI_UTCL1_CNTL2__LINE_VALID__SHIFT                                                                    0xa
#define RMI_UTCL1_CNTL2__DIS_EDC__SHIFT                                                                       0xb
#define RMI_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT                                                                0xc
#define RMI_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT                                                                 0xd
#define RMI_UTCL1_CNTL2__FORCE_SNOOP__SHIFT                                                                   0xe
#define RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT                                                           0xf
#define RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE__SHIFT                                                          0x10
#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR__SHIFT                                                 0x12
#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR__SHIFT                                                        0x13
#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID__SHIFT                                                  0x14
#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID__SHIFT                                                         0x15
#define RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ__SHIFT                                                         0x19
#define RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K__SHIFT                                                    0x1a
#define RMI_UTCL1_CNTL2__PERM_MODE_OVRD__SHIFT                                                                0x1b
#define RMI_UTCL1_CNTL2__LINE_INVALIDATE_OPT__SHIFT                                                           0x1c
#define RMI_UTCL1_CNTL2__GPUVM_16K_DEFAULT__SHIFT                                                             0x1d
#define RMI_UTCL1_CNTL2__FGCG_DISABLE__SHIFT                                                                  0x1e
#define RMI_UTCL1_CNTL2__RESERVED__SHIFT                                                                      0x1f
#define RMI_UTCL1_CNTL2__UTC_SPARE_MASK                                                                       0x000000FFL
#define RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK                                                                  0x00000200L
#define RMI_UTCL1_CNTL2__LINE_VALID_MASK                                                                      0x00000400L
#define RMI_UTCL1_CNTL2__DIS_EDC_MASK                                                                         0x00000800L
#define RMI_UTCL1_CNTL2__GPUVM_INV_MODE_MASK                                                                  0x00001000L
#define RMI_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK                                                                   0x00002000L
#define RMI_UTCL1_CNTL2__FORCE_SNOOP_MASK                                                                     0x00004000L
#define RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK                                                             0x00008000L
#define RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE_MASK                                                            0x00030000L
#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR_MASK                                                   0x00040000L
#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR_MASK                                                          0x00080000L
#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID_MASK                                                    0x00100000L
#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID_MASK                                                           0x01E00000L
#define RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ_MASK                                                           0x02000000L
#define RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K_MASK                                                      0x04000000L
#define RMI_UTCL1_CNTL2__PERM_MODE_OVRD_MASK                                                                  0x08000000L
#define RMI_UTCL1_CNTL2__LINE_INVALIDATE_OPT_MASK                                                             0x10000000L
#define RMI_UTCL1_CNTL2__GPUVM_16K_DEFAULT_MASK                                                               0x20000000L
#define RMI_UTCL1_CNTL2__FGCG_DISABLE_MASK                                                                    0x40000000L
#define RMI_UTCL1_CNTL2__RESERVED_MASK                                                                        0x80000000L
//RMI_UTC_UNIT_CONFIG
//RMI_TCIW_FORMATTER0_CNTL
#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_OVERRIDE__SHIFT                                             0x0
#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_TIME_OUT_WINDOW__SHIFT                                          0x1
#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ__SHIFT                                       0x9
#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA__SHIFT                                         0x13
#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_UPDATE__SHIFT                                  0x1b
#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_REQ_SAFE_MODE__SHIFT                                                  0x1c
#define RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS__SHIFT                                                  0x1d
#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_AT_LAST_OF_BURST__SHIFT                                     0x1e
#define RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA__SHIFT                                                  0x1f
#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_OVERRIDE_MASK                                               0x00000001L
#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_TIME_OUT_WINDOW_MASK                                            0x000001FEL
#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ_MASK                                         0x0007FE00L
#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_MASK                                           0x07F80000L
#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_UPDATE_MASK                                    0x08000000L
#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_REQ_SAFE_MODE_MASK                                                    0x10000000L
#define RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS_MASK                                                    0x20000000L
#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_AT_LAST_OF_BURST_MASK                                       0x40000000L
#define RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA_MASK                                                    0x80000000L
//RMI_TCIW_FORMATTER1_CNTL
#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE__SHIFT                                             0x0
#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW__SHIFT                                          0x1
#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ__SHIFT                                       0x9
#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA__SHIFT                                         0x13
#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_UPDATE__SHIFT                                  0x1b
#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_REQ_SAFE_MODE__SHIFT                                                  0x1c
#define RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS__SHIFT                                                  0x1d
#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST__SHIFT                                     0x1e
#define RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA__SHIFT                                                  0x1f
#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE_MASK                                               0x00000001L
#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW_MASK                                            0x000001FEL
#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ_MASK                                         0x0007FE00L
#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_MASK                                           0x07F80000L
#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_UPDATE_MASK                                    0x08000000L
#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_REQ_SAFE_MODE_MASK                                                    0x10000000L
#define RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS_MASK                                                    0x20000000L
#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST_MASK                                       0x40000000L
#define RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA_MASK                                                    0x80000000L
//RMI_SCOREBOARD_CNTL
#define RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH__SHIFT                                                        0x0
#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0__SHIFT                                              0x1
#define RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH__SHIFT                                                        0x2
#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1__SHIFT                                              0x3
#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB1__SHIFT                                                      0x4
#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN__SHIFT                                         0x5
#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE__SHIFT                                      0x6
#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB0__SHIFT                                                      0x7
#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_EN__SHIFT                                                  0x8
#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE__SHIFT                                   0x9
#define RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH_MASK                                                          0x00000001L
#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0_MASK                                                0x00000002L
#define RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH_MASK                                                          0x00000004L
#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1_MASK                                                0x00000008L
#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB1_MASK                                                        0x00000010L
#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN_MASK                                           0x00000020L
#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE_MASK                                        0x00000040L
#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB0_MASK                                                        0x00000080L
#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_EN_MASK                                                    0x00000100L
#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE_MASK                                     0x001FFE00L
//RMI_SCOREBOARD_STATUS0
#define RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID__SHIFT                                                     0x0
#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG__SHIFT                                                    0x1
#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID__SHIFT                                                   0x2
#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE__SHIFT                                                   0x12
#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE__SHIFT                                                       0x13
#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE__SHIFT                                                 0x14
#define RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE__SHIFT                                                    0x15
#define RMI_SCOREBOARD_STATUS0__COUNTER_SELECT__SHIFT                                                         0x16
#define RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID_MASK                                                       0x00000001L
#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG_MASK                                                      0x00000002L
#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID_MASK                                                     0x0003FFFCL
#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE_MASK                                                     0x00040000L
#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE_MASK                                                         0x00080000L
#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE_MASK                                                   0x00100000L
#define RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE_MASK                                                      0x00200000L
#define RMI_SCOREBOARD_STATUS0__COUNTER_SELECT_MASK                                                           0x07C00000L
//RMI_SCOREBOARD_STATUS1
#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0__SHIFT                                                        0x0
#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0__SHIFT                                              0xc
#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0__SHIFT                                               0xd
#define RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED__SHIFT                                      0xe
#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1__SHIFT                                                        0xf
#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1__SHIFT                                              0x1b
#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1__SHIFT                                               0x1c
#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1__SHIFT                                                  0x1d
#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0__SHIFT                                                  0x1e
#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0_MASK                                                          0x00000FFFL
#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0_MASK                                                0x00001000L
#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0_MASK                                                 0x00002000L
#define RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED_MASK                                        0x00004000L
#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1_MASK                                                          0x07FF8000L
#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1_MASK                                                0x08000000L
#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1_MASK                                                 0x10000000L
#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1_MASK                                                    0x20000000L
#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0_MASK                                                    0x40000000L
//RMI_SCOREBOARD_STATUS2
#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0__SHIFT                                                       0x0
#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0__SHIFT                                             0xc
#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1__SHIFT                                                       0xd
#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1__SHIFT                                             0x19
#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1__SHIFT                                                     0x1a
#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0__SHIFT                                                     0x1b
#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0__SHIFT                                           0x1c
#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1__SHIFT                                           0x1d
#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0__SHIFT                                              0x1e
#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1__SHIFT                                              0x1f
#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0_MASK                                                         0x00000FFFL
#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0_MASK                                               0x00001000L
#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1_MASK                                                         0x01FFE000L
#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1_MASK                                               0x02000000L
#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1_MASK                                                       0x04000000L
#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0_MASK                                                       0x08000000L
#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0_MASK                                             0x10000000L
#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1_MASK                                             0x20000000L
#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0_MASK                                                0x40000000L
#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1_MASK                                                0x80000000L
//RMI_XBAR_ARBITER_CONFIG
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE__SHIFT                                                        0x0
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR__SHIFT                                     0x2
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL__SHIFT                                                       0x3
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN__SHIFT                                         0x4
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE_OVERRIDE_EN__SHIFT                                            0x5
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE__SHIFT                                        0x6
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE__SHIFT                                     0x8
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE__SHIFT                                                        0x10
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR__SHIFT                                     0x12
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL__SHIFT                                                       0x13
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN__SHIFT                                         0x14
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE_OVERRIDE_EN__SHIFT                                            0x15
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE__SHIFT                                        0x16
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE__SHIFT                                     0x18
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE_MASK                                                          0x00000003L
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR_MASK                                       0x00000004L
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_MASK                                                         0x00000008L
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN_MASK                                           0x00000010L
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE_OVERRIDE_EN_MASK                                              0x00000020L
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE_MASK                                          0x000000C0L
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE_MASK                                       0x0000FF00L
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE_MASK                                                          0x00030000L
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR_MASK                                       0x00040000L
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_MASK                                                         0x00080000L
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN_MASK                                           0x00100000L
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE_OVERRIDE_EN_MASK                                              0x00200000L
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE_MASK                                          0x00C00000L
#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE_MASK                                       0xFF000000L
//RMI_XBAR_ARBITER_CONFIG_1
#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD__SHIFT                                  0x0
#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR__SHIFT                                  0x8
#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD_MASK                                    0x000000FFL
#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR_MASK                                    0x0000FF00L
//RMI_CLOCK_CNTRL
#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK__SHIFT                                                         0x0
#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK__SHIFT                                                         0x5
#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK__SHIFT                                                       0xa
#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK__SHIFT                                                       0xf
#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK_MASK                                                           0x0000001FL
#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK_MASK                                                           0x000003E0L
#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK_MASK                                                         0x00007C00L
#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK_MASK                                                         0x000F8000L
//RMI_UTCL1_STATUS
#define RMI_UTCL1_STATUS__FAULT_DETECTED__SHIFT                                                               0x0
#define RMI_UTCL1_STATUS__RETRY_DETECTED__SHIFT                                                               0x1
#define RMI_UTCL1_STATUS__PRT_DETECTED__SHIFT                                                                 0x2
#define RMI_UTCL1_STATUS__FAULT_DETECTED_MASK                                                                 0x00000001L
#define RMI_UTCL1_STATUS__RETRY_DETECTED_MASK                                                                 0x00000002L
#define RMI_UTCL1_STATUS__PRT_DETECTED_MASK                                                                   0x00000004L
//RMI_RB_GLX_CID_MAP
#define RMI_RB_GLX_CID_MAP__CB_COLOR_MAP__SHIFT                                                               0x0
#define RMI_RB_GLX_CID_MAP__CB_FMASK_MAP__SHIFT                                                               0x4
#define RMI_RB_GLX_CID_MAP__CB_CMASK_MAP__SHIFT                                                               0x8
#define RMI_RB_GLX_CID_MAP__CB_DCC_MAP__SHIFT                                                                 0xc
#define RMI_RB_GLX_CID_MAP__DB_Z_MAP__SHIFT                                                                   0x10
#define RMI_RB_GLX_CID_MAP__DB_S_MAP__SHIFT                                                                   0x14
#define RMI_RB_GLX_CID_MAP__DB_TILE_MAP__SHIFT                                                                0x18
#define RMI_RB_GLX_CID_MAP__DB_ZPCPSD_MAP__SHIFT                                                              0x1c
#define RMI_RB_GLX_CID_MAP__CB_COLOR_MAP_MASK                                                                 0x0000000FL
#define RMI_RB_GLX_CID_MAP__CB_FMASK_MAP_MASK                                                                 0x000000F0L
#define RMI_RB_GLX_CID_MAP__CB_CMASK_MAP_MASK                                                                 0x00000F00L
#define RMI_RB_GLX_CID_MAP__CB_DCC_MAP_MASK                                                                   0x0000F000L
#define RMI_RB_GLX_CID_MAP__DB_Z_MAP_MASK                                                                     0x000F0000L
#define RMI_RB_GLX_CID_MAP__DB_S_MAP_MASK                                                                     0x00F00000L
#define RMI_RB_GLX_CID_MAP__DB_TILE_MAP_MASK                                                                  0x0F000000L
#define RMI_RB_GLX_CID_MAP__DB_ZPCPSD_MAP_MASK                                                                0xF0000000L
//RMI_SPARE
#define RMI_SPARE__RMI_ARBITER_STALL_TIMER_ENABLED_ALLOW_STREAMING__SHIFT                                     0x0
#define RMI_SPARE__RMI_2_GL1_128B_READ_DISABLE__SHIFT                                                         0x1
#define RMI_SPARE__RMI_2_GL1_REPEATER_FGCG_DISABLE__SHIFT                                                     0x2
#define RMI_SPARE__RMI_2_RB_REPEATER_FGCG_DISABLE__SHIFT                                                      0x3
#define RMI_SPARE__EARLY_WRITE_ACK_ENABLE_C_RW_NOA_RESOLVE_DIS__SHIFT                                         0x4
#define RMI_SPARE__RMI_REORDER_BYPASS_CHANNEL_DIS__SHIFT                                                      0x5
#define RMI_SPARE__XNACK_RETURN_DATA_OVERRIDE__SHIFT                                                          0x6
#define RMI_SPARE__SPARE_BIT_7__SHIFT                                                                         0x7
#define RMI_SPARE__NOFILL_RMI_CID_CC__SHIFT                                                                   0x8
#define RMI_SPARE__NOFILL_RMI_CID_FC__SHIFT                                                                   0x9
#define RMI_SPARE__NOFILL_RMI_CID_CM__SHIFT                                                                   0xa
#define RMI_SPARE__NOFILL_RMI_CID_DC__SHIFT                                                                   0xb
#define RMI_SPARE__NOFILL_RMI_CID_Z__SHIFT                                                                    0xc
#define RMI_SPARE__NOFILL_RMI_CID_S__SHIFT                                                                    0xd
#define RMI_SPARE__NOFILL_RMI_CID_TILE__SHIFT                                                                 0xe
#define RMI_SPARE__SPARE_BIT_15_0__SHIFT                                                                      0xf
#define RMI_SPARE__ARBITER_ADDRESS_MASK__SHIFT                                                                0x10
#define RMI_SPARE__RMI_ARBITER_STALL_TIMER_ENABLED_ALLOW_STREAMING_MASK                                       0x00000001L
#define RMI_SPARE__RMI_2_GL1_128B_READ_DISABLE_MASK                                                           0x00000002L
#define RMI_SPARE__RMI_2_GL1_REPEATER_FGCG_DISABLE_MASK                                                       0x00000004L
#define RMI_SPARE__RMI_2_RB_REPEATER_FGCG_DISABLE_MASK                                                        0x00000008L
#define RMI_SPARE__EARLY_WRITE_ACK_ENABLE_C_RW_NOA_RESOLVE_DIS_MASK                                           0x00000010L
#define RMI_SPARE__RMI_REORDER_BYPASS_CHANNEL_DIS_MASK                                                        0x00000020L
#define RMI_SPARE__XNACK_RETURN_DATA_OVERRIDE_MASK                                                            0x00000040L
#define RMI_SPARE__SPARE_BIT_7_MASK                                                                           0x00000080L
#define RMI_SPARE__NOFILL_RMI_CID_CC_MASK                                                                     0x00000100L
#define RMI_SPARE__NOFILL_RMI_CID_FC_MASK                                                                     0x00000200L
#define RMI_SPARE__NOFILL_RMI_CID_CM_MASK                                                                     0x00000400L
#define RMI_SPARE__NOFILL_RMI_CID_DC_MASK                                                                     0x00000800L
#define RMI_SPARE__NOFILL_RMI_CID_Z_MASK                                                                      0x00001000L
#define RMI_SPARE__NOFILL_RMI_CID_S_MASK                                                                      0x00002000L
#define RMI_SPARE__NOFILL_RMI_CID_TILE_MASK                                                                   0x00004000L
#define RMI_SPARE__SPARE_BIT_15_0_MASK                                                                        0x00008000L
#define RMI_SPARE__ARBITER_ADDRESS_MASK_MASK                                                                  0xFFFF0000L
//RMI_SPARE_1
#define RMI_SPARE_1__EARLY_WRACK_FIFO_DISABLE__SHIFT                                                          0x0
#define RMI_SPARE_1__SPARE_BIT_9__SHIFT                                                                       0x1
#define RMI_SPARE_1__SPARE_BIT_10__SHIFT                                                                      0x2
#define RMI_SPARE_1__SPARE_BIT_11__SHIFT                                                                      0x3
#define RMI_SPARE_1__SPARE_BIT_12__SHIFT                                                                      0x4
#define RMI_SPARE_1__SPARE_BIT_13__SHIFT                                                                      0x5
#define RMI_SPARE_1__SPARE_BIT_14__SHIFT                                                                      0x6
#define RMI_SPARE_1__SPARE_BIT_15__SHIFT                                                                      0x7
#define RMI_SPARE_1__RMI_REORDER_DIS_BY_CID__SHIFT                                                            0x8
#define RMI_SPARE_1__SPARE_BIT_16_1__SHIFT                                                                    0x10
#define RMI_SPARE_1__EARLY_WRACK_FIFO_DISABLE_MASK                                                            0x00000001L
#define RMI_SPARE_1__SPARE_BIT_9_MASK                                                                         0x00000002L
#define RMI_SPARE_1__SPARE_BIT_10_MASK                                                                        0x00000004L
#define RMI_SPARE_1__SPARE_BIT_11_MASK                                                                        0x00000008L
#define RMI_SPARE_1__SPARE_BIT_12_MASK                                                                        0x00000010L
#define RMI_SPARE_1__SPARE_BIT_13_MASK                                                                        0x00000020L
#define RMI_SPARE_1__SPARE_BIT_14_MASK                                                                        0x00000040L
#define RMI_SPARE_1__SPARE_BIT_15_MASK                                                                        0x00000080L
#define RMI_SPARE_1__RMI_REORDER_DIS_BY_CID_MASK                                                              0x0000FF00L
#define RMI_SPARE_1__SPARE_BIT_16_1_MASK                                                                      0xFFFF0000L
//RMI_SPARE_2
#define RMI_SPARE_2__ERROR_ZERO_BYTE_MASK_CID__SHIFT                                                          0x0
#define RMI_SPARE_2__SPARE_BIT_8_2__SHIFT                                                                     0x10
#define RMI_SPARE_2__SPARE_BIT_8_3__SHIFT                                                                     0x18
#define RMI_SPARE_2__ERROR_ZERO_BYTE_MASK_CID_MASK                                                            0x0000FFFFL
#define RMI_SPARE_2__SPARE_BIT_8_2_MASK                                                                       0x00FF0000L
#define RMI_SPARE_2__SPARE_BIT_8_3_MASK                                                                       0xFF000000L
//CC_RMI_REDUNDANCY
#define CC_RMI_REDUNDANCY__REPAIR_EN_IN_0__SHIFT                                                              0x1
#define CC_RMI_REDUNDANCY__REPAIR_EN_IN_1__SHIFT                                                              0x2
#define CC_RMI_REDUNDANCY__REPAIR_RMI_OVERRIDE__SHIFT                                                         0x3
#define CC_RMI_REDUNDANCY__REPAIR_ID_SWAP__SHIFT                                                              0x4
#define CC_RMI_REDUNDANCY__REPAIR_EN_IN_0_MASK                                                                0x00000002L
#define CC_RMI_REDUNDANCY__REPAIR_EN_IN_1_MASK                                                                0x00000004L
#define CC_RMI_REDUNDANCY__REPAIR_RMI_OVERRIDE_MASK                                                           0x00000008L
#define CC_RMI_REDUNDANCY__REPAIR_ID_SWAP_MASK                                                                0x00000010L
//GC_USER_RMI_REDUNDANCY
#define GC_USER_RMI_REDUNDANCY__REPAIR_EN_IN_0__SHIFT                                                         0x1
#define GC_USER_RMI_REDUNDANCY__REPAIR_EN_IN_1__SHIFT                                                         0x2
#define GC_USER_RMI_REDUNDANCY__REPAIR_RMI_OVERRIDE__SHIFT                                                    0x3
#define GC_USER_RMI_REDUNDANCY__REPAIR_ID_SWAP__SHIFT                                                         0x4
#define GC_USER_RMI_REDUNDANCY__REPAIR_EN_IN_0_MASK                                                           0x00000002L
#define GC_USER_RMI_REDUNDANCY__REPAIR_EN_IN_1_MASK                                                           0x00000004L
#define GC_USER_RMI_REDUNDANCY__REPAIR_RMI_OVERRIDE_MASK                                                      0x00000008L
#define GC_USER_RMI_REDUNDANCY__REPAIR_ID_SWAP_MASK                                                           0x00000010L


// addressBlock: gc_pmmdec
//GCR_GENERAL_CNTL
#define GCR_GENERAL_CNTL__FORCE_4K_L2_RESP__SHIFT                                                             0x0
#define GCR_GENERAL_CNTL__REDUCE_HALF_MAIN_WQ__SHIFT                                                          0x1
#define GCR_GENERAL_CNTL__REDUCE_HALF_PHY_WQ__SHIFT                                                           0x2
#define GCR_GENERAL_CNTL__FORCE_INV_ALL__SHIFT                                                                0x3
#define GCR_GENERAL_CNTL__HI_PRIORITY_CNTL__SHIFT                                                             0x4
#define GCR_GENERAL_CNTL__HI_PRIORITY_DISABLE__SHIFT                                                          0x6
#define GCR_GENERAL_CNTL__BIG_PAGE_FILTER_DISABLE__SHIFT                                                      0x7
#define GCR_GENERAL_CNTL__PERF_CNTR_ENABLE__SHIFT                                                             0x8
#define GCR_GENERAL_CNTL__FORCE_SINGLE_WQ__SHIFT                                                              0x9
#define GCR_GENERAL_CNTL__UTCL2_REQ_PERM__SHIFT                                                               0xa
#define GCR_GENERAL_CNTL__TARGET_MGCG_CLKEN_DIS__SHIFT                                                        0xd
#define GCR_GENERAL_CNTL__MIXED_RANGE_MODE_DIS__SHIFT                                                         0xe
#define GCR_GENERAL_CNTL__ENABLE_16K_UTCL2_REQ__SHIFT                                                         0xf
#define GCR_GENERAL_CNTL__DISABLE_FGCG__SHIFT                                                                 0x10
#define GCR_GENERAL_CNTL__CLIENT_ID__SHIFT                                                                    0x14
#define GCR_GENERAL_CNTL__FORCE_4K_L2_RESP_MASK                                                               0x00000001L
#define GCR_GENERAL_CNTL__REDUCE_HALF_MAIN_WQ_MASK                                                            0x00000002L
#define GCR_GENERAL_CNTL__REDUCE_HALF_PHY_WQ_MASK                                                             0x00000004L
#define GCR_GENERAL_CNTL__FORCE_INV_ALL_MASK                                                                  0x00000008L
#define GCR_GENERAL_CNTL__HI_PRIORITY_CNTL_MASK                                                               0x00000030L
#define GCR_GENERAL_CNTL__HI_PRIORITY_DISABLE_MASK                                                            0x00000040L
#define GCR_GENERAL_CNTL__BIG_PAGE_FILTER_DISABLE_MASK                                                        0x00000080L
#define GCR_GENERAL_CNTL__PERF_CNTR_ENABLE_MASK                                                               0x00000100L
#define GCR_GENERAL_CNTL__FORCE_SINGLE_WQ_MASK                                                                0x00000200L
#define GCR_GENERAL_CNTL__UTCL2_REQ_PERM_MASK                                                                 0x00001C00L
#define GCR_GENERAL_CNTL__TARGET_MGCG_CLKEN_DIS_MASK                                                          0x00002000L
#define GCR_GENERAL_CNTL__MIXED_RANGE_MODE_DIS_MASK                                                           0x00004000L
#define GCR_GENERAL_CNTL__ENABLE_16K_UTCL2_REQ_MASK                                                           0x00008000L
#define GCR_GENERAL_CNTL__DISABLE_FGCG_MASK                                                                   0x00010000L
#define GCR_GENERAL_CNTL__CLIENT_ID_MASK                                                                      0x1FF00000L
//GCR_CMD_STATUS
#define GCR_CMD_STATUS__GCR_CONTROL__SHIFT                                                                    0x0
#define GCR_CMD_STATUS__GCR_SRC__SHIFT                                                                        0x14
#define GCR_CMD_STATUS__GCR_TLB_SHOOTDOWN__SHIFT                                                              0x17
#define GCR_CMD_STATUS__GCR_TLB_SHOOTDOWN_VMID__SHIFT                                                         0x18
#define GCR_CMD_STATUS__UTCL2_NACK_STATUS__SHIFT                                                              0x1c
#define GCR_CMD_STATUS__GCR_SEQ_OP_ERROR__SHIFT                                                               0x1e
#define GCR_CMD_STATUS__UTCL2_NACK_ERROR__SHIFT                                                               0x1f
#define GCR_CMD_STATUS__GCR_CONTROL_MASK                                                                      0x0007FFFFL
#define GCR_CMD_STATUS__GCR_SRC_MASK                                                                          0x00700000L
#define GCR_CMD_STATUS__GCR_TLB_SHOOTDOWN_MASK                                                                0x00800000L
#define GCR_CMD_STATUS__GCR_TLB_SHOOTDOWN_VMID_MASK                                                           0x0F000000L
#define GCR_CMD_STATUS__UTCL2_NACK_STATUS_MASK                                                                0x30000000L
#define GCR_CMD_STATUS__GCR_SEQ_OP_ERROR_MASK                                                                 0x40000000L
#define GCR_CMD_STATUS__UTCL2_NACK_ERROR_MASK                                                                 0x80000000L
//GCR_SPARE
#define GCR_SPARE__SPARE_BIT_1__SHIFT                                                                         0x1
#define GCR_SPARE__SPARE_BIT_2__SHIFT                                                                         0x2
#define GCR_SPARE__SPARE_BIT_3__SHIFT                                                                         0x3
#define GCR_SPARE__SPARE_BIT_4__SHIFT                                                                         0x4
#define GCR_SPARE__SPARE_BIT_5__SHIFT                                                                         0x5
#define GCR_SPARE__SPARE_BIT_6__SHIFT                                                                         0x6
#define GCR_SPARE__SPARE_BIT_7__SHIFT                                                                         0x7
#define GCR_SPARE__SPARE_BIT_8_0__SHIFT                                                                       0x8
#define GCR_SPARE__SPARE_BIT_31_16__SHIFT                                                                     0x10
#define GCR_SPARE__SPARE_BIT_1_MASK                                                                           0x00000002L
#define GCR_SPARE__SPARE_BIT_2_MASK                                                                           0x00000004L
#define GCR_SPARE__SPARE_BIT_3_MASK                                                                           0x00000008L
#define GCR_SPARE__SPARE_BIT_4_MASK                                                                           0x00000010L
#define GCR_SPARE__SPARE_BIT_5_MASK                                                                           0x00000020L
#define GCR_SPARE__SPARE_BIT_6_MASK                                                                           0x00000040L
#define GCR_SPARE__SPARE_BIT_7_MASK                                                                           0x00000080L
#define GCR_SPARE__SPARE_BIT_8_0_MASK                                                                         0x0000FF00L
#define GCR_SPARE__SPARE_BIT_31_16_MASK                                                                       0xFFFF0000L
//PMM_GENERAL_CNTL
#define PMM_GENERAL_CNTL__PMM_MODE__SHIFT                                                                     0x0
#define PMM_GENERAL_CNTL__PMM_DISABLE__SHIFT                                                                  0x1
#define PMM_GENERAL_CNTL__PMM_ALOG_IH_IDLE__SHIFT                                                             0x2
#define PMM_GENERAL_CNTL__PMM_MODE_MASK                                                                       0x00000001L
#define PMM_GENERAL_CNTL__PMM_DISABLE_MASK                                                                    0x00000002L
#define PMM_GENERAL_CNTL__PMM_ALOG_IH_IDLE_MASK                                                               0x00000004L
//GCR_PIO_CNTL
#define GCR_PIO_CNTL__GCR_DATA_INDEX__SHIFT                                                                   0x0
#define GCR_PIO_CNTL__GCR_REG_DONE__SHIFT                                                                     0x2
#define GCR_PIO_CNTL__GCR_REG_RESET__SHIFT                                                                    0x3
#define GCR_PIO_CNTL__GCR_PIO_RSP_TAG__SHIFT                                                                  0x10
#define GCR_PIO_CNTL__GCR_PIO_RSP_DONE__SHIFT                                                                 0x1e
#define GCR_PIO_CNTL__GCR_READY__SHIFT                                                                        0x1f
#define GCR_PIO_CNTL__GCR_DATA_INDEX_MASK                                                                     0x00000003L
#define GCR_PIO_CNTL__GCR_REG_DONE_MASK                                                                       0x00000004L
#define GCR_PIO_CNTL__GCR_REG_RESET_MASK                                                                      0x00000008L
#define GCR_PIO_CNTL__GCR_PIO_RSP_TAG_MASK                                                                    0x00FF0000L
#define GCR_PIO_CNTL__GCR_PIO_RSP_DONE_MASK                                                                   0x40000000L
#define GCR_PIO_CNTL__GCR_READY_MASK                                                                          0x80000000L
//GCR_PIO_DATA
#define GCR_PIO_DATA__GCR_DATA__SHIFT                                                                         0x0
#define GCR_PIO_DATA__GCR_DATA_MASK                                                                           0xFFFFFFFFL


// addressBlock: gc_utcl1dec
//UTCL1_CTRL
#define UTCL1_CTRL__UTCL1_SMALL_PAGE_SIZE__SHIFT                                                              0x0
#define UTCL1_CTRL__UTCL1_LARGE_PAGE_SIZE__SHIFT                                                              0x1
#define UTCL1_CTRL__UTCL1_CACHE_CORE_BYPASS__SHIFT                                                            0x2
#define UTCL1_CTRL__UTCL1_TCP_BYPASS__SHIFT                                                                   0x3
#define UTCL1_CTRL__UTCL1_SQCI_BYPASS__SHIFT                                                                  0x4
#define UTCL1_CTRL__UTCL1_SQCD_BYPASS__SHIFT                                                                  0x5
#define UTCL1_CTRL__UTCL1_RMI_BYPASS__SHIFT                                                                   0x6
#define UTCL1_CTRL__UTCL1_SQG_BYPASS__SHIFT                                                                   0x7
#define UTCL1_CTRL__UTCL1_RMI_DEDICATED_CACHE_CORE__SHIFT                                                     0x8
#define UTCL1_CTRL__UTCL1_FORCE_RANGE_INV_TO_VMID__SHIFT                                                      0x9
#define UTCL1_CTRL__UTCL1_FORCE_INV_ALL__SHIFT                                                                0xa
#define UTCL1_CTRL__UTCL1_FORCE_INV_ALL_DONE__SHIFT                                                           0xb
#define UTCL1_CTRL__UTCL1_UTCL2_FGCG_REPEATERS_OVERRIDE__SHIFT                                                0xc
#define UTCL1_CTRL__UTCL1_INV_FILTER_2M__SHIFT                                                                0xd
#define UTCL1_CTRL__UTCL1_RANGE_INV_FORCE_CHK_ALL__SHIFT                                                      0xe
#define UTCL1_CTRL__UTCL1_UTCL0_RET_FGCG_REPEATERS_OVERRIDE__SHIFT                                            0xf
#define UTCL1_CTRL__UTCL1_UTCL0_INVREQ_FGCG_REPEATERS_OVERRIDE__SHIFT                                         0x10
#define UTCL1_CTRL__GCRD_FGCG_DISABLE__SHIFT                                                                  0x11
#define UTCL1_CTRL__UTCL1_MH_INV_FRAG_SIZE_OVERRIDE__SHIFT                                                    0x12
#define UTCL1_CTRL__UTCL1_CACHE_WRITE_PERM__SHIFT                                                             0x13
#define UTCL1_CTRL__UTCL1_MH_CAM_DUPLICATE_4K_FILTER__SHIFT                                                   0x14
#define UTCL1_CTRL__UTCL1_MH_DISABLE_DUPLICATES__SHIFT                                                        0x15
#define UTCL1_CTRL__UTCL1_MH_DISABLE_RECENT_BUFFER__SHIFT                                                     0x17
#define UTCL1_CTRL__UTCL1_MISS_CC_PRIORITY__SHIFT                                                             0x18
#define UTCL1_CTRL__UTCL1_REDUCE_CC_SIZE__SHIFT                                                               0x1a
#define UTCL1_CTRL__RESERVED__SHIFT                                                                           0x1c
#define UTCL1_CTRL__UTCL1_SMALL_PAGE_SIZE_MASK                                                                0x00000001L
#define UTCL1_CTRL__UTCL1_LARGE_PAGE_SIZE_MASK                                                                0x00000002L
#define UTCL1_CTRL__UTCL1_CACHE_CORE_BYPASS_MASK                                                              0x00000004L
#define UTCL1_CTRL__UTCL1_TCP_BYPASS_MASK                                                                     0x00000008L
#define UTCL1_CTRL__UTCL1_SQCI_BYPASS_MASK                                                                    0x00000010L
#define UTCL1_CTRL__UTCL1_SQCD_BYPASS_MASK                                                                    0x00000020L
#define UTCL1_CTRL__UTCL1_RMI_BYPASS_MASK                                                                     0x00000040L
#define UTCL1_CTRL__UTCL1_SQG_BYPASS_MASK                                                                     0x00000080L
#define UTCL1_CTRL__UTCL1_RMI_DEDICATED_CACHE_CORE_MASK                                                       0x00000100L
#define UTCL1_CTRL__UTCL1_FORCE_RANGE_INV_TO_VMID_MASK                                                        0x00000200L
#define UTCL1_CTRL__UTCL1_FORCE_INV_ALL_MASK                                                                  0x00000400L
#define UTCL1_CTRL__UTCL1_FORCE_INV_ALL_DONE_MASK                                                             0x00000800L
#define UTCL1_CTRL__UTCL1_UTCL2_FGCG_REPEATERS_OVERRIDE_MASK                                                  0x00001000L
#define UTCL1_CTRL__UTCL1_INV_FILTER_2M_MASK                                                                  0x00002000L
#define UTCL1_CTRL__UTCL1_RANGE_INV_FORCE_CHK_ALL_MASK                                                        0x00004000L
#define UTCL1_CTRL__UTCL1_UTCL0_RET_FGCG_REPEATERS_OVERRIDE_MASK                                              0x00008000L
#define UTCL1_CTRL__UTCL1_UTCL0_INVREQ_FGCG_REPEATERS_OVERRIDE_MASK                                           0x00010000L
#define UTCL1_CTRL__GCRD_FGCG_DISABLE_MASK                                                                    0x00020000L
#define UTCL1_CTRL__UTCL1_MH_INV_FRAG_SIZE_OVERRIDE_MASK                                                      0x00040000L
#define UTCL1_CTRL__UTCL1_CACHE_WRITE_PERM_MASK                                                               0x00080000L
#define UTCL1_CTRL__UTCL1_MH_CAM_DUPLICATE_4K_FILTER_MASK                                                     0x00100000L
#define UTCL1_CTRL__UTCL1_MH_DISABLE_DUPLICATES_MASK                                                          0x00200000L
#define UTCL1_CTRL__UTCL1_MH_DISABLE_RECENT_BUFFER_MASK                                                       0x00800000L
#define UTCL1_CTRL__UTCL1_MISS_CC_PRIORITY_MASK                                                               0x03000000L
#define UTCL1_CTRL__UTCL1_REDUCE_CC_SIZE_MASK                                                                 0x0C000000L
#define UTCL1_CTRL__RESERVED_MASK                                                                             0xF0000000L
//UTCL1_ALOG
#define UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER1_THRESHOLD__SHIFT                                                 0x0
#define UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER2_BYPASS__SHIFT                                                    0x3
#define UTCL1_ALOG__UTCL1_ALOG_ACTIVE__SHIFT                                                                  0x4
#define UTCL1_ALOG__UTCL1_ALOG_MODE__SHIFT                                                                    0x5
#define UTCL1_ALOG__UTCL1_ALOG_MODE2_LOCK_WINDOW__SHIFT                                                       0x6
#define UTCL1_ALOG__UTCL1_ALOG_ONLY_MISS__SHIFT                                                               0x9
#define UTCL1_ALOG__UTCL1_ALOG_MODE2_INTR_THRESHOLD__SHIFT                                                    0xa
#define UTCL1_ALOG__UTCL1_ALOG_SPACE_EN__SHIFT                                                                0xc
#define UTCL1_ALOG__UTCL1_ALOG_CLEAN__SHIFT                                                                   0xf
#define UTCL1_ALOG__UTCL1_ALOG_IDLE__SHIFT                                                                    0x10
#define UTCL1_ALOG__UTCL1_ALOG_TRACK_SEGMENT_SIZE__SHIFT                                                      0x11
#define UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER1_BYPASS__SHIFT                                                    0x17
#define UTCL1_ALOG__UTCL1_ALOG_MODE1_INTR_ON_ALLOC__SHIFT                                                     0x18
#define UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER1_THRESHOLD_MASK                                                   0x00000007L
#define UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER2_BYPASS_MASK                                                      0x00000008L
#define UTCL1_ALOG__UTCL1_ALOG_ACTIVE_MASK                                                                    0x00000010L
#define UTCL1_ALOG__UTCL1_ALOG_MODE_MASK                                                                      0x00000020L
#define UTCL1_ALOG__UTCL1_ALOG_MODE2_LOCK_WINDOW_MASK                                                         0x000001C0L
#define UTCL1_ALOG__UTCL1_ALOG_ONLY_MISS_MASK                                                                 0x00000200L
#define UTCL1_ALOG__UTCL1_ALOG_MODE2_INTR_THRESHOLD_MASK                                                      0x00000C00L
#define UTCL1_ALOG__UTCL1_ALOG_SPACE_EN_MASK                                                                  0x00007000L
#define UTCL1_ALOG__UTCL1_ALOG_CLEAN_MASK                                                                     0x00008000L
#define UTCL1_ALOG__UTCL1_ALOG_IDLE_MASK                                                                      0x00010000L
#define UTCL1_ALOG__UTCL1_ALOG_TRACK_SEGMENT_SIZE_MASK                                                        0x007E0000L
#define UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER1_BYPASS_MASK                                                      0x00800000L
#define UTCL1_ALOG__UTCL1_ALOG_MODE1_INTR_ON_ALLOC_MASK                                                       0x01000000L
//UTCL1_UTCL0_INVREQ_DISABLE
#define UTCL1_UTCL0_INVREQ_DISABLE__UTCL1_UTCL0_INVREQ_DISABLE__SHIFT                                         0x0
#define UTCL1_UTCL0_INVREQ_DISABLE__UTCL1_UTCL0_INVREQ_DISABLE_MASK                                           0xFFFFFFFFL
//GCRD_SA_TARGETS_DISABLE
#define GCRD_SA_TARGETS_DISABLE__GCRD_TARGETS_DISABLE__SHIFT                                                  0x0
#define GCRD_SA_TARGETS_DISABLE__GCRD_TARGETS_DISABLE_MASK                                                    0x0007FFFFL
//UTCL1_STATUS
#define UTCL1_STATUS__UTCL1_HIT_PATH_BUSY__SHIFT                                                              0x0
#define UTCL1_STATUS__UTCL1_MH_BUSY__SHIFT                                                                    0x1
#define UTCL1_STATUS__UTCL1_INV_BUSY__SHIFT                                                                   0x2
#define UTCL1_STATUS__UTCL1_PENDING_UTCL2_REQ__SHIFT                                                          0x3
#define UTCL1_STATUS__UTCL1_PENDING_UTCL2_RET__SHIFT                                                          0x4
#define UTCL1_STATUS__UTCL1_LAST_UTCL2_RET_XNACK__SHIFT                                                       0x5
#define UTCL1_STATUS__UTCL1_RANGE_INV_IN_PROGRESS__SHIFT                                                      0x7
#define UTCL1_STATUS__RESERVED__SHIFT                                                                         0x8
#define UTCL1_STATUS__UTCL1_HIT_PATH_BUSY_MASK                                                                0x00000001L
#define UTCL1_STATUS__UTCL1_MH_BUSY_MASK                                                                      0x00000002L
#define UTCL1_STATUS__UTCL1_INV_BUSY_MASK                                                                     0x00000004L
#define UTCL1_STATUS__UTCL1_PENDING_UTCL2_REQ_MASK                                                            0x00000008L
#define UTCL1_STATUS__UTCL1_PENDING_UTCL2_RET_MASK                                                            0x00000010L
#define UTCL1_STATUS__UTCL1_LAST_UTCL2_RET_XNACK_MASK                                                         0x00000060L
#define UTCL1_STATUS__UTCL1_RANGE_INV_IN_PROGRESS_MASK                                                        0x00000080L
#define UTCL1_STATUS__RESERVED_MASK                                                                           0x00000100L


// addressBlock: gc_gcvml2pfdec
//GCVM_L2_CNTL
#define GCVM_L2_CNTL__ENABLE_L2_CACHE__SHIFT                                                                  0x0
#define GCVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT                                                    0x1
#define GCVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT                                                    0x2
#define GCVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT                                                    0x4
#define GCVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT                                                0x8
#define GCVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT                                          0x9
#define GCVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT                                         0xa
#define GCVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT                                         0xb
#define GCVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT                                                         0xc
#define GCVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT                                                          0xf
#define GCVM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT                                                         0x12
#define GCVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT                                                    0x13
#define GCVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT                                                      0x15
#define GCVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT                                                           0x1a
#define GCVM_L2_CNTL__ENABLE_L2_CACHE_MASK                                                                    0x00000001L
#define GCVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK                                                      0x00000002L
#define GCVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK                                                      0x0000000CL
#define GCVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK                                                      0x00000030L
#define GCVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK                                                  0x00000100L
#define GCVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK                                            0x00000200L
#define GCVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK                                           0x00000400L
#define GCVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK                                           0x00000800L
#define GCVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK                                                           0x00007000L
#define GCVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK                                                            0x00038000L
#define GCVM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK                                                           0x00040000L
#define GCVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK                                                      0x00180000L
#define GCVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK                                                        0x03E00000L
#define GCVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK                                                             0x0C000000L
//GCVM_L2_CNTL2
#define GCVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT                                                          0x0
#define GCVM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT                                                             0x1
#define GCVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT                                                   0x15
#define GCVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT                                                 0x16
#define GCVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT                                                          0x17
#define GCVM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT                                                           0x1a
#define GCVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT                                                        0x1c
#define GCVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK                                                            0x00000001L
#define GCVM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK                                                               0x00000002L
#define GCVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK                                                     0x00200000L
#define GCVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK                                                   0x00400000L
#define GCVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK                                                            0x03800000L
#define GCVM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK                                                             0x0C000000L
#define GCVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK                                                          0x70000000L
//GCVM_L2_CNTL3
#define GCVM_L2_CNTL3__BANK_SELECT__SHIFT                                                                     0x0
#define GCVM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT                                                            0x6
#define GCVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT                                        0x8
#define GCVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT                                                     0xf
#define GCVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT                                                     0x14
#define GCVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT                                                      0x15
#define GCVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT                                                    0x18
#define GCVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT                                                          0x1c
#define GCVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT                                                        0x1d
#define GCVM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT                                                            0x1e
#define GCVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT                                                       0x1f
#define GCVM_L2_CNTL3__BANK_SELECT_MASK                                                                       0x0000003FL
#define GCVM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK                                                              0x000000C0L
#define GCVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK                                          0x00001F00L
#define GCVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                                                       0x000F8000L
#define GCVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK                                                       0x00100000L
#define GCVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK                                                        0x00E00000L
#define GCVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK                                                      0x0F000000L
#define GCVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK                                                            0x10000000L
#define GCVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK                                                          0x20000000L
#define GCVM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK                                                              0x40000000L
#define GCVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK                                                         0x80000000L
//GCVM_L2_STATUS
#define GCVM_L2_STATUS__L2_BUSY__SHIFT                                                                        0x0
#define GCVM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT                                                            0x1
#define GCVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT                                               0x11
#define GCVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT                                             0x12
#define GCVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT                                                 0x13
#define GCVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT                                                 0x14
#define GCVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT                                                 0x15
#define GCVM_L2_STATUS__L2_BUSY_MASK                                                                          0x00000001L
#define GCVM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK                                                              0x0001FFFEL
#define GCVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK                                                 0x00020000L
#define GCVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK                                               0x00040000L
#define GCVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK                                                   0x00080000L
#define GCVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK                                                   0x00100000L
#define GCVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK                                                   0x00200000L
//GCVM_DUMMY_PAGE_FAULT_CNTL
#define GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT                                            0x0
#define GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT                                         0x1
#define GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT                                            0x2
#define GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK                                              0x00000001L
#define GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK                                           0x00000002L
#define GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK                                              0x000000FCL
//GCVM_DUMMY_PAGE_FAULT_ADDR_LO32
#define GCVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT                                          0x0
#define GCVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK                                            0xFFFFFFFFL
//GCVM_DUMMY_PAGE_FAULT_ADDR_HI32
#define GCVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT                                           0x0
#define GCVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK                                             0x0000000FL
//GCVM_INVALIDATE_CNTL
#define GCVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING__SHIFT                                                      0x0
#define GCVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING__SHIFT                                                      0x8
#define GCVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING_MASK                                                        0x000000FFL
#define GCVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING_MASK                                                        0x0000FF00L
//GCVM_L2_PROTECTION_FAULT_CNTL
#define GCVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                              0x0
#define GCVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT           0x1
#define GCVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                           0x2
#define GCVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                            0x3
#define GCVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                            0x4
#define GCVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                            0x5
#define GCVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT               0x6
#define GCVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                            0x7
#define GCVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                      0x8
#define GCVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                           0x9
#define GCVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                            0xa
#define GCVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                           0xb
#define GCVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                         0xc
#define GCVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT                              0xd
#define GCVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT                        0x1d
#define GCVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT                                         0x1e
#define GCVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT                                            0x1f
#define GCVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                0x00000001L
#define GCVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK             0x00000002L
#define GCVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                             0x00000004L
#define GCVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                              0x00000008L
#define GCVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                              0x00000010L
#define GCVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                              0x00000020L
#define GCVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                 0x00000040L
#define GCVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                              0x00000080L
#define GCVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                        0x00000100L
#define GCVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                             0x00000200L
#define GCVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                              0x00000400L
#define GCVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                             0x00000800L
#define GCVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                           0x00001000L
#define GCVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK                                0x1FFFE000L
#define GCVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK                          0x20000000L
#define GCVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK                                           0x40000000L
#define GCVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK                                              0x80000000L
//GCVM_L2_PROTECTION_FAULT_CNTL2
#define GCVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT                                  0x0
#define GCVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT                            0x10
#define GCVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT                                      0x11
#define GCVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT                           0x12
#define GCVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT                                   0x13
#define GCVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK                                    0x0000FFFFL
#define GCVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK                              0x00010000L
#define GCVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK                                        0x00020000L
#define GCVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK                             0x00040000L
#define GCVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK                                     0x00080000L
//GCVM_L2_PROTECTION_FAULT_MM_CNTL3
#define GCVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT                0x0
#define GCVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK                  0xFFFFFFFFL
//GCVM_L2_PROTECTION_FAULT_MM_CNTL4
#define GCVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT               0x0
#define GCVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK                 0xFFFFFFFFL
//GCVM_L2_PROTECTION_FAULT_STATUS
#define GCVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT                                                   0x0
#define GCVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT                                                  0x1
#define GCVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT                                             0x4
#define GCVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT                                                 0x8
#define GCVM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT                                                           0x9
#define GCVM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT                                                            0x12
#define GCVM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT                                                        0x13
#define GCVM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT                                                          0x14
#define GCVM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT                                                            0x18
#define GCVM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT                                                          0x19
#define GCVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK                                                     0x00000001L
#define GCVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK                                                    0x0000000EL
#define GCVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK                                               0x000000F0L
#define GCVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK                                                   0x00000100L
#define GCVM_L2_PROTECTION_FAULT_STATUS__CID_MASK                                                             0x0003FE00L
#define GCVM_L2_PROTECTION_FAULT_STATUS__RW_MASK                                                              0x00040000L
#define GCVM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK                                                          0x00080000L
#define GCVM_L2_PROTECTION_FAULT_STATUS__VMID_MASK                                                            0x00F00000L
#define GCVM_L2_PROTECTION_FAULT_STATUS__VF_MASK                                                              0x01000000L
#define GCVM_L2_PROTECTION_FAULT_STATUS__VFID_MASK                                                            0x3E000000L
//GCVM_L2_PROTECTION_FAULT_ADDR_LO32
#define GCVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT                                     0x0
#define GCVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK                                       0xFFFFFFFFL
//GCVM_L2_PROTECTION_FAULT_ADDR_HI32
#define GCVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT                                      0x0
#define GCVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK                                        0x0000000FL
//GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32
#define GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT                            0x0
#define GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK                              0xFFFFFFFFL
//GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32
#define GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT                             0x0
#define GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK                               0x0000000FL
//GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32
#define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                     0x0
#define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                       0xFFFFFFFFL
//GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32
#define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                      0x0
#define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                        0x0000000FL
//GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32
#define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                    0x0
#define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                      0xFFFFFFFFL
//GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32
#define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                     0x0
#define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                       0x0000000FL
//GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32
#define GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT                       0x0
#define GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK                         0xFFFFFFFFL
//GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32
#define GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT                        0x0
#define GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK                          0x0000000FL
//GCVM_L2_CNTL4
#define GCVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT                                                     0x0
#define GCVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT                                                    0x6
#define GCVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT                                                    0x7
#define GCVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT                                         0x8
#define GCVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT                                        0x12
#define GCVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT                                                             0x1c
#define GCVM_L2_CNTL4__GC_CH_FGCG_OFF__SHIFT                                                                  0x1d
#define GCVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK                                                       0x0000003FL
#define GCVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK                                                      0x00000040L
#define GCVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK                                                      0x00000080L
#define GCVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK                                           0x0003FF00L
#define GCVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK                                          0x0FFC0000L
#define GCVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK                                                               0x10000000L
#define GCVM_L2_CNTL4__GC_CH_FGCG_OFF_MASK                                                                    0x20000000L
//GCVM_L2_MM_GROUP_RT_CLASSES
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT                                                  0x0
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT                                                  0x1
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT                                                  0x2
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT                                                  0x3
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT                                                  0x4
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT                                                  0x5
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT                                                  0x6
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT                                                  0x7
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT                                                  0x8
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT                                                  0x9
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT                                                 0xa
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT                                                 0xb
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT                                                 0xc
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT                                                 0xd
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT                                                 0xe
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT                                                 0xf
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT                                                 0x10
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT                                                 0x11
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT                                                 0x12
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT                                                 0x13
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT                                                 0x14
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT                                                 0x15
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT                                                 0x16
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT                                                 0x17
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT                                                 0x18
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT                                                 0x19
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT                                                 0x1a
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT                                                 0x1b
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT                                                 0x1c
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT                                                 0x1d
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT                                                 0x1e
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT                                                 0x1f
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK                                                    0x00000001L
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK                                                    0x00000002L
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK                                                    0x00000004L
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK                                                    0x00000008L
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK                                                    0x00000010L
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK                                                    0x00000020L
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK                                                    0x00000040L
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK                                                    0x00000080L
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK                                                    0x00000100L
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK                                                    0x00000200L
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK                                                   0x00000400L
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK                                                   0x00000800L
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK                                                   0x00001000L
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK                                                   0x00002000L
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK                                                   0x00004000L
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK                                                   0x00008000L
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK                                                   0x00010000L
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK                                                   0x00020000L
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK                                                   0x00040000L
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK                                                   0x00080000L
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK                                                   0x00100000L
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK                                                   0x00200000L
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK                                                   0x00400000L
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK                                                   0x00800000L
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK                                                   0x01000000L
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK                                                   0x02000000L
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK                                                   0x04000000L
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK                                                   0x08000000L
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK                                                   0x10000000L
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK                                                   0x20000000L
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK                                                   0x40000000L
#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK                                                   0x80000000L
//GCVM_L2_BANK_SELECT_RESERVED_CID
#define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT                                      0x0
#define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT                                     0xa
#define GCVM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT                                                       0x14
#define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT                             0x18
#define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT                          0x19
#define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT                                 0x1a
#define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK                                        0x000001FFL
#define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK                                       0x0007FC00L
#define GCVM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK                                                         0x00100000L
#define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK                               0x01000000L
#define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK                            0x02000000L
#define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE_MASK                                   0x7C000000L
//GCVM_L2_BANK_SELECT_RESERVED_CID2
#define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT                                     0x0
#define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT                                    0xa
#define GCVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT                                                      0x14
#define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT                            0x18
#define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT                         0x19
#define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT                                0x1a
#define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK                                       0x000001FFL
#define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK                                      0x0007FC00L
#define GCVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK                                                        0x00100000L
#define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK                              0x01000000L
#define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK                           0x02000000L
#define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE_MASK                                  0x7C000000L
//GCVM_L2_CACHE_PARITY_CNTL
#define GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT                               0x0
#define GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT                             0x1
#define GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT                                  0x2
#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT                               0x3
#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT                             0x4
#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT                                  0x5
#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT                                                    0x6
#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT                                                  0x9
#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT                                                   0xc
#define GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK                                 0x00000001L
#define GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK                               0x00000002L
#define GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK                                    0x00000004L
#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK                                 0x00000008L
#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK                               0x00000010L
#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK                                    0x00000020L
#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK                                                      0x000001C0L
#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK                                                    0x00000E00L
#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK                                                     0x0000F000L
//GCVM_L2_CNTL5
#define GCVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT                                                   0x0
#define GCVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID__SHIFT                                                       0x5
#define GCVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK                                                     0x0000001FL
#define GCVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID_MASK                                                         0x00003FE0L
//GCVM_L2_GCR_CNTL
#define GCVM_L2_GCR_CNTL__GCR_ENABLE__SHIFT                                                                   0x0
#define GCVM_L2_GCR_CNTL__GCR_CLIENT_ID__SHIFT                                                                0x1
#define GCVM_L2_GCR_CNTL__GCR_ENABLE_MASK                                                                     0x00000001L
#define GCVM_L2_GCR_CNTL__GCR_CLIENT_ID_MASK                                                                  0x000003FEL
//GCVML2_WALKER_MACRO_THROTTLE_TIME
#define GCVML2_WALKER_MACRO_THROTTLE_TIME__TIME__SHIFT                                                        0x0
#define GCVML2_WALKER_MACRO_THROTTLE_TIME__TIME_MASK                                                          0x00FFFFFFL
//GCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT
#define GCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT__LIMIT__SHIFT                                                0x1
#define GCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT__LIMIT_MASK                                                  0x0000FFFEL
//GCVML2_WALKER_MICRO_THROTTLE_TIME
#define GCVML2_WALKER_MICRO_THROTTLE_TIME__TIME__SHIFT                                                        0x0
#define GCVML2_WALKER_MICRO_THROTTLE_TIME__TIME_MASK                                                          0x00FFFFFFL
//GCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT
#define GCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT__LIMIT__SHIFT                                                0x1
#define GCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT__LIMIT_MASK                                                  0x0000FFFEL
//GCVM_L2_PTE_CACHE_DUMP_CNTL
#define GCVM_L2_PTE_CACHE_DUMP_CNTL__ENABLE__SHIFT                                                            0x0
#define GCVM_L2_PTE_CACHE_DUMP_CNTL__READY__SHIFT                                                             0x1
#define GCVM_L2_PTE_CACHE_DUMP_CNTL__BANK__SHIFT                                                              0x4
#define GCVM_L2_PTE_CACHE_DUMP_CNTL__CACHE__SHIFT                                                             0x8
#define GCVM_L2_PTE_CACHE_DUMP_CNTL__ASSOC__SHIFT                                                             0xc
#define GCVM_L2_PTE_CACHE_DUMP_CNTL__INDEX__SHIFT                                                             0x10
#define GCVM_L2_PTE_CACHE_DUMP_CNTL__ENABLE_MASK                                                              0x00000001L
#define GCVM_L2_PTE_CACHE_DUMP_CNTL__READY_MASK                                                               0x00000002L
#define GCVM_L2_PTE_CACHE_DUMP_CNTL__BANK_MASK                                                                0x000000F0L
#define GCVM_L2_PTE_CACHE_DUMP_CNTL__CACHE_MASK                                                               0x00000F00L
#define GCVM_L2_PTE_CACHE_DUMP_CNTL__ASSOC_MASK                                                               0x0000F000L
#define GCVM_L2_PTE_CACHE_DUMP_CNTL__INDEX_MASK                                                               0xFFFF0000L
//GCVM_L2_PTE_CACHE_DUMP_READ
#define GCVM_L2_PTE_CACHE_DUMP_READ__DATA__SHIFT                                                              0x0
#define GCVM_L2_PTE_CACHE_DUMP_READ__DATA_MASK                                                                0xFFFFFFFFL


// addressBlock: gc_gcvml2vcdec
//GCVM_CONTEXT0_CNTL
#define GCVM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT                                                             0x0
#define GCVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                           0x1
#define GCVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                      0x3
#define GCVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                     0x7
#define GCVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT                                                          0x8
#define GCVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x9
#define GCVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xa
#define GCVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xb
#define GCVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xc
#define GCVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xd
#define GCVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xe
#define GCVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xf
#define GCVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x10
#define GCVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x11
#define GCVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x12
#define GCVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x13
#define GCVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x14
#define GCVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x15
#define GCVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x16
#define GCVM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK                                                               0x00000001L
#define GCVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK                                                             0x00000006L
#define GCVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                        0x00000078L
#define GCVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                       0x00000080L
#define GCVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK                                                            0x00000100L
#define GCVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00000200L
#define GCVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00000400L
#define GCVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00000800L
#define GCVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00001000L
#define GCVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00002000L
#define GCVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00004000L
#define GCVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00008000L
#define GCVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00010000L
#define GCVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00020000L
#define GCVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00040000L
#define GCVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00080000L
#define GCVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00100000L
#define GCVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00200000L
#define GCVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x00400000L
//GCVM_CONTEXT1_CNTL
#define GCVM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT                                                             0x0
#define GCVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                           0x1
#define GCVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                      0x3
#define GCVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                     0x7
#define GCVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT                                                          0x8
#define GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x9
#define GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xa
#define GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xb
#define GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xc
#define GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xd
#define GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xe
#define GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xf
#define GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x10
#define GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x11
#define GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x12
#define GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x13
#define GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x14
#define GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x15
#define GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x16
#define GCVM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK                                                               0x00000001L
#define GCVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK                                                             0x00000006L
#define GCVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                        0x00000078L
#define GCVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                       0x00000080L
#define GCVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK                                                            0x00000100L
#define GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00000200L
#define GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00000400L
#define GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00000800L
#define GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00001000L
#define GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00002000L
#define GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00004000L
#define GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00008000L
#define GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00010000L
#define GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00020000L
#define GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00040000L
#define GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00080000L
#define GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00100000L
#define GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00200000L
#define GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x00400000L
//GCVM_CONTEXT2_CNTL
#define GCVM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT                                                             0x0
#define GCVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                           0x1
#define GCVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                      0x3
#define GCVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                     0x7
#define GCVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT                                                          0x8
#define GCVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x9
#define GCVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xa
#define GCVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xb
#define GCVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xc
#define GCVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xd
#define GCVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xe
#define GCVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xf
#define GCVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x10
#define GCVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x11
#define GCVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x12
#define GCVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x13
#define GCVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x14
#define GCVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x15
#define GCVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x16
#define GCVM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK                                                               0x00000001L
#define GCVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK                                                             0x00000006L
#define GCVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                        0x00000078L
#define GCVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                       0x00000080L
#define GCVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK                                                            0x00000100L
#define GCVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00000200L
#define GCVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00000400L
#define GCVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00000800L
#define GCVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00001000L
#define GCVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00002000L
#define GCVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00004000L
#define GCVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00008000L
#define GCVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00010000L
#define GCVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00020000L
#define GCVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00040000L
#define GCVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00080000L
#define GCVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00100000L
#define GCVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00200000L
#define GCVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x00400000L
//GCVM_CONTEXT3_CNTL
#define GCVM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT                                                             0x0
#define GCVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                           0x1
#define GCVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                      0x3
#define GCVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                     0x7
#define GCVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT                                                          0x8
#define GCVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x9
#define GCVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xa
#define GCVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xb
#define GCVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xc
#define GCVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xd
#define GCVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xe
#define GCVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xf
#define GCVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x10
#define GCVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x11
#define GCVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x12
#define GCVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x13
#define GCVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x14
#define GCVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x15
#define GCVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x16
#define GCVM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK                                                               0x00000001L
#define GCVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK                                                             0x00000006L
#define GCVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                        0x00000078L
#define GCVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                       0x00000080L
#define GCVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK                                                            0x00000100L
#define GCVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00000200L
#define GCVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00000400L
#define GCVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00000800L
#define GCVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00001000L
#define GCVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00002000L
#define GCVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00004000L
#define GCVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00008000L
#define GCVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00010000L
#define GCVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00020000L
#define GCVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00040000L
#define GCVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00080000L
#define GCVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00100000L
#define GCVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00200000L
#define GCVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x00400000L
//GCVM_CONTEXT4_CNTL
#define GCVM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT                                                             0x0
#define GCVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                           0x1
#define GCVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                      0x3
#define GCVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                     0x7
#define GCVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT                                                          0x8
#define GCVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x9
#define GCVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xa
#define GCVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xb
#define GCVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xc
#define GCVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xd
#define GCVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xe
#define GCVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xf
#define GCVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x10
#define GCVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x11
#define GCVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x12
#define GCVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x13
#define GCVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x14
#define GCVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x15
#define GCVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x16
#define GCVM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK                                                               0x00000001L
#define GCVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK                                                             0x00000006L
#define GCVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                        0x00000078L
#define GCVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                       0x00000080L
#define GCVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK                                                            0x00000100L
#define GCVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00000200L
#define GCVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00000400L
#define GCVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00000800L
#define GCVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00001000L
#define GCVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00002000L
#define GCVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00004000L
#define GCVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00008000L
#define GCVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00010000L
#define GCVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00020000L
#define GCVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00040000L
#define GCVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00080000L
#define GCVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00100000L
#define GCVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00200000L
#define GCVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x00400000L
//GCVM_CONTEXT5_CNTL
#define GCVM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT                                                             0x0
#define GCVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                           0x1
#define GCVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                      0x3
#define GCVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                     0x7
#define GCVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT                                                          0x8
#define GCVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x9
#define GCVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xa
#define GCVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xb
#define GCVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xc
#define GCVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xd
#define GCVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xe
#define GCVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xf
#define GCVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x10
#define GCVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x11
#define GCVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x12
#define GCVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x13
#define GCVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x14
#define GCVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x15
#define GCVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x16
#define GCVM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK                                                               0x00000001L
#define GCVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK                                                             0x00000006L
#define GCVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                        0x00000078L
#define GCVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                       0x00000080L
#define GCVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK                                                            0x00000100L
#define GCVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00000200L
#define GCVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00000400L
#define GCVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00000800L
#define GCVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00001000L
#define GCVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00002000L
#define GCVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00004000L
#define GCVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00008000L
#define GCVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00010000L
#define GCVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00020000L
#define GCVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00040000L
#define GCVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00080000L
#define GCVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00100000L
#define GCVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00200000L
#define GCVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x00400000L
//GCVM_CONTEXT6_CNTL
#define GCVM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT                                                             0x0
#define GCVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                           0x1
#define GCVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                      0x3
#define GCVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                     0x7
#define GCVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT                                                          0x8
#define GCVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x9
#define GCVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xa
#define GCVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xb
#define GCVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xc
#define GCVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xd
#define GCVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xe
#define GCVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xf
#define GCVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x10
#define GCVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x11
#define GCVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x12
#define GCVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x13
#define GCVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x14
#define GCVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x15
#define GCVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x16
#define GCVM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK                                                               0x00000001L
#define GCVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK                                                             0x00000006L
#define GCVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                        0x00000078L
#define GCVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                       0x00000080L
#define GCVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK                                                            0x00000100L
#define GCVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00000200L
#define GCVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00000400L
#define GCVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00000800L
#define GCVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00001000L
#define GCVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00002000L
#define GCVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00004000L
#define GCVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00008000L
#define GCVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00010000L
#define GCVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00020000L
#define GCVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00040000L
#define GCVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00080000L
#define GCVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00100000L
#define GCVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00200000L
#define GCVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x00400000L
//GCVM_CONTEXT7_CNTL
#define GCVM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT                                                             0x0
#define GCVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                           0x1
#define GCVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                      0x3
#define GCVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                     0x7
#define GCVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT                                                          0x8
#define GCVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x9
#define GCVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xa
#define GCVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xb
#define GCVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xc
#define GCVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xd
#define GCVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xe
#define GCVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xf
#define GCVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x10
#define GCVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x11
#define GCVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x12
#define GCVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x13
#define GCVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x14
#define GCVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x15
#define GCVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x16
#define GCVM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK                                                               0x00000001L
#define GCVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK                                                             0x00000006L
#define GCVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                        0x00000078L
#define GCVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                       0x00000080L
#define GCVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK                                                            0x00000100L
#define GCVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00000200L
#define GCVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00000400L
#define GCVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00000800L
#define GCVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00001000L
#define GCVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00002000L
#define GCVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00004000L
#define GCVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00008000L
#define GCVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00010000L
#define GCVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00020000L
#define GCVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00040000L
#define GCVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00080000L
#define GCVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00100000L
#define GCVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00200000L
#define GCVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x00400000L
//GCVM_CONTEXT8_CNTL
#define GCVM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT                                                             0x0
#define GCVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                           0x1
#define GCVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                      0x3
#define GCVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                     0x7
#define GCVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT                                                          0x8
#define GCVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x9
#define GCVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xa
#define GCVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xb
#define GCVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xc
#define GCVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xd
#define GCVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xe
#define GCVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xf
#define GCVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x10
#define GCVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x11
#define GCVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x12
#define GCVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x13
#define GCVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x14
#define GCVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x15
#define GCVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x16
#define GCVM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK                                                               0x00000001L
#define GCVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK                                                             0x00000006L
#define GCVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                        0x00000078L
#define GCVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                       0x00000080L
#define GCVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK                                                            0x00000100L
#define GCVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00000200L
#define GCVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00000400L
#define GCVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00000800L
#define GCVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00001000L
#define GCVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00002000L
#define GCVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00004000L
#define GCVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00008000L
#define GCVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00010000L
#define GCVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00020000L
#define GCVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00040000L
#define GCVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00080000L
#define GCVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00100000L
#define GCVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00200000L
#define GCVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x00400000L
//GCVM_CONTEXT9_CNTL
#define GCVM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT                                                             0x0
#define GCVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                           0x1
#define GCVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                      0x3
#define GCVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                     0x7
#define GCVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT                                                          0x8
#define GCVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x9
#define GCVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xa
#define GCVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xb
#define GCVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xc
#define GCVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xd
#define GCVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xe
#define GCVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xf
#define GCVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x10
#define GCVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x11
#define GCVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x12
#define GCVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x13
#define GCVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x14
#define GCVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x15
#define GCVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x16
#define GCVM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK                                                               0x00000001L
#define GCVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK                                                             0x00000006L
#define GCVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                        0x00000078L
#define GCVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                       0x00000080L
#define GCVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK                                                            0x00000100L
#define GCVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00000200L
#define GCVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00000400L
#define GCVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00000800L
#define GCVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00001000L
#define GCVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00002000L
#define GCVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00004000L
#define GCVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00008000L
#define GCVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00010000L
#define GCVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00020000L
#define GCVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00040000L
#define GCVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00080000L
#define GCVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00100000L
#define GCVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00200000L
#define GCVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x00400000L
//GCVM_CONTEXT10_CNTL
#define GCVM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT                                                            0x0
#define GCVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                          0x1
#define GCVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                     0x3
#define GCVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                    0x7
#define GCVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT                                                         0x8
#define GCVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x9
#define GCVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0xa
#define GCVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xb
#define GCVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xc
#define GCVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xd
#define GCVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xe
#define GCVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0xf
#define GCVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x10
#define GCVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x11
#define GCVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x12
#define GCVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x13
#define GCVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x14
#define GCVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0x15
#define GCVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0x16
#define GCVM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK                                                              0x00000001L
#define GCVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK                                                            0x00000006L
#define GCVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                       0x00000078L
#define GCVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                      0x00000080L
#define GCVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK                                                           0x00000100L
#define GCVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00000200L
#define GCVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00000400L
#define GCVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000800L
#define GCVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00001000L
#define GCVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00002000L
#define GCVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00004000L
#define GCVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00008000L
#define GCVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00010000L
#define GCVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00020000L
#define GCVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00040000L
#define GCVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00080000L
#define GCVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00100000L
#define GCVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00200000L
#define GCVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00400000L
//GCVM_CONTEXT11_CNTL
#define GCVM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT                                                            0x0
#define GCVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                          0x1
#define GCVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                     0x3
#define GCVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                    0x7
#define GCVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT                                                         0x8
#define GCVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x9
#define GCVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0xa
#define GCVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xb
#define GCVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xc
#define GCVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xd
#define GCVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xe
#define GCVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0xf
#define GCVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x10
#define GCVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x11
#define GCVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x12
#define GCVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x13
#define GCVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x14
#define GCVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0x15
#define GCVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0x16
#define GCVM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK                                                              0x00000001L
#define GCVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK                                                            0x00000006L
#define GCVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                       0x00000078L
#define GCVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                      0x00000080L
#define GCVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK                                                           0x00000100L
#define GCVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00000200L
#define GCVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00000400L
#define GCVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000800L
#define GCVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00001000L
#define GCVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00002000L
#define GCVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00004000L
#define GCVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00008000L
#define GCVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00010000L
#define GCVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00020000L
#define GCVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00040000L
#define GCVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00080000L
#define GCVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00100000L
#define GCVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00200000L
#define GCVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00400000L
//GCVM_CONTEXT12_CNTL
#define GCVM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT                                                            0x0
#define GCVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                          0x1
#define GCVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                     0x3
#define GCVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                    0x7
#define GCVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT                                                         0x8
#define GCVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x9
#define GCVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0xa
#define GCVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xb
#define GCVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xc
#define GCVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xd
#define GCVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xe
#define GCVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0xf
#define GCVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x10
#define GCVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x11
#define GCVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x12
#define GCVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x13
#define GCVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x14
#define GCVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0x15
#define GCVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0x16
#define GCVM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK                                                              0x00000001L
#define GCVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK                                                            0x00000006L
#define GCVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                       0x00000078L
#define GCVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                      0x00000080L
#define GCVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK                                                           0x00000100L
#define GCVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00000200L
#define GCVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00000400L
#define GCVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000800L
#define GCVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00001000L
#define GCVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00002000L
#define GCVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00004000L
#define GCVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00008000L
#define GCVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00010000L
#define GCVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00020000L
#define GCVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00040000L
#define GCVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00080000L
#define GCVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00100000L
#define GCVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00200000L
#define GCVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00400000L
//GCVM_CONTEXT13_CNTL
#define GCVM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT                                                            0x0
#define GCVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                          0x1
#define GCVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                     0x3
#define GCVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                    0x7
#define GCVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT                                                         0x8
#define GCVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x9
#define GCVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0xa
#define GCVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xb
#define GCVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xc
#define GCVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xd
#define GCVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xe
#define GCVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0xf
#define GCVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x10
#define GCVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x11
#define GCVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x12
#define GCVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x13
#define GCVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x14
#define GCVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0x15
#define GCVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0x16
#define GCVM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK                                                              0x00000001L
#define GCVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK                                                            0x00000006L
#define GCVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                       0x00000078L
#define GCVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                      0x00000080L
#define GCVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK                                                           0x00000100L
#define GCVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00000200L
#define GCVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00000400L
#define GCVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000800L
#define GCVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00001000L
#define GCVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00002000L
#define GCVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00004000L
#define GCVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00008000L
#define GCVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00010000L
#define GCVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00020000L
#define GCVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00040000L
#define GCVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00080000L
#define GCVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00100000L
#define GCVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00200000L
#define GCVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00400000L
//GCVM_CONTEXT14_CNTL
#define GCVM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT                                                            0x0
#define GCVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                          0x1
#define GCVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                     0x3
#define GCVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                    0x7
#define GCVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT                                                         0x8
#define GCVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x9
#define GCVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0xa
#define GCVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xb
#define GCVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xc
#define GCVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xd
#define GCVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xe
#define GCVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0xf
#define GCVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x10
#define GCVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x11
#define GCVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x12
#define GCVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x13
#define GCVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x14
#define GCVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0x15
#define GCVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0x16
#define GCVM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK                                                              0x00000001L
#define GCVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK                                                            0x00000006L
#define GCVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                       0x00000078L
#define GCVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                      0x00000080L
#define GCVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK                                                           0x00000100L
#define GCVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00000200L
#define GCVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00000400L
#define GCVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000800L
#define GCVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00001000L
#define GCVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00002000L
#define GCVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00004000L
#define GCVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00008000L
#define GCVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00010000L
#define GCVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00020000L
#define GCVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00040000L
#define GCVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00080000L
#define GCVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00100000L
#define GCVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00200000L
#define GCVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00400000L
//GCVM_CONTEXT15_CNTL
#define GCVM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT                                                            0x0
#define GCVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                          0x1
#define GCVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                     0x3
#define GCVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                    0x7
#define GCVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT                                                         0x8
#define GCVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x9
#define GCVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0xa
#define GCVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xb
#define GCVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xc
#define GCVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xd
#define GCVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xe
#define GCVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0xf
#define GCVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x10
#define GCVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x11
#define GCVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x12
#define GCVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x13
#define GCVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x14
#define GCVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0x15
#define GCVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0x16
#define GCVM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK                                                              0x00000001L
#define GCVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK                                                            0x00000006L
#define GCVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                       0x00000078L
#define GCVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                      0x00000080L
#define GCVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK                                                           0x00000100L
#define GCVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00000200L
#define GCVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00000400L
#define GCVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000800L
#define GCVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00001000L
#define GCVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00002000L
#define GCVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00004000L
#define GCVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00008000L
#define GCVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00010000L
#define GCVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00020000L
#define GCVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00040000L
#define GCVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00080000L
#define GCVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00100000L
#define GCVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00200000L
#define GCVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00400000L
//GCVM_CONTEXTS_DISABLE
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT                                                       0x0
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT                                                       0x1
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT                                                       0x2
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT                                                       0x3
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT                                                       0x4
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT                                                       0x5
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT                                                       0x6
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT                                                       0x7
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT                                                       0x8
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT                                                       0x9
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT                                                      0xa
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT                                                      0xb
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT                                                      0xc
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT                                                      0xd
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT                                                      0xe
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT                                                      0xf
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK                                                         0x00000001L
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK                                                         0x00000002L
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK                                                         0x00000004L
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK                                                         0x00000008L
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK                                                         0x00000010L
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK                                                         0x00000020L
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK                                                         0x00000040L
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK                                                         0x00000080L
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK                                                         0x00000100L
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK                                                         0x00000200L
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK                                                        0x00000400L
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK                                                        0x00000800L
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK                                                        0x00001000L
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK                                                        0x00002000L
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK                                                        0x00004000L
#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK                                                        0x00008000L
//GCVM_INVALIDATE_ENG0_SEM
#define GCVM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT                                                            0x0
#define GCVM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK                                                              0x00000001L
//GCVM_INVALIDATE_ENG1_SEM
#define GCVM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT                                                            0x0
#define GCVM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK                                                              0x00000001L
//GCVM_INVALIDATE_ENG2_SEM
#define GCVM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT                                                            0x0
#define GCVM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK                                                              0x00000001L
//GCVM_INVALIDATE_ENG3_SEM
#define GCVM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT                                                            0x0
#define GCVM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK                                                              0x00000001L
//GCVM_INVALIDATE_ENG4_SEM
#define GCVM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT                                                            0x0
#define GCVM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK                                                              0x00000001L
//GCVM_INVALIDATE_ENG5_SEM
#define GCVM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT                                                            0x0
#define GCVM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK                                                              0x00000001L
//GCVM_INVALIDATE_ENG6_SEM
#define GCVM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT                                                            0x0
#define GCVM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK                                                              0x00000001L
//GCVM_INVALIDATE_ENG7_SEM
#define GCVM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT                                                            0x0
#define GCVM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK                                                              0x00000001L
//GCVM_INVALIDATE_ENG8_SEM
#define GCVM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT                                                            0x0
#define GCVM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK                                                              0x00000001L
//GCVM_INVALIDATE_ENG9_SEM
#define GCVM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT                                                            0x0
#define GCVM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK                                                              0x00000001L
//GCVM_INVALIDATE_ENG10_SEM
#define GCVM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT                                                           0x0
#define GCVM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK                                                             0x00000001L
//GCVM_INVALIDATE_ENG11_SEM
#define GCVM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT                                                           0x0
#define GCVM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK                                                             0x00000001L
//GCVM_INVALIDATE_ENG12_SEM
#define GCVM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT                                                           0x0
#define GCVM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK                                                             0x00000001L
//GCVM_INVALIDATE_ENG13_SEM
#define GCVM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT                                                           0x0
#define GCVM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK                                                             0x00000001L
//GCVM_INVALIDATE_ENG14_SEM
#define GCVM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT                                                           0x0
#define GCVM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK                                                             0x00000001L
//GCVM_INVALIDATE_ENG15_SEM
#define GCVM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT                                                           0x0
#define GCVM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK                                                             0x00000001L
//GCVM_INVALIDATE_ENG16_SEM
#define GCVM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT                                                           0x0
#define GCVM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK                                                             0x00000001L
//GCVM_INVALIDATE_ENG17_SEM
#define GCVM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT                                                           0x0
#define GCVM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK                                                             0x00000001L
//GCVM_INVALIDATE_ENG0_REQ
#define GCVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                              0x0
#define GCVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT                                                           0x10
#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT                                                   0x13
#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT                                                   0x14
#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT                                                   0x15
#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT                                                   0x16
#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT                                                   0x17
#define GCVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                   0x18
#define GCVM_INVALIDATE_ENG0_REQ__LOG_REQUEST__SHIFT                                                          0x19
#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                             0x1a
#define GCVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                0x0000FFFFL
#define GCVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK                                                             0x00070000L
#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK                                                     0x00080000L
#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK                                                     0x00100000L
#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK                                                     0x00200000L
#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK                                                     0x00400000L
#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK                                                     0x00800000L
#define GCVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                     0x01000000L
#define GCVM_INVALIDATE_ENG0_REQ__LOG_REQUEST_MASK                                                            0x02000000L
#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                               0x04000000L
//GCVM_INVALIDATE_ENG1_REQ
#define GCVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                              0x0
#define GCVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT                                                           0x10
#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT                                                   0x13
#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT                                                   0x14
#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT                                                   0x15
#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT                                                   0x16
#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT                                                   0x17
#define GCVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                   0x18
#define GCVM_INVALIDATE_ENG1_REQ__LOG_REQUEST__SHIFT                                                          0x19
#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                             0x1a
#define GCVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                0x0000FFFFL
#define GCVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK                                                             0x00070000L
#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK                                                     0x00080000L
#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK                                                     0x00100000L
#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK                                                     0x00200000L
#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK                                                     0x00400000L
#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK                                                     0x00800000L
#define GCVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                     0x01000000L
#define GCVM_INVALIDATE_ENG1_REQ__LOG_REQUEST_MASK                                                            0x02000000L
#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                               0x04000000L
//GCVM_INVALIDATE_ENG2_REQ
#define GCVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                              0x0
#define GCVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT                                                           0x10
#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT                                                   0x13
#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT                                                   0x14
#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT                                                   0x15
#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT                                                   0x16
#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT                                                   0x17
#define GCVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                   0x18
#define GCVM_INVALIDATE_ENG2_REQ__LOG_REQUEST__SHIFT                                                          0x19
#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                             0x1a
#define GCVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                0x0000FFFFL
#define GCVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK                                                             0x00070000L
#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK                                                     0x00080000L
#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK                                                     0x00100000L
#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK                                                     0x00200000L
#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK                                                     0x00400000L
#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK                                                     0x00800000L
#define GCVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                     0x01000000L
#define GCVM_INVALIDATE_ENG2_REQ__LOG_REQUEST_MASK                                                            0x02000000L
#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                               0x04000000L
//GCVM_INVALIDATE_ENG3_REQ
#define GCVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                              0x0
#define GCVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT                                                           0x10
#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT                                                   0x13
#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT                                                   0x14
#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT                                                   0x15
#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT                                                   0x16
#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT                                                   0x17
#define GCVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                   0x18
#define GCVM_INVALIDATE_ENG3_REQ__LOG_REQUEST__SHIFT                                                          0x19
#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                             0x1a
#define GCVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                0x0000FFFFL
#define GCVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK                                                             0x00070000L
#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK                                                     0x00080000L
#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK                                                     0x00100000L
#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK                                                     0x00200000L
#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK                                                     0x00400000L
#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK                                                     0x00800000L
#define GCVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                     0x01000000L
#define GCVM_INVALIDATE_ENG3_REQ__LOG_REQUEST_MASK                                                            0x02000000L
#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                               0x04000000L
//GCVM_INVALIDATE_ENG4_REQ
#define GCVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                              0x0
#define GCVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT                                                           0x10
#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT                                                   0x13
#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT                                                   0x14
#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT                                                   0x15
#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT                                                   0x16
#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT                                                   0x17
#define GCVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                   0x18
#define GCVM_INVALIDATE_ENG4_REQ__LOG_REQUEST__SHIFT                                                          0x19
#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                             0x1a
#define GCVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                0x0000FFFFL
#define GCVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK                                                             0x00070000L
#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK                                                     0x00080000L
#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK                                                     0x00100000L
#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK                                                     0x00200000L
#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK                                                     0x00400000L
#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK                                                     0x00800000L
#define GCVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                     0x01000000L
#define GCVM_INVALIDATE_ENG4_REQ__LOG_REQUEST_MASK                                                            0x02000000L
#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                               0x04000000L
//GCVM_INVALIDATE_ENG5_REQ
#define GCVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                              0x0
#define GCVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT                                                           0x10
#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT                                                   0x13
#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT                                                   0x14
#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT                                                   0x15
#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT                                                   0x16
#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT                                                   0x17
#define GCVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                   0x18
#define GCVM_INVALIDATE_ENG5_REQ__LOG_REQUEST__SHIFT                                                          0x19
#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                             0x1a
#define GCVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                0x0000FFFFL
#define GCVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK                                                             0x00070000L
#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK                                                     0x00080000L
#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK                                                     0x00100000L
#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK                                                     0x00200000L
#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK                                                     0x00400000L
#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK                                                     0x00800000L
#define GCVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                     0x01000000L
#define GCVM_INVALIDATE_ENG5_REQ__LOG_REQUEST_MASK                                                            0x02000000L
#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                               0x04000000L
//GCVM_INVALIDATE_ENG6_REQ
#define GCVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                              0x0
#define GCVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT                                                           0x10
#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT                                                   0x13
#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT                                                   0x14
#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT                                                   0x15
#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT                                                   0x16
#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT                                                   0x17
#define GCVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                   0x18
#define GCVM_INVALIDATE_ENG6_REQ__LOG_REQUEST__SHIFT                                                          0x19
#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                             0x1a
#define GCVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                0x0000FFFFL
#define GCVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK                                                             0x00070000L
#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK                                                     0x00080000L
#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK                                                     0x00100000L
#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK                                                     0x00200000L
#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK                                                     0x00400000L
#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK                                                     0x00800000L
#define GCVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                     0x01000000L
#define GCVM_INVALIDATE_ENG6_REQ__LOG_REQUEST_MASK                                                            0x02000000L
#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                               0x04000000L
//GCVM_INVALIDATE_ENG7_REQ
#define GCVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                              0x0
#define GCVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT                                                           0x10
#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT                                                   0x13
#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT                                                   0x14
#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT                                                   0x15
#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT                                                   0x16
#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT                                                   0x17
#define GCVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                   0x18
#define GCVM_INVALIDATE_ENG7_REQ__LOG_REQUEST__SHIFT                                                          0x19
#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                             0x1a
#define GCVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                0x0000FFFFL
#define GCVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK                                                             0x00070000L
#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK                                                     0x00080000L
#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK                                                     0x00100000L
#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK                                                     0x00200000L
#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK                                                     0x00400000L
#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK                                                     0x00800000L
#define GCVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                     0x01000000L
#define GCVM_INVALIDATE_ENG7_REQ__LOG_REQUEST_MASK                                                            0x02000000L
#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                               0x04000000L
//GCVM_INVALIDATE_ENG8_REQ
#define GCVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                              0x0
#define GCVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT                                                           0x10
#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT                                                   0x13
#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT                                                   0x14
#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT                                                   0x15
#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT                                                   0x16
#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT                                                   0x17
#define GCVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                   0x18
#define GCVM_INVALIDATE_ENG8_REQ__LOG_REQUEST__SHIFT                                                          0x19
#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                             0x1a
#define GCVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                0x0000FFFFL
#define GCVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK                                                             0x00070000L
#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK                                                     0x00080000L
#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK                                                     0x00100000L
#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK                                                     0x00200000L
#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK                                                     0x00400000L
#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK                                                     0x00800000L
#define GCVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                     0x01000000L
#define GCVM_INVALIDATE_ENG8_REQ__LOG_REQUEST_MASK                                                            0x02000000L
#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                               0x04000000L
//GCVM_INVALIDATE_ENG9_REQ
#define GCVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                              0x0
#define GCVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT                                                           0x10
#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT                                                   0x13
#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT                                                   0x14
#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT                                                   0x15
#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT                                                   0x16
#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT                                                   0x17
#define GCVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                   0x18
#define GCVM_INVALIDATE_ENG9_REQ__LOG_REQUEST__SHIFT                                                          0x19
#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                             0x1a
#define GCVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                0x0000FFFFL
#define GCVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK                                                             0x00070000L
#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK                                                     0x00080000L
#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK                                                     0x00100000L
#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK                                                     0x00200000L
#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK                                                     0x00400000L
#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK                                                     0x00800000L
#define GCVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                     0x01000000L
#define GCVM_INVALIDATE_ENG9_REQ__LOG_REQUEST_MASK                                                            0x02000000L
#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                               0x04000000L
//GCVM_INVALIDATE_ENG10_REQ
#define GCVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                             0x0
#define GCVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT                                                          0x10
#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT                                                  0x13
#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT                                                  0x14
#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT                                                  0x15
#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT                                                  0x16
#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT                                                  0x17
#define GCVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                  0x18
#define GCVM_INVALIDATE_ENG10_REQ__LOG_REQUEST__SHIFT                                                         0x19
#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                            0x1a
#define GCVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK                                               0x0000FFFFL
#define GCVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK                                                            0x00070000L
#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK                                                    0x00080000L
#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK                                                    0x00100000L
#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK                                                    0x00200000L
#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK                                                    0x00400000L
#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK                                                    0x00800000L
#define GCVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                    0x01000000L
#define GCVM_INVALIDATE_ENG10_REQ__LOG_REQUEST_MASK                                                           0x02000000L
#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                              0x04000000L
//GCVM_INVALIDATE_ENG11_REQ
#define GCVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                             0x0
#define GCVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT                                                          0x10
#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT                                                  0x13
#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT                                                  0x14
#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT                                                  0x15
#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT                                                  0x16
#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT                                                  0x17
#define GCVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                  0x18
#define GCVM_INVALIDATE_ENG11_REQ__LOG_REQUEST__SHIFT                                                         0x19
#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                            0x1a
#define GCVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK                                               0x0000FFFFL
#define GCVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK                                                            0x00070000L
#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK                                                    0x00080000L
#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK                                                    0x00100000L
#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK                                                    0x00200000L
#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK                                                    0x00400000L
#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK                                                    0x00800000L
#define GCVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                    0x01000000L
#define GCVM_INVALIDATE_ENG11_REQ__LOG_REQUEST_MASK                                                           0x02000000L
#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                              0x04000000L
//GCVM_INVALIDATE_ENG12_REQ
#define GCVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                             0x0
#define GCVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT                                                          0x10
#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT                                                  0x13
#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT                                                  0x14
#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT                                                  0x15
#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT                                                  0x16
#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT                                                  0x17
#define GCVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                  0x18
#define GCVM_INVALIDATE_ENG12_REQ__LOG_REQUEST__SHIFT                                                         0x19
#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                            0x1a
#define GCVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK                                               0x0000FFFFL
#define GCVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK                                                            0x00070000L
#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK                                                    0x00080000L
#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK                                                    0x00100000L
#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK                                                    0x00200000L
#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK                                                    0x00400000L
#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK                                                    0x00800000L
#define GCVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                    0x01000000L
#define GCVM_INVALIDATE_ENG12_REQ__LOG_REQUEST_MASK                                                           0x02000000L
#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                              0x04000000L
//GCVM_INVALIDATE_ENG13_REQ
#define GCVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                             0x0
#define GCVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT                                                          0x10
#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT                                                  0x13
#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT                                                  0x14
#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT                                                  0x15
#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT                                                  0x16
#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT                                                  0x17
#define GCVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                  0x18
#define GCVM_INVALIDATE_ENG13_REQ__LOG_REQUEST__SHIFT                                                         0x19
#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                            0x1a
#define GCVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK                                               0x0000FFFFL
#define GCVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK                                                            0x00070000L
#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK                                                    0x00080000L
#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK                                                    0x00100000L
#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK                                                    0x00200000L
#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK                                                    0x00400000L
#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK                                                    0x00800000L
#define GCVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                    0x01000000L
#define GCVM_INVALIDATE_ENG13_REQ__LOG_REQUEST_MASK                                                           0x02000000L
#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                              0x04000000L
//GCVM_INVALIDATE_ENG14_REQ
#define GCVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                             0x0
#define GCVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT                                                          0x10
#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT                                                  0x13
#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT                                                  0x14
#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT                                                  0x15
#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT                                                  0x16
#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT                                                  0x17
#define GCVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                  0x18
#define GCVM_INVALIDATE_ENG14_REQ__LOG_REQUEST__SHIFT                                                         0x19
#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                            0x1a
#define GCVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK                                               0x0000FFFFL
#define GCVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK                                                            0x00070000L
#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK                                                    0x00080000L
#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK                                                    0x00100000L
#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK                                                    0x00200000L
#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK                                                    0x00400000L
#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK                                                    0x00800000L
#define GCVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                    0x01000000L
#define GCVM_INVALIDATE_ENG14_REQ__LOG_REQUEST_MASK                                                           0x02000000L
#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                              0x04000000L
//GCVM_INVALIDATE_ENG15_REQ
#define GCVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                             0x0
#define GCVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT                                                          0x10
#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT                                                  0x13
#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT                                                  0x14
#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT                                                  0x15
#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT                                                  0x16
#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT                                                  0x17
#define GCVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                  0x18
#define GCVM_INVALIDATE_ENG15_REQ__LOG_REQUEST__SHIFT                                                         0x19
#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                            0x1a
#define GCVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK                                               0x0000FFFFL
#define GCVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK                                                            0x00070000L
#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK                                                    0x00080000L
#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK                                                    0x00100000L
#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK                                                    0x00200000L
#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK                                                    0x00400000L
#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK                                                    0x00800000L
#define GCVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                    0x01000000L
#define GCVM_INVALIDATE_ENG15_REQ__LOG_REQUEST_MASK                                                           0x02000000L
#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                              0x04000000L
//GCVM_INVALIDATE_ENG16_REQ
#define GCVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                             0x0
#define GCVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT                                                          0x10
#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT                                                  0x13
#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT                                                  0x14
#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT                                                  0x15
#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT                                                  0x16
#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT                                                  0x17
#define GCVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                  0x18
#define GCVM_INVALIDATE_ENG16_REQ__LOG_REQUEST__SHIFT                                                         0x19
#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                            0x1a
#define GCVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK                                               0x0000FFFFL
#define GCVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK                                                            0x00070000L
#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK                                                    0x00080000L
#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK                                                    0x00100000L
#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK                                                    0x00200000L
#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK                                                    0x00400000L
#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK                                                    0x00800000L
#define GCVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                    0x01000000L
#define GCVM_INVALIDATE_ENG16_REQ__LOG_REQUEST_MASK                                                           0x02000000L
#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                              0x04000000L
//GCVM_INVALIDATE_ENG17_REQ
#define GCVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                             0x0
#define GCVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT                                                          0x10
#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT                                                  0x13
#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT                                                  0x14
#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT                                                  0x15
#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT                                                  0x16
#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT                                                  0x17
#define GCVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                  0x18
#define GCVM_INVALIDATE_ENG17_REQ__LOG_REQUEST__SHIFT                                                         0x19
#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                            0x1a
#define GCVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK                                               0x0000FFFFL
#define GCVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK                                                            0x00070000L
#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK                                                    0x00080000L
#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK                                                    0x00100000L
#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK                                                    0x00200000L
#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK                                                    0x00400000L
#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK                                                    0x00800000L
#define GCVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                    0x01000000L
#define GCVM_INVALIDATE_ENG17_REQ__LOG_REQUEST_MASK                                                           0x02000000L
#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                              0x04000000L
//GCVM_INVALIDATE_ENG0_ACK
#define GCVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                              0x0
#define GCVM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT                                                            0x10
#define GCVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                0x0000FFFFL
#define GCVM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK                                                              0x00010000L
//GCVM_INVALIDATE_ENG1_ACK
#define GCVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                              0x0
#define GCVM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT                                                            0x10
#define GCVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                0x0000FFFFL
#define GCVM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK                                                              0x00010000L
//GCVM_INVALIDATE_ENG2_ACK
#define GCVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                              0x0
#define GCVM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT                                                            0x10
#define GCVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                0x0000FFFFL
#define GCVM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK                                                              0x00010000L
//GCVM_INVALIDATE_ENG3_ACK
#define GCVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                              0x0
#define GCVM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT                                                            0x10
#define GCVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                0x0000FFFFL
#define GCVM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK                                                              0x00010000L
//GCVM_INVALIDATE_ENG4_ACK
#define GCVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                              0x0
#define GCVM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT                                                            0x10
#define GCVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                0x0000FFFFL
#define GCVM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK                                                              0x00010000L
//GCVM_INVALIDATE_ENG5_ACK
#define GCVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                              0x0
#define GCVM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT                                                            0x10
#define GCVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                0x0000FFFFL
#define GCVM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK                                                              0x00010000L
//GCVM_INVALIDATE_ENG6_ACK
#define GCVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                              0x0
#define GCVM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT                                                            0x10
#define GCVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                0x0000FFFFL
#define GCVM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK                                                              0x00010000L
//GCVM_INVALIDATE_ENG7_ACK
#define GCVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                              0x0
#define GCVM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT                                                            0x10
#define GCVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                0x0000FFFFL
#define GCVM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK                                                              0x00010000L
//GCVM_INVALIDATE_ENG8_ACK
#define GCVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                              0x0
#define GCVM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT                                                            0x10
#define GCVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                0x0000FFFFL
#define GCVM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK                                                              0x00010000L
//GCVM_INVALIDATE_ENG9_ACK
#define GCVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                              0x0
#define GCVM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT                                                            0x10
#define GCVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                0x0000FFFFL
#define GCVM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK                                                              0x00010000L
//GCVM_INVALIDATE_ENG10_ACK
#define GCVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                             0x0
#define GCVM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT                                                           0x10
#define GCVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK                                               0x0000FFFFL
#define GCVM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK                                                             0x00010000L
//GCVM_INVALIDATE_ENG11_ACK
#define GCVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                             0x0
#define GCVM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT                                                           0x10
#define GCVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK                                               0x0000FFFFL
#define GCVM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK                                                             0x00010000L
//GCVM_INVALIDATE_ENG12_ACK
#define GCVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                             0x0
#define GCVM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT                                                           0x10
#define GCVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK                                               0x0000FFFFL
#define GCVM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK                                                             0x00010000L
//GCVM_INVALIDATE_ENG13_ACK
#define GCVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                             0x0
#define GCVM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT                                                           0x10
#define GCVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK                                               0x0000FFFFL
#define GCVM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK                                                             0x00010000L
//GCVM_INVALIDATE_ENG14_ACK
#define GCVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                             0x0
#define GCVM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT                                                           0x10
#define GCVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK                                               0x0000FFFFL
#define GCVM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK                                                             0x00010000L
//GCVM_INVALIDATE_ENG15_ACK
#define GCVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                             0x0
#define GCVM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT                                                           0x10
#define GCVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK                                               0x0000FFFFL
#define GCVM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK                                                             0x00010000L
//GCVM_INVALIDATE_ENG16_ACK
#define GCVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                             0x0
#define GCVM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT                                                           0x10
#define GCVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK                                               0x0000FFFFL
#define GCVM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK                                                             0x00010000L
//GCVM_INVALIDATE_ENG17_ACK
#define GCVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                             0x0
#define GCVM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT                                                           0x10
#define GCVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK                                               0x0000FFFFL
#define GCVM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK                                                             0x00010000L
//GCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32
#define GCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT                                                    0x0
#define GCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                0x1
#define GCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK                                                      0x00000001L
#define GCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                  0xFFFFFFFEL
//GCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32
#define GCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                 0x0
#define GCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                   0x0000001FL
//GCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32
#define GCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT                                                    0x0
#define GCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                0x1
#define GCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK                                                      0x00000001L
#define GCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                  0xFFFFFFFEL
//GCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32
#define GCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                 0x0
#define GCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                   0x0000001FL
//GCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32
#define GCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT                                                    0x0
#define GCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                0x1
#define GCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK                                                      0x00000001L
#define GCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                  0xFFFFFFFEL
//GCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32
#define GCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                 0x0
#define GCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                   0x0000001FL
//GCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32
#define GCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT                                                    0x0
#define GCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                0x1
#define GCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK                                                      0x00000001L
#define GCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                  0xFFFFFFFEL
//GCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32
#define GCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                 0x0
#define GCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                   0x0000001FL
//GCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32
#define GCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT                                                    0x0
#define GCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                0x1
#define GCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK                                                      0x00000001L
#define GCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                  0xFFFFFFFEL
//GCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32
#define GCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                 0x0
#define GCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                   0x0000001FL
//GCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32
#define GCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT                                                    0x0
#define GCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                0x1
#define GCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK                                                      0x00000001L
#define GCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                  0xFFFFFFFEL
//GCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32
#define GCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                 0x0
#define GCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                   0x0000001FL
//GCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32
#define GCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT                                                    0x0
#define GCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                0x1
#define GCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK                                                      0x00000001L
#define GCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                  0xFFFFFFFEL
//GCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32
#define GCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                 0x0
#define GCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                   0x0000001FL
//GCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32
#define GCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT                                                    0x0
#define GCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                0x1
#define GCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK                                                      0x00000001L
#define GCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                  0xFFFFFFFEL
//GCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32
#define GCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                 0x0
#define GCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                   0x0000001FL
//GCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32
#define GCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT                                                    0x0
#define GCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                0x1
#define GCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK                                                      0x00000001L
#define GCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                  0xFFFFFFFEL
//GCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32
#define GCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                 0x0
#define GCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                   0x0000001FL
//GCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32
#define GCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT                                                    0x0
#define GCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                0x1
#define GCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK                                                      0x00000001L
#define GCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                  0xFFFFFFFEL
//GCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32
#define GCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                 0x0
#define GCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                   0x0000001FL
//GCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32
#define GCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT                                                   0x0
#define GCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                               0x1
#define GCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK                                                     0x00000001L
#define GCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                 0xFFFFFFFEL
//GCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32
#define GCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                0x0
#define GCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                  0x0000001FL
//GCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32
#define GCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT                                                   0x0
#define GCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                               0x1
#define GCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK                                                     0x00000001L
#define GCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                 0xFFFFFFFEL
//GCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32
#define GCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                0x0
#define GCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                  0x0000001FL
//GCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32
#define GCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT                                                   0x0
#define GCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                               0x1
#define GCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK                                                     0x00000001L
#define GCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                 0xFFFFFFFEL
//GCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32
#define GCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                0x0
#define GCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                  0x0000001FL
//GCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32
#define GCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT                                                   0x0
#define GCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                               0x1
#define GCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK                                                     0x00000001L
#define GCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                 0xFFFFFFFEL
//GCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32
#define GCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                0x0
#define GCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                  0x0000001FL
//GCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32
#define GCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT                                                   0x0
#define GCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                               0x1
#define GCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK                                                     0x00000001L
#define GCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                 0xFFFFFFFEL
//GCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32
#define GCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                0x0
#define GCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                  0x0000001FL
//GCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32
#define GCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT                                                   0x0
#define GCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                               0x1
#define GCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK                                                     0x00000001L
#define GCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                 0xFFFFFFFEL
//GCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32
#define GCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                0x0
#define GCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                  0x0000001FL
//GCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32
#define GCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT                                                   0x0
#define GCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                               0x1
#define GCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK                                                     0x00000001L
#define GCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                 0xFFFFFFFEL
//GCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32
#define GCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                0x0
#define GCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                  0x0000001FL
//GCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32
#define GCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT                                                   0x0
#define GCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                               0x1
#define GCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK                                                     0x00000001L
#define GCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                 0xFFFFFFFEL
//GCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32
#define GCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                0x0
#define GCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                  0x0000001FL
//GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32
#define GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                             0x0
#define GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                               0xFFFFFFFFL
//GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32
#define GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                             0x0
#define GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                               0xFFFFFFFFL
//GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32
#define GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                             0x0
#define GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                               0xFFFFFFFFL
//GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32
#define GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                             0x0
#define GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                               0xFFFFFFFFL
//GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32
#define GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                             0x0
#define GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                               0xFFFFFFFFL
//GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32
#define GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                             0x0
#define GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                               0xFFFFFFFFL
//GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32
#define GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                             0x0
#define GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                               0xFFFFFFFFL
//GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32
#define GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                             0x0
#define GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                               0xFFFFFFFFL
//GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32
#define GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                             0x0
#define GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                               0xFFFFFFFFL
//GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32
#define GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                             0x0
#define GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                               0xFFFFFFFFL
//GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32
#define GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                             0x0
#define GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                               0xFFFFFFFFL
//GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32
#define GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                             0x0
#define GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                               0xFFFFFFFFL
//GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32
#define GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                             0x0
#define GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                               0xFFFFFFFFL
//GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32
#define GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                             0x0
#define GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                               0xFFFFFFFFL
//GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32
#define GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                             0x0
#define GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                               0xFFFFFFFFL
//GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32
#define GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                             0x0
#define GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                               0xFFFFFFFFL
//GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32
#define GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                             0x0
#define GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                               0xFFFFFFFFL
//GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32
#define GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                             0x0
#define GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                               0xFFFFFFFFL
//GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32
#define GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                             0x0
#define GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                               0xFFFFFFFFL
//GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32
#define GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                             0x0
#define GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                               0xFFFFFFFFL
//GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32
#define GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                            0x0
#define GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                              0xFFFFFFFFL
//GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32
#define GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                            0x0
#define GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                              0xFFFFFFFFL
//GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32
#define GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                            0x0
#define GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                              0xFFFFFFFFL
//GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32
#define GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                            0x0
#define GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                              0xFFFFFFFFL
//GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32
#define GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                            0x0
#define GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                              0xFFFFFFFFL
//GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32
#define GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                            0x0
#define GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                              0xFFFFFFFFL
//GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32
#define GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                            0x0
#define GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                              0xFFFFFFFFL
//GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32
#define GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                            0x0
#define GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                              0xFFFFFFFFL
//GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32
#define GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                            0x0
#define GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                              0xFFFFFFFFL
//GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32
#define GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                            0x0
#define GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                              0xFFFFFFFFL
//GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32
#define GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                            0x0
#define GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                              0xFFFFFFFFL
//GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32
#define GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                            0x0
#define GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                              0xFFFFFFFFL
//GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32
#define GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                             0x0
#define GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                               0xFFFFFFFFL
//GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32
#define GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                              0x0
#define GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                0x0000000FL
//GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32
#define GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                             0x0
#define GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                               0xFFFFFFFFL
//GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32
#define GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                              0x0
#define GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                0x0000000FL
//GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32
#define GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                             0x0
#define GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                               0xFFFFFFFFL
//GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32
#define GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                              0x0
#define GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                0x0000000FL
//GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32
#define GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                             0x0
#define GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                               0xFFFFFFFFL
//GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32
#define GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                              0x0
#define GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                0x0000000FL
//GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32
#define GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                             0x0
#define GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                               0xFFFFFFFFL
//GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32
#define GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                              0x0
#define GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                0x0000000FL
//GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32
#define GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                             0x0
#define GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                               0xFFFFFFFFL
//GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32
#define GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                              0x0
#define GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                0x0000000FL
//GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32
#define GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                             0x0
#define GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                               0xFFFFFFFFL
//GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32
#define GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                              0x0
#define GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                0x0000000FL
//GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32
#define GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                             0x0
#define GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                               0xFFFFFFFFL
//GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32
#define GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                              0x0
#define GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                0x0000000FL
//GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32
#define GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                             0x0
#define GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                               0xFFFFFFFFL
//GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32
#define GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                              0x0
#define GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                0x0000000FL
//GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32
#define GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                             0x0
#define GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                               0xFFFFFFFFL
//GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32
#define GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                              0x0
#define GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                0x0000000FL
//GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32
#define GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                            0x0
#define GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                              0xFFFFFFFFL
//GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32
#define GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                             0x0
#define GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                               0x0000000FL
//GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32
#define GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                            0x0
#define GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                              0xFFFFFFFFL
//GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32
#define GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                             0x0
#define GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                               0x0000000FL
//GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32
#define GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                            0x0
#define GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                              0xFFFFFFFFL
//GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32
#define GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                             0x0
#define GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                               0x0000000FL
//GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32
#define GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                            0x0
#define GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                              0xFFFFFFFFL
//GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32
#define GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                             0x0
#define GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                               0x0000000FL
//GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32
#define GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                            0x0
#define GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                              0xFFFFFFFFL
//GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32
#define GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                             0x0
#define GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                               0x0000000FL
//GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32
#define GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                            0x0
#define GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                              0xFFFFFFFFL
//GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32
#define GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                             0x0
#define GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                               0x0000000FL
//GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32
#define GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
#define GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
//GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32
#define GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
#define GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
//GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32
#define GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
#define GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
//GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32
#define GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
#define GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
//GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32
#define GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
#define GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
//GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32
#define GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
#define GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
//GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32
#define GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
#define GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
//GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32
#define GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
#define GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
//GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32
#define GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
#define GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
//GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32
#define GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
#define GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
//GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32
#define GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
#define GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
//GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32
#define GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
#define GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
//GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32
#define GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
#define GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
//GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32
#define GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
#define GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
//GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32
#define GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
#define GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
//GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32
#define GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
#define GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
//GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32
#define GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
#define GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
//GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32
#define GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
#define GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
//GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32
#define GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
#define GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
//GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32
#define GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
#define GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
//GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32
#define GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                              0x0
#define GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                0xFFFFFFFFL
//GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32
#define GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                               0x0
#define GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                 0x0000000FL
//GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32
#define GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                              0x0
#define GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                0xFFFFFFFFL
//GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32
#define GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                               0x0
#define GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                 0x0000000FL
//GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32
#define GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                              0x0
#define GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                0xFFFFFFFFL
//GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32
#define GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                               0x0
#define GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                 0x0000000FL
//GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32
#define GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                              0x0
#define GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                0xFFFFFFFFL
//GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32
#define GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                               0x0
#define GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                 0x0000000FL
//GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32
#define GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                              0x0
#define GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                0xFFFFFFFFL
//GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32
#define GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                               0x0
#define GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                 0x0000000FL
//GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32
#define GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                              0x0
#define GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                0xFFFFFFFFL
//GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32
#define GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                               0x0
#define GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                 0x0000000FL
//GCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
#define GCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT                       0x0
#define GCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT                         0x5
#define GCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                                         0xa
#define GCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK                         0x0000001FL
#define GCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                           0x000003E0L
#define GCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                           0x0000FC00L
//GCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
#define GCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT              0x0
#define GCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT                0x5
#define GCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                                0xa
#define GCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK                0x0000001FL
#define GCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                  0x000003E0L
#define GCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                  0x0000FC00L
//GCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
#define GCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT              0x0
#define GCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT                0x5
#define GCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                                0xa
#define GCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK                0x0000001FL
#define GCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                  0x000003E0L
#define GCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                  0x0000FC00L
//GCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
#define GCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT              0x0
#define GCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT                0x5
#define GCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                                0xa
#define GCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK                0x0000001FL
#define GCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                  0x000003E0L
#define GCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                  0x0000FC00L
//GCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
#define GCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT              0x0
#define GCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT                0x5
#define GCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                                0xa
#define GCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK                0x0000001FL
#define GCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                  0x000003E0L
#define GCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                  0x0000FC00L
//GCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
#define GCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT              0x0
#define GCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT                0x5
#define GCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                                0xa
#define GCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK                0x0000001FL
#define GCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                  0x000003E0L
#define GCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                  0x0000FC00L
//GCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
#define GCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT              0x0
#define GCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT                0x5
#define GCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                                0xa
#define GCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK                0x0000001FL
#define GCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                  0x000003E0L
#define GCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                  0x0000FC00L
//GCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
#define GCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT              0x0
#define GCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT                0x5
#define GCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                                0xa
#define GCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK                0x0000001FL
#define GCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                  0x000003E0L
#define GCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                  0x0000FC00L
//GCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
#define GCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT              0x0
#define GCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT                0x5
#define GCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                                0xa
#define GCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK                0x0000001FL
#define GCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                  0x000003E0L
#define GCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                  0x0000FC00L
//GCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
#define GCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT              0x0
#define GCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT                0x5
#define GCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                                0xa
#define GCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK                0x0000001FL
#define GCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                  0x000003E0L
#define GCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                  0x0000FC00L
//GCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
#define GCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT              0x0
#define GCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT                0x5
#define GCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                                0xa
#define GCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK                0x0000001FL
#define GCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                  0x000003E0L
#define GCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                  0x0000FC00L
//GCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
#define GCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT             0x0
#define GCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT               0x5
#define GCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                               0xa
#define GCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK               0x0000001FL
#define GCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                 0x000003E0L
#define GCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                 0x0000FC00L
//GCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
#define GCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT             0x0
#define GCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT               0x5
#define GCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                               0xa
#define GCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK               0x0000001FL
#define GCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                 0x000003E0L
#define GCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                 0x0000FC00L
//GCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
#define GCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT             0x0
#define GCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT               0x5
#define GCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                               0xa
#define GCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK               0x0000001FL
#define GCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                 0x000003E0L
#define GCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                 0x0000FC00L
//GCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
#define GCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT             0x0
#define GCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT               0x5
#define GCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                               0xa
#define GCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK               0x0000001FL
#define GCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                 0x000003E0L
#define GCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                 0x0000FC00L
//GCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
#define GCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT             0x0
#define GCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT               0x5
#define GCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                               0xa
#define GCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK               0x0000001FL
#define GCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                 0x000003E0L
#define GCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                 0x0000FC00L
//GCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
#define GCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT             0x0
#define GCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT               0x5
#define GCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                               0xa
#define GCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK               0x0000001FL
#define GCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                 0x000003E0L
#define GCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                 0x0000FC00L


// addressBlock: gc_gcvmsharedpfdec
//GCMC_VM_NB_MMIOBASE
#define GCMC_VM_NB_MMIOBASE__MMIOBASE__SHIFT                                                                  0x0
#define GCMC_VM_NB_MMIOBASE__MMIOBASE_MASK                                                                    0xFFFFFFFFL
//GCMC_VM_NB_MMIOLIMIT
#define GCMC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT                                                                0x0
#define GCMC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK                                                                  0xFFFFFFFFL
//GCMC_VM_NB_PCI_CTRL
#define GCMC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT                                                                0x17
#define GCMC_VM_NB_PCI_CTRL__MMIOENABLE_MASK                                                                  0x00800000L
//GCMC_VM_NB_PCI_ARB
#define GCMC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT                                                                   0x3
#define GCMC_VM_NB_PCI_ARB__VGA_HOLE_MASK                                                                     0x00000008L
//GCMC_VM_NB_TOP_OF_DRAM_SLOT1
#define GCMC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT                                                      0x17
#define GCMC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK                                                        0xFF800000L
//GCMC_VM_NB_LOWER_TOP_OF_DRAM2
#define GCMC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT                                                          0x0
#define GCMC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT                                                      0x17
#define GCMC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK                                                            0x00000001L
#define GCMC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK                                                        0xFF800000L
//GCMC_VM_NB_UPPER_TOP_OF_DRAM2
#define GCMC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT                                                      0x0
#define GCMC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK                                                        0x00000FFFL
//GCMC_VM_FB_OFFSET
#define GCMC_VM_FB_OFFSET__FB_OFFSET__SHIFT                                                                   0x0
#define GCMC_VM_FB_OFFSET__FB_OFFSET_MASK                                                                     0x00FFFFFFL
//GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB
#define GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT                             0x0
#define GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK                               0xFFFFFFFFL
//GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB
#define GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT                             0x0
#define GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK                               0x0000000FL
//GCMC_VM_STEERING
#define GCMC_VM_STEERING__DEFAULT_STEERING__SHIFT                                                             0x0
#define GCMC_VM_STEERING__DEFAULT_STEERING_MASK                                                               0x00000003L
//GCMC_SHARED_VIRT_RESET_REQ
#define GCMC_SHARED_VIRT_RESET_REQ__VF__SHIFT                                                                 0x0
#define GCMC_SHARED_VIRT_RESET_REQ__PF__SHIFT                                                                 0x1f
#define GCMC_SHARED_VIRT_RESET_REQ__VF_MASK                                                                   0x7FFFFFFFL
#define GCMC_SHARED_VIRT_RESET_REQ__PF_MASK                                                                   0x80000000L
//GCMC_MEM_POWER_LS
#define GCMC_MEM_POWER_LS__LS_SETUP__SHIFT                                                                    0x0
#define GCMC_MEM_POWER_LS__LS_HOLD__SHIFT                                                                     0x6
#define GCMC_MEM_POWER_LS__LS_SETUP_MASK                                                                      0x0000003FL
#define GCMC_MEM_POWER_LS__LS_HOLD_MASK                                                                       0x00000FC0L
//GCMC_VM_CACHEABLE_DRAM_ADDRESS_START
#define GCMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT                                                  0x0
#define GCMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK                                                    0x000FFFFFL
//GCMC_VM_CACHEABLE_DRAM_ADDRESS_END
#define GCMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT                                                    0x0
#define GCMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK                                                      0x000FFFFFL
//GCMC_VM_APT_CNTL
#define GCMC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT                                                               0x0
#define GCMC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT                                                             0x1
#define GCMC_VM_APT_CNTL__FRAG_APT_INTXN_MODE__SHIFT                                                          0x2
#define GCMC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK                                                                 0x00000001L
#define GCMC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK                                                               0x00000002L
#define GCMC_VM_APT_CNTL__FRAG_APT_INTXN_MODE_MASK                                                            0x0000000CL
//GCMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL
#define GCMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT                                                      0x0
#define GCMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK                                                        0x00000001L
//GCMC_VM_LOCAL_HBM_ADDRESS_START
#define GCMC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS__SHIFT                                                       0x0
#define GCMC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_MASK                                                         0x000FFFFFL
//GCMC_VM_LOCAL_HBM_ADDRESS_END
#define GCMC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS__SHIFT                                                         0x0
#define GCMC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_MASK                                                           0x000FFFFFL
//GCMC_SHARED_ACTIVE_FCN_ID
#define GCMC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT                                                                0x0
#define GCMC_SHARED_ACTIVE_FCN_ID__VF__SHIFT                                                                  0x1f
#define GCMC_SHARED_ACTIVE_FCN_ID__VFID_MASK                                                                  0x0000001FL
#define GCMC_SHARED_ACTIVE_FCN_ID__VF_MASK                                                                    0x80000000L
//GCMC_SHARED_VIRT_RESET_REQ2
#define GCMC_SHARED_VIRT_RESET_REQ2__VF__SHIFT                                                                0x0
#define GCMC_SHARED_VIRT_RESET_REQ2__VF_MASK                                                                  0x00000001L
//GCMC_VM_XGMI_LFB_CNTL
#define GCMC_VM_XGMI_LFB_CNTL__PF_LFB_REGION__SHIFT                                                           0x0
#define GCMC_VM_XGMI_LFB_CNTL__PF_MAX_REGION__SHIFT                                                           0x4
#define GCMC_VM_XGMI_LFB_CNTL__PF_LFB_REGION_MASK                                                             0x0000000FL
#define GCMC_VM_XGMI_LFB_CNTL__PF_MAX_REGION_MASK                                                             0x000000F0L
//GCMC_VM_XGMI_LFB_SIZE
#define GCMC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE__SHIFT                                                             0x0
#define GCMC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE_MASK                                                               0x0001FFFFL
//GCUTCL2_HARVEST_BYPASS_GROUPS
#define GCUTCL2_HARVEST_BYPASS_GROUPS__BYPASS_GROUPS__SHIFT                                                   0x0
#define GCUTCL2_HARVEST_BYPASS_GROUPS__BYPASS_GROUPS_MASK                                                     0xFFFFFFFFL


// addressBlock: gc_gcvmsharedvcdec
//GCMC_VM_FB_LOCATION_BASE
#define GCMC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT                                                              0x0
#define GCMC_VM_FB_LOCATION_BASE__FB_BASE_MASK                                                                0x00FFFFFFL
//GCMC_VM_FB_LOCATION_TOP
#define GCMC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT                                                                0x0
#define GCMC_VM_FB_LOCATION_TOP__FB_TOP_MASK                                                                  0x00FFFFFFL
//GCMC_VM_AGP_TOP
#define GCMC_VM_AGP_TOP__AGP_TOP__SHIFT                                                                       0x0
#define GCMC_VM_AGP_TOP__AGP_TOP_MASK                                                                         0x00FFFFFFL
//GCMC_VM_AGP_BOT
#define GCMC_VM_AGP_BOT__AGP_BOT__SHIFT                                                                       0x0
#define GCMC_VM_AGP_BOT__AGP_BOT_MASK                                                                         0x00FFFFFFL
//GCMC_VM_AGP_BASE
#define GCMC_VM_AGP_BASE__AGP_BASE__SHIFT                                                                     0x0
#define GCMC_VM_AGP_BASE__AGP_BASE_MASK                                                                       0x00FFFFFFL
//GCMC_VM_SYSTEM_APERTURE_LOW_ADDR
#define GCMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT                                                 0x0
#define GCMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK                                                   0x3FFFFFFFL
//GCMC_VM_SYSTEM_APERTURE_HIGH_ADDR
#define GCMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT                                                0x0
#define GCMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK                                                  0x3FFFFFFFL
//GCMC_VM_MX_L1_TLB_CNTL
#define GCMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT                                                          0x0
#define GCMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT                                                     0x3
#define GCMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT                                        0x5
#define GCMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT                                           0x6
#define GCMC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT                                                               0x7
#define GCMC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT                                                                  0xb
#define GCMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK                                                            0x00000001L
#define GCMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK                                                       0x00000018L
#define GCMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK                                          0x00000020L
#define GCMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK                                             0x00000040L
#define GCMC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK                                                                 0x00000780L
#define GCMC_VM_MX_L1_TLB_CNTL__MTYPE_MASK                                                                    0x00003800L


// addressBlock: gc_gceadec
//GCEA_DRAM_RD_CLI2GRP_MAP0
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                          0x0
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                          0x2
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                          0x4
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                          0x6
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                          0x8
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                          0xa
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                          0xc
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                          0xe
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                          0x10
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                          0x12
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                         0x14
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                         0x16
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                         0x18
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                         0x1a
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                         0x1c
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                         0x1e
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                            0x00000003L
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                            0x0000000CL
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                            0x00000030L
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                            0x000000C0L
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                            0x00000300L
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                            0x00000C00L
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                            0x00003000L
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                            0x0000C000L
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                            0x00030000L
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                            0x000C0000L
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                           0x00300000L
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                           0x00C00000L
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                           0x03000000L
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                           0x0C000000L
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                           0x30000000L
#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                           0xC0000000L
//GCEA_DRAM_RD_CLI2GRP_MAP1
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                         0x0
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                         0x2
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                         0x4
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                         0x6
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                         0x8
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                         0xa
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                         0xc
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                         0xe
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                         0x10
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                         0x12
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                         0x14
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                         0x16
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                         0x18
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                         0x1a
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                         0x1c
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                         0x1e
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                           0x00000003L
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                           0x0000000CL
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                           0x00000030L
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                           0x000000C0L
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                           0x00000300L
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                           0x00000C00L
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                           0x00003000L
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                           0x0000C000L
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                           0x00030000L
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                           0x000C0000L
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                           0x00300000L
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                           0x00C00000L
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                           0x03000000L
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                           0x0C000000L
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                           0x30000000L
#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                           0xC0000000L
//GCEA_DRAM_WR_CLI2GRP_MAP0
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                          0x0
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                          0x2
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                          0x4
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                          0x6
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                          0x8
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                          0xa
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                          0xc
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                          0xe
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                          0x10
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                          0x12
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                         0x14
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                         0x16
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                         0x18
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                         0x1a
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                         0x1c
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                         0x1e
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                            0x00000003L
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                            0x0000000CL
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                            0x00000030L
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                            0x000000C0L
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                            0x00000300L
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                            0x00000C00L
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                            0x00003000L
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                            0x0000C000L
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                            0x00030000L
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                            0x000C0000L
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                           0x00300000L
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                           0x00C00000L
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                           0x03000000L
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                           0x0C000000L
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                           0x30000000L
#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                           0xC0000000L
//GCEA_DRAM_WR_CLI2GRP_MAP1
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                         0x0
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                         0x2
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                         0x4
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                         0x6
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                         0x8
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                         0xa
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                         0xc
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                         0xe
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                         0x10
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                         0x12
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                         0x14
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                         0x16
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                         0x18
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                         0x1a
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                         0x1c
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                         0x1e
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                           0x00000003L
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                           0x0000000CL
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                           0x00000030L
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                           0x000000C0L
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                           0x00000300L
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                           0x00000C00L
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                           0x00003000L
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                           0x0000C000L
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                           0x00030000L
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                           0x000C0000L
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                           0x00300000L
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                           0x00C00000L
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                           0x03000000L
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                           0x0C000000L
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                           0x30000000L
#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                           0xC0000000L
//GCEA_DRAM_RD_GRP2VC_MAP
#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT                                                             0x0
#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT                                                             0x3
#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT                                                             0x6
#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT                                                             0x9
#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK                                                               0x00000007L
#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK                                                               0x00000038L
#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK                                                               0x000001C0L
#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK                                                               0x00000E00L
//GCEA_DRAM_WR_GRP2VC_MAP
#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT                                                             0x0
#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT                                                             0x3
#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT                                                             0x6
#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT                                                             0x9
#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK                                                               0x00000007L
#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK                                                               0x00000038L
#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK                                                               0x000001C0L
#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK                                                               0x00000E00L
//GCEA_DRAM_RD_LAZY
#define GCEA_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT                                                                0x0
#define GCEA_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT                                                                0x3
#define GCEA_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT                                                                0x6
#define GCEA_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT                                                                0x9
#define GCEA_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT                                                            0xc
#define GCEA_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                           0x14
#define GCEA_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                           0x1b
#define GCEA_DRAM_RD_LAZY__GROUP0_DELAY_MASK                                                                  0x00000007L
#define GCEA_DRAM_RD_LAZY__GROUP1_DELAY_MASK                                                                  0x00000038L
#define GCEA_DRAM_RD_LAZY__GROUP2_DELAY_MASK                                                                  0x000001C0L
#define GCEA_DRAM_RD_LAZY__GROUP3_DELAY_MASK                                                                  0x00000E00L
#define GCEA_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK                                                              0x0003F000L
#define GCEA_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                             0x07F00000L
#define GCEA_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                             0x78000000L
//GCEA_DRAM_WR_LAZY
#define GCEA_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT                                                                0x0
#define GCEA_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT                                                                0x3
#define GCEA_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT                                                                0x6
#define GCEA_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT                                                                0x9
#define GCEA_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT                                                            0xc
#define GCEA_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                           0x14
#define GCEA_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                           0x1b
#define GCEA_DRAM_WR_LAZY__GROUP0_DELAY_MASK                                                                  0x00000007L
#define GCEA_DRAM_WR_LAZY__GROUP1_DELAY_MASK                                                                  0x00000038L
#define GCEA_DRAM_WR_LAZY__GROUP2_DELAY_MASK                                                                  0x000001C0L
#define GCEA_DRAM_WR_LAZY__GROUP3_DELAY_MASK                                                                  0x00000E00L
#define GCEA_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK                                                              0x0003F000L
#define GCEA_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                             0x07F00000L
#define GCEA_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                             0x78000000L
//GCEA_DRAM_RD_CAM_CNTL
#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                            0x0
#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                            0x4
#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                            0x8
#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                            0xc
#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                    0x10
#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                    0x13
#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                    0x16
#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                    0x19
#define GCEA_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT                                                            0x1c
#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK                                                              0x0000000FL
#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK                                                              0x000000F0L
#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK                                                              0x00000F00L
#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK                                                              0x0000F000L
#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                      0x00070000L
#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                      0x00380000L
#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                      0x01C00000L
#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                      0x0E000000L
#define GCEA_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK                                                              0x10000000L
//GCEA_DRAM_WR_CAM_CNTL
#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                            0x0
#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                            0x4
#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                            0x8
#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                            0xc
#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                    0x10
#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                    0x13
#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                    0x16
#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                    0x19
#define GCEA_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT                                                            0x1c
#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK                                                              0x0000000FL
#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK                                                              0x000000F0L
#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK                                                              0x00000F00L
#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK                                                              0x0000F000L
#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                      0x00070000L
#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                      0x00380000L
#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                      0x01C00000L
#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                      0x0E000000L
#define GCEA_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK                                                              0x10000000L
//GCEA_DRAM_PAGE_BURST
#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT                                                              0x0
#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT                                                              0x8
#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT                                                              0x10
#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT                                                              0x18
#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK                                                                0x000000FFL
#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK                                                                0x0000FF00L
#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK                                                                0x00FF0000L
#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK                                                                0xFF000000L
//GCEA_DRAM_RD_PRI_AGE
#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                        0x0
#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                        0x3
#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                        0x6
#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                        0x9
#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                   0xc
#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                   0xf
#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                   0x12
#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                   0x15
#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                          0x00000007L
#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                          0x00000038L
#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                          0x000001C0L
#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                          0x00000E00L
#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                     0x00007000L
#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                     0x00038000L
#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                     0x001C0000L
#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                     0x00E00000L
//GCEA_DRAM_WR_PRI_AGE
#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                        0x0
#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                        0x3
#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                        0x6
#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                        0x9
#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                   0xc
#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                   0xf
#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                   0x12
#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                   0x15
#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                          0x00000007L
#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                          0x00000038L
#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                          0x000001C0L
#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                          0x00000E00L
#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                     0x00007000L
#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                     0x00038000L
#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                     0x001C0000L
#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                     0x00E00000L
//GCEA_DRAM_RD_PRI_QUEUING
#define GCEA_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                           0x0
#define GCEA_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                           0x3
#define GCEA_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                           0x6
#define GCEA_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                           0x9
#define GCEA_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                             0x00000007L
#define GCEA_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                             0x00000038L
#define GCEA_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                             0x000001C0L
#define GCEA_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                             0x00000E00L
//GCEA_DRAM_WR_PRI_QUEUING
#define GCEA_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                           0x0
#define GCEA_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                           0x3
#define GCEA_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                           0x6
#define GCEA_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                           0x9
#define GCEA_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                             0x00000007L
#define GCEA_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                             0x00000038L
#define GCEA_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                             0x000001C0L
#define GCEA_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                             0x00000E00L
//GCEA_DRAM_RD_PRI_FIXED
#define GCEA_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                               0x0
#define GCEA_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                               0x3
#define GCEA_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                               0x6
#define GCEA_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                               0x9
#define GCEA_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                 0x00000007L
#define GCEA_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                 0x00000038L
#define GCEA_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                 0x000001C0L
#define GCEA_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                 0x00000E00L
//GCEA_DRAM_WR_PRI_FIXED
#define GCEA_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                               0x0
#define GCEA_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                               0x3
#define GCEA_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                               0x6
#define GCEA_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                               0x9
#define GCEA_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                 0x00000007L
#define GCEA_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                 0x00000038L
#define GCEA_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                 0x000001C0L
#define GCEA_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                 0x00000E00L
//GCEA_DRAM_RD_PRI_URGENCY
#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                           0x0
#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                           0x3
#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                           0x6
#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                           0x9
#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                  0xc
#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                  0xd
#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                  0xe
#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                  0xf
#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                             0x00000007L
#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                             0x00000038L
#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                             0x000001C0L
#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                             0x00000E00L
#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                    0x00001000L
#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                    0x00002000L
#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                    0x00004000L
#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                    0x00008000L
//GCEA_DRAM_WR_PRI_URGENCY
#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                           0x0
#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                           0x3
#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                           0x6
#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                           0x9
#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                  0xc
#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                  0xd
#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                  0xe
#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                  0xf
#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                             0x00000007L
#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                             0x00000038L
#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                             0x000001C0L
#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                             0x00000E00L
#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                    0x00001000L
#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                    0x00002000L
#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                    0x00004000L
#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                    0x00008000L
//GCEA_DRAM_RD_PRI_QUANT_PRI1
#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                  0x0
#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                  0x8
#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                  0x10
#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                  0x18
#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
//GCEA_DRAM_RD_PRI_QUANT_PRI2
#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                  0x0
#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                  0x8
#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                  0x10
#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                  0x18
#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
//GCEA_DRAM_RD_PRI_QUANT_PRI3
#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                  0x0
#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                  0x8
#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                  0x10
#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                  0x18
#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
//GCEA_DRAM_WR_PRI_QUANT_PRI1
#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                  0x0
#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                  0x8
#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                  0x10
#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                  0x18
#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
//GCEA_DRAM_WR_PRI_QUANT_PRI2
#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                  0x0
#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                  0x8
#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                  0x10
#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                  0x18
#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
//GCEA_DRAM_WR_PRI_QUANT_PRI3
#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                  0x0
#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                  0x8
#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                  0x10
#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                  0x18
#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
//GCEA_IO_RD_CLI2GRP_MAP0
#define GCEA_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                            0x0
#define GCEA_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                            0x2
#define GCEA_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                            0x4
#define GCEA_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                            0x6
#define GCEA_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                            0x8
#define GCEA_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                            0xa
#define GCEA_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                            0xc
#define GCEA_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                            0xe
#define GCEA_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                            0x10
#define GCEA_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                            0x12
#define GCEA_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                           0x14
#define GCEA_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                           0x16
#define GCEA_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                           0x18
#define GCEA_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                           0x1a
#define GCEA_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                           0x1c
#define GCEA_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                           0x1e
#define GCEA_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                              0x00000003L
#define GCEA_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                              0x0000000CL
#define GCEA_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                              0x00000030L
#define GCEA_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                              0x000000C0L
#define GCEA_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                              0x00000300L
#define GCEA_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                              0x00000C00L
#define GCEA_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                              0x00003000L
#define GCEA_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                              0x0000C000L
#define GCEA_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                              0x00030000L
#define GCEA_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                              0x000C0000L
#define GCEA_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                             0x00300000L
#define GCEA_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                             0x00C00000L
#define GCEA_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                             0x03000000L
#define GCEA_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                             0x0C000000L
#define GCEA_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                             0x30000000L
#define GCEA_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                             0xC0000000L
//GCEA_IO_RD_CLI2GRP_MAP1
#define GCEA_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                           0x0
#define GCEA_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                           0x2
#define GCEA_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                           0x4
#define GCEA_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                           0x6
#define GCEA_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                           0x8
#define GCEA_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                           0xa
#define GCEA_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                           0xc
#define GCEA_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                           0xe
#define GCEA_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                           0x10
#define GCEA_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                           0x12
#define GCEA_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                           0x14
#define GCEA_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                           0x16
#define GCEA_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                           0x18
#define GCEA_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                           0x1a
#define GCEA_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                           0x1c
#define GCEA_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                           0x1e
#define GCEA_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                             0x00000003L
#define GCEA_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                             0x0000000CL
#define GCEA_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                             0x00000030L
#define GCEA_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                             0x000000C0L
#define GCEA_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                             0x00000300L
#define GCEA_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                             0x00000C00L
#define GCEA_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                             0x00003000L
#define GCEA_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                             0x0000C000L
#define GCEA_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                             0x00030000L
#define GCEA_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                             0x000C0000L
#define GCEA_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                             0x00300000L
#define GCEA_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                             0x00C00000L
#define GCEA_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                             0x03000000L
#define GCEA_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                             0x0C000000L
#define GCEA_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                             0x30000000L
#define GCEA_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                             0xC0000000L
//GCEA_IO_WR_CLI2GRP_MAP0
#define GCEA_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                            0x0
#define GCEA_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                            0x2
#define GCEA_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                            0x4
#define GCEA_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                            0x6
#define GCEA_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                            0x8
#define GCEA_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                            0xa
#define GCEA_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                            0xc
#define GCEA_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                            0xe
#define GCEA_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                            0x10
#define GCEA_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                            0x12
#define GCEA_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                           0x14
#define GCEA_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                           0x16
#define GCEA_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                           0x18
#define GCEA_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                           0x1a
#define GCEA_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                           0x1c
#define GCEA_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                           0x1e
#define GCEA_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                              0x00000003L
#define GCEA_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                              0x0000000CL
#define GCEA_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                              0x00000030L
#define GCEA_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                              0x000000C0L
#define GCEA_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                              0x00000300L
#define GCEA_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                              0x00000C00L
#define GCEA_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                              0x00003000L
#define GCEA_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                              0x0000C000L
#define GCEA_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                              0x00030000L
#define GCEA_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                              0x000C0000L
#define GCEA_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                             0x00300000L
#define GCEA_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                             0x00C00000L
#define GCEA_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                             0x03000000L
#define GCEA_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                             0x0C000000L
#define GCEA_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                             0x30000000L
#define GCEA_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                             0xC0000000L
//GCEA_IO_WR_CLI2GRP_MAP1
#define GCEA_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                           0x0
#define GCEA_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                           0x2
#define GCEA_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                           0x4
#define GCEA_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                           0x6
#define GCEA_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                           0x8
#define GCEA_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                           0xa
#define GCEA_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                           0xc
#define GCEA_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                           0xe
#define GCEA_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                           0x10
#define GCEA_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                           0x12
#define GCEA_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                           0x14
#define GCEA_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                           0x16
#define GCEA_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                           0x18
#define GCEA_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                           0x1a
#define GCEA_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                           0x1c
#define GCEA_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                           0x1e
#define GCEA_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                             0x00000003L
#define GCEA_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                             0x0000000CL
#define GCEA_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                             0x00000030L
#define GCEA_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                             0x000000C0L
#define GCEA_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                             0x00000300L
#define GCEA_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                             0x00000C00L
#define GCEA_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                             0x00003000L
#define GCEA_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                             0x0000C000L
#define GCEA_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                             0x00030000L
#define GCEA_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                             0x000C0000L
#define GCEA_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                             0x00300000L
#define GCEA_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                             0x00C00000L
#define GCEA_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                             0x03000000L
#define GCEA_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                             0x0C000000L
#define GCEA_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                             0x30000000L
#define GCEA_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                             0xC0000000L
//GCEA_IO_RD_COMBINE_FLUSH
#define GCEA_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT                                                         0x0
#define GCEA_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT                                                         0x4
#define GCEA_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT                                                         0x8
#define GCEA_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT                                                         0xc
#define GCEA_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT                                                    0x10
#define GCEA_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK                                                           0x0000000FL
#define GCEA_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK                                                           0x000000F0L
#define GCEA_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK                                                           0x00000F00L
#define GCEA_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK                                                           0x0000F000L
#define GCEA_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK                                                      0x00010000L
//GCEA_IO_WR_COMBINE_FLUSH
#define GCEA_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT                                                         0x0
#define GCEA_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT                                                         0x4
#define GCEA_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT                                                         0x8
#define GCEA_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT                                                         0xc
#define GCEA_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT                                                    0x10
#define GCEA_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK                                                           0x0000000FL
#define GCEA_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK                                                           0x000000F0L
#define GCEA_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK                                                           0x00000F00L
#define GCEA_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK                                                           0x0000F000L
#define GCEA_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK                                                      0x00010000L
//GCEA_IO_GROUP_BURST
#define GCEA_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT                                                               0x0
#define GCEA_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT                                                               0x8
#define GCEA_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT                                                               0x10
#define GCEA_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT                                                               0x18
#define GCEA_IO_GROUP_BURST__RD_LIMIT_LO_MASK                                                                 0x000000FFL
#define GCEA_IO_GROUP_BURST__RD_LIMIT_HI_MASK                                                                 0x0000FF00L
#define GCEA_IO_GROUP_BURST__WR_LIMIT_LO_MASK                                                                 0x00FF0000L
#define GCEA_IO_GROUP_BURST__WR_LIMIT_HI_MASK                                                                 0xFF000000L
//GCEA_IO_RD_PRI_AGE
#define GCEA_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                          0x0
#define GCEA_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                          0x3
#define GCEA_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                          0x6
#define GCEA_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                          0x9
#define GCEA_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                     0xc
#define GCEA_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                     0xf
#define GCEA_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                     0x12
#define GCEA_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                     0x15
#define GCEA_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                            0x00000007L
#define GCEA_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                            0x00000038L
#define GCEA_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                            0x000001C0L
#define GCEA_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                            0x00000E00L
#define GCEA_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                       0x00007000L
#define GCEA_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                       0x00038000L
#define GCEA_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                       0x001C0000L
#define GCEA_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                       0x00E00000L
//GCEA_IO_WR_PRI_AGE
#define GCEA_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                          0x0
#define GCEA_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                          0x3
#define GCEA_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                          0x6
#define GCEA_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                          0x9
#define GCEA_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                     0xc
#define GCEA_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                     0xf
#define GCEA_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                     0x12
#define GCEA_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                     0x15
#define GCEA_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                            0x00000007L
#define GCEA_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                            0x00000038L
#define GCEA_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                            0x000001C0L
#define GCEA_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                            0x00000E00L
#define GCEA_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                       0x00007000L
#define GCEA_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                       0x00038000L
#define GCEA_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                       0x001C0000L
#define GCEA_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                       0x00E00000L
//GCEA_IO_RD_PRI_QUEUING
#define GCEA_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                             0x0
#define GCEA_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                             0x3
#define GCEA_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                             0x6
#define GCEA_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                             0x9
#define GCEA_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                               0x00000007L
#define GCEA_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                               0x00000038L
#define GCEA_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                               0x000001C0L
#define GCEA_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                               0x00000E00L
//GCEA_IO_WR_PRI_QUEUING
#define GCEA_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                             0x0
#define GCEA_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                             0x3
#define GCEA_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                             0x6
#define GCEA_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                             0x9
#define GCEA_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                               0x00000007L
#define GCEA_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                               0x00000038L
#define GCEA_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                               0x000001C0L
#define GCEA_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                               0x00000E00L
//GCEA_IO_RD_PRI_FIXED
#define GCEA_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                                 0x0
#define GCEA_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                                 0x3
#define GCEA_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                                 0x6
#define GCEA_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                                 0x9
#define GCEA_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                   0x00000007L
#define GCEA_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                   0x00000038L
#define GCEA_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                   0x000001C0L
#define GCEA_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                   0x00000E00L
//GCEA_IO_WR_PRI_FIXED
#define GCEA_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                                 0x0
#define GCEA_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                                 0x3
#define GCEA_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                                 0x6
#define GCEA_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                                 0x9
#define GCEA_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                   0x00000007L
#define GCEA_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                   0x00000038L
#define GCEA_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                   0x000001C0L
#define GCEA_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                   0x00000E00L
//GCEA_IO_RD_PRI_URGENCY
#define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                             0x0
#define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                             0x3
#define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                             0x6
#define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                             0x9
#define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                    0xc
#define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                    0xd
#define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                    0xe
#define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                    0xf
#define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                               0x00000007L
#define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                               0x00000038L
#define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                               0x000001C0L
#define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                               0x00000E00L
#define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                      0x00001000L
#define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                      0x00002000L
#define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                      0x00004000L
#define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                      0x00008000L
//GCEA_IO_WR_PRI_URGENCY
#define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                             0x0
#define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                             0x3
#define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                             0x6
#define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                             0x9
#define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                    0xc
#define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                    0xd
#define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                    0xe
#define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                    0xf
#define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                               0x00000007L
#define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                               0x00000038L
#define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                               0x000001C0L
#define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                               0x00000E00L
#define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                      0x00001000L
#define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                      0x00002000L
#define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                      0x00004000L
#define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                      0x00008000L
//GCEA_IO_RD_PRI_URGENCY_MASKING
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                      0x0
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                      0x1
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                      0x2
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                      0x3
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                      0x4
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                      0x5
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                      0x6
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                      0x7
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                      0x8
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                      0x9
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                     0xa
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                     0xb
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                     0xc
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                     0xd
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                     0xe
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                     0xf
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                     0x10
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                     0x11
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                     0x12
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                     0x13
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                     0x14
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                     0x15
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                     0x16
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                     0x17
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                     0x18
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                     0x19
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                     0x1a
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                     0x1b
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                     0x1c
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                     0x1d
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                     0x1e
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                     0x1f
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                        0x00000001L
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                        0x00000002L
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                        0x00000004L
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                        0x00000008L
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                        0x00000010L
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                        0x00000020L
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                        0x00000040L
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                        0x00000080L
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                        0x00000100L
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                        0x00000200L
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                       0x00000400L
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                       0x00000800L
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                       0x00001000L
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                       0x00002000L
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                       0x00004000L
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                       0x00008000L
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                       0x00010000L
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                       0x00020000L
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                       0x00040000L
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                       0x00080000L
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                       0x00100000L
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                       0x00200000L
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                       0x00400000L
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                       0x00800000L
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                       0x01000000L
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                       0x02000000L
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                       0x04000000L
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                       0x08000000L
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                       0x10000000L
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                       0x20000000L
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                       0x40000000L
#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                       0x80000000L
//GCEA_IO_WR_PRI_URGENCY_MASKING
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                      0x0
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                      0x1
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                      0x2
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                      0x3
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                      0x4
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                      0x5
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                      0x6
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                      0x7
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                      0x8
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                      0x9
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                     0xa
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                     0xb
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                     0xc
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                     0xd
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                     0xe
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                     0xf
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                     0x10
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                     0x11
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                     0x12
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                     0x13
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                     0x14
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                     0x15
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                     0x16
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                     0x17
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                     0x18
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                     0x19
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                     0x1a
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                     0x1b
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                     0x1c
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                     0x1d
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                     0x1e
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                     0x1f
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                        0x00000001L
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                        0x00000002L
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                        0x00000004L
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                        0x00000008L
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                        0x00000010L
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                        0x00000020L
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                        0x00000040L
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                        0x00000080L
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                        0x00000100L
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                        0x00000200L
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                       0x00000400L
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                       0x00000800L
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                       0x00001000L
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                       0x00002000L
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                       0x00004000L
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                       0x00008000L
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                       0x00010000L
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                       0x00020000L
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                       0x00040000L
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                       0x00080000L
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                       0x00100000L
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                       0x00200000L
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                       0x00400000L
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                       0x00800000L
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                       0x01000000L
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                       0x02000000L
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                       0x04000000L
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                       0x08000000L
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                       0x10000000L
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                       0x20000000L
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                       0x40000000L
#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                       0x80000000L
//GCEA_IO_RD_PRI_QUANT_PRI1
#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                    0x0
#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                    0x8
#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                    0x10
#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                    0x18
#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                      0x000000FFL
#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                      0x0000FF00L
#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                      0x00FF0000L
#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                      0xFF000000L
//GCEA_IO_RD_PRI_QUANT_PRI2
#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                    0x0
#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                    0x8
#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                    0x10
#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                    0x18
#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                      0x000000FFL
#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                      0x0000FF00L
#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                      0x00FF0000L
#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                      0xFF000000L
//GCEA_IO_RD_PRI_QUANT_PRI3
#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                    0x0
#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                    0x8
#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                    0x10
#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                    0x18
#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                      0x000000FFL
#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                      0x0000FF00L
#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                      0x00FF0000L
#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                      0xFF000000L
//GCEA_IO_WR_PRI_QUANT_PRI1
#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                    0x0
#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                    0x8
#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                    0x10
#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                    0x18
#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                      0x000000FFL
#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                      0x0000FF00L
#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                      0x00FF0000L
#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                      0xFF000000L
//GCEA_IO_WR_PRI_QUANT_PRI2
#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                    0x0
#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                    0x8
#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                    0x10
#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                    0x18
#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                      0x000000FFL
#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                      0x0000FF00L
#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                      0x00FF0000L
#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                      0xFF000000L
//GCEA_IO_WR_PRI_QUANT_PRI3
#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                    0x0
#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                    0x8
#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                    0x10
#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                    0x18
#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                      0x000000FFL
#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                      0x0000FF00L
#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                      0x00FF0000L
#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                      0xFF000000L


// addressBlock: gc_tcdec
//TCP_INVALIDATE
#define TCP_INVALIDATE__START__SHIFT                                                                          0x0
#define TCP_INVALIDATE__START_MASK                                                                            0x00000001L
//TCP_STATUS
#define TCP_STATUS__TCP_BUSY__SHIFT                                                                           0x0
#define TCP_STATUS__INPUT_BUSY__SHIFT                                                                         0x1
#define TCP_STATUS__ADRS_BUSY__SHIFT                                                                          0x2
#define TCP_STATUS__TAGRAMS_BUSY__SHIFT                                                                       0x3
#define TCP_STATUS__CNTRL_BUSY__SHIFT                                                                         0x4
#define TCP_STATUS__LFIFO_BUSY__SHIFT                                                                         0x5
#define TCP_STATUS__READ_BUSY__SHIFT                                                                          0x6
#define TCP_STATUS__FORMAT_BUSY__SHIFT                                                                        0x7
#define TCP_STATUS__VM_BUSY__SHIFT                                                                            0x8
#define TCP_STATUS__MEMIF_BUSY__SHIFT                                                                         0x9
#define TCP_STATUS__GCR_BUSY__SHIFT                                                                           0xa
#define TCP_STATUS__OFIFO_BUSY__SHIFT                                                                         0xb
#define TCP_STATUS__OFIFO_QUEUE_BUSY__SHIFT                                                                   0xc
#define TCP_STATUS__TCP_BUSY_MASK                                                                             0x00000001L
#define TCP_STATUS__INPUT_BUSY_MASK                                                                           0x00000002L
#define TCP_STATUS__ADRS_BUSY_MASK                                                                            0x00000004L
#define TCP_STATUS__TAGRAMS_BUSY_MASK                                                                         0x00000008L
#define TCP_STATUS__CNTRL_BUSY_MASK                                                                           0x00000010L
#define TCP_STATUS__LFIFO_BUSY_MASK                                                                           0x00000020L
#define TCP_STATUS__READ_BUSY_MASK                                                                            0x00000040L
#define TCP_STATUS__FORMAT_BUSY_MASK                                                                          0x00000080L
#define TCP_STATUS__VM_BUSY_MASK                                                                              0x00000100L
#define TCP_STATUS__MEMIF_BUSY_MASK                                                                           0x00000200L
#define TCP_STATUS__GCR_BUSY_MASK                                                                             0x00000400L
#define TCP_STATUS__OFIFO_BUSY_MASK                                                                           0x00000800L
#define TCP_STATUS__OFIFO_QUEUE_BUSY_MASK                                                                     0x00003000L
//TCP_EDC_CNT
#define TCP_EDC_CNT__SEC_COUNT__SHIFT                                                                         0x0
#define TCP_EDC_CNT__LFIFO_SED_COUNT__SHIFT                                                                   0x8
#define TCP_EDC_CNT__DED_COUNT__SHIFT                                                                         0x10
#define TCP_EDC_CNT__SEC_COUNT_MASK                                                                           0x000000FFL
#define TCP_EDC_CNT__LFIFO_SED_COUNT_MASK                                                                     0x0000FF00L
#define TCP_EDC_CNT__DED_COUNT_MASK                                                                           0x00FF0000L
//TCI_STATUS
#define TCI_STATUS__TCI_BUSY__SHIFT                                                                           0x0
#define TCI_STATUS__TCI_BUSY_MASK                                                                             0x00000001L
//TCI_CNTL_1
#define TCI_CNTL_1__WBINVL1_NUM_CYCLES__SHIFT                                                                 0x0
#define TCI_CNTL_1__REQ_FIFO_DEPTH__SHIFT                                                                     0x10
#define TCI_CNTL_1__WDATA_RAM_DEPTH__SHIFT                                                                    0x18
#define TCI_CNTL_1__WBINVL1_NUM_CYCLES_MASK                                                                   0x0000FFFFL
#define TCI_CNTL_1__REQ_FIFO_DEPTH_MASK                                                                       0x00FF0000L
#define TCI_CNTL_1__WDATA_RAM_DEPTH_MASK                                                                      0xFF000000L
//TCI_CNTL_2
#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2__SHIFT                                                                0x0
#define TCI_CNTL_2__TCA_MAX_CREDIT__SHIFT                                                                     0x1
#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2_MASK                                                                  0x00000001L
#define TCI_CNTL_2__TCA_MAX_CREDIT_MASK                                                                       0x000001FEL


// addressBlock: gc_shdec
//SPI_SHADER_PGM_RSRC4_PS
#define SPI_SHADER_PGM_RSRC4_PS__CU_EN__SHIFT                                                                 0x0
#define SPI_SHADER_PGM_RSRC4_PS__CU_EN_MASK                                                                   0x0000FFFFL
//SPI_SHADER_PGM_CHKSUM_PS
#define SPI_SHADER_PGM_CHKSUM_PS__CHECKSUM__SHIFT                                                             0x0
#define SPI_SHADER_PGM_CHKSUM_PS__CHECKSUM_MASK                                                               0xFFFFFFFFL
//SPI_SHADER_PGM_RSRC3_PS
#define SPI_SHADER_PGM_RSRC3_PS__CU_EN__SHIFT                                                                 0x0
#define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT__SHIFT                                                            0x10
#define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD__SHIFT                                                    0x16
#define SPI_SHADER_PGM_RSRC3_PS__CU_EN_MASK                                                                   0x0000FFFFL
#define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT_MASK                                                              0x003F0000L
#define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD_MASK                                                      0x03C00000L
//SPI_SHADER_PGM_LO_PS
#define SPI_SHADER_PGM_LO_PS__MEM_BASE__SHIFT                                                                 0x0
#define SPI_SHADER_PGM_LO_PS__MEM_BASE_MASK                                                                   0xFFFFFFFFL
//SPI_SHADER_PGM_HI_PS
#define SPI_SHADER_PGM_HI_PS__MEM_BASE__SHIFT                                                                 0x0
#define SPI_SHADER_PGM_HI_PS__MEM_BASE_MASK                                                                   0xFFL
//SPI_SHADER_PGM_RSRC1_PS
#define SPI_SHADER_PGM_RSRC1_PS__VGPRS__SHIFT                                                                 0x0
#define SPI_SHADER_PGM_RSRC1_PS__SGPRS__SHIFT                                                                 0x6
#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY__SHIFT                                                              0xa
#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE__SHIFT                                                            0xc
#define SPI_SHADER_PGM_RSRC1_PS__PRIV__SHIFT                                                                  0x14
#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP__SHIFT                                                            0x15
#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE__SHIFT                                                             0x17
#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE__SHIFT                                                      0x18
#define SPI_SHADER_PGM_RSRC1_PS__MEM_ORDERED__SHIFT                                                           0x19
#define SPI_SHADER_PGM_RSRC1_PS__FWD_PROGRESS__SHIFT                                                          0x1a
#define SPI_SHADER_PGM_RSRC1_PS__LOAD_PROVOKING_VTX__SHIFT                                                    0x1b
#define SPI_SHADER_PGM_RSRC1_PS__FP16_OVFL__SHIFT                                                             0x1d
#define SPI_SHADER_PGM_RSRC1_PS__VGPRS_MASK                                                                   0x0000003FL
#define SPI_SHADER_PGM_RSRC1_PS__SGPRS_MASK                                                                   0x000003C0L
#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY_MASK                                                                0x00000C00L
#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE_MASK                                                              0x000FF000L
#define SPI_SHADER_PGM_RSRC1_PS__PRIV_MASK                                                                    0x00100000L
#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP_MASK                                                              0x00200000L
#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE_MASK                                                               0x00800000L
#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE_MASK                                                        0x01000000L
#define SPI_SHADER_PGM_RSRC1_PS__MEM_ORDERED_MASK                                                             0x02000000L
#define SPI_SHADER_PGM_RSRC1_PS__FWD_PROGRESS_MASK                                                            0x04000000L
#define SPI_SHADER_PGM_RSRC1_PS__LOAD_PROVOKING_VTX_MASK                                                      0x08000000L
#define SPI_SHADER_PGM_RSRC1_PS__FP16_OVFL_MASK                                                               0x20000000L
//SPI_SHADER_PGM_RSRC2_PS
#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN__SHIFT                                                            0x0
#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR__SHIFT                                                             0x1
#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT__SHIFT                                                          0x6
#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN__SHIFT                                                           0x7
#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE__SHIFT                                                        0x8
#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN__SHIFT                                                               0x10
#define SPI_SHADER_PGM_RSRC2_PS__LOAD_COLLISION_WAVEID__SHIFT                                                 0x19
#define SPI_SHADER_PGM_RSRC2_PS__LOAD_INTRAWAVE_COLLISION__SHIFT                                              0x1a
#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MSB__SHIFT                                                         0x1b
#define SPI_SHADER_PGM_RSRC2_PS__SHARED_VGPR_CNT__SHIFT                                                       0x1c
#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN_MASK                                                              0x00000001L
#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MASK                                                               0x0000003EL
#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT_MASK                                                            0x00000040L
#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN_MASK                                                             0x00000080L
#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE_MASK                                                          0x0000FF00L
#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN_MASK                                                                 0x01FF0000L
#define SPI_SHADER_PGM_RSRC2_PS__LOAD_COLLISION_WAVEID_MASK                                                   0x02000000L
#define SPI_SHADER_PGM_RSRC2_PS__LOAD_INTRAWAVE_COLLISION_MASK                                                0x04000000L
#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MSB_MASK                                                           0x08000000L
#define SPI_SHADER_PGM_RSRC2_PS__SHARED_VGPR_CNT_MASK                                                         0xF0000000L
//SPI_SHADER_USER_DATA_PS_0
#define SPI_SHADER_USER_DATA_PS_0__DATA__SHIFT                                                                0x0
#define SPI_SHADER_USER_DATA_PS_0__DATA_MASK                                                                  0xFFFFFFFFL
//SPI_SHADER_USER_DATA_PS_1
#define SPI_SHADER_USER_DATA_PS_1__DATA__SHIFT                                                                0x0
#define SPI_SHADER_USER_DATA_PS_1__DATA_MASK                                                                  0xFFFFFFFFL
//SPI_SHADER_USER_DATA_PS_2
#define SPI_SHADER_USER_DATA_PS_2__DATA__SHIFT                                                                0x0
#define SPI_SHADER_USER_DATA_PS_2__DATA_MASK                                                                  0xFFFFFFFFL
//SPI_SHADER_USER_DATA_PS_3
#define SPI_SHADER_USER_DATA_PS_3__DATA__SHIFT                                                                0x0
#define SPI_SHADER_USER_DATA_PS_3__DATA_MASK                                                                  0xFFFFFFFFL
//SPI_SHADER_USER_DATA_PS_4
#define SPI_SHADER_USER_DATA_PS_4__DATA__SHIFT                                                                0x0
#define SPI_SHADER_USER_DATA_PS_4__DATA_MASK                                                                  0xFFFFFFFFL
//SPI_SHADER_USER_DATA_PS_5
#define SPI_SHADER_USER_DATA_PS_5__DATA__SHIFT                                                                0x0
#define SPI_SHADER_USER_DATA_PS_5__DATA_MASK                                                                  0xFFFFFFFFL
//SPI_SHADER_USER_DATA_PS_6
#define SPI_SHADER_USER_DATA_PS_6__DATA__SHIFT                                                                0x0
#define SPI_SHADER_USER_DATA_PS_6__DATA_MASK                                                                  0xFFFFFFFFL
//SPI_SHADER_USER_DATA_PS_7
#define SPI_SHADER_USER_DATA_PS_7__DATA__SHIFT                                                                0x0
#define SPI_SHADER_USER_DATA_PS_7__DATA_MASK                                                                  0xFFFFFFFFL
//SPI_SHADER_USER_DATA_PS_8
#define SPI_SHADER_USER_DATA_PS_8__DATA__SHIFT                                                                0x0
#define SPI_SHADER_USER_DATA_PS_8__DATA_MASK                                                                  0xFFFFFFFFL
//SPI_SHADER_USER_DATA_PS_9
#define SPI_SHADER_USER_DATA_PS_9__DATA__SHIFT                                                                0x0
#define SPI_SHADER_USER_DATA_PS_9__DATA_MASK                                                                  0xFFFFFFFFL
//SPI_SHADER_USER_DATA_PS_10
#define SPI_SHADER_USER_DATA_PS_10__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_PS_10__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_PS_11
#define SPI_SHADER_USER_DATA_PS_11__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_PS_11__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_PS_12
#define SPI_SHADER_USER_DATA_PS_12__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_PS_12__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_PS_13
#define SPI_SHADER_USER_DATA_PS_13__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_PS_13__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_PS_14
#define SPI_SHADER_USER_DATA_PS_14__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_PS_14__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_PS_15
#define SPI_SHADER_USER_DATA_PS_15__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_PS_15__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_PS_16
#define SPI_SHADER_USER_DATA_PS_16__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_PS_16__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_PS_17
#define SPI_SHADER_USER_DATA_PS_17__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_PS_17__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_PS_18
#define SPI_SHADER_USER_DATA_PS_18__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_PS_18__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_PS_19
#define SPI_SHADER_USER_DATA_PS_19__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_PS_19__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_PS_20
#define SPI_SHADER_USER_DATA_PS_20__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_PS_20__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_PS_21
#define SPI_SHADER_USER_DATA_PS_21__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_PS_21__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_PS_22
#define SPI_SHADER_USER_DATA_PS_22__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_PS_22__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_PS_23
#define SPI_SHADER_USER_DATA_PS_23__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_PS_23__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_PS_24
#define SPI_SHADER_USER_DATA_PS_24__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_PS_24__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_PS_25
#define SPI_SHADER_USER_DATA_PS_25__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_PS_25__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_PS_26
#define SPI_SHADER_USER_DATA_PS_26__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_PS_26__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_PS_27
#define SPI_SHADER_USER_DATA_PS_27__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_PS_27__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_PS_28
#define SPI_SHADER_USER_DATA_PS_28__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_PS_28__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_PS_29
#define SPI_SHADER_USER_DATA_PS_29__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_PS_29__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_PS_30
#define SPI_SHADER_USER_DATA_PS_30__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_PS_30__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_PS_31
#define SPI_SHADER_USER_DATA_PS_31__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_PS_31__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_REQ_CTRL_PS
#define SPI_SHADER_REQ_CTRL_PS__SOFT_GROUPING_EN__SHIFT                                                       0x0
#define SPI_SHADER_REQ_CTRL_PS__NUMBER_OF_REQUESTS_PER_CU__SHIFT                                              0x1
#define SPI_SHADER_REQ_CTRL_PS__SOFT_GROUPING_ALLOCATION_TIMEOUT__SHIFT                                       0x5
#define SPI_SHADER_REQ_CTRL_PS__HARD_LOCK_HYSTERESIS__SHIFT                                                   0x9
#define SPI_SHADER_REQ_CTRL_PS__HARD_LOCK_LOW_THRESHOLD__SHIFT                                                0xa
#define SPI_SHADER_REQ_CTRL_PS__PRODUCER_REQUEST_LOCKOUT__SHIFT                                               0xf
#define SPI_SHADER_REQ_CTRL_PS__GLOBAL_SCANNING_EN__SHIFT                                                     0x10
#define SPI_SHADER_REQ_CTRL_PS__ALLOCATION_RATE_THROTTLING_THRESHOLD__SHIFT                                   0x11
#define SPI_SHADER_REQ_CTRL_PS__SOFT_GROUPING_EN_MASK                                                         0x00000001L
#define SPI_SHADER_REQ_CTRL_PS__NUMBER_OF_REQUESTS_PER_CU_MASK                                                0x0000001EL
#define SPI_SHADER_REQ_CTRL_PS__SOFT_GROUPING_ALLOCATION_TIMEOUT_MASK                                         0x000001E0L
#define SPI_SHADER_REQ_CTRL_PS__HARD_LOCK_HYSTERESIS_MASK                                                     0x00000200L
#define SPI_SHADER_REQ_CTRL_PS__HARD_LOCK_LOW_THRESHOLD_MASK                                                  0x00007C00L
#define SPI_SHADER_REQ_CTRL_PS__PRODUCER_REQUEST_LOCKOUT_MASK                                                 0x00008000L
#define SPI_SHADER_REQ_CTRL_PS__GLOBAL_SCANNING_EN_MASK                                                       0x00010000L
#define SPI_SHADER_REQ_CTRL_PS__ALLOCATION_RATE_THROTTLING_THRESHOLD_MASK                                     0x000E0000L
//SPI_SHADER_USER_ACCUM_PS_0
#define SPI_SHADER_USER_ACCUM_PS_0__CONTRIBUTION__SHIFT                                                       0x0
#define SPI_SHADER_USER_ACCUM_PS_0__CONTRIBUTION_MASK                                                         0x0000007FL
//SPI_SHADER_USER_ACCUM_PS_1
#define SPI_SHADER_USER_ACCUM_PS_1__CONTRIBUTION__SHIFT                                                       0x0
#define SPI_SHADER_USER_ACCUM_PS_1__CONTRIBUTION_MASK                                                         0x0000007FL
//SPI_SHADER_USER_ACCUM_PS_2
#define SPI_SHADER_USER_ACCUM_PS_2__CONTRIBUTION__SHIFT                                                       0x0
#define SPI_SHADER_USER_ACCUM_PS_2__CONTRIBUTION_MASK                                                         0x0000007FL
//SPI_SHADER_USER_ACCUM_PS_3
#define SPI_SHADER_USER_ACCUM_PS_3__CONTRIBUTION__SHIFT                                                       0x0
#define SPI_SHADER_USER_ACCUM_PS_3__CONTRIBUTION_MASK                                                         0x0000007FL
//SPI_SHADER_PGM_RSRC4_VS
#define SPI_SHADER_PGM_RSRC4_VS__CU_EN__SHIFT                                                                 0x0
#define SPI_SHADER_PGM_RSRC4_VS__CU_EN_MASK                                                                   0x0000FFFFL
//SPI_SHADER_PGM_CHKSUM_VS
#define SPI_SHADER_PGM_CHKSUM_VS__CHECKSUM__SHIFT                                                             0x0
#define SPI_SHADER_PGM_CHKSUM_VS__CHECKSUM_MASK                                                               0xFFFFFFFFL
//SPI_SHADER_PGM_RSRC3_VS
#define SPI_SHADER_PGM_RSRC3_VS__CU_EN__SHIFT                                                                 0x0
#define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT__SHIFT                                                            0x10
#define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD__SHIFT                                                    0x16
#define SPI_SHADER_PGM_RSRC3_VS__CU_EN_MASK                                                                   0x0000FFFFL
#define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT_MASK                                                              0x003F0000L
#define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD_MASK                                                      0x03C00000L
//SPI_SHADER_LATE_ALLOC_VS
#define SPI_SHADER_LATE_ALLOC_VS__LIMIT__SHIFT                                                                0x0
#define SPI_SHADER_LATE_ALLOC_VS__LIMIT_MASK                                                                  0x0000003FL
//SPI_SHADER_PGM_LO_VS
#define SPI_SHADER_PGM_LO_VS__MEM_BASE__SHIFT                                                                 0x0
#define SPI_SHADER_PGM_LO_VS__MEM_BASE_MASK                                                                   0xFFFFFFFFL
//SPI_SHADER_PGM_HI_VS
#define SPI_SHADER_PGM_HI_VS__MEM_BASE__SHIFT                                                                 0x0
#define SPI_SHADER_PGM_HI_VS__MEM_BASE_MASK                                                                   0xFFL
//SPI_SHADER_PGM_RSRC1_VS
#define SPI_SHADER_PGM_RSRC1_VS__VGPRS__SHIFT                                                                 0x0
#define SPI_SHADER_PGM_RSRC1_VS__SGPRS__SHIFT                                                                 0x6
#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY__SHIFT                                                              0xa
#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE__SHIFT                                                            0xc
#define SPI_SHADER_PGM_RSRC1_VS__PRIV__SHIFT                                                                  0x14
#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP__SHIFT                                                            0x15
#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE__SHIFT                                                             0x17
#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT__SHIFT                                                         0x18
#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE__SHIFT                                                       0x1a
#define SPI_SHADER_PGM_RSRC1_VS__MEM_ORDERED__SHIFT                                                           0x1b
#define SPI_SHADER_PGM_RSRC1_VS__FWD_PROGRESS__SHIFT                                                          0x1c
#define SPI_SHADER_PGM_RSRC1_VS__FP16_OVFL__SHIFT                                                             0x1f
#define SPI_SHADER_PGM_RSRC1_VS__VGPRS_MASK                                                                   0x0000003FL
#define SPI_SHADER_PGM_RSRC1_VS__SGPRS_MASK                                                                   0x000003C0L
#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY_MASK                                                                0x00000C00L
#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE_MASK                                                              0x000FF000L
#define SPI_SHADER_PGM_RSRC1_VS__PRIV_MASK                                                                    0x00100000L
#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP_MASK                                                              0x00200000L
#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE_MASK                                                               0x00800000L
#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT_MASK                                                           0x03000000L
#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE_MASK                                                         0x04000000L
#define SPI_SHADER_PGM_RSRC1_VS__MEM_ORDERED_MASK                                                             0x08000000L
#define SPI_SHADER_PGM_RSRC1_VS__FWD_PROGRESS_MASK                                                            0x10000000L
#define SPI_SHADER_PGM_RSRC1_VS__FP16_OVFL_MASK                                                               0x80000000L
//SPI_SHADER_PGM_RSRC2_VS
#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN__SHIFT                                                            0x0
#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR__SHIFT                                                             0x1
#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT__SHIFT                                                          0x6
#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN__SHIFT                                                             0x7
#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN__SHIFT                                                           0x8
#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN__SHIFT                                                           0x9
#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN__SHIFT                                                           0xa
#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN__SHIFT                                                           0xb
#define SPI_SHADER_PGM_RSRC2_VS__SO_EN__SHIFT                                                                 0xc
#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN__SHIFT                                                               0xd
#define SPI_SHADER_PGM_RSRC2_VS__PC_BASE_EN__SHIFT                                                            0x16
#define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN__SHIFT                                                      0x18
#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MSB__SHIFT                                                         0x1b
#define SPI_SHADER_PGM_RSRC2_VS__SHARED_VGPR_CNT__SHIFT                                                       0x1c
#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN_MASK                                                              0x00000001L
#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MASK                                                               0x0000003EL
#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT_MASK                                                            0x00000040L
#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN_MASK                                                               0x00000080L
#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN_MASK                                                             0x00000100L
#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN_MASK                                                             0x00000200L
#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN_MASK                                                             0x00000400L
#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN_MASK                                                             0x00000800L
#define SPI_SHADER_PGM_RSRC2_VS__SO_EN_MASK                                                                   0x00001000L
#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN_MASK                                                                 0x003FE000L
#define SPI_SHADER_PGM_RSRC2_VS__PC_BASE_EN_MASK                                                              0x00400000L
#define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN_MASK                                                        0x01000000L
#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MSB_MASK                                                           0x08000000L
#define SPI_SHADER_PGM_RSRC2_VS__SHARED_VGPR_CNT_MASK                                                         0xF0000000L
//SPI_SHADER_USER_DATA_VS_0
#define SPI_SHADER_USER_DATA_VS_0__DATA__SHIFT                                                                0x0
#define SPI_SHADER_USER_DATA_VS_0__DATA_MASK                                                                  0xFFFFFFFFL
//SPI_SHADER_USER_DATA_VS_1
#define SPI_SHADER_USER_DATA_VS_1__DATA__SHIFT                                                                0x0
#define SPI_SHADER_USER_DATA_VS_1__DATA_MASK                                                                  0xFFFFFFFFL
//SPI_SHADER_USER_DATA_VS_2
#define SPI_SHADER_USER_DATA_VS_2__DATA__SHIFT                                                                0x0
#define SPI_SHADER_USER_DATA_VS_2__DATA_MASK                                                                  0xFFFFFFFFL
//SPI_SHADER_USER_DATA_VS_3
#define SPI_SHADER_USER_DATA_VS_3__DATA__SHIFT                                                                0x0
#define SPI_SHADER_USER_DATA_VS_3__DATA_MASK                                                                  0xFFFFFFFFL
//SPI_SHADER_USER_DATA_VS_4
#define SPI_SHADER_USER_DATA_VS_4__DATA__SHIFT                                                                0x0
#define SPI_SHADER_USER_DATA_VS_4__DATA_MASK                                                                  0xFFFFFFFFL
//SPI_SHADER_USER_DATA_VS_5
#define SPI_SHADER_USER_DATA_VS_5__DATA__SHIFT                                                                0x0
#define SPI_SHADER_USER_DATA_VS_5__DATA_MASK                                                                  0xFFFFFFFFL
//SPI_SHADER_USER_DATA_VS_6
#define SPI_SHADER_USER_DATA_VS_6__DATA__SHIFT                                                                0x0
#define SPI_SHADER_USER_DATA_VS_6__DATA_MASK                                                                  0xFFFFFFFFL
//SPI_SHADER_USER_DATA_VS_7
#define SPI_SHADER_USER_DATA_VS_7__DATA__SHIFT                                                                0x0
#define SPI_SHADER_USER_DATA_VS_7__DATA_MASK                                                                  0xFFFFFFFFL
//SPI_SHADER_USER_DATA_VS_8
#define SPI_SHADER_USER_DATA_VS_8__DATA__SHIFT                                                                0x0
#define SPI_SHADER_USER_DATA_VS_8__DATA_MASK                                                                  0xFFFFFFFFL
//SPI_SHADER_USER_DATA_VS_9
#define SPI_SHADER_USER_DATA_VS_9__DATA__SHIFT                                                                0x0
#define SPI_SHADER_USER_DATA_VS_9__DATA_MASK                                                                  0xFFFFFFFFL
//SPI_SHADER_USER_DATA_VS_10
#define SPI_SHADER_USER_DATA_VS_10__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_VS_10__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_VS_11
#define SPI_SHADER_USER_DATA_VS_11__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_VS_11__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_VS_12
#define SPI_SHADER_USER_DATA_VS_12__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_VS_12__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_VS_13
#define SPI_SHADER_USER_DATA_VS_13__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_VS_13__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_VS_14
#define SPI_SHADER_USER_DATA_VS_14__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_VS_14__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_VS_15
#define SPI_SHADER_USER_DATA_VS_15__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_VS_15__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_VS_16
#define SPI_SHADER_USER_DATA_VS_16__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_VS_16__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_VS_17
#define SPI_SHADER_USER_DATA_VS_17__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_VS_17__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_VS_18
#define SPI_SHADER_USER_DATA_VS_18__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_VS_18__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_VS_19
#define SPI_SHADER_USER_DATA_VS_19__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_VS_19__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_VS_20
#define SPI_SHADER_USER_DATA_VS_20__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_VS_20__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_VS_21
#define SPI_SHADER_USER_DATA_VS_21__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_VS_21__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_VS_22
#define SPI_SHADER_USER_DATA_VS_22__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_VS_22__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_VS_23
#define SPI_SHADER_USER_DATA_VS_23__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_VS_23__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_VS_24
#define SPI_SHADER_USER_DATA_VS_24__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_VS_24__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_VS_25
#define SPI_SHADER_USER_DATA_VS_25__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_VS_25__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_VS_26
#define SPI_SHADER_USER_DATA_VS_26__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_VS_26__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_VS_27
#define SPI_SHADER_USER_DATA_VS_27__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_VS_27__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_VS_28
#define SPI_SHADER_USER_DATA_VS_28__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_VS_28__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_VS_29
#define SPI_SHADER_USER_DATA_VS_29__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_VS_29__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_VS_30
#define SPI_SHADER_USER_DATA_VS_30__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_VS_30__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_VS_31
#define SPI_SHADER_USER_DATA_VS_31__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_VS_31__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_REQ_CTRL_VS
#define SPI_SHADER_REQ_CTRL_VS__SOFT_GROUPING_EN__SHIFT                                                       0x0
#define SPI_SHADER_REQ_CTRL_VS__NUMBER_OF_REQUESTS_PER_CU__SHIFT                                              0x1
#define SPI_SHADER_REQ_CTRL_VS__SOFT_GROUPING_ALLOCATION_TIMEOUT__SHIFT                                       0x5
#define SPI_SHADER_REQ_CTRL_VS__HARD_LOCK_HYSTERESIS__SHIFT                                                   0x9
#define SPI_SHADER_REQ_CTRL_VS__HARD_LOCK_LOW_THRESHOLD__SHIFT                                                0xa
#define SPI_SHADER_REQ_CTRL_VS__PRODUCER_REQUEST_LOCKOUT__SHIFT                                               0xf
#define SPI_SHADER_REQ_CTRL_VS__GLOBAL_SCANNING_EN__SHIFT                                                     0x10
#define SPI_SHADER_REQ_CTRL_VS__ALLOCATION_RATE_THROTTLING_THRESHOLD__SHIFT                                   0x11
#define SPI_SHADER_REQ_CTRL_VS__SOFT_GROUPING_EN_MASK                                                         0x00000001L
#define SPI_SHADER_REQ_CTRL_VS__NUMBER_OF_REQUESTS_PER_CU_MASK                                                0x0000001EL
#define SPI_SHADER_REQ_CTRL_VS__SOFT_GROUPING_ALLOCATION_TIMEOUT_MASK                                         0x000001E0L
#define SPI_SHADER_REQ_CTRL_VS__HARD_LOCK_HYSTERESIS_MASK                                                     0x00000200L
#define SPI_SHADER_REQ_CTRL_VS__HARD_LOCK_LOW_THRESHOLD_MASK                                                  0x00007C00L
#define SPI_SHADER_REQ_CTRL_VS__PRODUCER_REQUEST_LOCKOUT_MASK                                                 0x00008000L
#define SPI_SHADER_REQ_CTRL_VS__GLOBAL_SCANNING_EN_MASK                                                       0x00010000L
#define SPI_SHADER_REQ_CTRL_VS__ALLOCATION_RATE_THROTTLING_THRESHOLD_MASK                                     0x000E0000L
//SPI_SHADER_USER_ACCUM_VS_0
#define SPI_SHADER_USER_ACCUM_VS_0__CONTRIBUTION__SHIFT                                                       0x0
#define SPI_SHADER_USER_ACCUM_VS_0__CONTRIBUTION_MASK                                                         0x0000007FL
//SPI_SHADER_USER_ACCUM_VS_1
#define SPI_SHADER_USER_ACCUM_VS_1__CONTRIBUTION__SHIFT                                                       0x0
#define SPI_SHADER_USER_ACCUM_VS_1__CONTRIBUTION_MASK                                                         0x0000007FL
//SPI_SHADER_USER_ACCUM_VS_2
#define SPI_SHADER_USER_ACCUM_VS_2__CONTRIBUTION__SHIFT                                                       0x0
#define SPI_SHADER_USER_ACCUM_VS_2__CONTRIBUTION_MASK                                                         0x0000007FL
//SPI_SHADER_USER_ACCUM_VS_3
#define SPI_SHADER_USER_ACCUM_VS_3__CONTRIBUTION__SHIFT                                                       0x0
#define SPI_SHADER_USER_ACCUM_VS_3__CONTRIBUTION_MASK                                                         0x0000007FL
//SPI_SHADER_PGM_RSRC2_GS_VS
#define SPI_SHADER_PGM_RSRC2_GS_VS__SCRATCH_EN__SHIFT                                                         0x0
#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR__SHIFT                                                          0x1
#define SPI_SHADER_PGM_RSRC2_GS_VS__TRAP_PRESENT__SHIFT                                                       0x6
#define SPI_SHADER_PGM_RSRC2_GS_VS__EXCP_EN__SHIFT                                                            0x7
#define SPI_SHADER_PGM_RSRC2_GS_VS__VGPR_COMP_CNT__SHIFT                                                      0x10
#define SPI_SHADER_PGM_RSRC2_GS_VS__OC_LDS_EN__SHIFT                                                          0x12
#define SPI_SHADER_PGM_RSRC2_GS_VS__LDS_SIZE__SHIFT                                                           0x13
#define SPI_SHADER_PGM_RSRC2_GS_VS__SKIP_USGPR0__SHIFT                                                        0x1b
#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MSB__SHIFT                                                      0x1c
#define SPI_SHADER_PGM_RSRC2_GS_VS__SCRATCH_EN_MASK                                                           0x00000001L
#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MASK                                                            0x0000003EL
#define SPI_SHADER_PGM_RSRC2_GS_VS__TRAP_PRESENT_MASK                                                         0x00000040L
#define SPI_SHADER_PGM_RSRC2_GS_VS__EXCP_EN_MASK                                                              0x0000FF80L
#define SPI_SHADER_PGM_RSRC2_GS_VS__VGPR_COMP_CNT_MASK                                                        0x00030000L
#define SPI_SHADER_PGM_RSRC2_GS_VS__OC_LDS_EN_MASK                                                            0x00040000L
#define SPI_SHADER_PGM_RSRC2_GS_VS__LDS_SIZE_MASK                                                             0x07F80000L
#define SPI_SHADER_PGM_RSRC2_GS_VS__SKIP_USGPR0_MASK                                                          0x08000000L
#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MSB_MASK                                                        0x10000000L
//SPI_SHADER_PGM_CHKSUM_GS
#define SPI_SHADER_PGM_CHKSUM_GS__CHECKSUM__SHIFT                                                             0x0
#define SPI_SHADER_PGM_CHKSUM_GS__CHECKSUM_MASK                                                               0xFFFFFFFFL
//SPI_SHADER_PGM_RSRC4_GS
#define SPI_SHADER_PGM_RSRC4_GS__CU_EN__SHIFT                                                                 0x0
#define SPI_SHADER_PGM_RSRC4_GS__SPI_SHADER_LATE_ALLOC_GS__SHIFT                                              0x10
#define SPI_SHADER_PGM_RSRC4_GS__CU_EN_MASK                                                                   0x0000FFFFL
#define SPI_SHADER_PGM_RSRC4_GS__SPI_SHADER_LATE_ALLOC_GS_MASK                                                0x007F0000L
//SPI_SHADER_USER_DATA_ADDR_LO_GS
#define SPI_SHADER_USER_DATA_ADDR_LO_GS__MEM_BASE__SHIFT                                                      0x0
#define SPI_SHADER_USER_DATA_ADDR_LO_GS__MEM_BASE_MASK                                                        0xFFFFFFFFL
//SPI_SHADER_USER_DATA_ADDR_HI_GS
#define SPI_SHADER_USER_DATA_ADDR_HI_GS__MEM_BASE__SHIFT                                                      0x0
#define SPI_SHADER_USER_DATA_ADDR_HI_GS__MEM_BASE_MASK                                                        0xFFFFFFFFL
//SPI_SHADER_PGM_LO_ES_GS
#define SPI_SHADER_PGM_LO_ES_GS__MEM_BASE__SHIFT                                                              0x0
#define SPI_SHADER_PGM_LO_ES_GS__MEM_BASE_MASK                                                                0xFFFFFFFFL
//SPI_SHADER_PGM_HI_ES_GS
#define SPI_SHADER_PGM_HI_ES_GS__MEM_BASE__SHIFT                                                              0x0
#define SPI_SHADER_PGM_HI_ES_GS__MEM_BASE_MASK                                                                0xFFL
//SPI_SHADER_PGM_RSRC3_GS
#define SPI_SHADER_PGM_RSRC3_GS__CU_EN__SHIFT                                                                 0x0
#define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT__SHIFT                                                            0x10
#define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD__SHIFT                                                    0x16
#define SPI_SHADER_PGM_RSRC3_GS__GROUP_FIFO_DEPTH__SHIFT                                                      0x1a
#define SPI_SHADER_PGM_RSRC3_GS__CU_EN_MASK                                                                   0x0000FFFFL
#define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT_MASK                                                              0x003F0000L
#define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD_MASK                                                      0x03C00000L
#define SPI_SHADER_PGM_RSRC3_GS__GROUP_FIFO_DEPTH_MASK                                                        0xFC000000L
//SPI_SHADER_PGM_LO_GS
#define SPI_SHADER_PGM_LO_GS__MEM_BASE__SHIFT                                                                 0x0
#define SPI_SHADER_PGM_LO_GS__MEM_BASE_MASK                                                                   0xFFFFFFFFL
//SPI_SHADER_PGM_HI_GS
#define SPI_SHADER_PGM_HI_GS__MEM_BASE__SHIFT                                                                 0x0
#define SPI_SHADER_PGM_HI_GS__MEM_BASE_MASK                                                                   0xFFL
//SPI_SHADER_PGM_RSRC1_GS
#define SPI_SHADER_PGM_RSRC1_GS__VGPRS__SHIFT                                                                 0x0
#define SPI_SHADER_PGM_RSRC1_GS__SGPRS__SHIFT                                                                 0x6
#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY__SHIFT                                                              0xa
#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE__SHIFT                                                            0xc
#define SPI_SHADER_PGM_RSRC1_GS__PRIV__SHIFT                                                                  0x14
#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP__SHIFT                                                            0x15
#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE__SHIFT                                                             0x17
#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE__SHIFT                                                       0x18
#define SPI_SHADER_PGM_RSRC1_GS__MEM_ORDERED__SHIFT                                                           0x19
#define SPI_SHADER_PGM_RSRC1_GS__FWD_PROGRESS__SHIFT                                                          0x1a
#define SPI_SHADER_PGM_RSRC1_GS__WGP_MODE__SHIFT                                                              0x1b
#define SPI_SHADER_PGM_RSRC1_GS__GS_VGPR_COMP_CNT__SHIFT                                                      0x1d
#define SPI_SHADER_PGM_RSRC1_GS__FP16_OVFL__SHIFT                                                             0x1f
#define SPI_SHADER_PGM_RSRC1_GS__VGPRS_MASK                                                                   0x0000003FL
#define SPI_SHADER_PGM_RSRC1_GS__SGPRS_MASK                                                                   0x000003C0L
#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY_MASK                                                                0x00000C00L
#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE_MASK                                                              0x000FF000L
#define SPI_SHADER_PGM_RSRC1_GS__PRIV_MASK                                                                    0x00100000L
#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP_MASK                                                              0x00200000L
#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE_MASK                                                               0x00800000L
#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE_MASK                                                         0x01000000L
#define SPI_SHADER_PGM_RSRC1_GS__MEM_ORDERED_MASK                                                             0x02000000L
#define SPI_SHADER_PGM_RSRC1_GS__FWD_PROGRESS_MASK                                                            0x04000000L
#define SPI_SHADER_PGM_RSRC1_GS__WGP_MODE_MASK                                                                0x08000000L
#define SPI_SHADER_PGM_RSRC1_GS__GS_VGPR_COMP_CNT_MASK                                                        0x60000000L
#define SPI_SHADER_PGM_RSRC1_GS__FP16_OVFL_MASK                                                               0x80000000L
//SPI_SHADER_PGM_RSRC2_GS
#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN__SHIFT                                                            0x0
#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR__SHIFT                                                             0x1
#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT__SHIFT                                                          0x6
#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN__SHIFT                                                               0x7
#define SPI_SHADER_PGM_RSRC2_GS__ES_VGPR_COMP_CNT__SHIFT                                                      0x10
#define SPI_SHADER_PGM_RSRC2_GS__OC_LDS_EN__SHIFT                                                             0x12
#define SPI_SHADER_PGM_RSRC2_GS__LDS_SIZE__SHIFT                                                              0x13
#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MSB__SHIFT                                                         0x1b
#define SPI_SHADER_PGM_RSRC2_GS__SHARED_VGPR_CNT__SHIFT                                                       0x1c
#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN_MASK                                                              0x00000001L
#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MASK                                                               0x0000003EL
#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT_MASK                                                            0x00000040L
#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN_MASK                                                                 0x0000FF80L
#define SPI_SHADER_PGM_RSRC2_GS__ES_VGPR_COMP_CNT_MASK                                                        0x00030000L
#define SPI_SHADER_PGM_RSRC2_GS__OC_LDS_EN_MASK                                                               0x00040000L
#define SPI_SHADER_PGM_RSRC2_GS__LDS_SIZE_MASK                                                                0x07F80000L
#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MSB_MASK                                                           0x08000000L
#define SPI_SHADER_PGM_RSRC2_GS__SHARED_VGPR_CNT_MASK                                                         0xF0000000L
//SPI_SHADER_USER_DATA_GS_0
#define SPI_SHADER_USER_DATA_GS_0__DATA__SHIFT                                                                0x0
#define SPI_SHADER_USER_DATA_GS_0__DATA_MASK                                                                  0xFFFFFFFFL
//SPI_SHADER_USER_DATA_GS_1
#define SPI_SHADER_USER_DATA_GS_1__DATA__SHIFT                                                                0x0
#define SPI_SHADER_USER_DATA_GS_1__DATA_MASK                                                                  0xFFFFFFFFL
//SPI_SHADER_USER_DATA_GS_2
#define SPI_SHADER_USER_DATA_GS_2__DATA__SHIFT                                                                0x0
#define SPI_SHADER_USER_DATA_GS_2__DATA_MASK                                                                  0xFFFFFFFFL
//SPI_SHADER_USER_DATA_GS_3
#define SPI_SHADER_USER_DATA_GS_3__DATA__SHIFT                                                                0x0
#define SPI_SHADER_USER_DATA_GS_3__DATA_MASK                                                                  0xFFFFFFFFL
//SPI_SHADER_USER_DATA_GS_4
#define SPI_SHADER_USER_DATA_GS_4__DATA__SHIFT                                                                0x0
#define SPI_SHADER_USER_DATA_GS_4__DATA_MASK                                                                  0xFFFFFFFFL
//SPI_SHADER_USER_DATA_GS_5
#define SPI_SHADER_USER_DATA_GS_5__DATA__SHIFT                                                                0x0
#define SPI_SHADER_USER_DATA_GS_5__DATA_MASK                                                                  0xFFFFFFFFL
//SPI_SHADER_USER_DATA_GS_6
#define SPI_SHADER_USER_DATA_GS_6__DATA__SHIFT                                                                0x0
#define SPI_SHADER_USER_DATA_GS_6__DATA_MASK                                                                  0xFFFFFFFFL
//SPI_SHADER_USER_DATA_GS_7
#define SPI_SHADER_USER_DATA_GS_7__DATA__SHIFT                                                                0x0
#define SPI_SHADER_USER_DATA_GS_7__DATA_MASK                                                                  0xFFFFFFFFL
//SPI_SHADER_USER_DATA_GS_8
#define SPI_SHADER_USER_DATA_GS_8__DATA__SHIFT                                                                0x0
#define SPI_SHADER_USER_DATA_GS_8__DATA_MASK                                                                  0xFFFFFFFFL
//SPI_SHADER_USER_DATA_GS_9
#define SPI_SHADER_USER_DATA_GS_9__DATA__SHIFT                                                                0x0
#define SPI_SHADER_USER_DATA_GS_9__DATA_MASK                                                                  0xFFFFFFFFL
//SPI_SHADER_USER_DATA_GS_10
#define SPI_SHADER_USER_DATA_GS_10__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_GS_10__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_GS_11
#define SPI_SHADER_USER_DATA_GS_11__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_GS_11__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_GS_12
#define SPI_SHADER_USER_DATA_GS_12__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_GS_12__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_GS_13
#define SPI_SHADER_USER_DATA_GS_13__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_GS_13__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_GS_14
#define SPI_SHADER_USER_DATA_GS_14__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_GS_14__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_GS_15
#define SPI_SHADER_USER_DATA_GS_15__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_GS_15__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_GS_16
#define SPI_SHADER_USER_DATA_GS_16__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_GS_16__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_GS_17
#define SPI_SHADER_USER_DATA_GS_17__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_GS_17__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_GS_18
#define SPI_SHADER_USER_DATA_GS_18__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_GS_18__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_GS_19
#define SPI_SHADER_USER_DATA_GS_19__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_GS_19__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_GS_20
#define SPI_SHADER_USER_DATA_GS_20__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_GS_20__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_GS_21
#define SPI_SHADER_USER_DATA_GS_21__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_GS_21__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_GS_22
#define SPI_SHADER_USER_DATA_GS_22__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_GS_22__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_GS_23
#define SPI_SHADER_USER_DATA_GS_23__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_GS_23__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_GS_24
#define SPI_SHADER_USER_DATA_GS_24__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_GS_24__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_GS_25
#define SPI_SHADER_USER_DATA_GS_25__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_GS_25__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_GS_26
#define SPI_SHADER_USER_DATA_GS_26__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_GS_26__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_GS_27
#define SPI_SHADER_USER_DATA_GS_27__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_GS_27__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_GS_28
#define SPI_SHADER_USER_DATA_GS_28__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_GS_28__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_GS_29
#define SPI_SHADER_USER_DATA_GS_29__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_GS_29__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_GS_30
#define SPI_SHADER_USER_DATA_GS_30__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_GS_30__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_GS_31
#define SPI_SHADER_USER_DATA_GS_31__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_GS_31__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_REQ_CTRL_ESGS
#define SPI_SHADER_REQ_CTRL_ESGS__SOFT_GROUPING_EN__SHIFT                                                     0x0
#define SPI_SHADER_REQ_CTRL_ESGS__NUMBER_OF_REQUESTS_PER_CU__SHIFT                                            0x1
#define SPI_SHADER_REQ_CTRL_ESGS__SOFT_GROUPING_ALLOCATION_TIMEOUT__SHIFT                                     0x5
#define SPI_SHADER_REQ_CTRL_ESGS__HARD_LOCK_HYSTERESIS__SHIFT                                                 0x9
#define SPI_SHADER_REQ_CTRL_ESGS__HARD_LOCK_LOW_THRESHOLD__SHIFT                                              0xa
#define SPI_SHADER_REQ_CTRL_ESGS__PRODUCER_REQUEST_LOCKOUT__SHIFT                                             0xf
#define SPI_SHADER_REQ_CTRL_ESGS__GLOBAL_SCANNING_EN__SHIFT                                                   0x10
#define SPI_SHADER_REQ_CTRL_ESGS__ALLOCATION_RATE_THROTTLING_THRESHOLD__SHIFT                                 0x11
#define SPI_SHADER_REQ_CTRL_ESGS__SOFT_GROUPING_EN_MASK                                                       0x00000001L
#define SPI_SHADER_REQ_CTRL_ESGS__NUMBER_OF_REQUESTS_PER_CU_MASK                                              0x0000001EL
#define SPI_SHADER_REQ_CTRL_ESGS__SOFT_GROUPING_ALLOCATION_TIMEOUT_MASK                                       0x000001E0L
#define SPI_SHADER_REQ_CTRL_ESGS__HARD_LOCK_HYSTERESIS_MASK                                                   0x00000200L
#define SPI_SHADER_REQ_CTRL_ESGS__HARD_LOCK_LOW_THRESHOLD_MASK                                                0x00007C00L
#define SPI_SHADER_REQ_CTRL_ESGS__PRODUCER_REQUEST_LOCKOUT_MASK                                               0x00008000L
#define SPI_SHADER_REQ_CTRL_ESGS__GLOBAL_SCANNING_EN_MASK                                                     0x00010000L
#define SPI_SHADER_REQ_CTRL_ESGS__ALLOCATION_RATE_THROTTLING_THRESHOLD_MASK                                   0x000E0000L
//SPI_SHADER_USER_ACCUM_ESGS_0
#define SPI_SHADER_USER_ACCUM_ESGS_0__CONTRIBUTION__SHIFT                                                     0x0
#define SPI_SHADER_USER_ACCUM_ESGS_0__CONTRIBUTION_MASK                                                       0x0000007FL
//SPI_SHADER_USER_ACCUM_ESGS_1
#define SPI_SHADER_USER_ACCUM_ESGS_1__CONTRIBUTION__SHIFT                                                     0x0
#define SPI_SHADER_USER_ACCUM_ESGS_1__CONTRIBUTION_MASK                                                       0x0000007FL
//SPI_SHADER_USER_ACCUM_ESGS_2
#define SPI_SHADER_USER_ACCUM_ESGS_2__CONTRIBUTION__SHIFT                                                     0x0
#define SPI_SHADER_USER_ACCUM_ESGS_2__CONTRIBUTION_MASK                                                       0x0000007FL
//SPI_SHADER_USER_ACCUM_ESGS_3
#define SPI_SHADER_USER_ACCUM_ESGS_3__CONTRIBUTION__SHIFT                                                     0x0
#define SPI_SHADER_USER_ACCUM_ESGS_3__CONTRIBUTION_MASK                                                       0x0000007FL
//SPI_SHADER_PGM_LO_ES
#define SPI_SHADER_PGM_LO_ES__MEM_BASE__SHIFT                                                                 0x0
#define SPI_SHADER_PGM_LO_ES__MEM_BASE_MASK                                                                   0xFFFFFFFFL
//SPI_SHADER_PGM_HI_ES
#define SPI_SHADER_PGM_HI_ES__MEM_BASE__SHIFT                                                                 0x0
#define SPI_SHADER_PGM_HI_ES__MEM_BASE_MASK                                                                   0xFFL
//SPI_SHADER_PGM_CHKSUM_HS
#define SPI_SHADER_PGM_CHKSUM_HS__CHECKSUM__SHIFT                                                             0x0
#define SPI_SHADER_PGM_CHKSUM_HS__CHECKSUM_MASK                                                               0xFFFFFFFFL
//SPI_SHADER_PGM_RSRC4_HS
#define SPI_SHADER_PGM_RSRC4_HS__CU_EN__SHIFT                                                                 0x0
#define SPI_SHADER_PGM_RSRC4_HS__CU_EN_MASK                                                                   0x0000FFFFL
//SPI_SHADER_USER_DATA_ADDR_LO_HS
#define SPI_SHADER_USER_DATA_ADDR_LO_HS__MEM_BASE__SHIFT                                                      0x0
#define SPI_SHADER_USER_DATA_ADDR_LO_HS__MEM_BASE_MASK                                                        0xFFFFFFFFL
//SPI_SHADER_USER_DATA_ADDR_HI_HS
#define SPI_SHADER_USER_DATA_ADDR_HI_HS__MEM_BASE__SHIFT                                                      0x0
#define SPI_SHADER_USER_DATA_ADDR_HI_HS__MEM_BASE_MASK                                                        0xFFFFFFFFL
//SPI_SHADER_PGM_LO_LS_HS
#define SPI_SHADER_PGM_LO_LS_HS__MEM_BASE__SHIFT                                                              0x0
#define SPI_SHADER_PGM_LO_LS_HS__MEM_BASE_MASK                                                                0xFFFFFFFFL
//SPI_SHADER_PGM_HI_LS_HS
#define SPI_SHADER_PGM_HI_LS_HS__MEM_BASE__SHIFT                                                              0x0
#define SPI_SHADER_PGM_HI_LS_HS__MEM_BASE_MASK                                                                0xFFL
//SPI_SHADER_PGM_RSRC3_HS
#define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT__SHIFT                                                            0x0
#define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD__SHIFT                                                    0x6
#define SPI_SHADER_PGM_RSRC3_HS__GROUP_FIFO_DEPTH__SHIFT                                                      0xa
#define SPI_SHADER_PGM_RSRC3_HS__CU_EN__SHIFT                                                                 0x10
#define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT_MASK                                                              0x0000003FL
#define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD_MASK                                                      0x000003C0L
#define SPI_SHADER_PGM_RSRC3_HS__GROUP_FIFO_DEPTH_MASK                                                        0x0000FC00L
#define SPI_SHADER_PGM_RSRC3_HS__CU_EN_MASK                                                                   0xFFFF0000L
//SPI_SHADER_PGM_LO_HS
#define SPI_SHADER_PGM_LO_HS__MEM_BASE__SHIFT                                                                 0x0
#define SPI_SHADER_PGM_LO_HS__MEM_BASE_MASK                                                                   0xFFFFFFFFL
//SPI_SHADER_PGM_HI_HS
#define SPI_SHADER_PGM_HI_HS__MEM_BASE__SHIFT                                                                 0x0
#define SPI_SHADER_PGM_HI_HS__MEM_BASE_MASK                                                                   0xFFL
//SPI_SHADER_PGM_RSRC1_HS
#define SPI_SHADER_PGM_RSRC1_HS__VGPRS__SHIFT                                                                 0x0
#define SPI_SHADER_PGM_RSRC1_HS__SGPRS__SHIFT                                                                 0x6
#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY__SHIFT                                                              0xa
#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE__SHIFT                                                            0xc
#define SPI_SHADER_PGM_RSRC1_HS__PRIV__SHIFT                                                                  0x14
#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP__SHIFT                                                            0x15
#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE__SHIFT                                                             0x17
#define SPI_SHADER_PGM_RSRC1_HS__MEM_ORDERED__SHIFT                                                           0x18
#define SPI_SHADER_PGM_RSRC1_HS__FWD_PROGRESS__SHIFT                                                          0x19
#define SPI_SHADER_PGM_RSRC1_HS__WGP_MODE__SHIFT                                                              0x1a
#define SPI_SHADER_PGM_RSRC1_HS__LS_VGPR_COMP_CNT__SHIFT                                                      0x1c
#define SPI_SHADER_PGM_RSRC1_HS__FP16_OVFL__SHIFT                                                             0x1e
#define SPI_SHADER_PGM_RSRC1_HS__VGPRS_MASK                                                                   0x0000003FL
#define SPI_SHADER_PGM_RSRC1_HS__SGPRS_MASK                                                                   0x000003C0L
#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY_MASK                                                                0x00000C00L
#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE_MASK                                                              0x000FF000L
#define SPI_SHADER_PGM_RSRC1_HS__PRIV_MASK                                                                    0x00100000L
#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP_MASK                                                              0x00200000L
#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE_MASK                                                               0x00800000L
#define SPI_SHADER_PGM_RSRC1_HS__MEM_ORDERED_MASK                                                             0x01000000L
#define SPI_SHADER_PGM_RSRC1_HS__FWD_PROGRESS_MASK                                                            0x02000000L
#define SPI_SHADER_PGM_RSRC1_HS__WGP_MODE_MASK                                                                0x04000000L
#define SPI_SHADER_PGM_RSRC1_HS__LS_VGPR_COMP_CNT_MASK                                                        0x30000000L
#define SPI_SHADER_PGM_RSRC1_HS__FP16_OVFL_MASK                                                               0x40000000L
//SPI_SHADER_PGM_RSRC2_HS
#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN__SHIFT                                                            0x0
#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR__SHIFT                                                             0x1
#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT__SHIFT                                                          0x6
#define SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN__SHIFT                                                             0x7
#define SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN__SHIFT                                                            0x8
#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN__SHIFT                                                               0x9
#define SPI_SHADER_PGM_RSRC2_HS__LDS_SIZE__SHIFT                                                              0x12
#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MSB__SHIFT                                                         0x1b
#define SPI_SHADER_PGM_RSRC2_HS__SHARED_VGPR_CNT__SHIFT                                                       0x1c
#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN_MASK                                                              0x00000001L
#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MASK                                                               0x0000003EL
#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT_MASK                                                            0x00000040L
#define SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN_MASK                                                               0x00000080L
#define SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN_MASK                                                              0x00000100L
#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN_MASK                                                                 0x0003FE00L
#define SPI_SHADER_PGM_RSRC2_HS__LDS_SIZE_MASK                                                                0x07FC0000L
#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MSB_MASK                                                           0x08000000L
#define SPI_SHADER_PGM_RSRC2_HS__SHARED_VGPR_CNT_MASK                                                         0xF0000000L
//SPI_SHADER_USER_DATA_HS_0
#define SPI_SHADER_USER_DATA_HS_0__DATA__SHIFT                                                                0x0
#define SPI_SHADER_USER_DATA_HS_0__DATA_MASK                                                                  0xFFFFFFFFL
//SPI_SHADER_USER_DATA_HS_1
#define SPI_SHADER_USER_DATA_HS_1__DATA__SHIFT                                                                0x0
#define SPI_SHADER_USER_DATA_HS_1__DATA_MASK                                                                  0xFFFFFFFFL
//SPI_SHADER_USER_DATA_HS_2
#define SPI_SHADER_USER_DATA_HS_2__DATA__SHIFT                                                                0x0
#define SPI_SHADER_USER_DATA_HS_2__DATA_MASK                                                                  0xFFFFFFFFL
//SPI_SHADER_USER_DATA_HS_3
#define SPI_SHADER_USER_DATA_HS_3__DATA__SHIFT                                                                0x0
#define SPI_SHADER_USER_DATA_HS_3__DATA_MASK                                                                  0xFFFFFFFFL
//SPI_SHADER_USER_DATA_HS_4
#define SPI_SHADER_USER_DATA_HS_4__DATA__SHIFT                                                                0x0
#define SPI_SHADER_USER_DATA_HS_4__DATA_MASK                                                                  0xFFFFFFFFL
//SPI_SHADER_USER_DATA_HS_5
#define SPI_SHADER_USER_DATA_HS_5__DATA__SHIFT                                                                0x0
#define SPI_SHADER_USER_DATA_HS_5__DATA_MASK                                                                  0xFFFFFFFFL
//SPI_SHADER_USER_DATA_HS_6
#define SPI_SHADER_USER_DATA_HS_6__DATA__SHIFT                                                                0x0
#define SPI_SHADER_USER_DATA_HS_6__DATA_MASK                                                                  0xFFFFFFFFL
//SPI_SHADER_USER_DATA_HS_7
#define SPI_SHADER_USER_DATA_HS_7__DATA__SHIFT                                                                0x0
#define SPI_SHADER_USER_DATA_HS_7__DATA_MASK                                                                  0xFFFFFFFFL
//SPI_SHADER_USER_DATA_HS_8
#define SPI_SHADER_USER_DATA_HS_8__DATA__SHIFT                                                                0x0
#define SPI_SHADER_USER_DATA_HS_8__DATA_MASK                                                                  0xFFFFFFFFL
//SPI_SHADER_USER_DATA_HS_9
#define SPI_SHADER_USER_DATA_HS_9__DATA__SHIFT                                                                0x0
#define SPI_SHADER_USER_DATA_HS_9__DATA_MASK                                                                  0xFFFFFFFFL
//SPI_SHADER_USER_DATA_HS_10
#define SPI_SHADER_USER_DATA_HS_10__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_HS_10__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_HS_11
#define SPI_SHADER_USER_DATA_HS_11__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_HS_11__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_HS_12
#define SPI_SHADER_USER_DATA_HS_12__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_HS_12__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_HS_13
#define SPI_SHADER_USER_DATA_HS_13__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_HS_13__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_HS_14
#define SPI_SHADER_USER_DATA_HS_14__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_HS_14__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_HS_15
#define SPI_SHADER_USER_DATA_HS_15__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_HS_15__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_HS_16
#define SPI_SHADER_USER_DATA_HS_16__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_HS_16__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_HS_17
#define SPI_SHADER_USER_DATA_HS_17__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_HS_17__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_HS_18
#define SPI_SHADER_USER_DATA_HS_18__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_HS_18__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_HS_19
#define SPI_SHADER_USER_DATA_HS_19__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_HS_19__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_HS_20
#define SPI_SHADER_USER_DATA_HS_20__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_HS_20__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_HS_21
#define SPI_SHADER_USER_DATA_HS_21__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_HS_21__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_HS_22
#define SPI_SHADER_USER_DATA_HS_22__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_HS_22__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_HS_23
#define SPI_SHADER_USER_DATA_HS_23__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_HS_23__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_HS_24
#define SPI_SHADER_USER_DATA_HS_24__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_HS_24__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_HS_25
#define SPI_SHADER_USER_DATA_HS_25__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_HS_25__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_HS_26
#define SPI_SHADER_USER_DATA_HS_26__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_HS_26__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_HS_27
#define SPI_SHADER_USER_DATA_HS_27__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_HS_27__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_HS_28
#define SPI_SHADER_USER_DATA_HS_28__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_HS_28__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_HS_29
#define SPI_SHADER_USER_DATA_HS_29__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_HS_29__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_HS_30
#define SPI_SHADER_USER_DATA_HS_30__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_HS_30__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_USER_DATA_HS_31
#define SPI_SHADER_USER_DATA_HS_31__DATA__SHIFT                                                               0x0
#define SPI_SHADER_USER_DATA_HS_31__DATA_MASK                                                                 0xFFFFFFFFL
//SPI_SHADER_REQ_CTRL_LSHS
#define SPI_SHADER_REQ_CTRL_LSHS__SOFT_GROUPING_EN__SHIFT                                                     0x0
#define SPI_SHADER_REQ_CTRL_LSHS__NUMBER_OF_REQUESTS_PER_CU__SHIFT                                            0x1
#define SPI_SHADER_REQ_CTRL_LSHS__SOFT_GROUPING_ALLOCATION_TIMEOUT__SHIFT                                     0x5
#define SPI_SHADER_REQ_CTRL_LSHS__HARD_LOCK_HYSTERESIS__SHIFT                                                 0x9
#define SPI_SHADER_REQ_CTRL_LSHS__HARD_LOCK_LOW_THRESHOLD__SHIFT                                              0xa
#define SPI_SHADER_REQ_CTRL_LSHS__PRODUCER_REQUEST_LOCKOUT__SHIFT                                             0xf
#define SPI_SHADER_REQ_CTRL_LSHS__GLOBAL_SCANNING_EN__SHIFT                                                   0x10
#define SPI_SHADER_REQ_CTRL_LSHS__ALLOCATION_RATE_THROTTLING_THRESHOLD__SHIFT                                 0x11
#define SPI_SHADER_REQ_CTRL_LSHS__SOFT_GROUPING_EN_MASK                                                       0x00000001L
#define SPI_SHADER_REQ_CTRL_LSHS__NUMBER_OF_REQUESTS_PER_CU_MASK                                              0x0000001EL
#define SPI_SHADER_REQ_CTRL_LSHS__SOFT_GROUPING_ALLOCATION_TIMEOUT_MASK                                       0x000001E0L
#define SPI_SHADER_REQ_CTRL_LSHS__HARD_LOCK_HYSTERESIS_MASK                                                   0x00000200L
#define SPI_SHADER_REQ_CTRL_LSHS__HARD_LOCK_LOW_THRESHOLD_MASK                                                0x00007C00L
#define SPI_SHADER_REQ_CTRL_LSHS__PRODUCER_REQUEST_LOCKOUT_MASK                                               0x00008000L
#define SPI_SHADER_REQ_CTRL_LSHS__GLOBAL_SCANNING_EN_MASK                                                     0x00010000L
#define SPI_SHADER_REQ_CTRL_LSHS__ALLOCATION_RATE_THROTTLING_THRESHOLD_MASK                                   0x000E0000L
//SPI_SHADER_USER_ACCUM_LSHS_0
#define SPI_SHADER_USER_ACCUM_LSHS_0__CONTRIBUTION__SHIFT                                                     0x0
#define SPI_SHADER_USER_ACCUM_LSHS_0__CONTRIBUTION_MASK                                                       0x0000007FL
//SPI_SHADER_USER_ACCUM_LSHS_1
#define SPI_SHADER_USER_ACCUM_LSHS_1__CONTRIBUTION__SHIFT                                                     0x0
#define SPI_SHADER_USER_ACCUM_LSHS_1__CONTRIBUTION_MASK                                                       0x0000007FL
//SPI_SHADER_USER_ACCUM_LSHS_2
#define SPI_SHADER_USER_ACCUM_LSHS_2__CONTRIBUTION__SHIFT                                                     0x0
#define SPI_SHADER_USER_ACCUM_LSHS_2__CONTRIBUTION_MASK                                                       0x0000007FL
//SPI_SHADER_USER_ACCUM_LSHS_3
#define SPI_SHADER_USER_ACCUM_LSHS_3__CONTRIBUTION__SHIFT                                                     0x0
#define SPI_SHADER_USER_ACCUM_LSHS_3__CONTRIBUTION_MASK                                                       0x0000007FL
//SPI_SHADER_PGM_LO_LS
#define SPI_SHADER_PGM_LO_LS__MEM_BASE__SHIFT                                                                 0x0
#define SPI_SHADER_PGM_LO_LS__MEM_BASE_MASK                                                                   0xFFFFFFFFL
//SPI_SHADER_PGM_HI_LS
#define SPI_SHADER_PGM_HI_LS__MEM_BASE__SHIFT                                                                 0x0
#define SPI_SHADER_PGM_HI_LS__MEM_BASE_MASK                                                                   0xFFL
//COMPUTE_DISPATCH_INITIATOR
#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN__SHIFT                                                  0x0
#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN__SHIFT                                                      0x1
#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000__SHIFT                                                 0x2
#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL__SHIFT                                                0x3
#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE__SHIFT                                                0x4
#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS__SHIFT                                              0x5
#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE__SHIFT                                                         0x6
#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL__SHIFT                                                  0xa
#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL__SHIFT                                                  0xb
#define COMPUTE_DISPATCH_INITIATOR__RESERVED__SHIFT                                                           0xc
#define COMPUTE_DISPATCH_INITIATOR__TUNNEL_ENABLE__SHIFT                                                      0xd
#define COMPUTE_DISPATCH_INITIATOR__RESTORE__SHIFT                                                            0xe
#define COMPUTE_DISPATCH_INITIATOR__CS_W32_EN__SHIFT                                                          0xf
#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN_MASK                                                    0x00000001L
#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN_MASK                                                        0x00000002L
#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000_MASK                                                   0x00000004L
#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL_MASK                                                  0x00000008L
#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE_MASK                                                  0x00000010L
#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS_MASK                                                0x00000020L
#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE_MASK                                                           0x00000040L
#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL_MASK                                                    0x00000400L
#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL_MASK                                                    0x00000800L
#define COMPUTE_DISPATCH_INITIATOR__RESERVED_MASK                                                             0x00001000L
#define COMPUTE_DISPATCH_INITIATOR__TUNNEL_ENABLE_MASK                                                        0x00002000L
#define COMPUTE_DISPATCH_INITIATOR__RESTORE_MASK                                                              0x00004000L
#define COMPUTE_DISPATCH_INITIATOR__CS_W32_EN_MASK                                                            0x00008000L
//COMPUTE_DIM_X
#define COMPUTE_DIM_X__SIZE__SHIFT                                                                            0x0
#define COMPUTE_DIM_X__SIZE_MASK                                                                              0xFFFFFFFFL
//COMPUTE_DIM_Y
#define COMPUTE_DIM_Y__SIZE__SHIFT                                                                            0x0
#define COMPUTE_DIM_Y__SIZE_MASK                                                                              0xFFFFFFFFL
//COMPUTE_DIM_Z
#define COMPUTE_DIM_Z__SIZE__SHIFT                                                                            0x0
#define COMPUTE_DIM_Z__SIZE_MASK                                                                              0xFFFFFFFFL
//COMPUTE_START_X
#define COMPUTE_START_X__START__SHIFT                                                                         0x0
#define COMPUTE_START_X__START_MASK                                                                           0xFFFFFFFFL
//COMPUTE_START_Y
#define COMPUTE_START_Y__START__SHIFT                                                                         0x0
#define COMPUTE_START_Y__START_MASK                                                                           0xFFFFFFFFL
//COMPUTE_START_Z
#define COMPUTE_START_Z__START__SHIFT                                                                         0x0
#define COMPUTE_START_Z__START_MASK                                                                           0xFFFFFFFFL
//COMPUTE_NUM_THREAD_X
#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL__SHIFT                                                          0x0
#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL__SHIFT                                                       0x10
#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL_MASK                                                            0x0000FFFFL
#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL_MASK                                                         0xFFFF0000L
//COMPUTE_NUM_THREAD_Y
#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL__SHIFT                                                          0x0
#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL__SHIFT                                                       0x10
#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL_MASK                                                            0x0000FFFFL
#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL_MASK                                                         0xFFFF0000L
//COMPUTE_NUM_THREAD_Z
#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL__SHIFT                                                          0x0
#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL__SHIFT                                                       0x10
#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL_MASK                                                            0x0000FFFFL
#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL_MASK                                                         0xFFFF0000L
//COMPUTE_PIPELINESTAT_ENABLE
#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE__SHIFT                                               0x0
#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE_MASK                                                 0x00000001L
//COMPUTE_PERFCOUNT_ENABLE
#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE__SHIFT                                                     0x0
#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE_MASK                                                       0x00000001L
//COMPUTE_PGM_LO
#define COMPUTE_PGM_LO__DATA__SHIFT                                                                           0x0
#define COMPUTE_PGM_LO__DATA_MASK                                                                             0xFFFFFFFFL
//COMPUTE_PGM_HI
#define COMPUTE_PGM_HI__DATA__SHIFT                                                                           0x0
#define COMPUTE_PGM_HI__DATA_MASK                                                                             0x000000FFL
//COMPUTE_DISPATCH_PKT_ADDR_LO
#define COMPUTE_DISPATCH_PKT_ADDR_LO__DATA__SHIFT                                                             0x0
#define COMPUTE_DISPATCH_PKT_ADDR_LO__DATA_MASK                                                               0xFFFFFFFFL
//COMPUTE_DISPATCH_PKT_ADDR_HI
#define COMPUTE_DISPATCH_PKT_ADDR_HI__DATA__SHIFT                                                             0x0
#define COMPUTE_DISPATCH_PKT_ADDR_HI__DATA_MASK                                                               0x000000FFL
//COMPUTE_DISPATCH_SCRATCH_BASE_LO
#define COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA__SHIFT                                                         0x0
#define COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA_MASK                                                           0xFFFFFFFFL
//COMPUTE_DISPATCH_SCRATCH_BASE_HI
#define COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA__SHIFT                                                         0x0
#define COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA_MASK                                                           0x000000FFL
//COMPUTE_PGM_RSRC1
#define COMPUTE_PGM_RSRC1__VGPRS__SHIFT                                                                       0x0
#define COMPUTE_PGM_RSRC1__SGPRS__SHIFT                                                                       0x6
#define COMPUTE_PGM_RSRC1__PRIORITY__SHIFT                                                                    0xa
#define COMPUTE_PGM_RSRC1__FLOAT_MODE__SHIFT                                                                  0xc
#define COMPUTE_PGM_RSRC1__PRIV__SHIFT                                                                        0x14
#define COMPUTE_PGM_RSRC1__DX10_CLAMP__SHIFT                                                                  0x15
#define COMPUTE_PGM_RSRC1__IEEE_MODE__SHIFT                                                                   0x17
#define COMPUTE_PGM_RSRC1__BULKY__SHIFT                                                                       0x18
#define COMPUTE_PGM_RSRC1__FP16_OVFL__SHIFT                                                                   0x1a
#define COMPUTE_PGM_RSRC1__WGP_MODE__SHIFT                                                                    0x1d
#define COMPUTE_PGM_RSRC1__MEM_ORDERED__SHIFT                                                                 0x1e
#define COMPUTE_PGM_RSRC1__FWD_PROGRESS__SHIFT                                                                0x1f
#define COMPUTE_PGM_RSRC1__VGPRS_MASK                                                                         0x0000003FL
#define COMPUTE_PGM_RSRC1__SGPRS_MASK                                                                         0x000003C0L
#define COMPUTE_PGM_RSRC1__PRIORITY_MASK                                                                      0x00000C00L
#define COMPUTE_PGM_RSRC1__FLOAT_MODE_MASK                                                                    0x000FF000L
#define COMPUTE_PGM_RSRC1__PRIV_MASK                                                                          0x00100000L
#define COMPUTE_PGM_RSRC1__DX10_CLAMP_MASK                                                                    0x00200000L
#define COMPUTE_PGM_RSRC1__IEEE_MODE_MASK                                                                     0x00800000L
#define COMPUTE_PGM_RSRC1__BULKY_MASK                                                                         0x01000000L
#define COMPUTE_PGM_RSRC1__FP16_OVFL_MASK                                                                     0x04000000L
#define COMPUTE_PGM_RSRC1__WGP_MODE_MASK                                                                      0x20000000L
#define COMPUTE_PGM_RSRC1__MEM_ORDERED_MASK                                                                   0x40000000L
#define COMPUTE_PGM_RSRC1__FWD_PROGRESS_MASK                                                                  0x80000000L
//COMPUTE_PGM_RSRC2
#define COMPUTE_PGM_RSRC2__SCRATCH_EN__SHIFT                                                                  0x0
#define COMPUTE_PGM_RSRC2__USER_SGPR__SHIFT                                                                   0x1
#define COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT                                                                0x6
#define COMPUTE_PGM_RSRC2__TGID_X_EN__SHIFT                                                                   0x7
#define COMPUTE_PGM_RSRC2__TGID_Y_EN__SHIFT                                                                   0x8
#define COMPUTE_PGM_RSRC2__TGID_Z_EN__SHIFT                                                                   0x9
#define COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT                                                                  0xa
#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT__SHIFT                                                              0xb
#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB__SHIFT                                                                 0xd
#define COMPUTE_PGM_RSRC2__LDS_SIZE__SHIFT                                                                    0xf
#define COMPUTE_PGM_RSRC2__EXCP_EN__SHIFT                                                                     0x18
#define COMPUTE_PGM_RSRC2__SCRATCH_EN_MASK                                                                    0x00000001L
#define COMPUTE_PGM_RSRC2__USER_SGPR_MASK                                                                     0x0000003EL
#define COMPUTE_PGM_RSRC2__TRAP_PRESENT_MASK                                                                  0x00000040L
#define COMPUTE_PGM_RSRC2__TGID_X_EN_MASK                                                                     0x00000080L
#define COMPUTE_PGM_RSRC2__TGID_Y_EN_MASK                                                                     0x00000100L
#define COMPUTE_PGM_RSRC2__TGID_Z_EN_MASK                                                                     0x00000200L
#define COMPUTE_PGM_RSRC2__TG_SIZE_EN_MASK                                                                    0x00000400L
#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT_MASK                                                                0x00001800L
#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB_MASK                                                                   0x00006000L
#define COMPUTE_PGM_RSRC2__LDS_SIZE_MASK                                                                      0x00FF8000L
#define COMPUTE_PGM_RSRC2__EXCP_EN_MASK                                                                       0x7F000000L
//COMPUTE_VMID
#define COMPUTE_VMID__DATA__SHIFT                                                                             0x0
#define COMPUTE_VMID__DATA_MASK                                                                               0x0000000FL
//COMPUTE_RESOURCE_LIMITS
#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH__SHIFT                                                          0x0
#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU__SHIFT                                                             0xc
#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD__SHIFT                                                        0x10
#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL__SHIFT                                                        0x16
#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST__SHIFT                                                       0x17
#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT__SHIFT                                                        0x18
#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH_MASK                                                            0x000003FFL
#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU_MASK                                                               0x0000F000L
#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD_MASK                                                          0x003F0000L
#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL_MASK                                                          0x00400000L
#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK                                                         0x00800000L
#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT_MASK                                                          0x07000000L
//COMPUTE_DESTINATION_EN_SE0
#define COMPUTE_DESTINATION_EN_SE0__CU_EN__SHIFT                                                              0x0
#define COMPUTE_DESTINATION_EN_SE0__CU_EN_MASK                                                                0xFFFFFFFFL
//COMPUTE_STATIC_THREAD_MGMT_SE0
#define COMPUTE_STATIC_THREAD_MGMT_SE0__SA0_CU_EN__SHIFT                                                      0x0
#define COMPUTE_STATIC_THREAD_MGMT_SE0__SA1_CU_EN__SHIFT                                                      0x10
#define COMPUTE_STATIC_THREAD_MGMT_SE0__SA0_CU_EN_MASK                                                        0x0000FFFFL
#define COMPUTE_STATIC_THREAD_MGMT_SE0__SA1_CU_EN_MASK                                                        0xFFFF0000L
//COMPUTE_DESTINATION_EN_SE1
#define COMPUTE_DESTINATION_EN_SE1__CU_EN__SHIFT                                                              0x0
#define COMPUTE_DESTINATION_EN_SE1__CU_EN_MASK                                                                0xFFFFFFFFL
//COMPUTE_STATIC_THREAD_MGMT_SE1
#define COMPUTE_STATIC_THREAD_MGMT_SE1__SA0_CU_EN__SHIFT                                                      0x0
#define COMPUTE_STATIC_THREAD_MGMT_SE1__SA1_CU_EN__SHIFT                                                      0x10
#define COMPUTE_STATIC_THREAD_MGMT_SE1__SA0_CU_EN_MASK                                                        0x0000FFFFL
#define COMPUTE_STATIC_THREAD_MGMT_SE1__SA1_CU_EN_MASK                                                        0xFFFF0000L
//COMPUTE_TMPRING_SIZE
#define COMPUTE_TMPRING_SIZE__WAVES__SHIFT                                                                    0x0
#define COMPUTE_TMPRING_SIZE__WAVESIZE__SHIFT                                                                 0xc
#define COMPUTE_TMPRING_SIZE__WAVES_MASK                                                                      0x00000FFFL
#define COMPUTE_TMPRING_SIZE__WAVESIZE_MASK                                                                   0x01FFF000L
//COMPUTE_DESTINATION_EN_SE2
#define COMPUTE_DESTINATION_EN_SE2__CU_EN__SHIFT                                                              0x0
#define COMPUTE_DESTINATION_EN_SE2__CU_EN_MASK                                                                0xFFFFFFFFL
//COMPUTE_STATIC_THREAD_MGMT_SE2
#define COMPUTE_STATIC_THREAD_MGMT_SE2__SA0_CU_EN__SHIFT                                                      0x0
#define COMPUTE_STATIC_THREAD_MGMT_SE2__SA1_CU_EN__SHIFT                                                      0x10
#define COMPUTE_STATIC_THREAD_MGMT_SE2__SA0_CU_EN_MASK                                                        0x0000FFFFL
#define COMPUTE_STATIC_THREAD_MGMT_SE2__SA1_CU_EN_MASK                                                        0xFFFF0000L
//COMPUTE_DESTINATION_EN_SE3
#define COMPUTE_DESTINATION_EN_SE3__CU_EN__SHIFT                                                              0x0
#define COMPUTE_DESTINATION_EN_SE3__CU_EN_MASK                                                                0xFFFFFFFFL
//COMPUTE_STATIC_THREAD_MGMT_SE3
#define COMPUTE_STATIC_THREAD_MGMT_SE3__SA0_CU_EN__SHIFT                                                      0x0
#define COMPUTE_STATIC_THREAD_MGMT_SE3__SA1_CU_EN__SHIFT                                                      0x10
#define COMPUTE_STATIC_THREAD_MGMT_SE3__SA0_CU_EN_MASK                                                        0x0000FFFFL
#define COMPUTE_STATIC_THREAD_MGMT_SE3__SA1_CU_EN_MASK                                                        0xFFFF0000L
//COMPUTE_RESTART_X
#define COMPUTE_RESTART_X__RESTART__SHIFT                                                                     0x0
#define COMPUTE_RESTART_X__RESTART_MASK                                                                       0xFFFFFFFFL
//COMPUTE_RESTART_Y
#define COMPUTE_RESTART_Y__RESTART__SHIFT                                                                     0x0
#define COMPUTE_RESTART_Y__RESTART_MASK                                                                       0xFFFFFFFFL
//COMPUTE_RESTART_Z
#define COMPUTE_RESTART_Z__RESTART__SHIFT                                                                     0x0
#define COMPUTE_RESTART_Z__RESTART_MASK                                                                       0xFFFFFFFFL
//COMPUTE_THREAD_TRACE_ENABLE
#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE__SHIFT                                               0x0
#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE_MASK                                                 0x00000001L
//COMPUTE_MISC_RESERVED
#define COMPUTE_MISC_RESERVED__SEND_SEID__SHIFT                                                               0x0
#define COMPUTE_MISC_RESERVED__RESERVED2__SHIFT                                                               0x2
#define COMPUTE_MISC_RESERVED__RESERVED3__SHIFT                                                               0x3
#define COMPUTE_MISC_RESERVED__RESERVED4__SHIFT                                                               0x4
#define COMPUTE_MISC_RESERVED__WAVE_ID_BASE__SHIFT                                                            0x5
#define COMPUTE_MISC_RESERVED__SEND_SEID_MASK                                                                 0x00000003L
#define COMPUTE_MISC_RESERVED__RESERVED2_MASK                                                                 0x00000004L
#define COMPUTE_MISC_RESERVED__RESERVED3_MASK                                                                 0x00000008L
#define COMPUTE_MISC_RESERVED__RESERVED4_MASK                                                                 0x00000010L
#define COMPUTE_MISC_RESERVED__WAVE_ID_BASE_MASK                                                              0x0001FFE0L
//COMPUTE_DISPATCH_ID
#define COMPUTE_DISPATCH_ID__DISPATCH_ID__SHIFT                                                               0x0
#define COMPUTE_DISPATCH_ID__DISPATCH_ID_MASK                                                                 0xFFFFFFFFL
//COMPUTE_THREADGROUP_ID
#define COMPUTE_THREADGROUP_ID__THREADGROUP_ID__SHIFT                                                         0x0
#define COMPUTE_THREADGROUP_ID__THREADGROUP_ID_MASK                                                           0xFFFFFFFFL
//COMPUTE_REQ_CTRL
#define COMPUTE_REQ_CTRL__SOFT_GROUPING_EN__SHIFT                                                             0x0
#define COMPUTE_REQ_CTRL__NUMBER_OF_REQUESTS_PER_CU__SHIFT                                                    0x1
#define COMPUTE_REQ_CTRL__SOFT_GROUPING_ALLOCATION_TIMEOUT__SHIFT                                             0x5
#define COMPUTE_REQ_CTRL__HARD_LOCK_HYSTERESIS__SHIFT                                                         0x9
#define COMPUTE_REQ_CTRL__HARD_LOCK_LOW_THRESHOLD__SHIFT                                                      0xa
#define COMPUTE_REQ_CTRL__PRODUCER_REQUEST_LOCKOUT__SHIFT                                                     0xf
#define COMPUTE_REQ_CTRL__GLOBAL_SCANNING_EN__SHIFT                                                           0x10
#define COMPUTE_REQ_CTRL__ALLOCATION_RATE_THROTTLING_THRESHOLD__SHIFT                                         0x11
#define COMPUTE_REQ_CTRL__DEDICATED_PREALLOCATION_BUFFER_LIMIT__SHIFT                                         0x14
#define COMPUTE_REQ_CTRL__SOFT_GROUPING_EN_MASK                                                               0x00000001L
#define COMPUTE_REQ_CTRL__NUMBER_OF_REQUESTS_PER_CU_MASK                                                      0x0000001EL
#define COMPUTE_REQ_CTRL__SOFT_GROUPING_ALLOCATION_TIMEOUT_MASK                                               0x000001E0L
#define COMPUTE_REQ_CTRL__HARD_LOCK_HYSTERESIS_MASK                                                           0x00000200L
#define COMPUTE_REQ_CTRL__HARD_LOCK_LOW_THRESHOLD_MASK                                                        0x00007C00L
#define COMPUTE_REQ_CTRL__PRODUCER_REQUEST_LOCKOUT_MASK                                                       0x00008000L
#define COMPUTE_REQ_CTRL__GLOBAL_SCANNING_EN_MASK                                                             0x00010000L
#define COMPUTE_REQ_CTRL__ALLOCATION_RATE_THROTTLING_THRESHOLD_MASK                                           0x000E0000L
#define COMPUTE_REQ_CTRL__DEDICATED_PREALLOCATION_BUFFER_LIMIT_MASK                                           0x07F00000L
//COMPUTE_USER_ACCUM_0
#define COMPUTE_USER_ACCUM_0__CONTRIBUTION__SHIFT                                                             0x0
#define COMPUTE_USER_ACCUM_0__CONTRIBUTION_MASK                                                               0x0000007FL
//COMPUTE_USER_ACCUM_1
#define COMPUTE_USER_ACCUM_1__CONTRIBUTION__SHIFT                                                             0x0
#define COMPUTE_USER_ACCUM_1__CONTRIBUTION_MASK                                                               0x0000007FL
//COMPUTE_USER_ACCUM_2
#define COMPUTE_USER_ACCUM_2__CONTRIBUTION__SHIFT                                                             0x0
#define COMPUTE_USER_ACCUM_2__CONTRIBUTION_MASK                                                               0x0000007FL
//COMPUTE_USER_ACCUM_3
#define COMPUTE_USER_ACCUM_3__CONTRIBUTION__SHIFT                                                             0x0
#define COMPUTE_USER_ACCUM_3__CONTRIBUTION_MASK                                                               0x0000007FL
//COMPUTE_PGM_RSRC3
#define COMPUTE_PGM_RSRC3__SHARED_VGPR_CNT__SHIFT                                                             0x0
#define COMPUTE_PGM_RSRC3__SHARED_VGPR_CNT_MASK                                                               0x0000000FL
//COMPUTE_DDID_INDEX
#define COMPUTE_DDID_INDEX__INDEX__SHIFT                                                                      0x0
#define COMPUTE_DDID_INDEX__INDEX_MASK                                                                        0x000007FFL
//COMPUTE_SHADER_CHKSUM
#define COMPUTE_SHADER_CHKSUM__CHECKSUM__SHIFT                                                                0x0
#define COMPUTE_SHADER_CHKSUM__CHECKSUM_MASK                                                                  0xFFFFFFFFL
//COMPUTE_RELAUNCH
#define COMPUTE_RELAUNCH__PAYLOAD__SHIFT                                                                      0x0
#define COMPUTE_RELAUNCH__IS_EVENT__SHIFT                                                                     0x1e
#define COMPUTE_RELAUNCH__IS_STATE__SHIFT                                                                     0x1f
#define COMPUTE_RELAUNCH__PAYLOAD_MASK                                                                        0x3FFFFFFFL
#define COMPUTE_RELAUNCH__IS_EVENT_MASK                                                                       0x40000000L
#define COMPUTE_RELAUNCH__IS_STATE_MASK                                                                       0x80000000L
//COMPUTE_WAVE_RESTORE_ADDR_LO
#define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR__SHIFT                                                             0x0
#define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR_MASK                                                               0xFFFFFFFFL
//COMPUTE_WAVE_RESTORE_ADDR_HI
#define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR__SHIFT                                                             0x0
#define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR_MASK                                                               0xFFFFL
//COMPUTE_RELAUNCH2
#define COMPUTE_RELAUNCH2__PAYLOAD__SHIFT                                                                     0x0
#define COMPUTE_RELAUNCH2__IS_EVENT__SHIFT                                                                    0x1e
#define COMPUTE_RELAUNCH2__IS_STATE__SHIFT                                                                    0x1f
#define COMPUTE_RELAUNCH2__PAYLOAD_MASK                                                                       0x3FFFFFFFL
#define COMPUTE_RELAUNCH2__IS_EVENT_MASK                                                                      0x40000000L
#define COMPUTE_RELAUNCH2__IS_STATE_MASK                                                                      0x80000000L
//COMPUTE_USER_DATA_0
#define COMPUTE_USER_DATA_0__DATA__SHIFT                                                                      0x0
#define COMPUTE_USER_DATA_0__DATA_MASK                                                                        0xFFFFFFFFL
//COMPUTE_USER_DATA_1
#define COMPUTE_USER_DATA_1__DATA__SHIFT                                                                      0x0
#define COMPUTE_USER_DATA_1__DATA_MASK                                                                        0xFFFFFFFFL
//COMPUTE_USER_DATA_2
#define COMPUTE_USER_DATA_2__DATA__SHIFT                                                                      0x0
#define COMPUTE_USER_DATA_2__DATA_MASK                                                                        0xFFFFFFFFL
//COMPUTE_USER_DATA_3
#define COMPUTE_USER_DATA_3__DATA__SHIFT                                                                      0x0
#define COMPUTE_USER_DATA_3__DATA_MASK                                                                        0xFFFFFFFFL
//COMPUTE_USER_DATA_4
#define COMPUTE_USER_DATA_4__DATA__SHIFT                                                                      0x0
#define COMPUTE_USER_DATA_4__DATA_MASK                                                                        0xFFFFFFFFL
//COMPUTE_USER_DATA_5
#define COMPUTE_USER_DATA_5__DATA__SHIFT                                                                      0x0
#define COMPUTE_USER_DATA_5__DATA_MASK                                                                        0xFFFFFFFFL
//COMPUTE_USER_DATA_6
#define COMPUTE_USER_DATA_6__DATA__SHIFT                                                                      0x0
#define COMPUTE_USER_DATA_6__DATA_MASK                                                                        0xFFFFFFFFL
//COMPUTE_USER_DATA_7
#define COMPUTE_USER_DATA_7__DATA__SHIFT                                                                      0x0
#define COMPUTE_USER_DATA_7__DATA_MASK                                                                        0xFFFFFFFFL
//COMPUTE_USER_DATA_8
#define COMPUTE_USER_DATA_8__DATA__SHIFT                                                                      0x0
#define COMPUTE_USER_DATA_8__DATA_MASK                                                                        0xFFFFFFFFL
//COMPUTE_USER_DATA_9
#define COMPUTE_USER_DATA_9__DATA__SHIFT                                                                      0x0
#define COMPUTE_USER_DATA_9__DATA_MASK                                                                        0xFFFFFFFFL
//COMPUTE_USER_DATA_10
#define COMPUTE_USER_DATA_10__DATA__SHIFT                                                                     0x0
#define COMPUTE_USER_DATA_10__DATA_MASK                                                                       0xFFFFFFFFL
//COMPUTE_USER_DATA_11
#define COMPUTE_USER_DATA_11__DATA__SHIFT                                                                     0x0
#define COMPUTE_USER_DATA_11__DATA_MASK                                                                       0xFFFFFFFFL
//COMPUTE_USER_DATA_12
#define COMPUTE_USER_DATA_12__DATA__SHIFT                                                                     0x0
#define COMPUTE_USER_DATA_12__DATA_MASK                                                                       0xFFFFFFFFL
//COMPUTE_USER_DATA_13
#define COMPUTE_USER_DATA_13__DATA__SHIFT                                                                     0x0
#define COMPUTE_USER_DATA_13__DATA_MASK                                                                       0xFFFFFFFFL
//COMPUTE_USER_DATA_14
#define COMPUTE_USER_DATA_14__DATA__SHIFT                                                                     0x0
#define COMPUTE_USER_DATA_14__DATA_MASK                                                                       0xFFFFFFFFL
//COMPUTE_USER_DATA_15
#define COMPUTE_USER_DATA_15__DATA__SHIFT                                                                     0x0
#define COMPUTE_USER_DATA_15__DATA_MASK                                                                       0xFFFFFFFFL
//COMPUTE_DISPATCH_TUNNEL
#define COMPUTE_DISPATCH_TUNNEL__OFF_DELAY__SHIFT                                                             0x0
#define COMPUTE_DISPATCH_TUNNEL__IMMEDIATE__SHIFT                                                             0xa
#define COMPUTE_DISPATCH_TUNNEL__OFF_DELAY_MASK                                                               0x000003FFL
#define COMPUTE_DISPATCH_TUNNEL__IMMEDIATE_MASK                                                               0x00000400L
//COMPUTE_DISPATCH_END
#define COMPUTE_DISPATCH_END__DATA__SHIFT                                                                     0x0
#define COMPUTE_DISPATCH_END__DATA_MASK                                                                       0xFFFFFFFFL
//COMPUTE_NOWHERE
#define COMPUTE_NOWHERE__DATA__SHIFT                                                                          0x0
#define COMPUTE_NOWHERE__DATA_MASK                                                                            0xFFFFFFFFL
//SH_RESERVED_REG0
#define SH_RESERVED_REG0__DATA__SHIFT                                                                         0x0
#define SH_RESERVED_REG0__DATA_MASK                                                                           0xFFFFFFFFL
//SH_RESERVED_REG1
#define SH_RESERVED_REG1__DATA__SHIFT                                                                         0x0
#define SH_RESERVED_REG1__DATA_MASK                                                                           0xFFFFFFFFL


// addressBlock: gc_cppdec
//CP_EOPQ_WAIT_TIME
#define CP_EOPQ_WAIT_TIME__WAIT_TIME__SHIFT                                                                   0x0
#define CP_EOPQ_WAIT_TIME__SCALE_COUNT__SHIFT                                                                 0xa
#define CP_EOPQ_WAIT_TIME__WAIT_TIME_MASK                                                                     0x000003FFL
#define CP_EOPQ_WAIT_TIME__SCALE_COUNT_MASK                                                                   0x0003FC00L
//CP_CPC_MGCG_SYNC_CNTL
#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD__SHIFT                                                         0x0
#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD__SHIFT                                                           0x8
#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD_MASK                                                           0x000000FFL
#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD_MASK                                                             0x0000FF00L
//CPC_INT_INFO
#define CPC_INT_INFO__ADDR_HI__SHIFT                                                                          0x0
#define CPC_INT_INFO__TYPE__SHIFT                                                                             0x10
#define CPC_INT_INFO__VMID__SHIFT                                                                             0x14
#define CPC_INT_INFO__QUEUE_ID__SHIFT                                                                         0x1c
#define CPC_INT_INFO__ADDR_HI_MASK                                                                            0x0000FFFFL
#define CPC_INT_INFO__TYPE_MASK                                                                               0x00010000L
#define CPC_INT_INFO__VMID_MASK                                                                               0x00F00000L
#define CPC_INT_INFO__QUEUE_ID_MASK                                                                           0x70000000L
//CP_VIRT_STATUS
#define CP_VIRT_STATUS__VIRT_STATUS__SHIFT                                                                    0x0
#define CP_VIRT_STATUS__VIRT_STATUS_MASK                                                                      0xFFFFFFFFL
//CPC_INT_ADDR
#define CPC_INT_ADDR__ADDR__SHIFT                                                                             0x0
#define CPC_INT_ADDR__ADDR_MASK                                                                               0xFFFFFFFFL
//CPC_INT_PASID
#define CPC_INT_PASID__PASID__SHIFT                                                                           0x0
#define CPC_INT_PASID__BYPASS_PASID__SHIFT                                                                    0x10
#define CPC_INT_PASID__PASID_MASK                                                                             0x0000FFFFL
#define CPC_INT_PASID__BYPASS_PASID_MASK                                                                      0x00010000L
//CP_GFX_ERROR
#define CP_GFX_ERROR__EDC_ERROR_ID__SHIFT                                                                     0x0
#define CP_GFX_ERROR__SUA_ERROR__SHIFT                                                                        0x4
#define CP_GFX_ERROR__CE_DATA_FETCHER_UTCL1_ERROR__SHIFT                                                      0x5
#define CP_GFX_ERROR__DATA_FETCHER_UTCL1_ERROR__SHIFT                                                         0x6
#define CP_GFX_ERROR__SEM_UTCL1_ERROR__SHIFT                                                                  0x7
#define CP_GFX_ERROR__QU_STRM_UTCL1_ERROR__SHIFT                                                              0x8
#define CP_GFX_ERROR__QU_EOP_UTCL1_ERROR__SHIFT                                                               0x9
#define CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR__SHIFT                                                              0xa
#define CP_GFX_ERROR__QU_READ_UTCL1_ERROR__SHIFT                                                              0xb
#define CP_GFX_ERROR__SYNC_MEMRD_UTCL1_ERROR__SHIFT                                                           0xc
#define CP_GFX_ERROR__SYNC_MEMWR_UTCL1_ERROR__SHIFT                                                           0xd
#define CP_GFX_ERROR__SHADOW_UTCL1_ERROR__SHIFT                                                               0xe
#define CP_GFX_ERROR__APPEND_UTCL1_ERROR__SHIFT                                                               0xf
#define CP_GFX_ERROR__CE_DMA_UTCL1_ERROR__SHIFT                                                               0x10
#define CP_GFX_ERROR__PFP_VGTDMA_UTCL1_ERROR__SHIFT                                                           0x11
#define CP_GFX_ERROR__DMA_SRC_UTCL1_ERROR__SHIFT                                                              0x12
#define CP_GFX_ERROR__DMA_DST_UTCL1_ERROR__SHIFT                                                              0x13
#define CP_GFX_ERROR__PFP_TC_UTCL1_ERROR__SHIFT                                                               0x14
#define CP_GFX_ERROR__ME_TC_UTCL1_ERROR__SHIFT                                                                0x15
#define CP_GFX_ERROR__CE_TC_UTCL1_ERROR__SHIFT                                                                0x16
#define CP_GFX_ERROR__PRT_LOD_UTCL1_ERROR__SHIFT                                                              0x17
#define CP_GFX_ERROR__RDPTR_RPT_UTCL1_ERROR__SHIFT                                                            0x18
#define CP_GFX_ERROR__RB_FETCHER_UTCL1_ERROR__SHIFT                                                           0x19
#define CP_GFX_ERROR__I1_FETCHER_UTCL1_ERROR__SHIFT                                                           0x1a
#define CP_GFX_ERROR__I2_FETCHER_UTCL1_ERROR__SHIFT                                                           0x1b
#define CP_GFX_ERROR__C1_FETCHER_UTCL1_ERROR__SHIFT                                                           0x1c
#define CP_GFX_ERROR__C2_FETCHER_UTCL1_ERROR__SHIFT                                                           0x1d
#define CP_GFX_ERROR__ST_FETCHER_UTCL1_ERROR__SHIFT                                                           0x1e
#define CP_GFX_ERROR__CE_INIT_UTCL1_ERROR__SHIFT                                                              0x1f
#define CP_GFX_ERROR__EDC_ERROR_ID_MASK                                                                       0x0000000FL
#define CP_GFX_ERROR__SUA_ERROR_MASK                                                                          0x00000010L
#define CP_GFX_ERROR__CE_DATA_FETCHER_UTCL1_ERROR_MASK                                                        0x00000020L
#define CP_GFX_ERROR__DATA_FETCHER_UTCL1_ERROR_MASK                                                           0x00000040L
#define CP_GFX_ERROR__SEM_UTCL1_ERROR_MASK                                                                    0x00000080L
#define CP_GFX_ERROR__QU_STRM_UTCL1_ERROR_MASK                                                                0x00000100L
#define CP_GFX_ERROR__QU_EOP_UTCL1_ERROR_MASK                                                                 0x00000200L
#define CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR_MASK                                                                0x00000400L
#define CP_GFX_ERROR__QU_READ_UTCL1_ERROR_MASK                                                                0x00000800L
#define CP_GFX_ERROR__SYNC_MEMRD_UTCL1_ERROR_MASK                                                             0x00001000L
#define CP_GFX_ERROR__SYNC_MEMWR_UTCL1_ERROR_MASK                                                             0x00002000L
#define CP_GFX_ERROR__SHADOW_UTCL1_ERROR_MASK                                                                 0x00004000L
#define CP_GFX_ERROR__APPEND_UTCL1_ERROR_MASK                                                                 0x00008000L
#define CP_GFX_ERROR__CE_DMA_UTCL1_ERROR_MASK                                                                 0x00010000L
#define CP_GFX_ERROR__PFP_VGTDMA_UTCL1_ERROR_MASK                                                             0x00020000L
#define CP_GFX_ERROR__DMA_SRC_UTCL1_ERROR_MASK                                                                0x00040000L
#define CP_GFX_ERROR__DMA_DST_UTCL1_ERROR_MASK                                                                0x00080000L
#define CP_GFX_ERROR__PFP_TC_UTCL1_ERROR_MASK                                                                 0x00100000L
#define CP_GFX_ERROR__ME_TC_UTCL1_ERROR_MASK                                                                  0x00200000L
#define CP_GFX_ERROR__CE_TC_UTCL1_ERROR_MASK                                                                  0x00400000L
#define CP_GFX_ERROR__PRT_LOD_UTCL1_ERROR_MASK                                                                0x00800000L
#define CP_GFX_ERROR__RDPTR_RPT_UTCL1_ERROR_MASK                                                              0x01000000L
#define CP_GFX_ERROR__RB_FETCHER_UTCL1_ERROR_MASK                                                             0x02000000L
#define CP_GFX_ERROR__I1_FETCHER_UTCL1_ERROR_MASK                                                             0x04000000L
#define CP_GFX_ERROR__I2_FETCHER_UTCL1_ERROR_MASK                                                             0x08000000L
#define CP_GFX_ERROR__C1_FETCHER_UTCL1_ERROR_MASK                                                             0x10000000L
#define CP_GFX_ERROR__C2_FETCHER_UTCL1_ERROR_MASK                                                             0x20000000L
#define CP_GFX_ERROR__ST_FETCHER_UTCL1_ERROR_MASK                                                             0x40000000L
#define CP_GFX_ERROR__CE_INIT_UTCL1_ERROR_MASK                                                                0x80000000L
//CPG_UTCL1_CNTL
#define CPG_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT                                                           0x0
#define CPG_UTCL1_CNTL__VMID_RESET_MODE__SHIFT                                                                0x17
#define CPG_UTCL1_CNTL__DROP_MODE__SHIFT                                                                      0x18
#define CPG_UTCL1_CNTL__INVALIDATE__SHIFT                                                                     0x1a
#define CPG_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT                                                                0x1b
#define CPG_UTCL1_CNTL__FORCE_SNOOP__SHIFT                                                                    0x1c
#define CPG_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT                                                              0x1e
#define CPG_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK                                                             0x000FFFFFL
#define CPG_UTCL1_CNTL__VMID_RESET_MODE_MASK                                                                  0x00800000L
#define CPG_UTCL1_CNTL__DROP_MODE_MASK                                                                        0x01000000L
#define CPG_UTCL1_CNTL__INVALIDATE_MASK                                                                       0x04000000L
#define CPG_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK                                                                  0x08000000L
#define CPG_UTCL1_CNTL__FORCE_SNOOP_MASK                                                                      0x10000000L
#define CPG_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK                                                                0x40000000L
//CPC_UTCL1_CNTL
#define CPC_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT                                                           0x0
#define CPC_UTCL1_CNTL__DROP_MODE__SHIFT                                                                      0x18
#define CPC_UTCL1_CNTL__INVALIDATE__SHIFT                                                                     0x1a
#define CPC_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT                                                                0x1b
#define CPC_UTCL1_CNTL__FORCE_SNOOP__SHIFT                                                                    0x1c
#define CPC_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT                                                              0x1e
#define CPC_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK                                                             0x000FFFFFL
#define CPC_UTCL1_CNTL__DROP_MODE_MASK                                                                        0x01000000L
#define CPC_UTCL1_CNTL__INVALIDATE_MASK                                                                       0x04000000L
#define CPC_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK                                                                  0x08000000L
#define CPC_UTCL1_CNTL__FORCE_SNOOP_MASK                                                                      0x10000000L
#define CPC_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK                                                                0x40000000L
//CPF_UTCL1_CNTL
#define CPF_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT                                                           0x0
#define CPF_UTCL1_CNTL__VMID_RESET_MODE__SHIFT                                                                0x17
#define CPF_UTCL1_CNTL__DROP_MODE__SHIFT                                                                      0x18
#define CPF_UTCL1_CNTL__INVALIDATE__SHIFT                                                                     0x1a
#define CPF_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT                                                                0x1b
#define CPF_UTCL1_CNTL__FORCE_SNOOP__SHIFT                                                                    0x1c
#define CPF_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT                                                              0x1e
#define CPF_UTCL1_CNTL__FORCE_NO_EXE__SHIFT                                                                   0x1f
#define CPF_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK                                                             0x000FFFFFL
#define CPF_UTCL1_CNTL__VMID_RESET_MODE_MASK                                                                  0x00800000L
#define CPF_UTCL1_CNTL__DROP_MODE_MASK                                                                        0x01000000L
#define CPF_UTCL1_CNTL__INVALIDATE_MASK                                                                       0x04000000L
#define CPF_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK                                                                  0x08000000L
#define CPF_UTCL1_CNTL__FORCE_SNOOP_MASK                                                                      0x10000000L
#define CPF_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK                                                                0x40000000L
#define CPF_UTCL1_CNTL__FORCE_NO_EXE_MASK                                                                     0x80000000L
//CP_AQL_SMM_STATUS
#define CP_AQL_SMM_STATUS__AQL_QUEUE_SMM__SHIFT                                                               0x0
#define CP_AQL_SMM_STATUS__AQL_QUEUE_SMM_MASK                                                                 0xFFFFFFFFL
//CP_RB0_BASE
#define CP_RB0_BASE__RB_BASE__SHIFT                                                                           0x0
#define CP_RB0_BASE__RB_BASE_MASK                                                                             0xFFFFFFFFL
//CP_RB_BASE
#define CP_RB_BASE__RB_BASE__SHIFT                                                                            0x0
#define CP_RB_BASE__RB_BASE_MASK                                                                              0xFFFFFFFFL
//CP_RB0_CNTL
#define CP_RB0_CNTL__RB_BUFSZ__SHIFT                                                                          0x0
#define CP_RB0_CNTL__RB_BLKSZ__SHIFT                                                                          0x8
#define CP_RB0_CNTL__RB_NON_PRIV__SHIFT                                                                       0xf
#define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT                                                                       0x14
#define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT                                                                    0x16
#define CP_RB0_CNTL__CACHE_POLICY__SHIFT                                                                      0x18
#define CP_RB0_CNTL__RB_VOLATILE__SHIFT                                                                       0x1a
#define CP_RB0_CNTL__RB_NO_UPDATE__SHIFT                                                                      0x1b
#define CP_RB0_CNTL__RB_EXE__SHIFT                                                                            0x1c
#define CP_RB0_CNTL__CE_HQD_NEQ_RB_HQD__SHIFT                                                                 0x1e
#define CP_RB0_CNTL__RB_RPTR_WR_ENA__SHIFT                                                                    0x1f
#define CP_RB0_CNTL__RB_BUFSZ_MASK                                                                            0x0000003FL
#define CP_RB0_CNTL__RB_BLKSZ_MASK                                                                            0x00003F00L
#define CP_RB0_CNTL__RB_NON_PRIV_MASK                                                                         0x00008000L
#define CP_RB0_CNTL__MIN_AVAILSZ_MASK                                                                         0x00300000L
#define CP_RB0_CNTL__MIN_IB_AVAILSZ_MASK                                                                      0x00C00000L
#define CP_RB0_CNTL__CACHE_POLICY_MASK                                                                        0x03000000L
#define CP_RB0_CNTL__RB_VOLATILE_MASK                                                                         0x04000000L
#define CP_RB0_CNTL__RB_NO_UPDATE_MASK                                                                        0x08000000L
#define CP_RB0_CNTL__RB_EXE_MASK                                                                              0x10000000L
#define CP_RB0_CNTL__CE_HQD_NEQ_RB_HQD_MASK                                                                   0x40000000L
#define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK                                                                      0x80000000L
//CP_RB_CNTL
#define CP_RB_CNTL__RB_BUFSZ__SHIFT                                                                           0x0
#define CP_RB_CNTL__RB_BLKSZ__SHIFT                                                                           0x8
#define CP_RB_CNTL__RB_NON_PRIV__SHIFT                                                                        0xf
#define CP_RB_CNTL__MIN_AVAILSZ__SHIFT                                                                        0x14
#define CP_RB_CNTL__MIN_IB_AVAILSZ__SHIFT                                                                     0x16
#define CP_RB_CNTL__CACHE_POLICY__SHIFT                                                                       0x18
#define CP_RB_CNTL__RB_VOLATILE__SHIFT                                                                        0x1a
#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT                                                                       0x1b
#define CP_RB_CNTL__RB_EXE__SHIFT                                                                             0x1c
#define CP_RB_CNTL__KMD_QUEUE__SHIFT                                                                          0x1d
#define CP_RB_CNTL__CE_HQD_NEQ_RB_HQD__SHIFT                                                                  0x1e
#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT                                                                     0x1f
#define CP_RB_CNTL__RB_BUFSZ_MASK                                                                             0x0000003FL
#define CP_RB_CNTL__RB_BLKSZ_MASK                                                                             0x00003F00L
#define CP_RB_CNTL__RB_NON_PRIV_MASK                                                                          0x00008000L
#define CP_RB_CNTL__MIN_AVAILSZ_MASK                                                                          0x00300000L
#define CP_RB_CNTL__MIN_IB_AVAILSZ_MASK                                                                       0x00C00000L
#define CP_RB_CNTL__CACHE_POLICY_MASK                                                                         0x03000000L
#define CP_RB_CNTL__RB_VOLATILE_MASK                                                                          0x04000000L
#define CP_RB_CNTL__RB_NO_UPDATE_MASK                                                                         0x08000000L
#define CP_RB_CNTL__RB_EXE_MASK                                                                               0x10000000L
#define CP_RB_CNTL__KMD_QUEUE_MASK                                                                            0x20000000L
#define CP_RB_CNTL__CE_HQD_NEQ_RB_HQD_MASK                                                                    0x40000000L
#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK                                                                       0x80000000L
//CP_RB_RPTR_WR
#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT                                                                      0x0
#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK                                                                        0x000FFFFFL
//CP_RB0_RPTR_ADDR
#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR__SHIFT                                                                 0x2
#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR_MASK                                                                   0xFFFFFFFCL
//CP_RB_RPTR_ADDR
#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT                                                                  0x2
#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK                                                                    0xFFFFFFFCL
//CP_RB0_RPTR_ADDR_HI
#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT                                                           0x0
#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK                                                             0x0000FFFFL
//CP_RB_RPTR_ADDR_HI
#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT                                                            0x0
#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK                                                              0x0000FFFFL
//CP_RB0_BUFSZ_MASK
#define CP_RB0_BUFSZ_MASK__DATA__SHIFT                                                                        0x0
#define CP_RB0_BUFSZ_MASK__DATA_MASK                                                                          0x000FFFFFL
//CP_RB_BUFSZ_MASK
#define CP_RB_BUFSZ_MASK__DATA__SHIFT                                                                         0x0
#define CP_RB_BUFSZ_MASK__DATA_MASK                                                                           0x000FFFFFL
//CP_INT_CNTL
#define CP_INT_CNTL__RESUME_INT_ENABLE__SHIFT                                                                 0x8
#define CP_INT_CNTL__SUSPEND_INT_ENABLE__SHIFT                                                                0x9
#define CP_INT_CNTL__DMA_WATCH_INT_ENABLE__SHIFT                                                              0xa
#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT                                                      0xb
#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                           0xe
#define CP_INT_CNTL__GPF_INT_ENABLE__SHIFT                                                                    0x10
#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                                       0x11
#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE__SHIFT                                                               0x12
#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE__SHIFT                                                              0x13
#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE__SHIFT                                                             0x14
#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE__SHIFT                                                               0x15
#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE__SHIFT                                                             0x16
#define CP_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT                                                               0x17
#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT                                                           0x18
#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT                                                             0x1a
#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                                     0x1b
#define CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT                                                               0x1d
#define CP_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT                                                               0x1e
#define CP_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT                                                               0x1f
#define CP_INT_CNTL__RESUME_INT_ENABLE_MASK                                                                   0x00000100L
#define CP_INT_CNTL__SUSPEND_INT_ENABLE_MASK                                                                  0x00000200L
#define CP_INT_CNTL__DMA_WATCH_INT_ENABLE_MASK                                                                0x00000400L
#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE_MASK                                                        0x00000800L
#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK                                                             0x00004000L
#define CP_INT_CNTL__GPF_INT_ENABLE_MASK                                                                      0x00010000L
#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                                         0x00020000L
#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE_MASK                                                                 0x00040000L
#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK                                                                0x00080000L
#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK                                                               0x00100000L
#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE_MASK                                                                 0x00200000L
#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK                                                               0x00400000L
#define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK                                                                 0x00800000L
#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK                                                             0x01000000L
#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK                                                               0x04000000L
#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                                       0x08000000L
#define CP_INT_CNTL__GENERIC2_INT_ENABLE_MASK                                                                 0x20000000L
#define CP_INT_CNTL__GENERIC1_INT_ENABLE_MASK                                                                 0x40000000L
#define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK                                                                 0x80000000L
//CP_INT_STATUS
#define CP_INT_STATUS__RESUME_INT_STAT__SHIFT                                                                 0x8
#define CP_INT_STATUS__SUSPEND_INT_STAT__SHIFT                                                                0x9
#define CP_INT_STATUS__DMA_WATCH_INT_STAT__SHIFT                                                              0xa
#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT__SHIFT                                                      0xb
#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT__SHIFT                                                           0xe
#define CP_INT_STATUS__GPF_INT_STAT__SHIFT                                                                    0x10
#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT__SHIFT                                                       0x11
#define CP_INT_STATUS__CMP_BUSY_INT_STAT__SHIFT                                                               0x12
#define CP_INT_STATUS__CNTX_BUSY_INT_STAT__SHIFT                                                              0x13
#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT__SHIFT                                                             0x14
#define CP_INT_STATUS__GFX_IDLE_INT_STAT__SHIFT                                                               0x15
#define CP_INT_STATUS__PRIV_INSTR_INT_STAT__SHIFT                                                             0x16
#define CP_INT_STATUS__PRIV_REG_INT_STAT__SHIFT                                                               0x17
#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT__SHIFT                                                           0x18
#define CP_INT_STATUS__TIME_STAMP_INT_STAT__SHIFT                                                             0x1a
#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT__SHIFT                                                     0x1b
#define CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT                                                               0x1d
#define CP_INT_STATUS__GENERIC1_INT_STAT__SHIFT                                                               0x1e
#define CP_INT_STATUS__GENERIC0_INT_STAT__SHIFT                                                               0x1f
#define CP_INT_STATUS__RESUME_INT_STAT_MASK                                                                   0x00000100L
#define CP_INT_STATUS__SUSPEND_INT_STAT_MASK                                                                  0x00000200L
#define CP_INT_STATUS__DMA_WATCH_INT_STAT_MASK                                                                0x00000400L
#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT_MASK                                                        0x00000800L
#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT_MASK                                                             0x00004000L
#define CP_INT_STATUS__GPF_INT_STAT_MASK                                                                      0x00010000L
#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT_MASK                                                         0x00020000L
#define CP_INT_STATUS__CMP_BUSY_INT_STAT_MASK                                                                 0x00040000L
#define CP_INT_STATUS__CNTX_BUSY_INT_STAT_MASK                                                                0x00080000L
#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT_MASK                                                               0x00100000L
#define CP_INT_STATUS__GFX_IDLE_INT_STAT_MASK                                                                 0x00200000L
#define CP_INT_STATUS__PRIV_INSTR_INT_STAT_MASK                                                               0x00400000L
#define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK                                                                 0x00800000L
#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT_MASK                                                             0x01000000L
#define CP_INT_STATUS__TIME_STAMP_INT_STAT_MASK                                                               0x04000000L
#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT_MASK                                                       0x08000000L
#define CP_INT_STATUS__GENERIC2_INT_STAT_MASK                                                                 0x20000000L
#define CP_INT_STATUS__GENERIC1_INT_STAT_MASK                                                                 0x40000000L
#define CP_INT_STATUS__GENERIC0_INT_STAT_MASK                                                                 0x80000000L
//CP_DEVICE_ID
#define CP_DEVICE_ID__DEVICE_ID__SHIFT                                                                        0x0
#define CP_DEVICE_ID__DEVICE_ID_MASK                                                                          0x000000FFL
//CP_ME0_PIPE_PRIORITY_CNTS
#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT                                                       0x0
#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT                                                      0x8
#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT                                                      0x10
#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT                                                       0x18
#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK                                                         0x000000FFL
#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK                                                        0x0000FF00L
#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK                                                        0x00FF0000L
#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK                                                         0xFF000000L
//CP_RING_PRIORITY_CNTS
#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT                                                           0x0
#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT                                                          0x8
#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT                                                          0x10
#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT                                                           0x18
#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT_MASK                                                             0x000000FFL
#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT_MASK                                                            0x0000FF00L
#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT_MASK                                                            0x00FF0000L
#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT_MASK                                                             0xFF000000L
//CP_ME0_PIPE0_PRIORITY
#define CP_ME0_PIPE0_PRIORITY__PRIORITY__SHIFT                                                                0x0
#define CP_ME0_PIPE0_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
//CP_RING0_PRIORITY
#define CP_RING0_PRIORITY__PRIORITY__SHIFT                                                                    0x0
#define CP_RING0_PRIORITY__PRIORITY_MASK                                                                      0x00000003L
//CP_ME0_PIPE1_PRIORITY
#define CP_ME0_PIPE1_PRIORITY__PRIORITY__SHIFT                                                                0x0
#define CP_ME0_PIPE1_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
//CP_RING1_PRIORITY
#define CP_RING1_PRIORITY__PRIORITY__SHIFT                                                                    0x0
#define CP_RING1_PRIORITY__PRIORITY_MASK                                                                      0x00000003L
//CP_ME0_PIPE2_PRIORITY
#define CP_ME0_PIPE2_PRIORITY__PRIORITY__SHIFT                                                                0x0
#define CP_ME0_PIPE2_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
//CP_RING2_PRIORITY
#define CP_RING2_PRIORITY__PRIORITY__SHIFT                                                                    0x0
#define CP_RING2_PRIORITY__PRIORITY_MASK                                                                      0x00000003L
//CP_FATAL_ERROR
#define CP_FATAL_ERROR__CPF_FATAL_ERROR__SHIFT                                                                0x0
#define CP_FATAL_ERROR__CPG_FATAL_ERROR__SHIFT                                                                0x1
#define CP_FATAL_ERROR__GFX_HALT_PROC__SHIFT                                                                  0x2
#define CP_FATAL_ERROR__DIS_CPG_FATAL_ERROR__SHIFT                                                            0x3
#define CP_FATAL_ERROR__CPG_TAG_FATAL_ERROR_EN__SHIFT                                                         0x4
#define CP_FATAL_ERROR__CPF_FATAL_ERROR_MASK                                                                  0x00000001L
#define CP_FATAL_ERROR__CPG_FATAL_ERROR_MASK                                                                  0x00000002L
#define CP_FATAL_ERROR__GFX_HALT_PROC_MASK                                                                    0x00000004L
#define CP_FATAL_ERROR__DIS_CPG_FATAL_ERROR_MASK                                                              0x00000008L
#define CP_FATAL_ERROR__CPG_TAG_FATAL_ERROR_EN_MASK                                                           0x00000010L
//CP_RB_VMID
#define CP_RB_VMID__RB0_VMID__SHIFT                                                                           0x0
#define CP_RB_VMID__RB1_VMID__SHIFT                                                                           0x8
#define CP_RB_VMID__RB2_VMID__SHIFT                                                                           0x10
#define CP_RB_VMID__RB0_VMID_MASK                                                                             0x0000000FL
#define CP_RB_VMID__RB1_VMID_MASK                                                                             0x00000F00L
#define CP_RB_VMID__RB2_VMID_MASK                                                                             0x000F0000L
//CP_ME0_PIPE0_VMID
#define CP_ME0_PIPE0_VMID__VMID__SHIFT                                                                        0x0
#define CP_ME0_PIPE0_VMID__VMID_MASK                                                                          0x0000000FL
//CP_ME0_PIPE1_VMID
#define CP_ME0_PIPE1_VMID__VMID__SHIFT                                                                        0x0
#define CP_ME0_PIPE1_VMID__VMID_MASK                                                                          0x0000000FL
//CP_RB0_WPTR
#define CP_RB0_WPTR__RB_WPTR__SHIFT                                                                           0x0
#define CP_RB0_WPTR__RB_WPTR_MASK                                                                             0xFFFFFFFFL
//CP_RB_WPTR
#define CP_RB_WPTR__RB_WPTR__SHIFT                                                                            0x0
#define CP_RB_WPTR__RB_WPTR_MASK                                                                              0xFFFFFFFFL
//CP_RB0_WPTR_HI
#define CP_RB0_WPTR_HI__RB_WPTR__SHIFT                                                                        0x0
#define CP_RB0_WPTR_HI__RB_WPTR_MASK                                                                          0xFFFFFFFFL
//CP_RB_WPTR_HI
#define CP_RB_WPTR_HI__RB_WPTR__SHIFT                                                                         0x0
#define CP_RB_WPTR_HI__RB_WPTR_MASK                                                                           0xFFFFFFFFL
//CP_RB1_WPTR
#define CP_RB1_WPTR__RB_WPTR__SHIFT                                                                           0x0
#define CP_RB1_WPTR__RB_WPTR_MASK                                                                             0xFFFFFFFFL
//CP_RB1_WPTR_HI
#define CP_RB1_WPTR_HI__RB_WPTR__SHIFT                                                                        0x0
#define CP_RB1_WPTR_HI__RB_WPTR_MASK                                                                          0xFFFFFFFFL
//CP_RB2_WPTR
#define CP_RB2_WPTR__RB_WPTR__SHIFT                                                                           0x0
#define CP_RB2_WPTR__RB_WPTR_MASK                                                                             0x000FFFFFL
//CP_PROCESS_QUANTUM
#define CP_PROCESS_QUANTUM__QUANTUM_DURATION__SHIFT                                                           0x0
#define CP_PROCESS_QUANTUM__TIMER_EXPIRED__SHIFT                                                              0x1c
#define CP_PROCESS_QUANTUM__QUANTUM_SCALE__SHIFT                                                              0x1d
#define CP_PROCESS_QUANTUM__QUANTUM_EN__SHIFT                                                                 0x1f
#define CP_PROCESS_QUANTUM__QUANTUM_DURATION_MASK                                                             0x0FFFFFFFL
#define CP_PROCESS_QUANTUM__TIMER_EXPIRED_MASK                                                                0x10000000L
#define CP_PROCESS_QUANTUM__QUANTUM_SCALE_MASK                                                                0x60000000L
#define CP_PROCESS_QUANTUM__QUANTUM_EN_MASK                                                                   0x80000000L
//CP_RB_DOORBELL_RANGE_LOWER
#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT                                               0x2
#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK                                                 0x00000FFCL
//CP_RB_DOORBELL_RANGE_UPPER
#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT                                               0x2
#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK                                                 0x00000FFCL
//CP_MEC_DOORBELL_RANGE_LOWER
#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT                                              0x2
#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK                                                0x00000FFCL
//CP_MEC_DOORBELL_RANGE_UPPER
#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT                                              0x2
#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK                                                0x00000FFCL
//CPG_UTCL1_ERROR
#define CPG_UTCL1_ERROR__ERROR_DETECTED_HALT__SHIFT                                                           0x0
#define CPG_UTCL1_ERROR__ERROR_DETECTED_HALT_MASK                                                             0x00000001L
//CPC_UTCL1_ERROR
#define CPC_UTCL1_ERROR__ERROR_DETECTED_HALT__SHIFT                                                           0x0
#define CPC_UTCL1_ERROR__ERROR_DETECTED_HALT_MASK                                                             0x00000001L
//CP_RB1_BASE
#define CP_RB1_BASE__RB_BASE__SHIFT                                                                           0x0
#define CP_RB1_BASE__RB_BASE_MASK                                                                             0xFFFFFFFFL
//CP_RB1_CNTL
#define CP_RB1_CNTL__RB_BUFSZ__SHIFT                                                                          0x0
#define CP_RB1_CNTL__RB_BLKSZ__SHIFT                                                                          0x8
#define CP_RB1_CNTL__RB_NON_PRIV__SHIFT                                                                       0xf
#define CP_RB1_CNTL__MIN_AVAILSZ__SHIFT                                                                       0x14
#define CP_RB1_CNTL__MIN_IB_AVAILSZ__SHIFT                                                                    0x16
#define CP_RB1_CNTL__CACHE_POLICY__SHIFT                                                                      0x18
#define CP_RB1_CNTL__RB_VOLATILE__SHIFT                                                                       0x1a
#define CP_RB1_CNTL__RB_NO_UPDATE__SHIFT                                                                      0x1b
#define CP_RB1_CNTL__RB_EXE__SHIFT                                                                            0x1c
#define CP_RB1_CNTL__KMD_QUEUE__SHIFT                                                                         0x1d
#define CP_RB1_CNTL__CE_HQD_NEQ_RB_HQD__SHIFT                                                                 0x1e
#define CP_RB1_CNTL__RB_RPTR_WR_ENA__SHIFT                                                                    0x1f
#define CP_RB1_CNTL__RB_BUFSZ_MASK                                                                            0x0000003FL
#define CP_RB1_CNTL__RB_BLKSZ_MASK                                                                            0x00003F00L
#define CP_RB1_CNTL__RB_NON_PRIV_MASK                                                                         0x00008000L
#define CP_RB1_CNTL__MIN_AVAILSZ_MASK                                                                         0x00300000L
#define CP_RB1_CNTL__MIN_IB_AVAILSZ_MASK                                                                      0x00C00000L
#define CP_RB1_CNTL__CACHE_POLICY_MASK                                                                        0x03000000L
#define CP_RB1_CNTL__RB_VOLATILE_MASK                                                                         0x04000000L
#define CP_RB1_CNTL__RB_NO_UPDATE_MASK                                                                        0x08000000L
#define CP_RB1_CNTL__RB_EXE_MASK                                                                              0x10000000L
#define CP_RB1_CNTL__KMD_QUEUE_MASK                                                                           0x20000000L
#define CP_RB1_CNTL__CE_HQD_NEQ_RB_HQD_MASK                                                                   0x40000000L
#define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK                                                                      0x80000000L
//CP_RB1_RPTR_ADDR
#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR__SHIFT                                                                 0x2
#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR_MASK                                                                   0xFFFFFFFCL
//CP_RB1_RPTR_ADDR_HI
#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT                                                           0x0
#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK                                                             0x0000FFFFL
//CP_RB1_BUFSZ_MASK
#define CP_RB1_BUFSZ_MASK__DATA__SHIFT                                                                        0x0
#define CP_RB1_BUFSZ_MASK__DATA_MASK                                                                          0x000FFFFFL
//CP_RB2_BASE
#define CP_RB2_BASE__RB_BASE__SHIFT                                                                           0x0
#define CP_RB2_BASE__RB_BASE_MASK                                                                             0xFFFFFFFFL
//CP_RB2_CNTL
#define CP_RB2_CNTL__RB_BUFSZ__SHIFT                                                                          0x0
#define CP_RB2_CNTL__RB_BLKSZ__SHIFT                                                                          0x8
#define CP_RB2_CNTL__RB_NON_PRIV__SHIFT                                                                       0xf
#define CP_RB2_CNTL__MIN_AVAILSZ__SHIFT                                                                       0x14
#define CP_RB2_CNTL__MIN_IB_AVAILSZ__SHIFT                                                                    0x16
#define CP_RB2_CNTL__CACHE_POLICY__SHIFT                                                                      0x18
#define CP_RB2_CNTL__RB_VOLATILE__SHIFT                                                                       0x1a
#define CP_RB2_CNTL__RB_NO_UPDATE__SHIFT                                                                      0x1b
#define CP_RB2_CNTL__RB_EXE__SHIFT                                                                            0x1c
#define CP_RB2_CNTL__KMD_QUEUE__SHIFT                                                                         0x1d
#define CP_RB2_CNTL__CE_HQD_NEQ_RB_HQD__SHIFT                                                                 0x1e
#define CP_RB2_CNTL__RB_RPTR_WR_ENA__SHIFT                                                                    0x1f
#define CP_RB2_CNTL__RB_BUFSZ_MASK                                                                            0x0000003FL
#define CP_RB2_CNTL__RB_BLKSZ_MASK                                                                            0x00003F00L
#define CP_RB2_CNTL__RB_NON_PRIV_MASK                                                                         0x00008000L
#define CP_RB2_CNTL__MIN_AVAILSZ_MASK                                                                         0x00300000L
#define CP_RB2_CNTL__MIN_IB_AVAILSZ_MASK                                                                      0x00C00000L
#define CP_RB2_CNTL__CACHE_POLICY_MASK                                                                        0x03000000L
#define CP_RB2_CNTL__RB_VOLATILE_MASK                                                                         0x04000000L
#define CP_RB2_CNTL__RB_NO_UPDATE_MASK                                                                        0x08000000L
#define CP_RB2_CNTL__RB_EXE_MASK                                                                              0x10000000L
#define CP_RB2_CNTL__KMD_QUEUE_MASK                                                                           0x20000000L
#define CP_RB2_CNTL__CE_HQD_NEQ_RB_HQD_MASK                                                                   0x40000000L
#define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK                                                                      0x80000000L
//CP_RB2_RPTR_ADDR
#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR__SHIFT                                                                 0x2
#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR_MASK                                                                   0xFFFFFFFCL
//CP_RB2_RPTR_ADDR_HI
#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT                                                           0x0
#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK                                                             0x0000FFFFL
//CP_INT_CNTL_RING0
#define CP_INT_CNTL_RING0__RESUME_INT_ENABLE__SHIFT                                                           0x8
#define CP_INT_CNTL_RING0__SUSPEND_INT_ENABLE__SHIFT                                                          0x9
#define CP_INT_CNTL_RING0__DMA_WATCH_INT_ENABLE__SHIFT                                                        0xa
#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT                                                0xb
#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                     0xe
#define CP_INT_CNTL_RING0__GPF_INT_ENABLE__SHIFT                                                              0x10
#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                                 0x11
#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE__SHIFT                                                         0x12
#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE__SHIFT                                                        0x13
#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE__SHIFT                                                       0x14
#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE__SHIFT                                                         0x15
#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE__SHIFT                                                       0x16
#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE__SHIFT                                                         0x17
#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE__SHIFT                                                     0x18
#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE__SHIFT                                                       0x1a
#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                               0x1b
#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT                                                         0x1d
#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE__SHIFT                                                         0x1e
#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE__SHIFT                                                         0x1f
#define CP_INT_CNTL_RING0__RESUME_INT_ENABLE_MASK                                                             0x00000100L
#define CP_INT_CNTL_RING0__SUSPEND_INT_ENABLE_MASK                                                            0x00000200L
#define CP_INT_CNTL_RING0__DMA_WATCH_INT_ENABLE_MASK                                                          0x00000400L
#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE_MASK                                                  0x00000800L
#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE_MASK                                                       0x00004000L
#define CP_INT_CNTL_RING0__GPF_INT_ENABLE_MASK                                                                0x00010000L
#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                                   0x00020000L
#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE_MASK                                                           0x00040000L
#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK                                                          0x00080000L
#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK                                                         0x00100000L
#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE_MASK                                                           0x00200000L
#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK                                                         0x00400000L
#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK                                                           0x00800000L
#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK                                                       0x01000000L
#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK                                                         0x04000000L
#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                                 0x08000000L
#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE_MASK                                                           0x20000000L
#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK                                                           0x40000000L
#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE_MASK                                                           0x80000000L
//CP_INT_CNTL_RING1
#define CP_INT_CNTL_RING1__DMA_WATCH_INT_ENABLE__SHIFT                                                        0xa
#define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT                                                0xb
#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                     0xe
#define CP_INT_CNTL_RING1__GPF_INT_ENABLE__SHIFT                                                              0x10
#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                                 0x11
#define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE__SHIFT                                                         0x12
#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE__SHIFT                                                        0x13
#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE__SHIFT                                                       0x14
#define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE__SHIFT                                                         0x15
#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT                                                       0x16
#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE__SHIFT                                                         0x17
#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE__SHIFT                                                     0x18
#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE__SHIFT                                                       0x1a
#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                               0x1b
#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE__SHIFT                                                         0x1d
#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE__SHIFT                                                         0x1e
#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE__SHIFT                                                         0x1f
#define CP_INT_CNTL_RING1__DMA_WATCH_INT_ENABLE_MASK                                                          0x00000400L
#define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE_MASK                                                  0x00000800L
#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE_MASK                                                       0x00004000L
#define CP_INT_CNTL_RING1__GPF_INT_ENABLE_MASK                                                                0x00010000L
#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                                   0x00020000L
#define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE_MASK                                                           0x00040000L
#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE_MASK                                                          0x00080000L
#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE_MASK                                                         0x00100000L
#define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE_MASK                                                           0x00200000L
#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK                                                         0x00400000L
#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK                                                           0x00800000L
#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK                                                       0x01000000L
#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK                                                         0x04000000L
#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                                 0x08000000L
#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK                                                           0x20000000L
#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE_MASK                                                           0x40000000L
#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE_MASK                                                           0x80000000L
//CP_INT_CNTL_RING2
#define CP_INT_CNTL_RING2__DMA_WATCH_INT_ENABLE__SHIFT                                                        0xa
#define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT                                                0xb
#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                     0xe
#define CP_INT_CNTL_RING2__GPF_INT_ENABLE__SHIFT                                                              0x10
#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                                 0x11
#define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE__SHIFT                                                         0x12
#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE__SHIFT                                                        0x13
#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE__SHIFT                                                       0x14
#define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE__SHIFT                                                         0x15
#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE__SHIFT                                                       0x16
#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE__SHIFT                                                         0x17
#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE__SHIFT                                                     0x18
#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE__SHIFT                                                       0x1a
#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                               0x1b
#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE__SHIFT                                                         0x1d
#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE__SHIFT                                                         0x1e
#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE__SHIFT                                                         0x1f
#define CP_INT_CNTL_RING2__DMA_WATCH_INT_ENABLE_MASK                                                          0x00000400L
#define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE_MASK                                                  0x00000800L
#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE_MASK                                                       0x00004000L
#define CP_INT_CNTL_RING2__GPF_INT_ENABLE_MASK                                                                0x00010000L
#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                                   0x00020000L
#define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE_MASK                                                           0x00040000L
#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE_MASK                                                          0x00080000L
#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE_MASK                                                         0x00100000L
#define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE_MASK                                                           0x00200000L
#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE_MASK                                                         0x00400000L
#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK                                                           0x00800000L
#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE_MASK                                                       0x01000000L
#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK                                                         0x04000000L
#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                                 0x08000000L
#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE_MASK                                                           0x20000000L
#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE_MASK                                                           0x40000000L
#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE_MASK                                                           0x80000000L
//CP_INT_STATUS_RING0
#define CP_INT_STATUS_RING0__RESUME_INT_STAT__SHIFT                                                           0x8
#define CP_INT_STATUS_RING0__SUSPEND_INT_STAT__SHIFT                                                          0x9
#define CP_INT_STATUS_RING0__DMA_WATCH_INT_STAT__SHIFT                                                        0xa
#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT__SHIFT                                                0xb
#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT__SHIFT                                                     0xe
#define CP_INT_STATUS_RING0__GPF_INT_STAT__SHIFT                                                              0x10
#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT__SHIFT                                                 0x11
#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT__SHIFT                                                         0x12
#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT__SHIFT                                                       0x13
#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT__SHIFT                                                       0x14
#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT__SHIFT                                                         0x15
#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT__SHIFT                                                       0x16
#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT__SHIFT                                                         0x17
#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT__SHIFT                                                     0x18
#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT__SHIFT                                                       0x1a
#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT__SHIFT                                               0x1b
#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT                                                         0x1d
#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT__SHIFT                                                         0x1e
#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT__SHIFT                                                         0x1f
#define CP_INT_STATUS_RING0__RESUME_INT_STAT_MASK                                                             0x00000100L
#define CP_INT_STATUS_RING0__SUSPEND_INT_STAT_MASK                                                            0x00000200L
#define CP_INT_STATUS_RING0__DMA_WATCH_INT_STAT_MASK                                                          0x00000400L
#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT_MASK                                                  0x00000800L
#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT_MASK                                                       0x00004000L
#define CP_INT_STATUS_RING0__GPF_INT_STAT_MASK                                                                0x00010000L
#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT_MASK                                                   0x00020000L
#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT_MASK                                                           0x00040000L
#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT_MASK                                                         0x00080000L
#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT_MASK                                                         0x00100000L
#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT_MASK                                                           0x00200000L
#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT_MASK                                                         0x00400000L
#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT_MASK                                                           0x00800000L
#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT_MASK                                                       0x01000000L
#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT_MASK                                                         0x04000000L
#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT_MASK                                                 0x08000000L
#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT_MASK                                                           0x20000000L
#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT_MASK                                                           0x40000000L
#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT_MASK                                                           0x80000000L
//CP_INT_STATUS_RING1
#define CP_INT_STATUS_RING1__DMA_WATCH_INT_STAT__SHIFT                                                        0xa
#define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT__SHIFT                                                0xb
#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT__SHIFT                                                     0xe
#define CP_INT_STATUS_RING1__GPF_INT_STAT__SHIFT                                                              0x10
#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT__SHIFT                                                 0x11
#define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT__SHIFT                                                         0x12
#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT__SHIFT                                                        0x13
#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT__SHIFT                                                       0x14
#define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT__SHIFT                                                         0x15
#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT__SHIFT                                                       0x16
#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT                                                         0x17
#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT__SHIFT                                                     0x18
#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT__SHIFT                                                       0x1a
#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT__SHIFT                                               0x1b
#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT__SHIFT                                                         0x1d
#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT__SHIFT                                                         0x1e
#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT__SHIFT                                                         0x1f
#define CP_INT_STATUS_RING1__DMA_WATCH_INT_STAT_MASK                                                          0x00000400L
#define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT_MASK                                                  0x00000800L
#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT_MASK                                                       0x00004000L
#define CP_INT_STATUS_RING1__GPF_INT_STAT_MASK                                                                0x00010000L
#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT_MASK                                                   0x00020000L
#define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT_MASK                                                           0x00040000L
#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT_MASK                                                          0x00080000L
#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT_MASK                                                         0x00100000L
#define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT_MASK                                                           0x00200000L
#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT_MASK                                                         0x00400000L
#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT_MASK                                                           0x00800000L
#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT_MASK                                                       0x01000000L
#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT_MASK                                                         0x04000000L
#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT_MASK                                                 0x08000000L
#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT_MASK                                                           0x20000000L
#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT_MASK                                                           0x40000000L
#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT_MASK                                                           0x80000000L
//CP_INT_STATUS_RING2
#define CP_INT_STATUS_RING2__DMA_WATCH_INT_STAT__SHIFT                                                        0xa
#define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT__SHIFT                                                0xb
#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT__SHIFT                                                     0xe
#define CP_INT_STATUS_RING2__GPF_INT_STAT__SHIFT                                                              0x10
#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT__SHIFT                                                 0x11
#define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT__SHIFT                                                         0x12
#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT__SHIFT                                                        0x13
#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT__SHIFT                                                       0x14
#define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT__SHIFT                                                         0x15
#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT__SHIFT                                                       0x16
#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT__SHIFT                                                         0x17
#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT__SHIFT                                                     0x18
#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT__SHIFT                                                       0x1a
#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT__SHIFT                                               0x1b
#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT__SHIFT                                                         0x1d
#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT__SHIFT                                                         0x1e
#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT__SHIFT                                                         0x1f
#define CP_INT_STATUS_RING2__DMA_WATCH_INT_STAT_MASK                                                          0x00000400L
#define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT_MASK                                                  0x00000800L
#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT_MASK                                                       0x00004000L
#define CP_INT_STATUS_RING2__GPF_INT_STAT_MASK                                                                0x00010000L
#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT_MASK                                                   0x00020000L
#define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT_MASK                                                           0x00040000L
#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT_MASK                                                          0x00080000L
#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT_MASK                                                         0x00100000L
#define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT_MASK                                                           0x00200000L
#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT_MASK                                                         0x00400000L
#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT_MASK                                                           0x00800000L
#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT_MASK                                                       0x01000000L
#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT_MASK                                                         0x04000000L
#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT_MASK                                                 0x08000000L
#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT_MASK                                                           0x20000000L
#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT_MASK                                                           0x40000000L
#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT_MASK                                                           0x80000000L
//CP_ME_F32_INTERRUPT
#define CP_ME_F32_INTERRUPT__ECC_ERROR_INT__SHIFT                                                             0x0
#define CP_ME_F32_INTERRUPT__TIME_STAMP_INT__SHIFT                                                            0x1
#define CP_ME_F32_INTERRUPT__ME_F32_INT_2__SHIFT                                                              0x2
#define CP_ME_F32_INTERRUPT__ME_F32_INT_3__SHIFT                                                              0x3
#define CP_ME_F32_INTERRUPT__ECC_ERROR_INT_MASK                                                               0x00000001L
#define CP_ME_F32_INTERRUPT__TIME_STAMP_INT_MASK                                                              0x00000002L
#define CP_ME_F32_INTERRUPT__ME_F32_INT_2_MASK                                                                0x00000004L
#define CP_ME_F32_INTERRUPT__ME_F32_INT_3_MASK                                                                0x00000008L
//CP_PFP_F32_INTERRUPT
#define CP_PFP_F32_INTERRUPT__ECC_ERROR_INT__SHIFT                                                            0x0
#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT                                                             0x1
#define CP_PFP_F32_INTERRUPT__RESERVED_BIT_ERR_INT__SHIFT                                                     0x2
#define CP_PFP_F32_INTERRUPT__PFP_F32_INT_3__SHIFT                                                            0x3
#define CP_PFP_F32_INTERRUPT__ECC_ERROR_INT_MASK                                                              0x00000001L
#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT_MASK                                                               0x00000002L
#define CP_PFP_F32_INTERRUPT__RESERVED_BIT_ERR_INT_MASK                                                       0x00000004L
#define CP_PFP_F32_INTERRUPT__PFP_F32_INT_3_MASK                                                              0x00000008L
//CP_CE_F32_INTERRUPT
#define CP_CE_F32_INTERRUPT__ECC_ERROR_INT__SHIFT                                                             0x0
#define CP_CE_F32_INTERRUPT__RESERVED_BIT_ERR_INT__SHIFT                                                      0x1
#define CP_CE_F32_INTERRUPT__CE_F32_INT_2__SHIFT                                                              0x2
#define CP_CE_F32_INTERRUPT__CE_F32_INT_3__SHIFT                                                              0x3
#define CP_CE_F32_INTERRUPT__ECC_ERROR_INT_MASK                                                               0x00000001L
#define CP_CE_F32_INTERRUPT__RESERVED_BIT_ERR_INT_MASK                                                        0x00000002L
#define CP_CE_F32_INTERRUPT__CE_F32_INT_2_MASK                                                                0x00000004L
#define CP_CE_F32_INTERRUPT__CE_F32_INT_3_MASK                                                                0x00000008L
//CP_MEC1_F32_INTERRUPT
#define CP_MEC1_F32_INTERRUPT__EDC_ROQ_FED_INT__SHIFT                                                         0x0
#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT__SHIFT                                                            0x1
#define CP_MEC1_F32_INTERRUPT__RESERVED_BIT_ERR_INT__SHIFT                                                    0x2
#define CP_MEC1_F32_INTERRUPT__EDC_TC_FED_INT__SHIFT                                                          0x3
#define CP_MEC1_F32_INTERRUPT__EDC_GDS_FED_INT__SHIFT                                                         0x4
#define CP_MEC1_F32_INTERRUPT__EDC_SCRATCH_FED_INT__SHIFT                                                     0x5
#define CP_MEC1_F32_INTERRUPT__WAVE_RESTORE_INT__SHIFT                                                        0x6
#define CP_MEC1_F32_INTERRUPT__SUA_VIOLATION_INT__SHIFT                                                       0x7
#define CP_MEC1_F32_INTERRUPT__EDC_DMA_FED_INT__SHIFT                                                         0x8
#define CP_MEC1_F32_INTERRUPT__IQ_TIMER_INT__SHIFT                                                            0x9
#define CP_MEC1_F32_INTERRUPT__GPF_INT_CPF__SHIFT                                                             0xa
#define CP_MEC1_F32_INTERRUPT__GPF_INT_DMA__SHIFT                                                             0xb
#define CP_MEC1_F32_INTERRUPT__GPF_INT_CPC__SHIFT                                                             0xc
#define CP_MEC1_F32_INTERRUPT__EDC_SR_MEM_FED_INT__SHIFT                                                      0xd
#define CP_MEC1_F32_INTERRUPT__QUEUE_MESSAGE_INT__SHIFT                                                       0xe
#define CP_MEC1_F32_INTERRUPT__FATAL_EDC_ERROR_INT__SHIFT                                                     0xf
#define CP_MEC1_F32_INTERRUPT__EDC_ROQ_FED_INT_MASK                                                           0x00000001L
#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT_MASK                                                              0x00000002L
#define CP_MEC1_F32_INTERRUPT__RESERVED_BIT_ERR_INT_MASK                                                      0x00000004L
#define CP_MEC1_F32_INTERRUPT__EDC_TC_FED_INT_MASK                                                            0x00000008L
#define CP_MEC1_F32_INTERRUPT__EDC_GDS_FED_INT_MASK                                                           0x00000010L
#define CP_MEC1_F32_INTERRUPT__EDC_SCRATCH_FED_INT_MASK                                                       0x00000020L
#define CP_MEC1_F32_INTERRUPT__WAVE_RESTORE_INT_MASK                                                          0x00000040L
#define CP_MEC1_F32_INTERRUPT__SUA_VIOLATION_INT_MASK                                                         0x00000080L
#define CP_MEC1_F32_INTERRUPT__EDC_DMA_FED_INT_MASK                                                           0x00000100L
#define CP_MEC1_F32_INTERRUPT__IQ_TIMER_INT_MASK                                                              0x00000200L
#define CP_MEC1_F32_INTERRUPT__GPF_INT_CPF_MASK                                                               0x00000400L
#define CP_MEC1_F32_INTERRUPT__GPF_INT_DMA_MASK                                                               0x00000800L
#define CP_MEC1_F32_INTERRUPT__GPF_INT_CPC_MASK                                                               0x00001000L
#define CP_MEC1_F32_INTERRUPT__EDC_SR_MEM_FED_INT_MASK                                                        0x00002000L
#define CP_MEC1_F32_INTERRUPT__QUEUE_MESSAGE_INT_MASK                                                         0x00004000L
#define CP_MEC1_F32_INTERRUPT__FATAL_EDC_ERROR_INT_MASK                                                       0x00008000L
//CP_MEC2_F32_INTERRUPT
#define CP_MEC2_F32_INTERRUPT__EDC_ROQ_FED_INT__SHIFT                                                         0x0
#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT__SHIFT                                                            0x1
#define CP_MEC2_F32_INTERRUPT__RESERVED_BIT_ERR_INT__SHIFT                                                    0x2
#define CP_MEC2_F32_INTERRUPT__EDC_TC_FED_INT__SHIFT                                                          0x3
#define CP_MEC2_F32_INTERRUPT__EDC_GDS_FED_INT__SHIFT                                                         0x4
#define CP_MEC2_F32_INTERRUPT__EDC_SCRATCH_FED_INT__SHIFT                                                     0x5
#define CP_MEC2_F32_INTERRUPT__WAVE_RESTORE_INT__SHIFT                                                        0x6
#define CP_MEC2_F32_INTERRUPT__SUA_VIOLATION_INT__SHIFT                                                       0x7
#define CP_MEC2_F32_INTERRUPT__EDC_DMA_FED_INT__SHIFT                                                         0x8
#define CP_MEC2_F32_INTERRUPT__IQ_TIMER_INT__SHIFT                                                            0x9
#define CP_MEC2_F32_INTERRUPT__GPF_INT_CPF__SHIFT                                                             0xa
#define CP_MEC2_F32_INTERRUPT__GPF_INT_DMA__SHIFT                                                             0xb
#define CP_MEC2_F32_INTERRUPT__GPF_INT_CPC__SHIFT                                                             0xc
#define CP_MEC2_F32_INTERRUPT__EDC_SR_MEM_FED_INT__SHIFT                                                      0xd
#define CP_MEC2_F32_INTERRUPT__QUEUE_MESSAGE_INT__SHIFT                                                       0xe
#define CP_MEC2_F32_INTERRUPT__FATAL_EDC_ERROR_INT__SHIFT                                                     0xf
#define CP_MEC2_F32_INTERRUPT__EDC_ROQ_FED_INT_MASK                                                           0x00000001L
#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT_MASK                                                              0x00000002L
#define CP_MEC2_F32_INTERRUPT__RESERVED_BIT_ERR_INT_MASK                                                      0x00000004L
#define CP_MEC2_F32_INTERRUPT__EDC_TC_FED_INT_MASK                                                            0x00000008L
#define CP_MEC2_F32_INTERRUPT__EDC_GDS_FED_INT_MASK                                                           0x00000010L
#define CP_MEC2_F32_INTERRUPT__EDC_SCRATCH_FED_INT_MASK                                                       0x00000020L
#define CP_MEC2_F32_INTERRUPT__WAVE_RESTORE_INT_MASK                                                          0x00000040L
#define CP_MEC2_F32_INTERRUPT__SUA_VIOLATION_INT_MASK                                                         0x00000080L
#define CP_MEC2_F32_INTERRUPT__EDC_DMA_FED_INT_MASK                                                           0x00000100L
#define CP_MEC2_F32_INTERRUPT__IQ_TIMER_INT_MASK                                                              0x00000200L
#define CP_MEC2_F32_INTERRUPT__GPF_INT_CPF_MASK                                                               0x00000400L
#define CP_MEC2_F32_INTERRUPT__GPF_INT_DMA_MASK                                                               0x00000800L
#define CP_MEC2_F32_INTERRUPT__GPF_INT_CPC_MASK                                                               0x00001000L
#define CP_MEC2_F32_INTERRUPT__EDC_SR_MEM_FED_INT_MASK                                                        0x00002000L
#define CP_MEC2_F32_INTERRUPT__QUEUE_MESSAGE_INT_MASK                                                         0x00004000L
#define CP_MEC2_F32_INTERRUPT__FATAL_EDC_ERROR_INT_MASK                                                       0x00008000L
//CP_PWR_CNTL
#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0__SHIFT                                                            0x0
#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1__SHIFT                                                            0x1
#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0__SHIFT                                                            0x8
#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT                                                            0x9
#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2__SHIFT                                                            0xa
#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3__SHIFT                                                            0xb
#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0__SHIFT                                                            0x10
#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1__SHIFT                                                            0x11
#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2__SHIFT                                                            0x12
#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3__SHIFT                                                            0x13
#define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE0__SHIFT                                                            0x14
#define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE1__SHIFT                                                            0x15
#define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE2__SHIFT                                                            0x16
#define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE3__SHIFT                                                            0x17
#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0_MASK                                                              0x00000001L
#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK                                                              0x00000002L
#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0_MASK                                                              0x00000100L
#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1_MASK                                                              0x00000200L
#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2_MASK                                                              0x00000400L
#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3_MASK                                                              0x00000800L
#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0_MASK                                                              0x00010000L
#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1_MASK                                                              0x00020000L
#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2_MASK                                                              0x00040000L
#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3_MASK                                                              0x00080000L
#define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE0_MASK                                                              0x00100000L
#define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE1_MASK                                                              0x00200000L
#define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE2_MASK                                                              0x00400000L
#define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE3_MASK                                                              0x00800000L
//CP_MEM_SLP_CNTL
#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN__SHIFT                                                                  0x0
#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN__SHIFT                                                                  0x1
#define CP_MEM_SLP_CNTL__RESERVED__SHIFT                                                                      0x2
#define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE__SHIFT                                                        0x7
#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY__SHIFT                                                            0x8
#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY__SHIFT                                                           0x10
#define CP_MEM_SLP_CNTL__RESERVED1__SHIFT                                                                     0x18
#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK                                                                    0x00000001L
#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN_MASK                                                                    0x00000002L
#define CP_MEM_SLP_CNTL__RESERVED_MASK                                                                        0x0000007CL
#define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE_MASK                                                          0x00000080L
#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY_MASK                                                              0x0000FF00L
#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY_MASK                                                             0x00FF0000L
#define CP_MEM_SLP_CNTL__RESERVED1_MASK                                                                       0xFF000000L
//CP_ECC_FIRSTOCCURRENCE
#define CP_ECC_FIRSTOCCURRENCE__INTERFACE__SHIFT                                                              0x0
#define CP_ECC_FIRSTOCCURRENCE__CLIENT__SHIFT                                                                 0x4
#define CP_ECC_FIRSTOCCURRENCE__ME__SHIFT                                                                     0x8
#define CP_ECC_FIRSTOCCURRENCE__PIPE__SHIFT                                                                   0xa
#define CP_ECC_FIRSTOCCURRENCE__QUEUE__SHIFT                                                                  0xc
#define CP_ECC_FIRSTOCCURRENCE__VMID__SHIFT                                                                   0x10
#define CP_ECC_FIRSTOCCURRENCE__INTERFACE_MASK                                                                0x00000003L
#define CP_ECC_FIRSTOCCURRENCE__CLIENT_MASK                                                                   0x000000F0L
#define CP_ECC_FIRSTOCCURRENCE__ME_MASK                                                                       0x00000300L
#define CP_ECC_FIRSTOCCURRENCE__PIPE_MASK                                                                     0x00000C00L
#define CP_ECC_FIRSTOCCURRENCE__QUEUE_MASK                                                                    0x00007000L
#define CP_ECC_FIRSTOCCURRENCE__VMID_MASK                                                                     0x000F0000L
//CP_ECC_FIRSTOCCURRENCE_RING0
#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE__SHIFT                                                         0x0
#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE_MASK                                                           0xFFFFFFFFL
//CP_ECC_FIRSTOCCURRENCE_RING1
#define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE__SHIFT                                                         0x0
#define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE_MASK                                                           0xFFFFFFFFL
//CP_ECC_FIRSTOCCURRENCE_RING2
#define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE__SHIFT                                                         0x0
#define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE_MASK                                                           0xFFFFFFFFL
//GB_EDC_MODE
#define GB_EDC_MODE__FORCE_SEC_ON_DED__SHIFT                                                                  0xf
#define GB_EDC_MODE__COUNT_FED_OUT__SHIFT                                                                     0x10
#define GB_EDC_MODE__GATE_FUE__SHIFT                                                                          0x11
#define GB_EDC_MODE__DED_MODE__SHIFT                                                                          0x14
#define GB_EDC_MODE__PROP_FED__SHIFT                                                                          0x1d
#define GB_EDC_MODE__BYPASS__SHIFT                                                                            0x1f
#define GB_EDC_MODE__FORCE_SEC_ON_DED_MASK                                                                    0x00008000L
#define GB_EDC_MODE__COUNT_FED_OUT_MASK                                                                       0x00010000L
#define GB_EDC_MODE__GATE_FUE_MASK                                                                            0x00020000L
#define GB_EDC_MODE__DED_MODE_MASK                                                                            0x00300000L
#define GB_EDC_MODE__PROP_FED_MASK                                                                            0x20000000L
#define GB_EDC_MODE__BYPASS_MASK                                                                              0x80000000L
//CP_PQ_WPTR_POLL_CNTL
#define CP_PQ_WPTR_POLL_CNTL__PERIOD__SHIFT                                                                   0x0
#define CP_PQ_WPTR_POLL_CNTL__DISABLE_PEND_REQ_ONE_SHOT__SHIFT                                                0x1d
#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE__SHIFT                                                              0x1e
#define CP_PQ_WPTR_POLL_CNTL__EN__SHIFT                                                                       0x1f
#define CP_PQ_WPTR_POLL_CNTL__PERIOD_MASK                                                                     0x000000FFL
#define CP_PQ_WPTR_POLL_CNTL__DISABLE_PEND_REQ_ONE_SHOT_MASK                                                  0x20000000L
#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE_MASK                                                                0x40000000L
#define CP_PQ_WPTR_POLL_CNTL__EN_MASK                                                                         0x80000000L
//CP_PQ_WPTR_POLL_CNTL1
#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK__SHIFT                                                              0x0
#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK_MASK                                                                0xFFFFFFFFL
//CP_ME1_PIPE0_INT_CNTL
#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT                                             0xc
#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT                                              0xd
#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                 0xe
#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT                                                0xf
#define CP_ME1_PIPE0_INT_CNTL__GPF_INT_ENABLE__SHIFT                                                          0x10
#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                             0x11
#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT                                                     0x17
#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT                                                 0x18
#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT                                                   0x1a
#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                           0x1b
#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT                                                     0x1d
#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT                                                     0x1e
#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT                                                     0x1f
#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK                                               0x00001000L
#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK                                                0x00002000L
#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK                                                   0x00004000L
#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK                                                  0x00008000L
#define CP_ME1_PIPE0_INT_CNTL__GPF_INT_ENABLE_MASK                                                            0x00010000L
#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                               0x00020000L
#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK                                                       0x00800000L
#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK                                                   0x01000000L
#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK                                                     0x04000000L
#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                             0x08000000L
#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK                                                       0x20000000L
#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK                                                       0x40000000L
#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK                                                       0x80000000L
//CP_ME1_PIPE1_INT_CNTL
#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT                                             0xc
#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT                                              0xd
#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                 0xe
#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT                                                0xf
#define CP_ME1_PIPE1_INT_CNTL__GPF_INT_ENABLE__SHIFT                                                          0x10
#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                             0x11
#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT                                                     0x17
#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT                                                 0x18
#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT                                                   0x1a
#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                           0x1b
#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT                                                     0x1d
#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT                                                     0x1e
#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT                                                     0x1f
#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK                                               0x00001000L
#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK                                                0x00002000L
#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK                                                   0x00004000L
#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK                                                  0x00008000L
#define CP_ME1_PIPE1_INT_CNTL__GPF_INT_ENABLE_MASK                                                            0x00010000L
#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                               0x00020000L
#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK                                                       0x00800000L
#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK                                                   0x01000000L
#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK                                                     0x04000000L
#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                             0x08000000L
#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK                                                       0x20000000L
#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK                                                       0x40000000L
#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK                                                       0x80000000L
//CP_ME1_PIPE2_INT_CNTL
#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT                                             0xc
#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT                                              0xd
#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                 0xe
#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT                                                0xf
#define CP_ME1_PIPE2_INT_CNTL__GPF_INT_ENABLE__SHIFT                                                          0x10
#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                             0x11
#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT                                                     0x17
#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT                                                 0x18
#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT                                                   0x1a
#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                           0x1b
#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT                                                     0x1d
#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT                                                     0x1e
#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT                                                     0x1f
#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK                                               0x00001000L
#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK                                                0x00002000L
#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK                                                   0x00004000L
#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK                                                  0x00008000L
#define CP_ME1_PIPE2_INT_CNTL__GPF_INT_ENABLE_MASK                                                            0x00010000L
#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                               0x00020000L
#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK                                                       0x00800000L
#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK                                                   0x01000000L
#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK                                                     0x04000000L
#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                             0x08000000L
#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK                                                       0x20000000L
#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK                                                       0x40000000L
#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK                                                       0x80000000L
//CP_ME1_PIPE3_INT_CNTL
#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT                                             0xc
#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT                                              0xd
#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                 0xe
#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT                                                0xf
#define CP_ME1_PIPE3_INT_CNTL__GPF_INT_ENABLE__SHIFT                                                          0x10
#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                             0x11
#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT                                                     0x17
#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT                                                 0x18
#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT                                                   0x1a
#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                           0x1b
#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT                                                     0x1d
#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT                                                     0x1e
#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT                                                     0x1f
#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK                                               0x00001000L
#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK                                                0x00002000L
#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK                                                   0x00004000L
#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK                                                  0x00008000L
#define CP_ME1_PIPE3_INT_CNTL__GPF_INT_ENABLE_MASK                                                            0x00010000L
#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                               0x00020000L
#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK                                                       0x00800000L
#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK                                                   0x01000000L
#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK                                                     0x04000000L
#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                             0x08000000L
#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK                                                       0x20000000L
#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK                                                       0x40000000L
#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK                                                       0x80000000L
//CP_ME2_PIPE0_INT_CNTL
#define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT                                             0xc
#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT                                              0xd
#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                 0xe
#define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT                                                0xf
#define CP_ME2_PIPE0_INT_CNTL__GPF_INT_ENABLE__SHIFT                                                          0x10
#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                             0x11
#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT                                                     0x17
#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT                                                 0x18
#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT                                                   0x1a
#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                           0x1b
#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT                                                     0x1d
#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT                                                     0x1e
#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT                                                     0x1f
#define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK                                               0x00001000L
#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK                                                0x00002000L
#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK                                                   0x00004000L
#define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK                                                  0x00008000L
#define CP_ME2_PIPE0_INT_CNTL__GPF_INT_ENABLE_MASK                                                            0x00010000L
#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                               0x00020000L
#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK                                                       0x00800000L
#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK                                                   0x01000000L
#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK                                                     0x04000000L
#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                             0x08000000L
#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK                                                       0x20000000L
#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK                                                       0x40000000L
#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK                                                       0x80000000L
//CP_ME2_PIPE1_INT_CNTL
#define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT                                             0xc
#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT                                              0xd
#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                 0xe
#define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT                                                0xf
#define CP_ME2_PIPE1_INT_CNTL__GPF_INT_ENABLE__SHIFT                                                          0x10
#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                             0x11
#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT                                                     0x17
#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT                                                 0x18
#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT                                                   0x1a
#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                           0x1b
#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT                                                     0x1d
#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT                                                     0x1e
#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT                                                     0x1f
#define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK                                               0x00001000L
#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK                                                0x00002000L
#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK                                                   0x00004000L
#define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK                                                  0x00008000L
#define CP_ME2_PIPE1_INT_CNTL__GPF_INT_ENABLE_MASK                                                            0x00010000L
#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                               0x00020000L
#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK                                                       0x00800000L
#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK                                                   0x01000000L
#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK                                                     0x04000000L
#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                             0x08000000L
#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK                                                       0x20000000L
#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK                                                       0x40000000L
#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK                                                       0x80000000L
//CP_ME2_PIPE2_INT_CNTL
#define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT                                             0xc
#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT                                              0xd
#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                 0xe
#define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT                                                0xf
#define CP_ME2_PIPE2_INT_CNTL__GPF_INT_ENABLE__SHIFT                                                          0x10
#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                             0x11
#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT                                                     0x17
#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT                                                 0x18
#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT                                                   0x1a
#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                           0x1b
#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT                                                     0x1d
#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT                                                     0x1e
#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT                                                     0x1f
#define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK                                               0x00001000L
#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK                                                0x00002000L
#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK                                                   0x00004000L
#define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK                                                  0x00008000L
#define CP_ME2_PIPE2_INT_CNTL__GPF_INT_ENABLE_MASK                                                            0x00010000L
#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                               0x00020000L
#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK                                                       0x00800000L
#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK                                                   0x01000000L
#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK                                                     0x04000000L
#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                             0x08000000L
#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK                                                       0x20000000L
#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK                                                       0x40000000L
#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK                                                       0x80000000L
//CP_ME2_PIPE3_INT_CNTL
#define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT                                             0xc
#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT                                              0xd
#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                 0xe
#define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT                                                0xf
#define CP_ME2_PIPE3_INT_CNTL__GPF_INT_ENABLE__SHIFT                                                          0x10
#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                             0x11
#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT                                                     0x17
#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT                                                 0x18
#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT                                                   0x1a
#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                           0x1b
#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT                                                     0x1d
#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT                                                     0x1e
#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT                                                     0x1f
#define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK                                               0x00001000L
#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK                                                0x00002000L
#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK                                                   0x00004000L
#define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK                                                  0x00008000L
#define CP_ME2_PIPE3_INT_CNTL__GPF_INT_ENABLE_MASK                                                            0x00010000L
#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                               0x00020000L
#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK                                                       0x00800000L
#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK                                                   0x01000000L
#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK                                                     0x04000000L
#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                             0x08000000L
#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK                                                       0x20000000L
#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK                                                       0x40000000L
#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK                                                       0x80000000L
//CP_ME1_PIPE0_INT_STATUS
#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT                                           0xc
#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT                                            0xd
#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT                                               0xe
#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT                                              0xf
#define CP_ME1_PIPE0_INT_STATUS__GPF_INT_STATUS__SHIFT                                                        0x10
#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT                                           0x11
#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT                                                   0x17
#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT                                               0x18
#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT                                                 0x1a
#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT                                         0x1b
#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT                                                   0x1d
#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT                                                   0x1e
#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT                                                   0x1f
#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK                                             0x00001000L
#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK                                              0x00002000L
#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK                                                 0x00004000L
#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK                                                0x00008000L
#define CP_ME1_PIPE0_INT_STATUS__GPF_INT_STATUS_MASK                                                          0x00010000L
#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK                                             0x00020000L
#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK                                                     0x00800000L
#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK                                                 0x01000000L
#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK                                                   0x04000000L
#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK                                           0x08000000L
#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK                                                     0x20000000L
#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK                                                     0x40000000L
#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK                                                     0x80000000L
//CP_ME1_PIPE1_INT_STATUS
#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT                                           0xc
#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT                                            0xd
#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT                                               0xe
#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT                                              0xf
#define CP_ME1_PIPE1_INT_STATUS__GPF_INT_STATUS__SHIFT                                                        0x10
#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT                                           0x11
#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT                                                   0x17
#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT                                               0x18
#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT                                                 0x1a
#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT                                         0x1b
#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT                                                   0x1d
#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT                                                   0x1e
#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT                                                   0x1f
#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK                                             0x00001000L
#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK                                              0x00002000L
#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK                                                 0x00004000L
#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK                                                0x00008000L
#define CP_ME1_PIPE1_INT_STATUS__GPF_INT_STATUS_MASK                                                          0x00010000L
#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK                                             0x00020000L
#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK                                                     0x00800000L
#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK                                                 0x01000000L
#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK                                                   0x04000000L
#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK                                           0x08000000L
#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK                                                     0x20000000L
#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK                                                     0x40000000L
#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK                                                     0x80000000L
//CP_ME1_PIPE2_INT_STATUS
#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT                                           0xc
#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT                                            0xd
#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT                                               0xe
#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT                                              0xf
#define CP_ME1_PIPE2_INT_STATUS__GPF_INT_STATUS__SHIFT                                                        0x10
#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT                                           0x11
#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT                                                   0x17
#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT                                               0x18
#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT                                                 0x1a
#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT                                         0x1b
#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT                                                   0x1d
#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT                                                   0x1e
#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT                                                   0x1f
#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK                                             0x00001000L
#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK                                              0x00002000L
#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK                                                 0x00004000L
#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK                                                0x00008000L
#define CP_ME1_PIPE2_INT_STATUS__GPF_INT_STATUS_MASK                                                          0x00010000L
#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK                                             0x00020000L
#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK                                                     0x00800000L
#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK                                                 0x01000000L
#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK                                                   0x04000000L
#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK                                           0x08000000L
#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK                                                     0x20000000L
#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK                                                     0x40000000L
#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK                                                     0x80000000L
//CP_ME1_PIPE3_INT_STATUS
#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT                                           0xc
#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT                                            0xd
#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT                                               0xe
#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT                                              0xf
#define CP_ME1_PIPE3_INT_STATUS__GPF_INT_STATUS__SHIFT                                                        0x10
#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT                                           0x11
#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT                                                   0x17
#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT                                               0x18
#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT                                                 0x1a
#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT                                         0x1b
#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT                                                   0x1d
#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT                                                   0x1e
#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT                                                   0x1f
#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK                                             0x00001000L
#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK                                              0x00002000L
#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK                                                 0x00004000L
#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK                                                0x00008000L
#define CP_ME1_PIPE3_INT_STATUS__GPF_INT_STATUS_MASK                                                          0x00010000L
#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK                                             0x00020000L
#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK                                                     0x00800000L
#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK                                                 0x01000000L
#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK                                                   0x04000000L
#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK                                           0x08000000L
#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK                                                     0x20000000L
#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK                                                     0x40000000L
#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK                                                     0x80000000L
//CP_ME2_PIPE0_INT_STATUS
#define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT                                           0xc
#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT                                            0xd
#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT                                               0xe
#define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT                                              0xf
#define CP_ME2_PIPE0_INT_STATUS__GPF_INT_STATUS__SHIFT                                                        0x10
#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT                                           0x11
#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT                                                   0x17
#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT                                               0x18
#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT                                                 0x1a
#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT                                         0x1b
#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT                                                   0x1d
#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT                                                   0x1e
#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT                                                   0x1f
#define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK                                             0x00001000L
#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK                                              0x00002000L
#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK                                                 0x00004000L
#define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK                                                0x00008000L
#define CP_ME2_PIPE0_INT_STATUS__GPF_INT_STATUS_MASK                                                          0x00010000L
#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK                                             0x00020000L
#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK                                                     0x00800000L
#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK                                                 0x01000000L
#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK                                                   0x04000000L
#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK                                           0x08000000L
#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK                                                     0x20000000L
#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK                                                     0x40000000L
#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK                                                     0x80000000L
//CP_ME2_PIPE1_INT_STATUS
#define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT                                           0xc
#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT                                            0xd
#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT                                               0xe
#define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT                                              0xf
#define CP_ME2_PIPE1_INT_STATUS__GPF_INT_STATUS__SHIFT                                                        0x10
#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT                                           0x11
#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT                                                   0x17
#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT                                               0x18
#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT                                                 0x1a
#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT                                         0x1b
#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT                                                   0x1d
#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT                                                   0x1e
#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT                                                   0x1f
#define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK                                             0x00001000L
#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK                                              0x00002000L
#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK                                                 0x00004000L
#define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK                                                0x00008000L
#define CP_ME2_PIPE1_INT_STATUS__GPF_INT_STATUS_MASK                                                          0x00010000L
#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK                                             0x00020000L
#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK                                                     0x00800000L
#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK                                                 0x01000000L
#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK                                                   0x04000000L
#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK                                           0x08000000L
#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK                                                     0x20000000L
#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK                                                     0x40000000L
#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK                                                     0x80000000L
//CP_ME2_PIPE2_INT_STATUS
#define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT                                           0xc
#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT                                            0xd
#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT                                               0xe
#define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT                                              0xf
#define CP_ME2_PIPE2_INT_STATUS__GPF_INT_STATUS__SHIFT                                                        0x10
#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT                                           0x11
#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT                                                   0x17
#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT                                               0x18
#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT                                                 0x1a
#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT                                         0x1b
#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT                                                   0x1d
#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT                                                   0x1e
#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT                                                   0x1f
#define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK                                             0x00001000L
#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK                                              0x00002000L
#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK                                                 0x00004000L
#define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK                                                0x00008000L
#define CP_ME2_PIPE2_INT_STATUS__GPF_INT_STATUS_MASK                                                          0x00010000L
#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK                                             0x00020000L
#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK                                                     0x00800000L
#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK                                                 0x01000000L
#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK                                                   0x04000000L
#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK                                           0x08000000L
#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK                                                     0x20000000L
#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK                                                     0x40000000L
#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK                                                     0x80000000L
//CP_ME2_PIPE3_INT_STATUS
#define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT                                           0xc
#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT                                            0xd
#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT                                               0xe
#define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT                                              0xf
#define CP_ME2_PIPE3_INT_STATUS__GPF_INT_STATUS__SHIFT                                                        0x10
#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT                                           0x11
#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT                                                   0x17
#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT                                               0x18
#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT                                                 0x1a
#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT                                         0x1b
#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT                                                   0x1d
#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT                                                   0x1e
#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT                                                   0x1f
#define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK                                             0x00001000L
#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK                                              0x00002000L
#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK                                                 0x00004000L
#define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK                                                0x00008000L
#define CP_ME2_PIPE3_INT_STATUS__GPF_INT_STATUS_MASK                                                          0x00010000L
#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK                                             0x00020000L
#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK                                                     0x00800000L
#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK                                                 0x01000000L
#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK                                                   0x04000000L
#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK                                           0x08000000L
#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK                                                     0x20000000L
#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK                                                     0x40000000L
#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK                                                     0x80000000L
#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT                                                   0x17
#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK                                                     0x00800000L
#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT                                                   0x17
#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK                                                     0x00800000L
//CP_GFX_QUEUE_INDEX
#define CP_GFX_QUEUE_INDEX__QUEUE_ACCESS__SHIFT                                                               0x0
#define CP_GFX_QUEUE_INDEX__PIPE_ID__SHIFT                                                                    0x4
#define CP_GFX_QUEUE_INDEX__QUEUE_ID__SHIFT                                                                   0x8
#define CP_GFX_QUEUE_INDEX__QUEUE_ACCESS_MASK                                                                 0x00000001L
#define CP_GFX_QUEUE_INDEX__PIPE_ID_MASK                                                                      0x00000030L
#define CP_GFX_QUEUE_INDEX__QUEUE_ID_MASK                                                                     0x00000700L
//CC_GC_EDC_CONFIG
#define CC_GC_EDC_CONFIG__DIS_EDC__SHIFT                                                                      0x1
#define CC_GC_EDC_CONFIG__DIS_EDC_MASK                                                                        0x00000002L
//CP_ME1_PIPE_PRIORITY_CNTS
#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT                                                       0x0
#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT                                                      0x8
#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT                                                      0x10
#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT                                                       0x18
#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK                                                         0x000000FFL
#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK                                                        0x0000FF00L
#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK                                                        0x00FF0000L
#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK                                                         0xFF000000L
//CP_ME1_PIPE0_PRIORITY
#define CP_ME1_PIPE0_PRIORITY__PRIORITY__SHIFT                                                                0x0
#define CP_ME1_PIPE0_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
//CP_ME1_PIPE1_PRIORITY
#define CP_ME1_PIPE1_PRIORITY__PRIORITY__SHIFT                                                                0x0
#define CP_ME1_PIPE1_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
//CP_ME1_PIPE2_PRIORITY
#define CP_ME1_PIPE2_PRIORITY__PRIORITY__SHIFT                                                                0x0
#define CP_ME1_PIPE2_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
//CP_ME1_PIPE3_PRIORITY
#define CP_ME1_PIPE3_PRIORITY__PRIORITY__SHIFT                                                                0x0
#define CP_ME1_PIPE3_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
//CP_ME2_PIPE_PRIORITY_CNTS
#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT                                                       0x0
#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT                                                      0x8
#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT                                                      0x10
#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT                                                       0x18
#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK                                                         0x000000FFL
#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK                                                        0x0000FF00L
#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK                                                        0x00FF0000L
#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK                                                         0xFF000000L
//CP_ME2_PIPE0_PRIORITY
#define CP_ME2_PIPE0_PRIORITY__PRIORITY__SHIFT                                                                0x0
#define CP_ME2_PIPE0_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
//CP_ME2_PIPE1_PRIORITY
#define CP_ME2_PIPE1_PRIORITY__PRIORITY__SHIFT                                                                0x0
#define CP_ME2_PIPE1_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
//CP_ME2_PIPE2_PRIORITY
#define CP_ME2_PIPE2_PRIORITY__PRIORITY__SHIFT                                                                0x0
#define CP_ME2_PIPE2_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
//CP_ME2_PIPE3_PRIORITY
#define CP_ME2_PIPE3_PRIORITY__PRIORITY__SHIFT                                                                0x0
#define CP_ME2_PIPE3_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
//CP_CE_PRGRM_CNTR_START
#define CP_CE_PRGRM_CNTR_START__IP_START__SHIFT                                                               0x0
#define CP_CE_PRGRM_CNTR_START__IP_START_MASK                                                                 0x000FFFFFL
//CP_PFP_PRGRM_CNTR_START
#define CP_PFP_PRGRM_CNTR_START__IP_START__SHIFT                                                              0x0
#define CP_PFP_PRGRM_CNTR_START__IP_START_MASK                                                                0x000FFFFFL
//CP_ME_PRGRM_CNTR_START
#define CP_ME_PRGRM_CNTR_START__IP_START__SHIFT                                                               0x0
#define CP_ME_PRGRM_CNTR_START__IP_START_MASK                                                                 0x000FFFFFL
//CP_MEC1_PRGRM_CNTR_START
#define CP_MEC1_PRGRM_CNTR_START__IP_START__SHIFT                                                             0x0
#define CP_MEC1_PRGRM_CNTR_START__IP_START_MASK                                                               0x000FFFFFL
//CP_MEC2_PRGRM_CNTR_START
#define CP_MEC2_PRGRM_CNTR_START__IP_START__SHIFT                                                             0x0
#define CP_MEC2_PRGRM_CNTR_START__IP_START_MASK                                                               0x000FFFFFL
//CP_CE_INTR_ROUTINE_START
#define CP_CE_INTR_ROUTINE_START__IR_START__SHIFT                                                             0x0
#define CP_CE_INTR_ROUTINE_START__IR_START_MASK                                                               0x000FFFFFL
//CP_PFP_INTR_ROUTINE_START
#define CP_PFP_INTR_ROUTINE_START__IR_START__SHIFT                                                            0x0
#define CP_PFP_INTR_ROUTINE_START__IR_START_MASK                                                              0x000FFFFFL
//CP_ME_INTR_ROUTINE_START
#define CP_ME_INTR_ROUTINE_START__IR_START__SHIFT                                                             0x0
#define CP_ME_INTR_ROUTINE_START__IR_START_MASK                                                               0x000FFFFFL
//CP_MEC1_INTR_ROUTINE_START
#define CP_MEC1_INTR_ROUTINE_START__IR_START__SHIFT                                                           0x0
#define CP_MEC1_INTR_ROUTINE_START__IR_START_MASK                                                             0x000FFFFFL
//CP_MEC2_INTR_ROUTINE_START
#define CP_MEC2_INTR_ROUTINE_START__IR_START__SHIFT                                                           0x0
#define CP_MEC2_INTR_ROUTINE_START__IR_START_MASK                                                             0x000FFFFFL
//CP_CONTEXT_CNTL
#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_GE_CNTX__SHIFT                                                          0x0
#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX__SHIFT                                                        0x4
#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_GE_CNTX__SHIFT                                                          0x10
#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX__SHIFT                                                        0x14
#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_GE_CNTX_MASK                                                            0x00000007L
#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX_MASK                                                          0x00000070L
#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_GE_CNTX_MASK                                                            0x00070000L
#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX_MASK                                                          0x00700000L
//CP_MAX_CONTEXT
#define CP_MAX_CONTEXT__MAX_CONTEXT__SHIFT                                                                    0x0
#define CP_MAX_CONTEXT__MAX_CONTEXT_MASK                                                                      0x00000007L
//CP_IQ_WAIT_TIME1
#define CP_IQ_WAIT_TIME1__IB_OFFLOAD__SHIFT                                                                   0x0
#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD__SHIFT                                                               0x8
#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD__SHIFT                                                                  0x10
#define CP_IQ_WAIT_TIME1__GWS__SHIFT                                                                          0x18
#define CP_IQ_WAIT_TIME1__IB_OFFLOAD_MASK                                                                     0x000000FFL
#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD_MASK                                                                 0x0000FF00L
#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD_MASK                                                                    0x00FF0000L
#define CP_IQ_WAIT_TIME1__GWS_MASK                                                                            0xFF000000L
//CP_IQ_WAIT_TIME2
#define CP_IQ_WAIT_TIME2__QUE_SLEEP__SHIFT                                                                    0x0
#define CP_IQ_WAIT_TIME2__SCH_WAVE__SHIFT                                                                     0x8
#define CP_IQ_WAIT_TIME2__SEM_REARM__SHIFT                                                                    0x10
#define CP_IQ_WAIT_TIME2__DEQ_RETRY__SHIFT                                                                    0x18
#define CP_IQ_WAIT_TIME2__QUE_SLEEP_MASK                                                                      0x000000FFL
#define CP_IQ_WAIT_TIME2__SCH_WAVE_MASK                                                                       0x0000FF00L
#define CP_IQ_WAIT_TIME2__SEM_REARM_MASK                                                                      0x00FF0000L
#define CP_IQ_WAIT_TIME2__DEQ_RETRY_MASK                                                                      0xFF000000L
//CP_RB0_BASE_HI
#define CP_RB0_BASE_HI__RB_BASE_HI__SHIFT                                                                     0x0
#define CP_RB0_BASE_HI__RB_BASE_HI_MASK                                                                       0x000000FFL
//CP_RB1_BASE_HI
#define CP_RB1_BASE_HI__RB_BASE_HI__SHIFT                                                                     0x0
#define CP_RB1_BASE_HI__RB_BASE_HI_MASK                                                                       0x000000FFL
//CP_VMID_RESET
#define CP_VMID_RESET__RESET_REQUEST__SHIFT                                                                   0x0
#define CP_VMID_RESET__PIPE0_QUEUES__SHIFT                                                                    0x10
#define CP_VMID_RESET__PIPE1_QUEUES__SHIFT                                                                    0x18
#define CP_VMID_RESET__RESET_REQUEST_MASK                                                                     0x0000FFFFL
#define CP_VMID_RESET__PIPE0_QUEUES_MASK                                                                      0x00FF0000L
#define CP_VMID_RESET__PIPE1_QUEUES_MASK                                                                      0xFF000000L
//CPC_INT_CNTL
#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT                                                      0xc
#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT                                                       0xd
#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                          0xe
#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT                                                         0xf
#define CPC_INT_CNTL__GPF_INT_ENABLE__SHIFT                                                                   0x10
#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                                      0x11
#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT                                                              0x17
#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT                                                          0x18
#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT                                                            0x1a
#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                                    0x1b
#define CPC_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT                                                              0x1d
#define CPC_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT                                                              0x1e
#define CPC_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT                                                              0x1f
#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK                                                        0x00001000L
#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK                                                         0x00002000L
#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK                                                            0x00004000L
#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK                                                           0x00008000L
#define CPC_INT_CNTL__GPF_INT_ENABLE_MASK                                                                     0x00010000L
#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                                        0x00020000L
#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK                                                                0x00800000L
#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK                                                            0x01000000L
#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK                                                              0x04000000L
#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                                      0x08000000L
#define CPC_INT_CNTL__GENERIC2_INT_ENABLE_MASK                                                                0x20000000L
#define CPC_INT_CNTL__GENERIC1_INT_ENABLE_MASK                                                                0x40000000L
#define CPC_INT_CNTL__GENERIC0_INT_ENABLE_MASK                                                                0x80000000L
//CPC_INT_STATUS
#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT                                                    0xc
#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT                                                     0xd
#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT                                                        0xe
#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT                                                       0xf
#define CPC_INT_STATUS__GPF_INT_STATUS__SHIFT                                                                 0x10
#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT                                                    0x11
#define CPC_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT                                                            0x17
#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT                                                        0x18
#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT                                                          0x1a
#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT                                                  0x1b
#define CPC_INT_STATUS__GENERIC2_INT_STATUS__SHIFT                                                            0x1d
#define CPC_INT_STATUS__GENERIC1_INT_STATUS__SHIFT                                                            0x1e
#define CPC_INT_STATUS__GENERIC0_INT_STATUS__SHIFT                                                            0x1f
#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK                                                      0x00001000L
#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK                                                       0x00002000L
#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK                                                          0x00004000L
#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK                                                         0x00008000L
#define CPC_INT_STATUS__GPF_INT_STATUS_MASK                                                                   0x00010000L
#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK                                                      0x00020000L
#define CPC_INT_STATUS__PRIV_REG_INT_STATUS_MASK                                                              0x00800000L
#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK                                                          0x01000000L
#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS_MASK                                                            0x04000000L
#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK                                                    0x08000000L
#define CPC_INT_STATUS__GENERIC2_INT_STATUS_MASK                                                              0x20000000L
#define CPC_INT_STATUS__GENERIC1_INT_STATUS_MASK                                                              0x40000000L
#define CPC_INT_STATUS__GENERIC0_INT_STATUS_MASK                                                              0x80000000L
//CP_VMID_PREEMPT
#define CP_VMID_PREEMPT__PREEMPT_REQUEST__SHIFT                                                               0x0
#define CP_VMID_PREEMPT__VIRT_COMMAND__SHIFT                                                                  0x10
#define CP_VMID_PREEMPT__PREEMPT_REQUEST_MASK                                                                 0x0000FFFFL
#define CP_VMID_PREEMPT__VIRT_COMMAND_MASK                                                                    0x000F0000L
//CPC_INT_CNTX_ID
#define CPC_INT_CNTX_ID__CNTX_ID__SHIFT                                                                       0x0
#define CPC_INT_CNTX_ID__CNTX_ID_MASK                                                                         0xFFFFFFFFL
//CP_PQ_STATUS
#define CP_PQ_STATUS__DOORBELL_UPDATED__SHIFT                                                                 0x0
#define CP_PQ_STATUS__DOORBELL_ENABLE__SHIFT                                                                  0x1
#define CP_PQ_STATUS__DOORBELL_UPDATED_EN__SHIFT                                                              0x2
#define CP_PQ_STATUS__DOORBELL_UPDATED_MODE__SHIFT                                                            0x3
#define CP_PQ_STATUS__DOORBELL_UPDATED_MASK                                                                   0x00000001L
#define CP_PQ_STATUS__DOORBELL_ENABLE_MASK                                                                    0x00000002L
#define CP_PQ_STATUS__DOORBELL_UPDATED_EN_MASK                                                                0x00000004L
#define CP_PQ_STATUS__DOORBELL_UPDATED_MODE_MASK                                                              0x00000008L
//CP_MEC1_F32_INT_DIS
#define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT                                                           0x0
#define CP_MEC1_F32_INT_DIS__PRIV_REG_INT__SHIFT                                                              0x1
#define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT                                                      0x2
#define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT__SHIFT                                                            0x3
#define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT                                                           0x4
#define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT                                                       0x5
#define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT                                                          0x6
#define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT                                                         0x7
#define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT                                                           0x8
#define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT__SHIFT                                                              0x9
#define CP_MEC1_F32_INT_DIS__GPF_INT_CPF__SHIFT                                                               0xa
#define CP_MEC1_F32_INT_DIS__GPF_INT_DMA__SHIFT                                                               0xb
#define CP_MEC1_F32_INT_DIS__GPF_INT_CPC__SHIFT                                                               0xc
#define CP_MEC1_F32_INT_DIS__EDC_SR_MEM_FED_INT__SHIFT                                                        0xd
#define CP_MEC1_F32_INT_DIS__QUEUE_MESSAGE_INT__SHIFT                                                         0xe
#define CP_MEC1_F32_INT_DIS__FATAL_EDC_ERROR_INT__SHIFT                                                       0xf
#define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT_MASK                                                             0x00000001L
#define CP_MEC1_F32_INT_DIS__PRIV_REG_INT_MASK                                                                0x00000002L
#define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK                                                        0x00000004L
#define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT_MASK                                                              0x00000008L
#define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT_MASK                                                             0x00000010L
#define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK                                                         0x00000020L
#define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT_MASK                                                            0x00000040L
#define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT_MASK                                                           0x00000080L
#define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT_MASK                                                             0x00000100L
#define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT_MASK                                                                0x00000200L
#define CP_MEC1_F32_INT_DIS__GPF_INT_CPF_MASK                                                                 0x00000400L
#define CP_MEC1_F32_INT_DIS__GPF_INT_DMA_MASK                                                                 0x00000800L
#define CP_MEC1_F32_INT_DIS__GPF_INT_CPC_MASK                                                                 0x00001000L
#define CP_MEC1_F32_INT_DIS__EDC_SR_MEM_FED_INT_MASK                                                          0x00002000L
#define CP_MEC1_F32_INT_DIS__QUEUE_MESSAGE_INT_MASK                                                           0x00004000L
#define CP_MEC1_F32_INT_DIS__FATAL_EDC_ERROR_INT_MASK                                                         0x00008000L
//CP_MEC2_F32_INT_DIS
#define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT                                                           0x0
#define CP_MEC2_F32_INT_DIS__PRIV_REG_INT__SHIFT                                                              0x1
#define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT                                                      0x2
#define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT__SHIFT                                                            0x3
#define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT                                                           0x4
#define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT                                                       0x5
#define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT                                                          0x6
#define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT                                                         0x7
#define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT                                                           0x8
#define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT__SHIFT                                                              0x9
#define CP_MEC2_F32_INT_DIS__GPF_INT_CPF__SHIFT                                                               0xa
#define CP_MEC2_F32_INT_DIS__GPF_INT_DMA__SHIFT                                                               0xb
#define CP_MEC2_F32_INT_DIS__GPF_INT_CPC__SHIFT                                                               0xc
#define CP_MEC2_F32_INT_DIS__EDC_SR_MEM_FED_INT__SHIFT                                                        0xd
#define CP_MEC2_F32_INT_DIS__QUEUE_MESSAGE_INT__SHIFT                                                         0xe
#define CP_MEC2_F32_INT_DIS__FATAL_EDC_ERROR_INT__SHIFT                                                       0xf
#define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT_MASK                                                             0x00000001L
#define CP_MEC2_F32_INT_DIS__PRIV_REG_INT_MASK                                                                0x00000002L
#define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK                                                        0x00000004L
#define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT_MASK                                                              0x00000008L
#define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT_MASK                                                             0x00000010L
#define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK                                                         0x00000020L
#define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT_MASK                                                            0x00000040L
#define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT_MASK                                                           0x00000080L
#define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT_MASK                                                             0x00000100L
#define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT_MASK                                                                0x00000200L
#define CP_MEC2_F32_INT_DIS__GPF_INT_CPF_MASK                                                                 0x00000400L
#define CP_MEC2_F32_INT_DIS__GPF_INT_DMA_MASK                                                                 0x00000800L
#define CP_MEC2_F32_INT_DIS__GPF_INT_CPC_MASK                                                                 0x00001000L
#define CP_MEC2_F32_INT_DIS__EDC_SR_MEM_FED_INT_MASK                                                          0x00002000L
#define CP_MEC2_F32_INT_DIS__QUEUE_MESSAGE_INT_MASK                                                           0x00004000L
#define CP_MEC2_F32_INT_DIS__FATAL_EDC_ERROR_INT_MASK                                                         0x00008000L
//CP_VMID_STATUS
#define CP_VMID_STATUS__PREEMPT_DE_STATUS__SHIFT                                                              0x0
#define CP_VMID_STATUS__PREEMPT_CE_STATUS__SHIFT                                                              0x10
#define CP_VMID_STATUS__PREEMPT_DE_STATUS_MASK                                                                0x0000FFFFL
#define CP_VMID_STATUS__PREEMPT_CE_STATUS_MASK                                                                0xFFFF0000L
//CPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO
#define CPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO__ADDR__SHIFT                                                        0xc
#define CPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO__ADDR_MASK                                                          0xFFFFF000L
//CPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI
#define CPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI__ADDR_HI__SHIFT                                                     0x0
#define CPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI__ADDR_HI_MASK                                                       0x0000FFFFL
//CPC_SUSPEND_CTX_SAVE_CONTROL
#define CPC_SUSPEND_CTX_SAVE_CONTROL__POLICY__SHIFT                                                           0x3
#define CPC_SUSPEND_CTX_SAVE_CONTROL__EXE_DISABLE__SHIFT                                                      0x17
#define CPC_SUSPEND_CTX_SAVE_CONTROL__POLICY_MASK                                                             0x00000018L
#define CPC_SUSPEND_CTX_SAVE_CONTROL__EXE_DISABLE_MASK                                                        0x00800000L
//CPC_SUSPEND_CNTL_STACK_OFFSET
#define CPC_SUSPEND_CNTL_STACK_OFFSET__OFFSET__SHIFT                                                          0x2
#define CPC_SUSPEND_CNTL_STACK_OFFSET__OFFSET_MASK                                                            0x00007FFCL
//CPC_SUSPEND_CNTL_STACK_SIZE
#define CPC_SUSPEND_CNTL_STACK_SIZE__SIZE__SHIFT                                                              0xc
#define CPC_SUSPEND_CNTL_STACK_SIZE__SIZE_MASK                                                                0x00007000L
//CPC_SUSPEND_WG_STATE_OFFSET
#define CPC_SUSPEND_WG_STATE_OFFSET__OFFSET__SHIFT                                                            0x2
#define CPC_SUSPEND_WG_STATE_OFFSET__OFFSET_MASK                                                              0x01FFFFFCL
//CPC_SUSPEND_CTX_SAVE_SIZE
#define CPC_SUSPEND_CTX_SAVE_SIZE__SIZE__SHIFT                                                                0xc
#define CPC_SUSPEND_CTX_SAVE_SIZE__SIZE_MASK                                                                  0x01FFF000L
//CPC_OS_PIPES
#define CPC_OS_PIPES__OS_PIPES__SHIFT                                                                         0x0
#define CPC_OS_PIPES__OS_PIPES_MASK                                                                           0x000000FFL
//CP_SUSPEND_RESUME_REQ
#define CP_SUSPEND_RESUME_REQ__SUSPEND_REQ__SHIFT                                                             0x0
#define CP_SUSPEND_RESUME_REQ__RESUME_REQ__SHIFT                                                              0x1
#define CP_SUSPEND_RESUME_REQ__SUSPEND_REQ_MASK                                                               0x00000001L
#define CP_SUSPEND_RESUME_REQ__RESUME_REQ_MASK                                                                0x00000002L
//CP_SUSPEND_CNTL
#define CP_SUSPEND_CNTL__SUSPEND_MODE__SHIFT                                                                  0x0
#define CP_SUSPEND_CNTL__SUSPEND_ENABLE__SHIFT                                                                0x1
#define CP_SUSPEND_CNTL__RESUME_LOCK__SHIFT                                                                   0x2
#define CP_SUSPEND_CNTL__ACE_SUSPEND_ACTIVE__SHIFT                                                            0x3
#define CP_SUSPEND_CNTL__SUSPEND_MODE_MASK                                                                    0x00000001L
#define CP_SUSPEND_CNTL__SUSPEND_ENABLE_MASK                                                                  0x00000002L
#define CP_SUSPEND_CNTL__RESUME_LOCK_MASK                                                                     0x00000004L
#define CP_SUSPEND_CNTL__ACE_SUSPEND_ACTIVE_MASK                                                              0x00000008L
//CP_IQ_WAIT_TIME3
#define CP_IQ_WAIT_TIME3__SUSPEND_QUE__SHIFT                                                                  0x0
#define CP_IQ_WAIT_TIME3__SUSPEND_QUE_MASK                                                                    0x000000FFL
//CPC_DDID_BASE_ADDR_LO
#define CPC_DDID_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT                                                            0x6
#define CPC_DDID_BASE_ADDR_LO__BASE_ADDR_LO_MASK                                                              0xFFFFFFC0L
//CP_DDID_BASE_ADDR_LO
#define CP_DDID_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT                                                             0x6
#define CP_DDID_BASE_ADDR_LO__BASE_ADDR_LO_MASK                                                               0xFFFFFFC0L
//CPC_DDID_BASE_ADDR_HI
#define CPC_DDID_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT                                                            0x0
#define CPC_DDID_BASE_ADDR_HI__BASE_ADDR_HI_MASK                                                              0x0000FFFFL
//CP_DDID_BASE_ADDR_HI
#define CP_DDID_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT                                                             0x0
#define CP_DDID_BASE_ADDR_HI__BASE_ADDR_HI_MASK                                                               0x0000FFFFL
//CPC_DDID_CNTL
#define CPC_DDID_CNTL__THRESHOLD__SHIFT                                                                       0x0
#define CPC_DDID_CNTL__SIZE__SHIFT                                                                            0x10
#define CPC_DDID_CNTL__NO_RING_MEMORY__SHIFT                                                                  0x13
#define CPC_DDID_CNTL__POLICY__SHIFT                                                                          0x1c
#define CPC_DDID_CNTL__MODE__SHIFT                                                                            0x1e
#define CPC_DDID_CNTL__ENABLE__SHIFT                                                                          0x1f
#define CPC_DDID_CNTL__THRESHOLD_MASK                                                                         0x000000FFL
#define CPC_DDID_CNTL__SIZE_MASK                                                                              0x00010000L
#define CPC_DDID_CNTL__NO_RING_MEMORY_MASK                                                                    0x00080000L
#define CPC_DDID_CNTL__POLICY_MASK                                                                            0x30000000L
#define CPC_DDID_CNTL__MODE_MASK                                                                              0x40000000L
#define CPC_DDID_CNTL__ENABLE_MASK                                                                            0x80000000L
//CP_DDID_CNTL
#define CP_DDID_CNTL__THRESHOLD__SHIFT                                                                        0x0
#define CP_DDID_CNTL__SIZE__SHIFT                                                                             0x10
#define CP_DDID_CNTL__NO_RING_MEMORY__SHIFT                                                                   0x13
#define CP_DDID_CNTL__VMID__SHIFT                                                                             0x14
#define CP_DDID_CNTL__VMID_SEL__SHIFT                                                                         0x18
#define CP_DDID_CNTL__POLICY__SHIFT                                                                           0x1c
#define CP_DDID_CNTL__MODE__SHIFT                                                                             0x1e
#define CP_DDID_CNTL__ENABLE__SHIFT                                                                           0x1f
#define CP_DDID_CNTL__THRESHOLD_MASK                                                                          0x000000FFL
#define CP_DDID_CNTL__SIZE_MASK                                                                               0x00010000L
#define CP_DDID_CNTL__NO_RING_MEMORY_MASK                                                                     0x00080000L
#define CP_DDID_CNTL__VMID_MASK                                                                               0x00F00000L
#define CP_DDID_CNTL__VMID_SEL_MASK                                                                           0x01000000L
#define CP_DDID_CNTL__POLICY_MASK                                                                             0x30000000L
#define CP_DDID_CNTL__MODE_MASK                                                                               0x40000000L
#define CP_DDID_CNTL__ENABLE_MASK                                                                             0x80000000L
//CP_GFX_DDID_INFLIGHT_COUNT
#define CP_GFX_DDID_INFLIGHT_COUNT__COUNT__SHIFT                                                              0x0
#define CP_GFX_DDID_INFLIGHT_COUNT__COUNT_MASK                                                                0x0000FFFFL
//CP_GFX_DDID_WPTR
#define CP_GFX_DDID_WPTR__COUNT__SHIFT                                                                        0x0
#define CP_GFX_DDID_WPTR__COUNT_MASK                                                                          0x0000FFFFL
//CP_GFX_DDID_RPTR
#define CP_GFX_DDID_RPTR__COUNT__SHIFT                                                                        0x0
#define CP_GFX_DDID_RPTR__COUNT_MASK                                                                          0x0000FFFFL
//CP_GFX_DDID_DELTA_RPT_COUNT
#define CP_GFX_DDID_DELTA_RPT_COUNT__COUNT__SHIFT                                                             0x0
#define CP_GFX_DDID_DELTA_RPT_COUNT__COUNT_MASK                                                               0x000000FFL
//CP_GFX_HPD_STATUS0
#define CP_GFX_HPD_STATUS0__QUEUE_STATE__SHIFT                                                                0x0
#define CP_GFX_HPD_STATUS0__MAPPED_QUEUE__SHIFT                                                               0x5
#define CP_GFX_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT                                                            0x8
#define CP_GFX_HPD_STATUS0__FORCE_MAPPED_QUEUE__SHIFT                                                         0x10
#define CP_GFX_HPD_STATUS0__FORCE_QUEUE_STATE__SHIFT                                                          0x14
#define CP_GFX_HPD_STATUS0__SUSPEND_REQ__SHIFT                                                                0x1c
#define CP_GFX_HPD_STATUS0__ENABLE_OVERIDE_QUEUEID__SHIFT                                                     0x1d
#define CP_GFX_HPD_STATUS0__OVERIDE_QUEUEID__SHIFT                                                            0x1e
#define CP_GFX_HPD_STATUS0__FORCE_QUEUE__SHIFT                                                                0x1f
#define CP_GFX_HPD_STATUS0__QUEUE_STATE_MASK                                                                  0x0000001FL
#define CP_GFX_HPD_STATUS0__MAPPED_QUEUE_MASK                                                                 0x000000E0L
#define CP_GFX_HPD_STATUS0__QUEUE_AVAILABLE_MASK                                                              0x0000FF00L
#define CP_GFX_HPD_STATUS0__FORCE_MAPPED_QUEUE_MASK                                                           0x00070000L
#define CP_GFX_HPD_STATUS0__FORCE_QUEUE_STATE_MASK                                                            0x01F00000L
#define CP_GFX_HPD_STATUS0__SUSPEND_REQ_MASK                                                                  0x10000000L
#define CP_GFX_HPD_STATUS0__ENABLE_OVERIDE_QUEUEID_MASK                                                       0x20000000L
#define CP_GFX_HPD_STATUS0__OVERIDE_QUEUEID_MASK                                                              0x40000000L
#define CP_GFX_HPD_STATUS0__FORCE_QUEUE_MASK                                                                  0x80000000L
//CP_GFX_HPD_CONTROL0
#define CP_GFX_HPD_CONTROL0__SUSPEND_ENABLE__SHIFT                                                            0x0
#define CP_GFX_HPD_CONTROL0__PIPE_HOLDING__SHIFT                                                              0x4
#define CP_GFX_HPD_CONTROL0__RB_CE_ROQ_CNTL__SHIFT                                                            0x8
#define CP_GFX_HPD_CONTROL0__SUSPEND_ENABLE_MASK                                                              0x00000001L
#define CP_GFX_HPD_CONTROL0__PIPE_HOLDING_MASK                                                                0x00000010L
#define CP_GFX_HPD_CONTROL0__RB_CE_ROQ_CNTL_MASK                                                              0x00000100L
//CP_GFX_HPD_OSPRE_FENCE_ADDR_LO
#define CP_GFX_HPD_OSPRE_FENCE_ADDR_LO__ADDR_LO__SHIFT                                                        0x2
#define CP_GFX_HPD_OSPRE_FENCE_ADDR_LO__ADDR_LO_MASK                                                          0xFFFFFFFCL
//CP_GFX_HPD_OSPRE_FENCE_ADDR_HI
#define CP_GFX_HPD_OSPRE_FENCE_ADDR_HI__ADDR_HI__SHIFT                                                        0x0
#define CP_GFX_HPD_OSPRE_FENCE_ADDR_HI__RSVD__SHIFT                                                           0x10
#define CP_GFX_HPD_OSPRE_FENCE_ADDR_HI__ADDR_HI_MASK                                                          0x0000FFFFL
#define CP_GFX_HPD_OSPRE_FENCE_ADDR_HI__RSVD_MASK                                                             0xFFFF0000L
//CP_GFX_HPD_OSPRE_FENCE_DATA_LO
#define CP_GFX_HPD_OSPRE_FENCE_DATA_LO__DATA_LO__SHIFT                                                        0x0
#define CP_GFX_HPD_OSPRE_FENCE_DATA_LO__DATA_LO_MASK                                                          0xFFFFFFFFL
//CP_GFX_HPD_OSPRE_FENCE_DATA_HI
#define CP_GFX_HPD_OSPRE_FENCE_DATA_HI__DATA_HI__SHIFT                                                        0x0
#define CP_GFX_HPD_OSPRE_FENCE_DATA_HI__DATA_HI_MASK                                                          0xFFFFFFFFL
//CP_GFX_INDEX_MUTEX
#define CP_GFX_INDEX_MUTEX__REQUEST__SHIFT                                                                    0x0
#define CP_GFX_INDEX_MUTEX__CLIENTID__SHIFT                                                                   0x1
#define CP_GFX_INDEX_MUTEX__REQUEST_MASK                                                                      0x00000001L
#define CP_GFX_INDEX_MUTEX__CLIENTID_MASK                                                                     0x0000000EL
//CP_GFX_MQD_BASE_ADDR
#define CP_GFX_MQD_BASE_ADDR__BASE_ADDR__SHIFT                                                                0x2
#define CP_GFX_MQD_BASE_ADDR__BASE_ADDR_MASK                                                                  0xFFFFFFFCL
//CP_GFX_MQD_BASE_ADDR_HI
#define CP_GFX_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT                                                          0x0
#define CP_GFX_MQD_BASE_ADDR_HI__APP_VMID__SHIFT                                                              0x1c
#define CP_GFX_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK                                                            0x0000FFFFL
#define CP_GFX_MQD_BASE_ADDR_HI__APP_VMID_MASK                                                                0xF0000000L
//CP_GFX_HQD_ACTIVE
#define CP_GFX_HQD_ACTIVE__ACTIVE__SHIFT                                                                      0x0
#define CP_GFX_HQD_ACTIVE__ACTIVE_MASK                                                                        0x00000001L
//CP_GFX_HQD_VMID
#define CP_GFX_HQD_VMID__VMID__SHIFT                                                                          0x0
#define CP_GFX_HQD_VMID__VMID_MASK                                                                            0x0000000FL
//CP_GFX_HQD_QUEUE_PRIORITY
#define CP_GFX_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT                                                      0x0
#define CP_GFX_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK                                                        0x0000000FL
//CP_GFX_HQD_QUANTUM
#define CP_GFX_HQD_QUANTUM__QUANTUM_EN__SHIFT                                                                 0x0
#define CP_GFX_HQD_QUANTUM__QUANTUM_SCALE__SHIFT                                                              0x3
#define CP_GFX_HQD_QUANTUM__QUANTUM_DURATION__SHIFT                                                           0x8
#define CP_GFX_HQD_QUANTUM__QUANTUM_ACTIVE__SHIFT                                                             0x1f
#define CP_GFX_HQD_QUANTUM__QUANTUM_EN_MASK                                                                   0x00000001L
#define CP_GFX_HQD_QUANTUM__QUANTUM_SCALE_MASK                                                                0x00000018L
#define CP_GFX_HQD_QUANTUM__QUANTUM_DURATION_MASK                                                             0x0000FF00L
#define CP_GFX_HQD_QUANTUM__QUANTUM_ACTIVE_MASK                                                               0x80000000L
//CP_GFX_HQD_BASE
#define CP_GFX_HQD_BASE__RB_BASE__SHIFT                                                                       0x0
#define CP_GFX_HQD_BASE__RB_BASE_MASK                                                                         0xFFFFFFFFL
//CP_GFX_HQD_BASE_HI
#define CP_GFX_HQD_BASE_HI__RB_BASE_HI__SHIFT                                                                 0x0
#define CP_GFX_HQD_BASE_HI__RB_BASE_HI_MASK                                                                   0x000000FFL
//CP_GFX_HQD_RPTR
#define CP_GFX_HQD_RPTR__RB_RPTR__SHIFT                                                                       0x0
#define CP_GFX_HQD_RPTR__RB_RPTR_MASK                                                                         0x000FFFFFL
//CP_GFX_HQD_RPTR_ADDR
#define CP_GFX_HQD_RPTR_ADDR__RB_RPTR_ADDR__SHIFT                                                             0x2
#define CP_GFX_HQD_RPTR_ADDR__RB_RPTR_ADDR_MASK                                                               0xFFFFFFFCL
//CP_GFX_HQD_RPTR_ADDR_HI
#define CP_GFX_HQD_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT                                                       0x0
#define CP_GFX_HQD_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK                                                         0x0000FFFFL
//CP_RB_WPTR_POLL_ADDR_LO
#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO__SHIFT                                                  0x2
#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO_MASK                                                    0xFFFFFFFCL
//CP_RB_WPTR_POLL_ADDR_HI
#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI__SHIFT                                                  0x0
#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI_MASK                                                    0x0000FFFFL
//CP_RB_DOORBELL_CONTROL
#define CP_RB_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT                                                      0x1
#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT                                                        0x2
#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN__SHIFT                                                            0x1e
#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT                                                           0x1f
#define CP_RB_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK                                                        0x00000002L
#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK                                                          0x0FFFFFFCL
#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN_MASK                                                              0x40000000L
#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT_MASK                                                             0x80000000L
//CP_GFX_HQD_OFFSET
#define CP_GFX_HQD_OFFSET__RB_OFFSET__SHIFT                                                                   0x0
#define CP_GFX_HQD_OFFSET__DISABLE_RB_OFFSET__SHIFT                                                           0x1f
#define CP_GFX_HQD_OFFSET__RB_OFFSET_MASK                                                                     0x000FFFFFL
#define CP_GFX_HQD_OFFSET__DISABLE_RB_OFFSET_MASK                                                             0x80000000L
//CP_GFX_HQD_CNTL
#define CP_GFX_HQD_CNTL__RB_BUFSZ__SHIFT                                                                      0x0
#define CP_GFX_HQD_CNTL__RB_BLKSZ__SHIFT                                                                      0x8
#define CP_GFX_HQD_CNTL__RB_NON_PRIV__SHIFT                                                                   0xf
#define CP_GFX_HQD_CNTL__BUF_SWAP__SHIFT                                                                      0x10
#define CP_GFX_HQD_CNTL__MIN_AVAILSZ__SHIFT                                                                   0x14
#define CP_GFX_HQD_CNTL__MIN_IB_AVAILSZ__SHIFT                                                                0x16
#define CP_GFX_HQD_CNTL__CACHE_POLICY__SHIFT                                                                  0x18
#define CP_GFX_HQD_CNTL__RB_VOLATILE__SHIFT                                                                   0x1a
#define CP_GFX_HQD_CNTL__RB_NO_UPDATE__SHIFT                                                                  0x1b
#define CP_GFX_HQD_CNTL__RB_EXE__SHIFT                                                                        0x1c
#define CP_GFX_HQD_CNTL__KMD_QUEUE__SHIFT                                                                     0x1d
#define CP_GFX_HQD_CNTL__CE_HQD_NEQ_RB_HQD__SHIFT                                                             0x1e
#define CP_GFX_HQD_CNTL__RB_RPTR_WR_ENA__SHIFT                                                                0x1f
#define CP_GFX_HQD_CNTL__RB_BUFSZ_MASK                                                                        0x0000003FL
#define CP_GFX_HQD_CNTL__RB_BLKSZ_MASK                                                                        0x00003F00L
#define CP_GFX_HQD_CNTL__RB_NON_PRIV_MASK                                                                     0x00008000L
#define CP_GFX_HQD_CNTL__BUF_SWAP_MASK                                                                        0x00030000L
#define CP_GFX_HQD_CNTL__MIN_AVAILSZ_MASK                                                                     0x00300000L
#define CP_GFX_HQD_CNTL__MIN_IB_AVAILSZ_MASK                                                                  0x00C00000L
#define CP_GFX_HQD_CNTL__CACHE_POLICY_MASK                                                                    0x03000000L
#define CP_GFX_HQD_CNTL__RB_VOLATILE_MASK                                                                     0x04000000L
#define CP_GFX_HQD_CNTL__RB_NO_UPDATE_MASK                                                                    0x08000000L
#define CP_GFX_HQD_CNTL__RB_EXE_MASK                                                                          0x10000000L
#define CP_GFX_HQD_CNTL__KMD_QUEUE_MASK                                                                       0x20000000L
#define CP_GFX_HQD_CNTL__CE_HQD_NEQ_RB_HQD_MASK                                                               0x40000000L
#define CP_GFX_HQD_CNTL__RB_RPTR_WR_ENA_MASK                                                                  0x80000000L
//CP_GFX_HQD_CSMD_RPTR
#define CP_GFX_HQD_CSMD_RPTR__RB_RPTR__SHIFT                                                                  0x0
#define CP_GFX_HQD_CSMD_RPTR__RB_RPTR_MASK                                                                    0x000FFFFFL
//CP_GFX_HQD_WPTR
#define CP_GFX_HQD_WPTR__RB_WPTR__SHIFT                                                                       0x0
#define CP_GFX_HQD_WPTR__RB_WPTR_MASK                                                                         0xFFFFFFFFL
//CP_GFX_HQD_WPTR_HI
#define CP_GFX_HQD_WPTR_HI__RB_WPTR__SHIFT                                                                    0x0
#define CP_GFX_HQD_WPTR_HI__RB_WPTR_MASK                                                                      0xFFFFFFFFL
//CP_GFX_HQD_DEQUEUE_REQUEST
#define CP_GFX_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT                                                        0x0
#define CP_GFX_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT                                                        0x4
#define CP_GFX_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN__SHIFT                                                     0x9
#define CP_GFX_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN__SHIFT                                                     0xa
#define CP_GFX_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK                                                          0x00000001L
#define CP_GFX_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK                                                          0x00000010L
#define CP_GFX_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN_MASK                                                       0x00000200L
#define CP_GFX_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN_MASK                                                       0x00000400L
//CP_GFX_HQD_MAPPED
#define CP_GFX_HQD_MAPPED__MAPPED__SHIFT                                                                      0x0
#define CP_GFX_HQD_MAPPED__MAPPED_MASK                                                                        0x00000001L
//CP_GFX_HQD_QUE_MGR_CONTROL
#define CP_GFX_HQD_QUE_MGR_CONTROL__CONTROL__SHIFT                                                            0x0
#define CP_GFX_HQD_QUE_MGR_CONTROL__CONTROL_MASK                                                              0x00FFFFFFL
//CP_GFX_HQD_HQ_STATUS0
#define CP_GFX_HQD_HQ_STATUS0__DEQUEUE_STATUS__SHIFT                                                          0x0
#define CP_GFX_HQD_HQ_STATUS0__OS_PREEMPT_STATUS__SHIFT                                                       0x4
#define CP_GFX_HQD_HQ_STATUS0__PREEMPT_ACK__SHIFT                                                             0x6
#define CP_GFX_HQD_HQ_STATUS0__QUEUE_IDLE__SHIFT                                                              0x1e
#define CP_GFX_HQD_HQ_STATUS0__DEQUEUE_STATUS_MASK                                                            0x00000001L
#define CP_GFX_HQD_HQ_STATUS0__OS_PREEMPT_STATUS_MASK                                                         0x00000030L
#define CP_GFX_HQD_HQ_STATUS0__PREEMPT_ACK_MASK                                                               0x00000040L
#define CP_GFX_HQD_HQ_STATUS0__QUEUE_IDLE_MASK                                                                0x40000000L
//CP_GFX_HQD_HQ_CONTROL0
#define CP_GFX_HQD_HQ_CONTROL0__COMMAND__SHIFT                                                                0x0
#define CP_GFX_HQD_HQ_CONTROL0__COMMAND_MASK                                                                  0x0000000FL
//CP_GFX_MQD_CONTROL
#define CP_GFX_MQD_CONTROL__VMID__SHIFT                                                                       0x0
#define CP_GFX_MQD_CONTROL__PRIV_STATE__SHIFT                                                                 0x8
#define CP_GFX_MQD_CONTROL__PROCESSING_MQD__SHIFT                                                             0xc
#define CP_GFX_MQD_CONTROL__PROCESSING_MQD_EN__SHIFT                                                          0xd
#define CP_GFX_MQD_CONTROL__EXE_DISABLE__SHIFT                                                                0x17
#define CP_GFX_MQD_CONTROL__CACHE_POLICY__SHIFT                                                               0x18
#define CP_GFX_MQD_CONTROL__VMID_MASK                                                                         0x0000000FL
#define CP_GFX_MQD_CONTROL__PRIV_STATE_MASK                                                                   0x00000100L
#define CP_GFX_MQD_CONTROL__PROCESSING_MQD_MASK                                                               0x00001000L
#define CP_GFX_MQD_CONTROL__PROCESSING_MQD_EN_MASK                                                            0x00002000L
#define CP_GFX_MQD_CONTROL__EXE_DISABLE_MASK                                                                  0x00800000L
#define CP_GFX_MQD_CONTROL__CACHE_POLICY_MASK                                                                 0x03000000L
//CP_HQD_GFX_CONTROL
#define CP_HQD_GFX_CONTROL__MESSAGE__SHIFT                                                                    0x0
#define CP_HQD_GFX_CONTROL__MISC__SHIFT                                                                       0x4
#define CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT                                                          0xf
#define CP_HQD_GFX_CONTROL__MESSAGE_MASK                                                                      0x0000000FL
#define CP_HQD_GFX_CONTROL__MISC_MASK                                                                         0x00007FF0L
#define CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN_MASK                                                            0x00008000L
//CP_HQD_GFX_STATUS
#define CP_HQD_GFX_STATUS__STATUS__SHIFT                                                                      0x0
#define CP_HQD_GFX_STATUS__STATUS_MASK                                                                        0x0000FFFFL
//CP_GFX_HQD_CE_RPTR_WR
#define CP_GFX_HQD_CE_RPTR_WR__RB_RPTR_WR__SHIFT                                                              0x0
#define CP_GFX_HQD_CE_RPTR_WR__RB_RPTR_WR_MASK                                                                0x000FFFFFL
//CP_GFX_HQD_CE_BASE
#define CP_GFX_HQD_CE_BASE__RB_BASE__SHIFT                                                                    0x0
#define CP_GFX_HQD_CE_BASE__RB_BASE_MASK                                                                      0xFFFFFFFFL
//CP_GFX_HQD_CE_BASE_HI
#define CP_GFX_HQD_CE_BASE_HI__RB_BASE_HI__SHIFT                                                              0x0
#define CP_GFX_HQD_CE_BASE_HI__RB_BASE_HI_MASK                                                                0x000000FFL
//CP_GFX_HQD_CE_RPTR
#define CP_GFX_HQD_CE_RPTR__RB_RPTR__SHIFT                                                                    0x0
#define CP_GFX_HQD_CE_RPTR__RB_RPTR_MASK                                                                      0x000FFFFFL
//CP_GFX_HQD_CE_RPTR_ADDR
#define CP_GFX_HQD_CE_RPTR_ADDR__RB_RPTR_ADDR__SHIFT                                                          0x2
#define CP_GFX_HQD_CE_RPTR_ADDR__RB_RPTR_ADDR_MASK                                                            0xFFFFFFFCL
//CP_GFX_HQD_CE_RPTR_ADDR_HI
#define CP_GFX_HQD_CE_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT                                                    0x0
#define CP_GFX_HQD_CE_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK                                                      0x0000FFFFL
//CP_GFX_HQD_CE_WPTR_POLL_ADDR_LO
#define CP_GFX_HQD_CE_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO__SHIFT                                          0x2
#define CP_GFX_HQD_CE_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO_MASK                                            0xFFFFFFFCL
//CP_GFX_HQD_CE_WPTR_POLL_ADDR_HI
#define CP_GFX_HQD_CE_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI__SHIFT                                          0x0
#define CP_GFX_HQD_CE_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI_MASK                                            0x0000FFFFL
//CP_GFX_HQD_CE_OFFSET
#define CP_GFX_HQD_CE_OFFSET__RB_OFFSET__SHIFT                                                                0x0
#define CP_GFX_HQD_CE_OFFSET__DISABLE_RB_OFFSET__SHIFT                                                        0x1f
#define CP_GFX_HQD_CE_OFFSET__RB_OFFSET_MASK                                                                  0x000FFFFFL
#define CP_GFX_HQD_CE_OFFSET__DISABLE_RB_OFFSET_MASK                                                          0x80000000L
//CP_GFX_HQD_CE_CNTL
#define CP_GFX_HQD_CE_CNTL__RB_BUFSZ__SHIFT                                                                   0x0
#define CP_GFX_HQD_CE_CNTL__RB_BLKSZ__SHIFT                                                                   0x8
#define CP_GFX_HQD_CE_CNTL__RB_NON_PRIV__SHIFT                                                                0xf
#define CP_GFX_HQD_CE_CNTL__MIN_AVAILSZ__SHIFT                                                                0x14
#define CP_GFX_HQD_CE_CNTL__MIN_IB_AVAILSZ__SHIFT                                                             0x16
#define CP_GFX_HQD_CE_CNTL__CACHE_POLICY__SHIFT                                                               0x18
#define CP_GFX_HQD_CE_CNTL__RB_VOLATILE__SHIFT                                                                0x1a
#define CP_GFX_HQD_CE_CNTL__RB_NO_UPDATE__SHIFT                                                               0x1b
#define CP_GFX_HQD_CE_CNTL__RB_EXE__SHIFT                                                                     0x1c
#define CP_GFX_HQD_CE_CNTL__RB_RPTR_WR_ENA__SHIFT                                                             0x1f
#define CP_GFX_HQD_CE_CNTL__RB_BUFSZ_MASK                                                                     0x0000003FL
#define CP_GFX_HQD_CE_CNTL__RB_BLKSZ_MASK                                                                     0x00003F00L
#define CP_GFX_HQD_CE_CNTL__RB_NON_PRIV_MASK                                                                  0x00008000L
#define CP_GFX_HQD_CE_CNTL__MIN_AVAILSZ_MASK                                                                  0x00300000L
#define CP_GFX_HQD_CE_CNTL__MIN_IB_AVAILSZ_MASK                                                               0x00C00000L
#define CP_GFX_HQD_CE_CNTL__CACHE_POLICY_MASK                                                                 0x03000000L
#define CP_GFX_HQD_CE_CNTL__RB_VOLATILE_MASK                                                                  0x04000000L
#define CP_GFX_HQD_CE_CNTL__RB_NO_UPDATE_MASK                                                                 0x08000000L
#define CP_GFX_HQD_CE_CNTL__RB_EXE_MASK                                                                       0x10000000L
#define CP_GFX_HQD_CE_CNTL__RB_RPTR_WR_ENA_MASK                                                               0x80000000L
//CP_GFX_HQD_CE_CSMD_RPTR
#define CP_GFX_HQD_CE_CSMD_RPTR__RB_RPTR__SHIFT                                                               0x0
#define CP_GFX_HQD_CE_CSMD_RPTR__RB_RPTR_MASK                                                                 0x000FFFFFL
//CP_GFX_HQD_CE_WPTR
#define CP_GFX_HQD_CE_WPTR__RB_WPTR__SHIFT                                                                    0x0
#define CP_GFX_HQD_CE_WPTR__RB_WPTR_MASK                                                                      0xFFFFFFFFL
//CP_GFX_HQD_CE_WPTR_HI
#define CP_GFX_HQD_CE_WPTR_HI__RB_WPTR__SHIFT                                                                 0x0
#define CP_GFX_HQD_CE_WPTR_HI__RB_WPTR_MASK                                                                   0xFFFFFFFFL
//CP_CE_DOORBELL_CONTROL
#define CP_CE_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT                                                      0x1
#define CP_CE_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT                                                        0x2
#define CP_CE_DOORBELL_CONTROL__DOORBELL_EN__SHIFT                                                            0x1e
#define CP_CE_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT                                                           0x1f
#define CP_CE_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK                                                        0x00000002L
#define CP_CE_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK                                                          0x0FFFFFFCL
#define CP_CE_DOORBELL_CONTROL__DOORBELL_EN_MASK                                                              0x40000000L
#define CP_CE_DOORBELL_CONTROL__DOORBELL_HIT_MASK                                                             0x80000000L
//CP_DMA_WATCH0_ADDR_LO
#define CP_DMA_WATCH0_ADDR_LO__RSVD__SHIFT                                                                    0x0
#define CP_DMA_WATCH0_ADDR_LO__ADDR_LO__SHIFT                                                                 0x7
#define CP_DMA_WATCH0_ADDR_LO__RSVD_MASK                                                                      0x0000007FL
#define CP_DMA_WATCH0_ADDR_LO__ADDR_LO_MASK                                                                   0xFFFFFF80L
//CP_DMA_WATCH0_ADDR_HI
#define CP_DMA_WATCH0_ADDR_HI__ADDR_HI__SHIFT                                                                 0x0
#define CP_DMA_WATCH0_ADDR_HI__RSVD__SHIFT                                                                    0x10
#define CP_DMA_WATCH0_ADDR_HI__ADDR_HI_MASK                                                                   0x0000FFFFL
#define CP_DMA_WATCH0_ADDR_HI__RSVD_MASK                                                                      0xFFFF0000L
//CP_DMA_WATCH0_MASK
#define CP_DMA_WATCH0_MASK__RSVD__SHIFT                                                                       0x0
#define CP_DMA_WATCH0_MASK__MASK__SHIFT                                                                       0x7
#define CP_DMA_WATCH0_MASK__RSVD_MASK                                                                         0x0000007FL
#define CP_DMA_WATCH0_MASK__MASK_MASK                                                                         0xFFFFFF80L
//CP_DMA_WATCH0_CNTL
#define CP_DMA_WATCH0_CNTL__VMID__SHIFT                                                                       0x0
#define CP_DMA_WATCH0_CNTL__RSVD1__SHIFT                                                                      0x4
#define CP_DMA_WATCH0_CNTL__WATCH_READS__SHIFT                                                                0x8
#define CP_DMA_WATCH0_CNTL__WATCH_WRITES__SHIFT                                                               0x9
#define CP_DMA_WATCH0_CNTL__ANY_VMID__SHIFT                                                                   0xa
#define CP_DMA_WATCH0_CNTL__RSVD2__SHIFT                                                                      0xb
#define CP_DMA_WATCH0_CNTL__VMID_MASK                                                                         0x0000000FL
#define CP_DMA_WATCH0_CNTL__RSVD1_MASK                                                                        0x000000F0L
#define CP_DMA_WATCH0_CNTL__WATCH_READS_MASK                                                                  0x00000100L
#define CP_DMA_WATCH0_CNTL__WATCH_WRITES_MASK                                                                 0x00000200L
#define CP_DMA_WATCH0_CNTL__ANY_VMID_MASK                                                                     0x00000400L
#define CP_DMA_WATCH0_CNTL__RSVD2_MASK                                                                        0xFFFFF800L
//CP_DMA_WATCH1_ADDR_LO
#define CP_DMA_WATCH1_ADDR_LO__RSVD__SHIFT                                                                    0x0
#define CP_DMA_WATCH1_ADDR_LO__ADDR_LO__SHIFT                                                                 0x7
#define CP_DMA_WATCH1_ADDR_LO__RSVD_MASK                                                                      0x0000007FL
#define CP_DMA_WATCH1_ADDR_LO__ADDR_LO_MASK                                                                   0xFFFFFF80L
//CP_DMA_WATCH1_ADDR_HI
#define CP_DMA_WATCH1_ADDR_HI__ADDR_HI__SHIFT                                                                 0x0
#define CP_DMA_WATCH1_ADDR_HI__RSVD__SHIFT                                                                    0x10
#define CP_DMA_WATCH1_ADDR_HI__ADDR_HI_MASK                                                                   0x0000FFFFL
#define CP_DMA_WATCH1_ADDR_HI__RSVD_MASK                                                                      0xFFFF0000L
//CP_DMA_WATCH1_MASK
#define CP_DMA_WATCH1_MASK__RSVD__SHIFT                                                                       0x0
#define CP_DMA_WATCH1_MASK__MASK__SHIFT                                                                       0x7
#define CP_DMA_WATCH1_MASK__RSVD_MASK                                                                         0x0000007FL
#define CP_DMA_WATCH1_MASK__MASK_MASK                                                                         0xFFFFFF80L
//CP_DMA_WATCH1_CNTL
#define CP_DMA_WATCH1_CNTL__VMID__SHIFT                                                                       0x0
#define CP_DMA_WATCH1_CNTL__RSVD1__SHIFT                                                                      0x4
#define CP_DMA_WATCH1_CNTL__WATCH_READS__SHIFT                                                                0x8
#define CP_DMA_WATCH1_CNTL__WATCH_WRITES__SHIFT                                                               0x9
#define CP_DMA_WATCH1_CNTL__ANY_VMID__SHIFT                                                                   0xa
#define CP_DMA_WATCH1_CNTL__RSVD2__SHIFT                                                                      0xb
#define CP_DMA_WATCH1_CNTL__VMID_MASK                                                                         0x0000000FL
#define CP_DMA_WATCH1_CNTL__RSVD1_MASK                                                                        0x000000F0L
#define CP_DMA_WATCH1_CNTL__WATCH_READS_MASK                                                                  0x00000100L
#define CP_DMA_WATCH1_CNTL__WATCH_WRITES_MASK                                                                 0x00000200L
#define CP_DMA_WATCH1_CNTL__ANY_VMID_MASK                                                                     0x00000400L
#define CP_DMA_WATCH1_CNTL__RSVD2_MASK                                                                        0xFFFFF800L
//CP_DMA_WATCH2_ADDR_LO
#define CP_DMA_WATCH2_ADDR_LO__RSVD__SHIFT                                                                    0x0
#define CP_DMA_WATCH2_ADDR_LO__ADDR_LO__SHIFT                                                                 0x7
#define CP_DMA_WATCH2_ADDR_LO__RSVD_MASK                                                                      0x0000007FL
#define CP_DMA_WATCH2_ADDR_LO__ADDR_LO_MASK                                                                   0xFFFFFF80L
//CP_DMA_WATCH2_ADDR_HI
#define CP_DMA_WATCH2_ADDR_HI__ADDR_HI__SHIFT                                                                 0x0
#define CP_DMA_WATCH2_ADDR_HI__RSVD__SHIFT                                                                    0x10
#define CP_DMA_WATCH2_ADDR_HI__ADDR_HI_MASK                                                                   0x0000FFFFL
#define CP_DMA_WATCH2_ADDR_HI__RSVD_MASK                                                                      0xFFFF0000L
//CP_DMA_WATCH2_MASK
#define CP_DMA_WATCH2_MASK__RSVD__SHIFT                                                                       0x0
#define CP_DMA_WATCH2_MASK__MASK__SHIFT                                                                       0x7
#define CP_DMA_WATCH2_MASK__RSVD_MASK                                                                         0x0000007FL
#define CP_DMA_WATCH2_MASK__MASK_MASK                                                                         0xFFFFFF80L
//CP_DMA_WATCH2_CNTL
#define CP_DMA_WATCH2_CNTL__VMID__SHIFT                                                                       0x0
#define CP_DMA_WATCH2_CNTL__RSVD1__SHIFT                                                                      0x4
#define CP_DMA_WATCH2_CNTL__WATCH_READS__SHIFT                                                                0x8
#define CP_DMA_WATCH2_CNTL__WATCH_WRITES__SHIFT                                                               0x9
#define CP_DMA_WATCH2_CNTL__ANY_VMID__SHIFT                                                                   0xa
#define CP_DMA_WATCH2_CNTL__RSVD2__SHIFT                                                                      0xb
#define CP_DMA_WATCH2_CNTL__VMID_MASK                                                                         0x0000000FL
#define CP_DMA_WATCH2_CNTL__RSVD1_MASK                                                                        0x000000F0L
#define CP_DMA_WATCH2_CNTL__WATCH_READS_MASK                                                                  0x00000100L
#define CP_DMA_WATCH2_CNTL__WATCH_WRITES_MASK                                                                 0x00000200L
#define CP_DMA_WATCH2_CNTL__ANY_VMID_MASK                                                                     0x00000400L
#define CP_DMA_WATCH2_CNTL__RSVD2_MASK                                                                        0xFFFFF800L
//CP_DMA_WATCH3_ADDR_LO
#define CP_DMA_WATCH3_ADDR_LO__RSVD__SHIFT                                                                    0x0
#define CP_DMA_WATCH3_ADDR_LO__ADDR_LO__SHIFT                                                                 0x7
#define CP_DMA_WATCH3_ADDR_LO__RSVD_MASK                                                                      0x0000007FL
#define CP_DMA_WATCH3_ADDR_LO__ADDR_LO_MASK                                                                   0xFFFFFF80L
//CP_DMA_WATCH3_ADDR_HI
#define CP_DMA_WATCH3_ADDR_HI__ADDR_HI__SHIFT                                                                 0x0
#define CP_DMA_WATCH3_ADDR_HI__RSVD__SHIFT                                                                    0x10
#define CP_DMA_WATCH3_ADDR_HI__ADDR_HI_MASK                                                                   0x0000FFFFL
#define CP_DMA_WATCH3_ADDR_HI__RSVD_MASK                                                                      0xFFFF0000L
//CP_DMA_WATCH3_MASK
#define CP_DMA_WATCH3_MASK__RSVD__SHIFT                                                                       0x0
#define CP_DMA_WATCH3_MASK__MASK__SHIFT                                                                       0x7
#define CP_DMA_WATCH3_MASK__RSVD_MASK                                                                         0x0000007FL
#define CP_DMA_WATCH3_MASK__MASK_MASK                                                                         0xFFFFFF80L
//CP_DMA_WATCH3_CNTL
#define CP_DMA_WATCH3_CNTL__VMID__SHIFT                                                                       0x0
#define CP_DMA_WATCH3_CNTL__RSVD1__SHIFT                                                                      0x4
#define CP_DMA_WATCH3_CNTL__WATCH_READS__SHIFT                                                                0x8
#define CP_DMA_WATCH3_CNTL__WATCH_WRITES__SHIFT                                                               0x9
#define CP_DMA_WATCH3_CNTL__ANY_VMID__SHIFT                                                                   0xa
#define CP_DMA_WATCH3_CNTL__RSVD2__SHIFT                                                                      0xb
#define CP_DMA_WATCH3_CNTL__VMID_MASK                                                                         0x0000000FL
#define CP_DMA_WATCH3_CNTL__RSVD1_MASK                                                                        0x000000F0L
#define CP_DMA_WATCH3_CNTL__WATCH_READS_MASK                                                                  0x00000100L
#define CP_DMA_WATCH3_CNTL__WATCH_WRITES_MASK                                                                 0x00000200L
#define CP_DMA_WATCH3_CNTL__ANY_VMID_MASK                                                                     0x00000400L
#define CP_DMA_WATCH3_CNTL__RSVD2_MASK                                                                        0xFFFFF800L
//CP_DMA_WATCH_STAT_ADDR_LO
#define CP_DMA_WATCH_STAT_ADDR_LO__ADDR_LO__SHIFT                                                             0x2
#define CP_DMA_WATCH_STAT_ADDR_LO__ADDR_LO_MASK                                                               0xFFFFFFFCL
//CP_DMA_WATCH_STAT_ADDR_HI
#define CP_DMA_WATCH_STAT_ADDR_HI__ADDR_HI__SHIFT                                                             0x0
#define CP_DMA_WATCH_STAT_ADDR_HI__ADDR_HI_MASK                                                               0x0000FFFFL
//CP_DMA_WATCH_STAT
#define CP_DMA_WATCH_STAT__VMID__SHIFT                                                                        0x0
#define CP_DMA_WATCH_STAT__QUEUE_ID__SHIFT                                                                    0x4
#define CP_DMA_WATCH_STAT__CLIENT_ID__SHIFT                                                                   0x8
#define CP_DMA_WATCH_STAT__PIPE__SHIFT                                                                        0xc
#define CP_DMA_WATCH_STAT__WATCH_ID__SHIFT                                                                    0x10
#define CP_DMA_WATCH_STAT__RD_WR__SHIFT                                                                       0x14
#define CP_DMA_WATCH_STAT__TRAP_FLAG__SHIFT                                                                   0x1f
#define CP_DMA_WATCH_STAT__VMID_MASK                                                                          0x0000000FL
#define CP_DMA_WATCH_STAT__QUEUE_ID_MASK                                                                      0x00000070L
#define CP_DMA_WATCH_STAT__CLIENT_ID_MASK                                                                     0x00000700L
#define CP_DMA_WATCH_STAT__PIPE_MASK                                                                          0x00003000L
#define CP_DMA_WATCH_STAT__WATCH_ID_MASK                                                                      0x00030000L
#define CP_DMA_WATCH_STAT__RD_WR_MASK                                                                         0x00100000L
#define CP_DMA_WATCH_STAT__TRAP_FLAG_MASK                                                                     0x80000000L
//CP_PFP_JT_STAT
#define CP_PFP_JT_STAT__JT_LOADED__SHIFT                                                                      0x0
#define CP_PFP_JT_STAT__WR_MASK__SHIFT                                                                        0x10
#define CP_PFP_JT_STAT__JT_LOADED_MASK                                                                        0x00000003L
#define CP_PFP_JT_STAT__WR_MASK_MASK                                                                          0x00030000L
//CP_CE_JT_STAT
#define CP_CE_JT_STAT__JT_LOADED__SHIFT                                                                       0x0
#define CP_CE_JT_STAT__WR_MASK__SHIFT                                                                         0x10
#define CP_CE_JT_STAT__JT_LOADED_MASK                                                                         0x00000003L
#define CP_CE_JT_STAT__WR_MASK_MASK                                                                           0x00030000L
//CP_MEC_JT_STAT
#define CP_MEC_JT_STAT__JT_LOADED__SHIFT                                                                      0x0
#define CP_MEC_JT_STAT__WR_MASK__SHIFT                                                                        0x10
#define CP_MEC_JT_STAT__JT_LOADED_MASK                                                                        0x000000FFL
#define CP_MEC_JT_STAT__WR_MASK_MASK                                                                          0x00FF0000L
//CP_FETCHER_SOURCE
#define CP_FETCHER_SOURCE__ME_SRC__SHIFT                                                                      0x0
#define CP_FETCHER_SOURCE__ME_SRC_MASK                                                                        0x00000001L
//CP_CE_CS_PARTITION_INDEX
#define CP_CE_CS_PARTITION_INDEX__CS1_INDEX__SHIFT                                                            0x0
#define CP_CE_CS_PARTITION_INDEX__CS1_INDEX_MASK                                                              0x0001FFFFL
//CP_RB_DOORBELL_CLEAR
#define CP_RB_DOORBELL_CLEAR__MAPPED_QUEUE__SHIFT                                                             0x0
#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_EN_CLEAR__SHIFT                                             0x8
#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_HIT_CLEAR__SHIFT                                            0x9
#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR__SHIFT                                                 0xa
#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_HIT_CLEAR__SHIFT                                                0xb
#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_EN_CLEAR__SHIFT                                                 0xc
#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_HIT_CLEAR__SHIFT                                                0xd
#define CP_RB_DOORBELL_CLEAR__MAPPED_QUEUE_MASK                                                               0x00000007L
#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_EN_CLEAR_MASK                                               0x00000100L
#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_HIT_CLEAR_MASK                                              0x00000200L
#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR_MASK                                                   0x00000400L
#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_HIT_CLEAR_MASK                                                  0x00000800L
#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_EN_CLEAR_MASK                                                   0x00001000L
#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_HIT_CLEAR_MASK                                                  0x00002000L
//CP_RB0_ACTIVE
#define CP_RB0_ACTIVE__ACTIVE__SHIFT                                                                          0x0
#define CP_RB0_ACTIVE__ACTIVE_MASK                                                                            0x00000001L
//CP_RB_ACTIVE
#define CP_RB_ACTIVE__ACTIVE__SHIFT                                                                           0x0
#define CP_RB_ACTIVE__ACTIVE_MASK                                                                             0x00000001L
//CP_RB1_ACTIVE
#define CP_RB1_ACTIVE__ACTIVE__SHIFT                                                                          0x0
#define CP_RB1_ACTIVE__ACTIVE_MASK                                                                            0x00000001L
//CP_RB_STATUS
#define CP_RB_STATUS__DOORBELL_UPDATED__SHIFT                                                                 0x0
#define CP_RB_STATUS__DOORBELL_ENABLE__SHIFT                                                                  0x1
#define CP_RB_STATUS__DOORBELL_UPDATED_MASK                                                                   0x00000001L
#define CP_RB_STATUS__DOORBELL_ENABLE_MASK                                                                    0x00000002L
//CPG_RCIU_CAM_INDEX
#define CPG_RCIU_CAM_INDEX__INDEX__SHIFT                                                                      0x0
#define CPG_RCIU_CAM_INDEX__INDEX_MASK                                                                        0x0000001FL
//CPG_RCIU_CAM_DATA
#define CPG_RCIU_CAM_DATA__DATA__SHIFT                                                                        0x0
#define CPG_RCIU_CAM_DATA__DATA_MASK                                                                          0xFFFFFFFFL
//CPG_RCIU_CAM_DATA_PHASE0
#define CPG_RCIU_CAM_DATA_PHASE0__ADDR__SHIFT                                                                 0x0
#define CPG_RCIU_CAM_DATA_PHASE0__PIPE0_EN__SHIFT                                                             0x18
#define CPG_RCIU_CAM_DATA_PHASE0__PIPE1_EN__SHIFT                                                             0x19
#define CPG_RCIU_CAM_DATA_PHASE0__SKIP_WR__SHIFT                                                              0x1f
#define CPG_RCIU_CAM_DATA_PHASE0__ADDR_MASK                                                                   0x0003FFFFL
#define CPG_RCIU_CAM_DATA_PHASE0__PIPE0_EN_MASK                                                               0x01000000L
#define CPG_RCIU_CAM_DATA_PHASE0__PIPE1_EN_MASK                                                               0x02000000L
#define CPG_RCIU_CAM_DATA_PHASE0__SKIP_WR_MASK                                                                0x80000000L
//CPG_RCIU_CAM_DATA_PHASE1
#define CPG_RCIU_CAM_DATA_PHASE1__MASK__SHIFT                                                                 0x0
#define CPG_RCIU_CAM_DATA_PHASE1__MASK_MASK                                                                   0xFFFFFFFFL
//CPG_RCIU_CAM_DATA_PHASE2
#define CPG_RCIU_CAM_DATA_PHASE2__VALUE__SHIFT                                                                0x0
#define CPG_RCIU_CAM_DATA_PHASE2__VALUE_MASK                                                                  0xFFFFFFFFL
//CP_GPU_TIMESTAMP_OFFSET_LO
#define CP_GPU_TIMESTAMP_OFFSET_LO__OFFSET_LO__SHIFT                                                          0x0
#define CP_GPU_TIMESTAMP_OFFSET_LO__OFFSET_LO_MASK                                                            0xFFFFFFFFL
//CP_GPU_TIMESTAMP_OFFSET_HI
#define CP_GPU_TIMESTAMP_OFFSET_HI__OFFSET_HI__SHIFT                                                          0x0
#define CP_GPU_TIMESTAMP_OFFSET_HI__OFFSET_HI_MASK                                                            0xFFFFFFFFL
//CPF_GCR_CNTL
#define CPF_GCR_CNTL__GCR_GL_CMD__SHIFT                                                                       0x0
#define CPF_GCR_CNTL__GCR_GL_CMD_MASK                                                                         0x0007FFFFL
//CPG_UTCL1_STATUS
#define CPG_UTCL1_STATUS__FAULT_DETECTED__SHIFT                                                               0x0
#define CPG_UTCL1_STATUS__RETRY_DETECTED__SHIFT                                                               0x1
#define CPG_UTCL1_STATUS__PRT_DETECTED__SHIFT                                                                 0x2
#define CPG_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT                                                                0x8
#define CPG_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT                                                                0x10
#define CPG_UTCL1_STATUS__PRT_UTCL1ID__SHIFT                                                                  0x18
#define CPG_UTCL1_STATUS__FAULT_DETECTED_MASK                                                                 0x00000001L
#define CPG_UTCL1_STATUS__RETRY_DETECTED_MASK                                                                 0x00000002L
#define CPG_UTCL1_STATUS__PRT_DETECTED_MASK                                                                   0x00000004L
#define CPG_UTCL1_STATUS__FAULT_UTCL1ID_MASK                                                                  0x00003F00L
#define CPG_UTCL1_STATUS__RETRY_UTCL1ID_MASK                                                                  0x003F0000L
#define CPG_UTCL1_STATUS__PRT_UTCL1ID_MASK                                                                    0x3F000000L
//CPC_UTCL1_STATUS
#define CPC_UTCL1_STATUS__FAULT_DETECTED__SHIFT                                                               0x0
#define CPC_UTCL1_STATUS__RETRY_DETECTED__SHIFT                                                               0x1
#define CPC_UTCL1_STATUS__PRT_DETECTED__SHIFT                                                                 0x2
#define CPC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT                                                                0x8
#define CPC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT                                                                0x10
#define CPC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT                                                                  0x18
#define CPC_UTCL1_STATUS__FAULT_DETECTED_MASK                                                                 0x00000001L
#define CPC_UTCL1_STATUS__RETRY_DETECTED_MASK                                                                 0x00000002L
#define CPC_UTCL1_STATUS__PRT_DETECTED_MASK                                                                   0x00000004L
#define CPC_UTCL1_STATUS__FAULT_UTCL1ID_MASK                                                                  0x00003F00L
#define CPC_UTCL1_STATUS__RETRY_UTCL1ID_MASK                                                                  0x003F0000L
#define CPC_UTCL1_STATUS__PRT_UTCL1ID_MASK                                                                    0x3F000000L
//CPF_UTCL1_STATUS
#define CPF_UTCL1_STATUS__FAULT_DETECTED__SHIFT                                                               0x0
#define CPF_UTCL1_STATUS__RETRY_DETECTED__SHIFT                                                               0x1
#define CPF_UTCL1_STATUS__PRT_DETECTED__SHIFT                                                                 0x2
#define CPF_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT                                                                0x8
#define CPF_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT                                                                0x10
#define CPF_UTCL1_STATUS__PRT_UTCL1ID__SHIFT                                                                  0x18
#define CPF_UTCL1_STATUS__FAULT_DETECTED_MASK                                                                 0x00000001L
#define CPF_UTCL1_STATUS__RETRY_DETECTED_MASK                                                                 0x00000002L
#define CPF_UTCL1_STATUS__PRT_DETECTED_MASK                                                                   0x00000004L
#define CPF_UTCL1_STATUS__FAULT_UTCL1ID_MASK                                                                  0x00003F00L
#define CPF_UTCL1_STATUS__RETRY_UTCL1ID_MASK                                                                  0x003F0000L
#define CPF_UTCL1_STATUS__PRT_UTCL1ID_MASK                                                                    0x3F000000L
//CP_SD_CNTL
#define CP_SD_CNTL__CPF_EN__SHIFT                                                                             0x0
#define CP_SD_CNTL__CPG_EN__SHIFT                                                                             0x1
#define CP_SD_CNTL__CPC_EN__SHIFT                                                                             0x2
#define CP_SD_CNTL__RLC_EN__SHIFT                                                                             0x3
#define CP_SD_CNTL__SPI_EN__SHIFT                                                                             0x4
#define CP_SD_CNTL__GE_EN__SHIFT                                                                              0x5
#define CP_SD_CNTL__UTCL1_EN__SHIFT                                                                           0x6
#define CP_SD_CNTL__EA_EN__SHIFT                                                                              0x9
#define CP_SD_CNTL__SDMA_EN__SHIFT                                                                            0xa
#define CP_SD_CNTL__SD_VMIDVEC_OVERRIDE__SHIFT                                                                0x1f
#define CP_SD_CNTL__CPF_EN_MASK                                                                               0x00000001L
#define CP_SD_CNTL__CPG_EN_MASK                                                                               0x00000002L
#define CP_SD_CNTL__CPC_EN_MASK                                                                               0x00000004L
#define CP_SD_CNTL__RLC_EN_MASK                                                                               0x00000008L
#define CP_SD_CNTL__SPI_EN_MASK                                                                               0x00000010L
#define CP_SD_CNTL__GE_EN_MASK                                                                                0x00000020L
#define CP_SD_CNTL__UTCL1_EN_MASK                                                                             0x00000040L
#define CP_SD_CNTL__EA_EN_MASK                                                                                0x00000200L
#define CP_SD_CNTL__SDMA_EN_MASK                                                                              0x00000400L
#define CP_SD_CNTL__SD_VMIDVEC_OVERRIDE_MASK                                                                  0x80000000L
//CP_SOFT_RESET_CNTL
#define CP_SOFT_RESET_CNTL__CMP_ONLY_SOFT_RESET__SHIFT                                                        0x0
#define CP_SOFT_RESET_CNTL__GFX_ONLY_SOFT_RESET__SHIFT                                                        0x1
#define CP_SOFT_RESET_CNTL__CMP_HQD_REG_RESET__SHIFT                                                          0x2
#define CP_SOFT_RESET_CNTL__CMP_INTR_REG_RESET__SHIFT                                                         0x3
#define CP_SOFT_RESET_CNTL__CMP_HQD_QUEUE_DOORBELL_RESET__SHIFT                                               0x4
#define CP_SOFT_RESET_CNTL__GFX_RB_DOORBELL_RESET__SHIFT                                                      0x5
#define CP_SOFT_RESET_CNTL__GFX_INTR_REG_RESET__SHIFT                                                         0x6
#define CP_SOFT_RESET_CNTL__CMP_ONLY_SOFT_RESET_MASK                                                          0x00000001L
#define CP_SOFT_RESET_CNTL__GFX_ONLY_SOFT_RESET_MASK                                                          0x00000002L
#define CP_SOFT_RESET_CNTL__CMP_HQD_REG_RESET_MASK                                                            0x00000004L
#define CP_SOFT_RESET_CNTL__CMP_INTR_REG_RESET_MASK                                                           0x00000008L
#define CP_SOFT_RESET_CNTL__CMP_HQD_QUEUE_DOORBELL_RESET_MASK                                                 0x00000010L
#define CP_SOFT_RESET_CNTL__GFX_RB_DOORBELL_RESET_MASK                                                        0x00000020L
#define CP_SOFT_RESET_CNTL__GFX_INTR_REG_RESET_MASK                                                           0x00000040L
//CP_CPC_GFX_CNTL
#define CP_CPC_GFX_CNTL__QUEUEID__SHIFT                                                                       0x0
#define CP_CPC_GFX_CNTL__PIPEID__SHIFT                                                                        0x3
#define CP_CPC_GFX_CNTL__MEID__SHIFT                                                                          0x5
#define CP_CPC_GFX_CNTL__VALID__SHIFT                                                                         0x7
#define CP_CPC_GFX_CNTL__QUEUEID_MASK                                                                         0x00000007L
#define CP_CPC_GFX_CNTL__PIPEID_MASK                                                                          0x00000018L
#define CP_CPC_GFX_CNTL__MEID_MASK                                                                            0x00000060L
#define CP_CPC_GFX_CNTL__VALID_MASK                                                                           0x00000080L


// addressBlock: gc_spipdec
//SPI_ARB_PRIORITY
#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0__SHIFT                                                               0x0
#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1__SHIFT                                                               0x3
#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2__SHIFT                                                               0x6
#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3__SHIFT                                                               0x9
#define SPI_ARB_PRIORITY__TS0_DUR_MULT__SHIFT                                                                 0xc
#define SPI_ARB_PRIORITY__TS1_DUR_MULT__SHIFT                                                                 0xe
#define SPI_ARB_PRIORITY__TS2_DUR_MULT__SHIFT                                                                 0x10
#define SPI_ARB_PRIORITY__TS3_DUR_MULT__SHIFT                                                                 0x12
#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0_MASK                                                                 0x00000007L
#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1_MASK                                                                 0x00000038L
#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2_MASK                                                                 0x000001C0L
#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3_MASK                                                                 0x00000E00L
#define SPI_ARB_PRIORITY__TS0_DUR_MULT_MASK                                                                   0x00003000L
#define SPI_ARB_PRIORITY__TS1_DUR_MULT_MASK                                                                   0x0000C000L
#define SPI_ARB_PRIORITY__TS2_DUR_MULT_MASK                                                                   0x00030000L
#define SPI_ARB_PRIORITY__TS3_DUR_MULT_MASK                                                                   0x000C0000L
//SPI_ARB_CYCLES_0
#define SPI_ARB_CYCLES_0__TS0_DURATION__SHIFT                                                                 0x0
#define SPI_ARB_CYCLES_0__TS1_DURATION__SHIFT                                                                 0x10
#define SPI_ARB_CYCLES_0__TS0_DURATION_MASK                                                                   0x0000FFFFL
#define SPI_ARB_CYCLES_0__TS1_DURATION_MASK                                                                   0xFFFF0000L
//SPI_ARB_CYCLES_1
#define SPI_ARB_CYCLES_1__TS2_DURATION__SHIFT                                                                 0x0
#define SPI_ARB_CYCLES_1__TS3_DURATION__SHIFT                                                                 0x10
#define SPI_ARB_CYCLES_1__TS2_DURATION_MASK                                                                   0x0000FFFFL
#define SPI_ARB_CYCLES_1__TS3_DURATION_MASK                                                                   0xFFFF0000L
//SPI_WCL_PIPE_PERCENT_GFX
#define SPI_WCL_PIPE_PERCENT_GFX__VALUE__SHIFT                                                                0x0
#define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE__SHIFT                                                         0xc
#define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE__SHIFT                                                         0x16
#define SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK                                                                  0x0000007FL
#define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE_MASK                                                           0x0001F000L
#define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE_MASK                                                           0x07C00000L
//SPI_WCL_PIPE_PERCENT_HP3D
#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE__SHIFT                                                               0x0
#define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE__SHIFT                                                        0xc
#define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE__SHIFT                                                        0x16
#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK                                                                 0x0000007FL
#define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE_MASK                                                          0x0001F000L
#define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE_MASK                                                          0x07C00000L
//SPI_WCL_PIPE_PERCENT_CS0
#define SPI_WCL_PIPE_PERCENT_CS0__VALUE__SHIFT                                                                0x0
#define SPI_WCL_PIPE_PERCENT_CS0__VALUE_MASK                                                                  0x7FL
//SPI_WCL_PIPE_PERCENT_CS1
#define SPI_WCL_PIPE_PERCENT_CS1__VALUE__SHIFT                                                                0x0
#define SPI_WCL_PIPE_PERCENT_CS1__VALUE_MASK                                                                  0x7FL
//SPI_WCL_PIPE_PERCENT_CS2
#define SPI_WCL_PIPE_PERCENT_CS2__VALUE__SHIFT                                                                0x0
#define SPI_WCL_PIPE_PERCENT_CS2__VALUE_MASK                                                                  0x7FL
//SPI_WCL_PIPE_PERCENT_CS3
#define SPI_WCL_PIPE_PERCENT_CS3__VALUE__SHIFT                                                                0x0
#define SPI_WCL_PIPE_PERCENT_CS3__VALUE_MASK                                                                  0x7FL
//SPI_GDBG_WAVE_CNTL
#define SPI_GDBG_WAVE_CNTL__STALL_RA__SHIFT                                                                   0x0
#define SPI_GDBG_WAVE_CNTL__STALL_VMID__SHIFT                                                                 0x1
#define SPI_GDBG_WAVE_CNTL__STALL_RA_MASK                                                                     0x00000001L
#define SPI_GDBG_WAVE_CNTL__STALL_VMID_MASK                                                                   0x0001FFFEL
//SPI_GDBG_TRAP_MASK
#define SPI_GDBG_TRAP_MASK__EXCP_EN__SHIFT                                                                    0x0
#define SPI_GDBG_TRAP_MASK__REPLACE__SHIFT                                                                    0x9
#define SPI_GDBG_TRAP_MASK__EXCP_EN_MASK                                                                      0x01FFL
#define SPI_GDBG_TRAP_MASK__REPLACE_MASK                                                                      0x0200L
//SPI_GDBG_WAVE_CNTL2
#define SPI_GDBG_WAVE_CNTL2__VMID_MASK__SHIFT                                                                 0x0
#define SPI_GDBG_WAVE_CNTL2__MODE__SHIFT                                                                      0x10
#define SPI_GDBG_WAVE_CNTL2__VMID_MASK_MASK                                                                   0x0000FFFFL
#define SPI_GDBG_WAVE_CNTL2__MODE_MASK                                                                        0x00030000L
//SPI_COMPUTE_QUEUE_RESET
#define SPI_COMPUTE_QUEUE_RESET__RESET__SHIFT                                                                 0x0
#define SPI_COMPUTE_QUEUE_RESET__RESET_MASK                                                                   0x01L
//SPI_RESOURCE_RESERVE_CU_0
#define SPI_RESOURCE_RESERVE_CU_0__VGPR__SHIFT                                                                0x0
#define SPI_RESOURCE_RESERVE_CU_0__SGPR__SHIFT                                                                0x4
#define SPI_RESOURCE_RESERVE_CU_0__LDS__SHIFT                                                                 0x8
#define SPI_RESOURCE_RESERVE_CU_0__WAVES__SHIFT                                                               0xc
#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS__SHIFT                                                            0xf
#define SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK                                                                  0x0000000FL
#define SPI_RESOURCE_RESERVE_CU_0__SGPR_MASK                                                                  0x000000F0L
#define SPI_RESOURCE_RESERVE_CU_0__LDS_MASK                                                                   0x00000F00L
#define SPI_RESOURCE_RESERVE_CU_0__WAVES_MASK                                                                 0x00007000L
#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS_MASK                                                              0x00078000L
//SPI_RESOURCE_RESERVE_CU_1
#define SPI_RESOURCE_RESERVE_CU_1__VGPR__SHIFT                                                                0x0
#define SPI_RESOURCE_RESERVE_CU_1__SGPR__SHIFT                                                                0x4
#define SPI_RESOURCE_RESERVE_CU_1__LDS__SHIFT                                                                 0x8
#define SPI_RESOURCE_RESERVE_CU_1__WAVES__SHIFT                                                               0xc
#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS__SHIFT                                                            0xf
#define SPI_RESOURCE_RESERVE_CU_1__VGPR_MASK                                                                  0x0000000FL
#define SPI_RESOURCE_RESERVE_CU_1__SGPR_MASK                                                                  0x000000F0L
#define SPI_RESOURCE_RESERVE_CU_1__LDS_MASK                                                                   0x00000F00L
#define SPI_RESOURCE_RESERVE_CU_1__WAVES_MASK                                                                 0x00007000L
#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS_MASK                                                              0x00078000L
//SPI_RESOURCE_RESERVE_CU_2
#define SPI_RESOURCE_RESERVE_CU_2__VGPR__SHIFT                                                                0x0
#define SPI_RESOURCE_RESERVE_CU_2__SGPR__SHIFT                                                                0x4
#define SPI_RESOURCE_RESERVE_CU_2__LDS__SHIFT                                                                 0x8
#define SPI_RESOURCE_RESERVE_CU_2__WAVES__SHIFT                                                               0xc
#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS__SHIFT                                                            0xf
#define SPI_RESOURCE_RESERVE_CU_2__VGPR_MASK                                                                  0x0000000FL
#define SPI_RESOURCE_RESERVE_CU_2__SGPR_MASK                                                                  0x000000F0L
#define SPI_RESOURCE_RESERVE_CU_2__LDS_MASK                                                                   0x00000F00L
#define SPI_RESOURCE_RESERVE_CU_2__WAVES_MASK                                                                 0x00007000L
#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS_MASK                                                              0x00078000L
//SPI_RESOURCE_RESERVE_CU_3
#define SPI_RESOURCE_RESERVE_CU_3__VGPR__SHIFT                                                                0x0
#define SPI_RESOURCE_RESERVE_CU_3__SGPR__SHIFT                                                                0x4
#define SPI_RESOURCE_RESERVE_CU_3__LDS__SHIFT                                                                 0x8
#define SPI_RESOURCE_RESERVE_CU_3__WAVES__SHIFT                                                               0xc
#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS__SHIFT                                                            0xf
#define SPI_RESOURCE_RESERVE_CU_3__VGPR_MASK                                                                  0x0000000FL
#define SPI_RESOURCE_RESERVE_CU_3__SGPR_MASK                                                                  0x000000F0L
#define SPI_RESOURCE_RESERVE_CU_3__LDS_MASK                                                                   0x00000F00L
#define SPI_RESOURCE_RESERVE_CU_3__WAVES_MASK                                                                 0x00007000L
#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS_MASK                                                              0x00078000L
//SPI_RESOURCE_RESERVE_CU_4
#define SPI_RESOURCE_RESERVE_CU_4__VGPR__SHIFT                                                                0x0
#define SPI_RESOURCE_RESERVE_CU_4__SGPR__SHIFT                                                                0x4
#define SPI_RESOURCE_RESERVE_CU_4__LDS__SHIFT                                                                 0x8
#define SPI_RESOURCE_RESERVE_CU_4__WAVES__SHIFT                                                               0xc
#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS__SHIFT                                                            0xf
#define SPI_RESOURCE_RESERVE_CU_4__VGPR_MASK                                                                  0x0000000FL
#define SPI_RESOURCE_RESERVE_CU_4__SGPR_MASK                                                                  0x000000F0L
#define SPI_RESOURCE_RESERVE_CU_4__LDS_MASK                                                                   0x00000F00L
#define SPI_RESOURCE_RESERVE_CU_4__WAVES_MASK                                                                 0x00007000L
#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS_MASK                                                              0x00078000L
//SPI_RESOURCE_RESERVE_CU_5
#define SPI_RESOURCE_RESERVE_CU_5__VGPR__SHIFT                                                                0x0
#define SPI_RESOURCE_RESERVE_CU_5__SGPR__SHIFT                                                                0x4
#define SPI_RESOURCE_RESERVE_CU_5__LDS__SHIFT                                                                 0x8
#define SPI_RESOURCE_RESERVE_CU_5__WAVES__SHIFT                                                               0xc
#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS__SHIFT                                                            0xf
#define SPI_RESOURCE_RESERVE_CU_5__VGPR_MASK                                                                  0x0000000FL
#define SPI_RESOURCE_RESERVE_CU_5__SGPR_MASK                                                                  0x000000F0L
#define SPI_RESOURCE_RESERVE_CU_5__LDS_MASK                                                                   0x00000F00L
#define SPI_RESOURCE_RESERVE_CU_5__WAVES_MASK                                                                 0x00007000L
#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS_MASK                                                              0x00078000L
//SPI_RESOURCE_RESERVE_CU_6
#define SPI_RESOURCE_RESERVE_CU_6__VGPR__SHIFT                                                                0x0
#define SPI_RESOURCE_RESERVE_CU_6__SGPR__SHIFT                                                                0x4
#define SPI_RESOURCE_RESERVE_CU_6__LDS__SHIFT                                                                 0x8
#define SPI_RESOURCE_RESERVE_CU_6__WAVES__SHIFT                                                               0xc
#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS__SHIFT                                                            0xf
#define SPI_RESOURCE_RESERVE_CU_6__VGPR_MASK                                                                  0x0000000FL
#define SPI_RESOURCE_RESERVE_CU_6__SGPR_MASK                                                                  0x000000F0L
#define SPI_RESOURCE_RESERVE_CU_6__LDS_MASK                                                                   0x00000F00L
#define SPI_RESOURCE_RESERVE_CU_6__WAVES_MASK                                                                 0x00007000L
#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS_MASK                                                              0x00078000L
//SPI_RESOURCE_RESERVE_CU_7
#define SPI_RESOURCE_RESERVE_CU_7__VGPR__SHIFT                                                                0x0
#define SPI_RESOURCE_RESERVE_CU_7__SGPR__SHIFT                                                                0x4
#define SPI_RESOURCE_RESERVE_CU_7__LDS__SHIFT                                                                 0x8
#define SPI_RESOURCE_RESERVE_CU_7__WAVES__SHIFT                                                               0xc
#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS__SHIFT                                                            0xf
#define SPI_RESOURCE_RESERVE_CU_7__VGPR_MASK                                                                  0x0000000FL
#define SPI_RESOURCE_RESERVE_CU_7__SGPR_MASK                                                                  0x000000F0L
#define SPI_RESOURCE_RESERVE_CU_7__LDS_MASK                                                                   0x00000F00L
#define SPI_RESOURCE_RESERVE_CU_7__WAVES_MASK                                                                 0x00007000L
#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS_MASK                                                              0x00078000L
//SPI_RESOURCE_RESERVE_CU_8
#define SPI_RESOURCE_RESERVE_CU_8__VGPR__SHIFT                                                                0x0
#define SPI_RESOURCE_RESERVE_CU_8__SGPR__SHIFT                                                                0x4
#define SPI_RESOURCE_RESERVE_CU_8__LDS__SHIFT                                                                 0x8
#define SPI_RESOURCE_RESERVE_CU_8__WAVES__SHIFT                                                               0xc
#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS__SHIFT                                                            0xf
#define SPI_RESOURCE_RESERVE_CU_8__VGPR_MASK                                                                  0x0000000FL
#define SPI_RESOURCE_RESERVE_CU_8__SGPR_MASK                                                                  0x000000F0L
#define SPI_RESOURCE_RESERVE_CU_8__LDS_MASK                                                                   0x00000F00L
#define SPI_RESOURCE_RESERVE_CU_8__WAVES_MASK                                                                 0x00007000L
#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS_MASK                                                              0x00078000L
//SPI_RESOURCE_RESERVE_CU_9
#define SPI_RESOURCE_RESERVE_CU_9__VGPR__SHIFT                                                                0x0
#define SPI_RESOURCE_RESERVE_CU_9__SGPR__SHIFT                                                                0x4
#define SPI_RESOURCE_RESERVE_CU_9__LDS__SHIFT                                                                 0x8
#define SPI_RESOURCE_RESERVE_CU_9__WAVES__SHIFT                                                               0xc
#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS__SHIFT                                                            0xf
#define SPI_RESOURCE_RESERVE_CU_9__VGPR_MASK                                                                  0x0000000FL
#define SPI_RESOURCE_RESERVE_CU_9__SGPR_MASK                                                                  0x000000F0L
#define SPI_RESOURCE_RESERVE_CU_9__LDS_MASK                                                                   0x00000F00L
#define SPI_RESOURCE_RESERVE_CU_9__WAVES_MASK                                                                 0x00007000L
#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS_MASK                                                              0x00078000L
//SPI_RESOURCE_RESERVE_EN_CU_0
#define SPI_RESOURCE_RESERVE_EN_CU_0__EN__SHIFT                                                               0x0
#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK__SHIFT                                                        0x1
#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK__SHIFT                                                       0x10
#define SPI_RESOURCE_RESERVE_EN_CU_0__EN_MASK                                                                 0x00000001L
#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK_MASK                                                          0x0000FFFEL
#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK_MASK                                                         0x00FF0000L
//SPI_RESOURCE_RESERVE_EN_CU_1
#define SPI_RESOURCE_RESERVE_EN_CU_1__EN__SHIFT                                                               0x0
#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK__SHIFT                                                        0x1
#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK__SHIFT                                                       0x10
#define SPI_RESOURCE_RESERVE_EN_CU_1__EN_MASK                                                                 0x00000001L
#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK_MASK                                                          0x0000FFFEL
#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK_MASK                                                         0x00FF0000L
//SPI_RESOURCE_RESERVE_EN_CU_2
#define SPI_RESOURCE_RESERVE_EN_CU_2__EN__SHIFT                                                               0x0
#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK__SHIFT                                                        0x1
#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK__SHIFT                                                       0x10
#define SPI_RESOURCE_RESERVE_EN_CU_2__EN_MASK                                                                 0x00000001L
#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK_MASK                                                          0x0000FFFEL
#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK_MASK                                                         0x00FF0000L
//SPI_RESOURCE_RESERVE_EN_CU_3
#define SPI_RESOURCE_RESERVE_EN_CU_3__EN__SHIFT                                                               0x0
#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK__SHIFT                                                        0x1
#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK__SHIFT                                                       0x10
#define SPI_RESOURCE_RESERVE_EN_CU_3__EN_MASK                                                                 0x00000001L
#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK_MASK                                                          0x0000FFFEL
#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK_MASK                                                         0x00FF0000L
//SPI_RESOURCE_RESERVE_EN_CU_4
#define SPI_RESOURCE_RESERVE_EN_CU_4__EN__SHIFT                                                               0x0
#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK__SHIFT                                                        0x1
#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK__SHIFT                                                       0x10
#define SPI_RESOURCE_RESERVE_EN_CU_4__EN_MASK                                                                 0x00000001L
#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK_MASK                                                          0x0000FFFEL
#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK_MASK                                                         0x00FF0000L
//SPI_RESOURCE_RESERVE_EN_CU_5
#define SPI_RESOURCE_RESERVE_EN_CU_5__EN__SHIFT                                                               0x0
#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK__SHIFT                                                        0x1
#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK__SHIFT                                                       0x10
#define SPI_RESOURCE_RESERVE_EN_CU_5__EN_MASK                                                                 0x00000001L
#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK_MASK                                                          0x0000FFFEL
#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK_MASK                                                         0x00FF0000L
//SPI_RESOURCE_RESERVE_EN_CU_6
#define SPI_RESOURCE_RESERVE_EN_CU_6__EN__SHIFT                                                               0x0
#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK__SHIFT                                                        0x1
#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK__SHIFT                                                       0x10
#define SPI_RESOURCE_RESERVE_EN_CU_6__EN_MASK                                                                 0x00000001L
#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK_MASK                                                          0x0000FFFEL
#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK_MASK                                                         0x00FF0000L
//SPI_RESOURCE_RESERVE_EN_CU_7
#define SPI_RESOURCE_RESERVE_EN_CU_7__EN__SHIFT                                                               0x0
#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK__SHIFT                                                        0x1
#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK__SHIFT                                                       0x10
#define SPI_RESOURCE_RESERVE_EN_CU_7__EN_MASK                                                                 0x00000001L
#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK_MASK                                                          0x0000FFFEL
#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK_MASK                                                         0x00FF0000L
//SPI_RESOURCE_RESERVE_EN_CU_8
#define SPI_RESOURCE_RESERVE_EN_CU_8__EN__SHIFT                                                               0x0
#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK__SHIFT                                                        0x1
#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK__SHIFT                                                       0x10
#define SPI_RESOURCE_RESERVE_EN_CU_8__EN_MASK                                                                 0x00000001L
#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK_MASK                                                          0x0000FFFEL
#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK_MASK                                                         0x00FF0000L
//SPI_RESOURCE_RESERVE_EN_CU_9
#define SPI_RESOURCE_RESERVE_EN_CU_9__EN__SHIFT                                                               0x0
#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK__SHIFT                                                        0x1
#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK__SHIFT                                                       0x10
#define SPI_RESOURCE_RESERVE_EN_CU_9__EN_MASK                                                                 0x00000001L
#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK_MASK                                                          0x0000FFFEL
#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK_MASK                                                         0x00FF0000L
//SPI_COMPUTE_WF_CTX_SAVE
#define SPI_COMPUTE_WF_CTX_SAVE__INITIATE__SHIFT                                                              0x0
#define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN__SHIFT                                                      0x1
#define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN__SHIFT                                                     0x2
#define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY__SHIFT                                                          0x1e
#define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY__SHIFT                                                             0x1f
#define SPI_COMPUTE_WF_CTX_SAVE__INITIATE_MASK                                                                0x00000001L
#define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN_MASK                                                        0x00000002L
#define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN_MASK                                                       0x00000004L
#define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY_MASK                                                            0x40000000L
#define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY_MASK                                                               0x80000000L
//SPI_ARB_CNTL_0
#define SPI_ARB_CNTL_0__EXP_ARB_COL_WT__SHIFT                                                                 0x0
#define SPI_ARB_CNTL_0__EXP_ARB_POS_WT__SHIFT                                                                 0x4
#define SPI_ARB_CNTL_0__EXP_ARB_GDS_WT__SHIFT                                                                 0x8
#define SPI_ARB_CNTL_0__EXP_ARB_COL_WT_MASK                                                                   0x0000000FL
#define SPI_ARB_CNTL_0__EXP_ARB_POS_WT_MASK                                                                   0x000000F0L
#define SPI_ARB_CNTL_0__EXP_ARB_GDS_WT_MASK                                                                   0x00000F00L
//SPI_FEATURE_CTRL
#define SPI_FEATURE_CTRL__CU_LOCKING_FAIRNESS_DISABLE__SHIFT                                                  0x0
#define SPI_FEATURE_CTRL__ALLOCATION_RATE_THROTTLE_THRESHOLD__SHIFT                                           0x2
#define SPI_FEATURE_CTRL__ACTIVE_HARD_LOCK_LIMIT__SHIFT                                                       0x7
#define SPI_FEATURE_CTRL__LR_IMBALANCE_THRESHOLD__SHIFT                                                       0xc
#define SPI_FEATURE_CTRL__RA_PIPE_DEPTH_THRESHOLD_ALLOC_STALL_EN__SHIFT                                       0x12
#define SPI_FEATURE_CTRL__BUS_ACTIVITY_THRESHOLD_ALLOC_STALL_EN__SHIFT                                        0x13
#define SPI_FEATURE_CTRL__BUS_ACTIVITY_THRESHOLD__SHIFT                                                       0x14
#define SPI_FEATURE_CTRL__TUNNELING_WAVE_LIMIT__SHIFT                                                         0x1c
#define SPI_FEATURE_CTRL__CU_LOCKING_FAIRNESS_DISABLE_MASK                                                    0x00000001L
#define SPI_FEATURE_CTRL__ALLOCATION_RATE_THROTTLE_THRESHOLD_MASK                                             0x0000007CL
#define SPI_FEATURE_CTRL__ACTIVE_HARD_LOCK_LIMIT_MASK                                                         0x00000F80L
#define SPI_FEATURE_CTRL__LR_IMBALANCE_THRESHOLD_MASK                                                         0x0003F000L
#define SPI_FEATURE_CTRL__RA_PIPE_DEPTH_THRESHOLD_ALLOC_STALL_EN_MASK                                         0x00040000L
#define SPI_FEATURE_CTRL__BUS_ACTIVITY_THRESHOLD_ALLOC_STALL_EN_MASK                                          0x00080000L
#define SPI_FEATURE_CTRL__BUS_ACTIVITY_THRESHOLD_MASK                                                         0x0FF00000L
#define SPI_FEATURE_CTRL__TUNNELING_WAVE_LIMIT_MASK                                                           0xF0000000L
//SPI_SHADER_RSRC_LIMIT_CTRL
#define SPI_SHADER_RSRC_LIMIT_CTRL__WAVES_PER_SIMD32__SHIFT                                                   0x0
#define SPI_SHADER_RSRC_LIMIT_CTRL__VGPR_PER_SIMD32__SHIFT                                                    0x5
#define SPI_SHADER_RSRC_LIMIT_CTRL__VGPR_WRAP_DISABLE__SHIFT                                                  0xc
#define SPI_SHADER_RSRC_LIMIT_CTRL__BARRIER_LIMIT__SHIFT                                                      0xd
#define SPI_SHADER_RSRC_LIMIT_CTRL__BARRIER_LIMIT_HIERARCHY_LEVEL__SHIFT                                      0x13
#define SPI_SHADER_RSRC_LIMIT_CTRL__LDS_LIMIT__SHIFT                                                          0x14
#define SPI_SHADER_RSRC_LIMIT_CTRL__LDS_LIMIT_HIERARCHY_LEVEL__SHIFT                                          0x1c
#define SPI_SHADER_RSRC_LIMIT_CTRL__PERFORMANCE_LIMIT_ENABLE__SHIFT                                           0x1f
#define SPI_SHADER_RSRC_LIMIT_CTRL__WAVES_PER_SIMD32_MASK                                                     0x0000001FL
#define SPI_SHADER_RSRC_LIMIT_CTRL__VGPR_PER_SIMD32_MASK                                                      0x00000FE0L
#define SPI_SHADER_RSRC_LIMIT_CTRL__VGPR_WRAP_DISABLE_MASK                                                    0x00001000L
#define SPI_SHADER_RSRC_LIMIT_CTRL__BARRIER_LIMIT_MASK                                                        0x0007E000L
#define SPI_SHADER_RSRC_LIMIT_CTRL__BARRIER_LIMIT_HIERARCHY_LEVEL_MASK                                        0x00080000L
#define SPI_SHADER_RSRC_LIMIT_CTRL__LDS_LIMIT_MASK                                                            0x0FF00000L
#define SPI_SHADER_RSRC_LIMIT_CTRL__LDS_LIMIT_HIERARCHY_LEVEL_MASK                                            0x10000000L
#define SPI_SHADER_RSRC_LIMIT_CTRL__PERFORMANCE_LIMIT_ENABLE_MASK                                             0x80000000L


// addressBlock: gc_cpphqddec
//CP_HPD_MES_ROQ_OFFSETS
#define CP_HPD_MES_ROQ_OFFSETS__IQ_OFFSET__SHIFT                                                              0x0
#define CP_HPD_MES_ROQ_OFFSETS__PQ_OFFSET__SHIFT                                                              0x8
#define CP_HPD_MES_ROQ_OFFSETS__IB_OFFSET__SHIFT                                                              0x10
#define CP_HPD_MES_ROQ_OFFSETS__IQ_OFFSET_MASK                                                                0x00000007L
#define CP_HPD_MES_ROQ_OFFSETS__PQ_OFFSET_MASK                                                                0x00003F00L
#define CP_HPD_MES_ROQ_OFFSETS__IB_OFFSET_MASK                                                                0x007F0000L
//CP_HPD_ROQ_OFFSETS
#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT                                                                  0x0
#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET__SHIFT                                                                  0x8
#define CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT                                                                  0x10
#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET_MASK                                                                    0x00000007L
#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET_MASK                                                                    0x00003F00L
#define CP_HPD_ROQ_OFFSETS__IB_OFFSET_MASK                                                                    0x007F0000L
//CP_HPD_STATUS0
#define CP_HPD_STATUS0__QUEUE_STATE__SHIFT                                                                    0x0
#define CP_HPD_STATUS0__MAPPED_QUEUE__SHIFT                                                                   0x5
#define CP_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT                                                                0x8
#define CP_HPD_STATUS0__FETCHING_MQD__SHIFT                                                                   0x10
#define CP_HPD_STATUS0__PEND_TXFER_SIZE_PQIB__SHIFT                                                           0x11
#define CP_HPD_STATUS0__PEND_TXFER_SIZE_IQ__SHIFT                                                             0x12
#define CP_HPD_STATUS0__FORCE_QUEUE_STATE__SHIFT                                                              0x14
#define CP_HPD_STATUS0__MASTER_QUEUE_IDLE_DIS__SHIFT                                                          0x1b
#define CP_HPD_STATUS0__ENABLE_OFFLOAD_CHECK__SHIFT                                                           0x1c
#define CP_HPD_STATUS0__FREEZE_QUEUE_STATE__SHIFT                                                             0x1e
#define CP_HPD_STATUS0__FORCE_QUEUE__SHIFT                                                                    0x1f
#define CP_HPD_STATUS0__QUEUE_STATE_MASK                                                                      0x0000001FL
#define CP_HPD_STATUS0__MAPPED_QUEUE_MASK                                                                     0x000000E0L
#define CP_HPD_STATUS0__QUEUE_AVAILABLE_MASK                                                                  0x0000FF00L
#define CP_HPD_STATUS0__FETCHING_MQD_MASK                                                                     0x00010000L
#define CP_HPD_STATUS0__PEND_TXFER_SIZE_PQIB_MASK                                                             0x00020000L
#define CP_HPD_STATUS0__PEND_TXFER_SIZE_IQ_MASK                                                               0x00040000L
#define CP_HPD_STATUS0__FORCE_QUEUE_STATE_MASK                                                                0x01F00000L
#define CP_HPD_STATUS0__MASTER_QUEUE_IDLE_DIS_MASK                                                            0x08000000L
#define CP_HPD_STATUS0__ENABLE_OFFLOAD_CHECK_MASK                                                             0x30000000L
#define CP_HPD_STATUS0__FREEZE_QUEUE_STATE_MASK                                                               0x40000000L
#define CP_HPD_STATUS0__FORCE_QUEUE_MASK                                                                      0x80000000L
//CP_HPD_UTCL1_CNTL
#define CP_HPD_UTCL1_CNTL__SELECT__SHIFT                                                                      0x0
#define CP_HPD_UTCL1_CNTL__SELECT_MASK                                                                        0x0000000FL
//CP_HPD_UTCL1_ERROR
#define CP_HPD_UTCL1_ERROR__ADDR_HI__SHIFT                                                                    0x0
#define CP_HPD_UTCL1_ERROR__TYPE__SHIFT                                                                       0x10
#define CP_HPD_UTCL1_ERROR__VMID__SHIFT                                                                       0x14
#define CP_HPD_UTCL1_ERROR__ADDR_HI_MASK                                                                      0x0000FFFFL
#define CP_HPD_UTCL1_ERROR__TYPE_MASK                                                                         0x00010000L
#define CP_HPD_UTCL1_ERROR__VMID_MASK                                                                         0x00F00000L
//CP_HPD_UTCL1_ERROR_ADDR
#define CP_HPD_UTCL1_ERROR_ADDR__ADDR__SHIFT                                                                  0xc
#define CP_HPD_UTCL1_ERROR_ADDR__ADDR_MASK                                                                    0xFFFFF000L
//CP_MQD_BASE_ADDR
#define CP_MQD_BASE_ADDR__BASE_ADDR__SHIFT                                                                    0x2
#define CP_MQD_BASE_ADDR__BASE_ADDR_MASK                                                                      0xFFFFFFFCL
//CP_MQD_BASE_ADDR_HI
#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT                                                              0x0
#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK                                                                0x0000FFFFL
//CP_HQD_ACTIVE
#define CP_HQD_ACTIVE__ACTIVE__SHIFT                                                                          0x0
#define CP_HQD_ACTIVE__BUSY_GATE__SHIFT                                                                       0x1
#define CP_HQD_ACTIVE__ACTIVE_MASK                                                                            0x00000001L
#define CP_HQD_ACTIVE__BUSY_GATE_MASK                                                                         0x00000002L
//CP_HQD_VMID
#define CP_HQD_VMID__VMID__SHIFT                                                                              0x0
#define CP_HQD_VMID__IB_VMID__SHIFT                                                                           0x8
#define CP_HQD_VMID__VQID__SHIFT                                                                              0x10
#define CP_HQD_VMID__VMID_MASK                                                                                0x0000000FL
#define CP_HQD_VMID__IB_VMID_MASK                                                                             0x00000F00L
#define CP_HQD_VMID__VQID_MASK                                                                                0x03FF0000L
//CP_HQD_PERSISTENT_STATE
#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ__SHIFT                                                           0x0
#define CP_HQD_PERSISTENT_STATE__SUSPEND_STATUS__SHIFT                                                        0x7
#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT                                                          0x8
#define CP_HQD_PERSISTENT_STATE__WPP_CLAMP_EN__SHIFT                                                          0x14
#define CP_HQD_PERSISTENT_STATE__WPP_SWITCH_QOS_EN__SHIFT                                                     0x15
#define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN__SHIFT                                                      0x16
#define CP_HQD_PERSISTENT_STATE__IB_SWITCH_QOS_EN__SHIFT                                                      0x17
#define CP_HQD_PERSISTENT_STATE__EOP_SWITCH_QOS_EN__SHIFT                                                     0x18
#define CP_HQD_PERSISTENT_STATE__PQ_SWITCH_QOS_EN__SHIFT                                                      0x19
#define CP_HQD_PERSISTENT_STATE__TC_OFFLOAD_QOS_EN__SHIFT                                                     0x1a
#define CP_HQD_PERSISTENT_STATE__CACHE_FULL_PACKET_EN__SHIFT                                                  0x1b
#define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE__SHIFT                                                        0x1c
#define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES__SHIFT                                                        0x1d
#define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT                                                          0x1e
#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE__SHIFT                                                           0x1f
#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK                                                             0x00000001L
#define CP_HQD_PERSISTENT_STATE__SUSPEND_STATUS_MASK                                                          0x00000080L
#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE_MASK                                                            0x0003FF00L
#define CP_HQD_PERSISTENT_STATE__WPP_CLAMP_EN_MASK                                                            0x00100000L
#define CP_HQD_PERSISTENT_STATE__WPP_SWITCH_QOS_EN_MASK                                                       0x00200000L
#define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN_MASK                                                        0x00400000L
#define CP_HQD_PERSISTENT_STATE__IB_SWITCH_QOS_EN_MASK                                                        0x00800000L
#define CP_HQD_PERSISTENT_STATE__EOP_SWITCH_QOS_EN_MASK                                                       0x01000000L
#define CP_HQD_PERSISTENT_STATE__PQ_SWITCH_QOS_EN_MASK                                                        0x02000000L
#define CP_HQD_PERSISTENT_STATE__TC_OFFLOAD_QOS_EN_MASK                                                       0x04000000L
#define CP_HQD_PERSISTENT_STATE__CACHE_FULL_PACKET_EN_MASK                                                    0x08000000L
#define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE_MASK                                                          0x10000000L
#define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES_MASK                                                          0x20000000L
#define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE_MASK                                                            0x40000000L
#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE_MASK                                                             0x80000000L
//CP_HQD_PIPE_PRIORITY
#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY__SHIFT                                                            0x0
#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY_MASK                                                              0x00000003L
//CP_HQD_QUEUE_PRIORITY
#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT                                                          0x0
#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK                                                            0x0000000FL
//CP_HQD_QUANTUM
#define CP_HQD_QUANTUM__QUANTUM_EN__SHIFT                                                                     0x0
#define CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT                                                                  0x4
#define CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT                                                               0x8
#define CP_HQD_QUANTUM__QUANTUM_ACTIVE__SHIFT                                                                 0x1f
#define CP_HQD_QUANTUM__QUANTUM_EN_MASK                                                                       0x00000001L
#define CP_HQD_QUANTUM__QUANTUM_SCALE_MASK                                                                    0x00000010L
#define CP_HQD_QUANTUM__QUANTUM_DURATION_MASK                                                                 0x00003F00L
#define CP_HQD_QUANTUM__QUANTUM_ACTIVE_MASK                                                                   0x80000000L
//CP_HQD_PQ_BASE
#define CP_HQD_PQ_BASE__ADDR__SHIFT                                                                           0x0
#define CP_HQD_PQ_BASE__ADDR_MASK                                                                             0xFFFFFFFFL
//CP_HQD_PQ_BASE_HI
#define CP_HQD_PQ_BASE_HI__ADDR_HI__SHIFT                                                                     0x0
#define CP_HQD_PQ_BASE_HI__ADDR_HI_MASK                                                                       0x000000FFL
//CP_HQD_PQ_RPTR
#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET__SHIFT                                                                0x0
#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET_MASK                                                                  0xFFFFFFFFL
//CP_HQD_PQ_RPTR_REPORT_ADDR
#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR__SHIFT                                                   0x2
#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR_MASK                                                     0xFFFFFFFCL
//CP_HQD_PQ_RPTR_REPORT_ADDR_HI
#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI__SHIFT                                             0x0
#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI_MASK                                               0x0000FFFFL
//CP_HQD_PQ_WPTR_POLL_ADDR
#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR__SHIFT                                                            0x3
#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR_MASK                                                              0xFFFFFFF8L
//CP_HQD_PQ_WPTR_POLL_ADDR_HI
#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI__SHIFT                                                      0x0
#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK                                                        0x0000FFFFL
//CP_HQD_PQ_DOORBELL_CONTROL
#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT                                                      0x0
#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT                                                  0x1
#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT                                                    0x2
#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE__SHIFT                                                    0x1c
#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT__SHIFT                                                  0x1d
#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN__SHIFT                                                        0x1e
#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT                                                       0x1f
#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE_MASK                                                        0x00000001L
#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK                                                    0x00000002L
#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK                                                      0x0FFFFFFCL
#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK                                                      0x10000000L
#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT_MASK                                                    0x20000000L
#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK                                                          0x40000000L
#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK                                                         0x80000000L
//CP_HQD_PQ_CONTROL
#define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT                                                                  0x0
#define CP_HQD_PQ_CONTROL__WPTR_CARRY__SHIFT                                                                  0x6
#define CP_HQD_PQ_CONTROL__RPTR_CARRY__SHIFT                                                                  0x7
#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT                                                             0x8
#define CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT                                                               0xe
#define CP_HQD_PQ_CONTROL__PQ_EMPTY__SHIFT                                                                    0xf
#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT                                                             0x12
#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE__SHIFT                                                              0x14
#define CP_HQD_PQ_CONTROL__EXE_DISABLE__SHIFT                                                                 0x17
#define CP_HQD_PQ_CONTROL__CACHE_POLICY__SHIFT                                                                0x18
#define CP_HQD_PQ_CONTROL__PQ_VOLATILE__SHIFT                                                                 0x1a
#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR__SHIFT                                                              0x1b
#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH__SHIFT                                                              0x1c
#define CP_HQD_PQ_CONTROL__TUNNEL_DISPATCH__SHIFT                                                             0x1d
#define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT                                                                  0x1e
#define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT                                                                   0x1f
#define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK                                                                    0x0000003FL
#define CP_HQD_PQ_CONTROL__WPTR_CARRY_MASK                                                                    0x00000040L
#define CP_HQD_PQ_CONTROL__RPTR_CARRY_MASK                                                                    0x00000080L
#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK                                                               0x00003F00L
#define CP_HQD_PQ_CONTROL__QUEUE_FULL_EN_MASK                                                                 0x00004000L
#define CP_HQD_PQ_CONTROL__PQ_EMPTY_MASK                                                                      0x00008000L
#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK                                                               0x000C0000L
#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE_MASK                                                                0x00300000L
#define CP_HQD_PQ_CONTROL__EXE_DISABLE_MASK                                                                   0x00800000L
#define CP_HQD_PQ_CONTROL__CACHE_POLICY_MASK                                                                  0x03000000L
#define CP_HQD_PQ_CONTROL__PQ_VOLATILE_MASK                                                                   0x04000000L
#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK                                                                0x08000000L
#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK                                                                0x10000000L
#define CP_HQD_PQ_CONTROL__TUNNEL_DISPATCH_MASK                                                               0x20000000L
#define CP_HQD_PQ_CONTROL__PRIV_STATE_MASK                                                                    0x40000000L
#define CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK                                                                     0x80000000L
//CP_HQD_IB_BASE_ADDR
#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR__SHIFT                                                              0x2
#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR_MASK                                                                0xFFFFFFFCL
//CP_HQD_IB_BASE_ADDR_HI
#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI__SHIFT                                                        0x0
#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI_MASK                                                          0x0000FFFFL
//CP_HQD_IB_RPTR
#define CP_HQD_IB_RPTR__CONSUMED_OFFSET__SHIFT                                                                0x0
#define CP_HQD_IB_RPTR__CONSUMED_OFFSET_MASK                                                                  0x000FFFFFL
//CP_HQD_IB_CONTROL
#define CP_HQD_IB_CONTROL__IB_SIZE__SHIFT                                                                     0x0
#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT                                                           0x14
#define CP_HQD_IB_CONTROL__IB_EXE_DISABLE__SHIFT                                                              0x17
#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY__SHIFT                                                             0x18
#define CP_HQD_IB_CONTROL__IB_VOLATILE__SHIFT                                                                 0x1a
#define CP_HQD_IB_CONTROL__PROCESSING_IB__SHIFT                                                               0x1f
#define CP_HQD_IB_CONTROL__IB_SIZE_MASK                                                                       0x000FFFFFL
#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE_MASK                                                             0x00300000L
#define CP_HQD_IB_CONTROL__IB_EXE_DISABLE_MASK                                                                0x00800000L
#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY_MASK                                                               0x03000000L
#define CP_HQD_IB_CONTROL__IB_VOLATILE_MASK                                                                   0x04000000L
#define CP_HQD_IB_CONTROL__PROCESSING_IB_MASK                                                                 0x80000000L
//CP_HQD_IQ_TIMER
#define CP_HQD_IQ_TIMER__WAIT_TIME__SHIFT                                                                     0x0
#define CP_HQD_IQ_TIMER__RETRY_TYPE__SHIFT                                                                    0x8
#define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE__SHIFT                                                              0xb
#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT                                                                0xc
#define CP_HQD_IQ_TIMER__CLOCK_COUNT__SHIFT                                                                   0xe
#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE__SHIFT                                                                0x10
#define CP_HQD_IQ_TIMER__QUANTUM_TIMER__SHIFT                                                                 0x16
#define CP_HQD_IQ_TIMER__EXE_DISABLE__SHIFT                                                                   0x17
#define CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT                                                                  0x18
#define CP_HQD_IQ_TIMER__IQ_VOLATILE__SHIFT                                                                   0x1a
#define CP_HQD_IQ_TIMER__QUEUE_TYPE__SHIFT                                                                    0x1b
#define CP_HQD_IQ_TIMER__REARM_TIMER__SHIFT                                                                   0x1c
#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN__SHIFT                                                                 0x1d
#define CP_HQD_IQ_TIMER__PROCESSING_IQ__SHIFT                                                                 0x1e
#define CP_HQD_IQ_TIMER__ACTIVE__SHIFT                                                                        0x1f
#define CP_HQD_IQ_TIMER__WAIT_TIME_MASK                                                                       0x000000FFL
#define CP_HQD_IQ_TIMER__RETRY_TYPE_MASK                                                                      0x00000700L
#define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE_MASK                                                                0x00000800L
#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE_MASK                                                                  0x00003000L
#define CP_HQD_IQ_TIMER__CLOCK_COUNT_MASK                                                                     0x0000C000L
#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK                                                                  0x003F0000L
#define CP_HQD_IQ_TIMER__QUANTUM_TIMER_MASK                                                                   0x00400000L
#define CP_HQD_IQ_TIMER__EXE_DISABLE_MASK                                                                     0x00800000L
#define CP_HQD_IQ_TIMER__CACHE_POLICY_MASK                                                                    0x03000000L
#define CP_HQD_IQ_TIMER__IQ_VOLATILE_MASK                                                                     0x04000000L
#define CP_HQD_IQ_TIMER__QUEUE_TYPE_MASK                                                                      0x08000000L
#define CP_HQD_IQ_TIMER__REARM_TIMER_MASK                                                                     0x10000000L
#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN_MASK                                                                   0x20000000L
#define CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK                                                                   0x40000000L
#define CP_HQD_IQ_TIMER__ACTIVE_MASK                                                                          0x80000000L
//CP_HQD_IQ_RPTR
#define CP_HQD_IQ_RPTR__OFFSET__SHIFT                                                                         0x0
#define CP_HQD_IQ_RPTR__OFFSET_MASK                                                                           0x0000003FL
//CP_HQD_DEQUEUE_REQUEST
#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT                                                            0x0
#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT                                                            0x4
#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT__SHIFT                                                            0x8
#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN__SHIFT                                                         0x9
#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN__SHIFT                                                         0xa
#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK                                                              0x0000000FL
#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK                                                              0x00000010L
#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT_MASK                                                              0x00000100L
#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN_MASK                                                           0x00000200L
#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN_MASK                                                           0x00000400L
//CP_HQD_DMA_OFFLOAD
#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD__SHIFT                                                                0x0
#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_MASK                                                                  0x00000001L
//CP_HQD_OFFLOAD
#define CP_HQD_OFFLOAD__DMA_OFFLOAD__SHIFT                                                                    0x0
#define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN__SHIFT                                                                 0x1
#define CP_HQD_OFFLOAD__AQL_OFFLOAD__SHIFT                                                                    0x2
#define CP_HQD_OFFLOAD__AQL_OFFLOAD_EN__SHIFT                                                                 0x3
#define CP_HQD_OFFLOAD__EOP_OFFLOAD__SHIFT                                                                    0x4
#define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN__SHIFT                                                                 0x5
#define CP_HQD_OFFLOAD__DMA_OFFLOAD_MASK                                                                      0x00000001L
#define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN_MASK                                                                   0x00000002L
#define CP_HQD_OFFLOAD__AQL_OFFLOAD_MASK                                                                      0x00000004L
#define CP_HQD_OFFLOAD__AQL_OFFLOAD_EN_MASK                                                                   0x00000008L
#define CP_HQD_OFFLOAD__EOP_OFFLOAD_MASK                                                                      0x00000010L
#define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN_MASK                                                                   0x00000020L
//CP_HQD_SEMA_CMD
#define CP_HQD_SEMA_CMD__RETRY__SHIFT                                                                         0x0
#define CP_HQD_SEMA_CMD__RESULT__SHIFT                                                                        0x1
#define CP_HQD_SEMA_CMD__POLLING_DIS__SHIFT                                                                   0x8
#define CP_HQD_SEMA_CMD__MESSAGE_EN__SHIFT                                                                    0x9
#define CP_HQD_SEMA_CMD__RETRY_MASK                                                                           0x00000001L
#define CP_HQD_SEMA_CMD__RESULT_MASK                                                                          0x00000006L
#define CP_HQD_SEMA_CMD__POLLING_DIS_MASK                                                                     0x00000100L
#define CP_HQD_SEMA_CMD__MESSAGE_EN_MASK                                                                      0x00000200L
//CP_HQD_MSG_TYPE
#define CP_HQD_MSG_TYPE__ACTION__SHIFT                                                                        0x0
#define CP_HQD_MSG_TYPE__SAVE_STATE__SHIFT                                                                    0x4
#define CP_HQD_MSG_TYPE__ACTION_MASK                                                                          0x00000007L
#define CP_HQD_MSG_TYPE__SAVE_STATE_MASK                                                                      0x00000070L
//CP_HQD_ATOMIC0_PREOP_LO
#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO__SHIFT                                                      0x0
#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO_MASK                                                        0xFFFFFFFFL
//CP_HQD_ATOMIC0_PREOP_HI
#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI__SHIFT                                                      0x0
#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI_MASK                                                        0xFFFFFFFFL
//CP_HQD_ATOMIC1_PREOP_LO
#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO__SHIFT                                                      0x0
#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO_MASK                                                        0xFFFFFFFFL
//CP_HQD_ATOMIC1_PREOP_HI
#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI__SHIFT                                                      0x0
#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI_MASK                                                        0xFFFFFFFFL
//CP_HQD_HQ_SCHEDULER0
#define CP_HQD_HQ_SCHEDULER0__SCHEDULER__SHIFT                                                                0x0
#define CP_HQD_HQ_SCHEDULER0__SCHEDULER_MASK                                                                  0xFFFFFFFFL
//CP_HQD_HQ_STATUS0
#define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS__SHIFT                                                              0x0
#define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT__SHIFT                                                           0x2
#define CP_HQD_HQ_STATUS0__RSV_6_4__SHIFT                                                                     0x4
#define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT__SHIFT                                                            0x7
#define CP_HQD_HQ_STATUS0__TCL2_DIRTY__SHIFT                                                                  0x8
#define CP_HQD_HQ_STATUS0__PG_ACTIVATED__SHIFT                                                                0x9
#define CP_HQD_HQ_STATUS0__RSVR_29_10__SHIFT                                                                  0xa
#define CP_HQD_HQ_STATUS0__QUEUE_IDLE__SHIFT                                                                  0x1e
#define CP_HQD_HQ_STATUS0__DB_UPDATED_MSG_EN__SHIFT                                                           0x1f
#define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS_MASK                                                                0x00000003L
#define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT_MASK                                                             0x0000000CL
#define CP_HQD_HQ_STATUS0__RSV_6_4_MASK                                                                       0x00000070L
#define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT_MASK                                                              0x00000080L
#define CP_HQD_HQ_STATUS0__TCL2_DIRTY_MASK                                                                    0x00000100L
#define CP_HQD_HQ_STATUS0__PG_ACTIVATED_MASK                                                                  0x00000200L
#define CP_HQD_HQ_STATUS0__RSVR_29_10_MASK                                                                    0x3FFFFC00L
#define CP_HQD_HQ_STATUS0__QUEUE_IDLE_MASK                                                                    0x40000000L
#define CP_HQD_HQ_STATUS0__DB_UPDATED_MSG_EN_MASK                                                             0x80000000L
//CP_HQD_HQ_CONTROL0
#define CP_HQD_HQ_CONTROL0__CONTROL__SHIFT                                                                    0x0
#define CP_HQD_HQ_CONTROL0__CONTROL_MASK                                                                      0xFFFFFFFFL
//CP_HQD_HQ_SCHEDULER1
#define CP_HQD_HQ_SCHEDULER1__SCHEDULER__SHIFT                                                                0x0
#define CP_HQD_HQ_SCHEDULER1__SCHEDULER_MASK                                                                  0xFFFFFFFFL
//CP_MQD_CONTROL
#define CP_MQD_CONTROL__VMID__SHIFT                                                                           0x0
#define CP_MQD_CONTROL__PRIV_STATE__SHIFT                                                                     0x8
#define CP_MQD_CONTROL__PROCESSING_MQD__SHIFT                                                                 0xc
#define CP_MQD_CONTROL__PROCESSING_MQD_EN__SHIFT                                                              0xd
#define CP_MQD_CONTROL__EXE_DISABLE__SHIFT                                                                    0x17
#define CP_MQD_CONTROL__CACHE_POLICY__SHIFT                                                                   0x18
#define CP_MQD_CONTROL__MQD_VOLATILE__SHIFT                                                                   0x1a
#define CP_MQD_CONTROL__VMID_MASK                                                                             0x0000000FL
#define CP_MQD_CONTROL__PRIV_STATE_MASK                                                                       0x00000100L
#define CP_MQD_CONTROL__PROCESSING_MQD_MASK                                                                   0x00001000L
#define CP_MQD_CONTROL__PROCESSING_MQD_EN_MASK                                                                0x00002000L
#define CP_MQD_CONTROL__EXE_DISABLE_MASK                                                                      0x00800000L
#define CP_MQD_CONTROL__CACHE_POLICY_MASK                                                                     0x03000000L
#define CP_MQD_CONTROL__MQD_VOLATILE_MASK                                                                     0x04000000L
//CP_HQD_HQ_STATUS1
#define CP_HQD_HQ_STATUS1__STATUS__SHIFT                                                                      0x0
#define CP_HQD_HQ_STATUS1__STATUS_MASK                                                                        0xFFFFFFFFL
//CP_HQD_HQ_CONTROL1
#define CP_HQD_HQ_CONTROL1__CONTROL__SHIFT                                                                    0x0
#define CP_HQD_HQ_CONTROL1__CONTROL_MASK                                                                      0xFFFFFFFFL
//CP_HQD_EOP_BASE_ADDR
#define CP_HQD_EOP_BASE_ADDR__BASE_ADDR__SHIFT                                                                0x0
#define CP_HQD_EOP_BASE_ADDR__BASE_ADDR_MASK                                                                  0xFFFFFFFFL
//CP_HQD_EOP_BASE_ADDR_HI
#define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT                                                          0x0
#define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI_MASK                                                            0x000000FFL
//CP_HQD_EOP_CONTROL
#define CP_HQD_EOP_CONTROL__EOP_SIZE__SHIFT                                                                   0x0
#define CP_HQD_EOP_CONTROL__PROCESSING_EOP__SHIFT                                                             0x8
#define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN__SHIFT                                                             0xc
#define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB__SHIFT                                                           0xd
#define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN__SHIFT                                                           0xe
#define CP_HQD_EOP_CONTROL__HALT_FETCHER__SHIFT                                                               0x15
#define CP_HQD_EOP_CONTROL__HALT_FETCHER_EN__SHIFT                                                            0x16
#define CP_HQD_EOP_CONTROL__EXE_DISABLE__SHIFT                                                                0x17
#define CP_HQD_EOP_CONTROL__CACHE_POLICY__SHIFT                                                               0x18
#define CP_HQD_EOP_CONTROL__EOP_VOLATILE__SHIFT                                                               0x1a
#define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT__SHIFT                                                             0x1d
#define CP_HQD_EOP_CONTROL__PEND_SIG_SEM__SHIFT                                                               0x1f
#define CP_HQD_EOP_CONTROL__EOP_SIZE_MASK                                                                     0x0000003FL
#define CP_HQD_EOP_CONTROL__PROCESSING_EOP_MASK                                                               0x00000100L
#define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN_MASK                                                               0x00001000L
#define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB_MASK                                                             0x00002000L
#define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN_MASK                                                             0x00004000L
#define CP_HQD_EOP_CONTROL__HALT_FETCHER_MASK                                                                 0x00200000L
#define CP_HQD_EOP_CONTROL__HALT_FETCHER_EN_MASK                                                              0x00400000L
#define CP_HQD_EOP_CONTROL__EXE_DISABLE_MASK                                                                  0x00800000L
#define CP_HQD_EOP_CONTROL__CACHE_POLICY_MASK                                                                 0x03000000L
#define CP_HQD_EOP_CONTROL__EOP_VOLATILE_MASK                                                                 0x04000000L
#define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT_MASK                                                               0x60000000L
#define CP_HQD_EOP_CONTROL__PEND_SIG_SEM_MASK                                                                 0x80000000L
//CP_HQD_EOP_RPTR
#define CP_HQD_EOP_RPTR__RPTR__SHIFT                                                                          0x0
#define CP_HQD_EOP_RPTR__RESET_FETCHER__SHIFT                                                                 0x1c
#define CP_HQD_EOP_RPTR__DEQUEUE_PEND__SHIFT                                                                  0x1d
#define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR__SHIFT                                                             0x1e
#define CP_HQD_EOP_RPTR__INIT_FETCHER__SHIFT                                                                  0x1f
#define CP_HQD_EOP_RPTR__RPTR_MASK                                                                            0x00001FFFL
#define CP_HQD_EOP_RPTR__RESET_FETCHER_MASK                                                                   0x10000000L
#define CP_HQD_EOP_RPTR__DEQUEUE_PEND_MASK                                                                    0x20000000L
#define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR_MASK                                                               0x40000000L
#define CP_HQD_EOP_RPTR__INIT_FETCHER_MASK                                                                    0x80000000L
//CP_HQD_EOP_WPTR
#define CP_HQD_EOP_WPTR__WPTR__SHIFT                                                                          0x0
#define CP_HQD_EOP_WPTR__EOP_EMPTY__SHIFT                                                                     0xf
#define CP_HQD_EOP_WPTR__EOP_AVAIL__SHIFT                                                                     0x10
#define CP_HQD_EOP_WPTR__WPTR_MASK                                                                            0x00001FFFL
#define CP_HQD_EOP_WPTR__EOP_EMPTY_MASK                                                                       0x00008000L
#define CP_HQD_EOP_WPTR__EOP_AVAIL_MASK                                                                       0x1FFF0000L
//CP_HQD_EOP_EVENTS
#define CP_HQD_EOP_EVENTS__EVENT_COUNT__SHIFT                                                                 0x0
#define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND__SHIFT                                                       0x10
#define CP_HQD_EOP_EVENTS__EVENT_COUNT_MASK                                                                   0x00000FFFL
#define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND_MASK                                                         0x00010000L
//CP_HQD_CTX_SAVE_BASE_ADDR_LO
#define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR__SHIFT                                                             0xc
#define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR_MASK                                                               0xFFFFF000L
//CP_HQD_CTX_SAVE_BASE_ADDR_HI
#define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI__SHIFT                                                          0x0
#define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI_MASK                                                            0x0000FFFFL
//CP_HQD_CTX_SAVE_CONTROL
#define CP_HQD_CTX_SAVE_CONTROL__POLICY__SHIFT                                                                0x3
#define CP_HQD_CTX_SAVE_CONTROL__EXE_DISABLE__SHIFT                                                           0x17
#define CP_HQD_CTX_SAVE_CONTROL__POLICY_MASK                                                                  0x00000018L
#define CP_HQD_CTX_SAVE_CONTROL__EXE_DISABLE_MASK                                                             0x00800000L
//CP_HQD_CNTL_STACK_OFFSET
#define CP_HQD_CNTL_STACK_OFFSET__OFFSET__SHIFT                                                               0x2
#define CP_HQD_CNTL_STACK_OFFSET__OFFSET_MASK                                                                 0x00007FFCL
//CP_HQD_CNTL_STACK_SIZE
#define CP_HQD_CNTL_STACK_SIZE__SIZE__SHIFT                                                                   0xc
#define CP_HQD_CNTL_STACK_SIZE__SIZE_MASK                                                                     0x00007000L
//CP_HQD_WG_STATE_OFFSET
#define CP_HQD_WG_STATE_OFFSET__OFFSET__SHIFT                                                                 0x2
#define CP_HQD_WG_STATE_OFFSET__OFFSET_MASK                                                                   0x01FFFFFCL
//CP_HQD_CTX_SAVE_SIZE
#define CP_HQD_CTX_SAVE_SIZE__SIZE__SHIFT                                                                     0xc
#define CP_HQD_CTX_SAVE_SIZE__SIZE_MASK                                                                       0x01FFF000L
//CP_HQD_GDS_RESOURCE_STATE
#define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED__SHIFT                                                         0x0
#define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED__SHIFT                                                         0x1
#define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE__SHIFT                                                            0x4
#define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR__SHIFT                                                            0xc
#define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED_MASK                                                           0x00000001L
#define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED_MASK                                                           0x00000002L
#define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE_MASK                                                              0x000003F0L
#define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR_MASK                                                              0x0003F000L
//CP_HQD_ERROR
#define CP_HQD_ERROR__EDC_ERROR_ID__SHIFT                                                                     0x0
#define CP_HQD_ERROR__SUA_ERROR__SHIFT                                                                        0x4
#define CP_HQD_ERROR__AQL_ERROR__SHIFT                                                                        0x5
#define CP_HQD_ERROR__PQ_UTCL1_ERROR__SHIFT                                                                   0x8
#define CP_HQD_ERROR__IB_UTCL1_ERROR__SHIFT                                                                   0x9
#define CP_HQD_ERROR__EOP_UTCL1_ERROR__SHIFT                                                                  0xa
#define CP_HQD_ERROR__IQ_UTCL1_ERROR__SHIFT                                                                   0xb
#define CP_HQD_ERROR__RRPT_UTCL1_ERROR__SHIFT                                                                 0xc
#define CP_HQD_ERROR__WPP_UTCL1_ERROR__SHIFT                                                                  0xd
#define CP_HQD_ERROR__SEM_UTCL1_ERROR__SHIFT                                                                  0xe
#define CP_HQD_ERROR__DMA_SRC_UTCL1_ERROR__SHIFT                                                              0xf
#define CP_HQD_ERROR__DMA_DST_UTCL1_ERROR__SHIFT                                                              0x10
#define CP_HQD_ERROR__SR_UTCL1_ERROR__SHIFT                                                                   0x11
#define CP_HQD_ERROR__QU_UTCL1_ERROR__SHIFT                                                                   0x12
#define CP_HQD_ERROR__TC_UTCL1_ERROR__SHIFT                                                                   0x13
#define CP_HQD_ERROR__EDC_ERROR_ID_MASK                                                                       0x0000000FL
#define CP_HQD_ERROR__SUA_ERROR_MASK                                                                          0x00000010L
#define CP_HQD_ERROR__AQL_ERROR_MASK                                                                          0x00000020L
#define CP_HQD_ERROR__PQ_UTCL1_ERROR_MASK                                                                     0x00000100L
#define CP_HQD_ERROR__IB_UTCL1_ERROR_MASK                                                                     0x00000200L
#define CP_HQD_ERROR__EOP_UTCL1_ERROR_MASK                                                                    0x00000400L
#define CP_HQD_ERROR__IQ_UTCL1_ERROR_MASK                                                                     0x00000800L
#define CP_HQD_ERROR__RRPT_UTCL1_ERROR_MASK                                                                   0x00001000L
#define CP_HQD_ERROR__WPP_UTCL1_ERROR_MASK                                                                    0x00002000L
#define CP_HQD_ERROR__SEM_UTCL1_ERROR_MASK                                                                    0x00004000L
#define CP_HQD_ERROR__DMA_SRC_UTCL1_ERROR_MASK                                                                0x00008000L
#define CP_HQD_ERROR__DMA_DST_UTCL1_ERROR_MASK                                                                0x00010000L
#define CP_HQD_ERROR__SR_UTCL1_ERROR_MASK                                                                     0x00020000L
#define CP_HQD_ERROR__QU_UTCL1_ERROR_MASK                                                                     0x00040000L
#define CP_HQD_ERROR__TC_UTCL1_ERROR_MASK                                                                     0x00080000L
//CP_HQD_EOP_WPTR_MEM
#define CP_HQD_EOP_WPTR_MEM__WPTR__SHIFT                                                                      0x0
#define CP_HQD_EOP_WPTR_MEM__WPTR_MASK                                                                        0x00001FFFL
//CP_HQD_AQL_CONTROL
#define CP_HQD_AQL_CONTROL__CONTROL0__SHIFT                                                                   0x0
#define CP_HQD_AQL_CONTROL__CONTROL0_EN__SHIFT                                                                0xf
#define CP_HQD_AQL_CONTROL__CONTROL1__SHIFT                                                                   0x10
#define CP_HQD_AQL_CONTROL__CONTROL1_EN__SHIFT                                                                0x1f
#define CP_HQD_AQL_CONTROL__CONTROL0_MASK                                                                     0x00007FFFL
#define CP_HQD_AQL_CONTROL__CONTROL0_EN_MASK                                                                  0x00008000L
#define CP_HQD_AQL_CONTROL__CONTROL1_MASK                                                                     0x7FFF0000L
#define CP_HQD_AQL_CONTROL__CONTROL1_EN_MASK                                                                  0x80000000L
//CP_HQD_PQ_WPTR_LO
#define CP_HQD_PQ_WPTR_LO__OFFSET__SHIFT                                                                      0x0
#define CP_HQD_PQ_WPTR_LO__OFFSET_MASK                                                                        0xFFFFFFFFL
//CP_HQD_PQ_WPTR_HI
#define CP_HQD_PQ_WPTR_HI__DATA__SHIFT                                                                        0x0
#define CP_HQD_PQ_WPTR_HI__DATA_MASK                                                                          0xFFFFFFFFL
//CP_HQD_SUSPEND_CNTL_STACK_OFFSET
#define CP_HQD_SUSPEND_CNTL_STACK_OFFSET__OFFSET__SHIFT                                                       0x2
#define CP_HQD_SUSPEND_CNTL_STACK_OFFSET__OFFSET_MASK                                                         0x00007FFCL
//CP_HQD_SUSPEND_CNTL_STACK_DW_CNT
#define CP_HQD_SUSPEND_CNTL_STACK_DW_CNT__CNT__SHIFT                                                          0x0
#define CP_HQD_SUSPEND_CNTL_STACK_DW_CNT__CNT_MASK                                                            0x00001FFFL
//CP_HQD_SUSPEND_WG_STATE_OFFSET
#define CP_HQD_SUSPEND_WG_STATE_OFFSET__OFFSET__SHIFT                                                         0x2
#define CP_HQD_SUSPEND_WG_STATE_OFFSET__OFFSET_MASK                                                           0x01FFFFFCL
//CP_HQD_DDID_RPTR
#define CP_HQD_DDID_RPTR__RPTR__SHIFT                                                                         0x0
#define CP_HQD_DDID_RPTR__RPTR_MASK                                                                           0x000007FFL
//CP_HQD_DDID_WPTR
#define CP_HQD_DDID_WPTR__WPTR__SHIFT                                                                         0x0
#define CP_HQD_DDID_WPTR__WPTR_MASK                                                                           0x000007FFL
//CP_HQD_DDID_INFLIGHT_COUNT
#define CP_HQD_DDID_INFLIGHT_COUNT__COUNT__SHIFT                                                              0x0
#define CP_HQD_DDID_INFLIGHT_COUNT__COUNT_MASK                                                                0x0000FFFFL
//CP_HQD_DDID_DELTA_RPT_COUNT
#define CP_HQD_DDID_DELTA_RPT_COUNT__COUNT__SHIFT                                                             0x0
#define CP_HQD_DDID_DELTA_RPT_COUNT__COUNT_MASK                                                               0x000000FFL
//CP_HQD_DEQUEUE_STATUS
#define CP_HQD_DEQUEUE_STATUS__DEQUEUE_STAT__SHIFT                                                            0x0
#define CP_HQD_DEQUEUE_STATUS__SUSPEND_REQ_PEND__SHIFT                                                        0x4
#define CP_HQD_DEQUEUE_STATUS__SUSPEND_REQ_PEND_EN__SHIFT                                                     0x9
#define CP_HQD_DEQUEUE_STATUS__DEQUEUE_STAT_EN__SHIFT                                                         0xa
#define CP_HQD_DEQUEUE_STATUS__DEQUEUE_STAT_MASK                                                              0x0000000FL
#define CP_HQD_DEQUEUE_STATUS__SUSPEND_REQ_PEND_MASK                                                          0x00000010L
#define CP_HQD_DEQUEUE_STATUS__SUSPEND_REQ_PEND_EN_MASK                                                       0x00000200L
#define CP_HQD_DEQUEUE_STATUS__DEQUEUE_STAT_EN_MASK                                                           0x00000400L


// addressBlock: gc_didtdec
//DIDT_IND_INDEX
#define DIDT_IND_INDEX__DIDT_IND_INDEX__SHIFT                                                                 0x0
#define DIDT_IND_INDEX__DIDT_IND_INDEX_MASK                                                                   0xFFFFFFFFL
//DIDT_IND_DATA
#define DIDT_IND_DATA__DIDT_IND_DATA__SHIFT                                                                   0x0
#define DIDT_IND_DATA__DIDT_IND_DATA_MASK                                                                     0xFFFFFFFFL
//DIDT_INDEX_AUTO_INCR_EN
#define DIDT_INDEX_AUTO_INCR_EN__DIDT_INDEX_AUTO_INCR_EN__SHIFT                                               0x0
#define DIDT_INDEX_AUTO_INCR_EN__DIDT_INDEX_AUTO_INCR_EN_MASK                                                 0x00000001L


// addressBlock: gc_gccacdec
//GC_CAC_CTRL_1
#define GC_CAC_CTRL_1__CAC_WINDOW__SHIFT                                                                      0x0
#define GC_CAC_CTRL_1__TDP_WINDOW__SHIFT                                                                      0x18
#define GC_CAC_CTRL_1__CAC_WINDOW_MASK                                                                        0x00FFFFFFL
#define GC_CAC_CTRL_1__TDP_WINDOW_MASK                                                                        0xFF000000L
//GC_CAC_CTRL_2
#define GC_CAC_CTRL_2__CAC_ENABLE__SHIFT                                                                      0x0
#define GC_CAC_CTRL_2__CAC_SOFT_CTRL_ENABLE__SHIFT                                                            0x1
#define GC_CAC_CTRL_2__GC_LCAC_ENABLE__SHIFT                                                                  0x2
#define GC_CAC_CTRL_2__SE_LCAC_ENABLE__SHIFT                                                                  0x3
#define GC_CAC_CTRL_2__GC_CAC_INDEX_AUTO_INCR_EN__SHIFT                                                       0x4
#define GC_CAC_CTRL_2__TOGGLE_EN__SHIFT                                                                       0x5
#define GC_CAC_CTRL_2__CAC_ENABLE_MASK                                                                        0x00000001L
#define GC_CAC_CTRL_2__CAC_SOFT_CTRL_ENABLE_MASK                                                              0x00000002L
#define GC_CAC_CTRL_2__GC_LCAC_ENABLE_MASK                                                                    0x00000004L
#define GC_CAC_CTRL_2__SE_LCAC_ENABLE_MASK                                                                    0x00000008L
#define GC_CAC_CTRL_2__GC_CAC_INDEX_AUTO_INCR_EN_MASK                                                         0x00000010L
#define GC_CAC_CTRL_2__TOGGLE_EN_MASK                                                                         0x00000020L
//GC_CAC_AGGR_LOWER
#define GC_CAC_AGGR_LOWER__AGGR_31_0__SHIFT                                                                   0x0
#define GC_CAC_AGGR_LOWER__AGGR_31_0_MASK                                                                     0xFFFFFFFFL
//GC_CAC_AGGR_UPPER
#define GC_CAC_AGGR_UPPER__AGGR_63_32__SHIFT                                                                  0x0
#define GC_CAC_AGGR_UPPER__AGGR_63_32_MASK                                                                    0xFFFFFFFFL
//GC_CAC_SOFT_CTRL
#define GC_CAC_SOFT_CTRL__SOFT_SNAP__SHIFT                                                                    0x0
#define GC_CAC_SOFT_CTRL__UNUSED__SHIFT                                                                       0x1
#define GC_CAC_SOFT_CTRL__SOFT_SNAP_MASK                                                                      0x00000001L
#define GC_CAC_SOFT_CTRL__UNUSED_MASK                                                                         0xFFFFFFFEL
//GC_EDC_CTRL
#define GC_EDC_CTRL__EDC_EN__SHIFT                                                                            0x0
#define GC_EDC_CTRL__EDC_SW_RST__SHIFT                                                                        0x1
#define GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT                                                               0x2
#define GC_EDC_CTRL__EDC_FORCE_STALL__SHIFT                                                                   0x3
#define GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT                                                       0x4
#define GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT                                                          0x9
#define GC_EDC_CTRL__EDC_THROTTLE_PATTERN_BIT_NUMS__SHIFT                                                     0xa
#define GC_EDC_CTRL__EDC_LEVEL_SEL__SHIFT                                                                     0xe
#define GC_EDC_CTRL__EDC_ALGORITHM_MODE__SHIFT                                                                0xf
#define GC_EDC_CTRL__EDC_AVGDIV__SHIFT                                                                        0x10
#define GC_EDC_CTRL__PSM_THROTTLE_SRC_SEL__SHIFT                                                              0x14
#define GC_EDC_CTRL__THROTTLE_SRC0_MASK__SHIFT                                                                0x17
#define GC_EDC_CTRL__THROTTLE_SRC1_MASK__SHIFT                                                                0x18
#define GC_EDC_CTRL__THROTTLE_SRC2_MASK__SHIFT                                                                0x19
#define GC_EDC_CTRL__THROTTLE_SRC3_MASK__SHIFT                                                                0x1a
#define GC_EDC_CTRL__EDC_EN_MASK                                                                              0x00000001L
#define GC_EDC_CTRL__EDC_SW_RST_MASK                                                                          0x00000002L
#define GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK                                                                 0x00000004L
#define GC_EDC_CTRL__EDC_FORCE_STALL_MASK                                                                     0x00000008L
#define GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK                                                         0x000001F0L
#define GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK                                                            0x00000200L
#define GC_EDC_CTRL__EDC_THROTTLE_PATTERN_BIT_NUMS_MASK                                                       0x00003C00L
#define GC_EDC_CTRL__EDC_LEVEL_SEL_MASK                                                                       0x00004000L
#define GC_EDC_CTRL__EDC_ALGORITHM_MODE_MASK                                                                  0x00008000L
#define GC_EDC_CTRL__EDC_AVGDIV_MASK                                                                          0x000F0000L
#define GC_EDC_CTRL__PSM_THROTTLE_SRC_SEL_MASK                                                                0x00700000L
#define GC_EDC_CTRL__THROTTLE_SRC0_MASK_MASK                                                                  0x00800000L
#define GC_EDC_CTRL__THROTTLE_SRC1_MASK_MASK                                                                  0x01000000L
#define GC_EDC_CTRL__THROTTLE_SRC2_MASK_MASK                                                                  0x02000000L
#define GC_EDC_CTRL__THROTTLE_SRC3_MASK_MASK                                                                  0x04000000L
//GC_EDC_THRESHOLD
#define GC_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT                                                                0x0
#define GC_EDC_THRESHOLD__EDC_THRESHOLD_MASK                                                                  0xFFFFFFFFL
//GC_EDC_STATUS
#define GC_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT                                                              0x0
#define GC_EDC_STATUS__GPIO_IN_0__SHIFT                                                                       0x3
#define GC_EDC_STATUS__GPIO_IN_1__SHIFT                                                                       0x4
#define GC_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK                                                                0x00000007L
#define GC_EDC_STATUS__GPIO_IN_0_MASK                                                                         0x00000008L
#define GC_EDC_STATUS__GPIO_IN_1_MASK                                                                         0x00000010L
//GC_EDC_OVERFLOW
#define GC_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT                                              0x0
#define GC_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT                                           0x1
#define GC_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK                                                0x00000001L
#define GC_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK                                             0x0001FFFEL
//GC_EDC_ROLLING_POWER_DELTA
#define GC_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT                                            0x0
#define GC_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK                                              0xFFFFFFFFL
//GC_THROTTLE_CTRL
#define GC_THROTTLE_CTRL__THROTTLE_CTRL_SW_RST__SHIFT                                                         0x0
#define GC_THROTTLE_CTRL__GC_EDC_STALL_EN__SHIFT                                                              0x1
#define GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT                                                              0x2
#define GC_THROTTLE_CTRL__PWRBRK_POLARITY_CNTL__SHIFT                                                         0x3
#define GC_THROTTLE_CTRL__PCC_STALL_EN__SHIFT                                                                 0x4
#define GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT                                                                 0x5
#define GC_THROTTLE_CTRL__GC_EDC_ONLY_MODE__SHIFT                                                             0x6
#define GC_THROTTLE_CTRL__GC_EDC_OVERRIDE__SHIFT                                                              0x7
#define GC_THROTTLE_CTRL__PCC_OVERRIDE__SHIFT                                                                 0x8
#define GC_THROTTLE_CTRL__PWRBRK_OVERRIDE__SHIFT                                                              0x9
#define GC_THROTTLE_CTRL__GC_EDC_PERF_COUNTER_EN__SHIFT                                                       0xa
#define GC_THROTTLE_CTRL__PCC_PERF_COUNTER_EN__SHIFT                                                          0xb
#define GC_THROTTLE_CTRL__PWRBRK_PERF_COUNTER_EN__SHIFT                                                       0xc
#define GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT                                                        0xd
#define GC_THROTTLE_CTRL__FIXED_PATTERN_PERF_COUNTER_EN__SHIFT                                                0x17
#define GC_THROTTLE_CTRL__FIXED_PATTERN_LOG_INDEX__SHIFT                                                      0x18
#define GC_THROTTLE_CTRL__LUT_HW_UPDATE__SHIFT                                                                0x1d
#define GC_THROTTLE_CTRL__THROTTLE_CTRL_CLK_EN_OVERRIDE__SHIFT                                                0x1e
#define GC_THROTTLE_CTRL__PCC_POLARITY_CNTL__SHIFT                                                            0x1f
#define GC_THROTTLE_CTRL__THROTTLE_CTRL_SW_RST_MASK                                                           0x00000001L
#define GC_THROTTLE_CTRL__GC_EDC_STALL_EN_MASK                                                                0x00000002L
#define GC_THROTTLE_CTRL__PWRBRK_STALL_EN_MASK                                                                0x00000004L
#define GC_THROTTLE_CTRL__PWRBRK_POLARITY_CNTL_MASK                                                           0x00000008L
#define GC_THROTTLE_CTRL__PCC_STALL_EN_MASK                                                                   0x00000010L
#define GC_THROTTLE_CTRL__PATTERN_MODE_MASK                                                                   0x00000020L
#define GC_THROTTLE_CTRL__GC_EDC_ONLY_MODE_MASK                                                               0x00000040L
#define GC_THROTTLE_CTRL__GC_EDC_OVERRIDE_MASK                                                                0x00000080L
#define GC_THROTTLE_CTRL__PCC_OVERRIDE_MASK                                                                   0x00000100L
#define GC_THROTTLE_CTRL__PWRBRK_OVERRIDE_MASK                                                                0x00000200L
#define GC_THROTTLE_CTRL__GC_EDC_PERF_COUNTER_EN_MASK                                                         0x00000400L
#define GC_THROTTLE_CTRL__PCC_PERF_COUNTER_EN_MASK                                                            0x00000800L
#define GC_THROTTLE_CTRL__PWRBRK_PERF_COUNTER_EN_MASK                                                         0x00001000L
#define GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL_MASK                                                          0x007FE000L
#define GC_THROTTLE_CTRL__FIXED_PATTERN_PERF_COUNTER_EN_MASK                                                  0x00800000L
#define GC_THROTTLE_CTRL__FIXED_PATTERN_LOG_INDEX_MASK                                                        0x1F000000L
#define GC_THROTTLE_CTRL__LUT_HW_UPDATE_MASK                                                                  0x20000000L
#define GC_THROTTLE_CTRL__THROTTLE_CTRL_CLK_EN_OVERRIDE_MASK                                                  0x40000000L
#define GC_THROTTLE_CTRL__PCC_POLARITY_CNTL_MASK                                                              0x80000000L
//GC_THROTTLE_CTRL1
#define GC_THROTTLE_CTRL1__PCC_FP_PROGRAM_STEP_EN__SHIFT                                                      0x0
#define GC_THROTTLE_CTRL1__PCC_PROGRAM_MIN_STEP__SHIFT                                                        0x1
#define GC_THROTTLE_CTRL1__PCC_PROGRAM_MAX_STEP__SHIFT                                                        0x5
#define GC_THROTTLE_CTRL1__PCC_PROGRAM_UPWARDS_STEP_SIZE__SHIFT                                               0xa
#define GC_THROTTLE_CTRL1__PWRBRK_FP_PROGRAM_STEP_EN__SHIFT                                                   0xd
#define GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_MIN_STEP__SHIFT                                                     0xe
#define GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_MAX_STEP__SHIFT                                                     0x12
#define GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_UPWARDS_STEP_SIZE__SHIFT                                            0x17
#define GC_THROTTLE_CTRL1__FIXED_PATTERN_SELECT__SHIFT                                                        0x1a
#define GC_THROTTLE_CTRL1__GC_EDC_STRETCH_PERF_COUNTER_EN__SHIFT                                              0x1e
#define GC_THROTTLE_CTRL1__GC_EDC_UNSTRETCH_PERF_COUNTER_EN__SHIFT                                            0x1f
#define GC_THROTTLE_CTRL1__PCC_FP_PROGRAM_STEP_EN_MASK                                                        0x00000001L
#define GC_THROTTLE_CTRL1__PCC_PROGRAM_MIN_STEP_MASK                                                          0x0000001EL
#define GC_THROTTLE_CTRL1__PCC_PROGRAM_MAX_STEP_MASK                                                          0x000003E0L
#define GC_THROTTLE_CTRL1__PCC_PROGRAM_UPWARDS_STEP_SIZE_MASK                                                 0x00001C00L
#define GC_THROTTLE_CTRL1__PWRBRK_FP_PROGRAM_STEP_EN_MASK                                                     0x00002000L
#define GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_MIN_STEP_MASK                                                       0x0003C000L
#define GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_MAX_STEP_MASK                                                       0x007C0000L
#define GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_UPWARDS_STEP_SIZE_MASK                                              0x03800000L
#define GC_THROTTLE_CTRL1__FIXED_PATTERN_SELECT_MASK                                                          0x0C000000L
#define GC_THROTTLE_CTRL1__GC_EDC_STRETCH_PERF_COUNTER_EN_MASK                                                0x40000000L
#define GC_THROTTLE_CTRL1__GC_EDC_UNSTRETCH_PERF_COUNTER_EN_MASK                                              0x80000000L
//GC_THROTTLE_STATUS
#define GC_THROTTLE_STATUS__FSM_STATE__SHIFT                                                                  0x0
#define GC_THROTTLE_STATUS__PATTERN_INDEX__SHIFT                                                              0x4
#define GC_THROTTLE_STATUS__FSM_STATE_MASK                                                                    0x0000000FL
#define GC_THROTTLE_STATUS__PATTERN_INDEX_MASK                                                                0x000003F0L
//EDC_PERF_COUNTER
#define EDC_PERF_COUNTER__EDC_PERF_COUNTER__SHIFT                                                             0x0
#define EDC_PERF_COUNTER__EDC_PERF_COUNTER_MASK                                                               0xFFFFFFFFL
//PCC_PERF_COUNTER
#define PCC_PERF_COUNTER__PCC_PERF_COUNTER__SHIFT                                                             0x0
#define PCC_PERF_COUNTER__PCC_PERF_COUNTER_MASK                                                               0xFFFFFFFFL
//PWRBRK_PERF_COUNTER
#define PWRBRK_PERF_COUNTER__PWRBRK_PERF_COUNTER__SHIFT                                                       0x0
#define PWRBRK_PERF_COUNTER__PWRBRK_PERF_COUNTER_MASK                                                         0xFFFFFFFFL
//GC_EDC_STRETCH_CTRL
#define GC_EDC_STRETCH_CTRL__EDC_STRETCH_EN__SHIFT                                                            0x0
#define GC_EDC_STRETCH_CTRL__EDC_STRETCH_DELAY__SHIFT                                                         0x1
#define GC_EDC_STRETCH_CTRL__EDC_UNSTRETCH_DELAY__SHIFT                                                       0xa
#define GC_EDC_STRETCH_CTRL__EDC_CLK_MONITOR_EN__SHIFT                                                        0x13
#define GC_EDC_STRETCH_CTRL__EDC_CLK_MONITOR_INTERVAL__SHIFT                                                  0x14
#define GC_EDC_STRETCH_CTRL__EDC_CLK_MONITOR_THRESHOLD__SHIFT                                                 0x18
#define GC_EDC_STRETCH_CTRL__EDC_STRETCH_EN_MASK                                                              0x00000001L
#define GC_EDC_STRETCH_CTRL__EDC_STRETCH_DELAY_MASK                                                           0x000003FEL
#define GC_EDC_STRETCH_CTRL__EDC_UNSTRETCH_DELAY_MASK                                                         0x0007FC00L
#define GC_EDC_STRETCH_CTRL__EDC_CLK_MONITOR_EN_MASK                                                          0x00080000L
#define GC_EDC_STRETCH_CTRL__EDC_CLK_MONITOR_INTERVAL_MASK                                                    0x00F00000L
#define GC_EDC_STRETCH_CTRL__EDC_CLK_MONITOR_THRESHOLD_MASK                                                   0xFF000000L
//GC_EDC_STRETCH_THRESHOLD
#define GC_EDC_STRETCH_THRESHOLD__EDC_STRETCH_THRESHOLD__SHIFT                                                0x0
#define GC_EDC_STRETCH_THRESHOLD__EDC_STRETCH_THRESHOLD_MASK                                                  0xFFFFFFFFL
//EDC_HYSTERESIS_CNTL
#define EDC_HYSTERESIS_CNTL__MAX_HYSTERESIS__SHIFT                                                            0x0
#define EDC_HYSTERESIS_CNTL__MAX_HYSTERESIS_MASK                                                              0x000000FFL
//EDC_HYSTERESIS_STAT
#define EDC_HYSTERESIS_STAT__HYSTERESIS_CNT__SHIFT                                                            0x0
#define EDC_HYSTERESIS_STAT__EDC_STATUS__SHIFT                                                                0x8
#define EDC_HYSTERESIS_STAT__HYSTERESIS_CNT_MASK                                                              0x000000FFL
#define EDC_HYSTERESIS_STAT__EDC_STATUS_MASK                                                                  0x00000100L
//GC_CAC_IND_INDEX
#define GC_CAC_IND_INDEX__GC_CAC_IND_ADDR__SHIFT                                                              0x0
#define GC_CAC_IND_INDEX__GC_CAC_IND_ADDR_MASK                                                                0xFFFFFFFFL
//GC_CAC_IND_DATA
#define GC_CAC_IND_DATA__GC_CAC_IND_DATA__SHIFT                                                               0x0
#define GC_CAC_IND_DATA__GC_CAC_IND_DATA_MASK                                                                 0xFFFFFFFFL
//SE_CAC_IND_INDEX
#define SE_CAC_IND_INDEX__SE_CAC_IND_ADDR__SHIFT                                                              0x0
#define SE_CAC_IND_INDEX__SE_CAC_IND_ADDR_MASK                                                                0xFFFFFFFFL
//SE_CAC_IND_DATA
#define SE_CAC_IND_DATA__SE_CAC_IND_DATA__SHIFT                                                               0x0
#define SE_CAC_IND_DATA__SE_CAC_IND_DATA_MASK                                                                 0xFFFFFFFFL


// addressBlock: gc_tcpdec
//TCP_WATCH0_ADDR_H
#define TCP_WATCH0_ADDR_H__ADDR__SHIFT                                                                        0x0
#define TCP_WATCH0_ADDR_H__ADDR_MASK                                                                          0x0000FFFFL
//TCP_WATCH0_ADDR_L
#define TCP_WATCH0_ADDR_L__ADDR__SHIFT                                                                        0x7
#define TCP_WATCH0_ADDR_L__ADDR_MASK                                                                          0xFFFFFF80L
//TCP_WATCH0_CNTL
#define TCP_WATCH0_CNTL__MASK__SHIFT                                                                          0x0
#define TCP_WATCH0_CNTL__VMID__SHIFT                                                                          0x18
#define TCP_WATCH0_CNTL__MODE__SHIFT                                                                          0x1d
#define TCP_WATCH0_CNTL__VALID__SHIFT                                                                         0x1f
#define TCP_WATCH0_CNTL__MASK_MASK                                                                            0x007FFFFFL
#define TCP_WATCH0_CNTL__VMID_MASK                                                                            0x0F000000L
#define TCP_WATCH0_CNTL__MODE_MASK                                                                            0x60000000L
#define TCP_WATCH0_CNTL__VALID_MASK                                                                           0x80000000L
//TCP_WATCH1_ADDR_H
#define TCP_WATCH1_ADDR_H__ADDR__SHIFT                                                                        0x0
#define TCP_WATCH1_ADDR_H__ADDR_MASK                                                                          0x0000FFFFL
//TCP_WATCH1_ADDR_L
#define TCP_WATCH1_ADDR_L__ADDR__SHIFT                                                                        0x7
#define TCP_WATCH1_ADDR_L__ADDR_MASK                                                                          0xFFFFFF80L
//TCP_WATCH1_CNTL
#define TCP_WATCH1_CNTL__MASK__SHIFT                                                                          0x0
#define TCP_WATCH1_CNTL__VMID__SHIFT                                                                          0x18
#define TCP_WATCH1_CNTL__MODE__SHIFT                                                                          0x1d
#define TCP_WATCH1_CNTL__VALID__SHIFT                                                                         0x1f
#define TCP_WATCH1_CNTL__MASK_MASK                                                                            0x007FFFFFL
#define TCP_WATCH1_CNTL__VMID_MASK                                                                            0x0F000000L
#define TCP_WATCH1_CNTL__MODE_MASK                                                                            0x60000000L
#define TCP_WATCH1_CNTL__VALID_MASK                                                                           0x80000000L
//TCP_WATCH2_ADDR_H
#define TCP_WATCH2_ADDR_H__ADDR__SHIFT                                                                        0x0
#define TCP_WATCH2_ADDR_H__ADDR_MASK                                                                          0x0000FFFFL
//TCP_WATCH2_ADDR_L
#define TCP_WATCH2_ADDR_L__ADDR__SHIFT                                                                        0x7
#define TCP_WATCH2_ADDR_L__ADDR_MASK                                                                          0xFFFFFF80L
//TCP_WATCH2_CNTL
#define TCP_WATCH2_CNTL__MASK__SHIFT                                                                          0x0
#define TCP_WATCH2_CNTL__VMID__SHIFT                                                                          0x18
#define TCP_WATCH2_CNTL__MODE__SHIFT                                                                          0x1d
#define TCP_WATCH2_CNTL__VALID__SHIFT                                                                         0x1f
#define TCP_WATCH2_CNTL__MASK_MASK                                                                            0x007FFFFFL
#define TCP_WATCH2_CNTL__VMID_MASK                                                                            0x0F000000L
#define TCP_WATCH2_CNTL__MODE_MASK                                                                            0x60000000L
#define TCP_WATCH2_CNTL__VALID_MASK                                                                           0x80000000L
//TCP_WATCH3_ADDR_H
#define TCP_WATCH3_ADDR_H__ADDR__SHIFT                                                                        0x0
#define TCP_WATCH3_ADDR_H__ADDR_MASK                                                                          0x0000FFFFL
//TCP_WATCH3_ADDR_L
#define TCP_WATCH3_ADDR_L__ADDR__SHIFT                                                                        0x7
#define TCP_WATCH3_ADDR_L__ADDR_MASK                                                                          0xFFFFFF80L
//TCP_WATCH3_CNTL
#define TCP_WATCH3_CNTL__MASK__SHIFT                                                                          0x0
#define TCP_WATCH3_CNTL__VMID__SHIFT                                                                          0x18
#define TCP_WATCH3_CNTL__MODE__SHIFT                                                                          0x1d
#define TCP_WATCH3_CNTL__VALID__SHIFT                                                                         0x1f
#define TCP_WATCH3_CNTL__MASK_MASK                                                                            0x007FFFFFL
#define TCP_WATCH3_CNTL__VMID_MASK                                                                            0x0F000000L
#define TCP_WATCH3_CNTL__MODE_MASK                                                                            0x60000000L
#define TCP_WATCH3_CNTL__VALID_MASK                                                                           0x80000000L
//TCP_PERFCOUNTER_FILTER
#define TCP_PERFCOUNTER_FILTER__BUFFER__SHIFT                                                                 0x0
#define TCP_PERFCOUNTER_FILTER__FLAT__SHIFT                                                                   0x1
#define TCP_PERFCOUNTER_FILTER__DIM__SHIFT                                                                    0x2
#define TCP_PERFCOUNTER_FILTER__DATA_FORMAT__SHIFT                                                            0x5
#define TCP_PERFCOUNTER_FILTER__NUM_FORMAT__SHIFT                                                             0xd
#define TCP_PERFCOUNTER_FILTER__SW_MODE__SHIFT                                                                0x11
#define TCP_PERFCOUNTER_FILTER__NUM_SAMPLES__SHIFT                                                            0x16
#define TCP_PERFCOUNTER_FILTER__OPCODE_TYPE__SHIFT                                                            0x18
#define TCP_PERFCOUNTER_FILTER__SLC__SHIFT                                                                    0x1b
#define TCP_PERFCOUNTER_FILTER__DLC__SHIFT                                                                    0x1c
#define TCP_PERFCOUNTER_FILTER__GLC__SHIFT                                                                    0x1d
#define TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE__SHIFT                                                     0x1e
#define TCP_PERFCOUNTER_FILTER__BUFFER_MASK                                                                   0x00000001L
#define TCP_PERFCOUNTER_FILTER__FLAT_MASK                                                                     0x00000002L
#define TCP_PERFCOUNTER_FILTER__DIM_MASK                                                                      0x0000001CL
#define TCP_PERFCOUNTER_FILTER__DATA_FORMAT_MASK                                                              0x00000FE0L
#define TCP_PERFCOUNTER_FILTER__NUM_FORMAT_MASK                                                               0x0001E000L
#define TCP_PERFCOUNTER_FILTER__SW_MODE_MASK                                                                  0x003E0000L
#define TCP_PERFCOUNTER_FILTER__NUM_SAMPLES_MASK                                                              0x00C00000L
#define TCP_PERFCOUNTER_FILTER__OPCODE_TYPE_MASK                                                              0x07000000L
#define TCP_PERFCOUNTER_FILTER__SLC_MASK                                                                      0x08000000L
#define TCP_PERFCOUNTER_FILTER__DLC_MASK                                                                      0x10000000L
#define TCP_PERFCOUNTER_FILTER__GLC_MASK                                                                      0x20000000L
#define TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE_MASK                                                       0x40000000L
//TCP_PERFCOUNTER_FILTER_EN
#define TCP_PERFCOUNTER_FILTER_EN__BUFFER__SHIFT                                                              0x0
#define TCP_PERFCOUNTER_FILTER_EN__FLAT__SHIFT                                                                0x1
#define TCP_PERFCOUNTER_FILTER_EN__DIM__SHIFT                                                                 0x2
#define TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT__SHIFT                                                         0x3
#define TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT__SHIFT                                                          0x4
#define TCP_PERFCOUNTER_FILTER_EN__SW_MODE__SHIFT                                                             0x5
#define TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES__SHIFT                                                         0x6
#define TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE__SHIFT                                                         0x7
#define TCP_PERFCOUNTER_FILTER_EN__SLC__SHIFT                                                                 0x8
#define TCP_PERFCOUNTER_FILTER_EN__DLC__SHIFT                                                                 0x9
#define TCP_PERFCOUNTER_FILTER_EN__GLC__SHIFT                                                                 0xa
#define TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE__SHIFT                                                  0xb
#define TCP_PERFCOUNTER_FILTER_EN__REQ_MODE__SHIFT                                                            0xc
#define TCP_PERFCOUNTER_FILTER_EN__BUFFER_MASK                                                                0x00000001L
#define TCP_PERFCOUNTER_FILTER_EN__FLAT_MASK                                                                  0x00000002L
#define TCP_PERFCOUNTER_FILTER_EN__DIM_MASK                                                                   0x00000004L
#define TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT_MASK                                                           0x00000008L
#define TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT_MASK                                                            0x00000010L
#define TCP_PERFCOUNTER_FILTER_EN__SW_MODE_MASK                                                               0x00000020L
#define TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES_MASK                                                           0x00000040L
#define TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE_MASK                                                           0x00000080L
#define TCP_PERFCOUNTER_FILTER_EN__SLC_MASK                                                                   0x00000100L
#define TCP_PERFCOUNTER_FILTER_EN__DLC_MASK                                                                   0x00000200L
#define TCP_PERFCOUNTER_FILTER_EN__GLC_MASK                                                                   0x00000400L
#define TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE_MASK                                                    0x00000800L
#define TCP_PERFCOUNTER_FILTER_EN__REQ_MODE_MASK                                                              0x00001000L
//TCP_PERFCOUNTER_FILTER2
#define TCP_PERFCOUNTER_FILTER2__REQ_MODE__SHIFT                                                              0x0
#define TCP_PERFCOUNTER_FILTER2__REQ_MODE_MASK                                                                0x00000007L


// addressBlock: gc_gdspdec
//GDS_VMID0_BASE
#define GDS_VMID0_BASE__BASE__SHIFT                                                                           0x0
#define GDS_VMID0_BASE__UNUSED__SHIFT                                                                         0x10
#define GDS_VMID0_BASE__BASE_MASK                                                                             0x0000FFFFL
#define GDS_VMID0_BASE__UNUSED_MASK                                                                           0xFFFF0000L
//GDS_VMID0_SIZE
#define GDS_VMID0_SIZE__SIZE__SHIFT                                                                           0x0
#define GDS_VMID0_SIZE__UNUSED__SHIFT                                                                         0x11
#define GDS_VMID0_SIZE__SIZE_MASK                                                                             0x0001FFFFL
#define GDS_VMID0_SIZE__UNUSED_MASK                                                                           0xFFFE0000L
//GDS_VMID1_BASE
#define GDS_VMID1_BASE__BASE__SHIFT                                                                           0x0
#define GDS_VMID1_BASE__UNUSED__SHIFT                                                                         0x10
#define GDS_VMID1_BASE__BASE_MASK                                                                             0x0000FFFFL
#define GDS_VMID1_BASE__UNUSED_MASK                                                                           0xFFFF0000L
//GDS_VMID1_SIZE
#define GDS_VMID1_SIZE__SIZE__SHIFT                                                                           0x0
#define GDS_VMID1_SIZE__UNUSED__SHIFT                                                                         0x11
#define GDS_VMID1_SIZE__SIZE_MASK                                                                             0x0001FFFFL
#define GDS_VMID1_SIZE__UNUSED_MASK                                                                           0xFFFE0000L
//GDS_VMID2_BASE
#define GDS_VMID2_BASE__BASE__SHIFT                                                                           0x0
#define GDS_VMID2_BASE__UNUSED__SHIFT                                                                         0x10
#define GDS_VMID2_BASE__BASE_MASK                                                                             0x0000FFFFL
#define GDS_VMID2_BASE__UNUSED_MASK                                                                           0xFFFF0000L
//GDS_VMID2_SIZE
#define GDS_VMID2_SIZE__SIZE__SHIFT                                                                           0x0
#define GDS_VMID2_SIZE__UNUSED__SHIFT                                                                         0x11
#define GDS_VMID2_SIZE__SIZE_MASK                                                                             0x0001FFFFL
#define GDS_VMID2_SIZE__UNUSED_MASK                                                                           0xFFFE0000L
//GDS_VMID3_BASE
#define GDS_VMID3_BASE__BASE__SHIFT                                                                           0x0
#define GDS_VMID3_BASE__UNUSED__SHIFT                                                                         0x10
#define GDS_VMID3_BASE__BASE_MASK                                                                             0x0000FFFFL
#define GDS_VMID3_BASE__UNUSED_MASK                                                                           0xFFFF0000L
//GDS_VMID3_SIZE
#define GDS_VMID3_SIZE__SIZE__SHIFT                                                                           0x0
#define GDS_VMID3_SIZE__UNUSED__SHIFT                                                                         0x11
#define GDS_VMID3_SIZE__SIZE_MASK                                                                             0x0001FFFFL
#define GDS_VMID3_SIZE__UNUSED_MASK                                                                           0xFFFE0000L
//GDS_VMID4_BASE
#define GDS_VMID4_BASE__BASE__SHIFT                                                                           0x0
#define GDS_VMID4_BASE__UNUSED__SHIFT                                                                         0x10
#define GDS_VMID4_BASE__BASE_MASK                                                                             0x0000FFFFL
#define GDS_VMID4_BASE__UNUSED_MASK                                                                           0xFFFF0000L
//GDS_VMID4_SIZE
#define GDS_VMID4_SIZE__SIZE__SHIFT                                                                           0x0
#define GDS_VMID4_SIZE__UNUSED__SHIFT                                                                         0x11
#define GDS_VMID4_SIZE__SIZE_MASK                                                                             0x0001FFFFL
#define GDS_VMID4_SIZE__UNUSED_MASK                                                                           0xFFFE0000L
//GDS_VMID5_BASE
#define GDS_VMID5_BASE__BASE__SHIFT                                                                           0x0
#define GDS_VMID5_BASE__UNUSED__SHIFT                                                                         0x10
#define GDS_VMID5_BASE__BASE_MASK                                                                             0x0000FFFFL
#define GDS_VMID5_BASE__UNUSED_MASK                                                                           0xFFFF0000L
//GDS_VMID5_SIZE
#define GDS_VMID5_SIZE__SIZE__SHIFT                                                                           0x0
#define GDS_VMID5_SIZE__UNUSED__SHIFT                                                                         0x11
#define GDS_VMID5_SIZE__SIZE_MASK                                                                             0x0001FFFFL
#define GDS_VMID5_SIZE__UNUSED_MASK                                                                           0xFFFE0000L
//GDS_VMID6_BASE
#define GDS_VMID6_BASE__BASE__SHIFT                                                                           0x0
#define GDS_VMID6_BASE__UNUSED__SHIFT                                                                         0x10
#define GDS_VMID6_BASE__BASE_MASK                                                                             0x0000FFFFL
#define GDS_VMID6_BASE__UNUSED_MASK                                                                           0xFFFF0000L
//GDS_VMID6_SIZE
#define GDS_VMID6_SIZE__SIZE__SHIFT                                                                           0x0
#define GDS_VMID6_SIZE__UNUSED__SHIFT                                                                         0x11
#define GDS_VMID6_SIZE__SIZE_MASK                                                                             0x0001FFFFL
#define GDS_VMID6_SIZE__UNUSED_MASK                                                                           0xFFFE0000L
//GDS_VMID7_BASE
#define GDS_VMID7_BASE__BASE__SHIFT                                                                           0x0
#define GDS_VMID7_BASE__UNUSED__SHIFT                                                                         0x10
#define GDS_VMID7_BASE__BASE_MASK                                                                             0x0000FFFFL
#define GDS_VMID7_BASE__UNUSED_MASK                                                                           0xFFFF0000L
//GDS_VMID7_SIZE
#define GDS_VMID7_SIZE__SIZE__SHIFT                                                                           0x0
#define GDS_VMID7_SIZE__UNUSED__SHIFT                                                                         0x11
#define GDS_VMID7_SIZE__SIZE_MASK                                                                             0x0001FFFFL
#define GDS_VMID7_SIZE__UNUSED_MASK                                                                           0xFFFE0000L
//GDS_VMID8_BASE
#define GDS_VMID8_BASE__BASE__SHIFT                                                                           0x0
#define GDS_VMID8_BASE__UNUSED__SHIFT                                                                         0x10
#define GDS_VMID8_BASE__BASE_MASK                                                                             0x0000FFFFL
#define GDS_VMID8_BASE__UNUSED_MASK                                                                           0xFFFF0000L
//GDS_VMID8_SIZE
#define GDS_VMID8_SIZE__SIZE__SHIFT                                                                           0x0
#define GDS_VMID8_SIZE__UNUSED__SHIFT                                                                         0x11
#define GDS_VMID8_SIZE__SIZE_MASK                                                                             0x0001FFFFL
#define GDS_VMID8_SIZE__UNUSED_MASK                                                                           0xFFFE0000L
//GDS_VMID9_BASE
#define GDS_VMID9_BASE__BASE__SHIFT                                                                           0x0
#define GDS_VMID9_BASE__UNUSED__SHIFT                                                                         0x10
#define GDS_VMID9_BASE__BASE_MASK                                                                             0x0000FFFFL
#define GDS_VMID9_BASE__UNUSED_MASK                                                                           0xFFFF0000L
//GDS_VMID9_SIZE
#define GDS_VMID9_SIZE__SIZE__SHIFT                                                                           0x0
#define GDS_VMID9_SIZE__UNUSED__SHIFT                                                                         0x11
#define GDS_VMID9_SIZE__SIZE_MASK                                                                             0x0001FFFFL
#define GDS_VMID9_SIZE__UNUSED_MASK                                                                           0xFFFE0000L
//GDS_VMID10_BASE
#define GDS_VMID10_BASE__BASE__SHIFT                                                                          0x0
#define GDS_VMID10_BASE__UNUSED__SHIFT                                                                        0x10
#define GDS_VMID10_BASE__BASE_MASK                                                                            0x0000FFFFL
#define GDS_VMID10_BASE__UNUSED_MASK                                                                          0xFFFF0000L
//GDS_VMID10_SIZE
#define GDS_VMID10_SIZE__SIZE__SHIFT                                                                          0x0
#define GDS_VMID10_SIZE__UNUSED__SHIFT                                                                        0x11
#define GDS_VMID10_SIZE__SIZE_MASK                                                                            0x0001FFFFL
#define GDS_VMID10_SIZE__UNUSED_MASK                                                                          0xFFFE0000L
//GDS_VMID11_BASE
#define GDS_VMID11_BASE__BASE__SHIFT                                                                          0x0
#define GDS_VMID11_BASE__UNUSED__SHIFT                                                                        0x10
#define GDS_VMID11_BASE__BASE_MASK                                                                            0x0000FFFFL
#define GDS_VMID11_BASE__UNUSED_MASK                                                                          0xFFFF0000L
//GDS_VMID11_SIZE
#define GDS_VMID11_SIZE__SIZE__SHIFT                                                                          0x0
#define GDS_VMID11_SIZE__UNUSED__SHIFT                                                                        0x11
#define GDS_VMID11_SIZE__SIZE_MASK                                                                            0x0001FFFFL
#define GDS_VMID11_SIZE__UNUSED_MASK                                                                          0xFFFE0000L
//GDS_VMID12_BASE
#define GDS_VMID12_BASE__BASE__SHIFT                                                                          0x0
#define GDS_VMID12_BASE__UNUSED__SHIFT                                                                        0x10
#define GDS_VMID12_BASE__BASE_MASK                                                                            0x0000FFFFL
#define GDS_VMID12_BASE__UNUSED_MASK                                                                          0xFFFF0000L
//GDS_VMID12_SIZE
#define GDS_VMID12_SIZE__SIZE__SHIFT                                                                          0x0
#define GDS_VMID12_SIZE__UNUSED__SHIFT                                                                        0x11
#define GDS_VMID12_SIZE__SIZE_MASK                                                                            0x0001FFFFL
#define GDS_VMID12_SIZE__UNUSED_MASK                                                                          0xFFFE0000L
//GDS_VMID13_BASE
#define GDS_VMID13_BASE__BASE__SHIFT                                                                          0x0
#define GDS_VMID13_BASE__UNUSED__SHIFT                                                                        0x10
#define GDS_VMID13_BASE__BASE_MASK                                                                            0x0000FFFFL
#define GDS_VMID13_BASE__UNUSED_MASK                                                                          0xFFFF0000L
//GDS_VMID13_SIZE
#define GDS_VMID13_SIZE__SIZE__SHIFT                                                                          0x0
#define GDS_VMID13_SIZE__UNUSED__SHIFT                                                                        0x11
#define GDS_VMID13_SIZE__SIZE_MASK                                                                            0x0001FFFFL
#define GDS_VMID13_SIZE__UNUSED_MASK                                                                          0xFFFE0000L
//GDS_VMID14_BASE
#define GDS_VMID14_BASE__BASE__SHIFT                                                                          0x0
#define GDS_VMID14_BASE__UNUSED__SHIFT                                                                        0x10
#define GDS_VMID14_BASE__BASE_MASK                                                                            0x0000FFFFL
#define GDS_VMID14_BASE__UNUSED_MASK                                                                          0xFFFF0000L
//GDS_VMID14_SIZE
#define GDS_VMID14_SIZE__SIZE__SHIFT                                                                          0x0
#define GDS_VMID14_SIZE__UNUSED__SHIFT                                                                        0x11
#define GDS_VMID14_SIZE__SIZE_MASK                                                                            0x0001FFFFL
#define GDS_VMID14_SIZE__UNUSED_MASK                                                                          0xFFFE0000L
//GDS_VMID15_BASE
#define GDS_VMID15_BASE__BASE__SHIFT                                                                          0x0
#define GDS_VMID15_BASE__UNUSED__SHIFT                                                                        0x10
#define GDS_VMID15_BASE__BASE_MASK                                                                            0x0000FFFFL
#define GDS_VMID15_BASE__UNUSED_MASK                                                                          0xFFFF0000L
//GDS_VMID15_SIZE
#define GDS_VMID15_SIZE__SIZE__SHIFT                                                                          0x0
#define GDS_VMID15_SIZE__UNUSED__SHIFT                                                                        0x11
#define GDS_VMID15_SIZE__SIZE_MASK                                                                            0x0001FFFFL
#define GDS_VMID15_SIZE__UNUSED_MASK                                                                          0xFFFE0000L
//GDS_GWS_VMID0
#define GDS_GWS_VMID0__BASE__SHIFT                                                                            0x0
#define GDS_GWS_VMID0__UNUSED1__SHIFT                                                                         0x6
#define GDS_GWS_VMID0__SIZE__SHIFT                                                                            0x10
#define GDS_GWS_VMID0__UNUSED2__SHIFT                                                                         0x17
#define GDS_GWS_VMID0__BASE_MASK                                                                              0x0000003FL
#define GDS_GWS_VMID0__UNUSED1_MASK                                                                           0x0000FFC0L
#define GDS_GWS_VMID0__SIZE_MASK                                                                              0x007F0000L
#define GDS_GWS_VMID0__UNUSED2_MASK                                                                           0xFF800000L
//GDS_GWS_VMID1
#define GDS_GWS_VMID1__BASE__SHIFT                                                                            0x0
#define GDS_GWS_VMID1__UNUSED1__SHIFT                                                                         0x6
#define GDS_GWS_VMID1__SIZE__SHIFT                                                                            0x10
#define GDS_GWS_VMID1__UNUSED2__SHIFT                                                                         0x17
#define GDS_GWS_VMID1__BASE_MASK                                                                              0x0000003FL
#define GDS_GWS_VMID1__UNUSED1_MASK                                                                           0x0000FFC0L
#define GDS_GWS_VMID1__SIZE_MASK                                                                              0x007F0000L
#define GDS_GWS_VMID1__UNUSED2_MASK                                                                           0xFF800000L
//GDS_GWS_VMID2
#define GDS_GWS_VMID2__BASE__SHIFT                                                                            0x0
#define GDS_GWS_VMID2__UNUSED1__SHIFT                                                                         0x6
#define GDS_GWS_VMID2__SIZE__SHIFT                                                                            0x10
#define GDS_GWS_VMID2__UNUSED2__SHIFT                                                                         0x17
#define GDS_GWS_VMID2__BASE_MASK                                                                              0x0000003FL
#define GDS_GWS_VMID2__UNUSED1_MASK                                                                           0x0000FFC0L
#define GDS_GWS_VMID2__SIZE_MASK                                                                              0x007F0000L
#define GDS_GWS_VMID2__UNUSED2_MASK                                                                           0xFF800000L
//GDS_GWS_VMID3
#define GDS_GWS_VMID3__BASE__SHIFT                                                                            0x0
#define GDS_GWS_VMID3__UNUSED1__SHIFT                                                                         0x6
#define GDS_GWS_VMID3__SIZE__SHIFT                                                                            0x10
#define GDS_GWS_VMID3__UNUSED2__SHIFT                                                                         0x17
#define GDS_GWS_VMID3__BASE_MASK                                                                              0x0000003FL
#define GDS_GWS_VMID3__UNUSED1_MASK                                                                           0x0000FFC0L
#define GDS_GWS_VMID3__SIZE_MASK                                                                              0x007F0000L
#define GDS_GWS_VMID3__UNUSED2_MASK                                                                           0xFF800000L
//GDS_GWS_VMID4
#define GDS_GWS_VMID4__BASE__SHIFT                                                                            0x0
#define GDS_GWS_VMID4__UNUSED1__SHIFT                                                                         0x6
#define GDS_GWS_VMID4__SIZE__SHIFT                                                                            0x10
#define GDS_GWS_VMID4__UNUSED2__SHIFT                                                                         0x17
#define GDS_GWS_VMID4__BASE_MASK                                                                              0x0000003FL
#define GDS_GWS_VMID4__UNUSED1_MASK                                                                           0x0000FFC0L
#define GDS_GWS_VMID4__SIZE_MASK                                                                              0x007F0000L
#define GDS_GWS_VMID4__UNUSED2_MASK                                                                           0xFF800000L
//GDS_GWS_VMID5
#define GDS_GWS_VMID5__BASE__SHIFT                                                                            0x0
#define GDS_GWS_VMID5__UNUSED1__SHIFT                                                                         0x6
#define GDS_GWS_VMID5__SIZE__SHIFT                                                                            0x10
#define GDS_GWS_VMID5__UNUSED2__SHIFT                                                                         0x17
#define GDS_GWS_VMID5__BASE_MASK                                                                              0x0000003FL
#define GDS_GWS_VMID5__UNUSED1_MASK                                                                           0x0000FFC0L
#define GDS_GWS_VMID5__SIZE_MASK                                                                              0x007F0000L
#define GDS_GWS_VMID5__UNUSED2_MASK                                                                           0xFF800000L
//GDS_GWS_VMID6
#define GDS_GWS_VMID6__BASE__SHIFT                                                                            0x0
#define GDS_GWS_VMID6__UNUSED1__SHIFT                                                                         0x6
#define GDS_GWS_VMID6__SIZE__SHIFT                                                                            0x10
#define GDS_GWS_VMID6__UNUSED2__SHIFT                                                                         0x17
#define GDS_GWS_VMID6__BASE_MASK                                                                              0x0000003FL
#define GDS_GWS_VMID6__UNUSED1_MASK                                                                           0x0000FFC0L
#define GDS_GWS_VMID6__SIZE_MASK                                                                              0x007F0000L
#define GDS_GWS_VMID6__UNUSED2_MASK                                                                           0xFF800000L
//GDS_GWS_VMID7
#define GDS_GWS_VMID7__BASE__SHIFT                                                                            0x0
#define GDS_GWS_VMID7__UNUSED1__SHIFT                                                                         0x6
#define GDS_GWS_VMID7__SIZE__SHIFT                                                                            0x10
#define GDS_GWS_VMID7__UNUSED2__SHIFT                                                                         0x17
#define GDS_GWS_VMID7__BASE_MASK                                                                              0x0000003FL
#define GDS_GWS_VMID7__UNUSED1_MASK                                                                           0x0000FFC0L
#define GDS_GWS_VMID7__SIZE_MASK                                                                              0x007F0000L
#define GDS_GWS_VMID7__UNUSED2_MASK                                                                           0xFF800000L
//GDS_GWS_VMID8
#define GDS_GWS_VMID8__BASE__SHIFT                                                                            0x0
#define GDS_GWS_VMID8__UNUSED1__SHIFT                                                                         0x6
#define GDS_GWS_VMID8__SIZE__SHIFT                                                                            0x10
#define GDS_GWS_VMID8__UNUSED2__SHIFT                                                                         0x17
#define GDS_GWS_VMID8__BASE_MASK                                                                              0x0000003FL
#define GDS_GWS_VMID8__UNUSED1_MASK                                                                           0x0000FFC0L
#define GDS_GWS_VMID8__SIZE_MASK                                                                              0x007F0000L
#define GDS_GWS_VMID8__UNUSED2_MASK                                                                           0xFF800000L
//GDS_GWS_VMID9
#define GDS_GWS_VMID9__BASE__SHIFT                                                                            0x0
#define GDS_GWS_VMID9__UNUSED1__SHIFT                                                                         0x6
#define GDS_GWS_VMID9__SIZE__SHIFT                                                                            0x10
#define GDS_GWS_VMID9__UNUSED2__SHIFT                                                                         0x17
#define GDS_GWS_VMID9__BASE_MASK                                                                              0x0000003FL
#define GDS_GWS_VMID9__UNUSED1_MASK                                                                           0x0000FFC0L
#define GDS_GWS_VMID9__SIZE_MASK                                                                              0x007F0000L
#define GDS_GWS_VMID9__UNUSED2_MASK                                                                           0xFF800000L
//GDS_GWS_VMID10
#define GDS_GWS_VMID10__BASE__SHIFT                                                                           0x0
#define GDS_GWS_VMID10__UNUSED1__SHIFT                                                                        0x6
#define GDS_GWS_VMID10__SIZE__SHIFT                                                                           0x10
#define GDS_GWS_VMID10__UNUSED2__SHIFT                                                                        0x17
#define GDS_GWS_VMID10__BASE_MASK                                                                             0x0000003FL
#define GDS_GWS_VMID10__UNUSED1_MASK                                                                          0x0000FFC0L
#define GDS_GWS_VMID10__SIZE_MASK                                                                             0x007F0000L
#define GDS_GWS_VMID10__UNUSED2_MASK                                                                          0xFF800000L
//GDS_GWS_VMID11
#define GDS_GWS_VMID11__BASE__SHIFT                                                                           0x0
#define GDS_GWS_VMID11__UNUSED1__SHIFT                                                                        0x6
#define GDS_GWS_VMID11__SIZE__SHIFT                                                                           0x10
#define GDS_GWS_VMID11__UNUSED2__SHIFT                                                                        0x17
#define GDS_GWS_VMID11__BASE_MASK                                                                             0x0000003FL
#define GDS_GWS_VMID11__UNUSED1_MASK                                                                          0x0000FFC0L
#define GDS_GWS_VMID11__SIZE_MASK                                                                             0x007F0000L
#define GDS_GWS_VMID11__UNUSED2_MASK                                                                          0xFF800000L
//GDS_GWS_VMID12
#define GDS_GWS_VMID12__BASE__SHIFT                                                                           0x0
#define GDS_GWS_VMID12__UNUSED1__SHIFT                                                                        0x6
#define GDS_GWS_VMID12__SIZE__SHIFT                                                                           0x10
#define GDS_GWS_VMID12__UNUSED2__SHIFT                                                                        0x17
#define GDS_GWS_VMID12__BASE_MASK                                                                             0x0000003FL
#define GDS_GWS_VMID12__UNUSED1_MASK                                                                          0x0000FFC0L
#define GDS_GWS_VMID12__SIZE_MASK                                                                             0x007F0000L
#define GDS_GWS_VMID12__UNUSED2_MASK                                                                          0xFF800000L
//GDS_GWS_VMID13
#define GDS_GWS_VMID13__BASE__SHIFT                                                                           0x0
#define GDS_GWS_VMID13__UNUSED1__SHIFT                                                                        0x6
#define GDS_GWS_VMID13__SIZE__SHIFT                                                                           0x10
#define GDS_GWS_VMID13__UNUSED2__SHIFT                                                                        0x17
#define GDS_GWS_VMID13__BASE_MASK                                                                             0x0000003FL
#define GDS_GWS_VMID13__UNUSED1_MASK                                                                          0x0000FFC0L
#define GDS_GWS_VMID13__SIZE_MASK                                                                             0x007F0000L
#define GDS_GWS_VMID13__UNUSED2_MASK                                                                          0xFF800000L
//GDS_GWS_VMID14
#define GDS_GWS_VMID14__BASE__SHIFT                                                                           0x0
#define GDS_GWS_VMID14__UNUSED1__SHIFT                                                                        0x6
#define GDS_GWS_VMID14__SIZE__SHIFT                                                                           0x10
#define GDS_GWS_VMID14__UNUSED2__SHIFT                                                                        0x17
#define GDS_GWS_VMID14__BASE_MASK                                                                             0x0000003FL
#define GDS_GWS_VMID14__UNUSED1_MASK                                                                          0x0000FFC0L
#define GDS_GWS_VMID14__SIZE_MASK                                                                             0x007F0000L
#define GDS_GWS_VMID14__UNUSED2_MASK                                                                          0xFF800000L
//GDS_GWS_VMID15
#define GDS_GWS_VMID15__BASE__SHIFT                                                                           0x0
#define GDS_GWS_VMID15__UNUSED1__SHIFT                                                                        0x6
#define GDS_GWS_VMID15__SIZE__SHIFT                                                                           0x10
#define GDS_GWS_VMID15__UNUSED2__SHIFT                                                                        0x17
#define GDS_GWS_VMID15__BASE_MASK                                                                             0x0000003FL
#define GDS_GWS_VMID15__UNUSED1_MASK                                                                          0x0000FFC0L
#define GDS_GWS_VMID15__SIZE_MASK                                                                             0x007F0000L
#define GDS_GWS_VMID15__UNUSED2_MASK                                                                          0xFF800000L
//GDS_OA_VMID0
#define GDS_OA_VMID0__MASK__SHIFT                                                                             0x0
#define GDS_OA_VMID0__UNUSED__SHIFT                                                                           0x10
#define GDS_OA_VMID0__MASK_MASK                                                                               0x0000FFFFL
#define GDS_OA_VMID0__UNUSED_MASK                                                                             0xFFFF0000L
//GDS_OA_VMID1
#define GDS_OA_VMID1__MASK__SHIFT                                                                             0x0
#define GDS_OA_VMID1__UNUSED__SHIFT                                                                           0x10
#define GDS_OA_VMID1__MASK_MASK                                                                               0x0000FFFFL
#define GDS_OA_VMID1__UNUSED_MASK                                                                             0xFFFF0000L
//GDS_OA_VMID2
#define GDS_OA_VMID2__MASK__SHIFT                                                                             0x0
#define GDS_OA_VMID2__UNUSED__SHIFT                                                                           0x10
#define GDS_OA_VMID2__MASK_MASK                                                                               0x0000FFFFL
#define GDS_OA_VMID2__UNUSED_MASK                                                                             0xFFFF0000L
//GDS_OA_VMID3
#define GDS_OA_VMID3__MASK__SHIFT                                                                             0x0
#define GDS_OA_VMID3__UNUSED__SHIFT                                                                           0x10
#define GDS_OA_VMID3__MASK_MASK                                                                               0x0000FFFFL
#define GDS_OA_VMID3__UNUSED_MASK                                                                             0xFFFF0000L
//GDS_OA_VMID4
#define GDS_OA_VMID4__MASK__SHIFT                                                                             0x0
#define GDS_OA_VMID4__UNUSED__SHIFT                                                                           0x10
#define GDS_OA_VMID4__MASK_MASK                                                                               0x0000FFFFL
#define GDS_OA_VMID4__UNUSED_MASK                                                                             0xFFFF0000L
//GDS_OA_VMID5
#define GDS_OA_VMID5__MASK__SHIFT                                                                             0x0
#define GDS_OA_VMID5__UNUSED__SHIFT                                                                           0x10
#define GDS_OA_VMID5__MASK_MASK                                                                               0x0000FFFFL
#define GDS_OA_VMID5__UNUSED_MASK                                                                             0xFFFF0000L
//GDS_OA_VMID6
#define GDS_OA_VMID6__MASK__SHIFT                                                                             0x0
#define GDS_OA_VMID6__UNUSED__SHIFT                                                                           0x10
#define GDS_OA_VMID6__MASK_MASK                                                                               0x0000FFFFL
#define GDS_OA_VMID6__UNUSED_MASK                                                                             0xFFFF0000L
//GDS_OA_VMID7
#define GDS_OA_VMID7__MASK__SHIFT                                                                             0x0
#define GDS_OA_VMID7__UNUSED__SHIFT                                                                           0x10
#define GDS_OA_VMID7__MASK_MASK                                                                               0x0000FFFFL
#define GDS_OA_VMID7__UNUSED_MASK                                                                             0xFFFF0000L
//GDS_OA_VMID8
#define GDS_OA_VMID8__MASK__SHIFT                                                                             0x0
#define GDS_OA_VMID8__UNUSED__SHIFT                                                                           0x10
#define GDS_OA_VMID8__MASK_MASK                                                                               0x0000FFFFL
#define GDS_OA_VMID8__UNUSED_MASK                                                                             0xFFFF0000L
//GDS_OA_VMID9
#define GDS_OA_VMID9__MASK__SHIFT                                                                             0x0
#define GDS_OA_VMID9__UNUSED__SHIFT                                                                           0x10
#define GDS_OA_VMID9__MASK_MASK                                                                               0x0000FFFFL
#define GDS_OA_VMID9__UNUSED_MASK                                                                             0xFFFF0000L
//GDS_OA_VMID10
#define GDS_OA_VMID10__MASK__SHIFT                                                                            0x0
#define GDS_OA_VMID10__UNUSED__SHIFT                                                                          0x10
#define GDS_OA_VMID10__MASK_MASK                                                                              0x0000FFFFL
#define GDS_OA_VMID10__UNUSED_MASK                                                                            0xFFFF0000L
//GDS_OA_VMID11
#define GDS_OA_VMID11__MASK__SHIFT                                                                            0x0
#define GDS_OA_VMID11__UNUSED__SHIFT                                                                          0x10
#define GDS_OA_VMID11__MASK_MASK                                                                              0x0000FFFFL
#define GDS_OA_VMID11__UNUSED_MASK                                                                            0xFFFF0000L
//GDS_OA_VMID12
#define GDS_OA_VMID12__MASK__SHIFT                                                                            0x0
#define GDS_OA_VMID12__UNUSED__SHIFT                                                                          0x10
#define GDS_OA_VMID12__MASK_MASK                                                                              0x0000FFFFL
#define GDS_OA_VMID12__UNUSED_MASK                                                                            0xFFFF0000L
//GDS_OA_VMID13
#define GDS_OA_VMID13__MASK__SHIFT                                                                            0x0
#define GDS_OA_VMID13__UNUSED__SHIFT                                                                          0x10
#define GDS_OA_VMID13__MASK_MASK                                                                              0x0000FFFFL
#define GDS_OA_VMID13__UNUSED_MASK                                                                            0xFFFF0000L
//GDS_OA_VMID14
#define GDS_OA_VMID14__MASK__SHIFT                                                                            0x0
#define GDS_OA_VMID14__UNUSED__SHIFT                                                                          0x10
#define GDS_OA_VMID14__MASK_MASK                                                                              0x0000FFFFL
#define GDS_OA_VMID14__UNUSED_MASK                                                                            0xFFFF0000L
//GDS_OA_VMID15
#define GDS_OA_VMID15__MASK__SHIFT                                                                            0x0
#define GDS_OA_VMID15__UNUSED__SHIFT                                                                          0x10
#define GDS_OA_VMID15__MASK_MASK                                                                              0x0000FFFFL
#define GDS_OA_VMID15__UNUSED_MASK                                                                            0xFFFF0000L
//GDS_GWS_RESET0
#define GDS_GWS_RESET0__RESOURCE0_RESET__SHIFT                                                                0x0
#define GDS_GWS_RESET0__RESOURCE1_RESET__SHIFT                                                                0x1
#define GDS_GWS_RESET0__RESOURCE2_RESET__SHIFT                                                                0x2
#define GDS_GWS_RESET0__RESOURCE3_RESET__SHIFT                                                                0x3
#define GDS_GWS_RESET0__RESOURCE4_RESET__SHIFT                                                                0x4
#define GDS_GWS_RESET0__RESOURCE5_RESET__SHIFT                                                                0x5
#define GDS_GWS_RESET0__RESOURCE6_RESET__SHIFT                                                                0x6
#define GDS_GWS_RESET0__RESOURCE7_RESET__SHIFT                                                                0x7
#define GDS_GWS_RESET0__RESOURCE8_RESET__SHIFT                                                                0x8
#define GDS_GWS_RESET0__RESOURCE9_RESET__SHIFT                                                                0x9
#define GDS_GWS_RESET0__RESOURCE10_RESET__SHIFT                                                               0xa
#define GDS_GWS_RESET0__RESOURCE11_RESET__SHIFT                                                               0xb
#define GDS_GWS_RESET0__RESOURCE12_RESET__SHIFT                                                               0xc
#define GDS_GWS_RESET0__RESOURCE13_RESET__SHIFT                                                               0xd
#define GDS_GWS_RESET0__RESOURCE14_RESET__SHIFT                                                               0xe
#define GDS_GWS_RESET0__RESOURCE15_RESET__SHIFT                                                               0xf
#define GDS_GWS_RESET0__RESOURCE16_RESET__SHIFT                                                               0x10
#define GDS_GWS_RESET0__RESOURCE17_RESET__SHIFT                                                               0x11
#define GDS_GWS_RESET0__RESOURCE18_RESET__SHIFT                                                               0x12
#define GDS_GWS_RESET0__RESOURCE19_RESET__SHIFT                                                               0x13
#define GDS_GWS_RESET0__RESOURCE20_RESET__SHIFT                                                               0x14
#define GDS_GWS_RESET0__RESOURCE21_RESET__SHIFT                                                               0x15
#define GDS_GWS_RESET0__RESOURCE22_RESET__SHIFT                                                               0x16
#define GDS_GWS_RESET0__RESOURCE23_RESET__SHIFT                                                               0x17
#define GDS_GWS_RESET0__RESOURCE24_RESET__SHIFT                                                               0x18
#define GDS_GWS_RESET0__RESOURCE25_RESET__SHIFT                                                               0x19
#define GDS_GWS_RESET0__RESOURCE26_RESET__SHIFT                                                               0x1a
#define GDS_GWS_RESET0__RESOURCE27_RESET__SHIFT                                                               0x1b
#define GDS_GWS_RESET0__RESOURCE28_RESET__SHIFT                                                               0x1c
#define GDS_GWS_RESET0__RESOURCE29_RESET__SHIFT                                                               0x1d
#define GDS_GWS_RESET0__RESOURCE30_RESET__SHIFT                                                               0x1e
#define GDS_GWS_RESET0__RESOURCE31_RESET__SHIFT                                                               0x1f
#define GDS_GWS_RESET0__RESOURCE0_RESET_MASK                                                                  0x00000001L
#define GDS_GWS_RESET0__RESOURCE1_RESET_MASK                                                                  0x00000002L
#define GDS_GWS_RESET0__RESOURCE2_RESET_MASK                                                                  0x00000004L
#define GDS_GWS_RESET0__RESOURCE3_RESET_MASK                                                                  0x00000008L
#define GDS_GWS_RESET0__RESOURCE4_RESET_MASK                                                                  0x00000010L
#define GDS_GWS_RESET0__RESOURCE5_RESET_MASK                                                                  0x00000020L
#define GDS_GWS_RESET0__RESOURCE6_RESET_MASK                                                                  0x00000040L
#define GDS_GWS_RESET0__RESOURCE7_RESET_MASK                                                                  0x00000080L
#define GDS_GWS_RESET0__RESOURCE8_RESET_MASK                                                                  0x00000100L
#define GDS_GWS_RESET0__RESOURCE9_RESET_MASK                                                                  0x00000200L
#define GDS_GWS_RESET0__RESOURCE10_RESET_MASK                                                                 0x00000400L
#define GDS_GWS_RESET0__RESOURCE11_RESET_MASK                                                                 0x00000800L
#define GDS_GWS_RESET0__RESOURCE12_RESET_MASK                                                                 0x00001000L
#define GDS_GWS_RESET0__RESOURCE13_RESET_MASK                                                                 0x00002000L
#define GDS_GWS_RESET0__RESOURCE14_RESET_MASK                                                                 0x00004000L
#define GDS_GWS_RESET0__RESOURCE15_RESET_MASK                                                                 0x00008000L
#define GDS_GWS_RESET0__RESOURCE16_RESET_MASK                                                                 0x00010000L
#define GDS_GWS_RESET0__RESOURCE17_RESET_MASK                                                                 0x00020000L
#define GDS_GWS_RESET0__RESOURCE18_RESET_MASK                                                                 0x00040000L
#define GDS_GWS_RESET0__RESOURCE19_RESET_MASK                                                                 0x00080000L
#define GDS_GWS_RESET0__RESOURCE20_RESET_MASK                                                                 0x00100000L
#define GDS_GWS_RESET0__RESOURCE21_RESET_MASK                                                                 0x00200000L
#define GDS_GWS_RESET0__RESOURCE22_RESET_MASK                                                                 0x00400000L
#define GDS_GWS_RESET0__RESOURCE23_RESET_MASK                                                                 0x00800000L
#define GDS_GWS_RESET0__RESOURCE24_RESET_MASK                                                                 0x01000000L
#define GDS_GWS_RESET0__RESOURCE25_RESET_MASK                                                                 0x02000000L
#define GDS_GWS_RESET0__RESOURCE26_RESET_MASK                                                                 0x04000000L
#define GDS_GWS_RESET0__RESOURCE27_RESET_MASK                                                                 0x08000000L
#define GDS_GWS_RESET0__RESOURCE28_RESET_MASK                                                                 0x10000000L
#define GDS_GWS_RESET0__RESOURCE29_RESET_MASK                                                                 0x20000000L
#define GDS_GWS_RESET0__RESOURCE30_RESET_MASK                                                                 0x40000000L
#define GDS_GWS_RESET0__RESOURCE31_RESET_MASK                                                                 0x80000000L
//GDS_GWS_RESET1
#define GDS_GWS_RESET1__RESOURCE32_RESET__SHIFT                                                               0x0
#define GDS_GWS_RESET1__RESOURCE33_RESET__SHIFT                                                               0x1
#define GDS_GWS_RESET1__RESOURCE34_RESET__SHIFT                                                               0x2
#define GDS_GWS_RESET1__RESOURCE35_RESET__SHIFT                                                               0x3
#define GDS_GWS_RESET1__RESOURCE36_RESET__SHIFT                                                               0x4
#define GDS_GWS_RESET1__RESOURCE37_RESET__SHIFT                                                               0x5
#define GDS_GWS_RESET1__RESOURCE38_RESET__SHIFT                                                               0x6
#define GDS_GWS_RESET1__RESOURCE39_RESET__SHIFT                                                               0x7
#define GDS_GWS_RESET1__RESOURCE40_RESET__SHIFT                                                               0x8
#define GDS_GWS_RESET1__RESOURCE41_RESET__SHIFT                                                               0x9
#define GDS_GWS_RESET1__RESOURCE42_RESET__SHIFT                                                               0xa
#define GDS_GWS_RESET1__RESOURCE43_RESET__SHIFT                                                               0xb
#define GDS_GWS_RESET1__RESOURCE44_RESET__SHIFT                                                               0xc
#define GDS_GWS_RESET1__RESOURCE45_RESET__SHIFT                                                               0xd
#define GDS_GWS_RESET1__RESOURCE46_RESET__SHIFT                                                               0xe
#define GDS_GWS_RESET1__RESOURCE47_RESET__SHIFT                                                               0xf
#define GDS_GWS_RESET1__RESOURCE48_RESET__SHIFT                                                               0x10
#define GDS_GWS_RESET1__RESOURCE49_RESET__SHIFT                                                               0x11
#define GDS_GWS_RESET1__RESOURCE50_RESET__SHIFT                                                               0x12
#define GDS_GWS_RESET1__RESOURCE51_RESET__SHIFT                                                               0x13
#define GDS_GWS_RESET1__RESOURCE52_RESET__SHIFT                                                               0x14
#define GDS_GWS_RESET1__RESOURCE53_RESET__SHIFT                                                               0x15
#define GDS_GWS_RESET1__RESOURCE54_RESET__SHIFT                                                               0x16
#define GDS_GWS_RESET1__RESOURCE55_RESET__SHIFT                                                               0x17
#define GDS_GWS_RESET1__RESOURCE56_RESET__SHIFT                                                               0x18
#define GDS_GWS_RESET1__RESOURCE57_RESET__SHIFT                                                               0x19
#define GDS_GWS_RESET1__RESOURCE58_RESET__SHIFT                                                               0x1a
#define GDS_GWS_RESET1__RESOURCE59_RESET__SHIFT                                                               0x1b
#define GDS_GWS_RESET1__RESOURCE60_RESET__SHIFT                                                               0x1c
#define GDS_GWS_RESET1__RESOURCE61_RESET__SHIFT                                                               0x1d
#define GDS_GWS_RESET1__RESOURCE62_RESET__SHIFT                                                               0x1e
#define GDS_GWS_RESET1__RESOURCE63_RESET__SHIFT                                                               0x1f
#define GDS_GWS_RESET1__RESOURCE32_RESET_MASK                                                                 0x00000001L
#define GDS_GWS_RESET1__RESOURCE33_RESET_MASK                                                                 0x00000002L
#define GDS_GWS_RESET1__RESOURCE34_RESET_MASK                                                                 0x00000004L
#define GDS_GWS_RESET1__RESOURCE35_RESET_MASK                                                                 0x00000008L
#define GDS_GWS_RESET1__RESOURCE36_RESET_MASK                                                                 0x00000010L
#define GDS_GWS_RESET1__RESOURCE37_RESET_MASK                                                                 0x00000020L
#define GDS_GWS_RESET1__RESOURCE38_RESET_MASK                                                                 0x00000040L
#define GDS_GWS_RESET1__RESOURCE39_RESET_MASK                                                                 0x00000080L
#define GDS_GWS_RESET1__RESOURCE40_RESET_MASK                                                                 0x00000100L
#define GDS_GWS_RESET1__RESOURCE41_RESET_MASK                                                                 0x00000200L
#define GDS_GWS_RESET1__RESOURCE42_RESET_MASK                                                                 0x00000400L
#define GDS_GWS_RESET1__RESOURCE43_RESET_MASK                                                                 0x00000800L
#define GDS_GWS_RESET1__RESOURCE44_RESET_MASK                                                                 0x00001000L
#define GDS_GWS_RESET1__RESOURCE45_RESET_MASK                                                                 0x00002000L
#define GDS_GWS_RESET1__RESOURCE46_RESET_MASK                                                                 0x00004000L
#define GDS_GWS_RESET1__RESOURCE47_RESET_MASK                                                                 0x00008000L
#define GDS_GWS_RESET1__RESOURCE48_RESET_MASK                                                                 0x00010000L
#define GDS_GWS_RESET1__RESOURCE49_RESET_MASK                                                                 0x00020000L
#define GDS_GWS_RESET1__RESOURCE50_RESET_MASK                                                                 0x00040000L
#define GDS_GWS_RESET1__RESOURCE51_RESET_MASK                                                                 0x00080000L
#define GDS_GWS_RESET1__RESOURCE52_RESET_MASK                                                                 0x00100000L
#define GDS_GWS_RESET1__RESOURCE53_RESET_MASK                                                                 0x00200000L
#define GDS_GWS_RESET1__RESOURCE54_RESET_MASK                                                                 0x00400000L
#define GDS_GWS_RESET1__RESOURCE55_RESET_MASK                                                                 0x00800000L
#define GDS_GWS_RESET1__RESOURCE56_RESET_MASK                                                                 0x01000000L
#define GDS_GWS_RESET1__RESOURCE57_RESET_MASK                                                                 0x02000000L
#define GDS_GWS_RESET1__RESOURCE58_RESET_MASK                                                                 0x04000000L
#define GDS_GWS_RESET1__RESOURCE59_RESET_MASK                                                                 0x08000000L
#define GDS_GWS_RESET1__RESOURCE60_RESET_MASK                                                                 0x10000000L
#define GDS_GWS_RESET1__RESOURCE61_RESET_MASK                                                                 0x20000000L
#define GDS_GWS_RESET1__RESOURCE62_RESET_MASK                                                                 0x40000000L
#define GDS_GWS_RESET1__RESOURCE63_RESET_MASK                                                                 0x80000000L
//GDS_GWS_RESOURCE_RESET
#define GDS_GWS_RESOURCE_RESET__RESET__SHIFT                                                                  0x0
#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID__SHIFT                                                            0x8
#define GDS_GWS_RESOURCE_RESET__UNUSED__SHIFT                                                                 0x10
#define GDS_GWS_RESOURCE_RESET__RESET_MASK                                                                    0x00000001L
#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID_MASK                                                              0x0000FF00L
#define GDS_GWS_RESOURCE_RESET__UNUSED_MASK                                                                   0xFFFF0000L
//GDS_COMPUTE_MAX_WAVE_ID
#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT                                                           0x0
#define GDS_COMPUTE_MAX_WAVE_ID__UNUSED__SHIFT                                                                0xc
#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID_MASK                                                             0x00000FFFL
#define GDS_COMPUTE_MAX_WAVE_ID__UNUSED_MASK                                                                  0xFFFFF000L
//GDS_OA_RESET_MASK
#define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET__SHIFT                                                       0x0
#define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET__SHIFT                                                       0x1
#define GDS_OA_RESET_MASK__ME0_CS_RESET__SHIFT                                                                0x2
#define GDS_OA_RESET_MASK__ME0_GFXHP3D_GS_RESET__SHIFT                                                        0x3
#define GDS_OA_RESET_MASK__ME1_PIPE0_RESET__SHIFT                                                             0x4
#define GDS_OA_RESET_MASK__ME1_PIPE1_RESET__SHIFT                                                             0x5
#define GDS_OA_RESET_MASK__ME1_PIPE2_RESET__SHIFT                                                             0x6
#define GDS_OA_RESET_MASK__ME1_PIPE3_RESET__SHIFT                                                             0x7
#define GDS_OA_RESET_MASK__ME2_PIPE0_RESET__SHIFT                                                             0x8
#define GDS_OA_RESET_MASK__ME2_PIPE1_RESET__SHIFT                                                             0x9
#define GDS_OA_RESET_MASK__ME2_PIPE2_RESET__SHIFT                                                             0xa
#define GDS_OA_RESET_MASK__ME2_PIPE3_RESET__SHIFT                                                             0xb
#define GDS_OA_RESET_MASK__ME0_PIPE1_CS_RESET__SHIFT                                                          0xc
#define GDS_OA_RESET_MASK__UNUSED1__SHIFT                                                                     0xd
#define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET_MASK                                                         0x00000001L
#define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET_MASK                                                         0x00000002L
#define GDS_OA_RESET_MASK__ME0_CS_RESET_MASK                                                                  0x00000004L
#define GDS_OA_RESET_MASK__ME0_GFXHP3D_GS_RESET_MASK                                                          0x00000008L
#define GDS_OA_RESET_MASK__ME1_PIPE0_RESET_MASK                                                               0x00000010L
#define GDS_OA_RESET_MASK__ME1_PIPE1_RESET_MASK                                                               0x00000020L
#define GDS_OA_RESET_MASK__ME1_PIPE2_RESET_MASK                                                               0x00000040L
#define GDS_OA_RESET_MASK__ME1_PIPE3_RESET_MASK                                                               0x00000080L
#define GDS_OA_RESET_MASK__ME2_PIPE0_RESET_MASK                                                               0x00000100L
#define GDS_OA_RESET_MASK__ME2_PIPE1_RESET_MASK                                                               0x00000200L
#define GDS_OA_RESET_MASK__ME2_PIPE2_RESET_MASK                                                               0x00000400L
#define GDS_OA_RESET_MASK__ME2_PIPE3_RESET_MASK                                                               0x00000800L
#define GDS_OA_RESET_MASK__ME0_PIPE1_CS_RESET_MASK                                                            0x00001000L
#define GDS_OA_RESET_MASK__UNUSED1_MASK                                                                       0xFFFFE000L
//GDS_OA_RESET
#define GDS_OA_RESET__RESET__SHIFT                                                                            0x0
#define GDS_OA_RESET__PIPE_ID__SHIFT                                                                          0x8
#define GDS_OA_RESET__UNUSED__SHIFT                                                                           0x10
#define GDS_OA_RESET__RESET_MASK                                                                              0x00000001L
#define GDS_OA_RESET__PIPE_ID_MASK                                                                            0x0000FF00L
#define GDS_OA_RESET__UNUSED_MASK                                                                             0xFFFF0000L
//GDS_ENHANCE2
#define GDS_ENHANCE2__MISC__SHIFT                                                                             0x0
#define GDS_ENHANCE2__RD_BUF_TAG_MISS__SHIFT                                                                  0x12
#define GDS_ENHANCE2__GDS_INTERFACES_FGCG_OVERRIDE__SHIFT                                                     0x15
#define GDS_ENHANCE2__GDS_CLK_ENHANCE_DIS__SHIFT                                                              0x16
#define GDS_ENHANCE2__DISABLE_LOGIC_ID_CLAMP__SHIFT                                                           0x17
#define GDS_ENHANCE2__DISABLE_MEMORY_VIOLATION_REPORT__SHIFT                                                  0x18
#define GDS_ENHANCE2__GDS_CLK_ENHANCE_DIS_MGCG_DSO__SHIFT                                                     0x19
#define GDS_ENHANCE2__GDS_CLK_ENHANCE_DIS_MGCG_DSA__SHIFT                                                     0x1d
#define GDS_ENHANCE2__MISC_MASK                                                                               0x0003FFFFL
#define GDS_ENHANCE2__RD_BUF_TAG_MISS_MASK                                                                    0x00040000L
#define GDS_ENHANCE2__GDS_INTERFACES_FGCG_OVERRIDE_MASK                                                       0x00200000L
#define GDS_ENHANCE2__GDS_CLK_ENHANCE_DIS_MASK                                                                0x00400000L
#define GDS_ENHANCE2__DISABLE_LOGIC_ID_CLAMP_MASK                                                             0x00800000L
#define GDS_ENHANCE2__DISABLE_MEMORY_VIOLATION_REPORT_MASK                                                    0x01000000L
#define GDS_ENHANCE2__GDS_CLK_ENHANCE_DIS_MGCG_DSO_MASK                                                       0x1E000000L
#define GDS_ENHANCE2__GDS_CLK_ENHANCE_DIS_MGCG_DSA_MASK                                                       0xE0000000L
//GDS_OA_CGPG_RESTORE
#define GDS_OA_CGPG_RESTORE__VMID__SHIFT                                                                      0x0
#define GDS_OA_CGPG_RESTORE__MEID__SHIFT                                                                      0x8
#define GDS_OA_CGPG_RESTORE__PIPEID__SHIFT                                                                    0xc
#define GDS_OA_CGPG_RESTORE__QUEUEID__SHIFT                                                                   0x10
#define GDS_OA_CGPG_RESTORE__UNUSED__SHIFT                                                                    0x14
#define GDS_OA_CGPG_RESTORE__VMID_MASK                                                                        0x000000FFL
#define GDS_OA_CGPG_RESTORE__MEID_MASK                                                                        0x00000F00L
#define GDS_OA_CGPG_RESTORE__PIPEID_MASK                                                                      0x0000F000L
#define GDS_OA_CGPG_RESTORE__QUEUEID_MASK                                                                     0x000F0000L
#define GDS_OA_CGPG_RESTORE__UNUSED_MASK                                                                      0xFFF00000L
//GDS_CS_CTXSW_STATUS
#define GDS_CS_CTXSW_STATUS__R__SHIFT                                                                         0x0
#define GDS_CS_CTXSW_STATUS__W__SHIFT                                                                         0x1
#define GDS_CS_CTXSW_STATUS__UNUSED__SHIFT                                                                    0x2
#define GDS_CS_CTXSW_STATUS__R_MASK                                                                           0x00000001L
#define GDS_CS_CTXSW_STATUS__W_MASK                                                                           0x00000002L
#define GDS_CS_CTXSW_STATUS__UNUSED_MASK                                                                      0xFFFFFFFCL
//GDS_CS_CTXSW_CNT0
#define GDS_CS_CTXSW_CNT0__UPDN__SHIFT                                                                        0x0
#define GDS_CS_CTXSW_CNT0__PTR__SHIFT                                                                         0x10
#define GDS_CS_CTXSW_CNT0__UPDN_MASK                                                                          0x0000FFFFL
#define GDS_CS_CTXSW_CNT0__PTR_MASK                                                                           0xFFFF0000L
//GDS_CS_CTXSW_CNT1
#define GDS_CS_CTXSW_CNT1__UPDN__SHIFT                                                                        0x0
#define GDS_CS_CTXSW_CNT1__PTR__SHIFT                                                                         0x10
#define GDS_CS_CTXSW_CNT1__UPDN_MASK                                                                          0x0000FFFFL
#define GDS_CS_CTXSW_CNT1__PTR_MASK                                                                           0xFFFF0000L
//GDS_CS_CTXSW_CNT2
#define GDS_CS_CTXSW_CNT2__UPDN__SHIFT                                                                        0x0
#define GDS_CS_CTXSW_CNT2__PTR__SHIFT                                                                         0x10
#define GDS_CS_CTXSW_CNT2__UPDN_MASK                                                                          0x0000FFFFL
#define GDS_CS_CTXSW_CNT2__PTR_MASK                                                                           0xFFFF0000L
//GDS_CS_CTXSW_CNT3
#define GDS_CS_CTXSW_CNT3__UPDN__SHIFT                                                                        0x0
#define GDS_CS_CTXSW_CNT3__PTR__SHIFT                                                                         0x10
#define GDS_CS_CTXSW_CNT3__UPDN_MASK                                                                          0x0000FFFFL
#define GDS_CS_CTXSW_CNT3__PTR_MASK                                                                           0xFFFF0000L
//GDS_GFX_CTXSW_STATUS
#define GDS_GFX_CTXSW_STATUS__R__SHIFT                                                                        0x0
#define GDS_GFX_CTXSW_STATUS__W__SHIFT                                                                        0x1
#define GDS_GFX_CTXSW_STATUS__UNUSED__SHIFT                                                                   0x2
#define GDS_GFX_CTXSW_STATUS__R_MASK                                                                          0x00000001L
#define GDS_GFX_CTXSW_STATUS__W_MASK                                                                          0x00000002L
#define GDS_GFX_CTXSW_STATUS__UNUSED_MASK                                                                     0xFFFFFFFCL
//GDS_VS_CTXSW_CNT0
#define GDS_VS_CTXSW_CNT0__UPDN__SHIFT                                                                        0x0
#define GDS_VS_CTXSW_CNT0__PTR__SHIFT                                                                         0x10
#define GDS_VS_CTXSW_CNT0__UPDN_MASK                                                                          0x0000FFFFL
#define GDS_VS_CTXSW_CNT0__PTR_MASK                                                                           0xFFFF0000L
//GDS_VS_CTXSW_CNT1
#define GDS_VS_CTXSW_CNT1__UPDN__SHIFT                                                                        0x0
#define GDS_VS_CTXSW_CNT1__PTR__SHIFT                                                                         0x10
#define GDS_VS_CTXSW_CNT1__UPDN_MASK                                                                          0x0000FFFFL
#define GDS_VS_CTXSW_CNT1__PTR_MASK                                                                           0xFFFF0000L
//GDS_VS_CTXSW_CNT2
#define GDS_VS_CTXSW_CNT2__UPDN__SHIFT                                                                        0x0
#define GDS_VS_CTXSW_CNT2__PTR__SHIFT                                                                         0x10
#define GDS_VS_CTXSW_CNT2__UPDN_MASK                                                                          0x0000FFFFL
#define GDS_VS_CTXSW_CNT2__PTR_MASK                                                                           0xFFFF0000L
//GDS_VS_CTXSW_CNT3
#define GDS_VS_CTXSW_CNT3__UPDN__SHIFT                                                                        0x0
#define GDS_VS_CTXSW_CNT3__PTR__SHIFT                                                                         0x10
#define GDS_VS_CTXSW_CNT3__UPDN_MASK                                                                          0x0000FFFFL
#define GDS_VS_CTXSW_CNT3__PTR_MASK                                                                           0xFFFF0000L
//GDS_PS_CTXSW_CNT0
#define GDS_PS_CTXSW_CNT0__UPDN__SHIFT                                                                        0x0
#define GDS_PS_CTXSW_CNT0__PTR__SHIFT                                                                         0x10
#define GDS_PS_CTXSW_CNT0__UPDN_MASK                                                                          0x0000FFFFL
#define GDS_PS_CTXSW_CNT0__PTR_MASK                                                                           0xFFFF0000L
//GDS_PS_CTXSW_CNT1
#define GDS_PS_CTXSW_CNT1__UPDN__SHIFT                                                                        0x0
#define GDS_PS_CTXSW_CNT1__PTR__SHIFT                                                                         0x10
#define GDS_PS_CTXSW_CNT1__UPDN_MASK                                                                          0x0000FFFFL
#define GDS_PS_CTXSW_CNT1__PTR_MASK                                                                           0xFFFF0000L
//GDS_PS_CTXSW_CNT2
#define GDS_PS_CTXSW_CNT2__UPDN__SHIFT                                                                        0x0
#define GDS_PS_CTXSW_CNT2__PTR__SHIFT                                                                         0x10
#define GDS_PS_CTXSW_CNT2__UPDN_MASK                                                                          0x0000FFFFL
#define GDS_PS_CTXSW_CNT2__PTR_MASK                                                                           0xFFFF0000L
//GDS_PS_CTXSW_CNT3
#define GDS_PS_CTXSW_CNT3__UPDN__SHIFT                                                                        0x0
#define GDS_PS_CTXSW_CNT3__PTR__SHIFT                                                                         0x10
#define GDS_PS_CTXSW_CNT3__UPDN_MASK                                                                          0x0000FFFFL
#define GDS_PS_CTXSW_CNT3__PTR_MASK                                                                           0xFFFF0000L
//GDS_PS_CTXSW_IDX
#define GDS_PS_CTXSW_IDX__PACKER_ID__SHIFT                                                                    0x0
#define GDS_PS_CTXSW_IDX__UNUSED__SHIFT                                                                       0x4
#define GDS_PS_CTXSW_IDX__PACKER_ID_MASK                                                                      0x0000000FL
#define GDS_PS_CTXSW_IDX__UNUSED_MASK                                                                         0xFFFFFFF0L
//GDS_GS_CTXSW_CNT0
#define GDS_GS_CTXSW_CNT0__UPDN__SHIFT                                                                        0x0
#define GDS_GS_CTXSW_CNT0__PTR__SHIFT                                                                         0x10
#define GDS_GS_CTXSW_CNT0__UPDN_MASK                                                                          0x0000FFFFL
#define GDS_GS_CTXSW_CNT0__PTR_MASK                                                                           0xFFFF0000L
//GDS_GS_CTXSW_CNT1
#define GDS_GS_CTXSW_CNT1__UPDN__SHIFT                                                                        0x0
#define GDS_GS_CTXSW_CNT1__PTR__SHIFT                                                                         0x10
#define GDS_GS_CTXSW_CNT1__UPDN_MASK                                                                          0x0000FFFFL
#define GDS_GS_CTXSW_CNT1__PTR_MASK                                                                           0xFFFF0000L
//GDS_GS_CTXSW_CNT2
#define GDS_GS_CTXSW_CNT2__UPDN__SHIFT                                                                        0x0
#define GDS_GS_CTXSW_CNT2__PTR__SHIFT                                                                         0x10
#define GDS_GS_CTXSW_CNT2__UPDN_MASK                                                                          0x0000FFFFL
#define GDS_GS_CTXSW_CNT2__PTR_MASK                                                                           0xFFFF0000L
//GDS_GS_CTXSW_CNT3
#define GDS_GS_CTXSW_CNT3__UPDN__SHIFT                                                                        0x0
#define GDS_GS_CTXSW_CNT3__PTR__SHIFT                                                                         0x10
#define GDS_GS_CTXSW_CNT3__UPDN_MASK                                                                          0x0000FFFFL
#define GDS_GS_CTXSW_CNT3__PTR_MASK                                                                           0xFFFF0000L
//GDS_MEMORY_CLEAN
#define GDS_MEMORY_CLEAN__START__SHIFT                                                                        0x0
#define GDS_MEMORY_CLEAN__FINISH__SHIFT                                                                       0x1
#define GDS_MEMORY_CLEAN__UNUSED__SHIFT                                                                       0x2
#define GDS_MEMORY_CLEAN__START_MASK                                                                          0x00000001L
#define GDS_MEMORY_CLEAN__FINISH_MASK                                                                         0x00000002L
#define GDS_MEMORY_CLEAN__UNUSED_MASK                                                                         0xFFFFFFFCL


// addressBlock: gc_gfxdec0
//DB_RENDER_CONTROL
#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT                                                          0x0
#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE__SHIFT                                                        0x1
#define DB_RENDER_CONTROL__DEPTH_COPY__SHIFT                                                                  0x2
#define DB_RENDER_CONTROL__STENCIL_COPY__SHIFT                                                                0x3
#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE__SHIFT                                                          0x4
#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE__SHIFT                                                    0x5
#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE__SHIFT                                                      0x6
#define DB_RENDER_CONTROL__COPY_CENTROID__SHIFT                                                               0x7
#define DB_RENDER_CONTROL__COPY_SAMPLE__SHIFT                                                                 0x8
#define DB_RENDER_CONTROL__DECOMPRESS_ENABLE__SHIFT                                                           0xc
#define DB_RENDER_CONTROL__PS_INVOKE_DISABLE__SHIFT                                                           0xd
#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE_MASK                                                            0x00000001L
#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE_MASK                                                          0x00000002L
#define DB_RENDER_CONTROL__DEPTH_COPY_MASK                                                                    0x00000004L
#define DB_RENDER_CONTROL__STENCIL_COPY_MASK                                                                  0x00000008L
#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE_MASK                                                            0x00000010L
#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE_MASK                                                      0x00000020L
#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE_MASK                                                        0x00000040L
#define DB_RENDER_CONTROL__COPY_CENTROID_MASK                                                                 0x00000080L
#define DB_RENDER_CONTROL__COPY_SAMPLE_MASK                                                                   0x00000F00L
#define DB_RENDER_CONTROL__DECOMPRESS_ENABLE_MASK                                                             0x00001000L
#define DB_RENDER_CONTROL__PS_INVOKE_DISABLE_MASK                                                             0x00002000L
//DB_COUNT_CONTROL
#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE__SHIFT                                                      0x0
#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS__SHIFT                                                         0x1
#define DB_COUNT_CONTROL__DISABLE_CONSERVATIVE_ZPASS_COUNTS__SHIFT                                            0x2
#define DB_COUNT_CONTROL__ENHANCED_CONSERVATIVE_ZPASS_COUNTS__SHIFT                                           0x3
#define DB_COUNT_CONTROL__SAMPLE_RATE__SHIFT                                                                  0x4
#define DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT                                                                 0x8
#define DB_COUNT_CONTROL__ZFAIL_ENABLE__SHIFT                                                                 0xc
#define DB_COUNT_CONTROL__SFAIL_ENABLE__SHIFT                                                                 0x10
#define DB_COUNT_CONTROL__DBFAIL_ENABLE__SHIFT                                                                0x14
#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE__SHIFT                                                            0x18
#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE__SHIFT                                                             0x1c
#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE_MASK                                                        0x00000001L
#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_MASK                                                           0x00000002L
#define DB_COUNT_CONTROL__DISABLE_CONSERVATIVE_ZPASS_COUNTS_MASK                                              0x00000004L
#define DB_COUNT_CONTROL__ENHANCED_CONSERVATIVE_ZPASS_COUNTS_MASK                                             0x00000008L
#define DB_COUNT_CONTROL__SAMPLE_RATE_MASK                                                                    0x00000070L
#define DB_COUNT_CONTROL__ZPASS_ENABLE_MASK                                                                   0x00000F00L
#define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK                                                                   0x0000F000L
#define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK                                                                   0x000F0000L
#define DB_COUNT_CONTROL__DBFAIL_ENABLE_MASK                                                                  0x00F00000L
#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE_MASK                                                              0x0F000000L
#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE_MASK                                                               0xF0000000L
//DB_DEPTH_VIEW
#define DB_DEPTH_VIEW__SLICE_START__SHIFT                                                                     0x0
#define DB_DEPTH_VIEW__SLICE_START_HI__SHIFT                                                                  0xb
#define DB_DEPTH_VIEW__SLICE_MAX__SHIFT                                                                       0xd
#define DB_DEPTH_VIEW__Z_READ_ONLY__SHIFT                                                                     0x18
#define DB_DEPTH_VIEW__STENCIL_READ_ONLY__SHIFT                                                               0x19
#define DB_DEPTH_VIEW__MIPID__SHIFT                                                                           0x1a
#define DB_DEPTH_VIEW__SLICE_MAX_HI__SHIFT                                                                    0x1e
#define DB_DEPTH_VIEW__SLICE_START_MASK                                                                       0x000007FFL
#define DB_DEPTH_VIEW__SLICE_START_HI_MASK                                                                    0x00001800L
#define DB_DEPTH_VIEW__SLICE_MAX_MASK                                                                         0x00FFE000L
#define DB_DEPTH_VIEW__Z_READ_ONLY_MASK                                                                       0x01000000L
#define DB_DEPTH_VIEW__STENCIL_READ_ONLY_MASK                                                                 0x02000000L
#define DB_DEPTH_VIEW__MIPID_MASK                                                                             0x3C000000L
#define DB_DEPTH_VIEW__SLICE_MAX_HI_MASK                                                                      0xC0000000L
//DB_RENDER_OVERRIDE
#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE__SHIFT                                                           0x0
#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0__SHIFT                                                          0x2
#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1__SHIFT                                                          0x4
#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER__SHIFT                                                       0x6
#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE__SHIFT                                                             0x7
#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE__SHIFT                                                       0x8
#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE__SHIFT                                                          0x9
#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT                                                           0xa
#define DB_RENDER_OVERRIDE__FORCE_Z_READ__SHIFT                                                               0xb
#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ__SHIFT                                                         0xc
#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE__SHIFT                                                         0xd
#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT__SHIFT                                                    0xf
#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP__SHIFT                                                     0x10
#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE__SHIFT                                                           0x11
#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED__SHIFT                                                      0x12
#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM__SHIFT                                                         0x13
#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT__SHIFT                                                           0x15
#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES__SHIFT                                                    0x1a
#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY__SHIFT                                                              0x1b
#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY__SHIFT                                                        0x1c
#define DB_RENDER_OVERRIDE__FORCE_Z_VALID__SHIFT                                                              0x1d
#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID__SHIFT                                                        0x1e
#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION__SHIFT                                                       0x1f
#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE_MASK                                                             0x00000003L
#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0_MASK                                                            0x0000000CL
#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1_MASK                                                            0x00000030L
#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER_MASK                                                         0x00000040L
#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE_MASK                                                               0x00000080L
#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE_MASK                                                         0x00000100L
#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE_MASK                                                            0x00000200L
#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL_MASK                                                             0x00000400L
#define DB_RENDER_OVERRIDE__FORCE_Z_READ_MASK                                                                 0x00000800L
#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ_MASK                                                           0x00001000L
#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE_MASK                                                           0x00006000L
#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT_MASK                                                      0x00008000L
#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP_MASK                                                       0x00010000L
#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE_MASK                                                             0x00020000L
#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED_MASK                                                        0x00040000L
#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM_MASK                                                           0x00180000L
#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT_MASK                                                             0x03E00000L
#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES_MASK                                                      0x04000000L
#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY_MASK                                                                0x08000000L
#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY_MASK                                                          0x10000000L
#define DB_RENDER_OVERRIDE__FORCE_Z_VALID_MASK                                                                0x20000000L
#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID_MASK                                                          0x40000000L
#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION_MASK                                                         0x80000000L
//DB_RENDER_OVERRIDE2
#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL__SHIFT                                              0x0
#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN__SHIFT                                            0x2
#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION__SHIFT                                       0x5
#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION__SHIFT                                        0x6
#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION__SHIFT                                               0x7
#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH__SHIFT                                                     0x8
#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP__SHIFT                                                         0x9
#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT                                           0xa
#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE__SHIFT                                                 0xb
#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC__SHIFT                                                                 0xc
#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF__SHIFT                                                              0xf
#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF__SHIFT                                                              0x12
#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE__SHIFT                                                           0x15
#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS__SHIFT                                                         0x16
#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS__SHIFT                                                         0x17
#define DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL__SHIFT                                               0x19
#define DB_RENDER_OVERRIDE2__CENTROID_COMPUTATION_MODE__SHIFT                                                 0x1b
#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL_MASK                                                0x00000003L
#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN_MASK                                              0x0000001CL
#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION_MASK                                         0x00000020L
#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION_MASK                                          0x00000040L
#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION_MASK                                                 0x00000080L
#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH_MASK                                                       0x00000100L
#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP_MASK                                                           0x00000200L
#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE_MASK                                             0x00000400L
#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE_MASK                                                   0x00000800L
#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC_MASK                                                                   0x00007000L
#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF_MASK                                                                0x00038000L
#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF_MASK                                                                0x001C0000L
#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE_MASK                                                             0x00200000L
#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS_MASK                                                           0x00400000L
#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS_MASK                                                           0x00800000L
#define DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL_MASK                                                 0x02000000L
#define DB_RENDER_OVERRIDE2__CENTROID_COMPUTATION_MODE_MASK                                                   0x18000000L
//DB_HTILE_DATA_BASE
#define DB_HTILE_DATA_BASE__BASE_256B__SHIFT                                                                  0x0
#define DB_HTILE_DATA_BASE__BASE_256B_MASK                                                                    0xFFFFFFFFL
//DB_DEPTH_SIZE_XY
#define DB_DEPTH_SIZE_XY__X_MAX__SHIFT                                                                        0x0
#define DB_DEPTH_SIZE_XY__Y_MAX__SHIFT                                                                        0x10
#define DB_DEPTH_SIZE_XY__X_MAX_MASK                                                                          0x00003FFFL
#define DB_DEPTH_SIZE_XY__Y_MAX_MASK                                                                          0x3FFF0000L
//DB_DEPTH_BOUNDS_MIN
#define DB_DEPTH_BOUNDS_MIN__MIN__SHIFT                                                                       0x0
#define DB_DEPTH_BOUNDS_MIN__MIN_MASK                                                                         0xFFFFFFFFL
//DB_DEPTH_BOUNDS_MAX
#define DB_DEPTH_BOUNDS_MAX__MAX__SHIFT                                                                       0x0
#define DB_DEPTH_BOUNDS_MAX__MAX_MASK                                                                         0xFFFFFFFFL
//DB_STENCIL_CLEAR
#define DB_STENCIL_CLEAR__CLEAR__SHIFT                                                                        0x0
#define DB_STENCIL_CLEAR__CLEAR_MASK                                                                          0x000000FFL
//DB_DEPTH_CLEAR
#define DB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT                                                                    0x0
#define DB_DEPTH_CLEAR__DEPTH_CLEAR_MASK                                                                      0xFFFFFFFFL
//PA_SC_SCREEN_SCISSOR_TL
#define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT                                                                  0x0
#define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT                                                                  0x10
#define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK                                                                    0x0000FFFFL
#define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK                                                                    0xFFFF0000L
//PA_SC_SCREEN_SCISSOR_BR
#define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT                                                                  0x0
#define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT                                                                  0x10
#define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK                                                                    0x0000FFFFL
#define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK                                                                    0xFFFF0000L
//DB_DFSM_CONTROL
#define DB_DFSM_CONTROL__PUNCHOUT_MODE__SHIFT                                                                 0x0
#define DB_DFSM_CONTROL__POPS_DRAIN_PS_ON_OVERLAP__SHIFT                                                      0x2
#define DB_DFSM_CONTROL__DISALLOW_OVERFLOW__SHIFT                                                             0x3
#define DB_DFSM_CONTROL__PUNCHOUT_MODE_MASK                                                                   0x00000003L
#define DB_DFSM_CONTROL__POPS_DRAIN_PS_ON_OVERLAP_MASK                                                        0x00000004L
#define DB_DFSM_CONTROL__DISALLOW_OVERFLOW_MASK                                                               0x00000008L
//DB_RESERVED_REG_2
#define DB_RESERVED_REG_2__FIELD_1__SHIFT                                                                     0x0
#define DB_RESERVED_REG_2__FIELD_2__SHIFT                                                                     0x4
#define DB_RESERVED_REG_2__FIELD_3__SHIFT                                                                     0x8
#define DB_RESERVED_REG_2__FIELD_4__SHIFT                                                                     0xd
#define DB_RESERVED_REG_2__FIELD_5__SHIFT                                                                     0xf
#define DB_RESERVED_REG_2__FIELD_6__SHIFT                                                                     0x11
#define DB_RESERVED_REG_2__FIELD_7__SHIFT                                                                     0x13
#define DB_RESERVED_REG_2__FIELD_8__SHIFT                                                                     0x1c
#define DB_RESERVED_REG_2__FIELD_1_MASK                                                                       0x0000000FL
#define DB_RESERVED_REG_2__FIELD_2_MASK                                                                       0x000000F0L
#define DB_RESERVED_REG_2__FIELD_3_MASK                                                                       0x00001F00L
#define DB_RESERVED_REG_2__FIELD_4_MASK                                                                       0x00006000L
#define DB_RESERVED_REG_2__FIELD_5_MASK                                                                       0x00018000L
#define DB_RESERVED_REG_2__FIELD_6_MASK                                                                       0x00060000L
#define DB_RESERVED_REG_2__FIELD_7_MASK                                                                       0x00180000L
#define DB_RESERVED_REG_2__FIELD_8_MASK                                                                       0xF0000000L
//DB_Z_INFO
#define DB_Z_INFO__FORMAT__SHIFT                                                                              0x0
#define DB_Z_INFO__NUM_SAMPLES__SHIFT                                                                         0x2
#define DB_Z_INFO__SW_MODE__SHIFT                                                                             0x4
#define DB_Z_INFO__FAULT_BEHAVIOR__SHIFT                                                                      0x9
#define DB_Z_INFO__ITERATE_FLUSH__SHIFT                                                                       0xb
#define DB_Z_INFO__PARTIALLY_RESIDENT__SHIFT                                                                  0xc
#define DB_Z_INFO__RESERVED_FIELD_1__SHIFT                                                                    0xd
#define DB_Z_INFO__MAXMIP__SHIFT                                                                              0x10
#define DB_Z_INFO__ITERATE_256__SHIFT                                                                         0x14
#define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES__SHIFT                                                             0x17
#define DB_Z_INFO__ALLOW_EXPCLEAR__SHIFT                                                                      0x1b
#define DB_Z_INFO__READ_SIZE__SHIFT                                                                           0x1c
#define DB_Z_INFO__TILE_SURFACE_ENABLE__SHIFT                                                                 0x1d
#define DB_Z_INFO__ZRANGE_PRECISION__SHIFT                                                                    0x1f
#define DB_Z_INFO__FORMAT_MASK                                                                                0x00000003L
#define DB_Z_INFO__NUM_SAMPLES_MASK                                                                           0x0000000CL
#define DB_Z_INFO__SW_MODE_MASK                                                                               0x000001F0L
#define DB_Z_INFO__FAULT_BEHAVIOR_MASK                                                                        0x00000600L
#define DB_Z_INFO__ITERATE_FLUSH_MASK                                                                         0x00000800L
#define DB_Z_INFO__PARTIALLY_RESIDENT_MASK                                                                    0x00001000L
#define DB_Z_INFO__RESERVED_FIELD_1_MASK                                                                      0x0000E000L
#define DB_Z_INFO__MAXMIP_MASK                                                                                0x000F0000L
#define DB_Z_INFO__ITERATE_256_MASK                                                                           0x00100000L
#define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES_MASK                                                               0x07800000L
#define DB_Z_INFO__ALLOW_EXPCLEAR_MASK                                                                        0x08000000L
#define DB_Z_INFO__READ_SIZE_MASK                                                                             0x10000000L
#define DB_Z_INFO__TILE_SURFACE_ENABLE_MASK                                                                   0x20000000L
#define DB_Z_INFO__ZRANGE_PRECISION_MASK                                                                      0x80000000L
//DB_STENCIL_INFO
#define DB_STENCIL_INFO__FORMAT__SHIFT                                                                        0x0
#define DB_STENCIL_INFO__SW_MODE__SHIFT                                                                       0x4
#define DB_STENCIL_INFO__FAULT_BEHAVIOR__SHIFT                                                                0x9
#define DB_STENCIL_INFO__ITERATE_FLUSH__SHIFT                                                                 0xb
#define DB_STENCIL_INFO__PARTIALLY_RESIDENT__SHIFT                                                            0xc
#define DB_STENCIL_INFO__RESERVED_FIELD_1__SHIFT                                                              0xd
#define DB_STENCIL_INFO__ITERATE_256__SHIFT                                                                   0x14
#define DB_STENCIL_INFO__ALLOW_EXPCLEAR__SHIFT                                                                0x1b
#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE__SHIFT                                                          0x1d
#define DB_STENCIL_INFO__FORMAT_MASK                                                                          0x00000001L
#define DB_STENCIL_INFO__SW_MODE_MASK                                                                         0x000001F0L
#define DB_STENCIL_INFO__FAULT_BEHAVIOR_MASK                                                                  0x00000600L
#define DB_STENCIL_INFO__ITERATE_FLUSH_MASK                                                                   0x00000800L
#define DB_STENCIL_INFO__PARTIALLY_RESIDENT_MASK                                                              0x00001000L
#define DB_STENCIL_INFO__RESERVED_FIELD_1_MASK                                                                0x0000E000L
#define DB_STENCIL_INFO__ITERATE_256_MASK                                                                     0x00100000L
#define DB_STENCIL_INFO__ALLOW_EXPCLEAR_MASK                                                                  0x08000000L
#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE_MASK                                                            0x20000000L
//DB_Z_READ_BASE
#define DB_Z_READ_BASE__BASE_256B__SHIFT                                                                      0x0
#define DB_Z_READ_BASE__BASE_256B_MASK                                                                        0xFFFFFFFFL
//DB_STENCIL_READ_BASE
#define DB_STENCIL_READ_BASE__BASE_256B__SHIFT                                                                0x0
#define DB_STENCIL_READ_BASE__BASE_256B_MASK                                                                  0xFFFFFFFFL
//DB_Z_WRITE_BASE
#define DB_Z_WRITE_BASE__BASE_256B__SHIFT                                                                     0x0
#define DB_Z_WRITE_BASE__BASE_256B_MASK                                                                       0xFFFFFFFFL
//DB_STENCIL_WRITE_BASE
#define DB_STENCIL_WRITE_BASE__BASE_256B__SHIFT                                                               0x0
#define DB_STENCIL_WRITE_BASE__BASE_256B_MASK                                                                 0xFFFFFFFFL
//DB_RESERVED_REG_1
#define DB_RESERVED_REG_1__FIELD_1__SHIFT                                                                     0x0
#define DB_RESERVED_REG_1__FIELD_2__SHIFT                                                                     0xb
#define DB_RESERVED_REG_1__FIELD_1_MASK                                                                       0x000007FFL
#define DB_RESERVED_REG_1__FIELD_2_MASK                                                                       0x003FF800L
//DB_RESERVED_REG_3
#define DB_RESERVED_REG_3__FIELD_1__SHIFT                                                                     0x0
#define DB_RESERVED_REG_3__FIELD_1_MASK                                                                       0x003FFFFFL
//DB_Z_READ_BASE_HI
#define DB_Z_READ_BASE_HI__BASE_HI__SHIFT                                                                     0x0
#define DB_Z_READ_BASE_HI__BASE_HI_MASK                                                                       0x000000FFL
//DB_STENCIL_READ_BASE_HI
#define DB_STENCIL_READ_BASE_HI__BASE_HI__SHIFT                                                               0x0
#define DB_STENCIL_READ_BASE_HI__BASE_HI_MASK                                                                 0x000000FFL
//DB_Z_WRITE_BASE_HI
#define DB_Z_WRITE_BASE_HI__BASE_HI__SHIFT                                                                    0x0
#define DB_Z_WRITE_BASE_HI__BASE_HI_MASK                                                                      0x000000FFL
//DB_STENCIL_WRITE_BASE_HI
#define DB_STENCIL_WRITE_BASE_HI__BASE_HI__SHIFT                                                              0x0
#define DB_STENCIL_WRITE_BASE_HI__BASE_HI_MASK                                                                0x000000FFL
//DB_HTILE_DATA_BASE_HI
#define DB_HTILE_DATA_BASE_HI__BASE_HI__SHIFT                                                                 0x0
#define DB_HTILE_DATA_BASE_HI__BASE_HI_MASK                                                                   0x000000FFL
//DB_RMI_L2_CACHE_CONTROL
#define DB_RMI_L2_CACHE_CONTROL__Z_WR_POLICY__SHIFT                                                           0x0
#define DB_RMI_L2_CACHE_CONTROL__S_WR_POLICY__SHIFT                                                           0x2
#define DB_RMI_L2_CACHE_CONTROL__HTILE_WR_POLICY__SHIFT                                                       0x4
#define DB_RMI_L2_CACHE_CONTROL__ZPCPSD_WR_POLICY__SHIFT                                                      0x6
#define DB_RMI_L2_CACHE_CONTROL__Z_RD_POLICY__SHIFT                                                           0x10
#define DB_RMI_L2_CACHE_CONTROL__S_RD_POLICY__SHIFT                                                           0x12
#define DB_RMI_L2_CACHE_CONTROL__HTILE_RD_POLICY__SHIFT                                                       0x14
#define DB_RMI_L2_CACHE_CONTROL__Z_BIG_PAGE__SHIFT                                                            0x18
#define DB_RMI_L2_CACHE_CONTROL__S_BIG_PAGE__SHIFT                                                            0x19
#define DB_RMI_L2_CACHE_CONTROL__Z_WR_POLICY_MASK                                                             0x00000003L
#define DB_RMI_L2_CACHE_CONTROL__S_WR_POLICY_MASK                                                             0x0000000CL
#define DB_RMI_L2_CACHE_CONTROL__HTILE_WR_POLICY_MASK                                                         0x00000030L
#define DB_RMI_L2_CACHE_CONTROL__ZPCPSD_WR_POLICY_MASK                                                        0x000000C0L
#define DB_RMI_L2_CACHE_CONTROL__Z_RD_POLICY_MASK                                                             0x00030000L
#define DB_RMI_L2_CACHE_CONTROL__S_RD_POLICY_MASK                                                             0x000C0000L
#define DB_RMI_L2_CACHE_CONTROL__HTILE_RD_POLICY_MASK                                                         0x00300000L
#define DB_RMI_L2_CACHE_CONTROL__Z_BIG_PAGE_MASK                                                              0x01000000L
#define DB_RMI_L2_CACHE_CONTROL__S_BIG_PAGE_MASK                                                              0x02000000L
//TA_BC_BASE_ADDR
#define TA_BC_BASE_ADDR__ADDRESS__SHIFT                                                                       0x0
#define TA_BC_BASE_ADDR__ADDRESS_MASK                                                                         0xFFFFFFFFL
//TA_BC_BASE_ADDR_HI
#define TA_BC_BASE_ADDR_HI__ADDRESS__SHIFT                                                                    0x0
#define TA_BC_BASE_ADDR_HI__ADDRESS_MASK                                                                      0x000000FFL
//COHER_DEST_BASE_HI_0
#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B__SHIFT                                                        0x0
#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B_MASK                                                          0x000000FFL
//COHER_DEST_BASE_HI_1
#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B__SHIFT                                                        0x0
#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B_MASK                                                          0x000000FFL
//COHER_DEST_BASE_HI_2
#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B__SHIFT                                                        0x0
#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B_MASK                                                          0x000000FFL
//COHER_DEST_BASE_HI_3
#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B__SHIFT                                                        0x0
#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B_MASK                                                          0x000000FFL
//COHER_DEST_BASE_2
#define COHER_DEST_BASE_2__DEST_BASE_256B__SHIFT                                                              0x0
#define COHER_DEST_BASE_2__DEST_BASE_256B_MASK                                                                0xFFFFFFFFL
//COHER_DEST_BASE_3
#define COHER_DEST_BASE_3__DEST_BASE_256B__SHIFT                                                              0x0
#define COHER_DEST_BASE_3__DEST_BASE_256B_MASK                                                                0xFFFFFFFFL
//PA_SC_WINDOW_OFFSET
#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT                                                           0x0
#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT                                                           0x10
#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK                                                             0x0000FFFFL
#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK                                                             0xFFFF0000L
//PA_SC_WINDOW_SCISSOR_TL
#define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT                                                                  0x0
#define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT                                                                  0x10
#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT                                                 0x1f
#define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK                                                                    0x00007FFFL
#define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK                                                                    0x7FFF0000L
#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK                                                   0x80000000L
//PA_SC_WINDOW_SCISSOR_BR
#define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT                                                                  0x0
#define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT                                                                  0x10
#define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK                                                                    0x00007FFFL
#define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK                                                                    0x7FFF0000L
//PA_SC_CLIPRECT_RULE
#define PA_SC_CLIPRECT_RULE__CLIP_RULE__SHIFT                                                                 0x0
#define PA_SC_CLIPRECT_RULE__CLIP_RULE_MASK                                                                   0x0000FFFFL
//PA_SC_CLIPRECT_0_TL
#define PA_SC_CLIPRECT_0_TL__TL_X__SHIFT                                                                      0x0
#define PA_SC_CLIPRECT_0_TL__TL_Y__SHIFT                                                                      0x10
#define PA_SC_CLIPRECT_0_TL__TL_X_MASK                                                                        0x00007FFFL
#define PA_SC_CLIPRECT_0_TL__TL_Y_MASK                                                                        0x7FFF0000L
//PA_SC_CLIPRECT_0_BR
#define PA_SC_CLIPRECT_0_BR__BR_X__SHIFT                                                                      0x0
#define PA_SC_CLIPRECT_0_BR__BR_Y__SHIFT                                                                      0x10
#define PA_SC_CLIPRECT_0_BR__BR_X_MASK                                                                        0x00007FFFL
#define PA_SC_CLIPRECT_0_BR__BR_Y_MASK                                                                        0x7FFF0000L
//PA_SC_CLIPRECT_1_TL
#define PA_SC_CLIPRECT_1_TL__TL_X__SHIFT                                                                      0x0
#define PA_SC_CLIPRECT_1_TL__TL_Y__SHIFT                                                                      0x10
#define PA_SC_CLIPRECT_1_TL__TL_X_MASK                                                                        0x00007FFFL
#define PA_SC_CLIPRECT_1_TL__TL_Y_MASK                                                                        0x7FFF0000L
//PA_SC_CLIPRECT_1_BR
#define PA_SC_CLIPRECT_1_BR__BR_X__SHIFT                                                                      0x0
#define PA_SC_CLIPRECT_1_BR__BR_Y__SHIFT                                                                      0x10
#define PA_SC_CLIPRECT_1_BR__BR_X_MASK                                                                        0x00007FFFL
#define PA_SC_CLIPRECT_1_BR__BR_Y_MASK                                                                        0x7FFF0000L
//PA_SC_CLIPRECT_2_TL
#define PA_SC_CLIPRECT_2_TL__TL_X__SHIFT                                                                      0x0
#define PA_SC_CLIPRECT_2_TL__TL_Y__SHIFT                                                                      0x10
#define PA_SC_CLIPRECT_2_TL__TL_X_MASK                                                                        0x00007FFFL
#define PA_SC_CLIPRECT_2_TL__TL_Y_MASK                                                                        0x7FFF0000L
//PA_SC_CLIPRECT_2_BR
#define PA_SC_CLIPRECT_2_BR__BR_X__SHIFT                                                                      0x0
#define PA_SC_CLIPRECT_2_BR__BR_Y__SHIFT                                                                      0x10
#define PA_SC_CLIPRECT_2_BR__BR_X_MASK                                                                        0x00007FFFL
#define PA_SC_CLIPRECT_2_BR__BR_Y_MASK                                                                        0x7FFF0000L
//PA_SC_CLIPRECT_3_TL
#define PA_SC_CLIPRECT_3_TL__TL_X__SHIFT                                                                      0x0
#define PA_SC_CLIPRECT_3_TL__TL_Y__SHIFT                                                                      0x10
#define PA_SC_CLIPRECT_3_TL__TL_X_MASK                                                                        0x00007FFFL
#define PA_SC_CLIPRECT_3_TL__TL_Y_MASK                                                                        0x7FFF0000L
//PA_SC_CLIPRECT_3_BR
#define PA_SC_CLIPRECT_3_BR__BR_X__SHIFT                                                                      0x0
#define PA_SC_CLIPRECT_3_BR__BR_Y__SHIFT                                                                      0x10
#define PA_SC_CLIPRECT_3_BR__BR_X_MASK                                                                        0x00007FFFL
#define PA_SC_CLIPRECT_3_BR__BR_Y_MASK                                                                        0x7FFF0000L
//PA_SC_EDGERULE
#define PA_SC_EDGERULE__ER_TRI__SHIFT                                                                         0x0
#define PA_SC_EDGERULE__ER_POINT__SHIFT                                                                       0x4
#define PA_SC_EDGERULE__ER_RECT__SHIFT                                                                        0x8
#define PA_SC_EDGERULE__ER_LINE_LR__SHIFT                                                                     0xc
#define PA_SC_EDGERULE__ER_LINE_RL__SHIFT                                                                     0x12
#define PA_SC_EDGERULE__ER_LINE_TB__SHIFT                                                                     0x18
#define PA_SC_EDGERULE__ER_LINE_BT__SHIFT                                                                     0x1c
#define PA_SC_EDGERULE__ER_TRI_MASK                                                                           0x0000000FL
#define PA_SC_EDGERULE__ER_POINT_MASK                                                                         0x000000F0L
#define PA_SC_EDGERULE__ER_RECT_MASK                                                                          0x00000F00L
#define PA_SC_EDGERULE__ER_LINE_LR_MASK                                                                       0x0003F000L
#define PA_SC_EDGERULE__ER_LINE_RL_MASK                                                                       0x00FC0000L
#define PA_SC_EDGERULE__ER_LINE_TB_MASK                                                                       0x0F000000L
#define PA_SC_EDGERULE__ER_LINE_BT_MASK                                                                       0xF0000000L
//PA_SU_HARDWARE_SCREEN_OFFSET
#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X__SHIFT                                               0x0
#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y__SHIFT                                               0x10
#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X_MASK                                                 0x000001FFL
#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y_MASK                                                 0x01FF0000L
//CB_TARGET_MASK
#define CB_TARGET_MASK__TARGET0_ENABLE__SHIFT                                                                 0x0
#define CB_TARGET_MASK__TARGET1_ENABLE__SHIFT                                                                 0x4
#define CB_TARGET_MASK__TARGET2_ENABLE__SHIFT                                                                 0x8
#define CB_TARGET_MASK__TARGET3_ENABLE__SHIFT                                                                 0xc
#define CB_TARGET_MASK__TARGET4_ENABLE__SHIFT                                                                 0x10
#define CB_TARGET_MASK__TARGET5_ENABLE__SHIFT                                                                 0x14
#define CB_TARGET_MASK__TARGET6_ENABLE__SHIFT                                                                 0x18
#define CB_TARGET_MASK__TARGET7_ENABLE__SHIFT                                                                 0x1c
#define CB_TARGET_MASK__TARGET0_ENABLE_MASK                                                                   0x0000000FL
#define CB_TARGET_MASK__TARGET1_ENABLE_MASK                                                                   0x000000F0L
#define CB_TARGET_MASK__TARGET2_ENABLE_MASK                                                                   0x00000F00L
#define CB_TARGET_MASK__TARGET3_ENABLE_MASK                                                                   0x0000F000L
#define CB_TARGET_MASK__TARGET4_ENABLE_MASK                                                                   0x000F0000L
#define CB_TARGET_MASK__TARGET5_ENABLE_MASK                                                                   0x00F00000L
#define CB_TARGET_MASK__TARGET6_ENABLE_MASK                                                                   0x0F000000L
#define CB_TARGET_MASK__TARGET7_ENABLE_MASK                                                                   0xF0000000L
//CB_SHADER_MASK
#define CB_SHADER_MASK__OUTPUT0_ENABLE__SHIFT                                                                 0x0
#define CB_SHADER_MASK__OUTPUT1_ENABLE__SHIFT                                                                 0x4
#define CB_SHADER_MASK__OUTPUT2_ENABLE__SHIFT                                                                 0x8
#define CB_SHADER_MASK__OUTPUT3_ENABLE__SHIFT                                                                 0xc
#define CB_SHADER_MASK__OUTPUT4_ENABLE__SHIFT                                                                 0x10
#define CB_SHADER_MASK__OUTPUT5_ENABLE__SHIFT                                                                 0x14
#define CB_SHADER_MASK__OUTPUT6_ENABLE__SHIFT                                                                 0x18
#define CB_SHADER_MASK__OUTPUT7_ENABLE__SHIFT                                                                 0x1c
#define CB_SHADER_MASK__OUTPUT0_ENABLE_MASK                                                                   0x0000000FL
#define CB_SHADER_MASK__OUTPUT1_ENABLE_MASK                                                                   0x000000F0L
#define CB_SHADER_MASK__OUTPUT2_ENABLE_MASK                                                                   0x00000F00L
#define CB_SHADER_MASK__OUTPUT3_ENABLE_MASK                                                                   0x0000F000L
#define CB_SHADER_MASK__OUTPUT4_ENABLE_MASK                                                                   0x000F0000L
#define CB_SHADER_MASK__OUTPUT5_ENABLE_MASK                                                                   0x00F00000L
#define CB_SHADER_MASK__OUTPUT6_ENABLE_MASK                                                                   0x0F000000L
#define CB_SHADER_MASK__OUTPUT7_ENABLE_MASK                                                                   0xF0000000L
//PA_SC_GENERIC_SCISSOR_TL
#define PA_SC_GENERIC_SCISSOR_TL__TL_X__SHIFT                                                                 0x0
#define PA_SC_GENERIC_SCISSOR_TL__TL_Y__SHIFT                                                                 0x10
#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT                                                0x1f
#define PA_SC_GENERIC_SCISSOR_TL__TL_X_MASK                                                                   0x00007FFFL
#define PA_SC_GENERIC_SCISSOR_TL__TL_Y_MASK                                                                   0x7FFF0000L
#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK                                                  0x80000000L
//PA_SC_GENERIC_SCISSOR_BR
#define PA_SC_GENERIC_SCISSOR_BR__BR_X__SHIFT                                                                 0x0
#define PA_SC_GENERIC_SCISSOR_BR__BR_Y__SHIFT                                                                 0x10
#define PA_SC_GENERIC_SCISSOR_BR__BR_X_MASK                                                                   0x00007FFFL
#define PA_SC_GENERIC_SCISSOR_BR__BR_Y_MASK                                                                   0x7FFF0000L
//COHER_DEST_BASE_0
#define COHER_DEST_BASE_0__DEST_BASE_256B__SHIFT                                                              0x0
#define COHER_DEST_BASE_0__DEST_BASE_256B_MASK                                                                0xFFFFFFFFL
//COHER_DEST_BASE_1
#define COHER_DEST_BASE_1__DEST_BASE_256B__SHIFT                                                              0x0
#define COHER_DEST_BASE_1__DEST_BASE_256B_MASK                                                                0xFFFFFFFFL
//PA_SC_VPORT_SCISSOR_0_TL
#define PA_SC_VPORT_SCISSOR_0_TL__TL_X__SHIFT                                                                 0x0
#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y__SHIFT                                                                 0x10
#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE__SHIFT                                                0x1f
#define PA_SC_VPORT_SCISSOR_0_TL__TL_X_MASK                                                                   0x00007FFFL
#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y_MASK                                                                   0x7FFF0000L
#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE_MASK                                                  0x80000000L
//PA_SC_VPORT_SCISSOR_0_BR
#define PA_SC_VPORT_SCISSOR_0_BR__BR_X__SHIFT                                                                 0x0
#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y__SHIFT                                                                 0x10
#define PA_SC_VPORT_SCISSOR_0_BR__BR_X_MASK                                                                   0x00007FFFL
#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y_MASK                                                                   0x7FFF0000L
//PA_SC_VPORT_SCISSOR_1_TL
#define PA_SC_VPORT_SCISSOR_1_TL__TL_X__SHIFT                                                                 0x0
#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y__SHIFT                                                                 0x10
#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE__SHIFT                                                0x1f
#define PA_SC_VPORT_SCISSOR_1_TL__TL_X_MASK                                                                   0x00007FFFL
#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y_MASK                                                                   0x7FFF0000L
#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE_MASK                                                  0x80000000L
//PA_SC_VPORT_SCISSOR_1_BR
#define PA_SC_VPORT_SCISSOR_1_BR__BR_X__SHIFT                                                                 0x0
#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y__SHIFT                                                                 0x10
#define PA_SC_VPORT_SCISSOR_1_BR__BR_X_MASK                                                                   0x00007FFFL
#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y_MASK                                                                   0x7FFF0000L
//PA_SC_VPORT_SCISSOR_2_TL
#define PA_SC_VPORT_SCISSOR_2_TL__TL_X__SHIFT                                                                 0x0
#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y__SHIFT                                                                 0x10
#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE__SHIFT                                                0x1f
#define PA_SC_VPORT_SCISSOR_2_TL__TL_X_MASK                                                                   0x00007FFFL
#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y_MASK                                                                   0x7FFF0000L
#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE_MASK                                                  0x80000000L
//PA_SC_VPORT_SCISSOR_2_BR
#define PA_SC_VPORT_SCISSOR_2_BR__BR_X__SHIFT                                                                 0x0
#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y__SHIFT                                                                 0x10
#define PA_SC_VPORT_SCISSOR_2_BR__BR_X_MASK                                                                   0x00007FFFL
#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y_MASK                                                                   0x7FFF0000L
//PA_SC_VPORT_SCISSOR_3_TL
#define PA_SC_VPORT_SCISSOR_3_TL__TL_X__SHIFT                                                                 0x0
#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y__SHIFT                                                                 0x10
#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE__SHIFT                                                0x1f
#define PA_SC_VPORT_SCISSOR_3_TL__TL_X_MASK                                                                   0x00007FFFL
#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y_MASK                                                                   0x7FFF0000L
#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE_MASK                                                  0x80000000L
//PA_SC_VPORT_SCISSOR_3_BR
#define PA_SC_VPORT_SCISSOR_3_BR__BR_X__SHIFT                                                                 0x0
#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y__SHIFT                                                                 0x10
#define PA_SC_VPORT_SCISSOR_3_BR__BR_X_MASK                                                                   0x00007FFFL
#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y_MASK                                                                   0x7FFF0000L
//PA_SC_VPORT_SCISSOR_4_TL
#define PA_SC_VPORT_SCISSOR_4_TL__TL_X__SHIFT                                                                 0x0
#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y__SHIFT                                                                 0x10
#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE__SHIFT                                                0x1f
#define PA_SC_VPORT_SCISSOR_4_TL__TL_X_MASK                                                                   0x00007FFFL
#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y_MASK                                                                   0x7FFF0000L
#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE_MASK                                                  0x80000000L
//PA_SC_VPORT_SCISSOR_4_BR
#define PA_SC_VPORT_SCISSOR_4_BR__BR_X__SHIFT                                                                 0x0
#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y__SHIFT                                                                 0x10
#define PA_SC_VPORT_SCISSOR_4_BR__BR_X_MASK                                                                   0x00007FFFL
#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y_MASK                                                                   0x7FFF0000L
//PA_SC_VPORT_SCISSOR_5_TL
#define PA_SC_VPORT_SCISSOR_5_TL__TL_X__SHIFT                                                                 0x0
#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y__SHIFT                                                                 0x10
#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE__SHIFT                                                0x1f
#define PA_SC_VPORT_SCISSOR_5_TL__TL_X_MASK                                                                   0x00007FFFL
#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y_MASK                                                                   0x7FFF0000L
#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE_MASK                                                  0x80000000L
//PA_SC_VPORT_SCISSOR_5_BR
#define PA_SC_VPORT_SCISSOR_5_BR__BR_X__SHIFT                                                                 0x0
#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y__SHIFT                                                                 0x10
#define PA_SC_VPORT_SCISSOR_5_BR__BR_X_MASK                                                                   0x00007FFFL
#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y_MASK                                                                   0x7FFF0000L
//PA_SC_VPORT_SCISSOR_6_TL
#define PA_SC_VPORT_SCISSOR_6_TL__TL_X__SHIFT                                                                 0x0
#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y__SHIFT                                                                 0x10
#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE__SHIFT                                                0x1f
#define PA_SC_VPORT_SCISSOR_6_TL__TL_X_MASK                                                                   0x00007FFFL
#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y_MASK                                                                   0x7FFF0000L
#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE_MASK                                                  0x80000000L
//PA_SC_VPORT_SCISSOR_6_BR
#define PA_SC_VPORT_SCISSOR_6_BR__BR_X__SHIFT                                                                 0x0
#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y__SHIFT                                                                 0x10
#define PA_SC_VPORT_SCISSOR_6_BR__BR_X_MASK                                                                   0x00007FFFL
#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y_MASK                                                                   0x7FFF0000L
//PA_SC_VPORT_SCISSOR_7_TL
#define PA_SC_VPORT_SCISSOR_7_TL__TL_X__SHIFT                                                                 0x0
#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y__SHIFT                                                                 0x10
#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE__SHIFT                                                0x1f
#define PA_SC_VPORT_SCISSOR_7_TL__TL_X_MASK                                                                   0x00007FFFL
#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y_MASK                                                                   0x7FFF0000L
#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE_MASK                                                  0x80000000L
//PA_SC_VPORT_SCISSOR_7_BR
#define PA_SC_VPORT_SCISSOR_7_BR__BR_X__SHIFT                                                                 0x0
#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y__SHIFT                                                                 0x10
#define PA_SC_VPORT_SCISSOR_7_BR__BR_X_MASK                                                                   0x00007FFFL
#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y_MASK                                                                   0x7FFF0000L
//PA_SC_VPORT_SCISSOR_8_TL
#define PA_SC_VPORT_SCISSOR_8_TL__TL_X__SHIFT                                                                 0x0
#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y__SHIFT                                                                 0x10
#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE__SHIFT                                                0x1f
#define PA_SC_VPORT_SCISSOR_8_TL__TL_X_MASK                                                                   0x00007FFFL
#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y_MASK                                                                   0x7FFF0000L
#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE_MASK                                                  0x80000000L
//PA_SC_VPORT_SCISSOR_8_BR
#define PA_SC_VPORT_SCISSOR_8_BR__BR_X__SHIFT                                                                 0x0
#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y__SHIFT                                                                 0x10
#define PA_SC_VPORT_SCISSOR_8_BR__BR_X_MASK                                                                   0x00007FFFL
#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y_MASK                                                                   0x7FFF0000L
//PA_SC_VPORT_SCISSOR_9_TL
#define PA_SC_VPORT_SCISSOR_9_TL__TL_X__SHIFT                                                                 0x0
#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y__SHIFT                                                                 0x10
#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE__SHIFT                                                0x1f
#define PA_SC_VPORT_SCISSOR_9_TL__TL_X_MASK                                                                   0x00007FFFL
#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y_MASK                                                                   0x7FFF0000L
#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE_MASK                                                  0x80000000L
//PA_SC_VPORT_SCISSOR_9_BR
#define PA_SC_VPORT_SCISSOR_9_BR__BR_X__SHIFT                                                                 0x0
#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y__SHIFT                                                                 0x10
#define PA_SC_VPORT_SCISSOR_9_BR__BR_X_MASK                                                                   0x00007FFFL
#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y_MASK                                                                   0x7FFF0000L
//PA_SC_VPORT_SCISSOR_10_TL
#define PA_SC_VPORT_SCISSOR_10_TL__TL_X__SHIFT                                                                0x0
#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y__SHIFT                                                                0x10
#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE__SHIFT                                               0x1f
#define PA_SC_VPORT_SCISSOR_10_TL__TL_X_MASK                                                                  0x00007FFFL
#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y_MASK                                                                  0x7FFF0000L
#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE_MASK                                                 0x80000000L
//PA_SC_VPORT_SCISSOR_10_BR
#define PA_SC_VPORT_SCISSOR_10_BR__BR_X__SHIFT                                                                0x0
#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y__SHIFT                                                                0x10
#define PA_SC_VPORT_SCISSOR_10_BR__BR_X_MASK                                                                  0x00007FFFL
#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y_MASK                                                                  0x7FFF0000L
//PA_SC_VPORT_SCISSOR_11_TL
#define PA_SC_VPORT_SCISSOR_11_TL__TL_X__SHIFT                                                                0x0
#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y__SHIFT                                                                0x10
#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE__SHIFT                                               0x1f
#define PA_SC_VPORT_SCISSOR_11_TL__TL_X_MASK                                                                  0x00007FFFL
#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y_MASK                                                                  0x7FFF0000L
#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE_MASK                                                 0x80000000L
//PA_SC_VPORT_SCISSOR_11_BR
#define PA_SC_VPORT_SCISSOR_11_BR__BR_X__SHIFT                                                                0x0
#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y__SHIFT                                                                0x10
#define PA_SC_VPORT_SCISSOR_11_BR__BR_X_MASK                                                                  0x00007FFFL
#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y_MASK                                                                  0x7FFF0000L
//PA_SC_VPORT_SCISSOR_12_TL
#define PA_SC_VPORT_SCISSOR_12_TL__TL_X__SHIFT                                                                0x0
#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y__SHIFT                                                                0x10
#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE__SHIFT                                               0x1f
#define PA_SC_VPORT_SCISSOR_12_TL__TL_X_MASK                                                                  0x00007FFFL
#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y_MASK                                                                  0x7FFF0000L
#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE_MASK                                                 0x80000000L
//PA_SC_VPORT_SCISSOR_12_BR
#define PA_SC_VPORT_SCISSOR_12_BR__BR_X__SHIFT                                                                0x0
#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y__SHIFT                                                                0x10
#define PA_SC_VPORT_SCISSOR_12_BR__BR_X_MASK                                                                  0x00007FFFL
#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y_MASK                                                                  0x7FFF0000L
//PA_SC_VPORT_SCISSOR_13_TL
#define PA_SC_VPORT_SCISSOR_13_TL__TL_X__SHIFT                                                                0x0
#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y__SHIFT                                                                0x10
#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE__SHIFT                                               0x1f
#define PA_SC_VPORT_SCISSOR_13_TL__TL_X_MASK                                                                  0x00007FFFL
#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y_MASK                                                                  0x7FFF0000L
#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE_MASK                                                 0x80000000L
//PA_SC_VPORT_SCISSOR_13_BR
#define PA_SC_VPORT_SCISSOR_13_BR__BR_X__SHIFT                                                                0x0
#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y__SHIFT                                                                0x10
#define PA_SC_VPORT_SCISSOR_13_BR__BR_X_MASK                                                                  0x00007FFFL
#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y_MASK                                                                  0x7FFF0000L
//PA_SC_VPORT_SCISSOR_14_TL
#define PA_SC_VPORT_SCISSOR_14_TL__TL_X__SHIFT                                                                0x0
#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y__SHIFT                                                                0x10
#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE__SHIFT                                               0x1f
#define PA_SC_VPORT_SCISSOR_14_TL__TL_X_MASK                                                                  0x00007FFFL
#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y_MASK                                                                  0x7FFF0000L
#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE_MASK                                                 0x80000000L
//PA_SC_VPORT_SCISSOR_14_BR
#define PA_SC_VPORT_SCISSOR_14_BR__BR_X__SHIFT                                                                0x0
#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y__SHIFT                                                                0x10
#define PA_SC_VPORT_SCISSOR_14_BR__BR_X_MASK                                                                  0x00007FFFL
#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y_MASK                                                                  0x7FFF0000L
//PA_SC_VPORT_SCISSOR_15_TL
#define PA_SC_VPORT_SCISSOR_15_TL__TL_X__SHIFT                                                                0x0
#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y__SHIFT                                                                0x10
#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE__SHIFT                                               0x1f
#define PA_SC_VPORT_SCISSOR_15_TL__TL_X_MASK                                                                  0x00007FFFL
#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y_MASK                                                                  0x7FFF0000L
#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE_MASK                                                 0x80000000L
//PA_SC_VPORT_SCISSOR_15_BR
#define PA_SC_VPORT_SCISSOR_15_BR__BR_X__SHIFT                                                                0x0
#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y__SHIFT                                                                0x10
#define PA_SC_VPORT_SCISSOR_15_BR__BR_X_MASK                                                                  0x00007FFFL
#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y_MASK                                                                  0x7FFF0000L
//PA_SC_VPORT_ZMIN_0
#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN__SHIFT                                                                 0x0
#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN_MASK                                                                   0xFFFFFFFFL
//PA_SC_VPORT_ZMAX_0
#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX__SHIFT                                                                 0x0
#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX_MASK                                                                   0xFFFFFFFFL
//PA_SC_VPORT_ZMIN_1
#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN__SHIFT                                                                 0x0
#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN_MASK                                                                   0xFFFFFFFFL
//PA_SC_VPORT_ZMAX_1
#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX__SHIFT                                                                 0x0
#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX_MASK                                                                   0xFFFFFFFFL
//PA_SC_VPORT_ZMIN_2
#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN__SHIFT                                                                 0x0
#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN_MASK                                                                   0xFFFFFFFFL
//PA_SC_VPORT_ZMAX_2
#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX__SHIFT                                                                 0x0
#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX_MASK                                                                   0xFFFFFFFFL
//PA_SC_VPORT_ZMIN_3
#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN__SHIFT                                                                 0x0
#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN_MASK                                                                   0xFFFFFFFFL
//PA_SC_VPORT_ZMAX_3
#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX__SHIFT                                                                 0x0
#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX_MASK                                                                   0xFFFFFFFFL
//PA_SC_VPORT_ZMIN_4
#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN__SHIFT                                                                 0x0
#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN_MASK                                                                   0xFFFFFFFFL
//PA_SC_VPORT_ZMAX_4
#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX__SHIFT                                                                 0x0
#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX_MASK                                                                   0xFFFFFFFFL
//PA_SC_VPORT_ZMIN_5
#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN__SHIFT                                                                 0x0
#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN_MASK                                                                   0xFFFFFFFFL
//PA_SC_VPORT_ZMAX_5
#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX__SHIFT                                                                 0x0
#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX_MASK                                                                   0xFFFFFFFFL
//PA_SC_VPORT_ZMIN_6
#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN__SHIFT                                                                 0x0
#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN_MASK                                                                   0xFFFFFFFFL
//PA_SC_VPORT_ZMAX_6
#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX__SHIFT                                                                 0x0
#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX_MASK                                                                   0xFFFFFFFFL
//PA_SC_VPORT_ZMIN_7
#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN__SHIFT                                                                 0x0
#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN_MASK                                                                   0xFFFFFFFFL
//PA_SC_VPORT_ZMAX_7
#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX__SHIFT                                                                 0x0
#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX_MASK                                                                   0xFFFFFFFFL
//PA_SC_VPORT_ZMIN_8
#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN__SHIFT                                                                 0x0
#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN_MASK                                                                   0xFFFFFFFFL
//PA_SC_VPORT_ZMAX_8
#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX__SHIFT                                                                 0x0
#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX_MASK                                                                   0xFFFFFFFFL
//PA_SC_VPORT_ZMIN_9
#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN__SHIFT                                                                 0x0
#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN_MASK                                                                   0xFFFFFFFFL
//PA_SC_VPORT_ZMAX_9
#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX__SHIFT                                                                 0x0
#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX_MASK                                                                   0xFFFFFFFFL
//PA_SC_VPORT_ZMIN_10
#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN__SHIFT                                                                0x0
#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN_MASK                                                                  0xFFFFFFFFL
//PA_SC_VPORT_ZMAX_10
#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX__SHIFT                                                                0x0
#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX_MASK                                                                  0xFFFFFFFFL
//PA_SC_VPORT_ZMIN_11
#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN__SHIFT                                                                0x0
#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN_MASK                                                                  0xFFFFFFFFL
//PA_SC_VPORT_ZMAX_11
#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX__SHIFT                                                                0x0
#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX_MASK                                                                  0xFFFFFFFFL
//PA_SC_VPORT_ZMIN_12
#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN__SHIFT                                                                0x0
#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN_MASK                                                                  0xFFFFFFFFL
//PA_SC_VPORT_ZMAX_12
#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX__SHIFT                                                                0x0
#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX_MASK                                                                  0xFFFFFFFFL
//PA_SC_VPORT_ZMIN_13
#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN__SHIFT                                                                0x0
#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN_MASK                                                                  0xFFFFFFFFL
//PA_SC_VPORT_ZMAX_13
#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX__SHIFT                                                                0x0
#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX_MASK                                                                  0xFFFFFFFFL
//PA_SC_VPORT_ZMIN_14
#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN__SHIFT                                                                0x0
#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN_MASK                                                                  0xFFFFFFFFL
//PA_SC_VPORT_ZMAX_14
#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX__SHIFT                                                                0x0
#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX_MASK                                                                  0xFFFFFFFFL
//PA_SC_VPORT_ZMIN_15
#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN__SHIFT                                                                0x0
#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN_MASK                                                                  0xFFFFFFFFL
//PA_SC_VPORT_ZMAX_15
#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX__SHIFT                                                                0x0
#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX_MASK                                                                  0xFFFFFFFFL
//PA_SC_RASTER_CONFIG
#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT                                                               0x0
#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT                                                               0x2
#define PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT                                                                  0x4
#define PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT                                                                   0x6
#define PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT                                                                   0x7
#define PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT                                                                   0x8
#define PA_SC_RASTER_CONFIG__PKR_XSEL__SHIFT                                                                  0xa
#define PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT                                                                  0xc
#define PA_SC_RASTER_CONFIG__PKR_XSEL2__SHIFT                                                                 0xe
#define PA_SC_RASTER_CONFIG__SC_MAP__SHIFT                                                                    0x10
#define PA_SC_RASTER_CONFIG__SC_XSEL__SHIFT                                                                   0x12
#define PA_SC_RASTER_CONFIG__SC_YSEL__SHIFT                                                                   0x14
#define PA_SC_RASTER_CONFIG__SE_MAP__SHIFT                                                                    0x18
#define PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT                                                                   0x1a
#define PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT                                                                   0x1c
#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK                                                                 0x00000003L
#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK                                                                 0x0000000CL
#define PA_SC_RASTER_CONFIG__RB_XSEL2_MASK                                                                    0x00000030L
#define PA_SC_RASTER_CONFIG__RB_XSEL_MASK                                                                     0x00000040L
#define PA_SC_RASTER_CONFIG__RB_YSEL_MASK                                                                     0x00000080L
#define PA_SC_RASTER_CONFIG__PKR_MAP_MASK                                                                     0x00000300L
#define PA_SC_RASTER_CONFIG__PKR_XSEL_MASK                                                                    0x00000C00L
#define PA_SC_RASTER_CONFIG__PKR_YSEL_MASK                                                                    0x00003000L
#define PA_SC_RASTER_CONFIG__PKR_XSEL2_MASK                                                                   0x0000C000L
#define PA_SC_RASTER_CONFIG__SC_MAP_MASK                                                                      0x00030000L
#define PA_SC_RASTER_CONFIG__SC_XSEL_MASK                                                                     0x000C0000L
#define PA_SC_RASTER_CONFIG__SC_YSEL_MASK                                                                     0x00300000L
#define PA_SC_RASTER_CONFIG__SE_MAP_MASK                                                                      0x03000000L
#define PA_SC_RASTER_CONFIG__SE_XSEL_MASK                                                                     0x0C000000L
#define PA_SC_RASTER_CONFIG__SE_YSEL_MASK                                                                     0x30000000L
//PA_SC_RASTER_CONFIG_1
#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP__SHIFT                                                             0x0
#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL__SHIFT                                                            0x2
#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL__SHIFT                                                            0x4
#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP_MASK                                                               0x00000003L
#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL_MASK                                                              0x0000000CL
#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL_MASK                                                              0x00000030L
//PA_SC_SCREEN_EXTENT_CONTROL
#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE__SHIFT                                                 0x0
#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE__SHIFT                                                  0x2
#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE_MASK                                                   0x00000003L
#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE_MASK                                                    0x0000000CL
//PA_SC_TILE_STEERING_OVERRIDE
#define PA_SC_TILE_STEERING_OVERRIDE__ENABLE__SHIFT                                                           0x0
#define PA_SC_TILE_STEERING_OVERRIDE__NUM_SE__SHIFT                                                           0x1
#define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SE__SHIFT                                                    0x5
#define PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT                                                           0xc
#define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT                                                    0x10
#define PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT                                                0x14
#define PA_SC_TILE_STEERING_OVERRIDE__ENABLE_MASK                                                             0x00000001L
#define PA_SC_TILE_STEERING_OVERRIDE__NUM_SE_MASK                                                             0x00000006L
#define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SE_MASK                                                      0x00000060L
#define PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK                                                             0x00003000L
#define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK                                                      0x00030000L
#define PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK                                                  0x00300000L
//CP_PERFMON_CNTX_CNTL
#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT                                                           0x1f
#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK                                                             0x80000000L
//CP_PIPEID
#define CP_PIPEID__PIPE_ID__SHIFT                                                                             0x0
#define CP_PIPEID__PIPE_ID_MASK                                                                               0x00000003L
//CP_RINGID
#define CP_RINGID__RINGID__SHIFT                                                                              0x0
#define CP_RINGID__RINGID_MASK                                                                                0x00000003L
//CP_VMID
#define CP_VMID__VMID__SHIFT                                                                                  0x0
#define CP_VMID__VMID_MASK                                                                                    0x0000000FL
//CONTEXT_RESERVED_REG0
#define CONTEXT_RESERVED_REG0__DATA__SHIFT                                                                    0x0
#define CONTEXT_RESERVED_REG0__DATA_MASK                                                                      0xFFFFFFFFL
//CONTEXT_RESERVED_REG1
#define CONTEXT_RESERVED_REG1__DATA__SHIFT                                                                    0x0
#define CONTEXT_RESERVED_REG1__DATA_MASK                                                                      0xFFFFFFFFL
//VGT_MAX_VTX_INDX
#define VGT_MAX_VTX_INDX__MAX_INDX__SHIFT                                                                     0x0
#define VGT_MAX_VTX_INDX__MAX_INDX_MASK                                                                       0xFFFFFFFFL
//VGT_MIN_VTX_INDX
#define VGT_MIN_VTX_INDX__MIN_INDX__SHIFT                                                                     0x0
#define VGT_MIN_VTX_INDX__MIN_INDX_MASK                                                                       0xFFFFFFFFL
//VGT_INDX_OFFSET
#define VGT_INDX_OFFSET__INDX_OFFSET__SHIFT                                                                   0x0
#define VGT_INDX_OFFSET__INDX_OFFSET_MASK                                                                     0xFFFFFFFFL
//VGT_MULTI_PRIM_IB_RESET_INDX
#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT                                                       0x0
#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK                                                         0xFFFFFFFFL
//CB_RMI_GL2_CACHE_CONTROL
#define CB_RMI_GL2_CACHE_CONTROL__CMASK_WR_POLICY__SHIFT                                                      0x0
#define CB_RMI_GL2_CACHE_CONTROL__FMASK_WR_POLICY__SHIFT                                                      0x2
#define CB_RMI_GL2_CACHE_CONTROL__DCC_WR_POLICY__SHIFT                                                        0x4
#define CB_RMI_GL2_CACHE_CONTROL__COLOR_WR_POLICY__SHIFT                                                      0x6
#define CB_RMI_GL2_CACHE_CONTROL__CMASK_RD_POLICY__SHIFT                                                      0x10
#define CB_RMI_GL2_CACHE_CONTROL__FMASK_RD_POLICY__SHIFT                                                      0x12
#define CB_RMI_GL2_CACHE_CONTROL__DCC_RD_POLICY__SHIFT                                                        0x14
#define CB_RMI_GL2_CACHE_CONTROL__COLOR_RD_POLICY__SHIFT                                                      0x16
#define CB_RMI_GL2_CACHE_CONTROL__CMASK_L3_BYPASS__SHIFT                                                      0x18
#define CB_RMI_GL2_CACHE_CONTROL__FMASK_L3_BYPASS__SHIFT                                                      0x19
#define CB_RMI_GL2_CACHE_CONTROL__DCC_L3_BYPASS__SHIFT                                                        0x1a
#define CB_RMI_GL2_CACHE_CONTROL__COLOR_L3_BYPASS__SHIFT                                                      0x1b
#define CB_RMI_GL2_CACHE_CONTROL__FMASK_BIG_PAGE__SHIFT                                                       0x1e
#define CB_RMI_GL2_CACHE_CONTROL__COLOR_BIG_PAGE__SHIFT                                                       0x1f
#define CB_RMI_GL2_CACHE_CONTROL__CMASK_WR_POLICY_MASK                                                        0x00000003L
#define CB_RMI_GL2_CACHE_CONTROL__FMASK_WR_POLICY_MASK                                                        0x0000000CL
#define CB_RMI_GL2_CACHE_CONTROL__DCC_WR_POLICY_MASK                                                          0x00000030L
#define CB_RMI_GL2_CACHE_CONTROL__COLOR_WR_POLICY_MASK                                                        0x000000C0L
#define CB_RMI_GL2_CACHE_CONTROL__CMASK_RD_POLICY_MASK                                                        0x00030000L
#define CB_RMI_GL2_CACHE_CONTROL__FMASK_RD_POLICY_MASK                                                        0x000C0000L
#define CB_RMI_GL2_CACHE_CONTROL__DCC_RD_POLICY_MASK                                                          0x00300000L
#define CB_RMI_GL2_CACHE_CONTROL__COLOR_RD_POLICY_MASK                                                        0x00C00000L
#define CB_RMI_GL2_CACHE_CONTROL__CMASK_L3_BYPASS_MASK                                                        0x01000000L
#define CB_RMI_GL2_CACHE_CONTROL__FMASK_L3_BYPASS_MASK                                                        0x02000000L
#define CB_RMI_GL2_CACHE_CONTROL__DCC_L3_BYPASS_MASK                                                          0x04000000L
#define CB_RMI_GL2_CACHE_CONTROL__COLOR_L3_BYPASS_MASK                                                        0x08000000L
#define CB_RMI_GL2_CACHE_CONTROL__FMASK_BIG_PAGE_MASK                                                         0x40000000L
#define CB_RMI_GL2_CACHE_CONTROL__COLOR_BIG_PAGE_MASK                                                         0x80000000L
//CB_BLEND_RED
#define CB_BLEND_RED__BLEND_RED__SHIFT                                                                        0x0
#define CB_BLEND_RED__BLEND_RED_MASK                                                                          0xFFFFFFFFL
//CB_BLEND_GREEN
#define CB_BLEND_GREEN__BLEND_GREEN__SHIFT                                                                    0x0
#define CB_BLEND_GREEN__BLEND_GREEN_MASK                                                                      0xFFFFFFFFL
//CB_BLEND_BLUE
#define CB_BLEND_BLUE__BLEND_BLUE__SHIFT                                                                      0x0
#define CB_BLEND_BLUE__BLEND_BLUE_MASK                                                                        0xFFFFFFFFL
//CB_BLEND_ALPHA
#define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT                                                                    0x0
#define CB_BLEND_ALPHA__BLEND_ALPHA_MASK                                                                      0xFFFFFFFFL
//CB_DCC_CONTROL
#define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT                                                     0x0
#define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK__SHIFT                                                   0x2
#define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_AC01__SHIFT                                                   0x8
#define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_SINGLE__SHIFT                                                 0x9
#define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT                                                    0xa
#define CB_DCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_AC01__SHIFT                                                    0xc
#define CB_DCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_SINGLE__SHIFT                                                  0xd
#define CB_DCC_CONTROL__ENABLE_ELIMFC_SKIP_OF_REG__SHIFT                                                      0xe
#define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK                                                       0x00000001L
#define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK_MASK                                                     0x0000007CL
#define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_AC01_MASK                                                     0x00000100L
#define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_SINGLE_MASK                                                   0x00000200L
#define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK                                                      0x00000400L
#define CB_DCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_AC01_MASK                                                      0x00001000L
#define CB_DCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_SINGLE_MASK                                                    0x00002000L
#define CB_DCC_CONTROL__ENABLE_ELIMFC_SKIP_OF_REG_MASK                                                        0x00004000L
//CB_COVERAGE_OUT_CONTROL
#define CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_ENABLE__SHIFT                                                   0x0
#define CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_MRT__SHIFT                                                      0x1
#define CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_CHANNEL__SHIFT                                                  0x4
#define CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_SAMPLES__SHIFT                                                  0x8
#define CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_ENABLE_MASK                                                     0x00000001L
#define CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_MRT_MASK                                                        0x0000000EL
#define CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_CHANNEL_MASK                                                    0x00000030L
#define CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_SAMPLES_MASK                                                    0x00000F00L
//DB_STENCIL_CONTROL
#define DB_STENCIL_CONTROL__STENCILFAIL__SHIFT                                                                0x0
#define DB_STENCIL_CONTROL__STENCILZPASS__SHIFT                                                               0x4
#define DB_STENCIL_CONTROL__STENCILZFAIL__SHIFT                                                               0x8
#define DB_STENCIL_CONTROL__STENCILFAIL_BF__SHIFT                                                             0xc
#define DB_STENCIL_CONTROL__STENCILZPASS_BF__SHIFT                                                            0x10
#define DB_STENCIL_CONTROL__STENCILZFAIL_BF__SHIFT                                                            0x14
#define DB_STENCIL_CONTROL__STENCILFAIL_MASK                                                                  0x0000000FL
#define DB_STENCIL_CONTROL__STENCILZPASS_MASK                                                                 0x000000F0L
#define DB_STENCIL_CONTROL__STENCILZFAIL_MASK                                                                 0x00000F00L
#define DB_STENCIL_CONTROL__STENCILFAIL_BF_MASK                                                               0x0000F000L
#define DB_STENCIL_CONTROL__STENCILZPASS_BF_MASK                                                              0x000F0000L
#define DB_STENCIL_CONTROL__STENCILZFAIL_BF_MASK                                                              0x00F00000L
//DB_STENCILREFMASK
#define DB_STENCILREFMASK__STENCILTESTVAL__SHIFT                                                              0x0
#define DB_STENCILREFMASK__STENCILMASK__SHIFT                                                                 0x8
#define DB_STENCILREFMASK__STENCILWRITEMASK__SHIFT                                                            0x10
#define DB_STENCILREFMASK__STENCILOPVAL__SHIFT                                                                0x18
#define DB_STENCILREFMASK__STENCILTESTVAL_MASK                                                                0x000000FFL
#define DB_STENCILREFMASK__STENCILMASK_MASK                                                                   0x0000FF00L
#define DB_STENCILREFMASK__STENCILWRITEMASK_MASK                                                              0x00FF0000L
#define DB_STENCILREFMASK__STENCILOPVAL_MASK                                                                  0xFF000000L
//DB_STENCILREFMASK_BF
#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF__SHIFT                                                        0x0
#define DB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT                                                           0x8
#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT                                                      0x10
#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF__SHIFT                                                          0x18
#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF_MASK                                                          0x000000FFL
#define DB_STENCILREFMASK_BF__STENCILMASK_BF_MASK                                                             0x0000FF00L
#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK                                                        0x00FF0000L
#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF_MASK                                                            0xFF000000L
//PA_CL_VPORT_XSCALE
#define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT                                                               0x0
#define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK                                                                 0xFFFFFFFFL
//PA_CL_VPORT_XOFFSET
#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT                                                             0x0
#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK                                                               0xFFFFFFFFL
//PA_CL_VPORT_YSCALE
#define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT                                                               0x0
#define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK                                                                 0xFFFFFFFFL
//PA_CL_VPORT_YOFFSET
#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT                                                             0x0
#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK                                                               0xFFFFFFFFL
//PA_CL_VPORT_ZSCALE
#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT                                                               0x0
#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK                                                                 0xFFFFFFFFL
//PA_CL_VPORT_ZOFFSET
#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT                                                             0x0
#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK                                                               0xFFFFFFFFL
//PA_CL_VPORT_XSCALE_1
#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE__SHIFT                                                             0x0
#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE_MASK                                                               0xFFFFFFFFL
//PA_CL_VPORT_XOFFSET_1
#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET__SHIFT                                                           0x0
#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET_MASK                                                             0xFFFFFFFFL
//PA_CL_VPORT_YSCALE_1
#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE__SHIFT                                                             0x0
#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE_MASK                                                               0xFFFFFFFFL
//PA_CL_VPORT_YOFFSET_1
#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET__SHIFT                                                           0x0
#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET_MASK                                                             0xFFFFFFFFL
//PA_CL_VPORT_ZSCALE_1
#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE__SHIFT                                                             0x0
#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE_MASK                                                               0xFFFFFFFFL
//PA_CL_VPORT_ZOFFSET_1
#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET__SHIFT                                                           0x0
#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET_MASK                                                             0xFFFFFFFFL
//PA_CL_VPORT_XSCALE_2
#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE__SHIFT                                                             0x0
#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE_MASK                                                               0xFFFFFFFFL
//PA_CL_VPORT_XOFFSET_2
#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET__SHIFT                                                           0x0
#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET_MASK                                                             0xFFFFFFFFL
//PA_CL_VPORT_YSCALE_2
#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE__SHIFT                                                             0x0
#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE_MASK                                                               0xFFFFFFFFL
//PA_CL_VPORT_YOFFSET_2
#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET__SHIFT                                                           0x0
#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET_MASK                                                             0xFFFFFFFFL
//PA_CL_VPORT_ZSCALE_2
#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE__SHIFT                                                             0x0
#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE_MASK                                                               0xFFFFFFFFL
//PA_CL_VPORT_ZOFFSET_2
#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET__SHIFT                                                           0x0
#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET_MASK                                                             0xFFFFFFFFL
//PA_CL_VPORT_XSCALE_3
#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE__SHIFT                                                             0x0
#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE_MASK                                                               0xFFFFFFFFL
//PA_CL_VPORT_XOFFSET_3
#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET__SHIFT                                                           0x0
#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET_MASK                                                             0xFFFFFFFFL
//PA_CL_VPORT_YSCALE_3
#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE__SHIFT                                                             0x0
#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE_MASK                                                               0xFFFFFFFFL
//PA_CL_VPORT_YOFFSET_3
#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET__SHIFT                                                           0x0
#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET_MASK                                                             0xFFFFFFFFL
//PA_CL_VPORT_ZSCALE_3
#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE__SHIFT                                                             0x0
#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE_MASK                                                               0xFFFFFFFFL
//PA_CL_VPORT_ZOFFSET_3
#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET__SHIFT                                                           0x0
#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET_MASK                                                             0xFFFFFFFFL
//PA_CL_VPORT_XSCALE_4
#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE__SHIFT                                                             0x0
#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE_MASK                                                               0xFFFFFFFFL
//PA_CL_VPORT_XOFFSET_4
#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET__SHIFT                                                           0x0
#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET_MASK                                                             0xFFFFFFFFL
//PA_CL_VPORT_YSCALE_4
#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE__SHIFT                                                             0x0
#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE_MASK                                                               0xFFFFFFFFL
//PA_CL_VPORT_YOFFSET_4
#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET__SHIFT                                                           0x0
#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET_MASK                                                             0xFFFFFFFFL
//PA_CL_VPORT_ZSCALE_4
#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE__SHIFT                                                             0x0
#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE_MASK                                                               0xFFFFFFFFL
//PA_CL_VPORT_ZOFFSET_4
#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET__SHIFT                                                           0x0
#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET_MASK                                                             0xFFFFFFFFL
//PA_CL_VPORT_XSCALE_5
#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE__SHIFT                                                             0x0
#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE_MASK                                                               0xFFFFFFFFL
//PA_CL_VPORT_XOFFSET_5
#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET__SHIFT                                                           0x0
#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET_MASK                                                             0xFFFFFFFFL
//PA_CL_VPORT_YSCALE_5
#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE__SHIFT                                                             0x0
#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE_MASK                                                               0xFFFFFFFFL
//PA_CL_VPORT_YOFFSET_5
#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET__SHIFT                                                           0x0
#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET_MASK                                                             0xFFFFFFFFL
//PA_CL_VPORT_ZSCALE_5
#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE__SHIFT                                                             0x0
#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE_MASK                                                               0xFFFFFFFFL
//PA_CL_VPORT_ZOFFSET_5
#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET__SHIFT                                                           0x0
#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET_MASK                                                             0xFFFFFFFFL
//PA_CL_VPORT_XSCALE_6
#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE__SHIFT                                                             0x0
#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE_MASK                                                               0xFFFFFFFFL
//PA_CL_VPORT_XOFFSET_6
#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET__SHIFT                                                           0x0
#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET_MASK                                                             0xFFFFFFFFL
//PA_CL_VPORT_YSCALE_6
#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE__SHIFT                                                             0x0
#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE_MASK                                                               0xFFFFFFFFL
//PA_CL_VPORT_YOFFSET_6
#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET__SHIFT                                                           0x0
#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET_MASK                                                             0xFFFFFFFFL
//PA_CL_VPORT_ZSCALE_6
#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE__SHIFT                                                             0x0
#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE_MASK                                                               0xFFFFFFFFL
//PA_CL_VPORT_ZOFFSET_6
#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET__SHIFT                                                           0x0
#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET_MASK                                                             0xFFFFFFFFL
//PA_CL_VPORT_XSCALE_7
#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE__SHIFT                                                             0x0
#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE_MASK                                                               0xFFFFFFFFL
//PA_CL_VPORT_XOFFSET_7
#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET__SHIFT                                                           0x0
#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET_MASK                                                             0xFFFFFFFFL
//PA_CL_VPORT_YSCALE_7
#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE__SHIFT                                                             0x0
#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE_MASK                                                               0xFFFFFFFFL
//PA_CL_VPORT_YOFFSET_7
#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET__SHIFT                                                           0x0
#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET_MASK                                                             0xFFFFFFFFL
//PA_CL_VPORT_ZSCALE_7
#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE__SHIFT                                                             0x0
#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE_MASK                                                               0xFFFFFFFFL
//PA_CL_VPORT_ZOFFSET_7
#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET__SHIFT                                                           0x0
#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET_MASK                                                             0xFFFFFFFFL
//PA_CL_VPORT_XSCALE_8
#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE__SHIFT                                                             0x0
#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE_MASK                                                               0xFFFFFFFFL
//PA_CL_VPORT_XOFFSET_8
#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET__SHIFT                                                           0x0
#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET_MASK                                                             0xFFFFFFFFL
//PA_CL_VPORT_YSCALE_8
#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE__SHIFT                                                             0x0
#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE_MASK                                                               0xFFFFFFFFL
//PA_CL_VPORT_YOFFSET_8
#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET__SHIFT                                                           0x0
#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET_MASK                                                             0xFFFFFFFFL
//PA_CL_VPORT_ZSCALE_8
#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE__SHIFT                                                             0x0
#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE_MASK                                                               0xFFFFFFFFL
//PA_CL_VPORT_ZOFFSET_8
#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET__SHIFT                                                           0x0
#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET_MASK                                                             0xFFFFFFFFL
//PA_CL_VPORT_XSCALE_9
#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE__SHIFT                                                             0x0
#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE_MASK                                                               0xFFFFFFFFL
//PA_CL_VPORT_XOFFSET_9
#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET__SHIFT                                                           0x0
#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET_MASK                                                             0xFFFFFFFFL
//PA_CL_VPORT_YSCALE_9
#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE__SHIFT                                                             0x0
#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE_MASK                                                               0xFFFFFFFFL
//PA_CL_VPORT_YOFFSET_9
#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET__SHIFT                                                           0x0
#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET_MASK                                                             0xFFFFFFFFL
//PA_CL_VPORT_ZSCALE_9
#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE__SHIFT                                                             0x0
#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE_MASK                                                               0xFFFFFFFFL
//PA_CL_VPORT_ZOFFSET_9
#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET__SHIFT                                                           0x0
#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET_MASK                                                             0xFFFFFFFFL
//PA_CL_VPORT_XSCALE_10
#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE__SHIFT                                                            0x0
#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE_MASK                                                              0xFFFFFFFFL
//PA_CL_VPORT_XOFFSET_10
#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET__SHIFT                                                          0x0
#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET_MASK                                                            0xFFFFFFFFL
//PA_CL_VPORT_YSCALE_10
#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE__SHIFT                                                            0x0
#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE_MASK                                                              0xFFFFFFFFL
//PA_CL_VPORT_YOFFSET_10
#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET__SHIFT                                                          0x0
#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET_MASK                                                            0xFFFFFFFFL
//PA_CL_VPORT_ZSCALE_10
#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE__SHIFT                                                            0x0
#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE_MASK                                                              0xFFFFFFFFL
//PA_CL_VPORT_ZOFFSET_10
#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET__SHIFT                                                          0x0
#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET_MASK                                                            0xFFFFFFFFL
//PA_CL_VPORT_XSCALE_11
#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE__SHIFT                                                            0x0
#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE_MASK                                                              0xFFFFFFFFL
//PA_CL_VPORT_XOFFSET_11
#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET__SHIFT                                                          0x0
#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET_MASK                                                            0xFFFFFFFFL
//PA_CL_VPORT_YSCALE_11
#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE__SHIFT                                                            0x0
#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE_MASK                                                              0xFFFFFFFFL
//PA_CL_VPORT_YOFFSET_11
#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET__SHIFT                                                          0x0
#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET_MASK                                                            0xFFFFFFFFL
//PA_CL_VPORT_ZSCALE_11
#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE__SHIFT                                                            0x0
#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE_MASK                                                              0xFFFFFFFFL
//PA_CL_VPORT_ZOFFSET_11
#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET__SHIFT                                                          0x0
#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET_MASK                                                            0xFFFFFFFFL
//PA_CL_VPORT_XSCALE_12
#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE__SHIFT                                                            0x0
#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE_MASK                                                              0xFFFFFFFFL
//PA_CL_VPORT_XOFFSET_12
#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET__SHIFT                                                          0x0
#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET_MASK                                                            0xFFFFFFFFL
//PA_CL_VPORT_YSCALE_12
#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE__SHIFT                                                            0x0
#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE_MASK                                                              0xFFFFFFFFL
//PA_CL_VPORT_YOFFSET_12
#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET__SHIFT                                                          0x0
#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET_MASK                                                            0xFFFFFFFFL
//PA_CL_VPORT_ZSCALE_12
#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE__SHIFT                                                            0x0
#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE_MASK                                                              0xFFFFFFFFL
//PA_CL_VPORT_ZOFFSET_12
#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET__SHIFT                                                          0x0
#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET_MASK                                                            0xFFFFFFFFL
//PA_CL_VPORT_XSCALE_13
#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE__SHIFT                                                            0x0
#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE_MASK                                                              0xFFFFFFFFL
//PA_CL_VPORT_XOFFSET_13
#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET__SHIFT                                                          0x0
#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET_MASK                                                            0xFFFFFFFFL
//PA_CL_VPORT_YSCALE_13
#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE__SHIFT                                                            0x0
#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE_MASK                                                              0xFFFFFFFFL
//PA_CL_VPORT_YOFFSET_13
#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET__SHIFT                                                          0x0
#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET_MASK                                                            0xFFFFFFFFL
//PA_CL_VPORT_ZSCALE_13
#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE__SHIFT                                                            0x0
#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE_MASK                                                              0xFFFFFFFFL
//PA_CL_VPORT_ZOFFSET_13
#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET__SHIFT                                                          0x0
#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET_MASK                                                            0xFFFFFFFFL
//PA_CL_VPORT_XSCALE_14
#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE__SHIFT                                                            0x0
#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE_MASK                                                              0xFFFFFFFFL
//PA_CL_VPORT_XOFFSET_14
#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET__SHIFT                                                          0x0
#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET_MASK                                                            0xFFFFFFFFL
//PA_CL_VPORT_YSCALE_14
#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE__SHIFT                                                            0x0
#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE_MASK                                                              0xFFFFFFFFL
//PA_CL_VPORT_YOFFSET_14
#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET__SHIFT                                                          0x0
#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET_MASK                                                            0xFFFFFFFFL
//PA_CL_VPORT_ZSCALE_14
#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE__SHIFT                                                            0x0
#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE_MASK                                                              0xFFFFFFFFL
//PA_CL_VPORT_ZOFFSET_14
#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET__SHIFT                                                          0x0
#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET_MASK                                                            0xFFFFFFFFL
//PA_CL_VPORT_XSCALE_15
#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE__SHIFT                                                            0x0
#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE_MASK                                                              0xFFFFFFFFL
//PA_CL_VPORT_XOFFSET_15
#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET__SHIFT                                                          0x0
#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET_MASK                                                            0xFFFFFFFFL
//PA_CL_VPORT_YSCALE_15
#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE__SHIFT                                                            0x0
#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE_MASK                                                              0xFFFFFFFFL
//PA_CL_VPORT_YOFFSET_15
#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET__SHIFT                                                          0x0
#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET_MASK                                                            0xFFFFFFFFL
//PA_CL_VPORT_ZSCALE_15
#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE__SHIFT                                                            0x0
#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE_MASK                                                              0xFFFFFFFFL
//PA_CL_VPORT_ZOFFSET_15
#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET__SHIFT                                                          0x0
#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET_MASK                                                            0xFFFFFFFFL
//PA_CL_UCP_0_X
#define PA_CL_UCP_0_X__DATA_REGISTER__SHIFT                                                                   0x0
#define PA_CL_UCP_0_X__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
//PA_CL_UCP_0_Y
#define PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT                                                                   0x0
#define PA_CL_UCP_0_Y__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
//PA_CL_UCP_0_Z
#define PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT                                                                   0x0
#define PA_CL_UCP_0_Z__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
//PA_CL_UCP_0_W
#define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT                                                                   0x0
#define PA_CL_UCP_0_W__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
//PA_CL_UCP_1_X
#define PA_CL_UCP_1_X__DATA_REGISTER__SHIFT                                                                   0x0
#define PA_CL_UCP_1_X__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
//PA_CL_UCP_1_Y
#define PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT                                                                   0x0
#define PA_CL_UCP_1_Y__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
//PA_CL_UCP_1_Z
#define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT                                                                   0x0
#define PA_CL_UCP_1_Z__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
//PA_CL_UCP_1_W
#define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT                                                                   0x0
#define PA_CL_UCP_1_W__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
//PA_CL_UCP_2_X
#define PA_CL_UCP_2_X__DATA_REGISTER__SHIFT                                                                   0x0
#define PA_CL_UCP_2_X__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
//PA_CL_UCP_2_Y
#define PA_CL_UCP_2_Y__DATA_REGISTER__SHIFT                                                                   0x0
#define PA_CL_UCP_2_Y__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
//PA_CL_UCP_2_Z
#define PA_CL_UCP_2_Z__DATA_REGISTER__SHIFT                                                                   0x0
#define PA_CL_UCP_2_Z__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
//PA_CL_UCP_2_W
#define PA_CL_UCP_2_W__DATA_REGISTER__SHIFT                                                                   0x0
#define PA_CL_UCP_2_W__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
//PA_CL_UCP_3_X
#define PA_CL_UCP_3_X__DATA_REGISTER__SHIFT                                                                   0x0
#define PA_CL_UCP_3_X__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
//PA_CL_UCP_3_Y
#define PA_CL_UCP_3_Y__DATA_REGISTER__SHIFT                                                                   0x0
#define PA_CL_UCP_3_Y__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
//PA_CL_UCP_3_Z
#define PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT                                                                   0x0
#define PA_CL_UCP_3_Z__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
//PA_CL_UCP_3_W
#define PA_CL_UCP_3_W__DATA_REGISTER__SHIFT                                                                   0x0
#define PA_CL_UCP_3_W__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
//PA_CL_UCP_4_X
#define PA_CL_UCP_4_X__DATA_REGISTER__SHIFT                                                                   0x0
#define PA_CL_UCP_4_X__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
//PA_CL_UCP_4_Y
#define PA_CL_UCP_4_Y__DATA_REGISTER__SHIFT                                                                   0x0
#define PA_CL_UCP_4_Y__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
//PA_CL_UCP_4_Z
#define PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT                                                                   0x0
#define PA_CL_UCP_4_Z__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
//PA_CL_UCP_4_W
#define PA_CL_UCP_4_W__DATA_REGISTER__SHIFT                                                                   0x0
#define PA_CL_UCP_4_W__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
//PA_CL_UCP_5_X
#define PA_CL_UCP_5_X__DATA_REGISTER__SHIFT                                                                   0x0
#define PA_CL_UCP_5_X__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
//PA_CL_UCP_5_Y
#define PA_CL_UCP_5_Y__DATA_REGISTER__SHIFT                                                                   0x0
#define PA_CL_UCP_5_Y__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
//PA_CL_UCP_5_Z
#define PA_CL_UCP_5_Z__DATA_REGISTER__SHIFT                                                                   0x0
#define PA_CL_UCP_5_Z__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
//PA_CL_UCP_5_W
#define PA_CL_UCP_5_W__DATA_REGISTER__SHIFT                                                                   0x0
#define PA_CL_UCP_5_W__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
//PA_CL_PROG_NEAR_CLIP_Z
#define PA_CL_PROG_NEAR_CLIP_Z__DATA_REGISTER__SHIFT                                                          0x0
#define PA_CL_PROG_NEAR_CLIP_Z__DATA_REGISTER_MASK                                                            0xFFFFFFFFL
//SPI_PS_INPUT_CNTL_0
#define SPI_PS_INPUT_CNTL_0__OFFSET__SHIFT                                                                    0x0
#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL__SHIFT                                                               0x8
#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE__SHIFT                                                                0xa
#define SPI_PS_INPUT_CNTL_0__ROTATE_PC_PTR__SHIFT                                                             0xb
#define SPI_PS_INPUT_CNTL_0__CYL_WRAP__SHIFT                                                                  0xd
#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX__SHIFT                                                             0x11
#define SPI_PS_INPUT_CNTL_0__DUP__SHIFT                                                                       0x12
#define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE__SHIFT                                                          0x13
#define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1__SHIFT                                                         0x14
#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1__SHIFT                                                         0x15
#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1__SHIFT                                                       0x17
#define SPI_PS_INPUT_CNTL_0__ATTR0_VALID__SHIFT                                                               0x18
#define SPI_PS_INPUT_CNTL_0__ATTR1_VALID__SHIFT                                                               0x19
#define SPI_PS_INPUT_CNTL_0__OFFSET_MASK                                                                      0x0000003FL
#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK                                                                 0x00000300L
#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE_MASK                                                                  0x00000400L
#define SPI_PS_INPUT_CNTL_0__ROTATE_PC_PTR_MASK                                                               0x00000800L
#define SPI_PS_INPUT_CNTL_0__CYL_WRAP_MASK                                                                    0x0001E000L
#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_MASK                                                               0x00020000L
#define SPI_PS_INPUT_CNTL_0__DUP_MASK                                                                         0x00040000L
#define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE_MASK                                                            0x00080000L
#define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1_MASK                                                           0x00100000L
#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1_MASK                                                           0x00600000L
#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1_MASK                                                         0x00800000L
#define SPI_PS_INPUT_CNTL_0__ATTR0_VALID_MASK                                                                 0x01000000L
#define SPI_PS_INPUT_CNTL_0__ATTR1_VALID_MASK                                                                 0x02000000L
//SPI_PS_INPUT_CNTL_1
#define SPI_PS_INPUT_CNTL_1__OFFSET__SHIFT                                                                    0x0
#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL__SHIFT                                                               0x8
#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE__SHIFT                                                                0xa
#define SPI_PS_INPUT_CNTL_1__ROTATE_PC_PTR__SHIFT                                                             0xb
#define SPI_PS_INPUT_CNTL_1__CYL_WRAP__SHIFT                                                                  0xd
#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX__SHIFT                                                             0x11
#define SPI_PS_INPUT_CNTL_1__DUP__SHIFT                                                                       0x12
#define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE__SHIFT                                                          0x13
#define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1__SHIFT                                                         0x14
#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1__SHIFT                                                         0x15
#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1__SHIFT                                                       0x17
#define SPI_PS_INPUT_CNTL_1__ATTR0_VALID__SHIFT                                                               0x18
#define SPI_PS_INPUT_CNTL_1__ATTR1_VALID__SHIFT                                                               0x19
#define SPI_PS_INPUT_CNTL_1__OFFSET_MASK                                                                      0x0000003FL
#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_MASK                                                                 0x00000300L
#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE_MASK                                                                  0x00000400L
#define SPI_PS_INPUT_CNTL_1__ROTATE_PC_PTR_MASK                                                               0x00000800L
#define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK                                                                    0x0001E000L
#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_MASK                                                               0x00020000L
#define SPI_PS_INPUT_CNTL_1__DUP_MASK                                                                         0x00040000L
#define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE_MASK                                                            0x00080000L
#define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1_MASK                                                           0x00100000L
#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1_MASK                                                           0x00600000L
#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1_MASK                                                         0x00800000L
#define SPI_PS_INPUT_CNTL_1__ATTR0_VALID_MASK                                                                 0x01000000L
#define SPI_PS_INPUT_CNTL_1__ATTR1_VALID_MASK                                                                 0x02000000L
//SPI_PS_INPUT_CNTL_2
#define SPI_PS_INPUT_CNTL_2__OFFSET__SHIFT                                                                    0x0
#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL__SHIFT                                                               0x8
#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE__SHIFT                                                                0xa
#define SPI_PS_INPUT_CNTL_2__ROTATE_PC_PTR__SHIFT                                                             0xb
#define SPI_PS_INPUT_CNTL_2__CYL_WRAP__SHIFT                                                                  0xd
#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX__SHIFT                                                             0x11
#define SPI_PS_INPUT_CNTL_2__DUP__SHIFT                                                                       0x12
#define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE__SHIFT                                                          0x13
#define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1__SHIFT                                                         0x14
#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1__SHIFT                                                         0x15
#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1__SHIFT                                                       0x17
#define SPI_PS_INPUT_CNTL_2__ATTR0_VALID__SHIFT                                                               0x18
#define SPI_PS_INPUT_CNTL_2__ATTR1_VALID__SHIFT                                                               0x19
#define SPI_PS_INPUT_CNTL_2__OFFSET_MASK                                                                      0x0000003FL
#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_MASK                                                                 0x00000300L
#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE_MASK                                                                  0x00000400L
#define SPI_PS_INPUT_CNTL_2__ROTATE_PC_PTR_MASK                                                               0x00000800L
#define SPI_PS_INPUT_CNTL_2__CYL_WRAP_MASK                                                                    0x0001E000L
#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_MASK                                                               0x00020000L
#define SPI_PS_INPUT_CNTL_2__DUP_MASK                                                                         0x00040000L
#define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE_MASK                                                            0x00080000L
#define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1_MASK                                                           0x00100000L
#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1_MASK                                                           0x00600000L
#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1_MASK                                                         0x00800000L
#define SPI_PS_INPUT_CNTL_2__ATTR0_VALID_MASK                                                                 0x01000000L
#define SPI_PS_INPUT_CNTL_2__ATTR1_VALID_MASK                                                                 0x02000000L
//SPI_PS_INPUT_CNTL_3
#define SPI_PS_INPUT_CNTL_3__OFFSET__SHIFT                                                                    0x0
#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL__SHIFT                                                               0x8
#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE__SHIFT                                                                0xa
#define SPI_PS_INPUT_CNTL_3__ROTATE_PC_PTR__SHIFT                                                             0xb
#define SPI_PS_INPUT_CNTL_3__CYL_WRAP__SHIFT                                                                  0xd
#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX__SHIFT                                                             0x11
#define SPI_PS_INPUT_CNTL_3__DUP__SHIFT                                                                       0x12
#define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE__SHIFT                                                          0x13
#define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1__SHIFT                                                         0x14
#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1__SHIFT                                                         0x15
#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1__SHIFT                                                       0x17
#define SPI_PS_INPUT_CNTL_3__ATTR0_VALID__SHIFT                                                               0x18
#define SPI_PS_INPUT_CNTL_3__ATTR1_VALID__SHIFT                                                               0x19
#define SPI_PS_INPUT_CNTL_3__OFFSET_MASK                                                                      0x0000003FL
#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_MASK                                                                 0x00000300L
#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE_MASK                                                                  0x00000400L
#define SPI_PS_INPUT_CNTL_3__ROTATE_PC_PTR_MASK                                                               0x00000800L
#define SPI_PS_INPUT_CNTL_3__CYL_WRAP_MASK                                                                    0x0001E000L
#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_MASK                                                               0x00020000L
#define SPI_PS_INPUT_CNTL_3__DUP_MASK                                                                         0x00040000L
#define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE_MASK                                                            0x00080000L
#define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1_MASK                                                           0x00100000L
#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1_MASK                                                           0x00600000L
#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1_MASK                                                         0x00800000L
#define SPI_PS_INPUT_CNTL_3__ATTR0_VALID_MASK                                                                 0x01000000L
#define SPI_PS_INPUT_CNTL_3__ATTR1_VALID_MASK                                                                 0x02000000L
//SPI_PS_INPUT_CNTL_4
#define SPI_PS_INPUT_CNTL_4__OFFSET__SHIFT                                                                    0x0
#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL__SHIFT                                                               0x8
#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE__SHIFT                                                                0xa
#define SPI_PS_INPUT_CNTL_4__ROTATE_PC_PTR__SHIFT                                                             0xb
#define SPI_PS_INPUT_CNTL_4__CYL_WRAP__SHIFT                                                                  0xd
#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX__SHIFT                                                             0x11
#define SPI_PS_INPUT_CNTL_4__DUP__SHIFT                                                                       0x12
#define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE__SHIFT                                                          0x13
#define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1__SHIFT                                                         0x14
#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1__SHIFT                                                         0x15
#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1__SHIFT                                                       0x17
#define SPI_PS_INPUT_CNTL_4__ATTR0_VALID__SHIFT                                                               0x18
#define SPI_PS_INPUT_CNTL_4__ATTR1_VALID__SHIFT                                                               0x19
#define SPI_PS_INPUT_CNTL_4__OFFSET_MASK                                                                      0x0000003FL
#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK                                                                 0x00000300L
#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE_MASK                                                                  0x00000400L
#define SPI_PS_INPUT_CNTL_4__ROTATE_PC_PTR_MASK                                                               0x00000800L
#define SPI_PS_INPUT_CNTL_4__CYL_WRAP_MASK                                                                    0x0001E000L
#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_MASK                                                               0x00020000L
#define SPI_PS_INPUT_CNTL_4__DUP_MASK                                                                         0x00040000L
#define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE_MASK                                                            0x00080000L
#define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1_MASK                                                           0x00100000L
#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1_MASK                                                           0x00600000L
#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1_MASK                                                         0x00800000L
#define SPI_PS_INPUT_CNTL_4__ATTR0_VALID_MASK                                                                 0x01000000L
#define SPI_PS_INPUT_CNTL_4__ATTR1_VALID_MASK                                                                 0x02000000L
//SPI_PS_INPUT_CNTL_5
#define SPI_PS_INPUT_CNTL_5__OFFSET__SHIFT                                                                    0x0
#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL__SHIFT                                                               0x8
#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE__SHIFT                                                                0xa
#define SPI_PS_INPUT_CNTL_5__ROTATE_PC_PTR__SHIFT                                                             0xb
#define SPI_PS_INPUT_CNTL_5__CYL_WRAP__SHIFT                                                                  0xd
#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX__SHIFT                                                             0x11
#define SPI_PS_INPUT_CNTL_5__DUP__SHIFT                                                                       0x12
#define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE__SHIFT                                                          0x13
#define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1__SHIFT                                                         0x14
#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1__SHIFT                                                         0x15
#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1__SHIFT                                                       0x17
#define SPI_PS_INPUT_CNTL_5__ATTR0_VALID__SHIFT                                                               0x18
#define SPI_PS_INPUT_CNTL_5__ATTR1_VALID__SHIFT                                                               0x19
#define SPI_PS_INPUT_CNTL_5__OFFSET_MASK                                                                      0x0000003FL
#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_MASK                                                                 0x00000300L
#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE_MASK                                                                  0x00000400L
#define SPI_PS_INPUT_CNTL_5__ROTATE_PC_PTR_MASK                                                               0x00000800L
#define SPI_PS_INPUT_CNTL_5__CYL_WRAP_MASK                                                                    0x0001E000L
#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_MASK                                                               0x00020000L
#define SPI_PS_INPUT_CNTL_5__DUP_MASK                                                                         0x00040000L
#define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE_MASK                                                            0x00080000L
#define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1_MASK                                                           0x00100000L
#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1_MASK                                                           0x00600000L
#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1_MASK                                                         0x00800000L
#define SPI_PS_INPUT_CNTL_5__ATTR0_VALID_MASK                                                                 0x01000000L
#define SPI_PS_INPUT_CNTL_5__ATTR1_VALID_MASK                                                                 0x02000000L
//SPI_PS_INPUT_CNTL_6
#define SPI_PS_INPUT_CNTL_6__OFFSET__SHIFT                                                                    0x0
#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL__SHIFT                                                               0x8
#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE__SHIFT                                                                0xa
#define SPI_PS_INPUT_CNTL_6__ROTATE_PC_PTR__SHIFT                                                             0xb
#define SPI_PS_INPUT_CNTL_6__CYL_WRAP__SHIFT                                                                  0xd
#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX__SHIFT                                                             0x11
#define SPI_PS_INPUT_CNTL_6__DUP__SHIFT                                                                       0x12
#define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE__SHIFT                                                          0x13
#define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1__SHIFT                                                         0x14
#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1__SHIFT                                                         0x15
#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1__SHIFT                                                       0x17
#define SPI_PS_INPUT_CNTL_6__ATTR0_VALID__SHIFT                                                               0x18
#define SPI_PS_INPUT_CNTL_6__ATTR1_VALID__SHIFT                                                               0x19
#define SPI_PS_INPUT_CNTL_6__OFFSET_MASK                                                                      0x0000003FL
#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_MASK                                                                 0x00000300L
#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE_MASK                                                                  0x00000400L
#define SPI_PS_INPUT_CNTL_6__ROTATE_PC_PTR_MASK                                                               0x00000800L
#define SPI_PS_INPUT_CNTL_6__CYL_WRAP_MASK                                                                    0x0001E000L
#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_MASK                                                               0x00020000L
#define SPI_PS_INPUT_CNTL_6__DUP_MASK                                                                         0x00040000L
#define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE_MASK                                                            0x00080000L
#define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1_MASK                                                           0x00100000L
#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1_MASK                                                           0x00600000L
#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1_MASK                                                         0x00800000L
#define SPI_PS_INPUT_CNTL_6__ATTR0_VALID_MASK                                                                 0x01000000L
#define SPI_PS_INPUT_CNTL_6__ATTR1_VALID_MASK                                                                 0x02000000L
//SPI_PS_INPUT_CNTL_7
#define SPI_PS_INPUT_CNTL_7__OFFSET__SHIFT                                                                    0x0
#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL__SHIFT                                                               0x8
#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE__SHIFT                                                                0xa
#define SPI_PS_INPUT_CNTL_7__ROTATE_PC_PTR__SHIFT                                                             0xb
#define SPI_PS_INPUT_CNTL_7__CYL_WRAP__SHIFT                                                                  0xd
#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX__SHIFT                                                             0x11
#define SPI_PS_INPUT_CNTL_7__DUP__SHIFT                                                                       0x12
#define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE__SHIFT                                                          0x13
#define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1__SHIFT                                                         0x14
#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1__SHIFT                                                         0x15
#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1__SHIFT                                                       0x17
#define SPI_PS_INPUT_CNTL_7__ATTR0_VALID__SHIFT                                                               0x18
#define SPI_PS_INPUT_CNTL_7__ATTR1_VALID__SHIFT                                                               0x19
#define SPI_PS_INPUT_CNTL_7__OFFSET_MASK                                                                      0x0000003FL
#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_MASK                                                                 0x00000300L
#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE_MASK                                                                  0x00000400L
#define SPI_PS_INPUT_CNTL_7__ROTATE_PC_PTR_MASK                                                               0x00000800L
#define SPI_PS_INPUT_CNTL_7__CYL_WRAP_MASK                                                                    0x0001E000L
#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_MASK                                                               0x00020000L
#define SPI_PS_INPUT_CNTL_7__DUP_MASK                                                                         0x00040000L
#define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE_MASK                                                            0x00080000L
#define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1_MASK                                                           0x00100000L
#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1_MASK                                                           0x00600000L
#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1_MASK                                                         0x00800000L
#define SPI_PS_INPUT_CNTL_7__ATTR0_VALID_MASK                                                                 0x01000000L
#define SPI_PS_INPUT_CNTL_7__ATTR1_VALID_MASK                                                                 0x02000000L
//SPI_PS_INPUT_CNTL_8
#define SPI_PS_INPUT_CNTL_8__OFFSET__SHIFT                                                                    0x0
#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL__SHIFT                                                               0x8
#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE__SHIFT                                                                0xa
#define SPI_PS_INPUT_CNTL_8__ROTATE_PC_PTR__SHIFT                                                             0xb
#define SPI_PS_INPUT_CNTL_8__CYL_WRAP__SHIFT                                                                  0xd
#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX__SHIFT                                                             0x11
#define SPI_PS_INPUT_CNTL_8__DUP__SHIFT                                                                       0x12
#define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE__SHIFT                                                          0x13
#define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1__SHIFT                                                         0x14
#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1__SHIFT                                                         0x15
#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1__SHIFT                                                       0x17
#define SPI_PS_INPUT_CNTL_8__ATTR0_VALID__SHIFT                                                               0x18
#define SPI_PS_INPUT_CNTL_8__ATTR1_VALID__SHIFT                                                               0x19
#define SPI_PS_INPUT_CNTL_8__OFFSET_MASK                                                                      0x0000003FL
#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_MASK                                                                 0x00000300L
#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE_MASK                                                                  0x00000400L
#define SPI_PS_INPUT_CNTL_8__ROTATE_PC_PTR_MASK                                                               0x00000800L
#define SPI_PS_INPUT_CNTL_8__CYL_WRAP_MASK                                                                    0x0001E000L
#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_MASK                                                               0x00020000L
#define SPI_PS_INPUT_CNTL_8__DUP_MASK                                                                         0x00040000L
#define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE_MASK                                                            0x00080000L
#define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1_MASK                                                           0x00100000L
#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1_MASK                                                           0x00600000L
#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1_MASK                                                         0x00800000L
#define SPI_PS_INPUT_CNTL_8__ATTR0_VALID_MASK                                                                 0x01000000L
#define SPI_PS_INPUT_CNTL_8__ATTR1_VALID_MASK                                                                 0x02000000L
//SPI_PS_INPUT_CNTL_9
#define SPI_PS_INPUT_CNTL_9__OFFSET__SHIFT                                                                    0x0
#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL__SHIFT                                                               0x8
#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE__SHIFT                                                                0xa
#define SPI_PS_INPUT_CNTL_9__ROTATE_PC_PTR__SHIFT                                                             0xb
#define SPI_PS_INPUT_CNTL_9__CYL_WRAP__SHIFT                                                                  0xd
#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX__SHIFT                                                             0x11
#define SPI_PS_INPUT_CNTL_9__DUP__SHIFT                                                                       0x12
#define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE__SHIFT                                                          0x13
#define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1__SHIFT                                                         0x14
#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1__SHIFT                                                         0x15
#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1__SHIFT                                                       0x17
#define SPI_PS_INPUT_CNTL_9__ATTR0_VALID__SHIFT                                                               0x18
#define SPI_PS_INPUT_CNTL_9__ATTR1_VALID__SHIFT                                                               0x19
#define SPI_PS_INPUT_CNTL_9__OFFSET_MASK                                                                      0x0000003FL
#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_MASK                                                                 0x00000300L
#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE_MASK                                                                  0x00000400L
#define SPI_PS_INPUT_CNTL_9__ROTATE_PC_PTR_MASK                                                               0x00000800L
#define SPI_PS_INPUT_CNTL_9__CYL_WRAP_MASK                                                                    0x0001E000L
#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_MASK                                                               0x00020000L
#define SPI_PS_INPUT_CNTL_9__DUP_MASK                                                                         0x00040000L
#define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE_MASK                                                            0x00080000L
#define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1_MASK                                                           0x00100000L
#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1_MASK                                                           0x00600000L
#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1_MASK                                                         0x00800000L
#define SPI_PS_INPUT_CNTL_9__ATTR0_VALID_MASK                                                                 0x01000000L
#define SPI_PS_INPUT_CNTL_9__ATTR1_VALID_MASK                                                                 0x02000000L
//SPI_PS_INPUT_CNTL_10
#define SPI_PS_INPUT_CNTL_10__OFFSET__SHIFT                                                                   0x0
#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL__SHIFT                                                              0x8
#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE__SHIFT                                                               0xa
#define SPI_PS_INPUT_CNTL_10__ROTATE_PC_PTR__SHIFT                                                            0xb
#define SPI_PS_INPUT_CNTL_10__CYL_WRAP__SHIFT                                                                 0xd
#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX__SHIFT                                                            0x11
#define SPI_PS_INPUT_CNTL_10__DUP__SHIFT                                                                      0x12
#define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE__SHIFT                                                         0x13
#define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1__SHIFT                                                      0x17
#define SPI_PS_INPUT_CNTL_10__ATTR0_VALID__SHIFT                                                              0x18
#define SPI_PS_INPUT_CNTL_10__ATTR1_VALID__SHIFT                                                              0x19
#define SPI_PS_INPUT_CNTL_10__OFFSET_MASK                                                                     0x0000003FL
#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_MASK                                                                0x00000300L
#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE_MASK                                                                 0x00000400L
#define SPI_PS_INPUT_CNTL_10__ROTATE_PC_PTR_MASK                                                              0x00000800L
#define SPI_PS_INPUT_CNTL_10__CYL_WRAP_MASK                                                                   0x0001E000L
#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_MASK                                                              0x00020000L
#define SPI_PS_INPUT_CNTL_10__DUP_MASK                                                                        0x00040000L
#define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE_MASK                                                           0x00080000L
#define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1_MASK                                                        0x00800000L
#define SPI_PS_INPUT_CNTL_10__ATTR0_VALID_MASK                                                                0x01000000L
#define SPI_PS_INPUT_CNTL_10__ATTR1_VALID_MASK                                                                0x02000000L
//SPI_PS_INPUT_CNTL_11
#define SPI_PS_INPUT_CNTL_11__OFFSET__SHIFT                                                                   0x0
#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL__SHIFT                                                              0x8
#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE__SHIFT                                                               0xa
#define SPI_PS_INPUT_CNTL_11__ROTATE_PC_PTR__SHIFT                                                            0xb
#define SPI_PS_INPUT_CNTL_11__CYL_WRAP__SHIFT                                                                 0xd
#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX__SHIFT                                                            0x11
#define SPI_PS_INPUT_CNTL_11__DUP__SHIFT                                                                      0x12
#define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE__SHIFT                                                         0x13
#define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1__SHIFT                                                      0x17
#define SPI_PS_INPUT_CNTL_11__ATTR0_VALID__SHIFT                                                              0x18
#define SPI_PS_INPUT_CNTL_11__ATTR1_VALID__SHIFT                                                              0x19
#define SPI_PS_INPUT_CNTL_11__OFFSET_MASK                                                                     0x0000003FL
#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_MASK                                                                0x00000300L
#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE_MASK                                                                 0x00000400L
#define SPI_PS_INPUT_CNTL_11__ROTATE_PC_PTR_MASK                                                              0x00000800L
#define SPI_PS_INPUT_CNTL_11__CYL_WRAP_MASK                                                                   0x0001E000L
#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_MASK                                                              0x00020000L
#define SPI_PS_INPUT_CNTL_11__DUP_MASK                                                                        0x00040000L
#define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE_MASK                                                           0x00080000L
#define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1_MASK                                                        0x00800000L
#define SPI_PS_INPUT_CNTL_11__ATTR0_VALID_MASK                                                                0x01000000L
#define SPI_PS_INPUT_CNTL_11__ATTR1_VALID_MASK                                                                0x02000000L
//SPI_PS_INPUT_CNTL_12
#define SPI_PS_INPUT_CNTL_12__OFFSET__SHIFT                                                                   0x0
#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL__SHIFT                                                              0x8
#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE__SHIFT                                                               0xa
#define SPI_PS_INPUT_CNTL_12__ROTATE_PC_PTR__SHIFT                                                            0xb
#define SPI_PS_INPUT_CNTL_12__CYL_WRAP__SHIFT                                                                 0xd
#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX__SHIFT                                                            0x11
#define SPI_PS_INPUT_CNTL_12__DUP__SHIFT                                                                      0x12
#define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE__SHIFT                                                         0x13
#define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1__SHIFT                                                      0x17
#define SPI_PS_INPUT_CNTL_12__ATTR0_VALID__SHIFT                                                              0x18
#define SPI_PS_INPUT_CNTL_12__ATTR1_VALID__SHIFT                                                              0x19
#define SPI_PS_INPUT_CNTL_12__OFFSET_MASK                                                                     0x0000003FL
#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_MASK                                                                0x00000300L
#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE_MASK                                                                 0x00000400L
#define SPI_PS_INPUT_CNTL_12__ROTATE_PC_PTR_MASK                                                              0x00000800L
#define SPI_PS_INPUT_CNTL_12__CYL_WRAP_MASK                                                                   0x0001E000L
#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_MASK                                                              0x00020000L
#define SPI_PS_INPUT_CNTL_12__DUP_MASK                                                                        0x00040000L
#define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE_MASK                                                           0x00080000L
#define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1_MASK                                                        0x00800000L
#define SPI_PS_INPUT_CNTL_12__ATTR0_VALID_MASK                                                                0x01000000L
#define SPI_PS_INPUT_CNTL_12__ATTR1_VALID_MASK                                                                0x02000000L
//SPI_PS_INPUT_CNTL_13
#define SPI_PS_INPUT_CNTL_13__OFFSET__SHIFT                                                                   0x0
#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL__SHIFT                                                              0x8
#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE__SHIFT                                                               0xa
#define SPI_PS_INPUT_CNTL_13__ROTATE_PC_PTR__SHIFT                                                            0xb
#define SPI_PS_INPUT_CNTL_13__CYL_WRAP__SHIFT                                                                 0xd
#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX__SHIFT                                                            0x11
#define SPI_PS_INPUT_CNTL_13__DUP__SHIFT                                                                      0x12
#define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE__SHIFT                                                         0x13
#define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1__SHIFT                                                      0x17
#define SPI_PS_INPUT_CNTL_13__ATTR0_VALID__SHIFT                                                              0x18
#define SPI_PS_INPUT_CNTL_13__ATTR1_VALID__SHIFT                                                              0x19
#define SPI_PS_INPUT_CNTL_13__OFFSET_MASK                                                                     0x0000003FL
#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_MASK                                                                0x00000300L
#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE_MASK                                                                 0x00000400L
#define SPI_PS_INPUT_CNTL_13__ROTATE_PC_PTR_MASK                                                              0x00000800L
#define SPI_PS_INPUT_CNTL_13__CYL_WRAP_MASK                                                                   0x0001E000L
#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_MASK                                                              0x00020000L
#define SPI_PS_INPUT_CNTL_13__DUP_MASK                                                                        0x00040000L
#define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE_MASK                                                           0x00080000L
#define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1_MASK                                                        0x00800000L
#define SPI_PS_INPUT_CNTL_13__ATTR0_VALID_MASK                                                                0x01000000L
#define SPI_PS_INPUT_CNTL_13__ATTR1_VALID_MASK                                                                0x02000000L
//SPI_PS_INPUT_CNTL_14
#define SPI_PS_INPUT_CNTL_14__OFFSET__SHIFT                                                                   0x0
#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL__SHIFT                                                              0x8
#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE__SHIFT                                                               0xa
#define SPI_PS_INPUT_CNTL_14__ROTATE_PC_PTR__SHIFT                                                            0xb
#define SPI_PS_INPUT_CNTL_14__CYL_WRAP__SHIFT                                                                 0xd
#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX__SHIFT                                                            0x11
#define SPI_PS_INPUT_CNTL_14__DUP__SHIFT                                                                      0x12
#define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE__SHIFT                                                         0x13
#define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1__SHIFT                                                      0x17
#define SPI_PS_INPUT_CNTL_14__ATTR0_VALID__SHIFT                                                              0x18
#define SPI_PS_INPUT_CNTL_14__ATTR1_VALID__SHIFT                                                              0x19
#define SPI_PS_INPUT_CNTL_14__OFFSET_MASK                                                                     0x0000003FL
#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_MASK                                                                0x00000300L
#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE_MASK                                                                 0x00000400L
#define SPI_PS_INPUT_CNTL_14__ROTATE_PC_PTR_MASK                                                              0x00000800L
#define SPI_PS_INPUT_CNTL_14__CYL_WRAP_MASK                                                                   0x0001E000L
#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_MASK                                                              0x00020000L
#define SPI_PS_INPUT_CNTL_14__DUP_MASK                                                                        0x00040000L
#define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE_MASK                                                           0x00080000L
#define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1_MASK                                                        0x00800000L
#define SPI_PS_INPUT_CNTL_14__ATTR0_VALID_MASK                                                                0x01000000L
#define SPI_PS_INPUT_CNTL_14__ATTR1_VALID_MASK                                                                0x02000000L
//SPI_PS_INPUT_CNTL_15
#define SPI_PS_INPUT_CNTL_15__OFFSET__SHIFT                                                                   0x0
#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL__SHIFT                                                              0x8
#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE__SHIFT                                                               0xa
#define SPI_PS_INPUT_CNTL_15__ROTATE_PC_PTR__SHIFT                                                            0xb
#define SPI_PS_INPUT_CNTL_15__CYL_WRAP__SHIFT                                                                 0xd
#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX__SHIFT                                                            0x11
#define SPI_PS_INPUT_CNTL_15__DUP__SHIFT                                                                      0x12
#define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE__SHIFT                                                         0x13
#define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1__SHIFT                                                      0x17
#define SPI_PS_INPUT_CNTL_15__ATTR0_VALID__SHIFT                                                              0x18
#define SPI_PS_INPUT_CNTL_15__ATTR1_VALID__SHIFT                                                              0x19
#define SPI_PS_INPUT_CNTL_15__OFFSET_MASK                                                                     0x0000003FL
#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_MASK                                                                0x00000300L
#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE_MASK                                                                 0x00000400L
#define SPI_PS_INPUT_CNTL_15__ROTATE_PC_PTR_MASK                                                              0x00000800L
#define SPI_PS_INPUT_CNTL_15__CYL_WRAP_MASK                                                                   0x0001E000L
#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_MASK                                                              0x00020000L
#define SPI_PS_INPUT_CNTL_15__DUP_MASK                                                                        0x00040000L
#define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE_MASK                                                           0x00080000L
#define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1_MASK                                                        0x00800000L
#define SPI_PS_INPUT_CNTL_15__ATTR0_VALID_MASK                                                                0x01000000L
#define SPI_PS_INPUT_CNTL_15__ATTR1_VALID_MASK                                                                0x02000000L
//SPI_PS_INPUT_CNTL_16
#define SPI_PS_INPUT_CNTL_16__OFFSET__SHIFT                                                                   0x0
#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL__SHIFT                                                              0x8
#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE__SHIFT                                                               0xa
#define SPI_PS_INPUT_CNTL_16__ROTATE_PC_PTR__SHIFT                                                            0xb
#define SPI_PS_INPUT_CNTL_16__CYL_WRAP__SHIFT                                                                 0xd
#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX__SHIFT                                                            0x11
#define SPI_PS_INPUT_CNTL_16__DUP__SHIFT                                                                      0x12
#define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE__SHIFT                                                         0x13
#define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1__SHIFT                                                      0x17
#define SPI_PS_INPUT_CNTL_16__ATTR0_VALID__SHIFT                                                              0x18
#define SPI_PS_INPUT_CNTL_16__ATTR1_VALID__SHIFT                                                              0x19
#define SPI_PS_INPUT_CNTL_16__OFFSET_MASK                                                                     0x0000003FL
#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_MASK                                                                0x00000300L
#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE_MASK                                                                 0x00000400L
#define SPI_PS_INPUT_CNTL_16__ROTATE_PC_PTR_MASK                                                              0x00000800L
#define SPI_PS_INPUT_CNTL_16__CYL_WRAP_MASK                                                                   0x0001E000L
#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_MASK                                                              0x00020000L
#define SPI_PS_INPUT_CNTL_16__DUP_MASK                                                                        0x00040000L
#define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE_MASK                                                           0x00080000L
#define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1_MASK                                                        0x00800000L
#define SPI_PS_INPUT_CNTL_16__ATTR0_VALID_MASK                                                                0x01000000L
#define SPI_PS_INPUT_CNTL_16__ATTR1_VALID_MASK                                                                0x02000000L
//SPI_PS_INPUT_CNTL_17
#define SPI_PS_INPUT_CNTL_17__OFFSET__SHIFT                                                                   0x0
#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL__SHIFT                                                              0x8
#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE__SHIFT                                                               0xa
#define SPI_PS_INPUT_CNTL_17__ROTATE_PC_PTR__SHIFT                                                            0xb
#define SPI_PS_INPUT_CNTL_17__CYL_WRAP__SHIFT                                                                 0xd
#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX__SHIFT                                                            0x11
#define SPI_PS_INPUT_CNTL_17__DUP__SHIFT                                                                      0x12
#define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE__SHIFT                                                         0x13
#define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1__SHIFT                                                      0x17
#define SPI_PS_INPUT_CNTL_17__ATTR0_VALID__SHIFT                                                              0x18
#define SPI_PS_INPUT_CNTL_17__ATTR1_VALID__SHIFT                                                              0x19
#define SPI_PS_INPUT_CNTL_17__OFFSET_MASK                                                                     0x0000003FL
#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_MASK                                                                0x00000300L
#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE_MASK                                                                 0x00000400L
#define SPI_PS_INPUT_CNTL_17__ROTATE_PC_PTR_MASK                                                              0x00000800L
#define SPI_PS_INPUT_CNTL_17__CYL_WRAP_MASK                                                                   0x0001E000L
#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_MASK                                                              0x00020000L
#define SPI_PS_INPUT_CNTL_17__DUP_MASK                                                                        0x00040000L
#define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE_MASK                                                           0x00080000L
#define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1_MASK                                                        0x00800000L
#define SPI_PS_INPUT_CNTL_17__ATTR0_VALID_MASK                                                                0x01000000L
#define SPI_PS_INPUT_CNTL_17__ATTR1_VALID_MASK                                                                0x02000000L
//SPI_PS_INPUT_CNTL_18
#define SPI_PS_INPUT_CNTL_18__OFFSET__SHIFT                                                                   0x0
#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL__SHIFT                                                              0x8
#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE__SHIFT                                                               0xa
#define SPI_PS_INPUT_CNTL_18__ROTATE_PC_PTR__SHIFT                                                            0xb
#define SPI_PS_INPUT_CNTL_18__CYL_WRAP__SHIFT                                                                 0xd
#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX__SHIFT                                                            0x11
#define SPI_PS_INPUT_CNTL_18__DUP__SHIFT                                                                      0x12
#define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE__SHIFT                                                         0x13
#define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1__SHIFT                                                      0x17
#define SPI_PS_INPUT_CNTL_18__ATTR0_VALID__SHIFT                                                              0x18
#define SPI_PS_INPUT_CNTL_18__ATTR1_VALID__SHIFT                                                              0x19
#define SPI_PS_INPUT_CNTL_18__OFFSET_MASK                                                                     0x0000003FL
#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_MASK                                                                0x00000300L
#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE_MASK                                                                 0x00000400L
#define SPI_PS_INPUT_CNTL_18__ROTATE_PC_PTR_MASK                                                              0x00000800L
#define SPI_PS_INPUT_CNTL_18__CYL_WRAP_MASK                                                                   0x0001E000L
#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_MASK                                                              0x00020000L
#define SPI_PS_INPUT_CNTL_18__DUP_MASK                                                                        0x00040000L
#define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE_MASK                                                           0x00080000L
#define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1_MASK                                                        0x00800000L
#define SPI_PS_INPUT_CNTL_18__ATTR0_VALID_MASK                                                                0x01000000L
#define SPI_PS_INPUT_CNTL_18__ATTR1_VALID_MASK                                                                0x02000000L
//SPI_PS_INPUT_CNTL_19
#define SPI_PS_INPUT_CNTL_19__OFFSET__SHIFT                                                                   0x0
#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL__SHIFT                                                              0x8
#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE__SHIFT                                                               0xa
#define SPI_PS_INPUT_CNTL_19__ROTATE_PC_PTR__SHIFT                                                            0xb
#define SPI_PS_INPUT_CNTL_19__CYL_WRAP__SHIFT                                                                 0xd
#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX__SHIFT                                                            0x11
#define SPI_PS_INPUT_CNTL_19__DUP__SHIFT                                                                      0x12
#define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE__SHIFT                                                         0x13
#define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1__SHIFT                                                      0x17
#define SPI_PS_INPUT_CNTL_19__ATTR0_VALID__SHIFT                                                              0x18
#define SPI_PS_INPUT_CNTL_19__ATTR1_VALID__SHIFT                                                              0x19
#define SPI_PS_INPUT_CNTL_19__OFFSET_MASK                                                                     0x0000003FL
#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_MASK                                                                0x00000300L
#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE_MASK                                                                 0x00000400L
#define SPI_PS_INPUT_CNTL_19__ROTATE_PC_PTR_MASK                                                              0x00000800L
#define SPI_PS_INPUT_CNTL_19__CYL_WRAP_MASK                                                                   0x0001E000L
#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_MASK                                                              0x00020000L
#define SPI_PS_INPUT_CNTL_19__DUP_MASK                                                                        0x00040000L
#define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE_MASK                                                           0x00080000L
#define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1_MASK                                                        0x00800000L
#define SPI_PS_INPUT_CNTL_19__ATTR0_VALID_MASK                                                                0x01000000L
#define SPI_PS_INPUT_CNTL_19__ATTR1_VALID_MASK                                                                0x02000000L
//SPI_PS_INPUT_CNTL_20
#define SPI_PS_INPUT_CNTL_20__OFFSET__SHIFT                                                                   0x0
#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL__SHIFT                                                              0x8
#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE__SHIFT                                                               0xa
#define SPI_PS_INPUT_CNTL_20__ROTATE_PC_PTR__SHIFT                                                            0xb
#define SPI_PS_INPUT_CNTL_20__DUP__SHIFT                                                                      0x12
#define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE__SHIFT                                                         0x13
#define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
#define SPI_PS_INPUT_CNTL_20__ATTR0_VALID__SHIFT                                                              0x18
#define SPI_PS_INPUT_CNTL_20__ATTR1_VALID__SHIFT                                                              0x19
#define SPI_PS_INPUT_CNTL_20__OFFSET_MASK                                                                     0x0000003FL
#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_MASK                                                                0x00000300L
#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE_MASK                                                                 0x00000400L
#define SPI_PS_INPUT_CNTL_20__ROTATE_PC_PTR_MASK                                                              0x00000800L
#define SPI_PS_INPUT_CNTL_20__DUP_MASK                                                                        0x00040000L
#define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE_MASK                                                           0x00080000L
#define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
#define SPI_PS_INPUT_CNTL_20__ATTR0_VALID_MASK                                                                0x01000000L
#define SPI_PS_INPUT_CNTL_20__ATTR1_VALID_MASK                                                                0x02000000L
//SPI_PS_INPUT_CNTL_21
#define SPI_PS_INPUT_CNTL_21__OFFSET__SHIFT                                                                   0x0
#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL__SHIFT                                                              0x8
#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE__SHIFT                                                               0xa
#define SPI_PS_INPUT_CNTL_21__ROTATE_PC_PTR__SHIFT                                                            0xb
#define SPI_PS_INPUT_CNTL_21__DUP__SHIFT                                                                      0x12
#define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE__SHIFT                                                         0x13
#define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
#define SPI_PS_INPUT_CNTL_21__ATTR0_VALID__SHIFT                                                              0x18
#define SPI_PS_INPUT_CNTL_21__ATTR1_VALID__SHIFT                                                              0x19
#define SPI_PS_INPUT_CNTL_21__OFFSET_MASK                                                                     0x0000003FL
#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_MASK                                                                0x00000300L
#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE_MASK                                                                 0x00000400L
#define SPI_PS_INPUT_CNTL_21__ROTATE_PC_PTR_MASK                                                              0x00000800L
#define SPI_PS_INPUT_CNTL_21__DUP_MASK                                                                        0x00040000L
#define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE_MASK                                                           0x00080000L
#define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
#define SPI_PS_INPUT_CNTL_21__ATTR0_VALID_MASK                                                                0x01000000L
#define SPI_PS_INPUT_CNTL_21__ATTR1_VALID_MASK                                                                0x02000000L
//SPI_PS_INPUT_CNTL_22
#define SPI_PS_INPUT_CNTL_22__OFFSET__SHIFT                                                                   0x0
#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL__SHIFT                                                              0x8
#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE__SHIFT                                                               0xa
#define SPI_PS_INPUT_CNTL_22__ROTATE_PC_PTR__SHIFT                                                            0xb
#define SPI_PS_INPUT_CNTL_22__DUP__SHIFT                                                                      0x12
#define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE__SHIFT                                                         0x13
#define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
#define SPI_PS_INPUT_CNTL_22__ATTR0_VALID__SHIFT                                                              0x18
#define SPI_PS_INPUT_CNTL_22__ATTR1_VALID__SHIFT                                                              0x19
#define SPI_PS_INPUT_CNTL_22__OFFSET_MASK                                                                     0x0000003FL
#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_MASK                                                                0x00000300L
#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE_MASK                                                                 0x00000400L
#define SPI_PS_INPUT_CNTL_22__ROTATE_PC_PTR_MASK                                                              0x00000800L
#define SPI_PS_INPUT_CNTL_22__DUP_MASK                                                                        0x00040000L
#define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE_MASK                                                           0x00080000L
#define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
#define SPI_PS_INPUT_CNTL_22__ATTR0_VALID_MASK                                                                0x01000000L
#define SPI_PS_INPUT_CNTL_22__ATTR1_VALID_MASK                                                                0x02000000L
//SPI_PS_INPUT_CNTL_23
#define SPI_PS_INPUT_CNTL_23__OFFSET__SHIFT                                                                   0x0
#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL__SHIFT                                                              0x8
#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE__SHIFT                                                               0xa
#define SPI_PS_INPUT_CNTL_23__ROTATE_PC_PTR__SHIFT                                                            0xb
#define SPI_PS_INPUT_CNTL_23__DUP__SHIFT                                                                      0x12
#define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE__SHIFT                                                         0x13
#define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
#define SPI_PS_INPUT_CNTL_23__ATTR0_VALID__SHIFT                                                              0x18
#define SPI_PS_INPUT_CNTL_23__ATTR1_VALID__SHIFT                                                              0x19
#define SPI_PS_INPUT_CNTL_23__OFFSET_MASK                                                                     0x0000003FL
#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_MASK                                                                0x00000300L
#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE_MASK                                                                 0x00000400L
#define SPI_PS_INPUT_CNTL_23__ROTATE_PC_PTR_MASK                                                              0x00000800L
#define SPI_PS_INPUT_CNTL_23__DUP_MASK                                                                        0x00040000L
#define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE_MASK                                                           0x00080000L
#define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
#define SPI_PS_INPUT_CNTL_23__ATTR0_VALID_MASK                                                                0x01000000L
#define SPI_PS_INPUT_CNTL_23__ATTR1_VALID_MASK                                                                0x02000000L
//SPI_PS_INPUT_CNTL_24
#define SPI_PS_INPUT_CNTL_24__OFFSET__SHIFT                                                                   0x0
#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL__SHIFT                                                              0x8
#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE__SHIFT                                                               0xa
#define SPI_PS_INPUT_CNTL_24__ROTATE_PC_PTR__SHIFT                                                            0xb
#define SPI_PS_INPUT_CNTL_24__DUP__SHIFT                                                                      0x12
#define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE__SHIFT                                                         0x13
#define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
#define SPI_PS_INPUT_CNTL_24__ATTR0_VALID__SHIFT                                                              0x18
#define SPI_PS_INPUT_CNTL_24__ATTR1_VALID__SHIFT                                                              0x19
#define SPI_PS_INPUT_CNTL_24__OFFSET_MASK                                                                     0x0000003FL
#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_MASK                                                                0x00000300L
#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE_MASK                                                                 0x00000400L
#define SPI_PS_INPUT_CNTL_24__ROTATE_PC_PTR_MASK                                                              0x00000800L
#define SPI_PS_INPUT_CNTL_24__DUP_MASK                                                                        0x00040000L
#define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE_MASK                                                           0x00080000L
#define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
#define SPI_PS_INPUT_CNTL_24__ATTR0_VALID_MASK                                                                0x01000000L
#define SPI_PS_INPUT_CNTL_24__ATTR1_VALID_MASK                                                                0x02000000L
//SPI_PS_INPUT_CNTL_25
#define SPI_PS_INPUT_CNTL_25__OFFSET__SHIFT                                                                   0x0
#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL__SHIFT                                                              0x8
#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE__SHIFT                                                               0xa
#define SPI_PS_INPUT_CNTL_25__ROTATE_PC_PTR__SHIFT                                                            0xb
#define SPI_PS_INPUT_CNTL_25__DUP__SHIFT                                                                      0x12
#define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE__SHIFT                                                         0x13
#define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
#define SPI_PS_INPUT_CNTL_25__ATTR0_VALID__SHIFT                                                              0x18
#define SPI_PS_INPUT_CNTL_25__ATTR1_VALID__SHIFT                                                              0x19
#define SPI_PS_INPUT_CNTL_25__OFFSET_MASK                                                                     0x0000003FL
#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_MASK                                                                0x00000300L
#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE_MASK                                                                 0x00000400L
#define SPI_PS_INPUT_CNTL_25__ROTATE_PC_PTR_MASK                                                              0x00000800L
#define SPI_PS_INPUT_CNTL_25__DUP_MASK                                                                        0x00040000L
#define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE_MASK                                                           0x00080000L
#define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
#define SPI_PS_INPUT_CNTL_25__ATTR0_VALID_MASK                                                                0x01000000L
#define SPI_PS_INPUT_CNTL_25__ATTR1_VALID_MASK                                                                0x02000000L
//SPI_PS_INPUT_CNTL_26
#define SPI_PS_INPUT_CNTL_26__OFFSET__SHIFT                                                                   0x0
#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL__SHIFT                                                              0x8
#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE__SHIFT                                                               0xa
#define SPI_PS_INPUT_CNTL_26__ROTATE_PC_PTR__SHIFT                                                            0xb
#define SPI_PS_INPUT_CNTL_26__DUP__SHIFT                                                                      0x12
#define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE__SHIFT                                                         0x13
#define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
#define SPI_PS_INPUT_CNTL_26__ATTR0_VALID__SHIFT                                                              0x18
#define SPI_PS_INPUT_CNTL_26__ATTR1_VALID__SHIFT                                                              0x19
#define SPI_PS_INPUT_CNTL_26__OFFSET_MASK                                                                     0x0000003FL
#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_MASK                                                                0x00000300L
#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE_MASK                                                                 0x00000400L
#define SPI_PS_INPUT_CNTL_26__ROTATE_PC_PTR_MASK                                                              0x00000800L
#define SPI_PS_INPUT_CNTL_26__DUP_MASK                                                                        0x00040000L
#define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE_MASK                                                           0x00080000L
#define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
#define SPI_PS_INPUT_CNTL_26__ATTR0_VALID_MASK                                                                0x01000000L
#define SPI_PS_INPUT_CNTL_26__ATTR1_VALID_MASK                                                                0x02000000L
//SPI_PS_INPUT_CNTL_27
#define SPI_PS_INPUT_CNTL_27__OFFSET__SHIFT                                                                   0x0
#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL__SHIFT                                                              0x8
#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE__SHIFT                                                               0xa
#define SPI_PS_INPUT_CNTL_27__ROTATE_PC_PTR__SHIFT                                                            0xb
#define SPI_PS_INPUT_CNTL_27__DUP__SHIFT                                                                      0x12
#define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE__SHIFT                                                         0x13
#define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
#define SPI_PS_INPUT_CNTL_27__ATTR0_VALID__SHIFT                                                              0x18
#define SPI_PS_INPUT_CNTL_27__ATTR1_VALID__SHIFT                                                              0x19
#define SPI_PS_INPUT_CNTL_27__OFFSET_MASK                                                                     0x0000003FL
#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_MASK                                                                0x00000300L
#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE_MASK                                                                 0x00000400L
#define SPI_PS_INPUT_CNTL_27__ROTATE_PC_PTR_MASK                                                              0x00000800L
#define SPI_PS_INPUT_CNTL_27__DUP_MASK                                                                        0x00040000L
#define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE_MASK                                                           0x00080000L
#define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
#define SPI_PS_INPUT_CNTL_27__ATTR0_VALID_MASK                                                                0x01000000L
#define SPI_PS_INPUT_CNTL_27__ATTR1_VALID_MASK                                                                0x02000000L
//SPI_PS_INPUT_CNTL_28
#define SPI_PS_INPUT_CNTL_28__OFFSET__SHIFT                                                                   0x0
#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL__SHIFT                                                              0x8
#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE__SHIFT                                                               0xa
#define SPI_PS_INPUT_CNTL_28__ROTATE_PC_PTR__SHIFT                                                            0xb
#define SPI_PS_INPUT_CNTL_28__DUP__SHIFT                                                                      0x12
#define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE__SHIFT                                                         0x13
#define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
#define SPI_PS_INPUT_CNTL_28__ATTR0_VALID__SHIFT                                                              0x18
#define SPI_PS_INPUT_CNTL_28__ATTR1_VALID__SHIFT                                                              0x19
#define SPI_PS_INPUT_CNTL_28__OFFSET_MASK                                                                     0x0000003FL
#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_MASK                                                                0x00000300L
#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE_MASK                                                                 0x00000400L
#define SPI_PS_INPUT_CNTL_28__ROTATE_PC_PTR_MASK                                                              0x00000800L
#define SPI_PS_INPUT_CNTL_28__DUP_MASK                                                                        0x00040000L
#define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE_MASK                                                           0x00080000L
#define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
#define SPI_PS_INPUT_CNTL_28__ATTR0_VALID_MASK                                                                0x01000000L
#define SPI_PS_INPUT_CNTL_28__ATTR1_VALID_MASK                                                                0x02000000L
//SPI_PS_INPUT_CNTL_29
#define SPI_PS_INPUT_CNTL_29__OFFSET__SHIFT                                                                   0x0
#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL__SHIFT                                                              0x8
#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE__SHIFT                                                               0xa
#define SPI_PS_INPUT_CNTL_29__ROTATE_PC_PTR__SHIFT                                                            0xb
#define SPI_PS_INPUT_CNTL_29__DUP__SHIFT                                                                      0x12
#define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE__SHIFT                                                         0x13
#define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
#define SPI_PS_INPUT_CNTL_29__ATTR0_VALID__SHIFT                                                              0x18
#define SPI_PS_INPUT_CNTL_29__ATTR1_VALID__SHIFT                                                              0x19
#define SPI_PS_INPUT_CNTL_29__OFFSET_MASK                                                                     0x0000003FL
#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_MASK                                                                0x00000300L
#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE_MASK                                                                 0x00000400L
#define SPI_PS_INPUT_CNTL_29__ROTATE_PC_PTR_MASK                                                              0x00000800L
#define SPI_PS_INPUT_CNTL_29__DUP_MASK                                                                        0x00040000L
#define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE_MASK                                                           0x00080000L
#define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
#define SPI_PS_INPUT_CNTL_29__ATTR0_VALID_MASK                                                                0x01000000L
#define SPI_PS_INPUT_CNTL_29__ATTR1_VALID_MASK                                                                0x02000000L
//SPI_PS_INPUT_CNTL_30
#define SPI_PS_INPUT_CNTL_30__OFFSET__SHIFT                                                                   0x0
#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL__SHIFT                                                              0x8
#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE__SHIFT                                                               0xa
#define SPI_PS_INPUT_CNTL_30__ROTATE_PC_PTR__SHIFT                                                            0xb
#define SPI_PS_INPUT_CNTL_30__DUP__SHIFT                                                                      0x12
#define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE__SHIFT                                                         0x13
#define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
#define SPI_PS_INPUT_CNTL_30__ATTR0_VALID__SHIFT                                                              0x18
#define SPI_PS_INPUT_CNTL_30__ATTR1_VALID__SHIFT                                                              0x19
#define SPI_PS_INPUT_CNTL_30__OFFSET_MASK                                                                     0x0000003FL
#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_MASK                                                                0x00000300L
#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE_MASK                                                                 0x00000400L
#define SPI_PS_INPUT_CNTL_30__ROTATE_PC_PTR_MASK                                                              0x00000800L
#define SPI_PS_INPUT_CNTL_30__DUP_MASK                                                                        0x00040000L
#define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE_MASK                                                           0x00080000L
#define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
#define SPI_PS_INPUT_CNTL_30__ATTR0_VALID_MASK                                                                0x01000000L
#define SPI_PS_INPUT_CNTL_30__ATTR1_VALID_MASK                                                                0x02000000L
//SPI_PS_INPUT_CNTL_31
#define SPI_PS_INPUT_CNTL_31__OFFSET__SHIFT                                                                   0x0
#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL__SHIFT                                                              0x8
#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE__SHIFT                                                               0xa
#define SPI_PS_INPUT_CNTL_31__ROTATE_PC_PTR__SHIFT                                                            0xb
#define SPI_PS_INPUT_CNTL_31__DUP__SHIFT                                                                      0x12
#define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE__SHIFT                                                         0x13
#define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
#define SPI_PS_INPUT_CNTL_31__ATTR0_VALID__SHIFT                                                              0x18
#define SPI_PS_INPUT_CNTL_31__ATTR1_VALID__SHIFT                                                              0x19
#define SPI_PS_INPUT_CNTL_31__OFFSET_MASK                                                                     0x0000003FL
#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_MASK                                                                0x00000300L
#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE_MASK                                                                 0x00000400L
#define SPI_PS_INPUT_CNTL_31__ROTATE_PC_PTR_MASK                                                              0x00000800L
#define SPI_PS_INPUT_CNTL_31__DUP_MASK                                                                        0x00040000L
#define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE_MASK                                                           0x00080000L
#define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
#define SPI_PS_INPUT_CNTL_31__ATTR0_VALID_MASK                                                                0x01000000L
#define SPI_PS_INPUT_CNTL_31__ATTR1_VALID_MASK                                                                0x02000000L
//SPI_VS_OUT_CONFIG
#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT__SHIFT                                                             0x1
#define SPI_VS_OUT_CONFIG__VS_HALF_PACK__SHIFT                                                                0x6
#define SPI_VS_OUT_CONFIG__NO_PC_EXPORT__SHIFT                                                                0x7
#define SPI_VS_OUT_CONFIG__PRIM_EXPORT_COUNT__SHIFT                                                           0x8
#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT_MASK                                                               0x0000003EL
#define SPI_VS_OUT_CONFIG__VS_HALF_PACK_MASK                                                                  0x00000040L
#define SPI_VS_OUT_CONFIG__NO_PC_EXPORT_MASK                                                                  0x00000080L
#define SPI_VS_OUT_CONFIG__PRIM_EXPORT_COUNT_MASK                                                             0x00001F00L
//SPI_PS_INPUT_ENA
#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA__SHIFT                                                             0x0
#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA__SHIFT                                                             0x1
#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA__SHIFT                                                           0x2
#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA__SHIFT                                                         0x3
#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA__SHIFT                                                            0x4
#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA__SHIFT                                                            0x5
#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA__SHIFT                                                          0x6
#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA__SHIFT                                                         0x7
#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA__SHIFT                                                              0x8
#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA__SHIFT                                                              0x9
#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA__SHIFT                                                              0xa
#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA__SHIFT                                                              0xb
#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA__SHIFT                                                               0xc
#define SPI_PS_INPUT_ENA__ANCILLARY_ENA__SHIFT                                                                0xd
#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA__SHIFT                                                          0xe
#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA__SHIFT                                                             0xf
#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA_MASK                                                               0x00000001L
#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA_MASK                                                               0x00000002L
#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA_MASK                                                             0x00000004L
#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA_MASK                                                           0x00000008L
#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA_MASK                                                              0x00000010L
#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA_MASK                                                              0x00000020L
#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA_MASK                                                            0x00000040L
#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA_MASK                                                           0x00000080L
#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA_MASK                                                                0x00000100L
#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA_MASK                                                                0x00000200L
#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA_MASK                                                                0x00000400L
#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA_MASK                                                                0x00000800L
#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA_MASK                                                                 0x00001000L
#define SPI_PS_INPUT_ENA__ANCILLARY_ENA_MASK                                                                  0x00002000L
#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA_MASK                                                            0x00004000L
#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA_MASK                                                               0x00008000L
//SPI_PS_INPUT_ADDR
#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA__SHIFT                                                            0x0
#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA__SHIFT                                                            0x1
#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA__SHIFT                                                          0x2
#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA__SHIFT                                                        0x3
#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA__SHIFT                                                           0x4
#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA__SHIFT                                                           0x5
#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA__SHIFT                                                         0x6
#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA__SHIFT                                                        0x7
#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA__SHIFT                                                             0x8
#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA__SHIFT                                                             0x9
#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA__SHIFT                                                             0xa
#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA__SHIFT                                                             0xb
#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA__SHIFT                                                              0xc
#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA__SHIFT                                                               0xd
#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA__SHIFT                                                         0xe
#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA__SHIFT                                                            0xf
#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA_MASK                                                              0x00000001L
#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA_MASK                                                              0x00000002L
#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA_MASK                                                            0x00000004L
#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA_MASK                                                          0x00000008L
#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA_MASK                                                             0x00000010L
#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA_MASK                                                             0x00000020L
#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA_MASK                                                           0x00000040L
#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA_MASK                                                          0x00000080L
#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA_MASK                                                               0x00000100L
#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA_MASK                                                               0x00000200L
#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA_MASK                                                               0x00000400L
#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA_MASK                                                               0x00000800L
#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA_MASK                                                                0x00001000L
#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA_MASK                                                                 0x00002000L
#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA_MASK                                                           0x00004000L
#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA_MASK                                                              0x00008000L
//SPI_INTERP_CONTROL_0
#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT                                                           0x0
#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA__SHIFT                                                           0x1
#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X__SHIFT                                                        0x2
#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y__SHIFT                                                        0x5
#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z__SHIFT                                                        0x8
#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W__SHIFT                                                        0xb
#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1__SHIFT                                                         0xe
#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA_MASK                                                             0x00000001L
#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA_MASK                                                             0x00000002L
#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X_MASK                                                          0x0000001CL
#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y_MASK                                                          0x000000E0L
#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z_MASK                                                          0x00000700L
#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W_MASK                                                          0x00003800L
#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1_MASK                                                           0x00004000L
//SPI_PS_IN_CONTROL
#define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT                                                                  0x0
#define SPI_PS_IN_CONTROL__OFFCHIP_PARAM_EN__SHIFT                                                            0x7
#define SPI_PS_IN_CONTROL__LATE_PC_DEALLOC__SHIFT                                                             0x8
#define SPI_PS_IN_CONTROL__NUM_PRIM_INTERP__SHIFT                                                             0x9
#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE__SHIFT                                                         0xe
#define SPI_PS_IN_CONTROL__PS_W32_EN__SHIFT                                                                   0xf
#define SPI_PS_IN_CONTROL__NUM_INTERP_MASK                                                                    0x0000003FL
#define SPI_PS_IN_CONTROL__OFFCHIP_PARAM_EN_MASK                                                              0x00000080L
#define SPI_PS_IN_CONTROL__LATE_PC_DEALLOC_MASK                                                               0x00000100L
#define SPI_PS_IN_CONTROL__NUM_PRIM_INTERP_MASK                                                               0x00003E00L
#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE_MASK                                                           0x00004000L
#define SPI_PS_IN_CONTROL__PS_W32_EN_MASK                                                                     0x00008000L
//SPI_BARYC_CNTL
#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL__SHIFT                                                              0x0
#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL__SHIFT                                                            0x4
#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL__SHIFT                                                             0x8
#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL__SHIFT                                                           0xc
#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION__SHIFT                                                             0x10
#define SPI_BARYC_CNTL__POS_FLOAT_ULC__SHIFT                                                                  0x14
#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS__SHIFT                                                            0x18
#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL_MASK                                                                0x00000001L
#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL_MASK                                                              0x00000010L
#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL_MASK                                                               0x00000100L
#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL_MASK                                                             0x00001000L
#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION_MASK                                                               0x00030000L
#define SPI_BARYC_CNTL__POS_FLOAT_ULC_MASK                                                                    0x00100000L
#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS_MASK                                                              0x01000000L
//SPI_TMPRING_SIZE
#define SPI_TMPRING_SIZE__WAVES__SHIFT                                                                        0x0
#define SPI_TMPRING_SIZE__WAVESIZE__SHIFT                                                                     0xc
#define SPI_TMPRING_SIZE__WAVES_MASK                                                                          0x00000FFFL
#define SPI_TMPRING_SIZE__WAVESIZE_MASK                                                                       0x01FFF000L
//SPI_SHADER_IDX_FORMAT
#define SPI_SHADER_IDX_FORMAT__IDX0_EXPORT_FORMAT__SHIFT                                                      0x0
#define SPI_SHADER_IDX_FORMAT__IDX0_EXPORT_FORMAT_MASK                                                        0x0000000FL
//SPI_SHADER_POS_FORMAT
#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT__SHIFT                                                      0x0
#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT__SHIFT                                                      0x4
#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT__SHIFT                                                      0x8
#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT__SHIFT                                                      0xc
#define SPI_SHADER_POS_FORMAT__POS4_EXPORT_FORMAT__SHIFT                                                      0x10
#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT_MASK                                                        0x0000000FL
#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT_MASK                                                        0x000000F0L
#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT_MASK                                                        0x00000F00L
#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT_MASK                                                        0x0000F000L
#define SPI_SHADER_POS_FORMAT__POS4_EXPORT_FORMAT_MASK                                                        0x000F0000L
//SPI_SHADER_Z_FORMAT
#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT__SHIFT                                                           0x0
#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT_MASK                                                             0x0000000FL
//SPI_SHADER_COL_FORMAT
#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT__SHIFT                                                      0x0
#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT__SHIFT                                                      0x4
#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT__SHIFT                                                      0x8
#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT__SHIFT                                                      0xc
#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT__SHIFT                                                      0x10
#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT__SHIFT                                                      0x14
#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT__SHIFT                                                      0x18
#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT__SHIFT                                                      0x1c
#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT_MASK                                                        0x0000000FL
#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT_MASK                                                        0x000000F0L
#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT_MASK                                                        0x00000F00L
#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT_MASK                                                        0x0000F000L
#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT_MASK                                                        0x000F0000L
#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT_MASK                                                        0x00F00000L
#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT_MASK                                                        0x0F000000L
#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT_MASK                                                        0xF0000000L
//SX_PS_DOWNCONVERT_CONTROL
#define SX_PS_DOWNCONVERT_CONTROL__MRT0_FMT_MAPPING_DISABLE__SHIFT                                            0x0
#define SX_PS_DOWNCONVERT_CONTROL__MRT1_FMT_MAPPING_DISABLE__SHIFT                                            0x1
#define SX_PS_DOWNCONVERT_CONTROL__MRT2_FMT_MAPPING_DISABLE__SHIFT                                            0x2
#define SX_PS_DOWNCONVERT_CONTROL__MRT3_FMT_MAPPING_DISABLE__SHIFT                                            0x3
#define SX_PS_DOWNCONVERT_CONTROL__MRT4_FMT_MAPPING_DISABLE__SHIFT                                            0x4
#define SX_PS_DOWNCONVERT_CONTROL__MRT5_FMT_MAPPING_DISABLE__SHIFT                                            0x5
#define SX_PS_DOWNCONVERT_CONTROL__MRT6_FMT_MAPPING_DISABLE__SHIFT                                            0x6
#define SX_PS_DOWNCONVERT_CONTROL__MRT7_FMT_MAPPING_DISABLE__SHIFT                                            0x7
#define SX_PS_DOWNCONVERT_CONTROL__MRT0_FMT_MAPPING_DISABLE_MASK                                              0x00000001L
#define SX_PS_DOWNCONVERT_CONTROL__MRT1_FMT_MAPPING_DISABLE_MASK                                              0x00000002L
#define SX_PS_DOWNCONVERT_CONTROL__MRT2_FMT_MAPPING_DISABLE_MASK                                              0x00000004L
#define SX_PS_DOWNCONVERT_CONTROL__MRT3_FMT_MAPPING_DISABLE_MASK                                              0x00000008L
#define SX_PS_DOWNCONVERT_CONTROL__MRT4_FMT_MAPPING_DISABLE_MASK                                              0x00000010L
#define SX_PS_DOWNCONVERT_CONTROL__MRT5_FMT_MAPPING_DISABLE_MASK                                              0x00000020L
#define SX_PS_DOWNCONVERT_CONTROL__MRT6_FMT_MAPPING_DISABLE_MASK                                              0x00000040L
#define SX_PS_DOWNCONVERT_CONTROL__MRT7_FMT_MAPPING_DISABLE_MASK                                              0x00000080L
//SX_PS_DOWNCONVERT
#define SX_PS_DOWNCONVERT__MRT0__SHIFT                                                                        0x0
#define SX_PS_DOWNCONVERT__MRT1__SHIFT                                                                        0x4
#define SX_PS_DOWNCONVERT__MRT2__SHIFT                                                                        0x8
#define SX_PS_DOWNCONVERT__MRT3__SHIFT                                                                        0xc
#define SX_PS_DOWNCONVERT__MRT4__SHIFT                                                                        0x10
#define SX_PS_DOWNCONVERT__MRT5__SHIFT                                                                        0x14
#define SX_PS_DOWNCONVERT__MRT6__SHIFT                                                                        0x18
#define SX_PS_DOWNCONVERT__MRT7__SHIFT                                                                        0x1c
#define SX_PS_DOWNCONVERT__MRT0_MASK                                                                          0x0000000FL
#define SX_PS_DOWNCONVERT__MRT1_MASK                                                                          0x000000F0L
#define SX_PS_DOWNCONVERT__MRT2_MASK                                                                          0x00000F00L
#define SX_PS_DOWNCONVERT__MRT3_MASK                                                                          0x0000F000L
#define SX_PS_DOWNCONVERT__MRT4_MASK                                                                          0x000F0000L
#define SX_PS_DOWNCONVERT__MRT5_MASK                                                                          0x00F00000L
#define SX_PS_DOWNCONVERT__MRT6_MASK                                                                          0x0F000000L
#define SX_PS_DOWNCONVERT__MRT7_MASK                                                                          0xF0000000L
//SX_BLEND_OPT_EPSILON
#define SX_BLEND_OPT_EPSILON__MRT0_EPSILON__SHIFT                                                             0x0
#define SX_BLEND_OPT_EPSILON__MRT1_EPSILON__SHIFT                                                             0x4
#define SX_BLEND_OPT_EPSILON__MRT2_EPSILON__SHIFT                                                             0x8
#define SX_BLEND_OPT_EPSILON__MRT3_EPSILON__SHIFT                                                             0xc
#define SX_BLEND_OPT_EPSILON__MRT4_EPSILON__SHIFT                                                             0x10
#define SX_BLEND_OPT_EPSILON__MRT5_EPSILON__SHIFT                                                             0x14
#define SX_BLEND_OPT_EPSILON__MRT6_EPSILON__SHIFT                                                             0x18
#define SX_BLEND_OPT_EPSILON__MRT7_EPSILON__SHIFT                                                             0x1c
#define SX_BLEND_OPT_EPSILON__MRT0_EPSILON_MASK                                                               0x0000000FL
#define SX_BLEND_OPT_EPSILON__MRT1_EPSILON_MASK                                                               0x000000F0L
#define SX_BLEND_OPT_EPSILON__MRT2_EPSILON_MASK                                                               0x00000F00L
#define SX_BLEND_OPT_EPSILON__MRT3_EPSILON_MASK                                                               0x0000F000L
#define SX_BLEND_OPT_EPSILON__MRT4_EPSILON_MASK                                                               0x000F0000L
#define SX_BLEND_OPT_EPSILON__MRT5_EPSILON_MASK                                                               0x00F00000L
#define SX_BLEND_OPT_EPSILON__MRT6_EPSILON_MASK                                                               0x0F000000L
#define SX_BLEND_OPT_EPSILON__MRT7_EPSILON_MASK                                                               0xF0000000L
//SX_BLEND_OPT_CONTROL
#define SX_BLEND_OPT_CONTROL__MRT0_COLOR_OPT_DISABLE__SHIFT                                                   0x0
#define SX_BLEND_OPT_CONTROL__MRT0_ALPHA_OPT_DISABLE__SHIFT                                                   0x1
#define SX_BLEND_OPT_CONTROL__MRT1_COLOR_OPT_DISABLE__SHIFT                                                   0x4
#define SX_BLEND_OPT_CONTROL__MRT1_ALPHA_OPT_DISABLE__SHIFT                                                   0x5
#define SX_BLEND_OPT_CONTROL__MRT2_COLOR_OPT_DISABLE__SHIFT                                                   0x8
#define SX_BLEND_OPT_CONTROL__MRT2_ALPHA_OPT_DISABLE__SHIFT                                                   0x9
#define SX_BLEND_OPT_CONTROL__MRT3_COLOR_OPT_DISABLE__SHIFT                                                   0xc
#define SX_BLEND_OPT_CONTROL__MRT3_ALPHA_OPT_DISABLE__SHIFT                                                   0xd
#define SX_BLEND_OPT_CONTROL__MRT4_COLOR_OPT_DISABLE__SHIFT                                                   0x10
#define SX_BLEND_OPT_CONTROL__MRT4_ALPHA_OPT_DISABLE__SHIFT                                                   0x11
#define SX_BLEND_OPT_CONTROL__MRT5_COLOR_OPT_DISABLE__SHIFT                                                   0x14
#define SX_BLEND_OPT_CONTROL__MRT5_ALPHA_OPT_DISABLE__SHIFT                                                   0x15
#define SX_BLEND_OPT_CONTROL__MRT6_COLOR_OPT_DISABLE__SHIFT                                                   0x18
#define SX_BLEND_OPT_CONTROL__MRT6_ALPHA_OPT_DISABLE__SHIFT                                                   0x19
#define SX_BLEND_OPT_CONTROL__MRT7_COLOR_OPT_DISABLE__SHIFT                                                   0x1c
#define SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE__SHIFT                                                   0x1d
#define SX_BLEND_OPT_CONTROL__PIXEN_ZERO_OPT_DISABLE__SHIFT                                                   0x1f
#define SX_BLEND_OPT_CONTROL__MRT0_COLOR_OPT_DISABLE_MASK                                                     0x00000001L
#define SX_BLEND_OPT_CONTROL__MRT0_ALPHA_OPT_DISABLE_MASK                                                     0x00000002L
#define SX_BLEND_OPT_CONTROL__MRT1_COLOR_OPT_DISABLE_MASK                                                     0x00000010L
#define SX_BLEND_OPT_CONTROL__MRT1_ALPHA_OPT_DISABLE_MASK                                                     0x00000020L
#define SX_BLEND_OPT_CONTROL__MRT2_COLOR_OPT_DISABLE_MASK                                                     0x00000100L
#define SX_BLEND_OPT_CONTROL__MRT2_ALPHA_OPT_DISABLE_MASK                                                     0x00000200L
#define SX_BLEND_OPT_CONTROL__MRT3_COLOR_OPT_DISABLE_MASK                                                     0x00001000L
#define SX_BLEND_OPT_CONTROL__MRT3_ALPHA_OPT_DISABLE_MASK                                                     0x00002000L
#define SX_BLEND_OPT_CONTROL__MRT4_COLOR_OPT_DISABLE_MASK                                                     0x00010000L
#define SX_BLEND_OPT_CONTROL__MRT4_ALPHA_OPT_DISABLE_MASK                                                     0x00020000L
#define SX_BLEND_OPT_CONTROL__MRT5_COLOR_OPT_DISABLE_MASK                                                     0x00100000L
#define SX_BLEND_OPT_CONTROL__MRT5_ALPHA_OPT_DISABLE_MASK                                                     0x00200000L
#define SX_BLEND_OPT_CONTROL__MRT6_COLOR_OPT_DISABLE_MASK                                                     0x01000000L
#define SX_BLEND_OPT_CONTROL__MRT6_ALPHA_OPT_DISABLE_MASK                                                     0x02000000L
#define SX_BLEND_OPT_CONTROL__MRT7_COLOR_OPT_DISABLE_MASK                                                     0x10000000L
#define SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE_MASK                                                     0x20000000L
#define SX_BLEND_OPT_CONTROL__PIXEN_ZERO_OPT_DISABLE_MASK                                                     0x80000000L
//SX_MRT0_BLEND_OPT
#define SX_MRT0_BLEND_OPT__COLOR_SRC_OPT__SHIFT                                                               0x0
#define SX_MRT0_BLEND_OPT__COLOR_DST_OPT__SHIFT                                                               0x4
#define SX_MRT0_BLEND_OPT__COLOR_COMB_FCN__SHIFT                                                              0x8
#define SX_MRT0_BLEND_OPT__ALPHA_SRC_OPT__SHIFT                                                               0x10
#define SX_MRT0_BLEND_OPT__ALPHA_DST_OPT__SHIFT                                                               0x14
#define SX_MRT0_BLEND_OPT__ALPHA_COMB_FCN__SHIFT                                                              0x18
#define SX_MRT0_BLEND_OPT__COLOR_SRC_OPT_MASK                                                                 0x00000007L
#define SX_MRT0_BLEND_OPT__COLOR_DST_OPT_MASK                                                                 0x00000070L
#define SX_MRT0_BLEND_OPT__COLOR_COMB_FCN_MASK                                                                0x00000700L
#define SX_MRT0_BLEND_OPT__ALPHA_SRC_OPT_MASK                                                                 0x00070000L
#define SX_MRT0_BLEND_OPT__ALPHA_DST_OPT_MASK                                                                 0x00700000L
#define SX_MRT0_BLEND_OPT__ALPHA_COMB_FCN_MASK                                                                0x07000000L
//SX_MRT1_BLEND_OPT
#define SX_MRT1_BLEND_OPT__COLOR_SRC_OPT__SHIFT                                                               0x0
#define SX_MRT1_BLEND_OPT__COLOR_DST_OPT__SHIFT                                                               0x4
#define SX_MRT1_BLEND_OPT__COLOR_COMB_FCN__SHIFT                                                              0x8
#define SX_MRT1_BLEND_OPT__ALPHA_SRC_OPT__SHIFT                                                               0x10
#define SX_MRT1_BLEND_OPT__ALPHA_DST_OPT__SHIFT                                                               0x14
#define SX_MRT1_BLEND_OPT__ALPHA_COMB_FCN__SHIFT                                                              0x18
#define SX_MRT1_BLEND_OPT__COLOR_SRC_OPT_MASK                                                                 0x00000007L
#define SX_MRT1_BLEND_OPT__COLOR_DST_OPT_MASK                                                                 0x00000070L
#define SX_MRT1_BLEND_OPT__COLOR_COMB_FCN_MASK                                                                0x00000700L
#define SX_MRT1_BLEND_OPT__ALPHA_SRC_OPT_MASK                                                                 0x00070000L
#define SX_MRT1_BLEND_OPT__ALPHA_DST_OPT_MASK                                                                 0x00700000L
#define SX_MRT1_BLEND_OPT__ALPHA_COMB_FCN_MASK                                                                0x07000000L
//SX_MRT2_BLEND_OPT
#define SX_MRT2_BLEND_OPT__COLOR_SRC_OPT__SHIFT                                                               0x0
#define SX_MRT2_BLEND_OPT__COLOR_DST_OPT__SHIFT                                                               0x4
#define SX_MRT2_BLEND_OPT__COLOR_COMB_FCN__SHIFT                                                              0x8
#define SX_MRT2_BLEND_OPT__ALPHA_SRC_OPT__SHIFT                                                               0x10
#define SX_MRT2_BLEND_OPT__ALPHA_DST_OPT__SHIFT                                                               0x14
#define SX_MRT2_BLEND_OPT__ALPHA_COMB_FCN__SHIFT                                                              0x18
#define SX_MRT2_BLEND_OPT__COLOR_SRC_OPT_MASK                                                                 0x00000007L
#define SX_MRT2_BLEND_OPT__COLOR_DST_OPT_MASK                                                                 0x00000070L
#define SX_MRT2_BLEND_OPT__COLOR_COMB_FCN_MASK                                                                0x00000700L
#define SX_MRT2_BLEND_OPT__ALPHA_SRC_OPT_MASK                                                                 0x00070000L
#define SX_MRT2_BLEND_OPT__ALPHA_DST_OPT_MASK                                                                 0x00700000L
#define SX_MRT2_BLEND_OPT__ALPHA_COMB_FCN_MASK                                                                0x07000000L
//SX_MRT3_BLEND_OPT
#define SX_MRT3_BLEND_OPT__COLOR_SRC_OPT__SHIFT                                                               0x0
#define SX_MRT3_BLEND_OPT__COLOR_DST_OPT__SHIFT                                                               0x4
#define SX_MRT3_BLEND_OPT__COLOR_COMB_FCN__SHIFT                                                              0x8
#define SX_MRT3_BLEND_OPT__ALPHA_SRC_OPT__SHIFT                                                               0x10
#define SX_MRT3_BLEND_OPT__ALPHA_DST_OPT__SHIFT                                                               0x14
#define SX_MRT3_BLEND_OPT__ALPHA_COMB_FCN__SHIFT                                                              0x18
#define SX_MRT3_BLEND_OPT__COLOR_SRC_OPT_MASK                                                                 0x00000007L
#define SX_MRT3_BLEND_OPT__COLOR_DST_OPT_MASK                                                                 0x00000070L
#define SX_MRT3_BLEND_OPT__COLOR_COMB_FCN_MASK                                                                0x00000700L
#define SX_MRT3_BLEND_OPT__ALPHA_SRC_OPT_MASK                                                                 0x00070000L
#define SX_MRT3_BLEND_OPT__ALPHA_DST_OPT_MASK                                                                 0x00700000L
#define SX_MRT3_BLEND_OPT__ALPHA_COMB_FCN_MASK                                                                0x07000000L
//SX_MRT4_BLEND_OPT
#define SX_MRT4_BLEND_OPT__COLOR_SRC_OPT__SHIFT                                                               0x0
#define SX_MRT4_BLEND_OPT__COLOR_DST_OPT__SHIFT                                                               0x4
#define SX_MRT4_BLEND_OPT__COLOR_COMB_FCN__SHIFT                                                              0x8
#define SX_MRT4_BLEND_OPT__ALPHA_SRC_OPT__SHIFT                                                               0x10
#define SX_MRT4_BLEND_OPT__ALPHA_DST_OPT__SHIFT                                                               0x14
#define SX_MRT4_BLEND_OPT__ALPHA_COMB_FCN__SHIFT                                                              0x18
#define SX_MRT4_BLEND_OPT__COLOR_SRC_OPT_MASK                                                                 0x00000007L
#define SX_MRT4_BLEND_OPT__COLOR_DST_OPT_MASK                                                                 0x00000070L
#define SX_MRT4_BLEND_OPT__COLOR_COMB_FCN_MASK                                                                0x00000700L
#define SX_MRT4_BLEND_OPT__ALPHA_SRC_OPT_MASK                                                                 0x00070000L
#define SX_MRT4_BLEND_OPT__ALPHA_DST_OPT_MASK                                                                 0x00700000L
#define SX_MRT4_BLEND_OPT__ALPHA_COMB_FCN_MASK                                                                0x07000000L
//SX_MRT5_BLEND_OPT
#define SX_MRT5_BLEND_OPT__COLOR_SRC_OPT__SHIFT                                                               0x0
#define SX_MRT5_BLEND_OPT__COLOR_DST_OPT__SHIFT                                                               0x4
#define SX_MRT5_BLEND_OPT__COLOR_COMB_FCN__SHIFT                                                              0x8
#define SX_MRT5_BLEND_OPT__ALPHA_SRC_OPT__SHIFT                                                               0x10
#define SX_MRT5_BLEND_OPT__ALPHA_DST_OPT__SHIFT                                                               0x14
#define SX_MRT5_BLEND_OPT__ALPHA_COMB_FCN__SHIFT                                                              0x18
#define SX_MRT5_BLEND_OPT__COLOR_SRC_OPT_MASK                                                                 0x00000007L
#define SX_MRT5_BLEND_OPT__COLOR_DST_OPT_MASK                                                                 0x00000070L
#define SX_MRT5_BLEND_OPT__COLOR_COMB_FCN_MASK                                                                0x00000700L
#define SX_MRT5_BLEND_OPT__ALPHA_SRC_OPT_MASK                                                                 0x00070000L
#define SX_MRT5_BLEND_OPT__ALPHA_DST_OPT_MASK                                                                 0x00700000L
#define SX_MRT5_BLEND_OPT__ALPHA_COMB_FCN_MASK                                                                0x07000000L
//SX_MRT6_BLEND_OPT
#define SX_MRT6_BLEND_OPT__COLOR_SRC_OPT__SHIFT                                                               0x0
#define SX_MRT6_BLEND_OPT__COLOR_DST_OPT__SHIFT                                                               0x4
#define SX_MRT6_BLEND_OPT__COLOR_COMB_FCN__SHIFT                                                              0x8
#define SX_MRT6_BLEND_OPT__ALPHA_SRC_OPT__SHIFT                                                               0x10
#define SX_MRT6_BLEND_OPT__ALPHA_DST_OPT__SHIFT                                                               0x14
#define SX_MRT6_BLEND_OPT__ALPHA_COMB_FCN__SHIFT                                                              0x18
#define SX_MRT6_BLEND_OPT__COLOR_SRC_OPT_MASK                                                                 0x00000007L
#define SX_MRT6_BLEND_OPT__COLOR_DST_OPT_MASK                                                                 0x00000070L
#define SX_MRT6_BLEND_OPT__COLOR_COMB_FCN_MASK                                                                0x00000700L
#define SX_MRT6_BLEND_OPT__ALPHA_SRC_OPT_MASK                                                                 0x00070000L
#define SX_MRT6_BLEND_OPT__ALPHA_DST_OPT_MASK                                                                 0x00700000L
#define SX_MRT6_BLEND_OPT__ALPHA_COMB_FCN_MASK                                                                0x07000000L
//SX_MRT7_BLEND_OPT
#define SX_MRT7_BLEND_OPT__COLOR_SRC_OPT__SHIFT                                                               0x0
#define SX_MRT7_BLEND_OPT__COLOR_DST_OPT__SHIFT                                                               0x4
#define SX_MRT7_BLEND_OPT__COLOR_COMB_FCN__SHIFT                                                              0x8
#define SX_MRT7_BLEND_OPT__ALPHA_SRC_OPT__SHIFT                                                               0x10
#define SX_MRT7_BLEND_OPT__ALPHA_DST_OPT__SHIFT                                                               0x14
#define SX_MRT7_BLEND_OPT__ALPHA_COMB_FCN__SHIFT                                                              0x18
#define SX_MRT7_BLEND_OPT__COLOR_SRC_OPT_MASK                                                                 0x00000007L
#define SX_MRT7_BLEND_OPT__COLOR_DST_OPT_MASK                                                                 0x00000070L
#define SX_MRT7_BLEND_OPT__COLOR_COMB_FCN_MASK                                                                0x00000700L
#define SX_MRT7_BLEND_OPT__ALPHA_SRC_OPT_MASK                                                                 0x00070000L
#define SX_MRT7_BLEND_OPT__ALPHA_DST_OPT_MASK                                                                 0x00700000L
#define SX_MRT7_BLEND_OPT__ALPHA_COMB_FCN_MASK                                                                0x07000000L
//CB_BLEND0_CONTROL
#define CB_BLEND0_CONTROL__COLOR_SRCBLEND__SHIFT                                                              0x0
#define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT                                                              0x5
#define CB_BLEND0_CONTROL__COLOR_DESTBLEND__SHIFT                                                             0x8
#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT                                                              0x10
#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT                                                              0x15
#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT                                                             0x18
#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT                                                        0x1d
#define CB_BLEND0_CONTROL__ENABLE__SHIFT                                                                      0x1e
#define CB_BLEND0_CONTROL__DISABLE_ROP3__SHIFT                                                                0x1f
#define CB_BLEND0_CONTROL__COLOR_SRCBLEND_MASK                                                                0x0000001FL
#define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK                                                                0x000000E0L
#define CB_BLEND0_CONTROL__COLOR_DESTBLEND_MASK                                                               0x00001F00L
#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK                                                                0x001F0000L
#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK                                                                0x00E00000L
#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK                                                               0x1F000000L
#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND_MASK                                                          0x20000000L
#define CB_BLEND0_CONTROL__ENABLE_MASK                                                                        0x40000000L
#define CB_BLEND0_CONTROL__DISABLE_ROP3_MASK                                                                  0x80000000L
//CB_BLEND1_CONTROL
#define CB_BLEND1_CONTROL__COLOR_SRCBLEND__SHIFT                                                              0x0
#define CB_BLEND1_CONTROL__COLOR_COMB_FCN__SHIFT                                                              0x5
#define CB_BLEND1_CONTROL__COLOR_DESTBLEND__SHIFT                                                             0x8
#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT                                                              0x10
#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN__SHIFT                                                              0x15
#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND__SHIFT                                                             0x18
#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT                                                        0x1d
#define CB_BLEND1_CONTROL__ENABLE__SHIFT                                                                      0x1e
#define CB_BLEND1_CONTROL__DISABLE_ROP3__SHIFT                                                                0x1f
#define CB_BLEND1_CONTROL__COLOR_SRCBLEND_MASK                                                                0x0000001FL
#define CB_BLEND1_CONTROL__COLOR_COMB_FCN_MASK                                                                0x000000E0L
#define CB_BLEND1_CONTROL__COLOR_DESTBLEND_MASK                                                               0x00001F00L
#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND_MASK                                                                0x001F0000L
#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN_MASK                                                                0x00E00000L
#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND_MASK                                                               0x1F000000L
#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND_MASK                                                          0x20000000L
#define CB_BLEND1_CONTROL__ENABLE_MASK                                                                        0x40000000L
#define CB_BLEND1_CONTROL__DISABLE_ROP3_MASK                                                                  0x80000000L
//CB_BLEND2_CONTROL
#define CB_BLEND2_CONTROL__COLOR_SRCBLEND__SHIFT                                                              0x0
#define CB_BLEND2_CONTROL__COLOR_COMB_FCN__SHIFT                                                              0x5
#define CB_BLEND2_CONTROL__COLOR_DESTBLEND__SHIFT                                                             0x8
#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT                                                              0x10
#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN__SHIFT                                                              0x15
#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND__SHIFT                                                             0x18
#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT                                                        0x1d
#define CB_BLEND2_CONTROL__ENABLE__SHIFT                                                                      0x1e
#define CB_BLEND2_CONTROL__DISABLE_ROP3__SHIFT                                                                0x1f
#define CB_BLEND2_CONTROL__COLOR_SRCBLEND_MASK                                                                0x0000001FL
#define CB_BLEND2_CONTROL__COLOR_COMB_FCN_MASK                                                                0x000000E0L
#define CB_BLEND2_CONTROL__COLOR_DESTBLEND_MASK                                                               0x00001F00L
#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND_MASK                                                                0x001F0000L
#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN_MASK                                                                0x00E00000L
#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND_MASK                                                               0x1F000000L
#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND_MASK                                                          0x20000000L
#define CB_BLEND2_CONTROL__ENABLE_MASK                                                                        0x40000000L
#define CB_BLEND2_CONTROL__DISABLE_ROP3_MASK                                                                  0x80000000L
//CB_BLEND3_CONTROL
#define CB_BLEND3_CONTROL__COLOR_SRCBLEND__SHIFT                                                              0x0
#define CB_BLEND3_CONTROL__COLOR_COMB_FCN__SHIFT                                                              0x5
#define CB_BLEND3_CONTROL__COLOR_DESTBLEND__SHIFT                                                             0x8
#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT                                                              0x10
#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN__SHIFT                                                              0x15
#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND__SHIFT                                                             0x18
#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT                                                        0x1d
#define CB_BLEND3_CONTROL__ENABLE__SHIFT                                                                      0x1e
#define CB_BLEND3_CONTROL__DISABLE_ROP3__SHIFT                                                                0x1f
#define CB_BLEND3_CONTROL__COLOR_SRCBLEND_MASK                                                                0x0000001FL
#define CB_BLEND3_CONTROL__COLOR_COMB_FCN_MASK                                                                0x000000E0L
#define CB_BLEND3_CONTROL__COLOR_DESTBLEND_MASK                                                               0x00001F00L
#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND_MASK                                                                0x001F0000L
#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN_MASK                                                                0x00E00000L
#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND_MASK                                                               0x1F000000L
#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND_MASK                                                          0x20000000L
#define CB_BLEND3_CONTROL__ENABLE_MASK                                                                        0x40000000L
#define CB_BLEND3_CONTROL__DISABLE_ROP3_MASK                                                                  0x80000000L
//CB_BLEND4_CONTROL
#define CB_BLEND4_CONTROL__COLOR_SRCBLEND__SHIFT                                                              0x0
#define CB_BLEND4_CONTROL__COLOR_COMB_FCN__SHIFT                                                              0x5
#define CB_BLEND4_CONTROL__COLOR_DESTBLEND__SHIFT                                                             0x8
#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND__SHIFT                                                              0x10
#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN__SHIFT                                                              0x15
#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND__SHIFT                                                             0x18
#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT                                                        0x1d
#define CB_BLEND4_CONTROL__ENABLE__SHIFT                                                                      0x1e
#define CB_BLEND4_CONTROL__DISABLE_ROP3__SHIFT                                                                0x1f
#define CB_BLEND4_CONTROL__COLOR_SRCBLEND_MASK                                                                0x0000001FL
#define CB_BLEND4_CONTROL__COLOR_COMB_FCN_MASK                                                                0x000000E0L
#define CB_BLEND4_CONTROL__COLOR_DESTBLEND_MASK                                                               0x00001F00L
#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND_MASK                                                                0x001F0000L
#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN_MASK                                                                0x00E00000L
#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND_MASK                                                               0x1F000000L
#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND_MASK                                                          0x20000000L
#define CB_BLEND4_CONTROL__ENABLE_MASK                                                                        0x40000000L
#define CB_BLEND4_CONTROL__DISABLE_ROP3_MASK                                                                  0x80000000L
//CB_BLEND5_CONTROL
#define CB_BLEND5_CONTROL__COLOR_SRCBLEND__SHIFT                                                              0x0
#define CB_BLEND5_CONTROL__COLOR_COMB_FCN__SHIFT                                                              0x5
#define CB_BLEND5_CONTROL__COLOR_DESTBLEND__SHIFT                                                             0x8
#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND__SHIFT                                                              0x10
#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN__SHIFT                                                              0x15
#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND__SHIFT                                                             0x18
#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT                                                        0x1d
#define CB_BLEND5_CONTROL__ENABLE__SHIFT                                                                      0x1e
#define CB_BLEND5_CONTROL__DISABLE_ROP3__SHIFT                                                                0x1f
#define CB_BLEND5_CONTROL__COLOR_SRCBLEND_MASK                                                                0x0000001FL
#define CB_BLEND5_CONTROL__COLOR_COMB_FCN_MASK                                                                0x000000E0L
#define CB_BLEND5_CONTROL__COLOR_DESTBLEND_MASK                                                               0x00001F00L
#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND_MASK                                                                0x001F0000L
#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN_MASK                                                                0x00E00000L
#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND_MASK                                                               0x1F000000L
#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND_MASK                                                          0x20000000L
#define CB_BLEND5_CONTROL__ENABLE_MASK                                                                        0x40000000L
#define CB_BLEND5_CONTROL__DISABLE_ROP3_MASK                                                                  0x80000000L
//CB_BLEND6_CONTROL
#define CB_BLEND6_CONTROL__COLOR_SRCBLEND__SHIFT                                                              0x0
#define CB_BLEND6_CONTROL__COLOR_COMB_FCN__SHIFT                                                              0x5
#define CB_BLEND6_CONTROL__COLOR_DESTBLEND__SHIFT                                                             0x8
#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND__SHIFT                                                              0x10
#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN__SHIFT                                                              0x15
#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND__SHIFT                                                             0x18
#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT                                                        0x1d
#define CB_BLEND6_CONTROL__ENABLE__SHIFT                                                                      0x1e
#define CB_BLEND6_CONTROL__DISABLE_ROP3__SHIFT                                                                0x1f
#define CB_BLEND6_CONTROL__COLOR_SRCBLEND_MASK                                                                0x0000001FL
#define CB_BLEND6_CONTROL__COLOR_COMB_FCN_MASK                                                                0x000000E0L
#define CB_BLEND6_CONTROL__COLOR_DESTBLEND_MASK                                                               0x00001F00L
#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND_MASK                                                                0x001F0000L
#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN_MASK                                                                0x00E00000L
#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND_MASK                                                               0x1F000000L
#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND_MASK                                                          0x20000000L
#define CB_BLEND6_CONTROL__ENABLE_MASK                                                                        0x40000000L
#define CB_BLEND6_CONTROL__DISABLE_ROP3_MASK                                                                  0x80000000L
//CB_BLEND7_CONTROL
#define CB_BLEND7_CONTROL__COLOR_SRCBLEND__SHIFT                                                              0x0
#define CB_BLEND7_CONTROL__COLOR_COMB_FCN__SHIFT                                                              0x5
#define CB_BLEND7_CONTROL__COLOR_DESTBLEND__SHIFT                                                             0x8
#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND__SHIFT                                                              0x10
#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN__SHIFT                                                              0x15
#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND__SHIFT                                                             0x18
#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT                                                        0x1d
#define CB_BLEND7_CONTROL__ENABLE__SHIFT                                                                      0x1e
#define CB_BLEND7_CONTROL__DISABLE_ROP3__SHIFT                                                                0x1f
#define CB_BLEND7_CONTROL__COLOR_SRCBLEND_MASK                                                                0x0000001FL
#define CB_BLEND7_CONTROL__COLOR_COMB_FCN_MASK                                                                0x000000E0L
#define CB_BLEND7_CONTROL__COLOR_DESTBLEND_MASK                                                               0x00001F00L
#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND_MASK                                                                0x001F0000L
#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN_MASK                                                                0x00E00000L
#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND_MASK                                                               0x1F000000L
#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND_MASK                                                          0x20000000L
#define CB_BLEND7_CONTROL__ENABLE_MASK                                                                        0x40000000L
#define CB_BLEND7_CONTROL__DISABLE_ROP3_MASK                                                                  0x80000000L
//CS_COPY_STATE
#define CS_COPY_STATE__SRC_STATE_ID__SHIFT                                                                    0x0
#define CS_COPY_STATE__SRC_STATE_ID_MASK                                                                      0x00000007L
//GFX_COPY_STATE
#define GFX_COPY_STATE__SRC_STATE_ID__SHIFT                                                                   0x0
#define GFX_COPY_STATE__SRC_STATE_ID_MASK                                                                     0x00000007L
//PA_CL_POINT_X_RAD
#define PA_CL_POINT_X_RAD__DATA_REGISTER__SHIFT                                                               0x0
#define PA_CL_POINT_X_RAD__DATA_REGISTER_MASK                                                                 0xFFFFFFFFL
//PA_CL_POINT_Y_RAD
#define PA_CL_POINT_Y_RAD__DATA_REGISTER__SHIFT                                                               0x0
#define PA_CL_POINT_Y_RAD__DATA_REGISTER_MASK                                                                 0xFFFFFFFFL
//PA_CL_POINT_SIZE
#define PA_CL_POINT_SIZE__DATA_REGISTER__SHIFT                                                                0x0
#define PA_CL_POINT_SIZE__DATA_REGISTER_MASK                                                                  0xFFFFFFFFL
//PA_CL_POINT_CULL_RAD
#define PA_CL_POINT_CULL_RAD__DATA_REGISTER__SHIFT                                                            0x0
#define PA_CL_POINT_CULL_RAD__DATA_REGISTER_MASK                                                              0xFFFFFFFFL
//VGT_DMA_BASE_HI
#define VGT_DMA_BASE_HI__BASE_ADDR__SHIFT                                                                     0x0
#define VGT_DMA_BASE_HI__BASE_ADDR_MASK                                                                       0x0000FFFFL
//VGT_DMA_BASE
#define VGT_DMA_BASE__BASE_ADDR__SHIFT                                                                        0x0
#define VGT_DMA_BASE__BASE_ADDR_MASK                                                                          0xFFFFFFFFL
//VGT_DRAW_INITIATOR
#define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT                                                              0x0
#define VGT_DRAW_INITIATOR__MAJOR_MODE__SHIFT                                                                 0x2
#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX__SHIFT                                                             0x4
#define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT                                                                    0x5
#define VGT_DRAW_INITIATOR__USE_OPAQUE__SHIFT                                                                 0x6
#define VGT_DRAW_INITIATOR__REG_RT_INDEX__SHIFT                                                               0x1d
#define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK                                                                0x00000003L
#define VGT_DRAW_INITIATOR__MAJOR_MODE_MASK                                                                   0x0000000CL
#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX_MASK                                                               0x00000010L
#define VGT_DRAW_INITIATOR__NOT_EOP_MASK                                                                      0x00000020L
#define VGT_DRAW_INITIATOR__USE_OPAQUE_MASK                                                                   0x00000040L
#define VGT_DRAW_INITIATOR__REG_RT_INDEX_MASK                                                                 0xE0000000L
//VGT_IMMED_DATA
#define VGT_IMMED_DATA__DATA__SHIFT                                                                           0x0
#define VGT_IMMED_DATA__DATA_MASK                                                                             0xFFFFFFFFL
//VGT_EVENT_ADDRESS_REG
#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW__SHIFT                                                             0x0
#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW_MASK                                                               0x0FFFFFFFL
//GE_MAX_OUTPUT_PER_SUBGROUP
#define GE_MAX_OUTPUT_PER_SUBGROUP__MAX_VERTS_PER_SUBGROUP__SHIFT                                             0x0
#define GE_MAX_OUTPUT_PER_SUBGROUP__MAX_VERTS_PER_SUBGROUP_MASK                                               0x000003FFL
//DB_DEPTH_CONTROL
#define DB_DEPTH_CONTROL__STENCIL_ENABLE__SHIFT                                                               0x0
#define DB_DEPTH_CONTROL__Z_ENABLE__SHIFT                                                                     0x1
#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE__SHIFT                                                               0x2
#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE__SHIFT                                                          0x3
#define DB_DEPTH_CONTROL__ZFUNC__SHIFT                                                                        0x4
#define DB_DEPTH_CONTROL__BACKFACE_ENABLE__SHIFT                                                              0x7
#define DB_DEPTH_CONTROL__STENCILFUNC__SHIFT                                                                  0x8
#define DB_DEPTH_CONTROL__STENCILFUNC_BF__SHIFT                                                               0x14
#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL__SHIFT                                            0x1e
#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS__SHIFT                                           0x1f
#define DB_DEPTH_CONTROL__STENCIL_ENABLE_MASK                                                                 0x00000001L
#define DB_DEPTH_CONTROL__Z_ENABLE_MASK                                                                       0x00000002L
#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE_MASK                                                                 0x00000004L
#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE_MASK                                                            0x00000008L
#define DB_DEPTH_CONTROL__ZFUNC_MASK                                                                          0x00000070L
#define DB_DEPTH_CONTROL__BACKFACE_ENABLE_MASK                                                                0x00000080L
#define DB_DEPTH_CONTROL__STENCILFUNC_MASK                                                                    0x00000700L
#define DB_DEPTH_CONTROL__STENCILFUNC_BF_MASK                                                                 0x00700000L
#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_MASK                                              0x40000000L
#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS_MASK                                             0x80000000L
//DB_EQAA
#define DB_EQAA__MAX_ANCHOR_SAMPLES__SHIFT                                                                    0x0
#define DB_EQAA__PS_ITER_SAMPLES__SHIFT                                                                       0x4
#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES__SHIFT                                                               0x8
#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES__SHIFT                                                             0xc
#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS__SHIFT                                                            0x10
#define DB_EQAA__INCOHERENT_EQAA_READS__SHIFT                                                                 0x11
#define DB_EQAA__INTERPOLATE_COMP_Z__SHIFT                                                                    0x12
#define DB_EQAA__INTERPOLATE_SRC_Z__SHIFT                                                                     0x13
#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS__SHIFT                                                            0x14
#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE__SHIFT                                                            0x15
#define DB_EQAA__OVERRASTERIZATION_AMOUNT__SHIFT                                                              0x18
#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION__SHIFT                                                        0x1b
#define DB_EQAA__MAX_ANCHOR_SAMPLES_MASK                                                                      0x00000007L
#define DB_EQAA__PS_ITER_SAMPLES_MASK                                                                         0x00000070L
#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES_MASK                                                                 0x00000700L
#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES_MASK                                                               0x00007000L
#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS_MASK                                                              0x00010000L
#define DB_EQAA__INCOHERENT_EQAA_READS_MASK                                                                   0x00020000L
#define DB_EQAA__INTERPOLATE_COMP_Z_MASK                                                                      0x00040000L
#define DB_EQAA__INTERPOLATE_SRC_Z_MASK                                                                       0x00080000L
#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS_MASK                                                              0x00100000L
#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE_MASK                                                              0x00200000L
#define DB_EQAA__OVERRASTERIZATION_AMOUNT_MASK                                                                0x07000000L
#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION_MASK                                                          0x08000000L
//CB_COLOR_CONTROL
#define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD__SHIFT                                                            0x0
#define CB_COLOR_CONTROL__ENABLE_1FRAG_PS_INVOKE__SHIFT                                                       0x1
#define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT                                                               0x3
#define CB_COLOR_CONTROL__MODE__SHIFT                                                                         0x4
#define CB_COLOR_CONTROL__ROP3__SHIFT                                                                         0x10
#define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD_MASK                                                              0x00000001L
#define CB_COLOR_CONTROL__ENABLE_1FRAG_PS_INVOKE_MASK                                                         0x00000002L
#define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK                                                                 0x00000008L
#define CB_COLOR_CONTROL__MODE_MASK                                                                           0x00000070L
#define CB_COLOR_CONTROL__ROP3_MASK                                                                           0x00FF0000L
//DB_SHADER_CONTROL
#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE__SHIFT                                                             0x0
#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE__SHIFT                                              0x1
#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE__SHIFT                                                0x2
#define DB_SHADER_CONTROL__Z_ORDER__SHIFT                                                                     0x4
#define DB_SHADER_CONTROL__KILL_ENABLE__SHIFT                                                                 0x6
#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE__SHIFT                                                     0x7
#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE__SHIFT                                                          0x8
#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL__SHIFT                                                           0x9
#define DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT                                                                0xa
#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE__SHIFT                                                       0xb
#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER__SHIFT                                                         0xc
#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT__SHIFT                                                       0xd
#define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE__SHIFT                                                           0xf
#define DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER__SHIFT                                              0x10
#define DB_SHADER_CONTROL__EXEC_IF_OVERLAPPED__SHIFT                                                          0x11
#define DB_SHADER_CONTROL__POPS_OVERLAP_NUM_SAMPLES__SHIFT                                                    0x14
#define DB_SHADER_CONTROL__PRE_SHADER_DEPTH_COVERAGE_ENABLE__SHIFT                                            0x17
#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE_MASK                                                               0x00000001L
#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE_MASK                                                0x00000002L
#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE_MASK                                                  0x00000004L
#define DB_SHADER_CONTROL__Z_ORDER_MASK                                                                       0x00000030L
#define DB_SHADER_CONTROL__KILL_ENABLE_MASK                                                                   0x00000040L
#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE_MASK                                                       0x00000080L
#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE_MASK                                                            0x00000100L
#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL_MASK                                                             0x00000200L
#define DB_SHADER_CONTROL__EXEC_ON_NOOP_MASK                                                                  0x00000400L
#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE_MASK                                                         0x00000800L
#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER_MASK                                                           0x00001000L
#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT_MASK                                                         0x00006000L
#define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE_MASK                                                             0x00008000L
#define DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER_MASK                                                0x00010000L
#define DB_SHADER_CONTROL__EXEC_IF_OVERLAPPED_MASK                                                            0x00020000L
#define DB_SHADER_CONTROL__POPS_OVERLAP_NUM_SAMPLES_MASK                                                      0x00700000L
#define DB_SHADER_CONTROL__PRE_SHADER_DEPTH_COVERAGE_ENABLE_MASK                                              0x00800000L
//PA_CL_CLIP_CNTL
#define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT                                                                     0x0
#define PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT                                                                     0x1
#define PA_CL_CLIP_CNTL__UCP_ENA_2__SHIFT                                                                     0x2
#define PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT                                                                     0x3
#define PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT                                                                     0x4
#define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT                                                                     0x5
#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG__SHIFT                                                            0xd
#define PA_CL_CLIP_CNTL__PS_UCP_MODE__SHIFT                                                                   0xe
#define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT                                                                  0x10
#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA__SHIFT                                                             0x11
#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT                                                        0x12
#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT                                                             0x13
#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT                                                           0x14
#define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT                                                                   0x15
#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL__SHIFT                                                         0x16
#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA__SHIFT                                                       0x18
#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE__SHIFT                                                     0x19
#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE__SHIFT                                                            0x1a
#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE__SHIFT                                                             0x1b
#define PA_CL_CLIP_CNTL__ZCLIP_PROG_NEAR_ENA__SHIFT                                                           0x1c
#define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK                                                                       0x00000001L
#define PA_CL_CLIP_CNTL__UCP_ENA_1_MASK                                                                       0x00000002L
#define PA_CL_CLIP_CNTL__UCP_ENA_2_MASK                                                                       0x00000004L
#define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK                                                                       0x00000008L
#define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK                                                                       0x00000010L
#define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK                                                                       0x00000020L
#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG_MASK                                                              0x00002000L
#define PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK                                                                     0x0000C000L
#define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK                                                                    0x00010000L
#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK                                                               0x00020000L
#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK                                                          0x00040000L
#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK                                                               0x00080000L
#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK                                                             0x00100000L
#define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK                                                                     0x00200000L
#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL_MASK                                                           0x00400000L
#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA_MASK                                                         0x01000000L
#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE_MASK                                                       0x02000000L
#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE_MASK                                                              0x04000000L
#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE_MASK                                                               0x08000000L
#define PA_CL_CLIP_CNTL__ZCLIP_PROG_NEAR_ENA_MASK                                                             0x10000000L
//PA_SU_SC_MODE_CNTL
#define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT                                                                 0x0
#define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT                                                                  0x1
#define PA_SU_SC_MODE_CNTL__FACE__SHIFT                                                                       0x2
#define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT                                                                  0x3
#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT                                                       0x5
#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT                                                        0x8
#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT                                                   0xb
#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT                                                    0xc
#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT                                                    0xd
#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT                                                   0x10
#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT                                                         0x13
#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT                                                             0x14
#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT                                                          0x15
#define PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF__SHIFT                                      0x16
#define PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION__SHIFT                                                     0x17
#define PA_SU_SC_MODE_CNTL__KEEP_TOGETHER_ENABLE__SHIFT                                                       0x18
#define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK                                                                   0x00000001L
#define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK                                                                    0x00000002L
#define PA_SU_SC_MODE_CNTL__FACE_MASK                                                                         0x00000004L
#define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK                                                                    0x00000018L
#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK                                                         0x000000E0L
#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK                                                          0x00000700L
#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK                                                     0x00000800L
#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK                                                      0x00001000L
#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK                                                      0x00002000L
#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK                                                     0x00010000L
#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK                                                           0x00080000L
#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK                                                               0x00100000L
#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK                                                            0x00200000L
#define PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF_MASK                                        0x00400000L
#define PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION_MASK                                                       0x00800000L
#define PA_SU_SC_MODE_CNTL__KEEP_TOGETHER_ENABLE_MASK                                                         0x01000000L
//PA_CL_VTE_CNTL
#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT                                                              0x0
#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT                                                             0x1
#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT                                                              0x2
#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT                                                             0x3
#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT                                                              0x4
#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT                                                             0x5
#define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT                                                                     0x8
#define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT                                                                      0x9
#define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT                                                                     0xa
#define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT                                                                0xb
#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK                                                                0x00000001L
#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK                                                               0x00000002L
#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK                                                                0x00000004L
#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK                                                               0x00000008L
#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK                                                                0x00000010L
#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK                                                               0x00000020L
#define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK                                                                       0x00000100L
#define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK                                                                        0x00000200L
#define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK                                                                       0x00000400L
#define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK                                                                  0x00000800L
//PA_CL_VS_OUT_CNTL
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0__SHIFT                                                             0x0
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1__SHIFT                                                             0x1
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2__SHIFT                                                             0x2
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3__SHIFT                                                             0x3
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4__SHIFT                                                             0x4
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5__SHIFT                                                             0x5
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6__SHIFT                                                             0x6
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7__SHIFT                                                             0x7
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0__SHIFT                                                             0x8
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1__SHIFT                                                             0x9
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2__SHIFT                                                             0xa
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3__SHIFT                                                             0xb
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4__SHIFT                                                             0xc
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5__SHIFT                                                             0xd
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6__SHIFT                                                             0xe
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7__SHIFT                                                             0xf
#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE__SHIFT                                                          0x10
#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG__SHIFT                                                           0x11
#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX__SHIFT                                                  0x12
#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX__SHIFT                                                       0x13
#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG__SHIFT                                                           0x14
#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA__SHIFT                                                         0x15
#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA__SHIFT                                                      0x16
#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA__SHIFT                                                      0x17
#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA__SHIFT                                                    0x18
#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG__SHIFT                                                         0x19
#define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH__SHIFT                                                          0x1b
#define PA_CL_VS_OUT_CNTL__BYPASS_VTX_RATE_COMBINER__SHIFT                                                    0x1d
#define PA_CL_VS_OUT_CNTL__BYPASS_PRIM_RATE_COMBINER__SHIFT                                                   0x1e
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0_MASK                                                               0x00000001L
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1_MASK                                                               0x00000002L
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2_MASK                                                               0x00000004L
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3_MASK                                                               0x00000008L
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4_MASK                                                               0x00000010L
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5_MASK                                                               0x00000020L
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6_MASK                                                               0x00000040L
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7_MASK                                                               0x00000080L
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0_MASK                                                               0x00000100L
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1_MASK                                                               0x00000200L
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2_MASK                                                               0x00000400L
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3_MASK                                                               0x00000800L
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4_MASK                                                               0x00001000L
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5_MASK                                                               0x00002000L
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6_MASK                                                               0x00004000L
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7_MASK                                                               0x00008000L
#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE_MASK                                                            0x00010000L
#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG_MASK                                                             0x00020000L
#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX_MASK                                                    0x00040000L
#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX_MASK                                                         0x00080000L
#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG_MASK                                                             0x00100000L
#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA_MASK                                                           0x00200000L
#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA_MASK                                                        0x00400000L
#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA_MASK                                                        0x00800000L
#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA_MASK                                                      0x01000000L
#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG_MASK                                                           0x02000000L
#define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH_MASK                                                            0x08000000L
#define PA_CL_VS_OUT_CNTL__BYPASS_VTX_RATE_COMBINER_MASK                                                      0x20000000L
#define PA_CL_VS_OUT_CNTL__BYPASS_PRIM_RATE_COMBINER_MASK                                                     0x40000000L
//PA_CL_NANINF_CNTL
#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT                                                          0x0
#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT                                                           0x1
#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT                                                           0x2
#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0__SHIFT                                                           0x3
#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN__SHIFT                                                           0x4
#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN__SHIFT                                                            0x5
#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN__SHIFT                                                            0x6
#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0__SHIFT                                                        0x7
#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF__SHIFT                                                            0x8
#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN__SHIFT                                                            0x9
#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF__SHIFT                                                             0xa
#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN__SHIFT                                                             0xb
#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF__SHIFT                                                             0xc
#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN__SHIFT                                                             0xd
#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD__SHIFT                                                    0xe
#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0__SHIFT                                                         0x14
#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD_MASK                                                            0x00000001L
#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD_MASK                                                             0x00000002L
#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD_MASK                                                             0x00000004L
#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0_MASK                                                             0x00000008L
#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN_MASK                                                             0x00000010L
#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN_MASK                                                              0x00000020L
#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN_MASK                                                              0x00000040L
#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0_MASK                                                          0x00000080L
#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF_MASK                                                              0x00000100L
#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN_MASK                                                              0x00000200L
#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF_MASK                                                               0x00000400L
#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN_MASK                                                               0x00000800L
#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF_MASK                                                               0x00001000L
#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN_MASK                                                               0x00002000L
#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD_MASK                                                      0x00004000L
#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0_MASK                                                           0x00100000L
//PA_SU_LINE_STIPPLE_CNTL
#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET__SHIFT                                                    0x0
#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH__SHIFT                                                    0x2
#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM__SHIFT                                                      0x3
#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST__SHIFT                                                        0x4
#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET_MASK                                                      0x00000003L
#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH_MASK                                                      0x00000004L
#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM_MASK                                                        0x00000008L
#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST_MASK                                                          0x00000010L
//PA_SU_LINE_STIPPLE_SCALE
#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE__SHIFT                                                   0x0
#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE_MASK                                                     0xFFFFFFFFL
//PA_SU_PRIM_FILTER_CNTL
#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT                                                0x0
#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT                                                    0x1
#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT                                                   0x2
#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT                                               0x3
#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA__SHIFT                                                    0x4
#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA__SHIFT                                                        0x5
#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA__SHIFT                                                       0x6
#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA__SHIFT                                                   0x7
#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT__SHIFT                                                   0x8
#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION__SHIFT                                                   0x1e
#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION__SHIFT                                                  0x1f
#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK                                                  0x00000001L
#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK                                                      0x00000002L
#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK                                                     0x00000004L
#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK                                                 0x00000008L
#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA_MASK                                                      0x00000010L
#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA_MASK                                                          0x00000020L
#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA_MASK                                                         0x00000040L
#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA_MASK                                                     0x00000080L
#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT_MASK                                                     0x0000FF00L
#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION_MASK                                                     0x40000000L
#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION_MASK                                                    0x80000000L
//PA_SU_SMALL_PRIM_FILTER_CNTL
#define PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE__SHIFT                                         0x0
#define PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT                                          0x1
#define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT                                              0x2
#define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT                                             0x3
#define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT                                         0x4
#define PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE_MASK                                           0x00000001L
#define PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK                                            0x00000002L
#define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK                                                0x00000004L
#define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK                                               0x00000008L
#define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK                                           0x00000010L
//PA_CL_NGG_CNTL
#define PA_CL_NGG_CNTL__VERTEX_REUSE_OFF__SHIFT                                                               0x0
#define PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA__SHIFT                                                        0x1
#define PA_CL_NGG_CNTL__VERTEX_REUSE_DEPTH__SHIFT                                                             0x2
#define PA_CL_NGG_CNTL__VERTEX_REUSE_OFF_MASK                                                                 0x00000001L
#define PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA_MASK                                                          0x00000002L
#define PA_CL_NGG_CNTL__VERTEX_REUSE_DEPTH_MASK                                                               0x000003FCL
//PA_SU_OVER_RASTERIZATION_CNTL
#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES__SHIFT                                        0x0
#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES__SHIFT                                            0x1
#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS__SHIFT                                           0x2
#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES__SHIFT                                       0x3
#define PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW__SHIFT                                                0x4
#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES_MASK                                          0x00000001L
#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES_MASK                                              0x00000002L
#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS_MASK                                             0x00000004L
#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES_MASK                                         0x00000008L
#define PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW_MASK                                                  0x00000010L
//PA_STEREO_CNTL
#define PA_STEREO_CNTL__STEREO_MODE__SHIFT                                                                    0x1
#define PA_STEREO_CNTL__RT_SLICE_MODE__SHIFT                                                                  0x5
#define PA_STEREO_CNTL__RT_SLICE_OFFSET__SHIFT                                                                0x8
#define PA_STEREO_CNTL__VP_ID_MODE__SHIFT                                                                     0x10
#define PA_STEREO_CNTL__VP_ID_OFFSET__SHIFT                                                                   0x13
#define PA_STEREO_CNTL__STEREO_MODE_MASK                                                                      0x0000001EL
#define PA_STEREO_CNTL__RT_SLICE_MODE_MASK                                                                    0x000000E0L
#define PA_STEREO_CNTL__RT_SLICE_OFFSET_MASK                                                                  0x00000F00L
#define PA_STEREO_CNTL__VP_ID_MODE_MASK                                                                       0x00070000L
#define PA_STEREO_CNTL__VP_ID_OFFSET_MASK                                                                     0x00780000L
//PA_STATE_STEREO_X
#define PA_STATE_STEREO_X__STEREO_X_OFFSET__SHIFT                                                             0x0
#define PA_STATE_STEREO_X__STEREO_X_OFFSET_MASK                                                               0xFFFFFFFFL
//PA_SU_POINT_SIZE
#define PA_SU_POINT_SIZE__HEIGHT__SHIFT                                                                       0x0
#define PA_SU_POINT_SIZE__WIDTH__SHIFT                                                                        0x10
#define PA_SU_POINT_SIZE__HEIGHT_MASK                                                                         0x0000FFFFL
#define PA_SU_POINT_SIZE__WIDTH_MASK                                                                          0xFFFF0000L
//PA_SU_POINT_MINMAX
#define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT                                                                   0x0
#define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT                                                                   0x10
#define PA_SU_POINT_MINMAX__MIN_SIZE_MASK                                                                     0x0000FFFFL
#define PA_SU_POINT_MINMAX__MAX_SIZE_MASK                                                                     0xFFFF0000L
//PA_SU_LINE_CNTL
#define PA_SU_LINE_CNTL__WIDTH__SHIFT                                                                         0x0
#define PA_SU_LINE_CNTL__WIDTH_MASK                                                                           0x0000FFFFL
//PA_SC_LINE_STIPPLE
#define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT                                                               0x0
#define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT                                                               0x10
#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT                                                          0x1c
#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT                                                            0x1d
#define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK                                                                 0x0000FFFFL
#define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK                                                                 0x00FF0000L
#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK                                                            0x10000000L
#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK                                                              0x60000000L
//VGT_OUTPUT_PATH_CNTL
#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT__SHIFT                                                              0x0
#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT_MASK                                                                0x00000007L
//VGT_HOS_CNTL
#define VGT_HOS_CNTL__TESS_MODE__SHIFT                                                                        0x0
#define VGT_HOS_CNTL__TESS_MODE_MASK                                                                          0x00000003L
//VGT_HOS_MAX_TESS_LEVEL
#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS__SHIFT                                                               0x0
#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS_MASK                                                                 0xFFFFFFFFL
//VGT_HOS_MIN_TESS_LEVEL
#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS__SHIFT                                                               0x0
#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS_MASK                                                                 0xFFFFFFFFL
//VGT_HOS_REUSE_DEPTH
#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH__SHIFT                                                               0x0
#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH_MASK                                                                 0x000000FFL
//VGT_GROUP_PRIM_TYPE
#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE__SHIFT                                                                 0x0
#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER__SHIFT                                                              0xe
#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS__SHIFT                                                              0xf
#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER__SHIFT                                                                0x10
#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE_MASK                                                                   0x0000001FL
#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER_MASK                                                                0x00004000L
#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS_MASK                                                                0x00008000L
#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER_MASK                                                                  0x00070000L
//VGT_GROUP_FIRST_DECR
#define VGT_GROUP_FIRST_DECR__FIRST_DECR__SHIFT                                                               0x0
#define VGT_GROUP_FIRST_DECR__FIRST_DECR_MASK                                                                 0x0000000FL
//VGT_GROUP_DECR
#define VGT_GROUP_DECR__DECR__SHIFT                                                                           0x0
#define VGT_GROUP_DECR__DECR_MASK                                                                             0x0000000FL
//VGT_GROUP_VECT_0_CNTL
#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN__SHIFT                                                               0x0
#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN__SHIFT                                                               0x1
#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN__SHIFT                                                               0x2
#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN__SHIFT                                                               0x3
#define VGT_GROUP_VECT_0_CNTL__STRIDE__SHIFT                                                                  0x8
#define VGT_GROUP_VECT_0_CNTL__SHIFT__SHIFT                                                                   0x10
#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN_MASK                                                                 0x00000001L
#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN_MASK                                                                 0x00000002L
#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN_MASK                                                                 0x00000004L
#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN_MASK                                                                 0x00000008L
#define VGT_GROUP_VECT_0_CNTL__STRIDE_MASK                                                                    0x0000FF00L
#define VGT_GROUP_VECT_0_CNTL__SHIFT_MASK                                                                     0x00FF0000L
//VGT_GROUP_VECT_1_CNTL
#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN__SHIFT                                                               0x0
#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN__SHIFT                                                               0x1
#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN__SHIFT                                                               0x2
#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN__SHIFT                                                               0x3
#define VGT_GROUP_VECT_1_CNTL__STRIDE__SHIFT                                                                  0x8
#define VGT_GROUP_VECT_1_CNTL__SHIFT__SHIFT                                                                   0x10
#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN_MASK                                                                 0x00000001L
#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN_MASK                                                                 0x00000002L
#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN_MASK                                                                 0x00000004L
#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN_MASK                                                                 0x00000008L
#define VGT_GROUP_VECT_1_CNTL__STRIDE_MASK                                                                    0x0000FF00L
#define VGT_GROUP_VECT_1_CNTL__SHIFT_MASK                                                                     0x00FF0000L
//VGT_GROUP_VECT_0_FMT_CNTL
#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV__SHIFT                                                              0x0
#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET__SHIFT                                                            0x4
#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV__SHIFT                                                              0x8
#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET__SHIFT                                                            0xc
#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV__SHIFT                                                              0x10
#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET__SHIFT                                                            0x14
#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV__SHIFT                                                              0x18
#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET__SHIFT                                                            0x1c
#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV_MASK                                                                0x0000000FL
#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET_MASK                                                              0x000000F0L
#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV_MASK                                                                0x00000F00L
#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET_MASK                                                              0x0000F000L
#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV_MASK                                                                0x000F0000L
#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET_MASK                                                              0x00F00000L
#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV_MASK                                                                0x0F000000L
#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET_MASK                                                              0xF0000000L
//VGT_GROUP_VECT_1_FMT_CNTL
#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV__SHIFT                                                              0x0
#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET__SHIFT                                                            0x4
#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV__SHIFT                                                              0x8
#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET__SHIFT                                                            0xc
#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV__SHIFT                                                              0x10
#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET__SHIFT                                                            0x14
#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV__SHIFT                                                              0x18
#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET__SHIFT                                                            0x1c
#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV_MASK                                                                0x0000000FL
#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET_MASK                                                              0x000000F0L
#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV_MASK                                                                0x00000F00L
#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET_MASK                                                              0x0000F000L
#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV_MASK                                                                0x000F0000L
#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET_MASK                                                              0x00F00000L
#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV_MASK                                                                0x0F000000L
#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET_MASK                                                              0xF0000000L
//VGT_GS_MODE
#define VGT_GS_MODE__MODE__SHIFT                                                                              0x0
#define VGT_GS_MODE__RESERVED_0__SHIFT                                                                        0x3
#define VGT_GS_MODE__CUT_MODE__SHIFT                                                                          0x4
#define VGT_GS_MODE__RESERVED_1__SHIFT                                                                        0x6
#define VGT_GS_MODE__GS_C_PACK_EN__SHIFT                                                                      0xb
#define VGT_GS_MODE__RESERVED_2__SHIFT                                                                        0xc
#define VGT_GS_MODE__ES_PASSTHRU__SHIFT                                                                       0xd
#define VGT_GS_MODE__COMPUTE_MODE__SHIFT                                                                      0xe
#define VGT_GS_MODE__FAST_COMPUTE_MODE__SHIFT                                                                 0xf
#define VGT_GS_MODE__ELEMENT_INFO_EN__SHIFT                                                                   0x10
#define VGT_GS_MODE__PARTIAL_THD_AT_EOI__SHIFT                                                                0x11
#define VGT_GS_MODE__SUPPRESS_CUTS__SHIFT                                                                     0x12
#define VGT_GS_MODE__ES_WRITE_OPTIMIZE__SHIFT                                                                 0x13
#define VGT_GS_MODE__GS_WRITE_OPTIMIZE__SHIFT                                                                 0x14
#define VGT_GS_MODE__ONCHIP__SHIFT                                                                            0x15
#define VGT_GS_MODE__MODE_MASK                                                                                0x00000007L
#define VGT_GS_MODE__RESERVED_0_MASK                                                                          0x00000008L
#define VGT_GS_MODE__CUT_MODE_MASK                                                                            0x00000030L
#define VGT_GS_MODE__RESERVED_1_MASK                                                                          0x000007C0L
#define VGT_GS_MODE__GS_C_PACK_EN_MASK                                                                        0x00000800L
#define VGT_GS_MODE__RESERVED_2_MASK                                                                          0x00001000L
#define VGT_GS_MODE__ES_PASSTHRU_MASK                                                                         0x00002000L
#define VGT_GS_MODE__COMPUTE_MODE_MASK                                                                        0x00004000L
#define VGT_GS_MODE__FAST_COMPUTE_MODE_MASK                                                                   0x00008000L
#define VGT_GS_MODE__ELEMENT_INFO_EN_MASK                                                                     0x00010000L
#define VGT_GS_MODE__PARTIAL_THD_AT_EOI_MASK                                                                  0x00020000L
#define VGT_GS_MODE__SUPPRESS_CUTS_MASK                                                                       0x00040000L
#define VGT_GS_MODE__ES_WRITE_OPTIMIZE_MASK                                                                   0x00080000L
#define VGT_GS_MODE__GS_WRITE_OPTIMIZE_MASK                                                                   0x00100000L
#define VGT_GS_MODE__ONCHIP_MASK                                                                              0x00600000L
//VGT_GS_ONCHIP_CNTL
#define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP__SHIFT                                                        0x0
#define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP__SHIFT                                                        0xb
#define VGT_GS_ONCHIP_CNTL__GS_INST_PRIMS_IN_SUBGRP__SHIFT                                                    0x16
#define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP_MASK                                                          0x000007FFL
#define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP_MASK                                                          0x003FF800L
#define VGT_GS_ONCHIP_CNTL__GS_INST_PRIMS_IN_SUBGRP_MASK                                                      0xFFC00000L
//PA_SC_MODE_CNTL_0
#define PA_SC_MODE_CNTL_0__MSAA_ENABLE__SHIFT                                                                 0x0
#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE__SHIFT                                                        0x1
#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE__SHIFT                                                         0x2
#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR__SHIFT                                                    0x3
#define PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE__SHIFT                                                      0x5
#define PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB__SHIFT                                               0x6
#define PA_SC_MODE_CNTL_0__MSAA_ENABLE_MASK                                                                   0x00000001L
#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE_MASK                                                          0x00000002L
#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE_MASK                                                           0x00000004L
#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR_MASK                                                      0x00000008L
#define PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE_MASK                                                        0x00000020L
#define PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB_MASK                                                 0x00000040L
//PA_SC_MODE_CNTL_1
#define PA_SC_MODE_CNTL_1__WALK_SIZE__SHIFT                                                                   0x0
#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT__SHIFT                                                              0x1
#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST__SHIFT                                                    0x2
#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE__SHIFT                                                           0x3
#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE__SHIFT                                                             0x4
#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE__SHIFT                                                 0x7
#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE__SHIFT                                                      0x8
#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE__SHIFT                                                          0x9
#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR__SHIFT                                                       0xa
#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT__SHIFT                                                             0xb
#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET__SHIFT                                                             0xc
#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT__SHIFT                                                             0xd
#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z__SHIFT                                                          0xe
#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK__SHIFT                                                   0xf
#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE__SHIFT                                                              0x10
#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE__SHIFT                                     0x11
#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE__SHIFT                                                  0x12
#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE__SHIFT                                                      0x13
#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE__SHIFT                                                             0x14
#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE__SHIFT                                               0x18
#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE__SHIFT                                                     0x19
#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE__SHIFT                                                        0x1a
#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE__SHIFT                                               0x1b
#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK__SHIFT                                                     0x1c
#define PA_SC_MODE_CNTL_1__WALK_SIZE_MASK                                                                     0x00000001L
#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT_MASK                                                                0x00000002L
#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST_MASK                                                      0x00000004L
#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE_MASK                                                             0x00000008L
#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE_MASK                                                               0x00000070L
#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE_MASK                                                   0x00000080L
#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE_MASK                                                        0x00000100L
#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE_MASK                                                            0x00000200L
#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR_MASK                                                         0x00000400L
#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT_MASK                                                               0x00000800L
#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET_MASK                                                               0x00001000L
#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT_MASK                                                               0x00002000L
#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z_MASK                                                            0x00004000L
#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK_MASK                                                     0x00008000L
#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE_MASK                                                                0x00010000L
#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE_MASK                                       0x00020000L
#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE_MASK                                                    0x00040000L
#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE_MASK                                                        0x00080000L
#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_MASK                                                               0x00F00000L
#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE_MASK                                                 0x01000000L
#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE_MASK                                                       0x02000000L
#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK                                                          0x04000000L
#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE_MASK                                                 0x08000000L
#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK_MASK                                                       0x70000000L
//VGT_ENHANCE
#define VGT_ENHANCE__MISC__SHIFT                                                                              0x0
#define VGT_ENHANCE__MISC_MASK                                                                                0xFFFFFFFFL
//VGT_GS_PER_ES
#define VGT_GS_PER_ES__GS_PER_ES__SHIFT                                                                       0x0
#define VGT_GS_PER_ES__GS_PER_ES_MASK                                                                         0x000007FFL
//VGT_ES_PER_GS
#define VGT_ES_PER_GS__ES_PER_GS__SHIFT                                                                       0x0
#define VGT_ES_PER_GS__ES_PER_GS_MASK                                                                         0x000007FFL
//VGT_GS_PER_VS
#define VGT_GS_PER_VS__GS_PER_VS__SHIFT                                                                       0x0
#define VGT_GS_PER_VS__GS_PER_VS_MASK                                                                         0x0000000FL
//VGT_GSVS_RING_OFFSET_1
#define VGT_GSVS_RING_OFFSET_1__OFFSET__SHIFT                                                                 0x0
#define VGT_GSVS_RING_OFFSET_1__OFFSET_MASK                                                                   0x00007FFFL
//VGT_GSVS_RING_OFFSET_2
#define VGT_GSVS_RING_OFFSET_2__OFFSET__SHIFT                                                                 0x0
#define VGT_GSVS_RING_OFFSET_2__OFFSET_MASK                                                                   0x00007FFFL
//VGT_GSVS_RING_OFFSET_3
#define VGT_GSVS_RING_OFFSET_3__OFFSET__SHIFT                                                                 0x0
#define VGT_GSVS_RING_OFFSET_3__OFFSET_MASK                                                                   0x00007FFFL
//VGT_GS_OUT_PRIM_TYPE
#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE__SHIFT                                                             0x0
#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1__SHIFT                                                           0x8
#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2__SHIFT                                                           0x10
#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3__SHIFT                                                           0x16
#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM__SHIFT                                                   0x1f
#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_MASK                                                               0x0000003FL
#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1_MASK                                                             0x00003F00L
#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2_MASK                                                             0x003F0000L
#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3_MASK                                                             0x0FC00000L
#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM_MASK                                                     0x80000000L
//IA_ENHANCE
#define IA_ENHANCE__MISC__SHIFT                                                                               0x0
#define IA_ENHANCE__MISC_MASK                                                                                 0xFFFFFFFFL
//VGT_DMA_SIZE
#define VGT_DMA_SIZE__NUM_INDICES__SHIFT                                                                      0x0
#define VGT_DMA_SIZE__NUM_INDICES_MASK                                                                        0xFFFFFFFFL
//VGT_DMA_MAX_SIZE
#define VGT_DMA_MAX_SIZE__MAX_SIZE__SHIFT                                                                     0x0
#define VGT_DMA_MAX_SIZE__MAX_SIZE_MASK                                                                       0xFFFFFFFFL
//VGT_DMA_INDEX_TYPE
#define VGT_DMA_INDEX_TYPE__INDEX_TYPE__SHIFT                                                                 0x0
#define VGT_DMA_INDEX_TYPE__SWAP_MODE__SHIFT                                                                  0x2
#define VGT_DMA_INDEX_TYPE__BUF_TYPE__SHIFT                                                                   0x4
#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY__SHIFT                                                               0x6
#define VGT_DMA_INDEX_TYPE__ATC__SHIFT                                                                        0x8
#define VGT_DMA_INDEX_TYPE__NOT_EOP__SHIFT                                                                    0x9
#define VGT_DMA_INDEX_TYPE__REQ_PATH__SHIFT                                                                   0xa
#define VGT_DMA_INDEX_TYPE__MTYPE__SHIFT                                                                      0xb
#define VGT_DMA_INDEX_TYPE__DISABLE_INSTANCE_PACKING__SHIFT                                                   0xe
#define VGT_DMA_INDEX_TYPE__INDEX_TYPE_MASK                                                                   0x00000003L
#define VGT_DMA_INDEX_TYPE__SWAP_MODE_MASK                                                                    0x0000000CL
#define VGT_DMA_INDEX_TYPE__BUF_TYPE_MASK                                                                     0x00000030L
#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY_MASK                                                                 0x000000C0L
#define VGT_DMA_INDEX_TYPE__ATC_MASK                                                                          0x00000100L
#define VGT_DMA_INDEX_TYPE__NOT_EOP_MASK                                                                      0x00000200L
#define VGT_DMA_INDEX_TYPE__REQ_PATH_MASK                                                                     0x00000400L
#define VGT_DMA_INDEX_TYPE__MTYPE_MASK                                                                        0x00003800L
#define VGT_DMA_INDEX_TYPE__DISABLE_INSTANCE_PACKING_MASK                                                     0x00004000L
//WD_ENHANCE
#define WD_ENHANCE__MISC__SHIFT                                                                               0x0
#define WD_ENHANCE__MISC_MASK                                                                                 0xFFFFFFFFL
//VGT_PRIMITIVEID_EN
#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN__SHIFT                                                             0x0
#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI__SHIFT                                                       0x1
#define VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE__SHIFT                                                   0x2
#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN_MASK                                                               0x00000001L
#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI_MASK                                                         0x00000002L
#define VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE_MASK                                                     0x00000004L
//VGT_DMA_NUM_INSTANCES
#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES__SHIFT                                                           0x0
#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES_MASK                                                             0xFFFFFFFFL
//VGT_PRIMITIVEID_RESET
#define VGT_PRIMITIVEID_RESET__VALUE__SHIFT                                                                   0x0
#define VGT_PRIMITIVEID_RESET__VALUE_MASK                                                                     0xFFFFFFFFL
//VGT_EVENT_INITIATOR
#define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT                                                                0x0
#define VGT_EVENT_INITIATOR__ADDRESS_HI__SHIFT                                                                0xa
#define VGT_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT                                                            0x1b
#define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK                                                                  0x0000003FL
#define VGT_EVENT_INITIATOR__ADDRESS_HI_MASK                                                                  0x07FFFC00L
#define VGT_EVENT_INITIATOR__EXTENDED_EVENT_MASK                                                              0x08000000L
//VGT_MULTI_PRIM_IB_RESET_EN
#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN__SHIFT                                                           0x0
#define VGT_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS__SHIFT                                                     0x1
#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN_MASK                                                             0x00000001L
#define VGT_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS_MASK                                                       0x00000002L
//VGT_DRAW_PAYLOAD_CNTL
#define VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX__SHIFT                                                         0x1
#define VGT_DRAW_PAYLOAD_CNTL__EN_PRIM_PAYLOAD__SHIFT                                                         0x3
#define VGT_DRAW_PAYLOAD_CNTL__EN_DRAW_VP__SHIFT                                                              0x4
#define VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX_MASK                                                           0x00000002L
#define VGT_DRAW_PAYLOAD_CNTL__EN_PRIM_PAYLOAD_MASK                                                           0x00000008L
#define VGT_DRAW_PAYLOAD_CNTL__EN_DRAW_VP_MASK                                                                0x00000010L
//VGT_INSTANCE_STEP_RATE_0
#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE__SHIFT                                                            0x0
#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE_MASK                                                              0xFFFFFFFFL
//VGT_INSTANCE_STEP_RATE_1
#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE__SHIFT                                                            0x0
#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE_MASK                                                              0xFFFFFFFFL
//IA_MULTI_VGT_PARAM
#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE__SHIFT                                                             0x0
#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON__SHIFT                                                         0x10
#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP__SHIFT                                                              0x11
#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON__SHIFT                                                         0x12
#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI__SHIFT                                                              0x13
#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP__SHIFT                                                           0x14
#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE_MASK                                                               0x0000FFFFL
#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON_MASK                                                           0x00010000L
#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP_MASK                                                                0x00020000L
#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON_MASK                                                           0x00040000L
#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI_MASK                                                                0x00080000L
#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP_MASK                                                             0x00100000L
//VGT_ESGS_RING_ITEMSIZE
#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE__SHIFT                                                               0x0
#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE_MASK                                                                 0x00007FFFL
//VGT_GSVS_RING_ITEMSIZE
#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE__SHIFT                                                               0x0
#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE_MASK                                                                 0x00007FFFL
//VGT_REUSE_OFF
#define VGT_REUSE_OFF__REUSE_OFF__SHIFT                                                                       0x0
#define VGT_REUSE_OFF__REUSE_OFF_MASK                                                                         0x00000001L
//VGT_VTX_CNT_EN
#define VGT_VTX_CNT_EN__VTX_CNT_EN__SHIFT                                                                     0x0
#define VGT_VTX_CNT_EN__VTX_CNT_EN_MASK                                                                       0x00000001L
//DB_HTILE_SURFACE
#define DB_HTILE_SURFACE__RESERVED_FIELD_1__SHIFT                                                             0x0
#define DB_HTILE_SURFACE__FULL_CACHE__SHIFT                                                                   0x1
#define DB_HTILE_SURFACE__RESERVED_FIELD_2__SHIFT                                                             0x2
#define DB_HTILE_SURFACE__RESERVED_FIELD_3__SHIFT                                                             0x3
#define DB_HTILE_SURFACE__RESERVED_FIELD_4__SHIFT                                                             0x4
#define DB_HTILE_SURFACE__RESERVED_FIELD_5__SHIFT                                                             0xa
#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE__SHIFT                                                      0x10
#define DB_HTILE_SURFACE__RESERVED_FIELD_6__SHIFT                                                             0x11
#define DB_HTILE_SURFACE__PIPE_ALIGNED__SHIFT                                                                 0x12
#define DB_HTILE_SURFACE__RESERVED_FIELD_1_MASK                                                               0x00000001L
#define DB_HTILE_SURFACE__FULL_CACHE_MASK                                                                     0x00000002L
#define DB_HTILE_SURFACE__RESERVED_FIELD_2_MASK                                                               0x00000004L
#define DB_HTILE_SURFACE__RESERVED_FIELD_3_MASK                                                               0x00000008L
#define DB_HTILE_SURFACE__RESERVED_FIELD_4_MASK                                                               0x000003F0L
#define DB_HTILE_SURFACE__RESERVED_FIELD_5_MASK                                                               0x0000FC00L
#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE_MASK                                                        0x00010000L
#define DB_HTILE_SURFACE__RESERVED_FIELD_6_MASK                                                               0x00020000L
#define DB_HTILE_SURFACE__PIPE_ALIGNED_MASK                                                                   0x00040000L
//DB_SRESULTS_COMPARE_STATE0
#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0__SHIFT                                                       0x0
#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0__SHIFT                                                      0x4
#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0__SHIFT                                                       0xc
#define DB_SRESULTS_COMPARE_STATE0__ENABLE0__SHIFT                                                            0x18
#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0_MASK                                                         0x00000007L
#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0_MASK                                                        0x00000FF0L
#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0_MASK                                                         0x000FF000L
#define DB_SRESULTS_COMPARE_STATE0__ENABLE0_MASK                                                              0x01000000L
//DB_SRESULTS_COMPARE_STATE1
#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1__SHIFT                                                       0x0
#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1__SHIFT                                                      0x4
#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1__SHIFT                                                       0xc
#define DB_SRESULTS_COMPARE_STATE1__ENABLE1__SHIFT                                                            0x18
#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1_MASK                                                         0x00000007L
#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1_MASK                                                        0x00000FF0L
#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1_MASK                                                         0x000FF000L
#define DB_SRESULTS_COMPARE_STATE1__ENABLE1_MASK                                                              0x01000000L
//DB_PRELOAD_CONTROL
#define DB_PRELOAD_CONTROL__START_X__SHIFT                                                                    0x0
#define DB_PRELOAD_CONTROL__START_Y__SHIFT                                                                    0x8
#define DB_PRELOAD_CONTROL__MAX_X__SHIFT                                                                      0x10
#define DB_PRELOAD_CONTROL__MAX_Y__SHIFT                                                                      0x18
#define DB_PRELOAD_CONTROL__START_X_MASK                                                                      0x000000FFL
#define DB_PRELOAD_CONTROL__START_Y_MASK                                                                      0x0000FF00L
#define DB_PRELOAD_CONTROL__MAX_X_MASK                                                                        0x00FF0000L
#define DB_PRELOAD_CONTROL__MAX_Y_MASK                                                                        0xFF000000L
//VGT_STRMOUT_BUFFER_SIZE_0
#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE__SHIFT                                                                0x0
#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE_MASK                                                                  0xFFFFFFFFL
//VGT_STRMOUT_VTX_STRIDE_0
#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE__SHIFT                                                               0x0
#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE_MASK                                                                 0x000003FFL
//VGT_STRMOUT_BUFFER_OFFSET_0
#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET__SHIFT                                                            0x0
#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET_MASK                                                              0xFFFFFFFFL
//VGT_STRMOUT_BUFFER_SIZE_1
#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE__SHIFT                                                                0x0
#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE_MASK                                                                  0xFFFFFFFFL
//VGT_STRMOUT_VTX_STRIDE_1
#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE__SHIFT                                                               0x0
#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE_MASK                                                                 0x000003FFL
//VGT_STRMOUT_BUFFER_OFFSET_1
#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET__SHIFT                                                            0x0
#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET_MASK                                                              0xFFFFFFFFL
//VGT_STRMOUT_BUFFER_SIZE_2
#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE__SHIFT                                                                0x0
#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE_MASK                                                                  0xFFFFFFFFL
//VGT_STRMOUT_VTX_STRIDE_2
#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE__SHIFT                                                               0x0
#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE_MASK                                                                 0x000003FFL
//VGT_STRMOUT_BUFFER_OFFSET_2
#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET__SHIFT                                                            0x0
#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET_MASK                                                              0xFFFFFFFFL
//VGT_STRMOUT_BUFFER_SIZE_3
#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE__SHIFT                                                                0x0
#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE_MASK                                                                  0xFFFFFFFFL
//VGT_STRMOUT_VTX_STRIDE_3
#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE__SHIFT                                                               0x0
#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE_MASK                                                                 0x000003FFL
//VGT_STRMOUT_BUFFER_OFFSET_3
#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET__SHIFT                                                            0x0
#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET_MASK                                                              0xFFFFFFFFL
//VGT_STRMOUT_DRAW_OPAQUE_OFFSET
#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET__SHIFT                                                         0x0
#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET_MASK                                                           0xFFFFFFFFL
//VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE__SHIFT                                               0x0
#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE_MASK                                                 0xFFFFFFFFL
//VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE__SHIFT                                           0x0
#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE_MASK                                             0x000001FFL
//VGT_GS_MAX_VERT_OUT
#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT__SHIFT                                                              0x0
#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT_MASK                                                                0x000007FFL
//GE_NGG_SUBGRP_CNTL
#define GE_NGG_SUBGRP_CNTL__PRIM_AMP_FACTOR__SHIFT                                                            0x0
#define GE_NGG_SUBGRP_CNTL__THDS_PER_SUBGRP__SHIFT                                                            0x9
#define GE_NGG_SUBGRP_CNTL__PRIM_AMP_FACTOR_MASK                                                              0x000001FFL
#define GE_NGG_SUBGRP_CNTL__THDS_PER_SUBGRP_MASK                                                              0x0003FE00L
//VGT_TESS_DISTRIBUTION
#define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE__SHIFT                                                           0x0
#define VGT_TESS_DISTRIBUTION__ACCUM_TRI__SHIFT                                                               0x8
#define VGT_TESS_DISTRIBUTION__ACCUM_QUAD__SHIFT                                                              0x10
#define VGT_TESS_DISTRIBUTION__DONUT_SPLIT__SHIFT                                                             0x18
#define VGT_TESS_DISTRIBUTION__TRAP_SPLIT__SHIFT                                                              0x1d
#define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE_MASK                                                             0x000000FFL
#define VGT_TESS_DISTRIBUTION__ACCUM_TRI_MASK                                                                 0x0000FF00L
#define VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK                                                                0x00FF0000L
#define VGT_TESS_DISTRIBUTION__DONUT_SPLIT_MASK                                                               0x1F000000L
#define VGT_TESS_DISTRIBUTION__TRAP_SPLIT_MASK                                                                0xE0000000L
//VGT_SHADER_STAGES_EN
#define VGT_SHADER_STAGES_EN__LS_EN__SHIFT                                                                    0x0
#define VGT_SHADER_STAGES_EN__HS_EN__SHIFT                                                                    0x2
#define VGT_SHADER_STAGES_EN__ES_EN__SHIFT                                                                    0x3
#define VGT_SHADER_STAGES_EN__GS_EN__SHIFT                                                                    0x5
#define VGT_SHADER_STAGES_EN__VS_EN__SHIFT                                                                    0x6
#define VGT_SHADER_STAGES_EN__DYNAMIC_HS__SHIFT                                                               0x8
#define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN__SHIFT                                                         0x9
#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0__SHIFT                                                      0xa
#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1__SHIFT                                                      0xb
#define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN__SHIFT                                                            0xc
#define VGT_SHADER_STAGES_EN__PRIMGEN_EN__SHIFT                                                               0xd
#define VGT_SHADER_STAGES_EN__ORDERED_ID_MODE__SHIFT                                                          0xe
#define VGT_SHADER_STAGES_EN__MAX_PRIMGRP_IN_WAVE__SHIFT                                                      0xf
#define VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH__SHIFT                                                           0x13
#define VGT_SHADER_STAGES_EN__HS_W32_EN__SHIFT                                                                0x15
#define VGT_SHADER_STAGES_EN__GS_W32_EN__SHIFT                                                                0x16
#define VGT_SHADER_STAGES_EN__VS_W32_EN__SHIFT                                                                0x17
#define VGT_SHADER_STAGES_EN__NGG_WAVE_ID_EN__SHIFT                                                           0x18
#define VGT_SHADER_STAGES_EN__PRIMGEN_PASSTHRU_EN__SHIFT                                                      0x19
#define VGT_SHADER_STAGES_EN__LS_EN_MASK                                                                      0x00000003L
#define VGT_SHADER_STAGES_EN__HS_EN_MASK                                                                      0x00000004L
#define VGT_SHADER_STAGES_EN__ES_EN_MASK                                                                      0x00000018L
#define VGT_SHADER_STAGES_EN__GS_EN_MASK                                                                      0x00000020L
#define VGT_SHADER_STAGES_EN__VS_EN_MASK                                                                      0x000000C0L
#define VGT_SHADER_STAGES_EN__DYNAMIC_HS_MASK                                                                 0x00000100L
#define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN_MASK                                                           0x00000200L
#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0_MASK                                                        0x00000400L
#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1_MASK                                                        0x00000800L
#define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN_MASK                                                              0x00001000L
#define VGT_SHADER_STAGES_EN__PRIMGEN_EN_MASK                                                                 0x00002000L
#define VGT_SHADER_STAGES_EN__ORDERED_ID_MODE_MASK                                                            0x00004000L
#define VGT_SHADER_STAGES_EN__MAX_PRIMGRP_IN_WAVE_MASK                                                        0x00078000L
#define VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH_MASK                                                             0x00180000L
#define VGT_SHADER_STAGES_EN__HS_W32_EN_MASK                                                                  0x00200000L
#define VGT_SHADER_STAGES_EN__GS_W32_EN_MASK                                                                  0x00400000L
#define VGT_SHADER_STAGES_EN__VS_W32_EN_MASK                                                                  0x00800000L
#define VGT_SHADER_STAGES_EN__NGG_WAVE_ID_EN_MASK                                                             0x01000000L
#define VGT_SHADER_STAGES_EN__PRIMGEN_PASSTHRU_EN_MASK                                                        0x02000000L
//VGT_LS_HS_CONFIG
#define VGT_LS_HS_CONFIG__NUM_PATCHES__SHIFT                                                                  0x0
#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT                                                              0x8
#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP__SHIFT                                                             0xe
#define VGT_LS_HS_CONFIG__NUM_PATCHES_MASK                                                                    0x000000FFL
#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK                                                                0x00003F00L
#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP_MASK                                                               0x000FC000L
//VGT_GS_VERT_ITEMSIZE
#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE__SHIFT                                                                 0x0
#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE_MASK                                                                   0x00007FFFL
//VGT_GS_VERT_ITEMSIZE_1
#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE__SHIFT                                                               0x0
#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE_MASK                                                                 0x00007FFFL
//VGT_GS_VERT_ITEMSIZE_2
#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE__SHIFT                                                               0x0
#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE_MASK                                                                 0x00007FFFL
//VGT_GS_VERT_ITEMSIZE_3
#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE__SHIFT                                                               0x0
#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE_MASK                                                                 0x00007FFFL
//VGT_TF_PARAM
#define VGT_TF_PARAM__TYPE__SHIFT                                                                             0x0
#define VGT_TF_PARAM__PARTITIONING__SHIFT                                                                     0x2
#define VGT_TF_PARAM__TOPOLOGY__SHIFT                                                                         0x5
#define VGT_TF_PARAM__RESERVED_REDUC_AXIS__SHIFT                                                              0x8
#define VGT_TF_PARAM__DEPRECATED__SHIFT                                                                       0x9
#define VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD__SHIFT                                                            0xa
#define VGT_TF_PARAM__DISABLE_DONUTS__SHIFT                                                                   0xe
#define VGT_TF_PARAM__RDREQ_POLICY__SHIFT                                                                     0xf
#define VGT_TF_PARAM__DISTRIBUTION_MODE__SHIFT                                                                0x11
#define VGT_TF_PARAM__DETECT_ONE__SHIFT                                                                       0x13
#define VGT_TF_PARAM__DETECT_ZERO__SHIFT                                                                      0x14
#define VGT_TF_PARAM__MTYPE__SHIFT                                                                            0x17
#define VGT_TF_PARAM__TYPE_MASK                                                                               0x00000003L
#define VGT_TF_PARAM__PARTITIONING_MASK                                                                       0x0000001CL
#define VGT_TF_PARAM__TOPOLOGY_MASK                                                                           0x000000E0L
#define VGT_TF_PARAM__RESERVED_REDUC_AXIS_MASK                                                                0x00000100L
#define VGT_TF_PARAM__DEPRECATED_MASK                                                                         0x00000200L
#define VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD_MASK                                                              0x00003C00L
#define VGT_TF_PARAM__DISABLE_DONUTS_MASK                                                                     0x00004000L
#define VGT_TF_PARAM__RDREQ_POLICY_MASK                                                                       0x00018000L
#define VGT_TF_PARAM__DISTRIBUTION_MODE_MASK                                                                  0x00060000L
#define VGT_TF_PARAM__DETECT_ONE_MASK                                                                         0x00080000L
#define VGT_TF_PARAM__DETECT_ZERO_MASK                                                                        0x00100000L
#define VGT_TF_PARAM__MTYPE_MASK                                                                              0x03800000L
//DB_ALPHA_TO_MASK
#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE__SHIFT                                                         0x0
#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0__SHIFT                                                        0x8
#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1__SHIFT                                                        0xa
#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2__SHIFT                                                        0xc
#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3__SHIFT                                                        0xe
#define DB_ALPHA_TO_MASK__OFFSET_ROUND__SHIFT                                                                 0x10
#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE_MASK                                                           0x00000001L
#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0_MASK                                                          0x00000300L
#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1_MASK                                                          0x00000C00L
#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2_MASK                                                          0x00003000L
#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3_MASK                                                          0x0000C000L
#define DB_ALPHA_TO_MASK__OFFSET_ROUND_MASK                                                                   0x00010000L
//VGT_DISPATCH_DRAW_INDEX
#define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX__SHIFT                                                           0x0
#define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX_MASK                                                             0xFFFFFFFFL
//PA_SU_POLY_OFFSET_DB_FMT_CNTL
#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS__SHIFT                                     0x0
#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT__SHIFT                                     0x8
#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS_MASK                                       0x000000FFL
#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT_MASK                                       0x00000100L
//PA_SU_POLY_OFFSET_CLAMP
#define PA_SU_POLY_OFFSET_CLAMP__CLAMP__SHIFT                                                                 0x0
#define PA_SU_POLY_OFFSET_CLAMP__CLAMP_MASK                                                                   0xFFFFFFFFL
//PA_SU_POLY_OFFSET_FRONT_SCALE
#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT                                                           0x0
#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK                                                             0xFFFFFFFFL
//PA_SU_POLY_OFFSET_FRONT_OFFSET
#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT                                                         0x0
#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK                                                           0xFFFFFFFFL
//PA_SU_POLY_OFFSET_BACK_SCALE
#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT                                                            0x0
#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK                                                              0xFFFFFFFFL
//PA_SU_POLY_OFFSET_BACK_OFFSET
#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT                                                          0x0
#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK                                                            0xFFFFFFFFL
//VGT_GS_INSTANCE_CNT
#define VGT_GS_INSTANCE_CNT__ENABLE__SHIFT                                                                    0x0
#define VGT_GS_INSTANCE_CNT__CNT__SHIFT                                                                       0x2
#define VGT_GS_INSTANCE_CNT__EN_MAX_VERT_OUT_PER_GS_INSTANCE__SHIFT                                           0x1f
#define VGT_GS_INSTANCE_CNT__ENABLE_MASK                                                                      0x00000001L
#define VGT_GS_INSTANCE_CNT__CNT_MASK                                                                         0x000001FCL
#define VGT_GS_INSTANCE_CNT__EN_MAX_VERT_OUT_PER_GS_INSTANCE_MASK                                             0x80000000L
//VGT_STRMOUT_CONFIG
#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN__SHIFT                                                             0x0
#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN__SHIFT                                                             0x1
#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN__SHIFT                                                             0x2
#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN__SHIFT                                                             0x3
#define VGT_STRMOUT_CONFIG__RAST_STREAM__SHIFT                                                                0x4
#define VGT_STRMOUT_CONFIG__EN_PRIMS_NEEDED_CNT__SHIFT                                                        0x7
#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK__SHIFT                                                           0x8
#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK__SHIFT                                                       0x1f
#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN_MASK                                                               0x00000001L
#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN_MASK                                                               0x00000002L
#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN_MASK                                                               0x00000004L
#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN_MASK                                                               0x00000008L
#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK                                                                  0x00000070L
#define VGT_STRMOUT_CONFIG__EN_PRIMS_NEEDED_CNT_MASK                                                          0x00000080L
#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK_MASK                                                             0x00000F00L
#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK_MASK                                                         0x80000000L
//VGT_STRMOUT_BUFFER_CONFIG
#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN__SHIFT                                                  0x0
#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN__SHIFT                                                  0x4
#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN__SHIFT                                                  0x8
#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN__SHIFT                                                  0xc
#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN_MASK                                                    0x0000000FL
#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN_MASK                                                    0x000000F0L
#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN_MASK                                                    0x00000F00L
#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN_MASK                                                    0x0000F000L
//VGT_DMA_EVENT_INITIATOR
#define VGT_DMA_EVENT_INITIATOR__EVENT_TYPE__SHIFT                                                            0x0
#define VGT_DMA_EVENT_INITIATOR__ADDRESS_HI__SHIFT                                                            0xa
#define VGT_DMA_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT                                                        0x1b
#define VGT_DMA_EVENT_INITIATOR__EVENT_TYPE_MASK                                                              0x0000003FL
#define VGT_DMA_EVENT_INITIATOR__ADDRESS_HI_MASK                                                              0x07FFFC00L
#define VGT_DMA_EVENT_INITIATOR__EXTENDED_EVENT_MASK                                                          0x08000000L
//PA_SC_CENTROID_PRIORITY_0
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0__SHIFT                                                          0x0
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1__SHIFT                                                          0x4
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2__SHIFT                                                          0x8
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3__SHIFT                                                          0xc
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4__SHIFT                                                          0x10
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5__SHIFT                                                          0x14
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6__SHIFT                                                          0x18
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7__SHIFT                                                          0x1c
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0_MASK                                                            0x0000000FL
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1_MASK                                                            0x000000F0L
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2_MASK                                                            0x00000F00L
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3_MASK                                                            0x0000F000L
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4_MASK                                                            0x000F0000L
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5_MASK                                                            0x00F00000L
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6_MASK                                                            0x0F000000L
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7_MASK                                                            0xF0000000L
//PA_SC_CENTROID_PRIORITY_1
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8__SHIFT                                                          0x0
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9__SHIFT                                                          0x4
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10__SHIFT                                                         0x8
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11__SHIFT                                                         0xc
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12__SHIFT                                                         0x10
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13__SHIFT                                                         0x14
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14__SHIFT                                                         0x18
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15__SHIFT                                                         0x1c
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8_MASK                                                            0x0000000FL
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9_MASK                                                            0x000000F0L
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10_MASK                                                           0x00000F00L
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11_MASK                                                           0x0000F000L
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12_MASK                                                           0x000F0000L
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13_MASK                                                           0x00F00000L
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14_MASK                                                           0x0F000000L
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15_MASK                                                           0xF0000000L
//PA_SC_LINE_CNTL
#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT                                                             0x9
#define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT                                                                    0xa
#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA__SHIFT                                                      0xb
#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA__SHIFT                                                         0xc
#define PA_SC_LINE_CNTL__EXTRA_DX_DY_PRECISION__SHIFT                                                         0xd
#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK                                                               0x00000200L
#define PA_SC_LINE_CNTL__LAST_PIXEL_MASK                                                                      0x00000400L
#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA_MASK                                                        0x00000800L
#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA_MASK                                                           0x00001000L
#define PA_SC_LINE_CNTL__EXTRA_DX_DY_PRECISION_MASK                                                           0x00002000L
//PA_SC_AA_CONFIG
#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT                                                              0x0
#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN__SHIFT                                                         0x4
#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT                                                               0xd
#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES__SHIFT                                                          0x14
#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE__SHIFT                                                        0x18
#define PA_SC_AA_CONFIG__COVERAGE_TO_SHADER_SELECT__SHIFT                                                     0x1a
#define PA_SC_AA_CONFIG__SAMPLE_COVERAGE_ENCODING__SHIFT                                                      0x1c
#define PA_SC_AA_CONFIG__COVERED_CENTROID_IS_CENTER__SHIFT                                                    0x1d
#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK                                                                0x00000007L
#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN_MASK                                                           0x00000010L
#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK                                                                 0x0001E000L
#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES_MASK                                                            0x00700000L
#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE_MASK                                                          0x03000000L
#define PA_SC_AA_CONFIG__COVERAGE_TO_SHADER_SELECT_MASK                                                       0x0C000000L
#define PA_SC_AA_CONFIG__SAMPLE_COVERAGE_ENCODING_MASK                                                        0x10000000L
#define PA_SC_AA_CONFIG__COVERED_CENTROID_IS_CENTER_MASK                                                      0x20000000L
//PA_SU_VTX_CNTL
#define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT                                                                     0x0
#define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT                                                                     0x1
#define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT                                                                     0x3
#define PA_SU_VTX_CNTL__PIX_CENTER_MASK                                                                       0x00000001L
#define PA_SU_VTX_CNTL__ROUND_MODE_MASK                                                                       0x00000006L
#define PA_SU_VTX_CNTL__QUANT_MODE_MASK                                                                       0x00000038L
//PA_CL_GB_VERT_CLIP_ADJ
#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT                                                          0x0
#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK                                                            0xFFFFFFFFL
//PA_CL_GB_VERT_DISC_ADJ
#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT                                                          0x0
#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK                                                            0xFFFFFFFFL
//PA_CL_GB_HORZ_CLIP_ADJ
#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT                                                          0x0
#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK                                                            0xFFFFFFFFL
//PA_CL_GB_HORZ_DISC_ADJ
#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT                                                          0x0
#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK                                                            0xFFFFFFFFL
//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X__SHIFT                                                        0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y__SHIFT                                                        0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X__SHIFT                                                        0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y__SHIFT                                                        0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X__SHIFT                                                        0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y__SHIFT                                                        0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X__SHIFT                                                        0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y__SHIFT                                                        0x1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X_MASK                                                          0x0000000FL
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y_MASK                                                          0x000000F0L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X_MASK                                                          0x00000F00L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y_MASK                                                          0x0000F000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X_MASK                                                          0x000F0000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y_MASK                                                          0x00F00000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X_MASK                                                          0x0F000000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y_MASK                                                          0xF0000000L
//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X__SHIFT                                                        0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y__SHIFT                                                        0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X__SHIFT                                                        0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y__SHIFT                                                        0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X__SHIFT                                                        0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y__SHIFT                                                        0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X__SHIFT                                                        0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y__SHIFT                                                        0x1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X_MASK                                                          0x0000000FL
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y_MASK                                                          0x000000F0L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X_MASK                                                          0x00000F00L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y_MASK                                                          0x0000F000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X_MASK                                                          0x000F0000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y_MASK                                                          0x00F00000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X_MASK                                                          0x0F000000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y_MASK                                                          0xF0000000L
//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X__SHIFT                                                        0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y__SHIFT                                                        0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X__SHIFT                                                        0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y__SHIFT                                                        0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X__SHIFT                                                       0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y__SHIFT                                                       0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X__SHIFT                                                       0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y__SHIFT                                                       0x1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X_MASK                                                          0x0000000FL
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y_MASK                                                          0x000000F0L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X_MASK                                                          0x00000F00L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y_MASK                                                          0x0000F000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X_MASK                                                         0x000F0000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y_MASK                                                         0x00F00000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X_MASK                                                         0x0F000000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y_MASK                                                         0xF0000000L
//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X__SHIFT                                                       0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y__SHIFT                                                       0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X__SHIFT                                                       0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y__SHIFT                                                       0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X__SHIFT                                                       0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y__SHIFT                                                       0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X__SHIFT                                                       0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y__SHIFT                                                       0x1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X_MASK                                                         0x0000000FL
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y_MASK                                                         0x000000F0L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X_MASK                                                         0x00000F00L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y_MASK                                                         0x0000F000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X_MASK                                                         0x000F0000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y_MASK                                                         0x00F00000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X_MASK                                                         0x0F000000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y_MASK                                                         0xF0000000L
//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X__SHIFT                                                        0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y__SHIFT                                                        0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X__SHIFT                                                        0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y__SHIFT                                                        0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X__SHIFT                                                        0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y__SHIFT                                                        0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X__SHIFT                                                        0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y__SHIFT                                                        0x1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X_MASK                                                          0x0000000FL
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y_MASK                                                          0x000000F0L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X_MASK                                                          0x00000F00L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y_MASK                                                          0x0000F000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X_MASK                                                          0x000F0000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y_MASK                                                          0x00F00000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X_MASK                                                          0x0F000000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y_MASK                                                          0xF0000000L
//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X__SHIFT                                                        0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y__SHIFT                                                        0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X__SHIFT                                                        0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y__SHIFT                                                        0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X__SHIFT                                                        0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y__SHIFT                                                        0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X__SHIFT                                                        0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y__SHIFT                                                        0x1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X_MASK                                                          0x0000000FL
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y_MASK                                                          0x000000F0L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X_MASK                                                          0x00000F00L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y_MASK                                                          0x0000F000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X_MASK                                                          0x000F0000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y_MASK                                                          0x00F00000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X_MASK                                                          0x0F000000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y_MASK                                                          0xF0000000L
//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X__SHIFT                                                        0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y__SHIFT                                                        0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X__SHIFT                                                        0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y__SHIFT                                                        0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X__SHIFT                                                       0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y__SHIFT                                                       0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X__SHIFT                                                       0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y__SHIFT                                                       0x1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X_MASK                                                          0x0000000FL
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y_MASK                                                          0x000000F0L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X_MASK                                                          0x00000F00L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y_MASK                                                          0x0000F000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X_MASK                                                         0x000F0000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y_MASK                                                         0x00F00000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X_MASK                                                         0x0F000000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y_MASK                                                         0xF0000000L
//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X__SHIFT                                                       0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y__SHIFT                                                       0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X__SHIFT                                                       0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y__SHIFT                                                       0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X__SHIFT                                                       0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y__SHIFT                                                       0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X__SHIFT                                                       0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y__SHIFT                                                       0x1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X_MASK                                                         0x0000000FL
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y_MASK                                                         0x000000F0L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X_MASK                                                         0x00000F00L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y_MASK                                                         0x0000F000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X_MASK                                                         0x000F0000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y_MASK                                                         0x00F00000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X_MASK                                                         0x0F000000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y_MASK                                                         0xF0000000L
//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X__SHIFT                                                        0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y__SHIFT                                                        0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X__SHIFT                                                        0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y__SHIFT                                                        0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X__SHIFT                                                        0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y__SHIFT                                                        0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X__SHIFT                                                        0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y__SHIFT                                                        0x1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X_MASK                                                          0x0000000FL
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y_MASK                                                          0x000000F0L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X_MASK                                                          0x00000F00L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y_MASK                                                          0x0000F000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X_MASK                                                          0x000F0000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y_MASK                                                          0x00F00000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X_MASK                                                          0x0F000000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y_MASK                                                          0xF0000000L
//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X__SHIFT                                                        0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y__SHIFT                                                        0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X__SHIFT                                                        0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y__SHIFT                                                        0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X__SHIFT                                                        0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y__SHIFT                                                        0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X__SHIFT                                                        0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y__SHIFT                                                        0x1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X_MASK                                                          0x0000000FL
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y_MASK                                                          0x000000F0L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X_MASK                                                          0x00000F00L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y_MASK                                                          0x0000F000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X_MASK                                                          0x000F0000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y_MASK                                                          0x00F00000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X_MASK                                                          0x0F000000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y_MASK                                                          0xF0000000L
//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X__SHIFT                                                        0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y__SHIFT                                                        0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X__SHIFT                                                        0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y__SHIFT                                                        0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X__SHIFT                                                       0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y__SHIFT                                                       0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X__SHIFT                                                       0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y__SHIFT                                                       0x1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X_MASK                                                          0x0000000FL
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y_MASK                                                          0x000000F0L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X_MASK                                                          0x00000F00L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y_MASK                                                          0x0000F000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X_MASK                                                         0x000F0000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y_MASK                                                         0x00F00000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X_MASK                                                         0x0F000000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y_MASK                                                         0xF0000000L
//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X__SHIFT                                                       0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y__SHIFT                                                       0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X__SHIFT                                                       0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y__SHIFT                                                       0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X__SHIFT                                                       0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y__SHIFT                                                       0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X__SHIFT                                                       0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y__SHIFT                                                       0x1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X_MASK                                                         0x0000000FL
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y_MASK                                                         0x000000F0L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X_MASK                                                         0x00000F00L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y_MASK                                                         0x0000F000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X_MASK                                                         0x000F0000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y_MASK                                                         0x00F00000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X_MASK                                                         0x0F000000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y_MASK                                                         0xF0000000L
//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X__SHIFT                                                        0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y__SHIFT                                                        0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X__SHIFT                                                        0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y__SHIFT                                                        0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X__SHIFT                                                        0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y__SHIFT                                                        0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X__SHIFT                                                        0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y__SHIFT                                                        0x1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X_MASK                                                          0x0000000FL
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y_MASK                                                          0x000000F0L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X_MASK                                                          0x00000F00L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y_MASK                                                          0x0000F000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X_MASK                                                          0x000F0000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y_MASK                                                          0x00F00000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X_MASK                                                          0x0F000000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y_MASK                                                          0xF0000000L
//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X__SHIFT                                                        0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y__SHIFT                                                        0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X__SHIFT                                                        0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y__SHIFT                                                        0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X__SHIFT                                                        0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y__SHIFT                                                        0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X__SHIFT                                                        0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y__SHIFT                                                        0x1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X_MASK                                                          0x0000000FL
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y_MASK                                                          0x000000F0L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X_MASK                                                          0x00000F00L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y_MASK                                                          0x0000F000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X_MASK                                                          0x000F0000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y_MASK                                                          0x00F00000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X_MASK                                                          0x0F000000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y_MASK                                                          0xF0000000L
//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X__SHIFT                                                        0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y__SHIFT                                                        0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X__SHIFT                                                        0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y__SHIFT                                                        0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X__SHIFT                                                       0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y__SHIFT                                                       0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X__SHIFT                                                       0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y__SHIFT                                                       0x1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X_MASK                                                          0x0000000FL
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y_MASK                                                          0x000000F0L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X_MASK                                                          0x00000F00L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y_MASK                                                          0x0000F000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X_MASK                                                         0x000F0000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y_MASK                                                         0x00F00000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X_MASK                                                         0x0F000000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y_MASK                                                         0xF0000000L
//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X__SHIFT                                                       0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y__SHIFT                                                       0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X__SHIFT                                                       0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y__SHIFT                                                       0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X__SHIFT                                                       0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y__SHIFT                                                       0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X__SHIFT                                                       0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y__SHIFT                                                       0x1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X_MASK                                                         0x0000000FL
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y_MASK                                                         0x000000F0L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X_MASK                                                         0x00000F00L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y_MASK                                                         0x0000F000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X_MASK                                                         0x000F0000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y_MASK                                                         0x00F00000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X_MASK                                                         0x0F000000L
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y_MASK                                                         0xF0000000L
//PA_SC_AA_MASK_X0Y0_X1Y0
#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0__SHIFT                                                          0x0
#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0__SHIFT                                                          0x10
#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0_MASK                                                            0x0000FFFFL
#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0_MASK                                                            0xFFFF0000L
//PA_SC_AA_MASK_X0Y1_X1Y1
#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1__SHIFT                                                          0x0
#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1__SHIFT                                                          0x10
#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1_MASK                                                            0x0000FFFFL
#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1_MASK                                                            0xFFFF0000L
//PA_SC_SHADER_CONTROL
#define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES__SHIFT                                             0x0
#define PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID__SHIFT                                                    0x2
#define PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION__SHIFT                                                 0x3
#define PA_SC_SHADER_CONTROL__WAVE_BREAK_REGION_SIZE__SHIFT                                                   0x5
#define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES_MASK                                               0x00000003L
#define PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID_MASK                                                      0x00000004L
#define PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION_MASK                                                   0x00000008L
#define PA_SC_SHADER_CONTROL__WAVE_BREAK_REGION_SIZE_MASK                                                     0x00000060L
//PA_SC_BINNER_CNTL_0
#define PA_SC_BINNER_CNTL_0__BINNING_MODE__SHIFT                                                              0x0
#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X__SHIFT                                                                0x2
#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y__SHIFT                                                                0x3
#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND__SHIFT                                                         0x4
#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND__SHIFT                                                         0x7
#define PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN__SHIFT                                                    0xa
#define PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN__SHIFT                                                 0xd
#define PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM__SHIFT                                                     0x12
#define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH__SHIFT                                                           0x13
#define PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION__SHIFT                                                     0x1b
#define PA_SC_BINNER_CNTL_0__FLUSH_ON_BINNING_TRANSITION__SHIFT                                               0x1c
#define PA_SC_BINNER_CNTL_0__BIN_MAPPING_MODE__SHIFT                                                          0x1d
#define PA_SC_BINNER_CNTL_0__BINNING_MODE_MASK                                                                0x00000003L
#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_MASK                                                                  0x00000004L
#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_MASK                                                                  0x00000008L
#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND_MASK                                                           0x00000070L
#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND_MASK                                                           0x00000380L
#define PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN_MASK                                                      0x00001C00L
#define PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN_MASK                                                   0x0003E000L
#define PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM_MASK                                                       0x00040000L
#define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH_MASK                                                             0x07F80000L
#define PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION_MASK                                                       0x08000000L
#define PA_SC_BINNER_CNTL_0__FLUSH_ON_BINNING_TRANSITION_MASK                                                 0x10000000L
#define PA_SC_BINNER_CNTL_0__BIN_MAPPING_MODE_MASK                                                            0x60000000L
//PA_SC_BINNER_CNTL_1
#define PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT__SHIFT                                                           0x0
#define PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH__SHIFT                                                        0x10
#define PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT_MASK                                                             0x0000FFFFL
#define PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH_MASK                                                          0xFFFF0000L
//PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE__SHIFT                                        0x0
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT__SHIFT                                 0x1
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE__SHIFT                                       0x5
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT__SHIFT                                0x6
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE__SHIFT                           0xa
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT__SHIFT                                          0xb
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET__SHIFT                                          0xc
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL__SHIFT                      0xd
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL__SHIFT                     0xe
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE__SHIFT             0xf
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE__SHIFT                                 0x10
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT                     0x12
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT                     0x13
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE__SHIFT                               0x14
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE__SHIFT                                 0x15
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE__SHIFT                                     0x16
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE__SHIFT                                    0x17
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE__SHIFT                                0x18
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MULT__SHIFT                                 0x19
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_PBB_MULT__SHIFT                             0x1b
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE_MASK                                          0x00000001L
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT_MASK                                   0x0000001EL
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE_MASK                                         0x00000020L
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT_MASK                                  0x000003C0L
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE_MASK                             0x00000400L
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT_MASK                                            0x00000800L
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET_MASK                                            0x00001000L
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL_MASK                        0x00002000L
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL_MASK                       0x00004000L
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE_MASK               0x00008000L
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE_MASK                                   0x00030000L
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK                       0x00040000L
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK                       0x00080000L
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE_MASK                                 0x00100000L
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE_MASK                                   0x00200000L
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE_MASK                                       0x00400000L
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE_MASK                                      0x00800000L
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE_MASK                                  0x01000000L
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MULT_MASK                                   0x06000000L
#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_PBB_MULT_MASK                               0x18000000L
//PA_SC_NGG_MODE_CNTL
#define PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE__SHIFT                                                      0x0
#define PA_SC_NGG_MODE_CNTL__MAX_FPOVS_IN_WAVE__SHIFT                                                         0x10
#define PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE_MASK                                                        0x000007FFL
#define PA_SC_NGG_MODE_CNTL__MAX_FPOVS_IN_WAVE_MASK                                                           0x00FF0000L
//VGT_VERTEX_REUSE_BLOCK_CNTL
#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT                                                   0x0
#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK                                                     0x000000FFL
//VGT_OUT_DEALLOC_CNTL
#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT                                                             0x0
#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK                                                               0x0000007FL
//CB_COLOR0_BASE
#define CB_COLOR0_BASE__BASE_256B__SHIFT                                                                      0x0
#define CB_COLOR0_BASE__BASE_256B_MASK                                                                        0xFFFFFFFFL
//CB_COLOR0_PITCH
#define CB_COLOR0_PITCH__TILE_MAX__SHIFT                                                                      0x0
#define CB_COLOR0_PITCH__FMASK_TILE_MAX__SHIFT                                                                0x14
#define CB_COLOR0_PITCH__TILE_MAX_MASK                                                                        0x000007FFL
#define CB_COLOR0_PITCH__FMASK_TILE_MAX_MASK                                                                  0x7FF00000L
//CB_COLOR0_SLICE
#define CB_COLOR0_SLICE__TILE_MAX__SHIFT                                                                      0x0
#define CB_COLOR0_SLICE__TILE_MAX_MASK                                                                        0x003FFFFFL
//CB_COLOR0_VIEW
#define CB_COLOR0_VIEW__SLICE_START__SHIFT                                                                    0x0
#define CB_COLOR0_VIEW__SLICE_MAX__SHIFT                                                                      0xd
#define CB_COLOR0_VIEW__MIP_LEVEL__SHIFT                                                                      0x1a
#define CB_COLOR0_VIEW__SLICE_START_MASK                                                                      0x00001FFFL
#define CB_COLOR0_VIEW__SLICE_MAX_MASK                                                                        0x03FFE000L
#define CB_COLOR0_VIEW__MIP_LEVEL_MASK                                                                        0x3C000000L
//CB_COLOR0_INFO
#define CB_COLOR0_INFO__ENDIAN__SHIFT                                                                         0x0
#define CB_COLOR0_INFO__FORMAT__SHIFT                                                                         0x2
#define CB_COLOR0_INFO__LINEAR_GENERAL__SHIFT                                                                 0x7
#define CB_COLOR0_INFO__NUMBER_TYPE__SHIFT                                                                    0x8
#define CB_COLOR0_INFO__COMP_SWAP__SHIFT                                                                      0xb
#define CB_COLOR0_INFO__FAST_CLEAR__SHIFT                                                                     0xd
#define CB_COLOR0_INFO__COMPRESSION__SHIFT                                                                    0xe
#define CB_COLOR0_INFO__BLEND_CLAMP__SHIFT                                                                    0xf
#define CB_COLOR0_INFO__BLEND_BYPASS__SHIFT                                                                   0x10
#define CB_COLOR0_INFO__SIMPLE_FLOAT__SHIFT                                                                   0x11
#define CB_COLOR0_INFO__ROUND_MODE__SHIFT                                                                     0x12
#define CB_COLOR0_INFO__CMASK_IS_LINEAR__SHIFT                                                                0x13
#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST__SHIFT                                                          0x14
#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT                                                        0x17
#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE__SHIFT                                                      0x1a
#define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT                                                      0x1b
#define CB_COLOR0_INFO__DCC_ENABLE__SHIFT                                                                     0x1c
#define CB_COLOR0_INFO__CMASK_ADDR_TYPE__SHIFT                                                                0x1d
#define CB_COLOR0_INFO__NBC_TILING__SHIFT                                                                     0x1f
#define CB_COLOR0_INFO__ENDIAN_MASK                                                                           0x00000003L
#define CB_COLOR0_INFO__FORMAT_MASK                                                                           0x0000007CL
#define CB_COLOR0_INFO__LINEAR_GENERAL_MASK                                                                   0x00000080L
#define CB_COLOR0_INFO__NUMBER_TYPE_MASK                                                                      0x00000700L
#define CB_COLOR0_INFO__COMP_SWAP_MASK                                                                        0x00001800L
#define CB_COLOR0_INFO__FAST_CLEAR_MASK                                                                       0x00002000L
#define CB_COLOR0_INFO__COMPRESSION_MASK                                                                      0x00004000L
#define CB_COLOR0_INFO__BLEND_CLAMP_MASK                                                                      0x00008000L
#define CB_COLOR0_INFO__BLEND_BYPASS_MASK                                                                     0x00010000L
#define CB_COLOR0_INFO__SIMPLE_FLOAT_MASK                                                                     0x00020000L
#define CB_COLOR0_INFO__ROUND_MODE_MASK                                                                       0x00040000L
#define CB_COLOR0_INFO__CMASK_IS_LINEAR_MASK                                                                  0x00080000L
#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST_MASK                                                            0x00700000L
#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL_MASK                                                          0x03800000L
#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE_MASK                                                        0x04000000L
#define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK                                                        0x08000000L
#define CB_COLOR0_INFO__DCC_ENABLE_MASK                                                                       0x10000000L
#define CB_COLOR0_INFO__CMASK_ADDR_TYPE_MASK                                                                  0x60000000L
#define CB_COLOR0_INFO__NBC_TILING_MASK                                                                       0x80000000L
//CB_COLOR0_ATTRIB
#define CB_COLOR0_ATTRIB__TILE_MODE_INDEX__SHIFT                                                              0x0
#define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT                                                        0x5
#define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT__SHIFT                                                            0xa
#define CB_COLOR0_ATTRIB__NUM_SAMPLES__SHIFT                                                                  0xc
#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS__SHIFT                                                                0xf
#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1__SHIFT                                                            0x11
#define CB_COLOR0_ATTRIB__DISABLE_FMASK_NOFETCH_OPT__SHIFT                                                    0x12
#define CB_COLOR0_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT                                                0x13
#define CB_COLOR0_ATTRIB__TILE_MODE_INDEX_MASK                                                                0x0000001FL
#define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX_MASK                                                          0x000003E0L
#define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT_MASK                                                              0x00000C00L
#define CB_COLOR0_ATTRIB__NUM_SAMPLES_MASK                                                                    0x00007000L
#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS_MASK                                                                  0x00018000L
#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1_MASK                                                              0x00020000L
#define CB_COLOR0_ATTRIB__DISABLE_FMASK_NOFETCH_OPT_MASK                                                      0x00040000L
#define CB_COLOR0_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK                                                  0x00080000L
//CB_COLOR0_DCC_CONTROL
#define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT                                              0x0
#define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT                                                        0x1
#define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT                                             0x2
#define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x4
#define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x5
#define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM__SHIFT                                                         0x7
#define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT                                                  0x9
#define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT                                                     0xa
#define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT                                                   0xe
#define CB_COLOR0_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT                                             0x12
#define CB_COLOR0_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT                                        0x13
#define CB_COLOR0_DCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT                                                 0x14
#define CB_COLOR0_DCC_CONTROL__SKIP_LOW_COMP_RATIO__SHIFT                                                     0x15
#define CB_COLOR0_DCC_CONTROL__DCC_COMPRESS_DISABLE__SHIFT                                                    0x16
#define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK                                                0x00000001L
#define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK                                                          0x00000002L
#define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK                                               0x0000000CL
#define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000010L
#define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000060L
#define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM_MASK                                                           0x00000180L
#define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK                                                    0x00000200L
#define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK                                                       0x00003C00L
#define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK                                                     0x0003C000L
#define CB_COLOR0_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK                                               0x00040000L
#define CB_COLOR0_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK                                          0x00080000L
#define CB_COLOR0_DCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK                                                   0x00100000L
#define CB_COLOR0_DCC_CONTROL__SKIP_LOW_COMP_RATIO_MASK                                                       0x00200000L
#define CB_COLOR0_DCC_CONTROL__DCC_COMPRESS_DISABLE_MASK                                                      0x00400000L
//CB_COLOR0_CMASK
#define CB_COLOR0_CMASK__BASE_256B__SHIFT                                                                     0x0
#define CB_COLOR0_CMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
//CB_COLOR0_CMASK_SLICE
#define CB_COLOR0_CMASK_SLICE__TILE_MAX__SHIFT                                                                0x0
#define CB_COLOR0_CMASK_SLICE__TILE_MAX_MASK                                                                  0x00003FFFL
//CB_COLOR0_FMASK
#define CB_COLOR0_FMASK__BASE_256B__SHIFT                                                                     0x0
#define CB_COLOR0_FMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
//CB_COLOR0_FMASK_SLICE
#define CB_COLOR0_FMASK_SLICE__TILE_MAX__SHIFT                                                                0x0
#define CB_COLOR0_FMASK_SLICE__TILE_MAX_MASK                                                                  0x003FFFFFL
//CB_COLOR0_CLEAR_WORD0
#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0__SHIFT                                                             0x0
#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0_MASK                                                               0xFFFFFFFFL
//CB_COLOR0_CLEAR_WORD1
#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1__SHIFT                                                             0x0
#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1_MASK                                                               0xFFFFFFFFL
//CB_COLOR0_DCC_BASE
#define CB_COLOR0_DCC_BASE__BASE_256B__SHIFT                                                                  0x0
#define CB_COLOR0_DCC_BASE__BASE_256B_MASK                                                                    0xFFFFFFFFL
//CB_COLOR1_BASE
#define CB_COLOR1_BASE__BASE_256B__SHIFT                                                                      0x0
#define CB_COLOR1_BASE__BASE_256B_MASK                                                                        0xFFFFFFFFL
//CB_COLOR1_PITCH
#define CB_COLOR1_PITCH__TILE_MAX__SHIFT                                                                      0x0
#define CB_COLOR1_PITCH__FMASK_TILE_MAX__SHIFT                                                                0x14
#define CB_COLOR1_PITCH__TILE_MAX_MASK                                                                        0x000007FFL
#define CB_COLOR1_PITCH__FMASK_TILE_MAX_MASK                                                                  0x7FF00000L
//CB_COLOR1_SLICE
#define CB_COLOR1_SLICE__TILE_MAX__SHIFT                                                                      0x0
#define CB_COLOR1_SLICE__TILE_MAX_MASK                                                                        0x003FFFFFL
//CB_COLOR1_VIEW
#define CB_COLOR1_VIEW__SLICE_START__SHIFT                                                                    0x0
#define CB_COLOR1_VIEW__SLICE_MAX__SHIFT                                                                      0xd
#define CB_COLOR1_VIEW__MIP_LEVEL__SHIFT                                                                      0x1a
#define CB_COLOR1_VIEW__SLICE_START_MASK                                                                      0x00001FFFL
#define CB_COLOR1_VIEW__SLICE_MAX_MASK                                                                        0x03FFE000L
#define CB_COLOR1_VIEW__MIP_LEVEL_MASK                                                                        0x3C000000L
//CB_COLOR1_INFO
#define CB_COLOR1_INFO__ENDIAN__SHIFT                                                                         0x0
#define CB_COLOR1_INFO__FORMAT__SHIFT                                                                         0x2
#define CB_COLOR1_INFO__LINEAR_GENERAL__SHIFT                                                                 0x7
#define CB_COLOR1_INFO__NUMBER_TYPE__SHIFT                                                                    0x8
#define CB_COLOR1_INFO__COMP_SWAP__SHIFT                                                                      0xb
#define CB_COLOR1_INFO__FAST_CLEAR__SHIFT                                                                     0xd
#define CB_COLOR1_INFO__COMPRESSION__SHIFT                                                                    0xe
#define CB_COLOR1_INFO__BLEND_CLAMP__SHIFT                                                                    0xf
#define CB_COLOR1_INFO__BLEND_BYPASS__SHIFT                                                                   0x10
#define CB_COLOR1_INFO__SIMPLE_FLOAT__SHIFT                                                                   0x11
#define CB_COLOR1_INFO__ROUND_MODE__SHIFT                                                                     0x12
#define CB_COLOR1_INFO__CMASK_IS_LINEAR__SHIFT                                                                0x13
#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST__SHIFT                                                          0x14
#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT                                                        0x17
#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE__SHIFT                                                      0x1a
#define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT                                                      0x1b
#define CB_COLOR1_INFO__DCC_ENABLE__SHIFT                                                                     0x1c
#define CB_COLOR1_INFO__CMASK_ADDR_TYPE__SHIFT                                                                0x1d
#define CB_COLOR1_INFO__NBC_TILING__SHIFT                                                                     0x1f
#define CB_COLOR1_INFO__ENDIAN_MASK                                                                           0x00000003L
#define CB_COLOR1_INFO__FORMAT_MASK                                                                           0x0000007CL
#define CB_COLOR1_INFO__LINEAR_GENERAL_MASK                                                                   0x00000080L
#define CB_COLOR1_INFO__NUMBER_TYPE_MASK                                                                      0x00000700L
#define CB_COLOR1_INFO__COMP_SWAP_MASK                                                                        0x00001800L
#define CB_COLOR1_INFO__FAST_CLEAR_MASK                                                                       0x00002000L
#define CB_COLOR1_INFO__COMPRESSION_MASK                                                                      0x00004000L
#define CB_COLOR1_INFO__BLEND_CLAMP_MASK                                                                      0x00008000L
#define CB_COLOR1_INFO__BLEND_BYPASS_MASK                                                                     0x00010000L
#define CB_COLOR1_INFO__SIMPLE_FLOAT_MASK                                                                     0x00020000L
#define CB_COLOR1_INFO__ROUND_MODE_MASK                                                                       0x00040000L
#define CB_COLOR1_INFO__CMASK_IS_LINEAR_MASK                                                                  0x00080000L
#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST_MASK                                                            0x00700000L
#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL_MASK                                                          0x03800000L
#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE_MASK                                                        0x04000000L
#define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK                                                        0x08000000L
#define CB_COLOR1_INFO__DCC_ENABLE_MASK                                                                       0x10000000L
#define CB_COLOR1_INFO__CMASK_ADDR_TYPE_MASK                                                                  0x60000000L
#define CB_COLOR1_INFO__NBC_TILING_MASK                                                                       0x80000000L
//CB_COLOR1_ATTRIB
#define CB_COLOR1_ATTRIB__TILE_MODE_INDEX__SHIFT                                                              0x0
#define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT                                                        0x5
#define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT__SHIFT                                                            0xa
#define CB_COLOR1_ATTRIB__NUM_SAMPLES__SHIFT                                                                  0xc
#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS__SHIFT                                                                0xf
#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1__SHIFT                                                            0x11
#define CB_COLOR1_ATTRIB__DISABLE_FMASK_NOFETCH_OPT__SHIFT                                                    0x12
#define CB_COLOR1_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT                                                0x13
#define CB_COLOR1_ATTRIB__TILE_MODE_INDEX_MASK                                                                0x0000001FL
#define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX_MASK                                                          0x000003E0L
#define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT_MASK                                                              0x00000C00L
#define CB_COLOR1_ATTRIB__NUM_SAMPLES_MASK                                                                    0x00007000L
#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS_MASK                                                                  0x00018000L
#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1_MASK                                                              0x00020000L
#define CB_COLOR1_ATTRIB__DISABLE_FMASK_NOFETCH_OPT_MASK                                                      0x00040000L
#define CB_COLOR1_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK                                                  0x00080000L
//CB_COLOR1_DCC_CONTROL
#define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT                                              0x0
#define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT                                                        0x1
#define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT                                             0x2
#define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x4
#define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x5
#define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM__SHIFT                                                         0x7
#define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT                                                  0x9
#define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT                                                     0xa
#define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT                                                   0xe
#define CB_COLOR1_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT                                             0x12
#define CB_COLOR1_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT                                        0x13
#define CB_COLOR1_DCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT                                                 0x14
#define CB_COLOR1_DCC_CONTROL__SKIP_LOW_COMP_RATIO__SHIFT                                                     0x15
#define CB_COLOR1_DCC_CONTROL__DCC_COMPRESS_DISABLE__SHIFT                                                    0x16
#define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK                                                0x00000001L
#define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK                                                          0x00000002L
#define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK                                               0x0000000CL
#define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000010L
#define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000060L
#define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM_MASK                                                           0x00000180L
#define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK                                                    0x00000200L
#define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK                                                       0x00003C00L
#define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK                                                     0x0003C000L
#define CB_COLOR1_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK                                               0x00040000L
#define CB_COLOR1_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK                                          0x00080000L
#define CB_COLOR1_DCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK                                                   0x00100000L
#define CB_COLOR1_DCC_CONTROL__SKIP_LOW_COMP_RATIO_MASK                                                       0x00200000L
#define CB_COLOR1_DCC_CONTROL__DCC_COMPRESS_DISABLE_MASK                                                      0x00400000L
//CB_COLOR1_CMASK
#define CB_COLOR1_CMASK__BASE_256B__SHIFT                                                                     0x0
#define CB_COLOR1_CMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
//CB_COLOR1_CMASK_SLICE
#define CB_COLOR1_CMASK_SLICE__TILE_MAX__SHIFT                                                                0x0
#define CB_COLOR1_CMASK_SLICE__TILE_MAX_MASK                                                                  0x00003FFFL
//CB_COLOR1_FMASK
#define CB_COLOR1_FMASK__BASE_256B__SHIFT                                                                     0x0
#define CB_COLOR1_FMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
//CB_COLOR1_FMASK_SLICE
#define CB_COLOR1_FMASK_SLICE__TILE_MAX__SHIFT                                                                0x0
#define CB_COLOR1_FMASK_SLICE__TILE_MAX_MASK                                                                  0x003FFFFFL
//CB_COLOR1_CLEAR_WORD0
#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0__SHIFT                                                             0x0
#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0_MASK                                                               0xFFFFFFFFL
//CB_COLOR1_CLEAR_WORD1
#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1__SHIFT                                                             0x0
#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1_MASK                                                               0xFFFFFFFFL
//CB_COLOR1_DCC_BASE
#define CB_COLOR1_DCC_BASE__BASE_256B__SHIFT                                                                  0x0
#define CB_COLOR1_DCC_BASE__BASE_256B_MASK                                                                    0xFFFFFFFFL
//CB_COLOR2_BASE
#define CB_COLOR2_BASE__BASE_256B__SHIFT                                                                      0x0
#define CB_COLOR2_BASE__BASE_256B_MASK                                                                        0xFFFFFFFFL
//CB_COLOR2_PITCH
#define CB_COLOR2_PITCH__TILE_MAX__SHIFT                                                                      0x0
#define CB_COLOR2_PITCH__FMASK_TILE_MAX__SHIFT                                                                0x14
#define CB_COLOR2_PITCH__TILE_MAX_MASK                                                                        0x000007FFL
#define CB_COLOR2_PITCH__FMASK_TILE_MAX_MASK                                                                  0x7FF00000L
//CB_COLOR2_SLICE
#define CB_COLOR2_SLICE__TILE_MAX__SHIFT                                                                      0x0
#define CB_COLOR2_SLICE__TILE_MAX_MASK                                                                        0x003FFFFFL
//CB_COLOR2_VIEW
#define CB_COLOR2_VIEW__SLICE_START__SHIFT                                                                    0x0
#define CB_COLOR2_VIEW__SLICE_MAX__SHIFT                                                                      0xd
#define CB_COLOR2_VIEW__MIP_LEVEL__SHIFT                                                                      0x1a
#define CB_COLOR2_VIEW__SLICE_START_MASK                                                                      0x00001FFFL
#define CB_COLOR2_VIEW__SLICE_MAX_MASK                                                                        0x03FFE000L
#define CB_COLOR2_VIEW__MIP_LEVEL_MASK                                                                        0x3C000000L
//CB_COLOR2_INFO
#define CB_COLOR2_INFO__ENDIAN__SHIFT                                                                         0x0
#define CB_COLOR2_INFO__FORMAT__SHIFT                                                                         0x2
#define CB_COLOR2_INFO__LINEAR_GENERAL__SHIFT                                                                 0x7
#define CB_COLOR2_INFO__NUMBER_TYPE__SHIFT                                                                    0x8
#define CB_COLOR2_INFO__COMP_SWAP__SHIFT                                                                      0xb
#define CB_COLOR2_INFO__FAST_CLEAR__SHIFT                                                                     0xd
#define CB_COLOR2_INFO__COMPRESSION__SHIFT                                                                    0xe
#define CB_COLOR2_INFO__BLEND_CLAMP__SHIFT                                                                    0xf
#define CB_COLOR2_INFO__BLEND_BYPASS__SHIFT                                                                   0x10
#define CB_COLOR2_INFO__SIMPLE_FLOAT__SHIFT                                                                   0x11
#define CB_COLOR2_INFO__ROUND_MODE__SHIFT                                                                     0x12
#define CB_COLOR2_INFO__CMASK_IS_LINEAR__SHIFT                                                                0x13
#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST__SHIFT                                                          0x14
#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT                                                        0x17
#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE__SHIFT                                                      0x1a
#define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT                                                      0x1b
#define CB_COLOR2_INFO__DCC_ENABLE__SHIFT                                                                     0x1c
#define CB_COLOR2_INFO__CMASK_ADDR_TYPE__SHIFT                                                                0x1d
#define CB_COLOR2_INFO__NBC_TILING__SHIFT                                                                     0x1f
#define CB_COLOR2_INFO__ENDIAN_MASK                                                                           0x00000003L
#define CB_COLOR2_INFO__FORMAT_MASK                                                                           0x0000007CL
#define CB_COLOR2_INFO__LINEAR_GENERAL_MASK                                                                   0x00000080L
#define CB_COLOR2_INFO__NUMBER_TYPE_MASK                                                                      0x00000700L
#define CB_COLOR2_INFO__COMP_SWAP_MASK                                                                        0x00001800L
#define CB_COLOR2_INFO__FAST_CLEAR_MASK                                                                       0x00002000L
#define CB_COLOR2_INFO__COMPRESSION_MASK                                                                      0x00004000L
#define CB_COLOR2_INFO__BLEND_CLAMP_MASK                                                                      0x00008000L
#define CB_COLOR2_INFO__BLEND_BYPASS_MASK                                                                     0x00010000L
#define CB_COLOR2_INFO__SIMPLE_FLOAT_MASK                                                                     0x00020000L
#define CB_COLOR2_INFO__ROUND_MODE_MASK                                                                       0x00040000L
#define CB_COLOR2_INFO__CMASK_IS_LINEAR_MASK                                                                  0x00080000L
#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST_MASK                                                            0x00700000L
#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL_MASK                                                          0x03800000L
#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE_MASK                                                        0x04000000L
#define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK                                                        0x08000000L
#define CB_COLOR2_INFO__DCC_ENABLE_MASK                                                                       0x10000000L
#define CB_COLOR2_INFO__CMASK_ADDR_TYPE_MASK                                                                  0x60000000L
#define CB_COLOR2_INFO__NBC_TILING_MASK                                                                       0x80000000L
//CB_COLOR2_ATTRIB
#define CB_COLOR2_ATTRIB__TILE_MODE_INDEX__SHIFT                                                              0x0
#define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT                                                        0x5
#define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT__SHIFT                                                            0xa
#define CB_COLOR2_ATTRIB__NUM_SAMPLES__SHIFT                                                                  0xc
#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS__SHIFT                                                                0xf
#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1__SHIFT                                                            0x11
#define CB_COLOR2_ATTRIB__DISABLE_FMASK_NOFETCH_OPT__SHIFT                                                    0x12
#define CB_COLOR2_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT                                                0x13
#define CB_COLOR2_ATTRIB__TILE_MODE_INDEX_MASK                                                                0x0000001FL
#define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX_MASK                                                          0x000003E0L
#define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT_MASK                                                              0x00000C00L
#define CB_COLOR2_ATTRIB__NUM_SAMPLES_MASK                                                                    0x00007000L
#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS_MASK                                                                  0x00018000L
#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1_MASK                                                              0x00020000L
#define CB_COLOR2_ATTRIB__DISABLE_FMASK_NOFETCH_OPT_MASK                                                      0x00040000L
#define CB_COLOR2_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK                                                  0x00080000L
//CB_COLOR2_DCC_CONTROL
#define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT                                              0x0
#define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT                                                        0x1
#define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT                                             0x2
#define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x4
#define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x5
#define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM__SHIFT                                                         0x7
#define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT                                                  0x9
#define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT                                                     0xa
#define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT                                                   0xe
#define CB_COLOR2_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT                                             0x12
#define CB_COLOR2_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT                                        0x13
#define CB_COLOR2_DCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT                                                 0x14
#define CB_COLOR2_DCC_CONTROL__SKIP_LOW_COMP_RATIO__SHIFT                                                     0x15
#define CB_COLOR2_DCC_CONTROL__DCC_COMPRESS_DISABLE__SHIFT                                                    0x16
#define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK                                                0x00000001L
#define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK                                                          0x00000002L
#define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK                                               0x0000000CL
#define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000010L
#define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000060L
#define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM_MASK                                                           0x00000180L
#define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK                                                    0x00000200L
#define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK                                                       0x00003C00L
#define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK                                                     0x0003C000L
#define CB_COLOR2_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK                                               0x00040000L
#define CB_COLOR2_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK                                          0x00080000L
#define CB_COLOR2_DCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK                                                   0x00100000L
#define CB_COLOR2_DCC_CONTROL__SKIP_LOW_COMP_RATIO_MASK                                                       0x00200000L
#define CB_COLOR2_DCC_CONTROL__DCC_COMPRESS_DISABLE_MASK                                                      0x00400000L
//CB_COLOR2_CMASK
#define CB_COLOR2_CMASK__BASE_256B__SHIFT                                                                     0x0
#define CB_COLOR2_CMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
//CB_COLOR2_CMASK_SLICE
#define CB_COLOR2_CMASK_SLICE__TILE_MAX__SHIFT                                                                0x0
#define CB_COLOR2_CMASK_SLICE__TILE_MAX_MASK                                                                  0x00003FFFL
//CB_COLOR2_FMASK
#define CB_COLOR2_FMASK__BASE_256B__SHIFT                                                                     0x0
#define CB_COLOR2_FMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
//CB_COLOR2_FMASK_SLICE
#define CB_COLOR2_FMASK_SLICE__TILE_MAX__SHIFT                                                                0x0
#define CB_COLOR2_FMASK_SLICE__TILE_MAX_MASK                                                                  0x003FFFFFL
//CB_COLOR2_CLEAR_WORD0
#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0__SHIFT                                                             0x0
#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0_MASK                                                               0xFFFFFFFFL
//CB_COLOR2_CLEAR_WORD1
#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1__SHIFT                                                             0x0
#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1_MASK                                                               0xFFFFFFFFL
//CB_COLOR2_DCC_BASE
#define CB_COLOR2_DCC_BASE__BASE_256B__SHIFT                                                                  0x0
#define CB_COLOR2_DCC_BASE__BASE_256B_MASK                                                                    0xFFFFFFFFL
//CB_COLOR3_BASE
#define CB_COLOR3_BASE__BASE_256B__SHIFT                                                                      0x0
#define CB_COLOR3_BASE__BASE_256B_MASK                                                                        0xFFFFFFFFL
//CB_COLOR3_PITCH
#define CB_COLOR3_PITCH__TILE_MAX__SHIFT                                                                      0x0
#define CB_COLOR3_PITCH__FMASK_TILE_MAX__SHIFT                                                                0x14
#define CB_COLOR3_PITCH__TILE_MAX_MASK                                                                        0x000007FFL
#define CB_COLOR3_PITCH__FMASK_TILE_MAX_MASK                                                                  0x7FF00000L
//CB_COLOR3_SLICE
#define CB_COLOR3_SLICE__TILE_MAX__SHIFT                                                                      0x0
#define CB_COLOR3_SLICE__TILE_MAX_MASK                                                                        0x003FFFFFL
//CB_COLOR3_VIEW
#define CB_COLOR3_VIEW__SLICE_START__SHIFT                                                                    0x0
#define CB_COLOR3_VIEW__SLICE_MAX__SHIFT                                                                      0xd
#define CB_COLOR3_VIEW__MIP_LEVEL__SHIFT                                                                      0x1a
#define CB_COLOR3_VIEW__SLICE_START_MASK                                                                      0x00001FFFL
#define CB_COLOR3_VIEW__SLICE_MAX_MASK                                                                        0x03FFE000L
#define CB_COLOR3_VIEW__MIP_LEVEL_MASK                                                                        0x3C000000L
//CB_COLOR3_INFO
#define CB_COLOR3_INFO__ENDIAN__SHIFT                                                                         0x0
#define CB_COLOR3_INFO__FORMAT__SHIFT                                                                         0x2
#define CB_COLOR3_INFO__LINEAR_GENERAL__SHIFT                                                                 0x7
#define CB_COLOR3_INFO__NUMBER_TYPE__SHIFT                                                                    0x8
#define CB_COLOR3_INFO__COMP_SWAP__SHIFT                                                                      0xb
#define CB_COLOR3_INFO__FAST_CLEAR__SHIFT                                                                     0xd
#define CB_COLOR3_INFO__COMPRESSION__SHIFT                                                                    0xe
#define CB_COLOR3_INFO__BLEND_CLAMP__SHIFT                                                                    0xf
#define CB_COLOR3_INFO__BLEND_BYPASS__SHIFT                                                                   0x10
#define CB_COLOR3_INFO__SIMPLE_FLOAT__SHIFT                                                                   0x11
#define CB_COLOR3_INFO__ROUND_MODE__SHIFT                                                                     0x12
#define CB_COLOR3_INFO__CMASK_IS_LINEAR__SHIFT                                                                0x13
#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST__SHIFT                                                          0x14
#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT                                                        0x17
#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE__SHIFT                                                      0x1a
#define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT                                                      0x1b
#define CB_COLOR3_INFO__DCC_ENABLE__SHIFT                                                                     0x1c
#define CB_COLOR3_INFO__CMASK_ADDR_TYPE__SHIFT                                                                0x1d
#define CB_COLOR3_INFO__NBC_TILING__SHIFT                                                                     0x1f
#define CB_COLOR3_INFO__ENDIAN_MASK                                                                           0x00000003L
#define CB_COLOR3_INFO__FORMAT_MASK                                                                           0x0000007CL
#define CB_COLOR3_INFO__LINEAR_GENERAL_MASK                                                                   0x00000080L
#define CB_COLOR3_INFO__NUMBER_TYPE_MASK                                                                      0x00000700L
#define CB_COLOR3_INFO__COMP_SWAP_MASK                                                                        0x00001800L
#define CB_COLOR3_INFO__FAST_CLEAR_MASK                                                                       0x00002000L
#define CB_COLOR3_INFO__COMPRESSION_MASK                                                                      0x00004000L
#define CB_COLOR3_INFO__BLEND_CLAMP_MASK                                                                      0x00008000L
#define CB_COLOR3_INFO__BLEND_BYPASS_MASK                                                                     0x00010000L
#define CB_COLOR3_INFO__SIMPLE_FLOAT_MASK                                                                     0x00020000L
#define CB_COLOR3_INFO__ROUND_MODE_MASK                                                                       0x00040000L
#define CB_COLOR3_INFO__CMASK_IS_LINEAR_MASK                                                                  0x00080000L
#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST_MASK                                                            0x00700000L
#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL_MASK                                                          0x03800000L
#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE_MASK                                                        0x04000000L
#define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK                                                        0x08000000L
#define CB_COLOR3_INFO__DCC_ENABLE_MASK                                                                       0x10000000L
#define CB_COLOR3_INFO__CMASK_ADDR_TYPE_MASK                                                                  0x60000000L
#define CB_COLOR3_INFO__NBC_TILING_MASK                                                                       0x80000000L
//CB_COLOR3_ATTRIB
#define CB_COLOR3_ATTRIB__TILE_MODE_INDEX__SHIFT                                                              0x0
#define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT                                                        0x5
#define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT__SHIFT                                                            0xa
#define CB_COLOR3_ATTRIB__NUM_SAMPLES__SHIFT                                                                  0xc
#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS__SHIFT                                                                0xf
#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1__SHIFT                                                            0x11
#define CB_COLOR3_ATTRIB__DISABLE_FMASK_NOFETCH_OPT__SHIFT                                                    0x12
#define CB_COLOR3_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT                                                0x13
#define CB_COLOR3_ATTRIB__TILE_MODE_INDEX_MASK                                                                0x0000001FL
#define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX_MASK                                                          0x000003E0L
#define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT_MASK                                                              0x00000C00L
#define CB_COLOR3_ATTRIB__NUM_SAMPLES_MASK                                                                    0x00007000L
#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS_MASK                                                                  0x00018000L
#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1_MASK                                                              0x00020000L
#define CB_COLOR3_ATTRIB__DISABLE_FMASK_NOFETCH_OPT_MASK                                                      0x00040000L
#define CB_COLOR3_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK                                                  0x00080000L
//CB_COLOR3_DCC_CONTROL
#define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT                                              0x0
#define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT                                                        0x1
#define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT                                             0x2
#define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x4
#define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x5
#define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM__SHIFT                                                         0x7
#define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT                                                  0x9
#define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT                                                     0xa
#define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT                                                   0xe
#define CB_COLOR3_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT                                             0x12
#define CB_COLOR3_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT                                        0x13
#define CB_COLOR3_DCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT                                                 0x14
#define CB_COLOR3_DCC_CONTROL__SKIP_LOW_COMP_RATIO__SHIFT                                                     0x15
#define CB_COLOR3_DCC_CONTROL__DCC_COMPRESS_DISABLE__SHIFT                                                    0x16
#define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK                                                0x00000001L
#define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK                                                          0x00000002L
#define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK                                               0x0000000CL
#define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000010L
#define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000060L
#define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM_MASK                                                           0x00000180L
#define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK                                                    0x00000200L
#define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK                                                       0x00003C00L
#define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK                                                     0x0003C000L
#define CB_COLOR3_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK                                               0x00040000L
#define CB_COLOR3_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK                                          0x00080000L
#define CB_COLOR3_DCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK                                                   0x00100000L
#define CB_COLOR3_DCC_CONTROL__SKIP_LOW_COMP_RATIO_MASK                                                       0x00200000L
#define CB_COLOR3_DCC_CONTROL__DCC_COMPRESS_DISABLE_MASK                                                      0x00400000L
//CB_COLOR3_CMASK
#define CB_COLOR3_CMASK__BASE_256B__SHIFT                                                                     0x0
#define CB_COLOR3_CMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
//CB_COLOR3_CMASK_SLICE
#define CB_COLOR3_CMASK_SLICE__TILE_MAX__SHIFT                                                                0x0
#define CB_COLOR3_CMASK_SLICE__TILE_MAX_MASK                                                                  0x00003FFFL
//CB_COLOR3_FMASK
#define CB_COLOR3_FMASK__BASE_256B__SHIFT                                                                     0x0
#define CB_COLOR3_FMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
//CB_COLOR3_FMASK_SLICE
#define CB_COLOR3_FMASK_SLICE__TILE_MAX__SHIFT                                                                0x0
#define CB_COLOR3_FMASK_SLICE__TILE_MAX_MASK                                                                  0x003FFFFFL
//CB_COLOR3_CLEAR_WORD0
#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0__SHIFT                                                             0x0
#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0_MASK                                                               0xFFFFFFFFL
//CB_COLOR3_CLEAR_WORD1
#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1__SHIFT                                                             0x0
#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1_MASK                                                               0xFFFFFFFFL
//CB_COLOR3_DCC_BASE
#define CB_COLOR3_DCC_BASE__BASE_256B__SHIFT                                                                  0x0
#define CB_COLOR3_DCC_BASE__BASE_256B_MASK                                                                    0xFFFFFFFFL
//CB_COLOR4_BASE
#define CB_COLOR4_BASE__BASE_256B__SHIFT                                                                      0x0
#define CB_COLOR4_BASE__BASE_256B_MASK                                                                        0xFFFFFFFFL
//CB_COLOR4_PITCH
#define CB_COLOR4_PITCH__TILE_MAX__SHIFT                                                                      0x0
#define CB_COLOR4_PITCH__FMASK_TILE_MAX__SHIFT                                                                0x14
#define CB_COLOR4_PITCH__TILE_MAX_MASK                                                                        0x000007FFL
#define CB_COLOR4_PITCH__FMASK_TILE_MAX_MASK                                                                  0x7FF00000L
//CB_COLOR4_SLICE
#define CB_COLOR4_SLICE__TILE_MAX__SHIFT                                                                      0x0
#define CB_COLOR4_SLICE__TILE_MAX_MASK                                                                        0x003FFFFFL
//CB_COLOR4_VIEW
#define CB_COLOR4_VIEW__SLICE_START__SHIFT                                                                    0x0
#define CB_COLOR4_VIEW__SLICE_MAX__SHIFT                                                                      0xd
#define CB_COLOR4_VIEW__MIP_LEVEL__SHIFT                                                                      0x1a
#define CB_COLOR4_VIEW__SLICE_START_MASK                                                                      0x00001FFFL
#define CB_COLOR4_VIEW__SLICE_MAX_MASK                                                                        0x03FFE000L
#define CB_COLOR4_VIEW__MIP_LEVEL_MASK                                                                        0x3C000000L
//CB_COLOR4_INFO
#define CB_COLOR4_INFO__ENDIAN__SHIFT                                                                         0x0
#define CB_COLOR4_INFO__FORMAT__SHIFT                                                                         0x2
#define CB_COLOR4_INFO__LINEAR_GENERAL__SHIFT                                                                 0x7
#define CB_COLOR4_INFO__NUMBER_TYPE__SHIFT                                                                    0x8
#define CB_COLOR4_INFO__COMP_SWAP__SHIFT                                                                      0xb
#define CB_COLOR4_INFO__FAST_CLEAR__SHIFT                                                                     0xd
#define CB_COLOR4_INFO__COMPRESSION__SHIFT                                                                    0xe
#define CB_COLOR4_INFO__BLEND_CLAMP__SHIFT                                                                    0xf
#define CB_COLOR4_INFO__BLEND_BYPASS__SHIFT                                                                   0x10
#define CB_COLOR4_INFO__SIMPLE_FLOAT__SHIFT                                                                   0x11
#define CB_COLOR4_INFO__ROUND_MODE__SHIFT                                                                     0x12
#define CB_COLOR4_INFO__CMASK_IS_LINEAR__SHIFT                                                                0x13
#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST__SHIFT                                                          0x14
#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT                                                        0x17
#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE__SHIFT                                                      0x1a
#define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT                                                      0x1b
#define CB_COLOR4_INFO__DCC_ENABLE__SHIFT                                                                     0x1c
#define CB_COLOR4_INFO__CMASK_ADDR_TYPE__SHIFT                                                                0x1d
#define CB_COLOR4_INFO__NBC_TILING__SHIFT                                                                     0x1f
#define CB_COLOR4_INFO__ENDIAN_MASK                                                                           0x00000003L
#define CB_COLOR4_INFO__FORMAT_MASK                                                                           0x0000007CL
#define CB_COLOR4_INFO__LINEAR_GENERAL_MASK                                                                   0x00000080L
#define CB_COLOR4_INFO__NUMBER_TYPE_MASK                                                                      0x00000700L
#define CB_COLOR4_INFO__COMP_SWAP_MASK                                                                        0x00001800L
#define CB_COLOR4_INFO__FAST_CLEAR_MASK                                                                       0x00002000L
#define CB_COLOR4_INFO__COMPRESSION_MASK                                                                      0x00004000L
#define CB_COLOR4_INFO__BLEND_CLAMP_MASK                                                                      0x00008000L
#define CB_COLOR4_INFO__BLEND_BYPASS_MASK                                                                     0x00010000L
#define CB_COLOR4_INFO__SIMPLE_FLOAT_MASK                                                                     0x00020000L
#define CB_COLOR4_INFO__ROUND_MODE_MASK                                                                       0x00040000L
#define CB_COLOR4_INFO__CMASK_IS_LINEAR_MASK                                                                  0x00080000L
#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST_MASK                                                            0x00700000L
#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL_MASK                                                          0x03800000L
#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE_MASK                                                        0x04000000L
#define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK                                                        0x08000000L
#define CB_COLOR4_INFO__DCC_ENABLE_MASK                                                                       0x10000000L
#define CB_COLOR4_INFO__CMASK_ADDR_TYPE_MASK                                                                  0x60000000L
#define CB_COLOR4_INFO__NBC_TILING_MASK                                                                       0x80000000L
//CB_COLOR4_ATTRIB
#define CB_COLOR4_ATTRIB__TILE_MODE_INDEX__SHIFT                                                              0x0
#define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT                                                        0x5
#define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT__SHIFT                                                            0xa
#define CB_COLOR4_ATTRIB__NUM_SAMPLES__SHIFT                                                                  0xc
#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS__SHIFT                                                                0xf
#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1__SHIFT                                                            0x11
#define CB_COLOR4_ATTRIB__DISABLE_FMASK_NOFETCH_OPT__SHIFT                                                    0x12
#define CB_COLOR4_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT                                                0x13
#define CB_COLOR4_ATTRIB__TILE_MODE_INDEX_MASK                                                                0x0000001FL
#define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX_MASK                                                          0x000003E0L
#define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT_MASK                                                              0x00000C00L
#define CB_COLOR4_ATTRIB__NUM_SAMPLES_MASK                                                                    0x00007000L
#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS_MASK                                                                  0x00018000L
#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1_MASK                                                              0x00020000L
#define CB_COLOR4_ATTRIB__DISABLE_FMASK_NOFETCH_OPT_MASK                                                      0x00040000L
#define CB_COLOR4_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK                                                  0x00080000L
//CB_COLOR4_DCC_CONTROL
#define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT                                              0x0
#define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT                                                        0x1
#define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT                                             0x2
#define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x4
#define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x5
#define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM__SHIFT                                                         0x7
#define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT                                                  0x9
#define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT                                                     0xa
#define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT                                                   0xe
#define CB_COLOR4_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT                                             0x12
#define CB_COLOR4_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT                                        0x13
#define CB_COLOR4_DCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT                                                 0x14
#define CB_COLOR4_DCC_CONTROL__SKIP_LOW_COMP_RATIO__SHIFT                                                     0x15
#define CB_COLOR4_DCC_CONTROL__DCC_COMPRESS_DISABLE__SHIFT                                                    0x16
#define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK                                                0x00000001L
#define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK                                                          0x00000002L
#define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK                                               0x0000000CL
#define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000010L
#define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000060L
#define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM_MASK                                                           0x00000180L
#define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK                                                    0x00000200L
#define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK                                                       0x00003C00L
#define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK                                                     0x0003C000L
#define CB_COLOR4_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK                                               0x00040000L
#define CB_COLOR4_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK                                          0x00080000L
#define CB_COLOR4_DCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK                                                   0x00100000L
#define CB_COLOR4_DCC_CONTROL__SKIP_LOW_COMP_RATIO_MASK                                                       0x00200000L
#define CB_COLOR4_DCC_CONTROL__DCC_COMPRESS_DISABLE_MASK                                                      0x00400000L
//CB_COLOR4_CMASK
#define CB_COLOR4_CMASK__BASE_256B__SHIFT                                                                     0x0
#define CB_COLOR4_CMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
//CB_COLOR4_CMASK_SLICE
#define CB_COLOR4_CMASK_SLICE__TILE_MAX__SHIFT                                                                0x0
#define CB_COLOR4_CMASK_SLICE__TILE_MAX_MASK                                                                  0x00003FFFL
//CB_COLOR4_FMASK
#define CB_COLOR4_FMASK__BASE_256B__SHIFT                                                                     0x0
#define CB_COLOR4_FMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
//CB_COLOR4_FMASK_SLICE
#define CB_COLOR4_FMASK_SLICE__TILE_MAX__SHIFT                                                                0x0
#define CB_COLOR4_FMASK_SLICE__TILE_MAX_MASK                                                                  0x003FFFFFL
//CB_COLOR4_CLEAR_WORD0
#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0__SHIFT                                                             0x0
#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0_MASK                                                               0xFFFFFFFFL
//CB_COLOR4_CLEAR_WORD1
#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1__SHIFT                                                             0x0
#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1_MASK                                                               0xFFFFFFFFL
//CB_COLOR4_DCC_BASE
#define CB_COLOR4_DCC_BASE__BASE_256B__SHIFT                                                                  0x0
#define CB_COLOR4_DCC_BASE__BASE_256B_MASK                                                                    0xFFFFFFFFL
//CB_COLOR5_BASE
#define CB_COLOR5_BASE__BASE_256B__SHIFT                                                                      0x0
#define CB_COLOR5_BASE__BASE_256B_MASK                                                                        0xFFFFFFFFL
//CB_COLOR5_PITCH
#define CB_COLOR5_PITCH__TILE_MAX__SHIFT                                                                      0x0
#define CB_COLOR5_PITCH__FMASK_TILE_MAX__SHIFT                                                                0x14
#define CB_COLOR5_PITCH__TILE_MAX_MASK                                                                        0x000007FFL
#define CB_COLOR5_PITCH__FMASK_TILE_MAX_MASK                                                                  0x7FF00000L
//CB_COLOR5_SLICE
#define CB_COLOR5_SLICE__TILE_MAX__SHIFT                                                                      0x0
#define CB_COLOR5_SLICE__TILE_MAX_MASK                                                                        0x003FFFFFL
//CB_COLOR5_VIEW
#define CB_COLOR5_VIEW__SLICE_START__SHIFT                                                                    0x0
#define CB_COLOR5_VIEW__SLICE_MAX__SHIFT                                                                      0xd
#define CB_COLOR5_VIEW__MIP_LEVEL__SHIFT                                                                      0x1a
#define CB_COLOR5_VIEW__SLICE_START_MASK                                                                      0x00001FFFL
#define CB_COLOR5_VIEW__SLICE_MAX_MASK                                                                        0x03FFE000L
#define CB_COLOR5_VIEW__MIP_LEVEL_MASK                                                                        0x3C000000L
//CB_COLOR5_INFO
#define CB_COLOR5_INFO__ENDIAN__SHIFT                                                                         0x0
#define CB_COLOR5_INFO__FORMAT__SHIFT                                                                         0x2
#define CB_COLOR5_INFO__LINEAR_GENERAL__SHIFT                                                                 0x7
#define CB_COLOR5_INFO__NUMBER_TYPE__SHIFT                                                                    0x8
#define CB_COLOR5_INFO__COMP_SWAP__SHIFT                                                                      0xb
#define CB_COLOR5_INFO__FAST_CLEAR__SHIFT                                                                     0xd
#define CB_COLOR5_INFO__COMPRESSION__SHIFT                                                                    0xe
#define CB_COLOR5_INFO__BLEND_CLAMP__SHIFT                                                                    0xf
#define CB_COLOR5_INFO__BLEND_BYPASS__SHIFT                                                                   0x10
#define CB_COLOR5_INFO__SIMPLE_FLOAT__SHIFT                                                                   0x11
#define CB_COLOR5_INFO__ROUND_MODE__SHIFT                                                                     0x12
#define CB_COLOR5_INFO__CMASK_IS_LINEAR__SHIFT                                                                0x13
#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST__SHIFT                                                          0x14
#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT                                                        0x17
#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE__SHIFT                                                      0x1a
#define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT                                                      0x1b
#define CB_COLOR5_INFO__DCC_ENABLE__SHIFT                                                                     0x1c
#define CB_COLOR5_INFO__CMASK_ADDR_TYPE__SHIFT                                                                0x1d
#define CB_COLOR5_INFO__NBC_TILING__SHIFT                                                                     0x1f
#define CB_COLOR5_INFO__ENDIAN_MASK                                                                           0x00000003L
#define CB_COLOR5_INFO__FORMAT_MASK                                                                           0x0000007CL
#define CB_COLOR5_INFO__LINEAR_GENERAL_MASK                                                                   0x00000080L
#define CB_COLOR5_INFO__NUMBER_TYPE_MASK                                                                      0x00000700L
#define CB_COLOR5_INFO__COMP_SWAP_MASK                                                                        0x00001800L
#define CB_COLOR5_INFO__FAST_CLEAR_MASK                                                                       0x00002000L
#define CB_COLOR5_INFO__COMPRESSION_MASK                                                                      0x00004000L
#define CB_COLOR5_INFO__BLEND_CLAMP_MASK                                                                      0x00008000L
#define CB_COLOR5_INFO__BLEND_BYPASS_MASK                                                                     0x00010000L
#define CB_COLOR5_INFO__SIMPLE_FLOAT_MASK                                                                     0x00020000L
#define CB_COLOR5_INFO__ROUND_MODE_MASK                                                                       0x00040000L
#define CB_COLOR5_INFO__CMASK_IS_LINEAR_MASK                                                                  0x00080000L
#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST_MASK                                                            0x00700000L
#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL_MASK                                                          0x03800000L
#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE_MASK                                                        0x04000000L
#define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK                                                        0x08000000L
#define CB_COLOR5_INFO__DCC_ENABLE_MASK                                                                       0x10000000L
#define CB_COLOR5_INFO__CMASK_ADDR_TYPE_MASK                                                                  0x60000000L
#define CB_COLOR5_INFO__NBC_TILING_MASK                                                                       0x80000000L
//CB_COLOR5_ATTRIB
#define CB_COLOR5_ATTRIB__TILE_MODE_INDEX__SHIFT                                                              0x0
#define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT                                                        0x5
#define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT__SHIFT                                                            0xa
#define CB_COLOR5_ATTRIB__NUM_SAMPLES__SHIFT                                                                  0xc
#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS__SHIFT                                                                0xf
#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1__SHIFT                                                            0x11
#define CB_COLOR5_ATTRIB__DISABLE_FMASK_NOFETCH_OPT__SHIFT                                                    0x12
#define CB_COLOR5_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT                                                0x13
#define CB_COLOR5_ATTRIB__TILE_MODE_INDEX_MASK                                                                0x0000001FL
#define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX_MASK                                                          0x000003E0L
#define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT_MASK                                                              0x00000C00L
#define CB_COLOR5_ATTRIB__NUM_SAMPLES_MASK                                                                    0x00007000L
#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS_MASK                                                                  0x00018000L
#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1_MASK                                                              0x00020000L
#define CB_COLOR5_ATTRIB__DISABLE_FMASK_NOFETCH_OPT_MASK                                                      0x00040000L
#define CB_COLOR5_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK                                                  0x00080000L
//CB_COLOR5_DCC_CONTROL
#define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT                                              0x0
#define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT                                                        0x1
#define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT                                             0x2
#define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x4
#define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x5
#define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM__SHIFT                                                         0x7
#define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT                                                  0x9
#define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT                                                     0xa
#define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT                                                   0xe
#define CB_COLOR5_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT                                             0x12
#define CB_COLOR5_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT                                        0x13
#define CB_COLOR5_DCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT                                                 0x14
#define CB_COLOR5_DCC_CONTROL__SKIP_LOW_COMP_RATIO__SHIFT                                                     0x15
#define CB_COLOR5_DCC_CONTROL__DCC_COMPRESS_DISABLE__SHIFT                                                    0x16
#define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK                                                0x00000001L
#define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK                                                          0x00000002L
#define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK                                               0x0000000CL
#define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000010L
#define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000060L
#define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM_MASK                                                           0x00000180L
#define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK                                                    0x00000200L
#define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK                                                       0x00003C00L
#define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK                                                     0x0003C000L
#define CB_COLOR5_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK                                               0x00040000L
#define CB_COLOR5_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK                                          0x00080000L
#define CB_COLOR5_DCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK                                                   0x00100000L
#define CB_COLOR5_DCC_CONTROL__SKIP_LOW_COMP_RATIO_MASK                                                       0x00200000L
#define CB_COLOR5_DCC_CONTROL__DCC_COMPRESS_DISABLE_MASK                                                      0x00400000L
//CB_COLOR5_CMASK
#define CB_COLOR5_CMASK__BASE_256B__SHIFT                                                                     0x0
#define CB_COLOR5_CMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
//CB_COLOR5_CMASK_SLICE
#define CB_COLOR5_CMASK_SLICE__TILE_MAX__SHIFT                                                                0x0
#define CB_COLOR5_CMASK_SLICE__TILE_MAX_MASK                                                                  0x00003FFFL
//CB_COLOR5_FMASK
#define CB_COLOR5_FMASK__BASE_256B__SHIFT                                                                     0x0
#define CB_COLOR5_FMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
//CB_COLOR5_FMASK_SLICE
#define CB_COLOR5_FMASK_SLICE__TILE_MAX__SHIFT                                                                0x0
#define CB_COLOR5_FMASK_SLICE__TILE_MAX_MASK                                                                  0x003FFFFFL
//CB_COLOR5_CLEAR_WORD0
#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0__SHIFT                                                             0x0
#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0_MASK                                                               0xFFFFFFFFL
//CB_COLOR5_CLEAR_WORD1
#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1__SHIFT                                                             0x0
#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1_MASK                                                               0xFFFFFFFFL
//CB_COLOR5_DCC_BASE
#define CB_COLOR5_DCC_BASE__BASE_256B__SHIFT                                                                  0x0
#define CB_COLOR5_DCC_BASE__BASE_256B_MASK                                                                    0xFFFFFFFFL
//CB_COLOR6_BASE
#define CB_COLOR6_BASE__BASE_256B__SHIFT                                                                      0x0
#define CB_COLOR6_BASE__BASE_256B_MASK                                                                        0xFFFFFFFFL
//CB_COLOR6_PITCH
#define CB_COLOR6_PITCH__TILE_MAX__SHIFT                                                                      0x0
#define CB_COLOR6_PITCH__FMASK_TILE_MAX__SHIFT                                                                0x14
#define CB_COLOR6_PITCH__TILE_MAX_MASK                                                                        0x000007FFL
#define CB_COLOR6_PITCH__FMASK_TILE_MAX_MASK                                                                  0x7FF00000L
//CB_COLOR6_SLICE
#define CB_COLOR6_SLICE__TILE_MAX__SHIFT                                                                      0x0
#define CB_COLOR6_SLICE__TILE_MAX_MASK                                                                        0x003FFFFFL
//CB_COLOR6_VIEW
#define CB_COLOR6_VIEW__SLICE_START__SHIFT                                                                    0x0
#define CB_COLOR6_VIEW__SLICE_MAX__SHIFT                                                                      0xd
#define CB_COLOR6_VIEW__MIP_LEVEL__SHIFT                                                                      0x1a
#define CB_COLOR6_VIEW__SLICE_START_MASK                                                                      0x00001FFFL
#define CB_COLOR6_VIEW__SLICE_MAX_MASK                                                                        0x03FFE000L
#define CB_COLOR6_VIEW__MIP_LEVEL_MASK                                                                        0x3C000000L
//CB_COLOR6_INFO
#define CB_COLOR6_INFO__ENDIAN__SHIFT                                                                         0x0
#define CB_COLOR6_INFO__FORMAT__SHIFT                                                                         0x2
#define CB_COLOR6_INFO__LINEAR_GENERAL__SHIFT                                                                 0x7
#define CB_COLOR6_INFO__NUMBER_TYPE__SHIFT                                                                    0x8
#define CB_COLOR6_INFO__COMP_SWAP__SHIFT                                                                      0xb
#define CB_COLOR6_INFO__FAST_CLEAR__SHIFT                                                                     0xd
#define CB_COLOR6_INFO__COMPRESSION__SHIFT                                                                    0xe
#define CB_COLOR6_INFO__BLEND_CLAMP__SHIFT                                                                    0xf
#define CB_COLOR6_INFO__BLEND_BYPASS__SHIFT                                                                   0x10
#define CB_COLOR6_INFO__SIMPLE_FLOAT__SHIFT                                                                   0x11
#define CB_COLOR6_INFO__ROUND_MODE__SHIFT                                                                     0x12
#define CB_COLOR6_INFO__CMASK_IS_LINEAR__SHIFT                                                                0x13
#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST__SHIFT                                                          0x14
#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT                                                        0x17
#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE__SHIFT                                                      0x1a
#define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT                                                      0x1b
#define CB_COLOR6_INFO__DCC_ENABLE__SHIFT                                                                     0x1c
#define CB_COLOR6_INFO__CMASK_ADDR_TYPE__SHIFT                                                                0x1d
#define CB_COLOR6_INFO__NBC_TILING__SHIFT                                                                     0x1f
#define CB_COLOR6_INFO__ENDIAN_MASK                                                                           0x00000003L
#define CB_COLOR6_INFO__FORMAT_MASK                                                                           0x0000007CL
#define CB_COLOR6_INFO__LINEAR_GENERAL_MASK                                                                   0x00000080L
#define CB_COLOR6_INFO__NUMBER_TYPE_MASK                                                                      0x00000700L
#define CB_COLOR6_INFO__COMP_SWAP_MASK                                                                        0x00001800L
#define CB_COLOR6_INFO__FAST_CLEAR_MASK                                                                       0x00002000L
#define CB_COLOR6_INFO__COMPRESSION_MASK                                                                      0x00004000L
#define CB_COLOR6_INFO__BLEND_CLAMP_MASK                                                                      0x00008000L
#define CB_COLOR6_INFO__BLEND_BYPASS_MASK                                                                     0x00010000L
#define CB_COLOR6_INFO__SIMPLE_FLOAT_MASK                                                                     0x00020000L
#define CB_COLOR6_INFO__ROUND_MODE_MASK                                                                       0x00040000L
#define CB_COLOR6_INFO__CMASK_IS_LINEAR_MASK                                                                  0x00080000L
#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST_MASK                                                            0x00700000L
#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL_MASK                                                          0x03800000L
#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE_MASK                                                        0x04000000L
#define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK                                                        0x08000000L
#define CB_COLOR6_INFO__DCC_ENABLE_MASK                                                                       0x10000000L
#define CB_COLOR6_INFO__CMASK_ADDR_TYPE_MASK                                                                  0x60000000L
#define CB_COLOR6_INFO__NBC_TILING_MASK                                                                       0x80000000L
//CB_COLOR6_ATTRIB
#define CB_COLOR6_ATTRIB__TILE_MODE_INDEX__SHIFT                                                              0x0
#define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT                                                        0x5
#define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT__SHIFT                                                            0xa
#define CB_COLOR6_ATTRIB__NUM_SAMPLES__SHIFT                                                                  0xc
#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS__SHIFT                                                                0xf
#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1__SHIFT                                                            0x11
#define CB_COLOR6_ATTRIB__DISABLE_FMASK_NOFETCH_OPT__SHIFT                                                    0x12
#define CB_COLOR6_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT                                                0x13
#define CB_COLOR6_ATTRIB__TILE_MODE_INDEX_MASK                                                                0x0000001FL
#define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX_MASK                                                          0x000003E0L
#define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT_MASK                                                              0x00000C00L
#define CB_COLOR6_ATTRIB__NUM_SAMPLES_MASK                                                                    0x00007000L
#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS_MASK                                                                  0x00018000L
#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1_MASK                                                              0x00020000L
#define CB_COLOR6_ATTRIB__DISABLE_FMASK_NOFETCH_OPT_MASK                                                      0x00040000L
#define CB_COLOR6_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK                                                  0x00080000L
//CB_COLOR6_DCC_CONTROL
#define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT                                              0x0
#define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT                                                        0x1
#define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT                                             0x2
#define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x4
#define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x5
#define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM__SHIFT                                                         0x7
#define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT                                                  0x9
#define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT                                                     0xa
#define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT                                                   0xe
#define CB_COLOR6_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT                                             0x12
#define CB_COLOR6_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT                                        0x13
#define CB_COLOR6_DCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT                                                 0x14
#define CB_COLOR6_DCC_CONTROL__SKIP_LOW_COMP_RATIO__SHIFT                                                     0x15
#define CB_COLOR6_DCC_CONTROL__DCC_COMPRESS_DISABLE__SHIFT                                                    0x16
#define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK                                                0x00000001L
#define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK                                                          0x00000002L
#define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK                                               0x0000000CL
#define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000010L
#define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000060L
#define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM_MASK                                                           0x00000180L
#define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK                                                    0x00000200L
#define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK                                                       0x00003C00L
#define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK                                                     0x0003C000L
#define CB_COLOR6_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK                                               0x00040000L
#define CB_COLOR6_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK                                          0x00080000L
#define CB_COLOR6_DCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK                                                   0x00100000L
#define CB_COLOR6_DCC_CONTROL__SKIP_LOW_COMP_RATIO_MASK                                                       0x00200000L
#define CB_COLOR6_DCC_CONTROL__DCC_COMPRESS_DISABLE_MASK                                                      0x00400000L
//CB_COLOR6_CMASK
#define CB_COLOR6_CMASK__BASE_256B__SHIFT                                                                     0x0
#define CB_COLOR6_CMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
//CB_COLOR6_CMASK_SLICE
#define CB_COLOR6_CMASK_SLICE__TILE_MAX__SHIFT                                                                0x0
#define CB_COLOR6_CMASK_SLICE__TILE_MAX_MASK                                                                  0x00003FFFL
//CB_COLOR6_FMASK
#define CB_COLOR6_FMASK__BASE_256B__SHIFT                                                                     0x0
#define CB_COLOR6_FMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
//CB_COLOR6_FMASK_SLICE
#define CB_COLOR6_FMASK_SLICE__TILE_MAX__SHIFT                                                                0x0
#define CB_COLOR6_FMASK_SLICE__TILE_MAX_MASK                                                                  0x003FFFFFL
//CB_COLOR6_CLEAR_WORD0
#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0__SHIFT                                                             0x0
#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0_MASK                                                               0xFFFFFFFFL
//CB_COLOR6_CLEAR_WORD1
#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1__SHIFT                                                             0x0
#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1_MASK                                                               0xFFFFFFFFL
//CB_COLOR6_DCC_BASE
#define CB_COLOR6_DCC_BASE__BASE_256B__SHIFT                                                                  0x0
#define CB_COLOR6_DCC_BASE__BASE_256B_MASK                                                                    0xFFFFFFFFL
//CB_COLOR7_BASE
#define CB_COLOR7_BASE__BASE_256B__SHIFT                                                                      0x0
#define CB_COLOR7_BASE__BASE_256B_MASK                                                                        0xFFFFFFFFL
//CB_COLOR7_PITCH
#define CB_COLOR7_PITCH__TILE_MAX__SHIFT                                                                      0x0
#define CB_COLOR7_PITCH__FMASK_TILE_MAX__SHIFT                                                                0x14
#define CB_COLOR7_PITCH__TILE_MAX_MASK                                                                        0x000007FFL
#define CB_COLOR7_PITCH__FMASK_TILE_MAX_MASK                                                                  0x7FF00000L
//CB_COLOR7_SLICE
#define CB_COLOR7_SLICE__TILE_MAX__SHIFT                                                                      0x0
#define CB_COLOR7_SLICE__TILE_MAX_MASK                                                                        0x003FFFFFL
//CB_COLOR7_VIEW
#define CB_COLOR7_VIEW__SLICE_START__SHIFT                                                                    0x0
#define CB_COLOR7_VIEW__SLICE_MAX__SHIFT                                                                      0xd
#define CB_COLOR7_VIEW__MIP_LEVEL__SHIFT                                                                      0x1a
#define CB_COLOR7_VIEW__SLICE_START_MASK                                                                      0x00001FFFL
#define CB_COLOR7_VIEW__SLICE_MAX_MASK                                                                        0x03FFE000L
#define CB_COLOR7_VIEW__MIP_LEVEL_MASK                                                                        0x3C000000L
//CB_COLOR7_INFO
#define CB_COLOR7_INFO__ENDIAN__SHIFT                                                                         0x0
#define CB_COLOR7_INFO__FORMAT__SHIFT                                                                         0x2
#define CB_COLOR7_INFO__LINEAR_GENERAL__SHIFT                                                                 0x7
#define CB_COLOR7_INFO__NUMBER_TYPE__SHIFT                                                                    0x8
#define CB_COLOR7_INFO__COMP_SWAP__SHIFT                                                                      0xb
#define CB_COLOR7_INFO__FAST_CLEAR__SHIFT                                                                     0xd
#define CB_COLOR7_INFO__COMPRESSION__SHIFT                                                                    0xe
#define CB_COLOR7_INFO__BLEND_CLAMP__SHIFT                                                                    0xf
#define CB_COLOR7_INFO__BLEND_BYPASS__SHIFT                                                                   0x10
#define CB_COLOR7_INFO__SIMPLE_FLOAT__SHIFT                                                                   0x11
#define CB_COLOR7_INFO__ROUND_MODE__SHIFT                                                                     0x12
#define CB_COLOR7_INFO__CMASK_IS_LINEAR__SHIFT                                                                0x13
#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST__SHIFT                                                          0x14
#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT                                                        0x17
#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE__SHIFT                                                      0x1a
#define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT                                                      0x1b
#define CB_COLOR7_INFO__DCC_ENABLE__SHIFT                                                                     0x1c
#define CB_COLOR7_INFO__CMASK_ADDR_TYPE__SHIFT                                                                0x1d
#define CB_COLOR7_INFO__NBC_TILING__SHIFT                                                                     0x1f
#define CB_COLOR7_INFO__ENDIAN_MASK                                                                           0x00000003L
#define CB_COLOR7_INFO__FORMAT_MASK                                                                           0x0000007CL
#define CB_COLOR7_INFO__LINEAR_GENERAL_MASK                                                                   0x00000080L
#define CB_COLOR7_INFO__NUMBER_TYPE_MASK                                                                      0x00000700L
#define CB_COLOR7_INFO__COMP_SWAP_MASK                                                                        0x00001800L
#define CB_COLOR7_INFO__FAST_CLEAR_MASK                                                                       0x00002000L
#define CB_COLOR7_INFO__COMPRESSION_MASK                                                                      0x00004000L
#define CB_COLOR7_INFO__BLEND_CLAMP_MASK                                                                      0x00008000L
#define CB_COLOR7_INFO__BLEND_BYPASS_MASK                                                                     0x00010000L
#define CB_COLOR7_INFO__SIMPLE_FLOAT_MASK                                                                     0x00020000L
#define CB_COLOR7_INFO__ROUND_MODE_MASK                                                                       0x00040000L
#define CB_COLOR7_INFO__CMASK_IS_LINEAR_MASK                                                                  0x00080000L
#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST_MASK                                                            0x00700000L
#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL_MASK                                                          0x03800000L
#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE_MASK                                                        0x04000000L
#define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK                                                        0x08000000L
#define CB_COLOR7_INFO__DCC_ENABLE_MASK                                                                       0x10000000L
#define CB_COLOR7_INFO__CMASK_ADDR_TYPE_MASK                                                                  0x60000000L
#define CB_COLOR7_INFO__NBC_TILING_MASK                                                                       0x80000000L
//CB_COLOR7_ATTRIB
#define CB_COLOR7_ATTRIB__TILE_MODE_INDEX__SHIFT                                                              0x0
#define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT                                                        0x5
#define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT__SHIFT                                                            0xa
#define CB_COLOR7_ATTRIB__NUM_SAMPLES__SHIFT                                                                  0xc
#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS__SHIFT                                                                0xf
#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1__SHIFT                                                            0x11
#define CB_COLOR7_ATTRIB__DISABLE_FMASK_NOFETCH_OPT__SHIFT                                                    0x12
#define CB_COLOR7_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT                                                0x13
#define CB_COLOR7_ATTRIB__TILE_MODE_INDEX_MASK                                                                0x0000001FL
#define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX_MASK                                                          0x000003E0L
#define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT_MASK                                                              0x00000C00L
#define CB_COLOR7_ATTRIB__NUM_SAMPLES_MASK                                                                    0x00007000L
#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS_MASK                                                                  0x00018000L
#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1_MASK                                                              0x00020000L
#define CB_COLOR7_ATTRIB__DISABLE_FMASK_NOFETCH_OPT_MASK                                                      0x00040000L
#define CB_COLOR7_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK                                                  0x00080000L
//CB_COLOR7_DCC_CONTROL
#define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT                                              0x0
#define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT                                                        0x1
#define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT                                             0x2
#define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x4
#define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x5
#define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM__SHIFT                                                         0x7
#define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT                                                  0x9
#define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT                                                     0xa
#define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT                                                   0xe
#define CB_COLOR7_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT                                             0x12
#define CB_COLOR7_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT                                        0x13
#define CB_COLOR7_DCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT                                                 0x14
#define CB_COLOR7_DCC_CONTROL__SKIP_LOW_COMP_RATIO__SHIFT                                                     0x15
#define CB_COLOR7_DCC_CONTROL__DCC_COMPRESS_DISABLE__SHIFT                                                    0x16
#define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK                                                0x00000001L
#define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK                                                          0x00000002L
#define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK                                               0x0000000CL
#define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000010L
#define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000060L
#define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM_MASK                                                           0x00000180L
#define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK                                                    0x00000200L
#define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK                                                       0x00003C00L
#define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK                                                     0x0003C000L
#define CB_COLOR7_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK                                               0x00040000L
#define CB_COLOR7_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK                                          0x00080000L
#define CB_COLOR7_DCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK                                                   0x00100000L
#define CB_COLOR7_DCC_CONTROL__SKIP_LOW_COMP_RATIO_MASK                                                       0x00200000L
#define CB_COLOR7_DCC_CONTROL__DCC_COMPRESS_DISABLE_MASK                                                      0x00400000L
//CB_COLOR7_CMASK
#define CB_COLOR7_CMASK__BASE_256B__SHIFT                                                                     0x0
#define CB_COLOR7_CMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
//CB_COLOR7_CMASK_SLICE
#define CB_COLOR7_CMASK_SLICE__TILE_MAX__SHIFT                                                                0x0
#define CB_COLOR7_CMASK_SLICE__TILE_MAX_MASK                                                                  0x00003FFFL
//CB_COLOR7_FMASK
#define CB_COLOR7_FMASK__BASE_256B__SHIFT                                                                     0x0
#define CB_COLOR7_FMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
//CB_COLOR7_FMASK_SLICE
#define CB_COLOR7_FMASK_SLICE__TILE_MAX__SHIFT                                                                0x0
#define CB_COLOR7_FMASK_SLICE__TILE_MAX_MASK                                                                  0x003FFFFFL
//CB_COLOR7_CLEAR_WORD0
#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0__SHIFT                                                             0x0
#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0_MASK                                                               0xFFFFFFFFL
//CB_COLOR7_CLEAR_WORD1
#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1__SHIFT                                                             0x0
#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1_MASK                                                               0xFFFFFFFFL
//CB_COLOR7_DCC_BASE
#define CB_COLOR7_DCC_BASE__BASE_256B__SHIFT                                                                  0x0
#define CB_COLOR7_DCC_BASE__BASE_256B_MASK                                                                    0xFFFFFFFFL
//CB_COLOR0_BASE_EXT
#define CB_COLOR0_BASE_EXT__BASE_256B__SHIFT                                                                  0x0
#define CB_COLOR0_BASE_EXT__BASE_256B_MASK                                                                    0x000000FFL
//CB_COLOR1_BASE_EXT
#define CB_COLOR1_BASE_EXT__BASE_256B__SHIFT                                                                  0x0
#define CB_COLOR1_BASE_EXT__BASE_256B_MASK                                                                    0x000000FFL
//CB_COLOR2_BASE_EXT
#define CB_COLOR2_BASE_EXT__BASE_256B__SHIFT                                                                  0x0
#define CB_COLOR2_BASE_EXT__BASE_256B_MASK                                                                    0x000000FFL
//CB_COLOR3_BASE_EXT
#define CB_COLOR3_BASE_EXT__BASE_256B__SHIFT                                                                  0x0
#define CB_COLOR3_BASE_EXT__BASE_256B_MASK                                                                    0x000000FFL
//CB_COLOR4_BASE_EXT
#define CB_COLOR4_BASE_EXT__BASE_256B__SHIFT                                                                  0x0
#define CB_COLOR4_BASE_EXT__BASE_256B_MASK                                                                    0x000000FFL
//CB_COLOR5_BASE_EXT
#define CB_COLOR5_BASE_EXT__BASE_256B__SHIFT                                                                  0x0
#define CB_COLOR5_BASE_EXT__BASE_256B_MASK                                                                    0x000000FFL
//CB_COLOR6_BASE_EXT
#define CB_COLOR6_BASE_EXT__BASE_256B__SHIFT                                                                  0x0
#define CB_COLOR6_BASE_EXT__BASE_256B_MASK                                                                    0x000000FFL
//CB_COLOR7_BASE_EXT
#define CB_COLOR7_BASE_EXT__BASE_256B__SHIFT                                                                  0x0
#define CB_COLOR7_BASE_EXT__BASE_256B_MASK                                                                    0x000000FFL
//CB_COLOR0_CMASK_BASE_EXT
#define CB_COLOR0_CMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
#define CB_COLOR0_CMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
//CB_COLOR1_CMASK_BASE_EXT
#define CB_COLOR1_CMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
#define CB_COLOR1_CMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
//CB_COLOR2_CMASK_BASE_EXT
#define CB_COLOR2_CMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
#define CB_COLOR2_CMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
//CB_COLOR3_CMASK_BASE_EXT
#define CB_COLOR3_CMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
#define CB_COLOR3_CMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
//CB_COLOR4_CMASK_BASE_EXT
#define CB_COLOR4_CMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
#define CB_COLOR4_CMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
//CB_COLOR5_CMASK_BASE_EXT
#define CB_COLOR5_CMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
#define CB_COLOR5_CMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
//CB_COLOR6_CMASK_BASE_EXT
#define CB_COLOR6_CMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
#define CB_COLOR6_CMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
//CB_COLOR7_CMASK_BASE_EXT
#define CB_COLOR7_CMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
#define CB_COLOR7_CMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
//CB_COLOR0_FMASK_BASE_EXT
#define CB_COLOR0_FMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
#define CB_COLOR0_FMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
//CB_COLOR1_FMASK_BASE_EXT
#define CB_COLOR1_FMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
#define CB_COLOR1_FMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
//CB_COLOR2_FMASK_BASE_EXT
#define CB_COLOR2_FMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
#define CB_COLOR2_FMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
//CB_COLOR3_FMASK_BASE_EXT
#define CB_COLOR3_FMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
#define CB_COLOR3_FMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
//CB_COLOR4_FMASK_BASE_EXT
#define CB_COLOR4_FMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
#define CB_COLOR4_FMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
//CB_COLOR5_FMASK_BASE_EXT
#define CB_COLOR5_FMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
#define CB_COLOR5_FMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
//CB_COLOR6_FMASK_BASE_EXT
#define CB_COLOR6_FMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
#define CB_COLOR6_FMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
//CB_COLOR7_FMASK_BASE_EXT
#define CB_COLOR7_FMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
#define CB_COLOR7_FMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
//CB_COLOR0_DCC_BASE_EXT
#define CB_COLOR0_DCC_BASE_EXT__BASE_256B__SHIFT                                                              0x0
#define CB_COLOR0_DCC_BASE_EXT__BASE_256B_MASK                                                                0x000000FFL
//CB_COLOR1_DCC_BASE_EXT
#define CB_COLOR1_DCC_BASE_EXT__BASE_256B__SHIFT                                                              0x0
#define CB_COLOR1_DCC_BASE_EXT__BASE_256B_MASK                                                                0x000000FFL
//CB_COLOR2_DCC_BASE_EXT
#define CB_COLOR2_DCC_BASE_EXT__BASE_256B__SHIFT                                                              0x0
#define CB_COLOR2_DCC_BASE_EXT__BASE_256B_MASK                                                                0x000000FFL
//CB_COLOR3_DCC_BASE_EXT
#define CB_COLOR3_DCC_BASE_EXT__BASE_256B__SHIFT                                                              0x0
#define CB_COLOR3_DCC_BASE_EXT__BASE_256B_MASK                                                                0x000000FFL
//CB_COLOR4_DCC_BASE_EXT
#define CB_COLOR4_DCC_BASE_EXT__BASE_256B__SHIFT                                                              0x0
#define CB_COLOR4_DCC_BASE_EXT__BASE_256B_MASK                                                                0x000000FFL
//CB_COLOR5_DCC_BASE_EXT
#define CB_COLOR5_DCC_BASE_EXT__BASE_256B__SHIFT                                                              0x0
#define CB_COLOR5_DCC_BASE_EXT__BASE_256B_MASK                                                                0x000000FFL
//CB_COLOR6_DCC_BASE_EXT
#define CB_COLOR6_DCC_BASE_EXT__BASE_256B__SHIFT                                                              0x0
#define CB_COLOR6_DCC_BASE_EXT__BASE_256B_MASK                                                                0x000000FFL
//CB_COLOR7_DCC_BASE_EXT
#define CB_COLOR7_DCC_BASE_EXT__BASE_256B__SHIFT                                                              0x0
#define CB_COLOR7_DCC_BASE_EXT__BASE_256B_MASK                                                                0x000000FFL
//CB_COLOR0_ATTRIB2
#define CB_COLOR0_ATTRIB2__MIP0_HEIGHT__SHIFT                                                                 0x0
#define CB_COLOR0_ATTRIB2__MIP0_WIDTH__SHIFT                                                                  0xe
#define CB_COLOR0_ATTRIB2__MAX_MIP__SHIFT                                                                     0x1c
#define CB_COLOR0_ATTRIB2__MIP0_HEIGHT_MASK                                                                   0x00003FFFL
#define CB_COLOR0_ATTRIB2__MIP0_WIDTH_MASK                                                                    0x0FFFC000L
#define CB_COLOR0_ATTRIB2__MAX_MIP_MASK                                                                       0xF0000000L
//CB_COLOR1_ATTRIB2
#define CB_COLOR1_ATTRIB2__MIP0_HEIGHT__SHIFT                                                                 0x0
#define CB_COLOR1_ATTRIB2__MIP0_WIDTH__SHIFT                                                                  0xe
#define CB_COLOR1_ATTRIB2__MAX_MIP__SHIFT                                                                     0x1c
#define CB_COLOR1_ATTRIB2__MIP0_HEIGHT_MASK                                                                   0x00003FFFL
#define CB_COLOR1_ATTRIB2__MIP0_WIDTH_MASK                                                                    0x0FFFC000L
#define CB_COLOR1_ATTRIB2__MAX_MIP_MASK                                                                       0xF0000000L
//CB_COLOR2_ATTRIB2
#define CB_COLOR2_ATTRIB2__MIP0_HEIGHT__SHIFT                                                                 0x0
#define CB_COLOR2_ATTRIB2__MIP0_WIDTH__SHIFT                                                                  0xe
#define CB_COLOR2_ATTRIB2__MAX_MIP__SHIFT                                                                     0x1c
#define CB_COLOR2_ATTRIB2__MIP0_HEIGHT_MASK                                                                   0x00003FFFL
#define CB_COLOR2_ATTRIB2__MIP0_WIDTH_MASK                                                                    0x0FFFC000L
#define CB_COLOR2_ATTRIB2__MAX_MIP_MASK                                                                       0xF0000000L
//CB_COLOR3_ATTRIB2
#define CB_COLOR3_ATTRIB2__MIP0_HEIGHT__SHIFT                                                                 0x0
#define CB_COLOR3_ATTRIB2__MIP0_WIDTH__SHIFT                                                                  0xe
#define CB_COLOR3_ATTRIB2__MAX_MIP__SHIFT                                                                     0x1c
#define CB_COLOR3_ATTRIB2__MIP0_HEIGHT_MASK                                                                   0x00003FFFL
#define CB_COLOR3_ATTRIB2__MIP0_WIDTH_MASK                                                                    0x0FFFC000L
#define CB_COLOR3_ATTRIB2__MAX_MIP_MASK                                                                       0xF0000000L
//CB_COLOR4_ATTRIB2
#define CB_COLOR4_ATTRIB2__MIP0_HEIGHT__SHIFT                                                                 0x0
#define CB_COLOR4_ATTRIB2__MIP0_WIDTH__SHIFT                                                                  0xe
#define CB_COLOR4_ATTRIB2__MAX_MIP__SHIFT                                                                     0x1c
#define CB_COLOR4_ATTRIB2__MIP0_HEIGHT_MASK                                                                   0x00003FFFL
#define CB_COLOR4_ATTRIB2__MIP0_WIDTH_MASK                                                                    0x0FFFC000L
#define CB_COLOR4_ATTRIB2__MAX_MIP_MASK                                                                       0xF0000000L
//CB_COLOR5_ATTRIB2
#define CB_COLOR5_ATTRIB2__MIP0_HEIGHT__SHIFT                                                                 0x0
#define CB_COLOR5_ATTRIB2__MIP0_WIDTH__SHIFT                                                                  0xe
#define CB_COLOR5_ATTRIB2__MAX_MIP__SHIFT                                                                     0x1c
#define CB_COLOR5_ATTRIB2__MIP0_HEIGHT_MASK                                                                   0x00003FFFL
#define CB_COLOR5_ATTRIB2__MIP0_WIDTH_MASK                                                                    0x0FFFC000L
#define CB_COLOR5_ATTRIB2__MAX_MIP_MASK                                                                       0xF0000000L
//CB_COLOR6_ATTRIB2
#define CB_COLOR6_ATTRIB2__MIP0_HEIGHT__SHIFT                                                                 0x0
#define CB_COLOR6_ATTRIB2__MIP0_WIDTH__SHIFT                                                                  0xe
#define CB_COLOR6_ATTRIB2__MAX_MIP__SHIFT                                                                     0x1c
#define CB_COLOR6_ATTRIB2__MIP0_HEIGHT_MASK                                                                   0x00003FFFL
#define CB_COLOR6_ATTRIB2__MIP0_WIDTH_MASK                                                                    0x0FFFC000L
#define CB_COLOR6_ATTRIB2__MAX_MIP_MASK                                                                       0xF0000000L
//CB_COLOR7_ATTRIB2
#define CB_COLOR7_ATTRIB2__MIP0_HEIGHT__SHIFT                                                                 0x0
#define CB_COLOR7_ATTRIB2__MIP0_WIDTH__SHIFT                                                                  0xe
#define CB_COLOR7_ATTRIB2__MAX_MIP__SHIFT                                                                     0x1c
#define CB_COLOR7_ATTRIB2__MIP0_HEIGHT_MASK                                                                   0x00003FFFL
#define CB_COLOR7_ATTRIB2__MIP0_WIDTH_MASK                                                                    0x0FFFC000L
#define CB_COLOR7_ATTRIB2__MAX_MIP_MASK                                                                       0xF0000000L
//CB_COLOR0_ATTRIB3
#define CB_COLOR0_ATTRIB3__MIP0_DEPTH__SHIFT                                                                  0x0
#define CB_COLOR0_ATTRIB3__META_LINEAR__SHIFT                                                                 0xd
#define CB_COLOR0_ATTRIB3__COLOR_SW_MODE__SHIFT                                                               0xe
#define CB_COLOR0_ATTRIB3__FMASK_SW_MODE__SHIFT                                                               0x13
#define CB_COLOR0_ATTRIB3__RESOURCE_TYPE__SHIFT                                                               0x18
#define CB_COLOR0_ATTRIB3__CMASK_PIPE_ALIGNED__SHIFT                                                          0x1a
#define CB_COLOR0_ATTRIB3__RESOURCE_LEVEL__SHIFT                                                              0x1b
#define CB_COLOR0_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT                                                            0x1e
#define CB_COLOR0_ATTRIB3__MIP0_DEPTH_MASK                                                                    0x00001FFFL
#define CB_COLOR0_ATTRIB3__META_LINEAR_MASK                                                                   0x00002000L
#define CB_COLOR0_ATTRIB3__COLOR_SW_MODE_MASK                                                                 0x0007C000L
#define CB_COLOR0_ATTRIB3__FMASK_SW_MODE_MASK                                                                 0x00F80000L
#define CB_COLOR0_ATTRIB3__RESOURCE_TYPE_MASK                                                                 0x03000000L
#define CB_COLOR0_ATTRIB3__CMASK_PIPE_ALIGNED_MASK                                                            0x04000000L
#define CB_COLOR0_ATTRIB3__RESOURCE_LEVEL_MASK                                                                0x38000000L
#define CB_COLOR0_ATTRIB3__DCC_PIPE_ALIGNED_MASK                                                              0x40000000L
//CB_COLOR1_ATTRIB3
#define CB_COLOR1_ATTRIB3__MIP0_DEPTH__SHIFT                                                                  0x0
#define CB_COLOR1_ATTRIB3__META_LINEAR__SHIFT                                                                 0xd
#define CB_COLOR1_ATTRIB3__COLOR_SW_MODE__SHIFT                                                               0xe
#define CB_COLOR1_ATTRIB3__FMASK_SW_MODE__SHIFT                                                               0x13
#define CB_COLOR1_ATTRIB3__RESOURCE_TYPE__SHIFT                                                               0x18
#define CB_COLOR1_ATTRIB3__CMASK_PIPE_ALIGNED__SHIFT                                                          0x1a
#define CB_COLOR1_ATTRIB3__RESOURCE_LEVEL__SHIFT                                                              0x1b
#define CB_COLOR1_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT                                                            0x1e
#define CB_COLOR1_ATTRIB3__MIP0_DEPTH_MASK                                                                    0x00001FFFL
#define CB_COLOR1_ATTRIB3__META_LINEAR_MASK                                                                   0x00002000L
#define CB_COLOR1_ATTRIB3__COLOR_SW_MODE_MASK                                                                 0x0007C000L
#define CB_COLOR1_ATTRIB3__FMASK_SW_MODE_MASK                                                                 0x00F80000L
#define CB_COLOR1_ATTRIB3__RESOURCE_TYPE_MASK                                                                 0x03000000L
#define CB_COLOR1_ATTRIB3__CMASK_PIPE_ALIGNED_MASK                                                            0x04000000L
#define CB_COLOR1_ATTRIB3__RESOURCE_LEVEL_MASK                                                                0x38000000L
#define CB_COLOR1_ATTRIB3__DCC_PIPE_ALIGNED_MASK                                                              0x40000000L
//CB_COLOR2_ATTRIB3
#define CB_COLOR2_ATTRIB3__MIP0_DEPTH__SHIFT                                                                  0x0
#define CB_COLOR2_ATTRIB3__META_LINEAR__SHIFT                                                                 0xd
#define CB_COLOR2_ATTRIB3__COLOR_SW_MODE__SHIFT                                                               0xe
#define CB_COLOR2_ATTRIB3__FMASK_SW_MODE__SHIFT                                                               0x13
#define CB_COLOR2_ATTRIB3__RESOURCE_TYPE__SHIFT                                                               0x18
#define CB_COLOR2_ATTRIB3__CMASK_PIPE_ALIGNED__SHIFT                                                          0x1a
#define CB_COLOR2_ATTRIB3__RESOURCE_LEVEL__SHIFT                                                              0x1b
#define CB_COLOR2_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT                                                            0x1e
#define CB_COLOR2_ATTRIB3__MIP0_DEPTH_MASK                                                                    0x00001FFFL
#define CB_COLOR2_ATTRIB3__META_LINEAR_MASK                                                                   0x00002000L
#define CB_COLOR2_ATTRIB3__COLOR_SW_MODE_MASK                                                                 0x0007C000L
#define CB_COLOR2_ATTRIB3__FMASK_SW_MODE_MASK                                                                 0x00F80000L
#define CB_COLOR2_ATTRIB3__RESOURCE_TYPE_MASK                                                                 0x03000000L
#define CB_COLOR2_ATTRIB3__CMASK_PIPE_ALIGNED_MASK                                                            0x04000000L
#define CB_COLOR2_ATTRIB3__RESOURCE_LEVEL_MASK                                                                0x38000000L
#define CB_COLOR2_ATTRIB3__DCC_PIPE_ALIGNED_MASK                                                              0x40000000L
//CB_COLOR3_ATTRIB3
#define CB_COLOR3_ATTRIB3__MIP0_DEPTH__SHIFT                                                                  0x0
#define CB_COLOR3_ATTRIB3__META_LINEAR__SHIFT                                                                 0xd
#define CB_COLOR3_ATTRIB3__COLOR_SW_MODE__SHIFT                                                               0xe
#define CB_COLOR3_ATTRIB3__FMASK_SW_MODE__SHIFT                                                               0x13
#define CB_COLOR3_ATTRIB3__RESOURCE_TYPE__SHIFT                                                               0x18
#define CB_COLOR3_ATTRIB3__CMASK_PIPE_ALIGNED__SHIFT                                                          0x1a
#define CB_COLOR3_ATTRIB3__RESOURCE_LEVEL__SHIFT                                                              0x1b
#define CB_COLOR3_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT                                                            0x1e
#define CB_COLOR3_ATTRIB3__MIP0_DEPTH_MASK                                                                    0x00001FFFL
#define CB_COLOR3_ATTRIB3__META_LINEAR_MASK                                                                   0x00002000L
#define CB_COLOR3_ATTRIB3__COLOR_SW_MODE_MASK                                                                 0x0007C000L
#define CB_COLOR3_ATTRIB3__FMASK_SW_MODE_MASK                                                                 0x00F80000L
#define CB_COLOR3_ATTRIB3__RESOURCE_TYPE_MASK                                                                 0x03000000L
#define CB_COLOR3_ATTRIB3__CMASK_PIPE_ALIGNED_MASK                                                            0x04000000L
#define CB_COLOR3_ATTRIB3__RESOURCE_LEVEL_MASK                                                                0x38000000L
#define CB_COLOR3_ATTRIB3__DCC_PIPE_ALIGNED_MASK                                                              0x40000000L
//CB_COLOR4_ATTRIB3
#define CB_COLOR4_ATTRIB3__MIP0_DEPTH__SHIFT                                                                  0x0
#define CB_COLOR4_ATTRIB3__META_LINEAR__SHIFT                                                                 0xd
#define CB_COLOR4_ATTRIB3__COLOR_SW_MODE__SHIFT                                                               0xe
#define CB_COLOR4_ATTRIB3__FMASK_SW_MODE__SHIFT                                                               0x13
#define CB_COLOR4_ATTRIB3__RESOURCE_TYPE__SHIFT                                                               0x18
#define CB_COLOR4_ATTRIB3__CMASK_PIPE_ALIGNED__SHIFT                                                          0x1a
#define CB_COLOR4_ATTRIB3__RESOURCE_LEVEL__SHIFT                                                              0x1b
#define CB_COLOR4_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT                                                            0x1e
#define CB_COLOR4_ATTRIB3__MIP0_DEPTH_MASK                                                                    0x00001FFFL
#define CB_COLOR4_ATTRIB3__META_LINEAR_MASK                                                                   0x00002000L
#define CB_COLOR4_ATTRIB3__COLOR_SW_MODE_MASK                                                                 0x0007C000L
#define CB_COLOR4_ATTRIB3__FMASK_SW_MODE_MASK                                                                 0x00F80000L
#define CB_COLOR4_ATTRIB3__RESOURCE_TYPE_MASK                                                                 0x03000000L
#define CB_COLOR4_ATTRIB3__CMASK_PIPE_ALIGNED_MASK                                                            0x04000000L
#define CB_COLOR4_ATTRIB3__RESOURCE_LEVEL_MASK                                                                0x38000000L
#define CB_COLOR4_ATTRIB3__DCC_PIPE_ALIGNED_MASK                                                              0x40000000L
//CB_COLOR5_ATTRIB3
#define CB_COLOR5_ATTRIB3__MIP0_DEPTH__SHIFT                                                                  0x0
#define CB_COLOR5_ATTRIB3__META_LINEAR__SHIFT                                                                 0xd
#define CB_COLOR5_ATTRIB3__COLOR_SW_MODE__SHIFT                                                               0xe
#define CB_COLOR5_ATTRIB3__FMASK_SW_MODE__SHIFT                                                               0x13
#define CB_COLOR5_ATTRIB3__RESOURCE_TYPE__SHIFT                                                               0x18
#define CB_COLOR5_ATTRIB3__CMASK_PIPE_ALIGNED__SHIFT                                                          0x1a
#define CB_COLOR5_ATTRIB3__RESOURCE_LEVEL__SHIFT                                                              0x1b
#define CB_COLOR5_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT                                                            0x1e
#define CB_COLOR5_ATTRIB3__MIP0_DEPTH_MASK                                                                    0x00001FFFL
#define CB_COLOR5_ATTRIB3__META_LINEAR_MASK                                                                   0x00002000L
#define CB_COLOR5_ATTRIB3__COLOR_SW_MODE_MASK                                                                 0x0007C000L
#define CB_COLOR5_ATTRIB3__FMASK_SW_MODE_MASK                                                                 0x00F80000L
#define CB_COLOR5_ATTRIB3__RESOURCE_TYPE_MASK                                                                 0x03000000L
#define CB_COLOR5_ATTRIB3__CMASK_PIPE_ALIGNED_MASK                                                            0x04000000L
#define CB_COLOR5_ATTRIB3__RESOURCE_LEVEL_MASK                                                                0x38000000L
#define CB_COLOR5_ATTRIB3__DCC_PIPE_ALIGNED_MASK                                                              0x40000000L
//CB_COLOR6_ATTRIB3
#define CB_COLOR6_ATTRIB3__MIP0_DEPTH__SHIFT                                                                  0x0
#define CB_COLOR6_ATTRIB3__META_LINEAR__SHIFT                                                                 0xd
#define CB_COLOR6_ATTRIB3__COLOR_SW_MODE__SHIFT                                                               0xe
#define CB_COLOR6_ATTRIB3__FMASK_SW_MODE__SHIFT                                                               0x13
#define CB_COLOR6_ATTRIB3__RESOURCE_TYPE__SHIFT                                                               0x18
#define CB_COLOR6_ATTRIB3__CMASK_PIPE_ALIGNED__SHIFT                                                          0x1a
#define CB_COLOR6_ATTRIB3__RESOURCE_LEVEL__SHIFT                                                              0x1b
#define CB_COLOR6_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT                                                            0x1e
#define CB_COLOR6_ATTRIB3__MIP0_DEPTH_MASK                                                                    0x00001FFFL
#define CB_COLOR6_ATTRIB3__META_LINEAR_MASK                                                                   0x00002000L
#define CB_COLOR6_ATTRIB3__COLOR_SW_MODE_MASK                                                                 0x0007C000L
#define CB_COLOR6_ATTRIB3__FMASK_SW_MODE_MASK                                                                 0x00F80000L
#define CB_COLOR6_ATTRIB3__RESOURCE_TYPE_MASK                                                                 0x03000000L
#define CB_COLOR6_ATTRIB3__CMASK_PIPE_ALIGNED_MASK                                                            0x04000000L
#define CB_COLOR6_ATTRIB3__RESOURCE_LEVEL_MASK                                                                0x38000000L
#define CB_COLOR6_ATTRIB3__DCC_PIPE_ALIGNED_MASK                                                              0x40000000L
//CB_COLOR7_ATTRIB3
#define CB_COLOR7_ATTRIB3__MIP0_DEPTH__SHIFT                                                                  0x0
#define CB_COLOR7_ATTRIB3__META_LINEAR__SHIFT                                                                 0xd
#define CB_COLOR7_ATTRIB3__COLOR_SW_MODE__SHIFT                                                               0xe
#define CB_COLOR7_ATTRIB3__FMASK_SW_MODE__SHIFT                                                               0x13
#define CB_COLOR7_ATTRIB3__RESOURCE_TYPE__SHIFT                                                               0x18
#define CB_COLOR7_ATTRIB3__CMASK_PIPE_ALIGNED__SHIFT                                                          0x1a
#define CB_COLOR7_ATTRIB3__RESOURCE_LEVEL__SHIFT                                                              0x1b
#define CB_COLOR7_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT                                                            0x1e
#define CB_COLOR7_ATTRIB3__MIP0_DEPTH_MASK                                                                    0x00001FFFL
#define CB_COLOR7_ATTRIB3__META_LINEAR_MASK                                                                   0x00002000L
#define CB_COLOR7_ATTRIB3__COLOR_SW_MODE_MASK                                                                 0x0007C000L
#define CB_COLOR7_ATTRIB3__FMASK_SW_MODE_MASK                                                                 0x00F80000L
#define CB_COLOR7_ATTRIB3__RESOURCE_TYPE_MASK                                                                 0x03000000L
#define CB_COLOR7_ATTRIB3__CMASK_PIPE_ALIGNED_MASK                                                            0x04000000L
#define CB_COLOR7_ATTRIB3__RESOURCE_LEVEL_MASK                                                                0x38000000L
#define CB_COLOR7_ATTRIB3__DCC_PIPE_ALIGNED_MASK                                                              0x40000000L


// addressBlock: gc_gfxudec
//CP_EOP_DONE_ADDR_LO
#define CP_EOP_DONE_ADDR_LO__ADDR_LO__SHIFT                                                                   0x2
#define CP_EOP_DONE_ADDR_LO__ADDR_LO_MASK                                                                     0xFFFFFFFCL
//CP_EOP_DONE_ADDR_HI
#define CP_EOP_DONE_ADDR_HI__ADDR_HI__SHIFT                                                                   0x0
#define CP_EOP_DONE_ADDR_HI__ADDR_HI_MASK                                                                     0x0000FFFFL
//CP_EOP_DONE_DATA_LO
#define CP_EOP_DONE_DATA_LO__DATA_LO__SHIFT                                                                   0x0
#define CP_EOP_DONE_DATA_LO__DATA_LO_MASK                                                                     0xFFFFFFFFL
//CP_EOP_DONE_DATA_HI
#define CP_EOP_DONE_DATA_HI__DATA_HI__SHIFT                                                                   0x0
#define CP_EOP_DONE_DATA_HI__DATA_HI_MASK                                                                     0xFFFFFFFFL
//CP_EOP_LAST_FENCE_LO
#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO__SHIFT                                                            0x0
#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO_MASK                                                              0xFFFFFFFFL
//CP_EOP_LAST_FENCE_HI
#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI__SHIFT                                                            0x0
#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI_MASK                                                              0xFFFFFFFFL
//CP_STREAM_OUT_ADDR_LO
#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO__SHIFT                                                      0x2
#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO_MASK                                                        0xFFFFFFFCL
//CP_STREAM_OUT_ADDR_HI
#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI__SHIFT                                                      0x0
#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI_MASK                                                        0x0000FFFFL
//CP_NUM_PRIM_WRITTEN_COUNT0_LO
#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO__SHIFT                                        0x0
#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO_MASK                                          0xFFFFFFFFL
//CP_NUM_PRIM_WRITTEN_COUNT0_HI
#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI__SHIFT                                        0x0
#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI_MASK                                          0xFFFFFFFFL
//CP_NUM_PRIM_NEEDED_COUNT0_LO
#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO__SHIFT                                          0x0
#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO_MASK                                            0xFFFFFFFFL
//CP_NUM_PRIM_NEEDED_COUNT0_HI
#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI__SHIFT                                          0x0
#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI_MASK                                            0xFFFFFFFFL
//CP_NUM_PRIM_WRITTEN_COUNT1_LO
#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO__SHIFT                                        0x0
#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO_MASK                                          0xFFFFFFFFL
//CP_NUM_PRIM_WRITTEN_COUNT1_HI
#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI__SHIFT                                        0x0
#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI_MASK                                          0xFFFFFFFFL
//CP_NUM_PRIM_NEEDED_COUNT1_LO
#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO__SHIFT                                          0x0
#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO_MASK                                            0xFFFFFFFFL
//CP_NUM_PRIM_NEEDED_COUNT1_HI
#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI__SHIFT                                          0x0
#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI_MASK                                            0xFFFFFFFFL
//CP_NUM_PRIM_WRITTEN_COUNT2_LO
#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO__SHIFT                                        0x0
#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO_MASK                                          0xFFFFFFFFL
//CP_NUM_PRIM_WRITTEN_COUNT2_HI
#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI__SHIFT                                        0x0
#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI_MASK                                          0xFFFFFFFFL
//CP_NUM_PRIM_NEEDED_COUNT2_LO
#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO__SHIFT                                          0x0
#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO_MASK                                            0xFFFFFFFFL
//CP_NUM_PRIM_NEEDED_COUNT2_HI
#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI__SHIFT                                          0x0
#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI_MASK                                            0xFFFFFFFFL
//CP_NUM_PRIM_WRITTEN_COUNT3_LO
#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO__SHIFT                                        0x0
#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO_MASK                                          0xFFFFFFFFL
//CP_NUM_PRIM_WRITTEN_COUNT3_HI
#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI__SHIFT                                        0x0
#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI_MASK                                          0xFFFFFFFFL
//CP_NUM_PRIM_NEEDED_COUNT3_LO
#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO__SHIFT                                          0x0
#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO_MASK                                            0xFFFFFFFFL
//CP_NUM_PRIM_NEEDED_COUNT3_HI
#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI__SHIFT                                          0x0
#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI_MASK                                            0xFFFFFFFFL
//CP_PIPE_STATS_ADDR_LO
#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO__SHIFT                                                      0x2
#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO_MASK                                                        0xFFFFFFFCL
//CP_PIPE_STATS_ADDR_HI
#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI__SHIFT                                                      0x0
#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI_MASK                                                        0x0000FFFFL
//CP_VGT_IAVERT_COUNT_LO
#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO__SHIFT                                                        0x0
#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO_MASK                                                          0xFFFFFFFFL
//CP_VGT_IAVERT_COUNT_HI
#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI__SHIFT                                                        0x0
#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI_MASK                                                          0xFFFFFFFFL
//CP_VGT_IAPRIM_COUNT_LO
#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO__SHIFT                                                        0x0
#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO_MASK                                                          0xFFFFFFFFL
//CP_VGT_IAPRIM_COUNT_HI
#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI__SHIFT                                                        0x0
#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI_MASK                                                          0xFFFFFFFFL
//CP_VGT_GSPRIM_COUNT_LO
#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO__SHIFT                                                        0x0
#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO_MASK                                                          0xFFFFFFFFL
//CP_VGT_GSPRIM_COUNT_HI
#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI__SHIFT                                                        0x0
#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI_MASK                                                          0xFFFFFFFFL
//CP_VGT_VSINVOC_COUNT_LO
#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO__SHIFT                                                      0x0
#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO_MASK                                                        0xFFFFFFFFL
//CP_VGT_VSINVOC_COUNT_HI
#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI__SHIFT                                                      0x0
#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI_MASK                                                        0xFFFFFFFFL
//CP_VGT_GSINVOC_COUNT_LO
#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO__SHIFT                                                      0x0
#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO_MASK                                                        0xFFFFFFFFL
//CP_VGT_GSINVOC_COUNT_HI
#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI__SHIFT                                                      0x0
#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI_MASK                                                        0xFFFFFFFFL
//CP_VGT_HSINVOC_COUNT_LO
#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO__SHIFT                                                      0x0
#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO_MASK                                                        0xFFFFFFFFL
//CP_VGT_HSINVOC_COUNT_HI
#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI__SHIFT                                                      0x0
#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI_MASK                                                        0xFFFFFFFFL
//CP_VGT_DSINVOC_COUNT_LO
#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO__SHIFT                                                      0x0
#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO_MASK                                                        0xFFFFFFFFL
//CP_VGT_DSINVOC_COUNT_HI
#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI__SHIFT                                                      0x0
#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI_MASK                                                        0xFFFFFFFFL
//CP_PA_CINVOC_COUNT_LO
#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO__SHIFT                                                         0x0
#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO_MASK                                                           0xFFFFFFFFL
//CP_PA_CINVOC_COUNT_HI
#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI__SHIFT                                                         0x0
#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI_MASK                                                           0xFFFFFFFFL
//CP_PA_CPRIM_COUNT_LO
#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO__SHIFT                                                           0x0
#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO_MASK                                                             0xFFFFFFFFL
//CP_PA_CPRIM_COUNT_HI
#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI__SHIFT                                                           0x0
#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI_MASK                                                             0xFFFFFFFFL
//CP_SC_PSINVOC_COUNT0_LO
#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO__SHIFT                                                     0x0
#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO_MASK                                                       0xFFFFFFFFL
//CP_SC_PSINVOC_COUNT0_HI
#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT                                                     0x0
#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI_MASK                                                       0xFFFFFFFFL
//CP_SC_PSINVOC_COUNT1_LO
#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE__SHIFT                                                              0x0
#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE_MASK                                                                0xFFFFFFFFL
//CP_SC_PSINVOC_COUNT1_HI
#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE__SHIFT                                                              0x0
#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE_MASK                                                                0xFFFFFFFFL
//CP_VGT_CSINVOC_COUNT_LO
#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO__SHIFT                                                      0x0
#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO_MASK                                                        0xFFFFFFFFL
//CP_VGT_CSINVOC_COUNT_HI
#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI__SHIFT                                                      0x0
#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI_MASK                                                        0xFFFFFFFFL
//CP_PIPE_STATS_CONTROL
#define CP_PIPE_STATS_CONTROL__CACHE_POLICY__SHIFT                                                            0x19
#define CP_PIPE_STATS_CONTROL__CACHE_POLICY_MASK                                                              0x06000000L
//CP_STREAM_OUT_CONTROL
#define CP_STREAM_OUT_CONTROL__CACHE_POLICY__SHIFT                                                            0x19
#define CP_STREAM_OUT_CONTROL__CACHE_POLICY_MASK                                                              0x06000000L
//CP_STRMOUT_CNTL
#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE__SHIFT                                                            0x0
#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE_MASK                                                              0x00000001L
//SCRATCH_REG0
#define SCRATCH_REG0__SCRATCH_REG0__SHIFT                                                                     0x0
#define SCRATCH_REG0__SCRATCH_REG0_MASK                                                                       0xFFFFFFFFL
//SCRATCH_REG1
#define SCRATCH_REG1__SCRATCH_REG1__SHIFT                                                                     0x0
#define SCRATCH_REG1__SCRATCH_REG1_MASK                                                                       0xFFFFFFFFL
//SCRATCH_REG2
#define SCRATCH_REG2__SCRATCH_REG2__SHIFT                                                                     0x0
#define SCRATCH_REG2__SCRATCH_REG2_MASK                                                                       0xFFFFFFFFL
//SCRATCH_REG3
#define SCRATCH_REG3__SCRATCH_REG3__SHIFT                                                                     0x0
#define SCRATCH_REG3__SCRATCH_REG3_MASK                                                                       0xFFFFFFFFL
//SCRATCH_REG4
#define SCRATCH_REG4__SCRATCH_REG4__SHIFT                                                                     0x0
#define SCRATCH_REG4__SCRATCH_REG4_MASK                                                                       0xFFFFFFFFL
//SCRATCH_REG5
#define SCRATCH_REG5__SCRATCH_REG5__SHIFT                                                                     0x0
#define SCRATCH_REG5__SCRATCH_REG5_MASK                                                                       0xFFFFFFFFL
//SCRATCH_REG6
#define SCRATCH_REG6__SCRATCH_REG6__SHIFT                                                                     0x0
#define SCRATCH_REG6__SCRATCH_REG6_MASK                                                                       0xFFFFFFFFL
//SCRATCH_REG7
#define SCRATCH_REG7__SCRATCH_REG7__SHIFT                                                                     0x0
#define SCRATCH_REG7__SCRATCH_REG7_MASK                                                                       0xFFFFFFFFL
//SCRATCH_REG_ATOMIC
#define SCRATCH_REG_ATOMIC__IMMED__SHIFT                                                                      0x0
#define SCRATCH_REG_ATOMIC__ID__SHIFT                                                                         0x18
#define SCRATCH_REG_ATOMIC__reserved27__SHIFT                                                                 0x1b
#define SCRATCH_REG_ATOMIC__OP__SHIFT                                                                         0x1c
#define SCRATCH_REG_ATOMIC__reserved31__SHIFT                                                                 0x1f
#define SCRATCH_REG_ATOMIC__IMMED_MASK                                                                        0x00FFFFFFL
#define SCRATCH_REG_ATOMIC__ID_MASK                                                                           0x07000000L
#define SCRATCH_REG_ATOMIC__reserved27_MASK                                                                   0x08000000L
#define SCRATCH_REG_ATOMIC__OP_MASK                                                                           0x70000000L
#define SCRATCH_REG_ATOMIC__reserved31_MASK                                                                   0x80000000L
//SCRATCH_REG_CMPSWAP_ATOMIC
#define SCRATCH_REG_CMPSWAP_ATOMIC__IMMED_COMPARE__SHIFT                                                      0x0
#define SCRATCH_REG_CMPSWAP_ATOMIC__IMMED_REPLACE__SHIFT                                                      0xc
#define SCRATCH_REG_CMPSWAP_ATOMIC__ID__SHIFT                                                                 0x18
#define SCRATCH_REG_CMPSWAP_ATOMIC__reserved27__SHIFT                                                         0x1b
#define SCRATCH_REG_CMPSWAP_ATOMIC__OP__SHIFT                                                                 0x1c
#define SCRATCH_REG_CMPSWAP_ATOMIC__reserved31__SHIFT                                                         0x1f
#define SCRATCH_REG_CMPSWAP_ATOMIC__IMMED_COMPARE_MASK                                                        0x00000FFFL
#define SCRATCH_REG_CMPSWAP_ATOMIC__IMMED_REPLACE_MASK                                                        0x00FFF000L
#define SCRATCH_REG_CMPSWAP_ATOMIC__ID_MASK                                                                   0x07000000L
#define SCRATCH_REG_CMPSWAP_ATOMIC__reserved27_MASK                                                           0x08000000L
#define SCRATCH_REG_CMPSWAP_ATOMIC__OP_MASK                                                                   0x70000000L
#define SCRATCH_REG_CMPSWAP_ATOMIC__reserved31_MASK                                                           0x80000000L
//CP_APPEND_DDID_CNT
#define CP_APPEND_DDID_CNT__DATA__SHIFT                                                                       0x0
#define CP_APPEND_DDID_CNT__DATA_MASK                                                                         0x000000FFL
//CP_APPEND_DATA_HI
#define CP_APPEND_DATA_HI__DATA__SHIFT                                                                        0x0
#define CP_APPEND_DATA_HI__DATA_MASK                                                                          0xFFFFFFFFL
//CP_APPEND_LAST_CS_FENCE_HI
#define CP_APPEND_LAST_CS_FENCE_HI__LAST_FENCE__SHIFT                                                         0x0
#define CP_APPEND_LAST_CS_FENCE_HI__LAST_FENCE_MASK                                                           0xFFFFFFFFL
//CP_APPEND_LAST_PS_FENCE_HI
#define CP_APPEND_LAST_PS_FENCE_HI__LAST_FENCE__SHIFT                                                         0x0
#define CP_APPEND_LAST_PS_FENCE_HI__LAST_FENCE_MASK                                                           0xFFFFFFFFL
//SCRATCH_UMSK
#define SCRATCH_UMSK__OBSOLETE_UMSK__SHIFT                                                                    0x0
#define SCRATCH_UMSK__OBSOLETE_SWAP__SHIFT                                                                    0x10
#define SCRATCH_UMSK__OBSOLETE_UMSK_MASK                                                                      0x000000FFL
#define SCRATCH_UMSK__OBSOLETE_SWAP_MASK                                                                      0x00030000L
//SCRATCH_ADDR
#define SCRATCH_ADDR__OBSOLETE_ADDR__SHIFT                                                                    0x0
#define SCRATCH_ADDR__OBSOLETE_ADDR_MASK                                                                      0xFFFFFFFFL
//CP_PFP_ATOMIC_PREOP_LO
#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT                                                        0x0
#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK                                                          0xFFFFFFFFL
//CP_PFP_ATOMIC_PREOP_HI
#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT                                                        0x0
#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK                                                          0xFFFFFFFFL
//CP_PFP_GDS_ATOMIC0_PREOP_LO
#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT                                              0x0
#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK                                                0xFFFFFFFFL
//CP_PFP_GDS_ATOMIC0_PREOP_HI
#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT                                              0x0
#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK                                                0xFFFFFFFFL
//CP_PFP_GDS_ATOMIC1_PREOP_LO
#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT                                              0x0
#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK                                                0xFFFFFFFFL
//CP_PFP_GDS_ATOMIC1_PREOP_HI
#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT                                              0x0
#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK                                                0xFFFFFFFFL
//CP_APPEND_ADDR_LO
#define CP_APPEND_ADDR_LO__MEM_ADDR_LO__SHIFT                                                                 0x2
#define CP_APPEND_ADDR_LO__MEM_ADDR_LO_MASK                                                                   0xFFFFFFFCL
//CP_APPEND_ADDR_HI
#define CP_APPEND_ADDR_HI__MEM_ADDR_HI__SHIFT                                                                 0x0
#define CP_APPEND_ADDR_HI__CS_PS_SEL__SHIFT                                                                   0x10
#define CP_APPEND_ADDR_HI__CACHE_POLICY__SHIFT                                                                0x19
#define CP_APPEND_ADDR_HI__COMMAND__SHIFT                                                                     0x1d
#define CP_APPEND_ADDR_HI__MEM_ADDR_HI_MASK                                                                   0x0000FFFFL
#define CP_APPEND_ADDR_HI__CS_PS_SEL_MASK                                                                     0x00010000L
#define CP_APPEND_ADDR_HI__CACHE_POLICY_MASK                                                                  0x06000000L
#define CP_APPEND_ADDR_HI__COMMAND_MASK                                                                       0xE0000000L
//CP_APPEND_DATA
#define CP_APPEND_DATA__DATA__SHIFT                                                                           0x0
#define CP_APPEND_DATA__DATA_MASK                                                                             0xFFFFFFFFL
//CP_APPEND_DATA_LO
#define CP_APPEND_DATA_LO__DATA__SHIFT                                                                        0x0
#define CP_APPEND_DATA_LO__DATA_MASK                                                                          0xFFFFFFFFL
//CP_APPEND_LAST_CS_FENCE
#define CP_APPEND_LAST_CS_FENCE__LAST_FENCE__SHIFT                                                            0x0
#define CP_APPEND_LAST_CS_FENCE__LAST_FENCE_MASK                                                              0xFFFFFFFFL
//CP_APPEND_LAST_CS_FENCE_LO
#define CP_APPEND_LAST_CS_FENCE_LO__LAST_FENCE__SHIFT                                                         0x0
#define CP_APPEND_LAST_CS_FENCE_LO__LAST_FENCE_MASK                                                           0xFFFFFFFFL
//CP_APPEND_LAST_PS_FENCE
#define CP_APPEND_LAST_PS_FENCE__LAST_FENCE__SHIFT                                                            0x0
#define CP_APPEND_LAST_PS_FENCE__LAST_FENCE_MASK                                                              0xFFFFFFFFL
//CP_APPEND_LAST_PS_FENCE_LO
#define CP_APPEND_LAST_PS_FENCE_LO__LAST_FENCE__SHIFT                                                         0x0
#define CP_APPEND_LAST_PS_FENCE_LO__LAST_FENCE_MASK                                                           0xFFFFFFFFL
//CP_ATOMIC_PREOP_LO
#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT                                                            0x0
#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK                                                              0xFFFFFFFFL
//CP_ME_ATOMIC_PREOP_LO
#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT                                                         0x0
#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK                                                           0xFFFFFFFFL
//CP_ATOMIC_PREOP_HI
#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT                                                            0x0
#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK                                                              0xFFFFFFFFL
//CP_ME_ATOMIC_PREOP_HI
#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT                                                         0x0
#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK                                                           0xFFFFFFFFL
//CP_GDS_ATOMIC0_PREOP_LO
#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT                                                  0x0
#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK                                                    0xFFFFFFFFL
//CP_ME_GDS_ATOMIC0_PREOP_LO
#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT                                               0x0
#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK                                                 0xFFFFFFFFL
//CP_GDS_ATOMIC0_PREOP_HI
#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT                                                  0x0
#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK                                                    0xFFFFFFFFL
//CP_ME_GDS_ATOMIC0_PREOP_HI
#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT                                               0x0
#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK                                                 0xFFFFFFFFL
//CP_GDS_ATOMIC1_PREOP_LO
#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT                                                  0x0
#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK                                                    0xFFFFFFFFL
//CP_ME_GDS_ATOMIC1_PREOP_LO
#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT                                               0x0
#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK                                                 0xFFFFFFFFL
//CP_GDS_ATOMIC1_PREOP_HI
#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT                                                  0x0
#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK                                                    0xFFFFFFFFL
//CP_ME_GDS_ATOMIC1_PREOP_HI
#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT                                               0x0
#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK                                                 0xFFFFFFFFL
//CP_ME_MC_WADDR_LO
#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO__SHIFT                                                              0x2
#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO_MASK                                                                0xFFFFFFFCL
//CP_ME_MC_WADDR_HI
#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI__SHIFT                                                              0x0
#define CP_ME_MC_WADDR_HI__CACHE_POLICY__SHIFT                                                                0x16
#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI_MASK                                                                0x0000FFFFL
#define CP_ME_MC_WADDR_HI__CACHE_POLICY_MASK                                                                  0x00C00000L
//CP_ME_MC_WDATA_LO
#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO__SHIFT                                                              0x0
#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO_MASK                                                                0xFFFFFFFFL
//CP_ME_MC_WDATA_HI
#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI__SHIFT                                                              0x0
#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI_MASK                                                                0xFFFFFFFFL
//CP_ME_MC_RADDR_LO
#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO__SHIFT                                                              0x2
#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO_MASK                                                                0xFFFFFFFCL
//CP_ME_MC_RADDR_HI
#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI__SHIFT                                                              0x0
#define CP_ME_MC_RADDR_HI__CACHE_POLICY__SHIFT                                                                0x16
#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI_MASK                                                                0x0000FFFFL
#define CP_ME_MC_RADDR_HI__CACHE_POLICY_MASK                                                                  0x00C00000L
//CP_SEM_WAIT_TIMER
#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER__SHIFT                                                              0x0
#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER_MASK                                                                0xFFFFFFFFL
//CP_SIG_SEM_ADDR_LO
#define CP_SIG_SEM_ADDR_LO__SEM_PRIV__SHIFT                                                                   0x0
#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT                                                                0x3
#define CP_SIG_SEM_ADDR_LO__SEM_PRIV_MASK                                                                     0x00000001L
#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO_MASK                                                                  0xFFFFFFF8L
//CP_SIG_SEM_ADDR_HI
#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT                                                                0x0
#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT                                                            0x10
#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT                                                            0x14
#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT                                                            0x18
#define CP_SIG_SEM_ADDR_HI__SEM_SELECT__SHIFT                                                                 0x1d
#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI_MASK                                                                  0x0000FFFFL
#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK                                                              0x00010000L
#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK                                                              0x00100000L
#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK                                                              0x03000000L
#define CP_SIG_SEM_ADDR_HI__SEM_SELECT_MASK                                                                   0xE0000000L
//CP_WAIT_REG_MEM_TIMEOUT
#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT__SHIFT                                                  0x0
#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT_MASK                                                    0xFFFFFFFFL
//CP_WAIT_SEM_ADDR_LO
#define CP_WAIT_SEM_ADDR_LO__SEM_PRIV__SHIFT                                                                  0x0
#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT                                                               0x3
#define CP_WAIT_SEM_ADDR_LO__SEM_PRIV_MASK                                                                    0x00000001L
#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO_MASK                                                                 0xFFFFFFF8L
//CP_WAIT_SEM_ADDR_HI
#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT                                                               0x0
#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT                                                           0x10
#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT                                                           0x14
#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT                                                           0x18
#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT                                                                0x1d
#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI_MASK                                                                 0x0000FFFFL
#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK                                                             0x00010000L
#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK                                                             0x00100000L
#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK                                                             0x03000000L
#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK                                                                  0xE0000000L
//CP_DMA_PFP_CONTROL
#define CP_DMA_PFP_CONTROL__MEMLOG_CLEAR__SHIFT                                                               0xa
#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY__SHIFT                                                           0xd
#define CP_DMA_PFP_CONTROL__SRC_VOLATLE__SHIFT                                                                0xf
#define CP_DMA_PFP_CONTROL__DST_SELECT__SHIFT                                                                 0x14
#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY__SHIFT                                                           0x19
#define CP_DMA_PFP_CONTROL__DST_VOLATLE__SHIFT                                                                0x1b
#define CP_DMA_PFP_CONTROL__SRC_SELECT__SHIFT                                                                 0x1d
#define CP_DMA_PFP_CONTROL__MEMLOG_CLEAR_MASK                                                                 0x00000400L
#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY_MASK                                                             0x00006000L
#define CP_DMA_PFP_CONTROL__SRC_VOLATLE_MASK                                                                  0x00008000L
#define CP_DMA_PFP_CONTROL__DST_SELECT_MASK                                                                   0x00300000L
#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY_MASK                                                             0x06000000L
#define CP_DMA_PFP_CONTROL__DST_VOLATLE_MASK                                                                  0x08000000L
#define CP_DMA_PFP_CONTROL__SRC_SELECT_MASK                                                                   0x60000000L
//CP_DMA_ME_CONTROL
#define CP_DMA_ME_CONTROL__MEMLOG_CLEAR__SHIFT                                                                0xa
#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT                                                            0xd
#define CP_DMA_ME_CONTROL__SRC_VOLATLE__SHIFT                                                                 0xf
#define CP_DMA_ME_CONTROL__DST_SELECT__SHIFT                                                                  0x14
#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT                                                            0x19
#define CP_DMA_ME_CONTROL__DST_VOLATLE__SHIFT                                                                 0x1b
#define CP_DMA_ME_CONTROL__SRC_SELECT__SHIFT                                                                  0x1d
#define CP_DMA_ME_CONTROL__MEMLOG_CLEAR_MASK                                                                  0x00000400L
#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK                                                              0x00006000L
#define CP_DMA_ME_CONTROL__SRC_VOLATLE_MASK                                                                   0x00008000L
#define CP_DMA_ME_CONTROL__DST_SELECT_MASK                                                                    0x00300000L
#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY_MASK                                                              0x06000000L
#define CP_DMA_ME_CONTROL__DST_VOLATLE_MASK                                                                   0x08000000L
#define CP_DMA_ME_CONTROL__SRC_SELECT_MASK                                                                    0x60000000L
//CP_COHER_BASE_HI
#define CP_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT                                                           0x0
#define CP_COHER_BASE_HI__COHER_BASE_HI_256B_MASK                                                             0x000000FFL
//CP_COHER_START_DELAY
#define CP_COHER_START_DELAY__START_DELAY_COUNT__SHIFT                                                        0x0
#define CP_COHER_START_DELAY__START_DELAY_COUNT_MASK                                                          0x0000003FL
//CP_COHER_CNTL
#define CP_COHER_CNTL__TC_NC_ACTION_ENA__SHIFT                                                                0x3
#define CP_COHER_CNTL__TC_WC_ACTION_ENA__SHIFT                                                                0x4
#define CP_COHER_CNTL__TC_INV_METADATA_ACTION_ENA__SHIFT                                                      0x5
#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA__SHIFT                                                             0xf
#define CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT                                                                0x12
#define CP_COHER_CNTL__TCL1_ACTION_ENA__SHIFT                                                                 0x16
#define CP_COHER_CNTL__TC_ACTION_ENA__SHIFT                                                                   0x17
#define CP_COHER_CNTL__CB_ACTION_ENA__SHIFT                                                                   0x19
#define CP_COHER_CNTL__DB_ACTION_ENA__SHIFT                                                                   0x1a
#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA__SHIFT                                                            0x1b
#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA__SHIFT                                                        0x1c
#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA__SHIFT                                                            0x1d
#define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA__SHIFT                                                         0x1e
#define CP_COHER_CNTL__TC_NC_ACTION_ENA_MASK                                                                  0x00000008L
#define CP_COHER_CNTL__TC_WC_ACTION_ENA_MASK                                                                  0x00000010L
#define CP_COHER_CNTL__TC_INV_METADATA_ACTION_ENA_MASK                                                        0x00000020L
#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA_MASK                                                               0x00008000L
#define CP_COHER_CNTL__TC_WB_ACTION_ENA_MASK                                                                  0x00040000L
#define CP_COHER_CNTL__TCL1_ACTION_ENA_MASK                                                                   0x00400000L
#define CP_COHER_CNTL__TC_ACTION_ENA_MASK                                                                     0x00800000L
#define CP_COHER_CNTL__CB_ACTION_ENA_MASK                                                                     0x02000000L
#define CP_COHER_CNTL__DB_ACTION_ENA_MASK                                                                     0x04000000L
#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA_MASK                                                              0x08000000L
#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA_MASK                                                          0x10000000L
#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA_MASK                                                              0x20000000L
#define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA_MASK                                                           0x40000000L
//CP_COHER_SIZE
#define CP_COHER_SIZE__COHER_SIZE_256B__SHIFT                                                                 0x0
#define CP_COHER_SIZE__COHER_SIZE_256B_MASK                                                                   0xFFFFFFFFL
//CP_COHER_BASE
#define CP_COHER_BASE__COHER_BASE_256B__SHIFT                                                                 0x0
#define CP_COHER_BASE__COHER_BASE_256B_MASK                                                                   0xFFFFFFFFL
//CP_COHER_STATUS
#define CP_COHER_STATUS__MEID__SHIFT                                                                          0x18
#define CP_COHER_STATUS__STATUS__SHIFT                                                                        0x1f
#define CP_COHER_STATUS__MEID_MASK                                                                            0x03000000L
#define CP_COHER_STATUS__STATUS_MASK                                                                          0x80000000L
//CP_DMA_ME_SRC_ADDR
#define CP_DMA_ME_SRC_ADDR__SRC_ADDR__SHIFT                                                                   0x0
#define CP_DMA_ME_SRC_ADDR__SRC_ADDR_MASK                                                                     0xFFFFFFFFL
//CP_DMA_ME_SRC_ADDR_HI
#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT                                                             0x0
#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI_MASK                                                               0x0000FFFFL
//CP_DMA_ME_DST_ADDR
#define CP_DMA_ME_DST_ADDR__DST_ADDR__SHIFT                                                                   0x0
#define CP_DMA_ME_DST_ADDR__DST_ADDR_MASK                                                                     0xFFFFFFFFL
//CP_DMA_ME_DST_ADDR_HI
#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI__SHIFT                                                             0x0
#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI_MASK                                                               0x0000FFFFL
//CP_DMA_ME_COMMAND
#define CP_DMA_ME_COMMAND__BYTE_COUNT__SHIFT                                                                  0x0
#define CP_DMA_ME_COMMAND__SAS__SHIFT                                                                         0x1a
#define CP_DMA_ME_COMMAND__DAS__SHIFT                                                                         0x1b
#define CP_DMA_ME_COMMAND__SAIC__SHIFT                                                                        0x1c
#define CP_DMA_ME_COMMAND__DAIC__SHIFT                                                                        0x1d
#define CP_DMA_ME_COMMAND__RAW_WAIT__SHIFT                                                                    0x1e
#define CP_DMA_ME_COMMAND__DIS_WC__SHIFT                                                                      0x1f
#define CP_DMA_ME_COMMAND__BYTE_COUNT_MASK                                                                    0x03FFFFFFL
#define CP_DMA_ME_COMMAND__SAS_MASK                                                                           0x04000000L
#define CP_DMA_ME_COMMAND__DAS_MASK                                                                           0x08000000L
#define CP_DMA_ME_COMMAND__SAIC_MASK                                                                          0x10000000L
#define CP_DMA_ME_COMMAND__DAIC_MASK                                                                          0x20000000L
#define CP_DMA_ME_COMMAND__RAW_WAIT_MASK                                                                      0x40000000L
#define CP_DMA_ME_COMMAND__DIS_WC_MASK                                                                        0x80000000L
//CP_DMA_PFP_SRC_ADDR
#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR__SHIFT                                                                  0x0
#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR_MASK                                                                    0xFFFFFFFFL
//CP_DMA_PFP_SRC_ADDR_HI
#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT                                                            0x0
#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI_MASK                                                              0x0000FFFFL
//CP_DMA_PFP_DST_ADDR
#define CP_DMA_PFP_DST_ADDR__DST_ADDR__SHIFT                                                                  0x0
#define CP_DMA_PFP_DST_ADDR__DST_ADDR_MASK                                                                    0xFFFFFFFFL
//CP_DMA_PFP_DST_ADDR_HI
#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI__SHIFT                                                            0x0
#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI_MASK                                                              0x0000FFFFL
//CP_DMA_PFP_COMMAND
#define CP_DMA_PFP_COMMAND__BYTE_COUNT__SHIFT                                                                 0x0
#define CP_DMA_PFP_COMMAND__SAS__SHIFT                                                                        0x1a
#define CP_DMA_PFP_COMMAND__DAS__SHIFT                                                                        0x1b
#define CP_DMA_PFP_COMMAND__SAIC__SHIFT                                                                       0x1c
#define CP_DMA_PFP_COMMAND__DAIC__SHIFT                                                                       0x1d
#define CP_DMA_PFP_COMMAND__RAW_WAIT__SHIFT                                                                   0x1e
#define CP_DMA_PFP_COMMAND__DIS_WC__SHIFT                                                                     0x1f
#define CP_DMA_PFP_COMMAND__BYTE_COUNT_MASK                                                                   0x03FFFFFFL
#define CP_DMA_PFP_COMMAND__SAS_MASK                                                                          0x04000000L
#define CP_DMA_PFP_COMMAND__DAS_MASK                                                                          0x08000000L
#define CP_DMA_PFP_COMMAND__SAIC_MASK                                                                         0x10000000L
#define CP_DMA_PFP_COMMAND__DAIC_MASK                                                                         0x20000000L
#define CP_DMA_PFP_COMMAND__RAW_WAIT_MASK                                                                     0x40000000L
#define CP_DMA_PFP_COMMAND__DIS_WC_MASK                                                                       0x80000000L
//CP_DMA_CNTL
#define CP_DMA_CNTL__UTCL1_FAULT_CONTROL__SHIFT                                                               0x0
#define CP_DMA_CNTL__WATCH_CONTROL__SHIFT                                                                     0x1
#define CP_DMA_CNTL__MIN_AVAILSZ__SHIFT                                                                       0x4
#define CP_DMA_CNTL__BUFFER_DEPTH__SHIFT                                                                      0x10
#define CP_DMA_CNTL__PIO_FIFO_EMPTY__SHIFT                                                                    0x1c
#define CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT                                                                     0x1d
#define CP_DMA_CNTL__PIO_COUNT__SHIFT                                                                         0x1e
#define CP_DMA_CNTL__UTCL1_FAULT_CONTROL_MASK                                                                 0x00000001L
#define CP_DMA_CNTL__WATCH_CONTROL_MASK                                                                       0x00000002L
#define CP_DMA_CNTL__MIN_AVAILSZ_MASK                                                                         0x00000030L
#define CP_DMA_CNTL__BUFFER_DEPTH_MASK                                                                        0x01FF0000L
#define CP_DMA_CNTL__PIO_FIFO_EMPTY_MASK                                                                      0x10000000L
#define CP_DMA_CNTL__PIO_FIFO_FULL_MASK                                                                       0x20000000L
#define CP_DMA_CNTL__PIO_COUNT_MASK                                                                           0xC0000000L
//CP_DMA_READ_TAGS
#define CP_DMA_READ_TAGS__DMA_READ_TAG__SHIFT                                                                 0x0
#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID__SHIFT                                                           0x1c
#define CP_DMA_READ_TAGS__DMA_READ_TAG_MASK                                                                   0x03FFFFFFL
#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID_MASK                                                             0x10000000L
//CP_COHER_SIZE_HI
#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT                                                           0x0
#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK                                                             0x000000FFL
//CP_PFP_IB_CONTROL
#define CP_PFP_IB_CONTROL__IB_EN__SHIFT                                                                       0x0
#define CP_PFP_IB_CONTROL__IB_EN_MASK                                                                         0x000000FFL
//CP_PFP_LOAD_CONTROL
#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN__SHIFT                                                             0x0
#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN__SHIFT                                                               0x1
#define CP_PFP_LOAD_CONTROL__UCONFIG_REG_EN__SHIFT                                                            0xf
#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT                                                             0x10
#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN__SHIFT                                                              0x18
#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN_MASK                                                               0x00000001L
#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN_MASK                                                                 0x00000002L
#define CP_PFP_LOAD_CONTROL__UCONFIG_REG_EN_MASK                                                              0x00008000L
#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN_MASK                                                               0x00010000L
#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN_MASK                                                                0x01000000L
//CP_SCRATCH_INDEX
#define CP_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT                                                                0x0
#define CP_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE__SHIFT                                                     0x1f
#define CP_SCRATCH_INDEX__SCRATCH_INDEX_MASK                                                                  0x000001FFL
#define CP_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE_MASK                                                       0x80000000L
//CP_SCRATCH_DATA
#define CP_SCRATCH_DATA__SCRATCH_DATA__SHIFT                                                                  0x0
#define CP_SCRATCH_DATA__SCRATCH_DATA_MASK                                                                    0xFFFFFFFFL
//CP_RB_OFFSET
#define CP_RB_OFFSET__RB_OFFSET__SHIFT                                                                        0x0
#define CP_RB_OFFSET__RB_OFFSET_MASK                                                                          0x000FFFFFL
//CP_IB2_OFFSET
#define CP_IB2_OFFSET__IB2_OFFSET__SHIFT                                                                      0x0
#define CP_IB2_OFFSET__IB2_OFFSET_MASK                                                                        0x000FFFFFL
//CP_IB2_PREAMBLE_BEGIN
#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN__SHIFT                                                      0x0
#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN_MASK                                                        0x000FFFFFL
//CP_IB2_PREAMBLE_END
#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END__SHIFT                                                          0x0
#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END_MASK                                                            0x000FFFFFL
//CP_CE_IB1_OFFSET
#define CP_CE_IB1_OFFSET__IB1_OFFSET__SHIFT                                                                   0x0
#define CP_CE_IB1_OFFSET__IB1_OFFSET_MASK                                                                     0x000FFFFFL
//CP_CE_IB2_OFFSET
#define CP_CE_IB2_OFFSET__IB2_OFFSET__SHIFT                                                                   0x0
#define CP_CE_IB2_OFFSET__IB2_OFFSET_MASK                                                                     0x000FFFFFL
//CP_CE_COUNTER
#define CP_CE_COUNTER__CONST_ENGINE_COUNT__SHIFT                                                              0x0
#define CP_CE_COUNTER__CONST_ENGINE_COUNT_MASK                                                                0xFFFFFFFFL
//CP_DMA_ME_CMD_ADDR_LO
#define CP_DMA_ME_CMD_ADDR_LO__RSVD__SHIFT                                                                    0x0
#define CP_DMA_ME_CMD_ADDR_LO__ADDR_LO__SHIFT                                                                 0x2
#define CP_DMA_ME_CMD_ADDR_LO__RSVD_MASK                                                                      0x00000003L
#define CP_DMA_ME_CMD_ADDR_LO__ADDR_LO_MASK                                                                   0xFFFFFFFCL
//CP_DMA_ME_CMD_ADDR_HI
#define CP_DMA_ME_CMD_ADDR_HI__ADDR_HI__SHIFT                                                                 0x0
#define CP_DMA_ME_CMD_ADDR_HI__RSVD__SHIFT                                                                    0x10
#define CP_DMA_ME_CMD_ADDR_HI__ADDR_HI_MASK                                                                   0x0000FFFFL
#define CP_DMA_ME_CMD_ADDR_HI__RSVD_MASK                                                                      0xFFFF0000L
//CP_DMA_PFP_CMD_ADDR_LO
#define CP_DMA_PFP_CMD_ADDR_LO__RSVD__SHIFT                                                                   0x0
#define CP_DMA_PFP_CMD_ADDR_LO__ADDR_LO__SHIFT                                                                0x2
#define CP_DMA_PFP_CMD_ADDR_LO__RSVD_MASK                                                                     0x00000003L
#define CP_DMA_PFP_CMD_ADDR_LO__ADDR_LO_MASK                                                                  0xFFFFFFFCL
//CP_DMA_PFP_CMD_ADDR_HI
#define CP_DMA_PFP_CMD_ADDR_HI__ADDR_HI__SHIFT                                                                0x0
#define CP_DMA_PFP_CMD_ADDR_HI__RSVD__SHIFT                                                                   0x10
#define CP_DMA_PFP_CMD_ADDR_HI__ADDR_HI_MASK                                                                  0x0000FFFFL
#define CP_DMA_PFP_CMD_ADDR_HI__RSVD_MASK                                                                     0xFFFF0000L
//CP_APPEND_CMD_ADDR_LO
#define CP_APPEND_CMD_ADDR_LO__RSVD__SHIFT                                                                    0x0
#define CP_APPEND_CMD_ADDR_LO__ADDR_LO__SHIFT                                                                 0x2
#define CP_APPEND_CMD_ADDR_LO__RSVD_MASK                                                                      0x00000003L
#define CP_APPEND_CMD_ADDR_LO__ADDR_LO_MASK                                                                   0xFFFFFFFCL
//CP_APPEND_CMD_ADDR_HI
#define CP_APPEND_CMD_ADDR_HI__ADDR_HI__SHIFT                                                                 0x0
#define CP_APPEND_CMD_ADDR_HI__RSVD__SHIFT                                                                    0x10
#define CP_APPEND_CMD_ADDR_HI__ADDR_HI_MASK                                                                   0x0000FFFFL
#define CP_APPEND_CMD_ADDR_HI__RSVD_MASK                                                                      0xFFFF0000L
//UCONFIG_RESERVED_REG0
#define UCONFIG_RESERVED_REG0__DATA__SHIFT                                                                    0x0
#define UCONFIG_RESERVED_REG0__DATA_MASK                                                                      0xFFFFFFFFL
//UCONFIG_RESERVED_REG1
#define UCONFIG_RESERVED_REG1__DATA__SHIFT                                                                    0x0
#define UCONFIG_RESERVED_REG1__DATA_MASK                                                                      0xFFFFFFFFL
//CP_CE_ATOMIC_PREOP_LO
#define CP_CE_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT                                                         0x0
#define CP_CE_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK                                                           0xFFFFFFFFL
//CP_CE_ATOMIC_PREOP_HI
#define CP_CE_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT                                                         0x0
#define CP_CE_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK                                                           0xFFFFFFFFL
//CP_CE_GDS_ATOMIC0_PREOP_LO
#define CP_CE_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT                                               0x0
#define CP_CE_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK                                                 0xFFFFFFFFL
//CP_CE_GDS_ATOMIC0_PREOP_HI
#define CP_CE_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT                                               0x0
#define CP_CE_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK                                                 0xFFFFFFFFL
//CP_CE_GDS_ATOMIC1_PREOP_LO
#define CP_CE_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT                                               0x0
#define CP_CE_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK                                                 0xFFFFFFFFL
//CP_CE_GDS_ATOMIC1_PREOP_HI
#define CP_CE_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT                                               0x0
#define CP_CE_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK                                                 0xFFFFFFFFL
//CP_CE_INIT_CMD_BUFSZ
#define CP_CE_INIT_CMD_BUFSZ__INIT_CMD_REQSZ__SHIFT                                                           0x0
#define CP_CE_INIT_CMD_BUFSZ__INIT_CMD_REQSZ_MASK                                                             0x00000FFFL
//CP_CE_IB1_CMD_BUFSZ
#define CP_CE_IB1_CMD_BUFSZ__IB1_CMD_REQSZ__SHIFT                                                             0x0
#define CP_CE_IB1_CMD_BUFSZ__IB1_CMD_REQSZ_MASK                                                               0x000FFFFFL
//CP_CE_IB2_CMD_BUFSZ
#define CP_CE_IB2_CMD_BUFSZ__IB2_CMD_REQSZ__SHIFT                                                             0x0
#define CP_CE_IB2_CMD_BUFSZ__IB2_CMD_REQSZ_MASK                                                               0x000FFFFFL
//CP_IB2_CMD_BUFSZ
#define CP_IB2_CMD_BUFSZ__IB2_CMD_REQSZ__SHIFT                                                                0x0
#define CP_IB2_CMD_BUFSZ__IB2_CMD_REQSZ_MASK                                                                  0x000FFFFFL
//CP_ST_CMD_BUFSZ
#define CP_ST_CMD_BUFSZ__ST_CMD_REQSZ__SHIFT                                                                  0x0
#define CP_ST_CMD_BUFSZ__ST_CMD_REQSZ_MASK                                                                    0x000FFFFFL
//CP_CE_INIT_BASE_LO
#define CP_CE_INIT_BASE_LO__INIT_BASE_LO__SHIFT                                                               0x5
#define CP_CE_INIT_BASE_LO__INIT_BASE_LO_MASK                                                                 0xFFFFFFE0L
//CP_CE_INIT_BASE_HI
#define CP_CE_INIT_BASE_HI__INIT_BASE_HI__SHIFT                                                               0x0
#define CP_CE_INIT_BASE_HI__INIT_BASE_HI_MASK                                                                 0x0000FFFFL
//CP_CE_INIT_BUFSZ
#define CP_CE_INIT_BUFSZ__INIT_BUFSZ__SHIFT                                                                   0x0
#define CP_CE_INIT_BUFSZ__INIT_BUFSZ_MASK                                                                     0x00000FFFL
//CP_CE_IB1_BASE_LO
#define CP_CE_IB1_BASE_LO__IB1_BASE_LO__SHIFT                                                                 0x2
#define CP_CE_IB1_BASE_LO__IB1_BASE_LO_MASK                                                                   0xFFFFFFFCL
//CP_CE_IB1_BASE_HI
#define CP_CE_IB1_BASE_HI__IB1_BASE_HI__SHIFT                                                                 0x0
#define CP_CE_IB1_BASE_HI__IB1_BASE_HI_MASK                                                                   0x0000FFFFL
//CP_CE_IB1_BUFSZ
#define CP_CE_IB1_BUFSZ__IB1_BUFSZ__SHIFT                                                                     0x0
#define CP_CE_IB1_BUFSZ__IB1_BUFSZ_MASK                                                                       0x000FFFFFL
//CP_CE_IB2_BASE_LO
#define CP_CE_IB2_BASE_LO__IB2_BASE_LO__SHIFT                                                                 0x2
#define CP_CE_IB2_BASE_LO__IB2_BASE_LO_MASK                                                                   0xFFFFFFFCL
//CP_CE_IB2_BASE_HI
#define CP_CE_IB2_BASE_HI__IB2_BASE_HI__SHIFT                                                                 0x0
#define CP_CE_IB2_BASE_HI__IB2_BASE_HI_MASK                                                                   0x0000FFFFL
//CP_CE_IB2_BUFSZ
#define CP_CE_IB2_BUFSZ__IB2_BUFSZ__SHIFT                                                                     0x0
#define CP_CE_IB2_BUFSZ__IB2_BUFSZ_MASK                                                                       0x000FFFFFL
//CP_IB2_BASE_LO
#define CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT                                                                    0x2
#define CP_IB2_BASE_LO__IB2_BASE_LO_MASK                                                                      0xFFFFFFFCL
//CP_IB2_BASE_HI
#define CP_IB2_BASE_HI__IB2_BASE_HI__SHIFT                                                                    0x0
#define CP_IB2_BASE_HI__IB2_BASE_HI_MASK                                                                      0x0000FFFFL
//CP_IB2_BUFSZ
#define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT                                                                        0x0
#define CP_IB2_BUFSZ__IB2_BUFSZ_MASK                                                                          0x000FFFFFL
//CP_ST_BASE_LO
#define CP_ST_BASE_LO__ST_BASE_LO__SHIFT                                                                      0x2
#define CP_ST_BASE_LO__ST_BASE_LO_MASK                                                                        0xFFFFFFFCL
//CP_ST_BASE_HI
#define CP_ST_BASE_HI__ST_BASE_HI__SHIFT                                                                      0x0
#define CP_ST_BASE_HI__ST_BASE_HI_MASK                                                                        0x0000FFFFL
//CP_ST_BUFSZ
#define CP_ST_BUFSZ__ST_BUFSZ__SHIFT                                                                          0x0
#define CP_ST_BUFSZ__ST_BUFSZ_MASK                                                                            0x000FFFFFL
//CP_EOP_DONE_EVENT_CNTL
#define CP_EOP_DONE_EVENT_CNTL__GCR_CNTL__SHIFT                                                               0xc
#define CP_EOP_DONE_EVENT_CNTL__CACHE_POLICY__SHIFT                                                           0x19
#define CP_EOP_DONE_EVENT_CNTL__EOP_VOLATILE__SHIFT                                                           0x1b
#define CP_EOP_DONE_EVENT_CNTL__EXECUTE__SHIFT                                                                0x1c
#define CP_EOP_DONE_EVENT_CNTL__GCR_CNTL_MASK                                                                 0x00FFF000L
#define CP_EOP_DONE_EVENT_CNTL__CACHE_POLICY_MASK                                                             0x06000000L
#define CP_EOP_DONE_EVENT_CNTL__EOP_VOLATILE_MASK                                                             0x08000000L
#define CP_EOP_DONE_EVENT_CNTL__EXECUTE_MASK                                                                  0x10000000L
//CP_EOP_DONE_DATA_CNTL
#define CP_EOP_DONE_DATA_CNTL__DST_SEL__SHIFT                                                                 0x10
#define CP_EOP_DONE_DATA_CNTL__ACTION_PIPE_ID__SHIFT                                                          0x14
#define CP_EOP_DONE_DATA_CNTL__ACTION_ID__SHIFT                                                               0x16
#define CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT                                                                 0x18
#define CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT                                                                0x1d
#define CP_EOP_DONE_DATA_CNTL__DST_SEL_MASK                                                                   0x00030000L
#define CP_EOP_DONE_DATA_CNTL__ACTION_PIPE_ID_MASK                                                            0x00300000L
#define CP_EOP_DONE_DATA_CNTL__ACTION_ID_MASK                                                                 0x00C00000L
#define CP_EOP_DONE_DATA_CNTL__INT_SEL_MASK                                                                   0x07000000L
#define CP_EOP_DONE_DATA_CNTL__DATA_SEL_MASK                                                                  0xE0000000L
//CP_EOP_DONE_CNTX_ID
#define CP_EOP_DONE_CNTX_ID__CNTX_ID__SHIFT                                                                   0x0
#define CP_EOP_DONE_CNTX_ID__CNTX_ID_MASK                                                                     0xFFFFFFFFL
//CP_DB_BASE_LO
#define CP_DB_BASE_LO__DB_BASE_LO__SHIFT                                                                      0x2
#define CP_DB_BASE_LO__DB_BASE_LO_MASK                                                                        0xFFFFFFFCL
//CP_DB_BASE_HI
#define CP_DB_BASE_HI__DB_BASE_HI__SHIFT                                                                      0x0
#define CP_DB_BASE_HI__DB_BASE_HI_MASK                                                                        0x0000FFFFL
//CP_DB_BUFSZ
#define CP_DB_BUFSZ__DB_BUFSZ__SHIFT                                                                          0x0
#define CP_DB_BUFSZ__DB_BUFSZ_MASK                                                                            0x000FFFFFL
//CP_DB_CMD_BUFSZ
#define CP_DB_CMD_BUFSZ__DB_CMD_REQSZ__SHIFT                                                                  0x0
#define CP_DB_CMD_BUFSZ__DB_CMD_REQSZ_MASK                                                                    0x000FFFFFL
//CP_CE_DB_BASE_LO
#define CP_CE_DB_BASE_LO__DB_BASE_LO__SHIFT                                                                   0x2
#define CP_CE_DB_BASE_LO__DB_BASE_LO_MASK                                                                     0xFFFFFFFCL
//CP_CE_DB_BASE_HI
#define CP_CE_DB_BASE_HI__DB_BASE_HI__SHIFT                                                                   0x0
#define CP_CE_DB_BASE_HI__DB_BASE_HI_MASK                                                                     0x0000FFFFL
//CP_CE_DB_BUFSZ
#define CP_CE_DB_BUFSZ__DB_BUFSZ__SHIFT                                                                       0x0
#define CP_CE_DB_BUFSZ__DB_BUFSZ_MASK                                                                         0x000FFFFFL
//CP_CE_DB_CMD_BUFSZ
#define CP_CE_DB_CMD_BUFSZ__DB_CMD_REQSZ__SHIFT                                                               0x0
#define CP_CE_DB_CMD_BUFSZ__DB_CMD_REQSZ_MASK                                                                 0x000FFFFFL
//CP_PFP_COMPLETION_STATUS
#define CP_PFP_COMPLETION_STATUS__STATUS__SHIFT                                                               0x0
#define CP_PFP_COMPLETION_STATUS__STATUS_MASK                                                                 0x00000003L
//CP_CE_COMPLETION_STATUS
#define CP_CE_COMPLETION_STATUS__STATUS__SHIFT                                                                0x0
#define CP_CE_COMPLETION_STATUS__STATUS_MASK                                                                  0x00000003L
//CP_PRED_NOT_VISIBLE
#define CP_PRED_NOT_VISIBLE__NOT_VISIBLE__SHIFT                                                               0x0
#define CP_PRED_NOT_VISIBLE__NOT_VISIBLE_MASK                                                                 0x00000001L
//CP_PFP_METADATA_BASE_ADDR
#define CP_PFP_METADATA_BASE_ADDR__ADDR_LO__SHIFT                                                             0x0
#define CP_PFP_METADATA_BASE_ADDR__ADDR_LO_MASK                                                               0xFFFFFFFFL
//CP_PFP_METADATA_BASE_ADDR_HI
#define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT                                                          0x0
#define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI_MASK                                                            0x0000FFFFL
//CP_CE_METADATA_BASE_ADDR
#define CP_CE_METADATA_BASE_ADDR__ADDR_LO__SHIFT                                                              0x0
#define CP_CE_METADATA_BASE_ADDR__ADDR_LO_MASK                                                                0xFFFFFFFFL
//CP_CE_METADATA_BASE_ADDR_HI
#define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT                                                           0x0
#define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI_MASK                                                             0x0000FFFFL
//CP_DRAW_INDX_INDR_ADDR
#define CP_DRAW_INDX_INDR_ADDR__ADDR_LO__SHIFT                                                                0x0
#define CP_DRAW_INDX_INDR_ADDR__ADDR_LO_MASK                                                                  0xFFFFFFFFL
//CP_DRAW_INDX_INDR_ADDR_HI
#define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI__SHIFT                                                             0x0
#define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI_MASK                                                               0x0000FFFFL
//CP_DISPATCH_INDR_ADDR
#define CP_DISPATCH_INDR_ADDR__ADDR_LO__SHIFT                                                                 0x0
#define CP_DISPATCH_INDR_ADDR__ADDR_LO_MASK                                                                   0xFFFFFFFFL
//CP_DISPATCH_INDR_ADDR_HI
#define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI__SHIFT                                                              0x0
#define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI_MASK                                                                0x0000FFFFL
//CP_INDEX_BASE_ADDR
#define CP_INDEX_BASE_ADDR__ADDR_LO__SHIFT                                                                    0x0
#define CP_INDEX_BASE_ADDR__ADDR_LO_MASK                                                                      0xFFFFFFFFL
//CP_INDEX_BASE_ADDR_HI
#define CP_INDEX_BASE_ADDR_HI__ADDR_HI__SHIFT                                                                 0x0
#define CP_INDEX_BASE_ADDR_HI__ADDR_HI_MASK                                                                   0x0000FFFFL
//CP_INDEX_TYPE
#define CP_INDEX_TYPE__INDEX_TYPE__SHIFT                                                                      0x0
#define CP_INDEX_TYPE__INDEX_TYPE_MASK                                                                        0x00000003L
//CP_GDS_BKUP_ADDR
#define CP_GDS_BKUP_ADDR__ADDR_LO__SHIFT                                                                      0x0
#define CP_GDS_BKUP_ADDR__ADDR_LO_MASK                                                                        0xFFFFFFFFL
//CP_GDS_BKUP_ADDR_HI
#define CP_GDS_BKUP_ADDR_HI__ADDR_HI__SHIFT                                                                   0x0
#define CP_GDS_BKUP_ADDR_HI__ADDR_HI_MASK                                                                     0x0000FFFFL
//CP_SAMPLE_STATUS
#define CP_SAMPLE_STATUS__Z_PASS_ACITVE__SHIFT                                                                0x0
#define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE__SHIFT                                                             0x1
#define CP_SAMPLE_STATUS__PIPELINE_ACTIVE__SHIFT                                                              0x2
#define CP_SAMPLE_STATUS__STIPPLE_ACTIVE__SHIFT                                                               0x3
#define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE__SHIFT                                                           0x4
#define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE__SHIFT                                                            0x5
#define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE__SHIFT                                                         0x6
#define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE__SHIFT                                                         0x7
#define CP_SAMPLE_STATUS__Z_PASS_ACITVE_MASK                                                                  0x00000001L
#define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE_MASK                                                               0x00000002L
#define CP_SAMPLE_STATUS__PIPELINE_ACTIVE_MASK                                                                0x00000004L
#define CP_SAMPLE_STATUS__STIPPLE_ACTIVE_MASK                                                                 0x00000008L
#define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE_MASK                                                             0x00000010L
#define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE_MASK                                                              0x00000020L
#define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE_MASK                                                           0x00000040L
#define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE_MASK                                                           0x00000080L
//CP_ME_COHER_CNTL
#define CP_ME_COHER_CNTL__DEST_BASE_0_ENA__SHIFT                                                              0x0
#define CP_ME_COHER_CNTL__DEST_BASE_1_ENA__SHIFT                                                              0x1
#define CP_ME_COHER_CNTL__CB0_DEST_BASE_ENA__SHIFT                                                            0x6
#define CP_ME_COHER_CNTL__CB1_DEST_BASE_ENA__SHIFT                                                            0x7
#define CP_ME_COHER_CNTL__CB2_DEST_BASE_ENA__SHIFT                                                            0x8
#define CP_ME_COHER_CNTL__CB3_DEST_BASE_ENA__SHIFT                                                            0x9
#define CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT                                                            0xa
#define CP_ME_COHER_CNTL__CB5_DEST_BASE_ENA__SHIFT                                                            0xb
#define CP_ME_COHER_CNTL__CB6_DEST_BASE_ENA__SHIFT                                                            0xc
#define CP_ME_COHER_CNTL__CB7_DEST_BASE_ENA__SHIFT                                                            0xd
#define CP_ME_COHER_CNTL__DB_DEST_BASE_ENA__SHIFT                                                             0xe
#define CP_ME_COHER_CNTL__DEST_BASE_2_ENA__SHIFT                                                              0x13
#define CP_ME_COHER_CNTL__DEST_BASE_3_ENA__SHIFT                                                              0x15
#define CP_ME_COHER_CNTL__DEST_BASE_0_ENA_MASK                                                                0x00000001L
#define CP_ME_COHER_CNTL__DEST_BASE_1_ENA_MASK                                                                0x00000002L
#define CP_ME_COHER_CNTL__CB0_DEST_BASE_ENA_MASK                                                              0x00000040L
#define CP_ME_COHER_CNTL__CB1_DEST_BASE_ENA_MASK                                                              0x00000080L
#define CP_ME_COHER_CNTL__CB2_DEST_BASE_ENA_MASK                                                              0x00000100L
#define CP_ME_COHER_CNTL__CB3_DEST_BASE_ENA_MASK                                                              0x00000200L
#define CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA_MASK                                                              0x00000400L
#define CP_ME_COHER_CNTL__CB5_DEST_BASE_ENA_MASK                                                              0x00000800L
#define CP_ME_COHER_CNTL__CB6_DEST_BASE_ENA_MASK                                                              0x00001000L
#define CP_ME_COHER_CNTL__CB7_DEST_BASE_ENA_MASK                                                              0x00002000L
#define CP_ME_COHER_CNTL__DB_DEST_BASE_ENA_MASK                                                               0x00004000L
#define CP_ME_COHER_CNTL__DEST_BASE_2_ENA_MASK                                                                0x00080000L
#define CP_ME_COHER_CNTL__DEST_BASE_3_ENA_MASK                                                                0x00200000L
//CP_ME_COHER_SIZE
#define CP_ME_COHER_SIZE__COHER_SIZE_256B__SHIFT                                                              0x0
#define CP_ME_COHER_SIZE__COHER_SIZE_256B_MASK                                                                0xFFFFFFFFL
//CP_ME_COHER_SIZE_HI
#define CP_ME_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT                                                        0x0
#define CP_ME_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK                                                          0x000000FFL
//CP_ME_COHER_BASE
#define CP_ME_COHER_BASE__COHER_BASE_256B__SHIFT                                                              0x0
#define CP_ME_COHER_BASE__COHER_BASE_256B_MASK                                                                0xFFFFFFFFL
//CP_ME_COHER_BASE_HI
#define CP_ME_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT                                                        0x0
#define CP_ME_COHER_BASE_HI__COHER_BASE_HI_256B_MASK                                                          0x000000FFL
//CP_ME_COHER_STATUS
#define CP_ME_COHER_STATUS__MATCHING_GFX_CNTX__SHIFT                                                          0x0
#define CP_ME_COHER_STATUS__STATUS__SHIFT                                                                     0x1f
#define CP_ME_COHER_STATUS__MATCHING_GFX_CNTX_MASK                                                            0x000000FFL
#define CP_ME_COHER_STATUS__STATUS_MASK                                                                       0x80000000L
//RLC_GPM_PERF_COUNT_0
#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL__SHIFT                                                              0x0
#define RLC_GPM_PERF_COUNT_0__SE_INDEX__SHIFT                                                                 0x4
#define RLC_GPM_PERF_COUNT_0__SA_INDEX__SHIFT                                                                 0x8
#define RLC_GPM_PERF_COUNT_0__WGP_INDEX__SHIFT                                                                0xc
#define RLC_GPM_PERF_COUNT_0__EVENT_SEL__SHIFT                                                                0x10
#define RLC_GPM_PERF_COUNT_0__UNUSED__SHIFT                                                                   0x12
#define RLC_GPM_PERF_COUNT_0__ENABLE__SHIFT                                                                   0x14
#define RLC_GPM_PERF_COUNT_0__RESERVED__SHIFT                                                                 0x15
#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL_MASK                                                                0x0000000FL
#define RLC_GPM_PERF_COUNT_0__SE_INDEX_MASK                                                                   0x000000F0L
#define RLC_GPM_PERF_COUNT_0__SA_INDEX_MASK                                                                   0x00000F00L
#define RLC_GPM_PERF_COUNT_0__WGP_INDEX_MASK                                                                  0x0000F000L
#define RLC_GPM_PERF_COUNT_0__EVENT_SEL_MASK                                                                  0x00030000L
#define RLC_GPM_PERF_COUNT_0__UNUSED_MASK                                                                     0x000C0000L
#define RLC_GPM_PERF_COUNT_0__ENABLE_MASK                                                                     0x00100000L
#define RLC_GPM_PERF_COUNT_0__RESERVED_MASK                                                                   0xFFE00000L
//RLC_GPM_PERF_COUNT_1
#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL__SHIFT                                                              0x0
#define RLC_GPM_PERF_COUNT_1__SE_INDEX__SHIFT                                                                 0x4
#define RLC_GPM_PERF_COUNT_1__SA_INDEX__SHIFT                                                                 0x8
#define RLC_GPM_PERF_COUNT_1__WGP_INDEX__SHIFT                                                                0xc
#define RLC_GPM_PERF_COUNT_1__EVENT_SEL__SHIFT                                                                0x10
#define RLC_GPM_PERF_COUNT_1__UNUSED__SHIFT                                                                   0x12
#define RLC_GPM_PERF_COUNT_1__ENABLE__SHIFT                                                                   0x14
#define RLC_GPM_PERF_COUNT_1__RESERVED__SHIFT                                                                 0x15
#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL_MASK                                                                0x0000000FL
#define RLC_GPM_PERF_COUNT_1__SE_INDEX_MASK                                                                   0x000000F0L
#define RLC_GPM_PERF_COUNT_1__SA_INDEX_MASK                                                                   0x00000F00L
#define RLC_GPM_PERF_COUNT_1__WGP_INDEX_MASK                                                                  0x0000F000L
#define RLC_GPM_PERF_COUNT_1__EVENT_SEL_MASK                                                                  0x00030000L
#define RLC_GPM_PERF_COUNT_1__UNUSED_MASK                                                                     0x000C0000L
#define RLC_GPM_PERF_COUNT_1__ENABLE_MASK                                                                     0x00100000L
#define RLC_GPM_PERF_COUNT_1__RESERVED_MASK                                                                   0xFFE00000L
//GRBM_GFX_INDEX
#define GRBM_GFX_INDEX__INSTANCE_INDEX__SHIFT                                                                 0x0
#define GRBM_GFX_INDEX__SA_INDEX__SHIFT                                                                       0x8
#define GRBM_GFX_INDEX__SE_INDEX__SHIFT                                                                       0x10
#define GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT                                                            0x1d
#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT                                                      0x1e
#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT                                                            0x1f
#define GRBM_GFX_INDEX__INSTANCE_INDEX_MASK                                                                   0x000000FFL
#define GRBM_GFX_INDEX__SA_INDEX_MASK                                                                         0x0000FF00L
#define GRBM_GFX_INDEX__SE_INDEX_MASK                                                                         0x00FF0000L
#define GRBM_GFX_INDEX__SA_BROADCAST_WRITES_MASK                                                              0x20000000L
#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK                                                        0x40000000L
#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK                                                              0x80000000L
//VGT_ESGS_RING_SIZE_UMD
#define VGT_ESGS_RING_SIZE_UMD__MEM_SIZE__SHIFT                                                               0x0
#define VGT_ESGS_RING_SIZE_UMD__MEM_SIZE_MASK                                                                 0xFFFFFFFFL
//VGT_GSVS_RING_SIZE_UMD
#define VGT_GSVS_RING_SIZE_UMD__MEM_SIZE__SHIFT                                                               0x0
#define VGT_GSVS_RING_SIZE_UMD__MEM_SIZE_MASK                                                                 0xFFFFFFFFL
//VGT_PRIMITIVE_TYPE
#define VGT_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT                                                                  0x0
#define VGT_PRIMITIVE_TYPE__PRIM_TYPE_MASK                                                                    0x0000003FL
//VGT_INDEX_TYPE
#define VGT_INDEX_TYPE__INDEX_TYPE__SHIFT                                                                     0x0
#define VGT_INDEX_TYPE__DISABLE_INSTANCE_PACKING__SHIFT                                                       0xe
#define VGT_INDEX_TYPE__INDEX_TYPE_MASK                                                                       0x00000003L
#define VGT_INDEX_TYPE__DISABLE_INSTANCE_PACKING_MASK                                                         0x00004000L
//VGT_STRMOUT_BUFFER_FILLED_SIZE_0
#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE__SHIFT                                                         0x0
#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE_MASK                                                           0xFFFFFFFFL
//VGT_STRMOUT_BUFFER_FILLED_SIZE_1
#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE__SHIFT                                                         0x0
#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE_MASK                                                           0xFFFFFFFFL
//VGT_STRMOUT_BUFFER_FILLED_SIZE_2
#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE__SHIFT                                                         0x0
#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE_MASK                                                           0xFFFFFFFFL
//VGT_STRMOUT_BUFFER_FILLED_SIZE_3
#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE__SHIFT                                                         0x0
#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE_MASK                                                           0xFFFFFFFFL
//GE_MIN_VTX_INDX
#define GE_MIN_VTX_INDX__MIN_INDX__SHIFT                                                                      0x0
#define GE_MIN_VTX_INDX__MIN_INDX_MASK                                                                        0xFFFFFFFFL
//GE_INDX_OFFSET
#define GE_INDX_OFFSET__INDX_OFFSET__SHIFT                                                                    0x0
#define GE_INDX_OFFSET__INDX_OFFSET_MASK                                                                      0xFFFFFFFFL
//GE_MULTI_PRIM_IB_RESET_EN
#define GE_MULTI_PRIM_IB_RESET_EN__RESET_EN__SHIFT                                                            0x0
#define GE_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS__SHIFT                                                      0x1
#define GE_MULTI_PRIM_IB_RESET_EN__RESET_EN_MASK                                                              0x00000001L
#define GE_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS_MASK                                                        0x00000002L
//VGT_NUM_INDICES
#define VGT_NUM_INDICES__NUM_INDICES__SHIFT                                                                   0x0
#define VGT_NUM_INDICES__NUM_INDICES_MASK                                                                     0xFFFFFFFFL
//VGT_NUM_INSTANCES
#define VGT_NUM_INSTANCES__NUM_INSTANCES__SHIFT                                                               0x0
#define VGT_NUM_INSTANCES__NUM_INSTANCES_MASK                                                                 0xFFFFFFFFL
//VGT_TF_RING_SIZE_UMD
#define VGT_TF_RING_SIZE_UMD__SIZE__SHIFT                                                                     0x0
#define VGT_TF_RING_SIZE_UMD__SIZE_MASK                                                                       0x0000FFFFL
//VGT_HS_OFFCHIP_PARAM_UMD
#define VGT_HS_OFFCHIP_PARAM_UMD__OFFCHIP_BUFFERING__SHIFT                                                    0x0
#define VGT_HS_OFFCHIP_PARAM_UMD__OFFCHIP_GRANULARITY__SHIFT                                                  0xa
#define VGT_HS_OFFCHIP_PARAM_UMD__OFFCHIP_BUFFERING_MASK                                                      0x000003FFL
#define VGT_HS_OFFCHIP_PARAM_UMD__OFFCHIP_GRANULARITY_MASK                                                    0x00000C00L
//VGT_TF_MEMORY_BASE_UMD
#define VGT_TF_MEMORY_BASE_UMD__BASE__SHIFT                                                                   0x0
#define VGT_TF_MEMORY_BASE_UMD__BASE_MASK                                                                     0xFFFFFFFFL
//GE_DMA_FIRST_INDEX
#define GE_DMA_FIRST_INDEX__FIRST_INDEX__SHIFT                                                                0x0
#define GE_DMA_FIRST_INDEX__FIRST_INDEX_MASK                                                                  0xFFFFFFFFL
//WD_POS_BUF_BASE
#define WD_POS_BUF_BASE__BASE__SHIFT                                                                          0x0
#define WD_POS_BUF_BASE__BASE_MASK                                                                            0xFFFFFFFFL
//WD_POS_BUF_BASE_HI
#define WD_POS_BUF_BASE_HI__BASE_HI__SHIFT                                                                    0x0
#define WD_POS_BUF_BASE_HI__BASE_HI_MASK                                                                      0x000000FFL
//WD_CNTL_SB_BUF_BASE
#define WD_CNTL_SB_BUF_BASE__BASE__SHIFT                                                                      0x0
#define WD_CNTL_SB_BUF_BASE__BASE_MASK                                                                        0xFFFFFFFFL
//WD_CNTL_SB_BUF_BASE_HI
#define WD_CNTL_SB_BUF_BASE_HI__BASE_HI__SHIFT                                                                0x0
#define WD_CNTL_SB_BUF_BASE_HI__BASE_HI_MASK                                                                  0x000000FFL
//WD_INDEX_BUF_BASE
#define WD_INDEX_BUF_BASE__BASE__SHIFT                                                                        0x0
#define WD_INDEX_BUF_BASE__BASE_MASK                                                                          0xFFFFFFFFL
//WD_INDEX_BUF_BASE_HI
#define WD_INDEX_BUF_BASE_HI__BASE_HI__SHIFT                                                                  0x0
#define WD_INDEX_BUF_BASE_HI__BASE_HI_MASK                                                                    0x000000FFL
//IA_MULTI_VGT_PARAM_PIPED
#define IA_MULTI_VGT_PARAM_PIPED__PRIMGROUP_SIZE__SHIFT                                                       0x0
#define IA_MULTI_VGT_PARAM_PIPED__PARTIAL_VS_WAVE_ON__SHIFT                                                   0x10
#define IA_MULTI_VGT_PARAM_PIPED__SWITCH_ON_EOP__SHIFT                                                        0x11
#define IA_MULTI_VGT_PARAM_PIPED__PARTIAL_ES_WAVE_ON__SHIFT                                                   0x12
#define IA_MULTI_VGT_PARAM_PIPED__SWITCH_ON_EOI__SHIFT                                                        0x13
#define IA_MULTI_VGT_PARAM_PIPED__WD_SWITCH_ON_EOP__SHIFT                                                     0x14
#define IA_MULTI_VGT_PARAM_PIPED__EN_INST_OPT_BASIC__SHIFT                                                    0x15
#define IA_MULTI_VGT_PARAM_PIPED__EN_INST_OPT_ADV__SHIFT                                                      0x16
#define IA_MULTI_VGT_PARAM_PIPED__HW_USE_ONLY__SHIFT                                                          0x17
#define IA_MULTI_VGT_PARAM_PIPED__PRIMGROUP_SIZE_MASK                                                         0x0000FFFFL
#define IA_MULTI_VGT_PARAM_PIPED__PARTIAL_VS_WAVE_ON_MASK                                                     0x00010000L
#define IA_MULTI_VGT_PARAM_PIPED__SWITCH_ON_EOP_MASK                                                          0x00020000L
#define IA_MULTI_VGT_PARAM_PIPED__PARTIAL_ES_WAVE_ON_MASK                                                     0x00040000L
#define IA_MULTI_VGT_PARAM_PIPED__SWITCH_ON_EOI_MASK                                                          0x00080000L
#define IA_MULTI_VGT_PARAM_PIPED__WD_SWITCH_ON_EOP_MASK                                                       0x00100000L
#define IA_MULTI_VGT_PARAM_PIPED__EN_INST_OPT_BASIC_MASK                                                      0x00200000L
#define IA_MULTI_VGT_PARAM_PIPED__EN_INST_OPT_ADV_MASK                                                        0x00400000L
#define IA_MULTI_VGT_PARAM_PIPED__HW_USE_ONLY_MASK                                                            0x00800000L
//GE_MAX_VTX_INDX
#define GE_MAX_VTX_INDX__MAX_INDX__SHIFT                                                                      0x0
#define GE_MAX_VTX_INDX__MAX_INDX_MASK                                                                        0xFFFFFFFFL
//VGT_INSTANCE_BASE_ID
#define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID__SHIFT                                                         0x0
#define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID_MASK                                                           0xFFFFFFFFL
//GE_CNTL
#define GE_CNTL__PRIM_GRP_SIZE__SHIFT                                                                         0x0
#define GE_CNTL__VERT_GRP_SIZE__SHIFT                                                                         0x9
#define GE_CNTL__BREAK_WAVE_AT_EOI__SHIFT                                                                     0x12
#define GE_CNTL__PACKET_TO_ONE_PA__SHIFT                                                                      0x13
#define GE_CNTL__PRIM_GRP_SIZE_MASK                                                                           0x000001FFL
#define GE_CNTL__VERT_GRP_SIZE_MASK                                                                           0x0003FE00L
#define GE_CNTL__BREAK_WAVE_AT_EOI_MASK                                                                       0x00040000L
#define GE_CNTL__PACKET_TO_ONE_PA_MASK                                                                        0x00080000L
//GE_USER_VGPR1
#define GE_USER_VGPR1__DATA__SHIFT                                                                            0x0
#define GE_USER_VGPR1__DATA_MASK                                                                              0xFFFFFFFFL
//GE_USER_VGPR2
#define GE_USER_VGPR2__DATA__SHIFT                                                                            0x0
#define GE_USER_VGPR2__DATA_MASK                                                                              0xFFFFFFFFL
//GE_USER_VGPR3
#define GE_USER_VGPR3__DATA__SHIFT                                                                            0x0
#define GE_USER_VGPR3__DATA_MASK                                                                              0xFFFFFFFFL
//GE_STEREO_CNTL
#define GE_STEREO_CNTL__RT_SLICE__SHIFT                                                                       0x0
#define GE_STEREO_CNTL__VIEWPORT__SHIFT                                                                       0x3
#define GE_STEREO_CNTL__EN_STEREO__SHIFT                                                                      0x8
#define GE_STEREO_CNTL__RT_SLICE_MASK                                                                         0x00000007L
#define GE_STEREO_CNTL__VIEWPORT_MASK                                                                         0x00000078L
#define GE_STEREO_CNTL__EN_STEREO_MASK                                                                        0x00000100L
//GE_PC_ALLOC
#define GE_PC_ALLOC__OVERSUB_EN__SHIFT                                                                        0x0
#define GE_PC_ALLOC__NUM_PC_LINES__SHIFT                                                                      0x1
#define GE_PC_ALLOC__OVERSUB_EN_MASK                                                                          0x00000001L
#define GE_PC_ALLOC__NUM_PC_LINES_MASK                                                                        0x000007FEL
//VGT_TF_MEMORY_BASE_HI_UMD
#define VGT_TF_MEMORY_BASE_HI_UMD__BASE_HI__SHIFT                                                             0x0
#define VGT_TF_MEMORY_BASE_HI_UMD__BASE_HI_MASK                                                               0x000000FFL
//GE_USER_VGPR_EN
#define GE_USER_VGPR_EN__EN_USER_VGPR1__SHIFT                                                                 0x0
#define GE_USER_VGPR_EN__EN_USER_VGPR2__SHIFT                                                                 0x1
#define GE_USER_VGPR_EN__EN_USER_VGPR3__SHIFT                                                                 0x2
#define GE_USER_VGPR_EN__EN_USER_VGPR1_MASK                                                                   0x00000001L
#define GE_USER_VGPR_EN__EN_USER_VGPR2_MASK                                                                   0x00000002L
#define GE_USER_VGPR_EN__EN_USER_VGPR3_MASK                                                                   0x00000004L
//PA_SU_LINE_STIPPLE_VALUE
#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE__SHIFT                                                   0x0
#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE_MASK                                                     0x00FFFFFFL
//PA_SC_LINE_STIPPLE_STATE
#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT                                                          0x0
#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT                                                        0x8
#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK                                                            0x0000000FL
#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK                                                          0x0000FF00L
//PA_SC_SCREEN_EXTENT_MIN_0
#define PA_SC_SCREEN_EXTENT_MIN_0__X__SHIFT                                                                   0x0
#define PA_SC_SCREEN_EXTENT_MIN_0__Y__SHIFT                                                                   0x10
#define PA_SC_SCREEN_EXTENT_MIN_0__X_MASK                                                                     0x0000FFFFL
#define PA_SC_SCREEN_EXTENT_MIN_0__Y_MASK                                                                     0xFFFF0000L
//PA_SC_SCREEN_EXTENT_MAX_0
#define PA_SC_SCREEN_EXTENT_MAX_0__X__SHIFT                                                                   0x0
#define PA_SC_SCREEN_EXTENT_MAX_0__Y__SHIFT                                                                   0x10
#define PA_SC_SCREEN_EXTENT_MAX_0__X_MASK                                                                     0x0000FFFFL
#define PA_SC_SCREEN_EXTENT_MAX_0__Y_MASK                                                                     0xFFFF0000L
//PA_SC_SCREEN_EXTENT_MIN_1
#define PA_SC_SCREEN_EXTENT_MIN_1__X__SHIFT                                                                   0x0
#define PA_SC_SCREEN_EXTENT_MIN_1__Y__SHIFT                                                                   0x10
#define PA_SC_SCREEN_EXTENT_MIN_1__X_MASK                                                                     0x0000FFFFL
#define PA_SC_SCREEN_EXTENT_MIN_1__Y_MASK                                                                     0xFFFF0000L
//PA_SC_SCREEN_EXTENT_MAX_1
#define PA_SC_SCREEN_EXTENT_MAX_1__X__SHIFT                                                                   0x0
#define PA_SC_SCREEN_EXTENT_MAX_1__Y__SHIFT                                                                   0x10
#define PA_SC_SCREEN_EXTENT_MAX_1__X_MASK                                                                     0x0000FFFFL
#define PA_SC_SCREEN_EXTENT_MAX_1__Y_MASK                                                                     0xFFFF0000L
//PA_SC_P3D_TRAP_SCREEN_HV_EN
#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT                                              0x0
#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT                                       0x1
#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK                                                0x00000001L
#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK                                         0x00000002L
//PA_SC_P3D_TRAP_SCREEN_H
#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD__SHIFT                                                               0x0
#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD_MASK                                                                 0x00003FFFL
//PA_SC_P3D_TRAP_SCREEN_V
#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD__SHIFT                                                               0x0
#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD_MASK                                                                 0x00003FFFL
//PA_SC_P3D_TRAP_SCREEN_OCCURRENCE
#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT                                                        0x0
#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK                                                          0x0000FFFFL
//PA_SC_P3D_TRAP_SCREEN_COUNT
#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT__SHIFT                                                             0x0
#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT_MASK                                                               0x0000FFFFL
//PA_SC_HP3D_TRAP_SCREEN_HV_EN
#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT                                             0x0
#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT                                      0x1
#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK                                               0x00000001L
#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK                                        0x00000002L
//PA_SC_HP3D_TRAP_SCREEN_H
#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD__SHIFT                                                              0x0
#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD_MASK                                                                0x00003FFFL
//PA_SC_HP3D_TRAP_SCREEN_V
#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD__SHIFT                                                              0x0
#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD_MASK                                                                0x00003FFFL
//PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE
#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT                                                       0x0
#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK                                                         0x0000FFFFL
//PA_SC_HP3D_TRAP_SCREEN_COUNT
#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT__SHIFT                                                            0x0
#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT_MASK                                                              0x0000FFFFL
//PA_SC_TRAP_SCREEN_HV_EN
#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT                                                  0x0
#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT                                           0x1
#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK                                                    0x00000001L
#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK                                             0x00000002L
//PA_SC_TRAP_SCREEN_H
#define PA_SC_TRAP_SCREEN_H__X_COORD__SHIFT                                                                   0x0
#define PA_SC_TRAP_SCREEN_H__X_COORD_MASK                                                                     0x00003FFFL
//PA_SC_TRAP_SCREEN_V
#define PA_SC_TRAP_SCREEN_V__Y_COORD__SHIFT                                                                   0x0
#define PA_SC_TRAP_SCREEN_V__Y_COORD_MASK                                                                     0x00003FFFL
//PA_SC_TRAP_SCREEN_OCCURRENCE
#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT                                                            0x0
#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT_MASK                                                              0x0000FFFFL
//PA_SC_TRAP_SCREEN_COUNT
#define PA_SC_TRAP_SCREEN_COUNT__COUNT__SHIFT                                                                 0x0
#define PA_SC_TRAP_SCREEN_COUNT__COUNT_MASK                                                                   0x0000FFFFL
//SQ_THREAD_TRACE_USERDATA_0
#define SQ_THREAD_TRACE_USERDATA_0__DATA__SHIFT                                                               0x0
#define SQ_THREAD_TRACE_USERDATA_0__DATA_MASK                                                                 0xFFFFFFFFL
//SQ_THREAD_TRACE_USERDATA_1
#define SQ_THREAD_TRACE_USERDATA_1__DATA__SHIFT                                                               0x0
#define SQ_THREAD_TRACE_USERDATA_1__DATA_MASK                                                                 0xFFFFFFFFL
//SQ_THREAD_TRACE_USERDATA_2
#define SQ_THREAD_TRACE_USERDATA_2__DATA__SHIFT                                                               0x0
#define SQ_THREAD_TRACE_USERDATA_2__DATA_MASK                                                                 0xFFFFFFFFL
//SQ_THREAD_TRACE_USERDATA_3
#define SQ_THREAD_TRACE_USERDATA_3__DATA__SHIFT                                                               0x0
#define SQ_THREAD_TRACE_USERDATA_3__DATA_MASK                                                                 0xFFFFFFFFL
//SQ_THREAD_TRACE_USERDATA_4
#define SQ_THREAD_TRACE_USERDATA_4__DATA__SHIFT                                                               0x0
#define SQ_THREAD_TRACE_USERDATA_4__DATA_MASK                                                                 0xFFFFFFFFL
//SQ_THREAD_TRACE_USERDATA_5
#define SQ_THREAD_TRACE_USERDATA_5__DATA__SHIFT                                                               0x0
#define SQ_THREAD_TRACE_USERDATA_5__DATA_MASK                                                                 0xFFFFFFFFL
//SQ_THREAD_TRACE_USERDATA_6
#define SQ_THREAD_TRACE_USERDATA_6__DATA__SHIFT                                                               0x0
#define SQ_THREAD_TRACE_USERDATA_6__DATA_MASK                                                                 0xFFFFFFFFL
//SQ_THREAD_TRACE_USERDATA_7
#define SQ_THREAD_TRACE_USERDATA_7__DATA__SHIFT                                                               0x0
#define SQ_THREAD_TRACE_USERDATA_7__DATA_MASK                                                                 0xFFFFFFFFL
//SQC_CACHES
#define SQC_CACHES__TARGET_INST__SHIFT                                                                        0x0
#define SQC_CACHES__TARGET_DATA__SHIFT                                                                        0x1
#define SQC_CACHES__INVALIDATE__SHIFT                                                                         0x2
#define SQC_CACHES__COMPLETE__SHIFT                                                                           0x10
#define SQC_CACHES__L2_WB_POLICY__SHIFT                                                                       0x11
#define SQC_CACHES__TARGET_INST_MASK                                                                          0x00000001L
#define SQC_CACHES__TARGET_DATA_MASK                                                                          0x00000002L
#define SQC_CACHES__INVALIDATE_MASK                                                                           0x00000004L
#define SQC_CACHES__COMPLETE_MASK                                                                             0x00010000L
#define SQC_CACHES__L2_WB_POLICY_MASK                                                                         0x00060000L
//TA_CS_BC_BASE_ADDR
#define TA_CS_BC_BASE_ADDR__ADDRESS__SHIFT                                                                    0x0
#define TA_CS_BC_BASE_ADDR__ADDRESS_MASK                                                                      0xFFFFFFFFL
//TA_CS_BC_BASE_ADDR_HI
#define TA_CS_BC_BASE_ADDR_HI__ADDRESS__SHIFT                                                                 0x0
#define TA_CS_BC_BASE_ADDR_HI__ADDRESS_MASK                                                                   0x000000FFL
//DB_OCCLUSION_COUNT0_LOW
#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW__SHIFT                                                             0x0
#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW_MASK                                                               0xFFFFFFFFL
//DB_OCCLUSION_COUNT0_HI
#define DB_OCCLUSION_COUNT0_HI__COUNT_HI__SHIFT                                                               0x0
#define DB_OCCLUSION_COUNT0_HI__COUNT_HI_MASK                                                                 0x7FFFFFFFL
//DB_OCCLUSION_COUNT1_LOW
#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW__SHIFT                                                             0x0
#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW_MASK                                                               0xFFFFFFFFL
//DB_OCCLUSION_COUNT1_HI
#define DB_OCCLUSION_COUNT1_HI__COUNT_HI__SHIFT                                                               0x0
#define DB_OCCLUSION_COUNT1_HI__COUNT_HI_MASK                                                                 0x7FFFFFFFL
//DB_OCCLUSION_COUNT2_LOW
#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW__SHIFT                                                             0x0
#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW_MASK                                                               0xFFFFFFFFL
//DB_OCCLUSION_COUNT2_HI
#define DB_OCCLUSION_COUNT2_HI__COUNT_HI__SHIFT                                                               0x0
#define DB_OCCLUSION_COUNT2_HI__COUNT_HI_MASK                                                                 0x7FFFFFFFL
//DB_OCCLUSION_COUNT3_LOW
#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW__SHIFT                                                             0x0
#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW_MASK                                                               0xFFFFFFFFL
//DB_OCCLUSION_COUNT3_HI
#define DB_OCCLUSION_COUNT3_HI__COUNT_HI__SHIFT                                                               0x0
#define DB_OCCLUSION_COUNT3_HI__COUNT_HI_MASK                                                                 0x7FFFFFFFL
//DB_ZPASS_COUNT_LOW
#define DB_ZPASS_COUNT_LOW__COUNT_LOW__SHIFT                                                                  0x0
#define DB_ZPASS_COUNT_LOW__COUNT_LOW_MASK                                                                    0xFFFFFFFFL
//DB_ZPASS_COUNT_HI
#define DB_ZPASS_COUNT_HI__COUNT_HI__SHIFT                                                                    0x0
#define DB_ZPASS_COUNT_HI__COUNT_HI_MASK                                                                      0x7FFFFFFFL
//GDS_RD_ADDR
#define GDS_RD_ADDR__READ_ADDR__SHIFT                                                                         0x0
#define GDS_RD_ADDR__READ_ADDR_MASK                                                                           0xFFFFFFFFL
//GDS_RD_DATA
#define GDS_RD_DATA__READ_DATA__SHIFT                                                                         0x0
#define GDS_RD_DATA__READ_DATA_MASK                                                                           0xFFFFFFFFL
//GDS_RD_BURST_ADDR
#define GDS_RD_BURST_ADDR__BURST_ADDR__SHIFT                                                                  0x0
#define GDS_RD_BURST_ADDR__BURST_ADDR_MASK                                                                    0xFFFFFFFFL
//GDS_RD_BURST_COUNT
#define GDS_RD_BURST_COUNT__BURST_COUNT__SHIFT                                                                0x0
#define GDS_RD_BURST_COUNT__BURST_COUNT_MASK                                                                  0xFFFFFFFFL
//GDS_RD_BURST_DATA
#define GDS_RD_BURST_DATA__BURST_DATA__SHIFT                                                                  0x0
#define GDS_RD_BURST_DATA__BURST_DATA_MASK                                                                    0xFFFFFFFFL
//GDS_WR_ADDR
#define GDS_WR_ADDR__WRITE_ADDR__SHIFT                                                                        0x0
#define GDS_WR_ADDR__WRITE_ADDR_MASK                                                                          0xFFFFFFFFL
//GDS_WR_DATA
#define GDS_WR_DATA__WRITE_DATA__SHIFT                                                                        0x0
#define GDS_WR_DATA__WRITE_DATA_MASK                                                                          0xFFFFFFFFL
//GDS_WR_BURST_ADDR
#define GDS_WR_BURST_ADDR__WRITE_ADDR__SHIFT                                                                  0x0
#define GDS_WR_BURST_ADDR__WRITE_ADDR_MASK                                                                    0xFFFFFFFFL
//GDS_WR_BURST_DATA
#define GDS_WR_BURST_DATA__WRITE_DATA__SHIFT                                                                  0x0
#define GDS_WR_BURST_DATA__WRITE_DATA_MASK                                                                    0xFFFFFFFFL
//GDS_WRITE_COMPLETE
#define GDS_WRITE_COMPLETE__WRITE_COMPLETE__SHIFT                                                             0x0
#define GDS_WRITE_COMPLETE__WRITE_COMPLETE_MASK                                                               0xFFFFFFFFL
//GDS_ATOM_CNTL
#define GDS_ATOM_CNTL__AINC__SHIFT                                                                            0x0
#define GDS_ATOM_CNTL__UNUSED1__SHIFT                                                                         0x6
#define GDS_ATOM_CNTL__DMODE__SHIFT                                                                           0x8
#define GDS_ATOM_CNTL__UNUSED2__SHIFT                                                                         0xa
#define GDS_ATOM_CNTL__AINC_MASK                                                                              0x0000003FL
#define GDS_ATOM_CNTL__UNUSED1_MASK                                                                           0x000000C0L
#define GDS_ATOM_CNTL__DMODE_MASK                                                                             0x00000300L
#define GDS_ATOM_CNTL__UNUSED2_MASK                                                                           0xFFFFFC00L
//GDS_ATOM_COMPLETE
#define GDS_ATOM_COMPLETE__COMPLETE__SHIFT                                                                    0x0
#define GDS_ATOM_COMPLETE__UNUSED__SHIFT                                                                      0x1
#define GDS_ATOM_COMPLETE__COMPLETE_MASK                                                                      0x00000001L
#define GDS_ATOM_COMPLETE__UNUSED_MASK                                                                        0xFFFFFFFEL
//GDS_ATOM_BASE
#define GDS_ATOM_BASE__BASE__SHIFT                                                                            0x0
#define GDS_ATOM_BASE__UNUSED__SHIFT                                                                          0x10
#define GDS_ATOM_BASE__BASE_MASK                                                                              0x0000FFFFL
#define GDS_ATOM_BASE__UNUSED_MASK                                                                            0xFFFF0000L
//GDS_ATOM_SIZE
#define GDS_ATOM_SIZE__SIZE__SHIFT                                                                            0x0
#define GDS_ATOM_SIZE__UNUSED__SHIFT                                                                          0x10
#define GDS_ATOM_SIZE__SIZE_MASK                                                                              0x0000FFFFL
#define GDS_ATOM_SIZE__UNUSED_MASK                                                                            0xFFFF0000L
//GDS_ATOM_OFFSET0
#define GDS_ATOM_OFFSET0__OFFSET0__SHIFT                                                                      0x0
#define GDS_ATOM_OFFSET0__UNUSED__SHIFT                                                                       0x8
#define GDS_ATOM_OFFSET0__OFFSET0_MASK                                                                        0x000000FFL
#define GDS_ATOM_OFFSET0__UNUSED_MASK                                                                         0xFFFFFF00L
//GDS_ATOM_OFFSET1
#define GDS_ATOM_OFFSET1__OFFSET1__SHIFT                                                                      0x0
#define GDS_ATOM_OFFSET1__UNUSED__SHIFT                                                                       0x8
#define GDS_ATOM_OFFSET1__OFFSET1_MASK                                                                        0x000000FFL
#define GDS_ATOM_OFFSET1__UNUSED_MASK                                                                         0xFFFFFF00L
//GDS_ATOM_DST
#define GDS_ATOM_DST__DST__SHIFT                                                                              0x0
#define GDS_ATOM_DST__DST_MASK                                                                                0xFFFFFFFFL
//GDS_ATOM_OP
#define GDS_ATOM_OP__OP__SHIFT                                                                                0x0
#define GDS_ATOM_OP__UNUSED__SHIFT                                                                            0x8
#define GDS_ATOM_OP__OP_MASK                                                                                  0x000000FFL
#define GDS_ATOM_OP__UNUSED_MASK                                                                              0xFFFFFF00L
//GDS_ATOM_SRC0
#define GDS_ATOM_SRC0__DATA__SHIFT                                                                            0x0
#define GDS_ATOM_SRC0__DATA_MASK                                                                              0xFFFFFFFFL
//GDS_ATOM_SRC0_U
#define GDS_ATOM_SRC0_U__DATA__SHIFT                                                                          0x0
#define GDS_ATOM_SRC0_U__DATA_MASK                                                                            0xFFFFFFFFL
//GDS_ATOM_SRC1
#define GDS_ATOM_SRC1__DATA__SHIFT                                                                            0x0
#define GDS_ATOM_SRC1__DATA_MASK                                                                              0xFFFFFFFFL
//GDS_ATOM_SRC1_U
#define GDS_ATOM_SRC1_U__DATA__SHIFT                                                                          0x0
#define GDS_ATOM_SRC1_U__DATA_MASK                                                                            0xFFFFFFFFL
//GDS_ATOM_READ0
#define GDS_ATOM_READ0__DATA__SHIFT                                                                           0x0
#define GDS_ATOM_READ0__DATA_MASK                                                                             0xFFFFFFFFL
//GDS_ATOM_READ0_U
#define GDS_ATOM_READ0_U__DATA__SHIFT                                                                         0x0
#define GDS_ATOM_READ0_U__DATA_MASK                                                                           0xFFFFFFFFL
//GDS_ATOM_READ1
#define GDS_ATOM_READ1__DATA__SHIFT                                                                           0x0
#define GDS_ATOM_READ1__DATA_MASK                                                                             0xFFFFFFFFL
//GDS_ATOM_READ1_U
#define GDS_ATOM_READ1_U__DATA__SHIFT                                                                         0x0
#define GDS_ATOM_READ1_U__DATA_MASK                                                                           0xFFFFFFFFL
//GDS_GWS_RESOURCE_CNTL
#define GDS_GWS_RESOURCE_CNTL__INDEX__SHIFT                                                                   0x0
#define GDS_GWS_RESOURCE_CNTL__UNUSED__SHIFT                                                                  0x6
#define GDS_GWS_RESOURCE_CNTL__INDEX_MASK                                                                     0x0000003FL
#define GDS_GWS_RESOURCE_CNTL__UNUSED_MASK                                                                    0xFFFFFFC0L
//GDS_GWS_RESOURCE
#define GDS_GWS_RESOURCE__FLAG__SHIFT                                                                         0x0
#define GDS_GWS_RESOURCE__COUNTER__SHIFT                                                                      0x1
#define GDS_GWS_RESOURCE__TYPE__SHIFT                                                                         0xd
#define GDS_GWS_RESOURCE__DED__SHIFT                                                                          0xe
#define GDS_GWS_RESOURCE__RELEASE_ALL__SHIFT                                                                  0xf
#define GDS_GWS_RESOURCE__HEAD_QUEUE__SHIFT                                                                   0x10
#define GDS_GWS_RESOURCE__HEAD_VALID__SHIFT                                                                   0x1b
#define GDS_GWS_RESOURCE__HEAD_FLAG__SHIFT                                                                    0x1c
#define GDS_GWS_RESOURCE__HALTED__SHIFT                                                                       0x1d
#define GDS_GWS_RESOURCE__HEAD_QUEUE1__SHIFT                                                                  0x1e
#define GDS_GWS_RESOURCE__UNUSED1__SHIFT                                                                      0x1f
#define GDS_GWS_RESOURCE__FLAG_MASK                                                                           0x00000001L
#define GDS_GWS_RESOURCE__COUNTER_MASK                                                                        0x00001FFEL
#define GDS_GWS_RESOURCE__TYPE_MASK                                                                           0x00002000L
#define GDS_GWS_RESOURCE__DED_MASK                                                                            0x00004000L
#define GDS_GWS_RESOURCE__RELEASE_ALL_MASK                                                                    0x00008000L
#define GDS_GWS_RESOURCE__HEAD_QUEUE_MASK                                                                     0x07FF0000L
#define GDS_GWS_RESOURCE__HEAD_VALID_MASK                                                                     0x08000000L
#define GDS_GWS_RESOURCE__HEAD_FLAG_MASK                                                                      0x10000000L
#define GDS_GWS_RESOURCE__HALTED_MASK                                                                         0x20000000L
#define GDS_GWS_RESOURCE__HEAD_QUEUE1_MASK                                                                    0x40000000L
#define GDS_GWS_RESOURCE__UNUSED1_MASK                                                                        0x80000000L
//GDS_GWS_RESOURCE_CNT
#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT__SHIFT                                                             0x0
#define GDS_GWS_RESOURCE_CNT__UNUSED__SHIFT                                                                   0x10
#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT_MASK                                                               0x0000FFFFL
#define GDS_GWS_RESOURCE_CNT__UNUSED_MASK                                                                     0xFFFF0000L
//GDS_OA_CNTL
#define GDS_OA_CNTL__INDEX__SHIFT                                                                             0x0
#define GDS_OA_CNTL__UNUSED__SHIFT                                                                            0x4
#define GDS_OA_CNTL__INDEX_MASK                                                                               0x0000000FL
#define GDS_OA_CNTL__UNUSED_MASK                                                                              0xFFFFFFF0L
//GDS_OA_COUNTER
#define GDS_OA_COUNTER__SPACE_AVAILABLE__SHIFT                                                                0x0
#define GDS_OA_COUNTER__SPACE_AVAILABLE_MASK                                                                  0xFFFFFFFFL
//GDS_OA_ADDRESS
#define GDS_OA_ADDRESS__DS_ADDRESS__SHIFT                                                                     0x0
#define GDS_OA_ADDRESS__CRAWLER_TYPE__SHIFT                                                                   0x10
#define GDS_OA_ADDRESS__CRAWLER__SHIFT                                                                        0x14
#define GDS_OA_ADDRESS__UNUSED__SHIFT                                                                         0x18
#define GDS_OA_ADDRESS__NO_ALLOC__SHIFT                                                                       0x1e
#define GDS_OA_ADDRESS__ENABLE__SHIFT                                                                         0x1f
#define GDS_OA_ADDRESS__DS_ADDRESS_MASK                                                                       0x0000FFFFL
#define GDS_OA_ADDRESS__CRAWLER_TYPE_MASK                                                                     0x000F0000L
#define GDS_OA_ADDRESS__CRAWLER_MASK                                                                          0x00F00000L
#define GDS_OA_ADDRESS__UNUSED_MASK                                                                           0x3F000000L
#define GDS_OA_ADDRESS__NO_ALLOC_MASK                                                                         0x40000000L
#define GDS_OA_ADDRESS__ENABLE_MASK                                                                           0x80000000L
//GDS_OA_INCDEC
#define GDS_OA_INCDEC__VALUE__SHIFT                                                                           0x0
#define GDS_OA_INCDEC__INCDEC__SHIFT                                                                          0x1f
#define GDS_OA_INCDEC__VALUE_MASK                                                                             0x7FFFFFFFL
#define GDS_OA_INCDEC__INCDEC_MASK                                                                            0x80000000L
//GDS_OA_RING_SIZE
#define GDS_OA_RING_SIZE__RING_SIZE__SHIFT                                                                    0x0
#define GDS_OA_RING_SIZE__RING_SIZE_MASK                                                                      0xFFFFFFFFL
//SPI_CONFIG_CNTL_REMAP
#define SPI_CONFIG_CNTL_REMAP__RESERVED__SHIFT                                                                0x0
#define SPI_CONFIG_CNTL_REMAP__RESERVED_MASK                                                                  0xFFFFFFFFL
//SPI_CONFIG_CNTL_1_REMAP
#define SPI_CONFIG_CNTL_1_REMAP__RESERVED__SHIFT                                                              0x0
#define SPI_CONFIG_CNTL_1_REMAP__RESERVED_MASK                                                                0xFFFFFFFFL
//SPI_CONFIG_CNTL_2_REMAP
#define SPI_CONFIG_CNTL_2_REMAP__RESERVED__SHIFT                                                              0x0
#define SPI_CONFIG_CNTL_2_REMAP__RESERVED_MASK                                                                0xFFFFFFFFL
//SPI_WAVE_LIMIT_CNTL_REMAP
#define SPI_WAVE_LIMIT_CNTL_REMAP__RESERVED__SHIFT                                                            0x0
#define SPI_WAVE_LIMIT_CNTL_REMAP__RESERVED_MASK                                                              0xFFFFFFFFL


// addressBlock: gc_cprs64dec
//CP_MES_PRGRM_CNTR_START
#define CP_MES_PRGRM_CNTR_START__IP_START__SHIFT                                                              0x0
#define CP_MES_PRGRM_CNTR_START__IP_START_MASK                                                                0x000FFFFFL
//CP_MES_INTR_ROUTINE_START
#define CP_MES_INTR_ROUTINE_START__IR_START__SHIFT                                                            0x0
#define CP_MES_INTR_ROUTINE_START__IR_START_MASK                                                              0xFFFFFFFFL
//CP_MES_MTVEC_LO
#define CP_MES_MTVEC_LO__ADDR_LO__SHIFT                                                                       0x0
#define CP_MES_MTVEC_LO__ADDR_LO_MASK                                                                         0xFFFFFFFFL
//CP_MES_MTVEC_HI
#define CP_MES_MTVEC_HI__ADDR_LO__SHIFT                                                                       0x0
#define CP_MES_MTVEC_HI__ADDR_LO_MASK                                                                         0xFFFFFFFFL
//CP_MES_CNTL
#define CP_MES_CNTL__MES_INVALIDATE_ICACHE__SHIFT                                                             0x4
#define CP_MES_CNTL__MES_PIPE0_RESET__SHIFT                                                                   0x10
#define CP_MES_CNTL__MES_PIPE1_RESET__SHIFT                                                                   0x11
#define CP_MES_CNTL__MES_PIPE2_RESET__SHIFT                                                                   0x12
#define CP_MES_CNTL__MES_PIPE3_RESET__SHIFT                                                                   0x13
#define CP_MES_CNTL__MES_PIPE0_ACTIVE__SHIFT                                                                  0x1a
#define CP_MES_CNTL__MES_PIPE1_ACTIVE__SHIFT                                                                  0x1b
#define CP_MES_CNTL__MES_PIPE2_ACTIVE__SHIFT                                                                  0x1c
#define CP_MES_CNTL__MES_PIPE3_ACTIVE__SHIFT                                                                  0x1d
#define CP_MES_CNTL__MES_HALT__SHIFT                                                                          0x1e
#define CP_MES_CNTL__MES_STEP__SHIFT                                                                          0x1f
#define CP_MES_CNTL__MES_INVALIDATE_ICACHE_MASK                                                               0x00000010L
#define CP_MES_CNTL__MES_PIPE0_RESET_MASK                                                                     0x00010000L
#define CP_MES_CNTL__MES_PIPE1_RESET_MASK                                                                     0x00020000L
#define CP_MES_CNTL__MES_PIPE2_RESET_MASK                                                                     0x00040000L
#define CP_MES_CNTL__MES_PIPE3_RESET_MASK                                                                     0x00080000L
#define CP_MES_CNTL__MES_PIPE0_ACTIVE_MASK                                                                    0x04000000L
#define CP_MES_CNTL__MES_PIPE1_ACTIVE_MASK                                                                    0x08000000L
#define CP_MES_CNTL__MES_PIPE2_ACTIVE_MASK                                                                    0x10000000L
#define CP_MES_CNTL__MES_PIPE3_ACTIVE_MASK                                                                    0x20000000L
#define CP_MES_CNTL__MES_HALT_MASK                                                                            0x40000000L
#define CP_MES_CNTL__MES_STEP_MASK                                                                            0x80000000L
//CP_MES_PIPE_PRIORITY_CNTS
#define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT                                                       0x0
#define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT                                                      0x8
#define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT                                                      0x10
#define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT                                                       0x18
#define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK                                                         0x000000FFL
#define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK                                                        0x0000FF00L
#define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK                                                        0x00FF0000L
#define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK                                                         0xFF000000L
//CP_MES_PIPE0_PRIORITY
#define CP_MES_PIPE0_PRIORITY__PRIORITY__SHIFT                                                                0x0
#define CP_MES_PIPE0_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
//CP_MES_PIPE1_PRIORITY
#define CP_MES_PIPE1_PRIORITY__PRIORITY__SHIFT                                                                0x0
#define CP_MES_PIPE1_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
//CP_MES_PIPE2_PRIORITY
#define CP_MES_PIPE2_PRIORITY__PRIORITY__SHIFT                                                                0x0
#define CP_MES_PIPE2_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
//CP_MES_PIPE3_PRIORITY
#define CP_MES_PIPE3_PRIORITY__PRIORITY__SHIFT                                                                0x0
#define CP_MES_PIPE3_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
//CP_MES_HEADER_DUMP
#define CP_MES_HEADER_DUMP__HEADER_DUMP__SHIFT                                                                0x0
#define CP_MES_HEADER_DUMP__HEADER_DUMP_MASK                                                                  0xFFFFFFFFL
//CP_MES_MIE_LO
#define CP_MES_MIE_LO__MES_INT__SHIFT                                                                         0x0
#define CP_MES_MIE_LO__MES_INT_MASK                                                                           0xFFFFFFFFL
//CP_MES_MIE_HI
#define CP_MES_MIE_HI__MES_INT__SHIFT                                                                         0x0
#define CP_MES_MIE_HI__MES_INT_MASK                                                                           0xFFFFFFFFL
//CP_MES_INTERRUPT
#define CP_MES_INTERRUPT__MES_INT__SHIFT                                                                      0x0
#define CP_MES_INTERRUPT__MES_INT_MASK                                                                        0xFFFFFFFFL
//CP_MES_SCRATCH_INDEX
#define CP_MES_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT                                                            0x0
#define CP_MES_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE__SHIFT                                                 0x1f
#define CP_MES_SCRATCH_INDEX__SCRATCH_INDEX_MASK                                                              0x000001FFL
#define CP_MES_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE_MASK                                                   0x80000000L
//CP_MES_SCRATCH_DATA
#define CP_MES_SCRATCH_DATA__SCRATCH_DATA__SHIFT                                                              0x0
#define CP_MES_SCRATCH_DATA__SCRATCH_DATA_MASK                                                                0xFFFFFFFFL
//CP_MES_INSTR_PNTR
#define CP_MES_INSTR_PNTR__INSTR_PNTR__SHIFT                                                                  0x0
#define CP_MES_INSTR_PNTR__INSTR_PNTR_MASK                                                                    0x000FFFFFL
//CP_MES_MSCRATCH_HI
#define CP_MES_MSCRATCH_HI__DATA__SHIFT                                                                       0x0
#define CP_MES_MSCRATCH_HI__DATA_MASK                                                                         0xFFFFFFFFL
//CP_MES_MSCRATCH_LO
#define CP_MES_MSCRATCH_LO__DATA__SHIFT                                                                       0x0
#define CP_MES_MSCRATCH_LO__DATA_MASK                                                                         0xFFFFFFFFL
//CP_MES_MSTATUS_LO
#define CP_MES_MSTATUS_LO__STATUS_LO__SHIFT                                                                   0x0
#define CP_MES_MSTATUS_LO__STATUS_LO_MASK                                                                     0xFFFFFFFFL
//CP_MES_MSTATUS_HI
#define CP_MES_MSTATUS_HI__STATUS_HI__SHIFT                                                                   0x0
#define CP_MES_MSTATUS_HI__STATUS_HI_MASK                                                                     0xFFFFFFFFL
//CP_MES_MEPC_LO
#define CP_MES_MEPC_LO__MEPC_LO__SHIFT                                                                        0x0
#define CP_MES_MEPC_LO__MEPC_LO_MASK                                                                          0xFFFFFFFFL
//CP_MES_MEPC_HI
#define CP_MES_MEPC_HI__MEPC_HI__SHIFT                                                                        0x0
#define CP_MES_MEPC_HI__MEPC_HI_MASK                                                                          0xFFFFFFFFL
//CP_MES_MCAUSE_LO
#define CP_MES_MCAUSE_LO__CAUSE_LO__SHIFT                                                                     0x0
#define CP_MES_MCAUSE_LO__CAUSE_LO_MASK                                                                       0xFFFFFFFFL
//CP_MES_MCAUSE_HI
#define CP_MES_MCAUSE_HI__CAUSE_HI__SHIFT                                                                     0x0
#define CP_MES_MCAUSE_HI__CAUSE_HI_MASK                                                                       0xFFFFFFFFL
//CP_MES_MBADADDR_LO
#define CP_MES_MBADADDR_LO__ADDR_LO__SHIFT                                                                    0x0
#define CP_MES_MBADADDR_LO__ADDR_LO_MASK                                                                      0xFFFFFFFFL
//CP_MES_MBADADDR_HI
#define CP_MES_MBADADDR_HI__ADDR_HI__SHIFT                                                                    0x0
#define CP_MES_MBADADDR_HI__ADDR_HI_MASK                                                                      0xFFFFFFFFL
//CP_MES_MIP_LO
#define CP_MES_MIP_LO__MIP_LO__SHIFT                                                                          0x0
#define CP_MES_MIP_LO__MIP_LO_MASK                                                                            0xFFFFFFFFL
//CP_MES_MIP_HI
#define CP_MES_MIP_HI__MIP_HI__SHIFT                                                                          0x0
#define CP_MES_MIP_HI__MIP_HI_MASK                                                                            0xFFFFFFFFL
//CP_MES_IC_OP_CNTL
#define CP_MES_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT                                                            0x0
#define CP_MES_IC_OP_CNTL__PRIME_ICACHE__SHIFT                                                                0x4
#define CP_MES_IC_OP_CNTL__ICACHE_PRIMED__SHIFT                                                               0x5
#define CP_MES_IC_OP_CNTL__INVALIDATE_CACHE_MASK                                                              0x00000001L
#define CP_MES_IC_OP_CNTL__PRIME_ICACHE_MASK                                                                  0x00000010L
#define CP_MES_IC_OP_CNTL__ICACHE_PRIMED_MASK                                                                 0x00000020L
//CP_MES_MCYCLE_LO
#define CP_MES_MCYCLE_LO__CYCLE_LO__SHIFT                                                                     0x0
#define CP_MES_MCYCLE_LO__CYCLE_LO_MASK                                                                       0xFFFFFFFFL
//CP_MES_MCYCLE_HI
#define CP_MES_MCYCLE_HI__CYCLE_HI__SHIFT                                                                     0x0
#define CP_MES_MCYCLE_HI__CYCLE_HI_MASK                                                                       0xFFFFFFFFL
//CP_MES_MTIME_LO
#define CP_MES_MTIME_LO__TIME_LO__SHIFT                                                                       0x0
#define CP_MES_MTIME_LO__TIME_LO_MASK                                                                         0xFFFFFFFFL
//CP_MES_MTIME_HI
#define CP_MES_MTIME_HI__TIME_HI__SHIFT                                                                       0x0
#define CP_MES_MTIME_HI__TIME_HI_MASK                                                                         0xFFFFFFFFL
//CP_MES_MINSTRET_LO
#define CP_MES_MINSTRET_LO__INSTRET_LO__SHIFT                                                                 0x0
#define CP_MES_MINSTRET_LO__INSTRET_LO_MASK                                                                   0xFFFFFFFFL
//CP_MES_MINSTRET_HI
#define CP_MES_MINSTRET_HI__INSTRET_HI__SHIFT                                                                 0x0
#define CP_MES_MINSTRET_HI__INSTRET_HI_MASK                                                                   0xFFFFFFFFL
//CP_MES_MISA_LO
#define CP_MES_MISA_LO__MISA_LO__SHIFT                                                                        0x0
#define CP_MES_MISA_LO__MISA_LO_MASK                                                                          0xFFFFFFFFL
//CP_MES_MISA_HI
#define CP_MES_MISA_HI__MISA_HI__SHIFT                                                                        0x0
#define CP_MES_MISA_HI__MISA_HI_MASK                                                                          0xFFFFFFFFL
//CP_MES_MVENDORID_LO
#define CP_MES_MVENDORID_LO__MVENDORID_LO__SHIFT                                                              0x0
#define CP_MES_MVENDORID_LO__MVENDORID_LO_MASK                                                                0xFFFFFFFFL
//CP_MES_MVENDORID_HI
#define CP_MES_MVENDORID_HI__MVENDORID_HI__SHIFT                                                              0x0
#define CP_MES_MVENDORID_HI__MVENDORID_HI_MASK                                                                0xFFFFFFFFL
//CP_MES_MARCHID_LO
#define CP_MES_MARCHID_LO__MARCHID_LO__SHIFT                                                                  0x0
#define CP_MES_MARCHID_LO__MARCHID_LO_MASK                                                                    0xFFFFFFFFL
//CP_MES_MARCHID_HI
#define CP_MES_MARCHID_HI__MARCHID_HI__SHIFT                                                                  0x0
#define CP_MES_MARCHID_HI__MARCHID_HI_MASK                                                                    0xFFFFFFFFL
//CP_MES_MIMPID_LO
#define CP_MES_MIMPID_LO__MIMPID_LO__SHIFT                                                                    0x0
#define CP_MES_MIMPID_LO__MIMPID_LO_MASK                                                                      0xFFFFFFFFL
//CP_MES_MIMPID_HI
#define CP_MES_MIMPID_HI__MIMPID_HI__SHIFT                                                                    0x0
#define CP_MES_MIMPID_HI__MIMPID_HI_MASK                                                                      0xFFFFFFFFL
//CP_MES_MHARTID_LO
#define CP_MES_MHARTID_LO__MHARTID_LO__SHIFT                                                                  0x0
#define CP_MES_MHARTID_LO__MHARTID_LO_MASK                                                                    0xFFFFFFFFL
//CP_MES_MHARTID_HI
#define CP_MES_MHARTID_HI__MHARTID_HI__SHIFT                                                                  0x0
#define CP_MES_MHARTID_HI__MHARTID_HI_MASK                                                                    0xFFFFFFFFL
//CP_MES_DC_BASE_CNTL
#define CP_MES_DC_BASE_CNTL__VMID__SHIFT                                                                      0x0
#define CP_MES_DC_BASE_CNTL__CACHE_POLICY__SHIFT                                                              0x18
#define CP_MES_DC_BASE_CNTL__VMID_MASK                                                                        0x0000000FL
#define CP_MES_DC_BASE_CNTL__CACHE_POLICY_MASK                                                                0x03000000L
//CP_MES_DC_OP_CNTL
#define CP_MES_DC_OP_CNTL__INVALIDATE_DCACHE__SHIFT                                                           0x0
#define CP_MES_DC_OP_CNTL__INVALIDATE_DCACHE_COMPLETE__SHIFT                                                  0x1
#define CP_MES_DC_OP_CNTL__BYPASS_ALL__SHIFT                                                                  0x2
#define CP_MES_DC_OP_CNTL__BYPASS_UNCACHED__SHIFT                                                             0x3
#define CP_MES_DC_OP_CNTL__PRIME_DCACHE__SHIFT                                                                0x4
#define CP_MES_DC_OP_CNTL__DCACHE_PRIMED__SHIFT                                                               0x5
#define CP_MES_DC_OP_CNTL__INVALIDATE_DCACHE_MASK                                                             0x00000001L
#define CP_MES_DC_OP_CNTL__INVALIDATE_DCACHE_COMPLETE_MASK                                                    0x00000002L
#define CP_MES_DC_OP_CNTL__BYPASS_ALL_MASK                                                                    0x00000004L
#define CP_MES_DC_OP_CNTL__BYPASS_UNCACHED_MASK                                                               0x00000008L
#define CP_MES_DC_OP_CNTL__PRIME_DCACHE_MASK                                                                  0x00000010L
#define CP_MES_DC_OP_CNTL__DCACHE_PRIMED_MASK                                                                 0x00000020L
//CP_MES_MTIMECMP_LO
#define CP_MES_MTIMECMP_LO__TIME_LO__SHIFT                                                                    0x0
#define CP_MES_MTIMECMP_LO__TIME_LO_MASK                                                                      0xFFFFFFFFL
//CP_MES_MTIMECMP_HI
#define CP_MES_MTIMECMP_HI__TIME_HI__SHIFT                                                                    0x0
#define CP_MES_MTIMECMP_HI__TIME_HI_MASK                                                                      0xFFFFFFFFL
//CP_MES_PROCESS_QUANTUM_PIPE0
#define CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_DURATION__SHIFT                                                 0x0
#define CP_MES_PROCESS_QUANTUM_PIPE0__TIMER_EXPIRED__SHIFT                                                    0x1c
#define CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_SCALE__SHIFT                                                    0x1d
#define CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_EN__SHIFT                                                       0x1f
#define CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_DURATION_MASK                                                   0x0FFFFFFFL
#define CP_MES_PROCESS_QUANTUM_PIPE0__TIMER_EXPIRED_MASK                                                      0x10000000L
#define CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_SCALE_MASK                                                      0x60000000L
#define CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_EN_MASK                                                         0x80000000L
//CP_MES_PROCESS_QUANTUM_PIPE1
#define CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_DURATION__SHIFT                                                 0x0
#define CP_MES_PROCESS_QUANTUM_PIPE1__TIMER_EXPIRED__SHIFT                                                    0x1c
#define CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_SCALE__SHIFT                                                    0x1d
#define CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_EN__SHIFT                                                       0x1f
#define CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_DURATION_MASK                                                   0x0FFFFFFFL
#define CP_MES_PROCESS_QUANTUM_PIPE1__TIMER_EXPIRED_MASK                                                      0x10000000L
#define CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_SCALE_MASK                                                      0x60000000L
#define CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_EN_MASK                                                         0x80000000L
//CP_MES_DOORBELL_CONTROL1
#define CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET__SHIFT                                                      0x2
#define CP_MES_DOORBELL_CONTROL1__DOORBELL_EN__SHIFT                                                          0x1e
#define CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT__SHIFT                                                         0x1f
#define CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET_MASK                                                        0x0FFFFFFCL
#define CP_MES_DOORBELL_CONTROL1__DOORBELL_EN_MASK                                                            0x40000000L
#define CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT_MASK                                                           0x80000000L
//CP_MES_DOORBELL_CONTROL2
#define CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET__SHIFT                                                      0x2
#define CP_MES_DOORBELL_CONTROL2__DOORBELL_EN__SHIFT                                                          0x1e
#define CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT__SHIFT                                                         0x1f
#define CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET_MASK                                                        0x0FFFFFFCL
#define CP_MES_DOORBELL_CONTROL2__DOORBELL_EN_MASK                                                            0x40000000L
#define CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT_MASK                                                           0x80000000L
//CP_MES_DOORBELL_CONTROL3
#define CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET__SHIFT                                                      0x2
#define CP_MES_DOORBELL_CONTROL3__DOORBELL_EN__SHIFT                                                          0x1e
#define CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT__SHIFT                                                         0x1f
#define CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET_MASK                                                        0x0FFFFFFCL
#define CP_MES_DOORBELL_CONTROL3__DOORBELL_EN_MASK                                                            0x40000000L
#define CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT_MASK                                                           0x80000000L
//CP_MES_DOORBELL_CONTROL4
#define CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET__SHIFT                                                      0x2
#define CP_MES_DOORBELL_CONTROL4__DOORBELL_EN__SHIFT                                                          0x1e
#define CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT__SHIFT                                                         0x1f
#define CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET_MASK                                                        0x0FFFFFFCL
#define CP_MES_DOORBELL_CONTROL4__DOORBELL_EN_MASK                                                            0x40000000L
#define CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT_MASK                                                           0x80000000L
//CP_MES_DOORBELL_CONTROL5
#define CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET__SHIFT                                                      0x2
#define CP_MES_DOORBELL_CONTROL5__DOORBELL_EN__SHIFT                                                          0x1e
#define CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT__SHIFT                                                         0x1f
#define CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET_MASK                                                        0x0FFFFFFCL
#define CP_MES_DOORBELL_CONTROL5__DOORBELL_EN_MASK                                                            0x40000000L
#define CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT_MASK                                                           0x80000000L
//CP_MES_DOORBELL_CONTROL6
#define CP_MES_DOORBELL_CONTROL6__DOORBELL_OFFSET__SHIFT                                                      0x2
#define CP_MES_DOORBELL_CONTROL6__DOORBELL_EN__SHIFT                                                          0x1e
#define CP_MES_DOORBELL_CONTROL6__DOORBELL_HIT__SHIFT                                                         0x1f
#define CP_MES_DOORBELL_CONTROL6__DOORBELL_OFFSET_MASK                                                        0x0FFFFFFCL
#define CP_MES_DOORBELL_CONTROL6__DOORBELL_EN_MASK                                                            0x40000000L
#define CP_MES_DOORBELL_CONTROL6__DOORBELL_HIT_MASK                                                           0x80000000L
//CP_MES_GP0_LO
#define CP_MES_GP0_LO__PG_VIRT_HALTED__SHIFT                                                                  0x0
#define CP_MES_GP0_LO__DATA__SHIFT                                                                            0x1
#define CP_MES_GP0_LO__PG_VIRT_HALTED_MASK                                                                    0x00000001L
#define CP_MES_GP0_LO__DATA_MASK                                                                              0xFFFFFFFEL
//CP_MES_GP0_HI
#define CP_MES_GP0_HI__M_RET_ADDR__SHIFT                                                                      0x0
#define CP_MES_GP0_HI__M_RET_ADDR_MASK                                                                        0xFFFFFFFFL
//CP_MES_GP1_LO
#define CP_MES_GP1_LO__RD_WR_SELECT_LO__SHIFT                                                                 0x0
#define CP_MES_GP1_LO__RD_WR_SELECT_LO_MASK                                                                   0xFFFFFFFFL
//CP_MES_GP1_HI
#define CP_MES_GP1_HI__RD_WR_SELECT_HI__SHIFT                                                                 0x0
#define CP_MES_GP1_HI__RD_WR_SELECT_HI_MASK                                                                   0xFFFFFFFFL
//CP_MES_GP2_LO
#define CP_MES_GP2_LO__STACK_PNTR_LO__SHIFT                                                                   0x0
#define CP_MES_GP2_LO__STACK_PNTR_LO_MASK                                                                     0xFFFFFFFFL
//CP_MES_GP2_HI
#define CP_MES_GP2_HI__STACK_PNTR_HI__SHIFT                                                                   0x0
#define CP_MES_GP2_HI__STACK_PNTR_HI_MASK                                                                     0xFFFFFFFFL
//CP_MES_GP3_LO
#define CP_MES_GP3_LO__DATA__SHIFT                                                                            0x0
#define CP_MES_GP3_LO__DATA_MASK                                                                              0xFFFFFFFFL
//CP_MES_GP3_HI
#define CP_MES_GP3_HI__DATA__SHIFT                                                                            0x0
#define CP_MES_GP3_HI__DATA_MASK                                                                              0xFFFFFFFFL
//CP_MES_GP4_LO
#define CP_MES_GP4_LO__DATA__SHIFT                                                                            0x0
#define CP_MES_GP4_LO__DATA_MASK                                                                              0xFFFFFFFFL
//CP_MES_GP4_HI
#define CP_MES_GP4_HI__DATA__SHIFT                                                                            0x0
#define CP_MES_GP4_HI__DATA_MASK                                                                              0xFFFFFFFFL
//CP_MES_GP5_LO
#define CP_MES_GP5_LO__PG_VIRT_HALTED__SHIFT                                                                  0x0
#define CP_MES_GP5_LO__DATA__SHIFT                                                                            0x1
#define CP_MES_GP5_LO__PG_VIRT_HALTED_MASK                                                                    0x00000001L
#define CP_MES_GP5_LO__DATA_MASK                                                                              0xFFFFFFFEL
//CP_MES_GP5_HI
#define CP_MES_GP5_HI__M_RET_ADDR__SHIFT                                                                      0x0
#define CP_MES_GP5_HI__M_RET_ADDR_MASK                                                                        0xFFFFFFFFL
//CP_MES_GP6_LO
#define CP_MES_GP6_LO__RD_WR_SELECT_LO__SHIFT                                                                 0x0
#define CP_MES_GP6_LO__RD_WR_SELECT_LO_MASK                                                                   0xFFFFFFFFL
//CP_MES_GP6_HI
#define CP_MES_GP6_HI__RD_WR_SELECT_HI__SHIFT                                                                 0x0
#define CP_MES_GP6_HI__RD_WR_SELECT_HI_MASK                                                                   0xFFFFFFFFL
//CP_MES_GP7_LO
#define CP_MES_GP7_LO__STACK_PNTR_LO__SHIFT                                                                   0x0
#define CP_MES_GP7_LO__STACK_PNTR_LO_MASK                                                                     0xFFFFFFFFL
//CP_MES_GP7_HI
#define CP_MES_GP7_HI__STACK_PNTR_HI__SHIFT                                                                   0x0
#define CP_MES_GP7_HI__STACK_PNTR_HI_MASK                                                                     0xFFFFFFFFL
//CP_MES_GP8_LO
#define CP_MES_GP8_LO__DATA__SHIFT                                                                            0x0
#define CP_MES_GP8_LO__DATA_MASK                                                                              0xFFFFFFFFL
//CP_MES_GP8_HI
#define CP_MES_GP8_HI__DATA__SHIFT                                                                            0x0
#define CP_MES_GP8_HI__DATA_MASK                                                                              0xFFFFFFFFL
//CP_MES_GP9_LO
#define CP_MES_GP9_LO__DATA__SHIFT                                                                            0x0
#define CP_MES_GP9_LO__DATA_MASK                                                                              0xFFFFFFFFL
//CP_MES_GP9_HI
#define CP_MES_GP9_HI__DATA__SHIFT                                                                            0x0
#define CP_MES_GP9_HI__DATA_MASK                                                                              0xFFFFFFFFL
//CP_MES_DM_INDEX_ADDR
#define CP_MES_DM_INDEX_ADDR__ADDR__SHIFT                                                                     0x0
#define CP_MES_DM_INDEX_ADDR__ADDR_MASK                                                                       0xFFFFFFFFL
//CP_MES_DM_INDEX_DATA
#define CP_MES_DM_INDEX_DATA__DATA__SHIFT                                                                     0x0
#define CP_MES_DM_INDEX_DATA__DATA_MASK                                                                       0xFFFFFFFFL
//CP_MES_PERFCOUNT_CNTL
#define CP_MES_PERFCOUNT_CNTL__EVENT_SEL__SHIFT                                                               0x0
#define CP_MES_PERFCOUNT_CNTL__EVENT_SEL_MASK                                                                 0x0000001FL
//CP_MES_PENDING_INTERRUPT
#define CP_MES_PENDING_INTERRUPT__PENDING_INTERRUPT__SHIFT                                                    0x0
#define CP_MES_PENDING_INTERRUPT__PENDING_INTERRUPT_MASK                                                      0xFFFFFFFFL


// addressBlock: gc_gusdec
//GUS_IO_RD_COMBINE_FLUSH
#define GUS_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT                                                          0x0
#define GUS_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT                                                          0x4
#define GUS_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT                                                          0x8
#define GUS_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT                                                          0xc
#define GUS_IO_RD_COMBINE_FLUSH__GROUP4_TIMER__SHIFT                                                          0x10
#define GUS_IO_RD_COMBINE_FLUSH__GROUP5_TIMER__SHIFT                                                          0x14
#define GUS_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK                                                            0x0000000FL
#define GUS_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK                                                            0x000000F0L
#define GUS_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK                                                            0x00000F00L
#define GUS_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK                                                            0x0000F000L
#define GUS_IO_RD_COMBINE_FLUSH__GROUP4_TIMER_MASK                                                            0x000F0000L
#define GUS_IO_RD_COMBINE_FLUSH__GROUP5_TIMER_MASK                                                            0x00F00000L
//GUS_IO_WR_COMBINE_FLUSH
#define GUS_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT                                                          0x0
#define GUS_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT                                                          0x4
#define GUS_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT                                                          0x8
#define GUS_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT                                                          0xc
#define GUS_IO_WR_COMBINE_FLUSH__GROUP4_TIMER__SHIFT                                                          0x10
#define GUS_IO_WR_COMBINE_FLUSH__GROUP5_TIMER__SHIFT                                                          0x14
#define GUS_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK                                                            0x0000000FL
#define GUS_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK                                                            0x000000F0L
#define GUS_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK                                                            0x00000F00L
#define GUS_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK                                                            0x0000F000L
#define GUS_IO_WR_COMBINE_FLUSH__GROUP4_TIMER_MASK                                                            0x000F0000L
#define GUS_IO_WR_COMBINE_FLUSH__GROUP5_TIMER_MASK                                                            0x00F00000L
//GUS_IO_RD_PRI_AGE_RATE
#define GUS_IO_RD_PRI_AGE_RATE__GROUP0_AGING_RATE__SHIFT                                                      0x0
#define GUS_IO_RD_PRI_AGE_RATE__GROUP1_AGING_RATE__SHIFT                                                      0x3
#define GUS_IO_RD_PRI_AGE_RATE__GROUP2_AGING_RATE__SHIFT                                                      0x6
#define GUS_IO_RD_PRI_AGE_RATE__GROUP3_AGING_RATE__SHIFT                                                      0x9
#define GUS_IO_RD_PRI_AGE_RATE__GROUP4_AGING_RATE__SHIFT                                                      0xc
#define GUS_IO_RD_PRI_AGE_RATE__GROUP5_AGING_RATE__SHIFT                                                      0xf
#define GUS_IO_RD_PRI_AGE_RATE__GROUP0_AGING_RATE_MASK                                                        0x00000007L
#define GUS_IO_RD_PRI_AGE_RATE__GROUP1_AGING_RATE_MASK                                                        0x00000038L
#define GUS_IO_RD_PRI_AGE_RATE__GROUP2_AGING_RATE_MASK                                                        0x000001C0L
#define GUS_IO_RD_PRI_AGE_RATE__GROUP3_AGING_RATE_MASK                                                        0x00000E00L
#define GUS_IO_RD_PRI_AGE_RATE__GROUP4_AGING_RATE_MASK                                                        0x00007000L
#define GUS_IO_RD_PRI_AGE_RATE__GROUP5_AGING_RATE_MASK                                                        0x00038000L
//GUS_IO_WR_PRI_AGE_RATE
#define GUS_IO_WR_PRI_AGE_RATE__GROUP0_AGING_RATE__SHIFT                                                      0x0
#define GUS_IO_WR_PRI_AGE_RATE__GROUP1_AGING_RATE__SHIFT                                                      0x3
#define GUS_IO_WR_PRI_AGE_RATE__GROUP2_AGING_RATE__SHIFT                                                      0x6
#define GUS_IO_WR_PRI_AGE_RATE__GROUP3_AGING_RATE__SHIFT                                                      0x9
#define GUS_IO_WR_PRI_AGE_RATE__GROUP4_AGING_RATE__SHIFT                                                      0xc
#define GUS_IO_WR_PRI_AGE_RATE__GROUP5_AGING_RATE__SHIFT                                                      0xf
#define GUS_IO_WR_PRI_AGE_RATE__GROUP0_AGING_RATE_MASK                                                        0x00000007L
#define GUS_IO_WR_PRI_AGE_RATE__GROUP1_AGING_RATE_MASK                                                        0x00000038L
#define GUS_IO_WR_PRI_AGE_RATE__GROUP2_AGING_RATE_MASK                                                        0x000001C0L
#define GUS_IO_WR_PRI_AGE_RATE__GROUP3_AGING_RATE_MASK                                                        0x00000E00L
#define GUS_IO_WR_PRI_AGE_RATE__GROUP4_AGING_RATE_MASK                                                        0x00007000L
#define GUS_IO_WR_PRI_AGE_RATE__GROUP5_AGING_RATE_MASK                                                        0x00038000L
//GUS_IO_RD_PRI_AGE_COEFF
#define GUS_IO_RD_PRI_AGE_COEFF__GROUP0_AGE_COEFFICIENT__SHIFT                                                0x0
#define GUS_IO_RD_PRI_AGE_COEFF__GROUP1_AGE_COEFFICIENT__SHIFT                                                0x3
#define GUS_IO_RD_PRI_AGE_COEFF__GROUP2_AGE_COEFFICIENT__SHIFT                                                0x6
#define GUS_IO_RD_PRI_AGE_COEFF__GROUP3_AGE_COEFFICIENT__SHIFT                                                0x9
#define GUS_IO_RD_PRI_AGE_COEFF__GROUP4_AGE_COEFFICIENT__SHIFT                                                0xc
#define GUS_IO_RD_PRI_AGE_COEFF__GROUP5_AGE_COEFFICIENT__SHIFT                                                0xf
#define GUS_IO_RD_PRI_AGE_COEFF__GROUP0_AGE_COEFFICIENT_MASK                                                  0x00000007L
#define GUS_IO_RD_PRI_AGE_COEFF__GROUP1_AGE_COEFFICIENT_MASK                                                  0x00000038L
#define GUS_IO_RD_PRI_AGE_COEFF__GROUP2_AGE_COEFFICIENT_MASK                                                  0x000001C0L
#define GUS_IO_RD_PRI_AGE_COEFF__GROUP3_AGE_COEFFICIENT_MASK                                                  0x00000E00L
#define GUS_IO_RD_PRI_AGE_COEFF__GROUP4_AGE_COEFFICIENT_MASK                                                  0x00007000L
#define GUS_IO_RD_PRI_AGE_COEFF__GROUP5_AGE_COEFFICIENT_MASK                                                  0x00038000L
//GUS_IO_WR_PRI_AGE_COEFF
#define GUS_IO_WR_PRI_AGE_COEFF__GROUP0_AGE_COEFFICIENT__SHIFT                                                0x0
#define GUS_IO_WR_PRI_AGE_COEFF__GROUP1_AGE_COEFFICIENT__SHIFT                                                0x3
#define GUS_IO_WR_PRI_AGE_COEFF__GROUP2_AGE_COEFFICIENT__SHIFT                                                0x6
#define GUS_IO_WR_PRI_AGE_COEFF__GROUP3_AGE_COEFFICIENT__SHIFT                                                0x9
#define GUS_IO_WR_PRI_AGE_COEFF__GROUP4_AGE_COEFFICIENT__SHIFT                                                0xc
#define GUS_IO_WR_PRI_AGE_COEFF__GROUP5_AGE_COEFFICIENT__SHIFT                                                0xf
#define GUS_IO_WR_PRI_AGE_COEFF__GROUP0_AGE_COEFFICIENT_MASK                                                  0x00000007L
#define GUS_IO_WR_PRI_AGE_COEFF__GROUP1_AGE_COEFFICIENT_MASK                                                  0x00000038L
#define GUS_IO_WR_PRI_AGE_COEFF__GROUP2_AGE_COEFFICIENT_MASK                                                  0x000001C0L
#define GUS_IO_WR_PRI_AGE_COEFF__GROUP3_AGE_COEFFICIENT_MASK                                                  0x00000E00L
#define GUS_IO_WR_PRI_AGE_COEFF__GROUP4_AGE_COEFFICIENT_MASK                                                  0x00007000L
#define GUS_IO_WR_PRI_AGE_COEFF__GROUP5_AGE_COEFFICIENT_MASK                                                  0x00038000L
//GUS_IO_RD_PRI_QUEUING
#define GUS_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                              0x0
#define GUS_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                              0x3
#define GUS_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                              0x6
#define GUS_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                              0x9
#define GUS_IO_RD_PRI_QUEUING__GROUP4_QUEUING_COEFFICIENT__SHIFT                                              0xc
#define GUS_IO_RD_PRI_QUEUING__GROUP5_QUEUING_COEFFICIENT__SHIFT                                              0xf
#define GUS_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                                0x00000007L
#define GUS_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                                0x00000038L
#define GUS_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                                0x000001C0L
#define GUS_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                                0x00000E00L
#define GUS_IO_RD_PRI_QUEUING__GROUP4_QUEUING_COEFFICIENT_MASK                                                0x00007000L
#define GUS_IO_RD_PRI_QUEUING__GROUP5_QUEUING_COEFFICIENT_MASK                                                0x00038000L
//GUS_IO_WR_PRI_QUEUING
#define GUS_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                              0x0
#define GUS_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                              0x3
#define GUS_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                              0x6
#define GUS_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                              0x9
#define GUS_IO_WR_PRI_QUEUING__GROUP4_QUEUING_COEFFICIENT__SHIFT                                              0xc
#define GUS_IO_WR_PRI_QUEUING__GROUP5_QUEUING_COEFFICIENT__SHIFT                                              0xf
#define GUS_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                                0x00000007L
#define GUS_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                                0x00000038L
#define GUS_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                                0x000001C0L
#define GUS_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                                0x00000E00L
#define GUS_IO_WR_PRI_QUEUING__GROUP4_QUEUING_COEFFICIENT_MASK                                                0x00007000L
#define GUS_IO_WR_PRI_QUEUING__GROUP5_QUEUING_COEFFICIENT_MASK                                                0x00038000L
//GUS_IO_RD_PRI_FIXED
#define GUS_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                                  0x0
#define GUS_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                                  0x3
#define GUS_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                                  0x6
#define GUS_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                                  0x9
#define GUS_IO_RD_PRI_FIXED__GROUP4_FIXED_COEFFICIENT__SHIFT                                                  0xc
#define GUS_IO_RD_PRI_FIXED__GROUP5_FIXED_COEFFICIENT__SHIFT                                                  0xf
#define GUS_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                    0x00000007L
#define GUS_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                    0x00000038L
#define GUS_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                    0x000001C0L
#define GUS_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                    0x00000E00L
#define GUS_IO_RD_PRI_FIXED__GROUP4_FIXED_COEFFICIENT_MASK                                                    0x00007000L
#define GUS_IO_RD_PRI_FIXED__GROUP5_FIXED_COEFFICIENT_MASK                                                    0x00038000L
//GUS_IO_WR_PRI_FIXED
#define GUS_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                                  0x0
#define GUS_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                                  0x3
#define GUS_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                                  0x6
#define GUS_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                                  0x9
#define GUS_IO_WR_PRI_FIXED__GROUP4_FIXED_COEFFICIENT__SHIFT                                                  0xc
#define GUS_IO_WR_PRI_FIXED__GROUP5_FIXED_COEFFICIENT__SHIFT                                                  0xf
#define GUS_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                    0x00000007L
#define GUS_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                    0x00000038L
#define GUS_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                    0x000001C0L
#define GUS_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                    0x00000E00L
#define GUS_IO_WR_PRI_FIXED__GROUP4_FIXED_COEFFICIENT_MASK                                                    0x00007000L
#define GUS_IO_WR_PRI_FIXED__GROUP5_FIXED_COEFFICIENT_MASK                                                    0x00038000L
//GUS_IO_RD_PRI_URGENCY_COEFF
#define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP0_URGENCY_COEFFICIENT__SHIFT                                        0x0
#define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP1_URGENCY_COEFFICIENT__SHIFT                                        0x3
#define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP2_URGENCY_COEFFICIENT__SHIFT                                        0x6
#define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP3_URGENCY_COEFFICIENT__SHIFT                                        0x9
#define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP4_URGENCY_COEFFICIENT__SHIFT                                        0xc
#define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP5_URGENCY_COEFFICIENT__SHIFT                                        0xf
#define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP0_URGENCY_COEFFICIENT_MASK                                          0x00000007L
#define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP1_URGENCY_COEFFICIENT_MASK                                          0x00000038L
#define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP2_URGENCY_COEFFICIENT_MASK                                          0x000001C0L
#define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP3_URGENCY_COEFFICIENT_MASK                                          0x00000E00L
#define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP4_URGENCY_COEFFICIENT_MASK                                          0x00007000L
#define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP5_URGENCY_COEFFICIENT_MASK                                          0x00038000L
//GUS_IO_WR_PRI_URGENCY_COEFF
#define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP0_URGENCY_COEFFICIENT__SHIFT                                        0x0
#define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP1_URGENCY_COEFFICIENT__SHIFT                                        0x3
#define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP2_URGENCY_COEFFICIENT__SHIFT                                        0x6
#define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP3_URGENCY_COEFFICIENT__SHIFT                                        0x9
#define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP4_URGENCY_COEFFICIENT__SHIFT                                        0xc
#define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP5_URGENCY_COEFFICIENT__SHIFT                                        0xf
#define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP0_URGENCY_COEFFICIENT_MASK                                          0x00000007L
#define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP1_URGENCY_COEFFICIENT_MASK                                          0x00000038L
#define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP2_URGENCY_COEFFICIENT_MASK                                          0x000001C0L
#define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP3_URGENCY_COEFFICIENT_MASK                                          0x00000E00L
#define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP4_URGENCY_COEFFICIENT_MASK                                          0x00007000L
#define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP5_URGENCY_COEFFICIENT_MASK                                          0x00038000L
//GUS_IO_RD_PRI_URGENCY_MODE
#define GUS_IO_RD_PRI_URGENCY_MODE__GROUP0_URGENCY_MODE__SHIFT                                                0x0
#define GUS_IO_RD_PRI_URGENCY_MODE__GROUP1_URGENCY_MODE__SHIFT                                                0x1
#define GUS_IO_RD_PRI_URGENCY_MODE__GROUP2_URGENCY_MODE__SHIFT                                                0x2
#define GUS_IO_RD_PRI_URGENCY_MODE__GROUP3_URGENCY_MODE__SHIFT                                                0x3
#define GUS_IO_RD_PRI_URGENCY_MODE__GROUP4_URGENCY_MODE__SHIFT                                                0x4
#define GUS_IO_RD_PRI_URGENCY_MODE__GROUP5_URGENCY_MODE__SHIFT                                                0x5
#define GUS_IO_RD_PRI_URGENCY_MODE__GROUP0_URGENCY_MODE_MASK                                                  0x00000001L
#define GUS_IO_RD_PRI_URGENCY_MODE__GROUP1_URGENCY_MODE_MASK                                                  0x00000002L
#define GUS_IO_RD_PRI_URGENCY_MODE__GROUP2_URGENCY_MODE_MASK                                                  0x00000004L
#define GUS_IO_RD_PRI_URGENCY_MODE__GROUP3_URGENCY_MODE_MASK                                                  0x00000008L
#define GUS_IO_RD_PRI_URGENCY_MODE__GROUP4_URGENCY_MODE_MASK                                                  0x00000010L
#define GUS_IO_RD_PRI_URGENCY_MODE__GROUP5_URGENCY_MODE_MASK                                                  0x00000020L
//GUS_IO_WR_PRI_URGENCY_MODE
#define GUS_IO_WR_PRI_URGENCY_MODE__GROUP0_URGENCY_MODE__SHIFT                                                0x0
#define GUS_IO_WR_PRI_URGENCY_MODE__GROUP1_URGENCY_MODE__SHIFT                                                0x1
#define GUS_IO_WR_PRI_URGENCY_MODE__GROUP2_URGENCY_MODE__SHIFT                                                0x2
#define GUS_IO_WR_PRI_URGENCY_MODE__GROUP3_URGENCY_MODE__SHIFT                                                0x3
#define GUS_IO_WR_PRI_URGENCY_MODE__GROUP4_URGENCY_MODE__SHIFT                                                0x4
#define GUS_IO_WR_PRI_URGENCY_MODE__GROUP5_URGENCY_MODE__SHIFT                                                0x5
#define GUS_IO_WR_PRI_URGENCY_MODE__GROUP0_URGENCY_MODE_MASK                                                  0x00000001L
#define GUS_IO_WR_PRI_URGENCY_MODE__GROUP1_URGENCY_MODE_MASK                                                  0x00000002L
#define GUS_IO_WR_PRI_URGENCY_MODE__GROUP2_URGENCY_MODE_MASK                                                  0x00000004L
#define GUS_IO_WR_PRI_URGENCY_MODE__GROUP3_URGENCY_MODE_MASK                                                  0x00000008L
#define GUS_IO_WR_PRI_URGENCY_MODE__GROUP4_URGENCY_MODE_MASK                                                  0x00000010L
#define GUS_IO_WR_PRI_URGENCY_MODE__GROUP5_URGENCY_MODE_MASK                                                  0x00000020L
//GUS_IO_RD_PRI_QUANT_PRI1
#define GUS_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                     0x0
#define GUS_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                     0x8
#define GUS_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                     0x10
#define GUS_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                     0x18
#define GUS_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                       0x000000FFL
#define GUS_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                       0x0000FF00L
#define GUS_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                       0x00FF0000L
#define GUS_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                       0xFF000000L
//GUS_IO_RD_PRI_QUANT_PRI2
#define GUS_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                     0x0
#define GUS_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                     0x8
#define GUS_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                     0x10
#define GUS_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                     0x18
#define GUS_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                       0x000000FFL
#define GUS_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                       0x0000FF00L
#define GUS_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                       0x00FF0000L
#define GUS_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                       0xFF000000L
//GUS_IO_RD_PRI_QUANT_PRI3
#define GUS_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                     0x0
#define GUS_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                     0x8
#define GUS_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                     0x10
#define GUS_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                     0x18
#define GUS_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                       0x000000FFL
#define GUS_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                       0x0000FF00L
#define GUS_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                       0x00FF0000L
#define GUS_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                       0xFF000000L
//GUS_IO_RD_PRI_QUANT_PRI4
#define GUS_IO_RD_PRI_QUANT_PRI4__GROUP0_THRESHOLD__SHIFT                                                     0x0
#define GUS_IO_RD_PRI_QUANT_PRI4__GROUP1_THRESHOLD__SHIFT                                                     0x8
#define GUS_IO_RD_PRI_QUANT_PRI4__GROUP2_THRESHOLD__SHIFT                                                     0x10
#define GUS_IO_RD_PRI_QUANT_PRI4__GROUP3_THRESHOLD__SHIFT                                                     0x18
#define GUS_IO_RD_PRI_QUANT_PRI4__GROUP0_THRESHOLD_MASK                                                       0x000000FFL
#define GUS_IO_RD_PRI_QUANT_PRI4__GROUP1_THRESHOLD_MASK                                                       0x0000FF00L
#define GUS_IO_RD_PRI_QUANT_PRI4__GROUP2_THRESHOLD_MASK                                                       0x00FF0000L
#define GUS_IO_RD_PRI_QUANT_PRI4__GROUP3_THRESHOLD_MASK                                                       0xFF000000L
//GUS_IO_WR_PRI_QUANT_PRI1
#define GUS_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                     0x0
#define GUS_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                     0x8
#define GUS_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                     0x10
#define GUS_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                     0x18
#define GUS_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                       0x000000FFL
#define GUS_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                       0x0000FF00L
#define GUS_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                       0x00FF0000L
#define GUS_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                       0xFF000000L
//GUS_IO_WR_PRI_QUANT_PRI2
#define GUS_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                     0x0
#define GUS_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                     0x8
#define GUS_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                     0x10
#define GUS_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                     0x18
#define GUS_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                       0x000000FFL
#define GUS_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                       0x0000FF00L
#define GUS_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                       0x00FF0000L
#define GUS_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                       0xFF000000L
//GUS_IO_WR_PRI_QUANT_PRI3
#define GUS_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                     0x0
#define GUS_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                     0x8
#define GUS_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                     0x10
#define GUS_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                     0x18
#define GUS_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                       0x000000FFL
#define GUS_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                       0x0000FF00L
#define GUS_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                       0x00FF0000L
#define GUS_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                       0xFF000000L
//GUS_IO_WR_PRI_QUANT_PRI4
#define GUS_IO_WR_PRI_QUANT_PRI4__GROUP0_THRESHOLD__SHIFT                                                     0x0
#define GUS_IO_WR_PRI_QUANT_PRI4__GROUP1_THRESHOLD__SHIFT                                                     0x8
#define GUS_IO_WR_PRI_QUANT_PRI4__GROUP2_THRESHOLD__SHIFT                                                     0x10
#define GUS_IO_WR_PRI_QUANT_PRI4__GROUP3_THRESHOLD__SHIFT                                                     0x18
#define GUS_IO_WR_PRI_QUANT_PRI4__GROUP0_THRESHOLD_MASK                                                       0x000000FFL
#define GUS_IO_WR_PRI_QUANT_PRI4__GROUP1_THRESHOLD_MASK                                                       0x0000FF00L
#define GUS_IO_WR_PRI_QUANT_PRI4__GROUP2_THRESHOLD_MASK                                                       0x00FF0000L
#define GUS_IO_WR_PRI_QUANT_PRI4__GROUP3_THRESHOLD_MASK                                                       0xFF000000L
//GUS_IO_RD_PRI_QUANT1_PRI1
#define GUS_IO_RD_PRI_QUANT1_PRI1__GROUP4_THRESHOLD__SHIFT                                                    0x0
#define GUS_IO_RD_PRI_QUANT1_PRI1__GROUP5_THRESHOLD__SHIFT                                                    0x8
#define GUS_IO_RD_PRI_QUANT1_PRI1__GROUP4_THRESHOLD_MASK                                                      0x000000FFL
#define GUS_IO_RD_PRI_QUANT1_PRI1__GROUP5_THRESHOLD_MASK                                                      0x0000FF00L
//GUS_IO_RD_PRI_QUANT1_PRI2
#define GUS_IO_RD_PRI_QUANT1_PRI2__GROUP4_THRESHOLD__SHIFT                                                    0x0
#define GUS_IO_RD_PRI_QUANT1_PRI2__GROUP5_THRESHOLD__SHIFT                                                    0x8
#define GUS_IO_RD_PRI_QUANT1_PRI2__GROUP4_THRESHOLD_MASK                                                      0x000000FFL
#define GUS_IO_RD_PRI_QUANT1_PRI2__GROUP5_THRESHOLD_MASK                                                      0x0000FF00L
//GUS_IO_RD_PRI_QUANT1_PRI3
#define GUS_IO_RD_PRI_QUANT1_PRI3__GROUP4_THRESHOLD__SHIFT                                                    0x0
#define GUS_IO_RD_PRI_QUANT1_PRI3__GROUP5_THRESHOLD__SHIFT                                                    0x8
#define GUS_IO_RD_PRI_QUANT1_PRI3__GROUP4_THRESHOLD_MASK                                                      0x000000FFL
#define GUS_IO_RD_PRI_QUANT1_PRI3__GROUP5_THRESHOLD_MASK                                                      0x0000FF00L
//GUS_IO_RD_PRI_QUANT1_PRI4
#define GUS_IO_RD_PRI_QUANT1_PRI4__GROUP4_THRESHOLD__SHIFT                                                    0x0
#define GUS_IO_RD_PRI_QUANT1_PRI4__GROUP5_THRESHOLD__SHIFT                                                    0x8
#define GUS_IO_RD_PRI_QUANT1_PRI4__GROUP4_THRESHOLD_MASK                                                      0x000000FFL
#define GUS_IO_RD_PRI_QUANT1_PRI4__GROUP5_THRESHOLD_MASK                                                      0x0000FF00L
//GUS_IO_WR_PRI_QUANT1_PRI1
#define GUS_IO_WR_PRI_QUANT1_PRI1__GROUP4_THRESHOLD__SHIFT                                                    0x0
#define GUS_IO_WR_PRI_QUANT1_PRI1__GROUP5_THRESHOLD__SHIFT                                                    0x8
#define GUS_IO_WR_PRI_QUANT1_PRI1__GROUP4_THRESHOLD_MASK                                                      0x000000FFL
#define GUS_IO_WR_PRI_QUANT1_PRI1__GROUP5_THRESHOLD_MASK                                                      0x0000FF00L
//GUS_IO_WR_PRI_QUANT1_PRI2
#define GUS_IO_WR_PRI_QUANT1_PRI2__GROUP4_THRESHOLD__SHIFT                                                    0x0
#define GUS_IO_WR_PRI_QUANT1_PRI2__GROUP5_THRESHOLD__SHIFT                                                    0x8
#define GUS_IO_WR_PRI_QUANT1_PRI2__GROUP4_THRESHOLD_MASK                                                      0x000000FFL
#define GUS_IO_WR_PRI_QUANT1_PRI2__GROUP5_THRESHOLD_MASK                                                      0x0000FF00L
//GUS_IO_WR_PRI_QUANT1_PRI3
#define GUS_IO_WR_PRI_QUANT1_PRI3__GROUP4_THRESHOLD__SHIFT                                                    0x0
#define GUS_IO_WR_PRI_QUANT1_PRI3__GROUP5_THRESHOLD__SHIFT                                                    0x8
#define GUS_IO_WR_PRI_QUANT1_PRI3__GROUP4_THRESHOLD_MASK                                                      0x000000FFL
#define GUS_IO_WR_PRI_QUANT1_PRI3__GROUP5_THRESHOLD_MASK                                                      0x0000FF00L
//GUS_IO_WR_PRI_QUANT1_PRI4
#define GUS_IO_WR_PRI_QUANT1_PRI4__GROUP4_THRESHOLD__SHIFT                                                    0x0
#define GUS_IO_WR_PRI_QUANT1_PRI4__GROUP5_THRESHOLD__SHIFT                                                    0x8
#define GUS_IO_WR_PRI_QUANT1_PRI4__GROUP4_THRESHOLD_MASK                                                      0x000000FFL
#define GUS_IO_WR_PRI_QUANT1_PRI4__GROUP5_THRESHOLD_MASK                                                      0x0000FF00L
//GUS_DRAM_COMBINE_FLUSH
#define GUS_DRAM_COMBINE_FLUSH__GROUP0_TIMER__SHIFT                                                           0x0
#define GUS_DRAM_COMBINE_FLUSH__GROUP1_TIMER__SHIFT                                                           0x4
#define GUS_DRAM_COMBINE_FLUSH__GROUP2_TIMER__SHIFT                                                           0x8
#define GUS_DRAM_COMBINE_FLUSH__GROUP3_TIMER__SHIFT                                                           0xc
#define GUS_DRAM_COMBINE_FLUSH__GROUP4_TIMER__SHIFT                                                           0x10
#define GUS_DRAM_COMBINE_FLUSH__GROUP5_TIMER__SHIFT                                                           0x14
#define GUS_DRAM_COMBINE_FLUSH__GROUP0_TIMER_MASK                                                             0x0000000FL
#define GUS_DRAM_COMBINE_FLUSH__GROUP1_TIMER_MASK                                                             0x000000F0L
#define GUS_DRAM_COMBINE_FLUSH__GROUP2_TIMER_MASK                                                             0x00000F00L
#define GUS_DRAM_COMBINE_FLUSH__GROUP3_TIMER_MASK                                                             0x0000F000L
#define GUS_DRAM_COMBINE_FLUSH__GROUP4_TIMER_MASK                                                             0x000F0000L
#define GUS_DRAM_COMBINE_FLUSH__GROUP5_TIMER_MASK                                                             0x00F00000L
//GUS_DRAM_COMBINE_RD_WR_EN
#define GUS_DRAM_COMBINE_RD_WR_EN__GROUP0_TIMER__SHIFT                                                        0x0
#define GUS_DRAM_COMBINE_RD_WR_EN__GROUP1_TIMER__SHIFT                                                        0x2
#define GUS_DRAM_COMBINE_RD_WR_EN__GROUP2_TIMER__SHIFT                                                        0x4
#define GUS_DRAM_COMBINE_RD_WR_EN__GROUP3_TIMER__SHIFT                                                        0x6
#define GUS_DRAM_COMBINE_RD_WR_EN__GROUP4_TIMER__SHIFT                                                        0x8
#define GUS_DRAM_COMBINE_RD_WR_EN__GROUP5_TIMER__SHIFT                                                        0xa
#define GUS_DRAM_COMBINE_RD_WR_EN__GROUP0_TIMER_MASK                                                          0x00000003L
#define GUS_DRAM_COMBINE_RD_WR_EN__GROUP1_TIMER_MASK                                                          0x0000000CL
#define GUS_DRAM_COMBINE_RD_WR_EN__GROUP2_TIMER_MASK                                                          0x00000030L
#define GUS_DRAM_COMBINE_RD_WR_EN__GROUP3_TIMER_MASK                                                          0x000000C0L
#define GUS_DRAM_COMBINE_RD_WR_EN__GROUP4_TIMER_MASK                                                          0x00000300L
#define GUS_DRAM_COMBINE_RD_WR_EN__GROUP5_TIMER_MASK                                                          0x00000C00L
//GUS_DRAM_PRI_AGE_RATE
#define GUS_DRAM_PRI_AGE_RATE__GROUP0_AGING_RATE__SHIFT                                                       0x0
#define GUS_DRAM_PRI_AGE_RATE__GROUP1_AGING_RATE__SHIFT                                                       0x3
#define GUS_DRAM_PRI_AGE_RATE__GROUP2_AGING_RATE__SHIFT                                                       0x6
#define GUS_DRAM_PRI_AGE_RATE__GROUP3_AGING_RATE__SHIFT                                                       0x9
#define GUS_DRAM_PRI_AGE_RATE__GROUP4_AGING_RATE__SHIFT                                                       0xc
#define GUS_DRAM_PRI_AGE_RATE__GROUP5_AGING_RATE__SHIFT                                                       0xf
#define GUS_DRAM_PRI_AGE_RATE__GROUP0_AGING_RATE_MASK                                                         0x00000007L
#define GUS_DRAM_PRI_AGE_RATE__GROUP1_AGING_RATE_MASK                                                         0x00000038L
#define GUS_DRAM_PRI_AGE_RATE__GROUP2_AGING_RATE_MASK                                                         0x000001C0L
#define GUS_DRAM_PRI_AGE_RATE__GROUP3_AGING_RATE_MASK                                                         0x00000E00L
#define GUS_DRAM_PRI_AGE_RATE__GROUP4_AGING_RATE_MASK                                                         0x00007000L
#define GUS_DRAM_PRI_AGE_RATE__GROUP5_AGING_RATE_MASK                                                         0x00038000L
//GUS_DRAM_PRI_AGE_COEFF
#define GUS_DRAM_PRI_AGE_COEFF__GROUP0_AGE_COEFFICIENT__SHIFT                                                 0x0
#define GUS_DRAM_PRI_AGE_COEFF__GROUP1_AGE_COEFFICIENT__SHIFT                                                 0x3
#define GUS_DRAM_PRI_AGE_COEFF__GROUP2_AGE_COEFFICIENT__SHIFT                                                 0x6
#define GUS_DRAM_PRI_AGE_COEFF__GROUP3_AGE_COEFFICIENT__SHIFT                                                 0x9
#define GUS_DRAM_PRI_AGE_COEFF__GROUP4_AGE_COEFFICIENT__SHIFT                                                 0xc
#define GUS_DRAM_PRI_AGE_COEFF__GROUP5_AGE_COEFFICIENT__SHIFT                                                 0xf
#define GUS_DRAM_PRI_AGE_COEFF__GROUP0_AGE_COEFFICIENT_MASK                                                   0x00000007L
#define GUS_DRAM_PRI_AGE_COEFF__GROUP1_AGE_COEFFICIENT_MASK                                                   0x00000038L
#define GUS_DRAM_PRI_AGE_COEFF__GROUP2_AGE_COEFFICIENT_MASK                                                   0x000001C0L
#define GUS_DRAM_PRI_AGE_COEFF__GROUP3_AGE_COEFFICIENT_MASK                                                   0x00000E00L
#define GUS_DRAM_PRI_AGE_COEFF__GROUP4_AGE_COEFFICIENT_MASK                                                   0x00007000L
#define GUS_DRAM_PRI_AGE_COEFF__GROUP5_AGE_COEFFICIENT_MASK                                                   0x00038000L
//GUS_DRAM_PRI_QUEUING
#define GUS_DRAM_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                               0x0
#define GUS_DRAM_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                               0x3
#define GUS_DRAM_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                               0x6
#define GUS_DRAM_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                               0x9
#define GUS_DRAM_PRI_QUEUING__GROUP4_QUEUING_COEFFICIENT__SHIFT                                               0xc
#define GUS_DRAM_PRI_QUEUING__GROUP5_QUEUING_COEFFICIENT__SHIFT                                               0xf
#define GUS_DRAM_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                                 0x00000007L
#define GUS_DRAM_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                                 0x00000038L
#define GUS_DRAM_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                                 0x000001C0L
#define GUS_DRAM_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                                 0x00000E00L
#define GUS_DRAM_PRI_QUEUING__GROUP4_QUEUING_COEFFICIENT_MASK                                                 0x00007000L
#define GUS_DRAM_PRI_QUEUING__GROUP5_QUEUING_COEFFICIENT_MASK                                                 0x00038000L
//GUS_DRAM_PRI_FIXED
#define GUS_DRAM_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                                   0x0
#define GUS_DRAM_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                                   0x3
#define GUS_DRAM_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                                   0x6
#define GUS_DRAM_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                                   0x9
#define GUS_DRAM_PRI_FIXED__GROUP4_FIXED_COEFFICIENT__SHIFT                                                   0xc
#define GUS_DRAM_PRI_FIXED__GROUP5_FIXED_COEFFICIENT__SHIFT                                                   0xf
#define GUS_DRAM_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                     0x00000007L
#define GUS_DRAM_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                     0x00000038L
#define GUS_DRAM_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                     0x000001C0L
#define GUS_DRAM_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                     0x00000E00L
#define GUS_DRAM_PRI_FIXED__GROUP4_FIXED_COEFFICIENT_MASK                                                     0x00007000L
#define GUS_DRAM_PRI_FIXED__GROUP5_FIXED_COEFFICIENT_MASK                                                     0x00038000L
//GUS_DRAM_PRI_URGENCY_COEFF
#define GUS_DRAM_PRI_URGENCY_COEFF__GROUP0_URGENCY_COEFFICIENT__SHIFT                                         0x0
#define GUS_DRAM_PRI_URGENCY_COEFF__GROUP1_URGENCY_COEFFICIENT__SHIFT                                         0x3
#define GUS_DRAM_PRI_URGENCY_COEFF__GROUP2_URGENCY_COEFFICIENT__SHIFT                                         0x6
#define GUS_DRAM_PRI_URGENCY_COEFF__GROUP3_URGENCY_COEFFICIENT__SHIFT                                         0x9
#define GUS_DRAM_PRI_URGENCY_COEFF__GROUP4_URGENCY_COEFFICIENT__SHIFT                                         0xc
#define GUS_DRAM_PRI_URGENCY_COEFF__GROUP5_URGENCY_COEFFICIENT__SHIFT                                         0xf
#define GUS_DRAM_PRI_URGENCY_COEFF__GROUP0_URGENCY_COEFFICIENT_MASK                                           0x00000007L
#define GUS_DRAM_PRI_URGENCY_COEFF__GROUP1_URGENCY_COEFFICIENT_MASK                                           0x00000038L
#define GUS_DRAM_PRI_URGENCY_COEFF__GROUP2_URGENCY_COEFFICIENT_MASK                                           0x000001C0L
#define GUS_DRAM_PRI_URGENCY_COEFF__GROUP3_URGENCY_COEFFICIENT_MASK                                           0x00000E00L
#define GUS_DRAM_PRI_URGENCY_COEFF__GROUP4_URGENCY_COEFFICIENT_MASK                                           0x00007000L
#define GUS_DRAM_PRI_URGENCY_COEFF__GROUP5_URGENCY_COEFFICIENT_MASK                                           0x00038000L
//GUS_DRAM_PRI_URGENCY_MODE
#define GUS_DRAM_PRI_URGENCY_MODE__GROUP0_URGENCY_MODE__SHIFT                                                 0x0
#define GUS_DRAM_PRI_URGENCY_MODE__GROUP1_URGENCY_MODE__SHIFT                                                 0x1
#define GUS_DRAM_PRI_URGENCY_MODE__GROUP2_URGENCY_MODE__SHIFT                                                 0x2
#define GUS_DRAM_PRI_URGENCY_MODE__GROUP3_URGENCY_MODE__SHIFT                                                 0x3
#define GUS_DRAM_PRI_URGENCY_MODE__GROUP4_URGENCY_MODE__SHIFT                                                 0x4
#define GUS_DRAM_PRI_URGENCY_MODE__GROUP5_URGENCY_MODE__SHIFT                                                 0x5
#define GUS_DRAM_PRI_URGENCY_MODE__GROUP0_URGENCY_MODE_MASK                                                   0x00000001L
#define GUS_DRAM_PRI_URGENCY_MODE__GROUP1_URGENCY_MODE_MASK                                                   0x00000002L
#define GUS_DRAM_PRI_URGENCY_MODE__GROUP2_URGENCY_MODE_MASK                                                   0x00000004L
#define GUS_DRAM_PRI_URGENCY_MODE__GROUP3_URGENCY_MODE_MASK                                                   0x00000008L
#define GUS_DRAM_PRI_URGENCY_MODE__GROUP4_URGENCY_MODE_MASK                                                   0x00000010L
#define GUS_DRAM_PRI_URGENCY_MODE__GROUP5_URGENCY_MODE_MASK                                                   0x00000020L
//GUS_DRAM_PRI_QUANT_PRI1
#define GUS_DRAM_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                      0x0
#define GUS_DRAM_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                      0x8
#define GUS_DRAM_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                      0x10
#define GUS_DRAM_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                      0x18
#define GUS_DRAM_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                        0x000000FFL
#define GUS_DRAM_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                        0x0000FF00L
#define GUS_DRAM_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                        0x00FF0000L
#define GUS_DRAM_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                        0xFF000000L
//GUS_DRAM_PRI_QUANT_PRI2
#define GUS_DRAM_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                      0x0
#define GUS_DRAM_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                      0x8
#define GUS_DRAM_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                      0x10
#define GUS_DRAM_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                      0x18
#define GUS_DRAM_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                        0x000000FFL
#define GUS_DRAM_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                        0x0000FF00L
#define GUS_DRAM_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                        0x00FF0000L
#define GUS_DRAM_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                        0xFF000000L
//GUS_DRAM_PRI_QUANT_PRI3
#define GUS_DRAM_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                      0x0
#define GUS_DRAM_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                      0x8
#define GUS_DRAM_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                      0x10
#define GUS_DRAM_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                      0x18
#define GUS_DRAM_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                        0x000000FFL
#define GUS_DRAM_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                        0x0000FF00L
#define GUS_DRAM_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                        0x00FF0000L
#define GUS_DRAM_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                        0xFF000000L
//GUS_DRAM_PRI_QUANT_PRI4
#define GUS_DRAM_PRI_QUANT_PRI4__GROUP0_THRESHOLD__SHIFT                                                      0x0
#define GUS_DRAM_PRI_QUANT_PRI4__GROUP1_THRESHOLD__SHIFT                                                      0x8
#define GUS_DRAM_PRI_QUANT_PRI4__GROUP2_THRESHOLD__SHIFT                                                      0x10
#define GUS_DRAM_PRI_QUANT_PRI4__GROUP3_THRESHOLD__SHIFT                                                      0x18
#define GUS_DRAM_PRI_QUANT_PRI4__GROUP0_THRESHOLD_MASK                                                        0x000000FFL
#define GUS_DRAM_PRI_QUANT_PRI4__GROUP1_THRESHOLD_MASK                                                        0x0000FF00L
#define GUS_DRAM_PRI_QUANT_PRI4__GROUP2_THRESHOLD_MASK                                                        0x00FF0000L
#define GUS_DRAM_PRI_QUANT_PRI4__GROUP3_THRESHOLD_MASK                                                        0xFF000000L
//GUS_DRAM_PRI_QUANT_PRI5
#define GUS_DRAM_PRI_QUANT_PRI5__GROUP0_THRESHOLD__SHIFT                                                      0x0
#define GUS_DRAM_PRI_QUANT_PRI5__GROUP1_THRESHOLD__SHIFT                                                      0x8
#define GUS_DRAM_PRI_QUANT_PRI5__GROUP2_THRESHOLD__SHIFT                                                      0x10
#define GUS_DRAM_PRI_QUANT_PRI5__GROUP3_THRESHOLD__SHIFT                                                      0x18
#define GUS_DRAM_PRI_QUANT_PRI5__GROUP0_THRESHOLD_MASK                                                        0x000000FFL
#define GUS_DRAM_PRI_QUANT_PRI5__GROUP1_THRESHOLD_MASK                                                        0x0000FF00L
#define GUS_DRAM_PRI_QUANT_PRI5__GROUP2_THRESHOLD_MASK                                                        0x00FF0000L
#define GUS_DRAM_PRI_QUANT_PRI5__GROUP3_THRESHOLD_MASK                                                        0xFF000000L
//GUS_DRAM_PRI_QUANT1_PRI1
#define GUS_DRAM_PRI_QUANT1_PRI1__GROUP4_THRESHOLD__SHIFT                                                     0x0
#define GUS_DRAM_PRI_QUANT1_PRI1__GROUP5_THRESHOLD__SHIFT                                                     0x8
#define GUS_DRAM_PRI_QUANT1_PRI1__GROUP4_THRESHOLD_MASK                                                       0x000000FFL
#define GUS_DRAM_PRI_QUANT1_PRI1__GROUP5_THRESHOLD_MASK                                                       0x0000FF00L
//GUS_DRAM_PRI_QUANT1_PRI2
#define GUS_DRAM_PRI_QUANT1_PRI2__GROUP4_THRESHOLD__SHIFT                                                     0x0
#define GUS_DRAM_PRI_QUANT1_PRI2__GROUP5_THRESHOLD__SHIFT                                                     0x8
#define GUS_DRAM_PRI_QUANT1_PRI2__GROUP4_THRESHOLD_MASK                                                       0x000000FFL
#define GUS_DRAM_PRI_QUANT1_PRI2__GROUP5_THRESHOLD_MASK                                                       0x0000FF00L
//GUS_DRAM_PRI_QUANT1_PRI3
#define GUS_DRAM_PRI_QUANT1_PRI3__GROUP4_THRESHOLD__SHIFT                                                     0x0
#define GUS_DRAM_PRI_QUANT1_PRI3__GROUP5_THRESHOLD__SHIFT                                                     0x8
#define GUS_DRAM_PRI_QUANT1_PRI3__GROUP4_THRESHOLD_MASK                                                       0x000000FFL
#define GUS_DRAM_PRI_QUANT1_PRI3__GROUP5_THRESHOLD_MASK                                                       0x0000FF00L
//GUS_DRAM_PRI_QUANT1_PRI4
#define GUS_DRAM_PRI_QUANT1_PRI4__GROUP4_THRESHOLD__SHIFT                                                     0x0
#define GUS_DRAM_PRI_QUANT1_PRI4__GROUP5_THRESHOLD__SHIFT                                                     0x8
#define GUS_DRAM_PRI_QUANT1_PRI4__GROUP4_THRESHOLD_MASK                                                       0x000000FFL
#define GUS_DRAM_PRI_QUANT1_PRI4__GROUP5_THRESHOLD_MASK                                                       0x0000FF00L
//GUS_DRAM_PRI_QUANT1_PRI5
#define GUS_DRAM_PRI_QUANT1_PRI5__GROUP4_THRESHOLD__SHIFT                                                     0x0
#define GUS_DRAM_PRI_QUANT1_PRI5__GROUP5_THRESHOLD__SHIFT                                                     0x8
#define GUS_DRAM_PRI_QUANT1_PRI5__GROUP4_THRESHOLD_MASK                                                       0x000000FFL
#define GUS_DRAM_PRI_QUANT1_PRI5__GROUP5_THRESHOLD_MASK                                                       0x0000FF00L
//GUS_IO_GROUP_BURST
#define GUS_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT                                                                0x0
#define GUS_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT                                                                0x8
#define GUS_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT                                                                0x10
#define GUS_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT                                                                0x18
#define GUS_IO_GROUP_BURST__RD_LIMIT_LO_MASK                                                                  0x000000FFL
#define GUS_IO_GROUP_BURST__RD_LIMIT_HI_MASK                                                                  0x0000FF00L
#define GUS_IO_GROUP_BURST__WR_LIMIT_LO_MASK                                                                  0x00FF0000L
#define GUS_IO_GROUP_BURST__WR_LIMIT_HI_MASK                                                                  0xFF000000L
//GUS_DRAM_GROUP_BURST
#define GUS_DRAM_GROUP_BURST__DRAM_LIMIT_LO__SHIFT                                                            0x0
#define GUS_DRAM_GROUP_BURST__DRAM_LIMIT_HI__SHIFT                                                            0x8
#define GUS_DRAM_GROUP_BURST__DRAM_LIMIT_LO_MASK                                                              0x000000FFL
#define GUS_DRAM_GROUP_BURST__DRAM_LIMIT_HI_MASK                                                              0x0000FF00L
//GUS_SDP_ARB_FINAL
#define GUS_SDP_ARB_FINAL__HI_DRAM_BURST_LIMIT__SHIFT                                                         0x0
#define GUS_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT                                                            0x5
#define GUS_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT                                                              0xa
#define GUS_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT                                                      0xf
#define GUS_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT                                                           0x11
#define GUS_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT                                                            0x12
#define GUS_SDP_ARB_FINAL__HI_DRAM_BURST_LIMIT_MASK                                                           0x0000001FL
#define GUS_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK                                                              0x000003E0L
#define GUS_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK                                                                0x00007C00L
#define GUS_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK                                                        0x00018000L
#define GUS_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK                                                             0x00020000L
#define GUS_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK                                                              0x00040000L
//GUS_SDP_QOS_VC_PRIORITY
#define GUS_SDP_QOS_VC_PRIORITY__VC2_IORD__SHIFT                                                              0x0
#define GUS_SDP_QOS_VC_PRIORITY__VC3_IOWR__SHIFT                                                              0x4
#define GUS_SDP_QOS_VC_PRIORITY__VC4_DRAM__SHIFT                                                              0x8
#define GUS_SDP_QOS_VC_PRIORITY__VC4_HI_DRAM__SHIFT                                                           0xc
#define GUS_SDP_QOS_VC_PRIORITY__VC2_IORD_MASK                                                                0x0000000FL
#define GUS_SDP_QOS_VC_PRIORITY__VC3_IOWR_MASK                                                                0x000000F0L
#define GUS_SDP_QOS_VC_PRIORITY__VC4_DRAM_MASK                                                                0x00000F00L
#define GUS_SDP_QOS_VC_PRIORITY__VC4_HI_DRAM_MASK                                                             0x0000F000L
//GUS_SDP_CREDITS
#define GUS_SDP_CREDITS__TAG_LIMIT__SHIFT                                                                     0x0
#define GUS_SDP_CREDITS__WR_RESP_CREDITS__SHIFT                                                               0x8
#define GUS_SDP_CREDITS__RD_RESP_CREDITS__SHIFT                                                               0x10
#define GUS_SDP_CREDITS__TAG_LIMIT_MASK                                                                       0x000000FFL
#define GUS_SDP_CREDITS__WR_RESP_CREDITS_MASK                                                                 0x00007F00L
#define GUS_SDP_CREDITS__RD_RESP_CREDITS_MASK                                                                 0x007F0000L
//GUS_SDP_TAG_RESERVE0
#define GUS_SDP_TAG_RESERVE0__VC0__SHIFT                                                                      0x0
#define GUS_SDP_TAG_RESERVE0__VC1__SHIFT                                                                      0x8
#define GUS_SDP_TAG_RESERVE0__VC2__SHIFT                                                                      0x10
#define GUS_SDP_TAG_RESERVE0__VC3__SHIFT                                                                      0x18
#define GUS_SDP_TAG_RESERVE0__VC0_MASK                                                                        0x000000FFL
#define GUS_SDP_TAG_RESERVE0__VC1_MASK                                                                        0x0000FF00L
#define GUS_SDP_TAG_RESERVE0__VC2_MASK                                                                        0x00FF0000L
#define GUS_SDP_TAG_RESERVE0__VC3_MASK                                                                        0xFF000000L
//GUS_SDP_TAG_RESERVE1
#define GUS_SDP_TAG_RESERVE1__VC4__SHIFT                                                                      0x0
#define GUS_SDP_TAG_RESERVE1__VC5__SHIFT                                                                      0x8
#define GUS_SDP_TAG_RESERVE1__VC6__SHIFT                                                                      0x10
#define GUS_SDP_TAG_RESERVE1__VC7__SHIFT                                                                      0x18
#define GUS_SDP_TAG_RESERVE1__VC4_MASK                                                                        0x000000FFL
#define GUS_SDP_TAG_RESERVE1__VC5_MASK                                                                        0x0000FF00L
#define GUS_SDP_TAG_RESERVE1__VC6_MASK                                                                        0x00FF0000L
#define GUS_SDP_TAG_RESERVE1__VC7_MASK                                                                        0xFF000000L
//GUS_SDP_VCC_RESERVE0
#define GUS_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT                                                              0x0
#define GUS_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT                                                              0x6
#define GUS_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT                                                              0xc
#define GUS_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT                                                              0x12
#define GUS_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT                                                              0x18
#define GUS_SDP_VCC_RESERVE0__VC0_CREDITS_MASK                                                                0x0000003FL
#define GUS_SDP_VCC_RESERVE0__VC1_CREDITS_MASK                                                                0x00000FC0L
#define GUS_SDP_VCC_RESERVE0__VC2_CREDITS_MASK                                                                0x0003F000L
#define GUS_SDP_VCC_RESERVE0__VC3_CREDITS_MASK                                                                0x00FC0000L
#define GUS_SDP_VCC_RESERVE0__VC4_CREDITS_MASK                                                                0x3F000000L
//GUS_SDP_VCC_RESERVE1
#define GUS_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT                                                              0x0
#define GUS_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT                                                              0x6
#define GUS_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT                                                              0xc
#define GUS_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT                                                          0x1f
#define GUS_SDP_VCC_RESERVE1__VC5_CREDITS_MASK                                                                0x0000003FL
#define GUS_SDP_VCC_RESERVE1__VC6_CREDITS_MASK                                                                0x00000FC0L
#define GUS_SDP_VCC_RESERVE1__VC7_CREDITS_MASK                                                                0x0003F000L
#define GUS_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK                                                            0x80000000L
//GUS_SDP_VCD_RESERVE0
#define GUS_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT                                                              0x0
#define GUS_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT                                                              0x6
#define GUS_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT                                                              0xc
#define GUS_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT                                                              0x12
#define GUS_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT                                                              0x18
#define GUS_SDP_VCD_RESERVE0__VC0_CREDITS_MASK                                                                0x0000003FL
#define GUS_SDP_VCD_RESERVE0__VC1_CREDITS_MASK                                                                0x00000FC0L
#define GUS_SDP_VCD_RESERVE0__VC2_CREDITS_MASK                                                                0x0003F000L
#define GUS_SDP_VCD_RESERVE0__VC3_CREDITS_MASK                                                                0x00FC0000L
#define GUS_SDP_VCD_RESERVE0__VC4_CREDITS_MASK                                                                0x3F000000L
//GUS_SDP_VCD_RESERVE1
#define GUS_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT                                                              0x0
#define GUS_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT                                                              0x6
#define GUS_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT                                                              0xc
#define GUS_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT                                                          0x1f
#define GUS_SDP_VCD_RESERVE1__VC5_CREDITS_MASK                                                                0x0000003FL
#define GUS_SDP_VCD_RESERVE1__VC6_CREDITS_MASK                                                                0x00000FC0L
#define GUS_SDP_VCD_RESERVE1__VC7_CREDITS_MASK                                                                0x0003F000L
#define GUS_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK                                                            0x80000000L
//GUS_SDP_REQ_CNTL
#define GUS_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT                                                    0x0
#define GUS_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT                                                   0x1
#define GUS_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT                                                  0x2
#define GUS_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT                                                      0x3
#define GUS_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT                                                            0x4
#define GUS_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK                                                      0x00000001L
#define GUS_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK                                                     0x00000002L
#define GUS_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK                                                    0x00000004L
#define GUS_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK                                                        0x00000008L
#define GUS_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK                                                              0x00000010L
//GUS_MISC
#define GUS_MISC__RELATIVE_PRI_IN_DRAM_ARB__SHIFT                                                             0x0
#define GUS_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT                                                            0x1
#define GUS_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT                                                            0x2
#define GUS_MISC__EARLY_SDP_ORIGDATA__SHIFT                                                                   0x3
#define GUS_MISC__LINKMGR_DYNAMIC_MODE__SHIFT                                                                 0x4
#define GUS_MISC__LINKMGR_HALT_THRESHOLD__SHIFT                                                               0x6
#define GUS_MISC__LINKMGR_RECONNECT_DELAY__SHIFT                                                              0x8
#define GUS_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT                                                               0xa
#define GUS_MISC__SEND0_IOWR_ONLY__SHIFT                                                                      0xf
#define GUS_MISC__RELATIVE_PRI_IN_DRAM_ARB_MASK                                                               0x00000001L
#define GUS_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK                                                              0x00000002L
#define GUS_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK                                                              0x00000004L
#define GUS_MISC__EARLY_SDP_ORIGDATA_MASK                                                                     0x00000008L
#define GUS_MISC__LINKMGR_DYNAMIC_MODE_MASK                                                                   0x00000030L
#define GUS_MISC__LINKMGR_HALT_THRESHOLD_MASK                                                                 0x000000C0L
#define GUS_MISC__LINKMGR_RECONNECT_DELAY_MASK                                                                0x00000300L
#define GUS_MISC__LINKMGR_IDLE_THRESHOLD_MASK                                                                 0x00007C00L
#define GUS_MISC__SEND0_IOWR_ONLY_MASK                                                                        0x00008000L
//GUS_LATENCY_SAMPLING
#define GUS_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT                                                            0x0
#define GUS_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT                                                            0x1
#define GUS_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT                                                              0x2
#define GUS_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT                                                              0x3
#define GUS_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT                                                            0x4
#define GUS_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT                                                            0x5
#define GUS_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT                                                           0x6
#define GUS_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT                                                           0x7
#define GUS_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT                                                      0x8
#define GUS_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT                                                      0x9
#define GUS_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT                                                    0xa
#define GUS_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT                                                    0xb
#define GUS_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT                                                              0xc
#define GUS_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT                                                              0x14
#define GUS_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK                                                              0x00000001L
#define GUS_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK                                                              0x00000002L
#define GUS_LATENCY_SAMPLING__SAMPLER0_IO_MASK                                                                0x00000004L
#define GUS_LATENCY_SAMPLING__SAMPLER1_IO_MASK                                                                0x00000008L
#define GUS_LATENCY_SAMPLING__SAMPLER0_READ_MASK                                                              0x00000010L
#define GUS_LATENCY_SAMPLING__SAMPLER1_READ_MASK                                                              0x00000020L
#define GUS_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK                                                             0x00000040L
#define GUS_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK                                                             0x00000080L
#define GUS_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK                                                        0x00000100L
#define GUS_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK                                                        0x00000200L
#define GUS_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK                                                      0x00000400L
#define GUS_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK                                                      0x00000800L
#define GUS_LATENCY_SAMPLING__SAMPLER0_VC_MASK                                                                0x000FF000L
#define GUS_LATENCY_SAMPLING__SAMPLER1_VC_MASK                                                                0x0FF00000L
//GUS_ERR_STATUS
#define GUS_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT                                                               0x0
#define GUS_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT                                                               0x4
#define GUS_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT                                                           0x8
#define GUS_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT                                                     0xa
#define GUS_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT                                                             0xb
#define GUS_ERR_STATUS__BUSY_ON_ERROR__SHIFT                                                                  0xc
#define GUS_ERR_STATUS__FUE_FLAG__SHIFT                                                                       0xd
#define GUS_ERR_STATUS__SDP_RDRSP_STATUS_MASK                                                                 0x0000000FL
#define GUS_ERR_STATUS__SDP_WRRSP_STATUS_MASK                                                                 0x000000F0L
#define GUS_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK                                                             0x00000300L
#define GUS_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK                                                       0x00000400L
#define GUS_ERR_STATUS__CLEAR_ERROR_STATUS_MASK                                                               0x00000800L
#define GUS_ERR_STATUS__BUSY_ON_ERROR_MASK                                                                    0x00001000L
#define GUS_ERR_STATUS__FUE_FLAG_MASK                                                                         0x00002000L
//GUS_MISC2
#define GUS_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT                                                             0x0
#define GUS_MISC2__CH_L1_RO_MASK__SHIFT                                                                       0x1
#define GUS_MISC2__SA0_L1_RO_MASK__SHIFT                                                                      0x2
#define GUS_MISC2__SA1_L1_RO_MASK__SHIFT                                                                      0x3
#define GUS_MISC2__SA2_L1_RO_MASK__SHIFT                                                                      0x4
#define GUS_MISC2__SA3_L1_RO_MASK__SHIFT                                                                      0x5
#define GUS_MISC2__CH_L1_PERF_MASK__SHIFT                                                                     0x6
#define GUS_MISC2__SA0_L1_PERF_MASK__SHIFT                                                                    0x7
#define GUS_MISC2__SA1_L1_PERF_MASK__SHIFT                                                                    0x8
#define GUS_MISC2__SA2_L1_PERF_MASK__SHIFT                                                                    0x9
#define GUS_MISC2__SA3_L1_PERF_MASK__SHIFT                                                                    0xa
#define GUS_MISC2__FP_ATOMICS_ENABLE__SHIFT                                                                   0xb
#define GUS_MISC2__L1_RET_CLKEN__SHIFT                                                                        0xc
#define GUS_MISC2__FGCLKEN_HIGH__SHIFT                                                                        0xd
#define GUS_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK                                                               0x00000001L
#define GUS_MISC2__CH_L1_RO_MASK_MASK                                                                         0x00000002L
#define GUS_MISC2__SA0_L1_RO_MASK_MASK                                                                        0x00000004L
#define GUS_MISC2__SA1_L1_RO_MASK_MASK                                                                        0x00000008L
#define GUS_MISC2__SA2_L1_RO_MASK_MASK                                                                        0x00000010L
#define GUS_MISC2__SA3_L1_RO_MASK_MASK                                                                        0x00000020L
#define GUS_MISC2__CH_L1_PERF_MASK_MASK                                                                       0x00000040L
#define GUS_MISC2__SA0_L1_PERF_MASK_MASK                                                                      0x00000080L
#define GUS_MISC2__SA1_L1_PERF_MASK_MASK                                                                      0x00000100L
#define GUS_MISC2__SA2_L1_PERF_MASK_MASK                                                                      0x00000200L
#define GUS_MISC2__SA3_L1_PERF_MASK_MASK                                                                      0x00000400L
#define GUS_MISC2__FP_ATOMICS_ENABLE_MASK                                                                     0x00000800L
#define GUS_MISC2__L1_RET_CLKEN_MASK                                                                          0x00001000L
#define GUS_MISC2__FGCLKEN_HIGH_MASK                                                                          0x00002000L
//GUS_SDP_ENABLE
#define GUS_SDP_ENABLE__ENABLE__SHIFT                                                                         0x0
#define GUS_SDP_ENABLE__ENABLE_MASK                                                                           0x00000001L
//GUS_L1_CH0_CMD_IN
#define GUS_L1_CH0_CMD_IN__COUNT__SHIFT                                                                       0x0
#define GUS_L1_CH0_CMD_IN__COUNT_MASK                                                                         0xFFFFFFFFL
//GUS_L1_CH0_CMD_OUT
#define GUS_L1_CH0_CMD_OUT__COUNT__SHIFT                                                                      0x0
#define GUS_L1_CH0_CMD_OUT__COUNT_MASK                                                                        0xFFFFFFFFL
//GUS_L1_CH0_DATA_IN
#define GUS_L1_CH0_DATA_IN__COUNT__SHIFT                                                                      0x0
#define GUS_L1_CH0_DATA_IN__COUNT_MASK                                                                        0xFFFFFFFFL
//GUS_L1_CH0_DATA_OUT
#define GUS_L1_CH0_DATA_OUT__COUNT__SHIFT                                                                     0x0
#define GUS_L1_CH0_DATA_OUT__COUNT_MASK                                                                       0xFFFFFFFFL
//GUS_L1_CH0_DATA_U_IN
#define GUS_L1_CH0_DATA_U_IN__COUNT__SHIFT                                                                    0x0
#define GUS_L1_CH0_DATA_U_IN__COUNT_MASK                                                                      0xFFFFFFFFL
//GUS_L1_CH0_DATA_U_OUT
#define GUS_L1_CH0_DATA_U_OUT__COUNT__SHIFT                                                                   0x0
#define GUS_L1_CH0_DATA_U_OUT__COUNT_MASK                                                                     0xFFFFFFFFL
//GUS_L1_CH1_CMD_IN
#define GUS_L1_CH1_CMD_IN__COUNT__SHIFT                                                                       0x0
#define GUS_L1_CH1_CMD_IN__COUNT_MASK                                                                         0xFFFFFFFFL
//GUS_L1_CH1_CMD_OUT
#define GUS_L1_CH1_CMD_OUT__COUNT__SHIFT                                                                      0x0
#define GUS_L1_CH1_CMD_OUT__COUNT_MASK                                                                        0xFFFFFFFFL
//GUS_L1_CH1_DATA_IN
#define GUS_L1_CH1_DATA_IN__COUNT__SHIFT                                                                      0x0
#define GUS_L1_CH1_DATA_IN__COUNT_MASK                                                                        0xFFFFFFFFL
//GUS_L1_CH1_DATA_OUT
#define GUS_L1_CH1_DATA_OUT__COUNT__SHIFT                                                                     0x0
#define GUS_L1_CH1_DATA_OUT__COUNT_MASK                                                                       0xFFFFFFFFL
//GUS_L1_CH1_DATA_U_IN
#define GUS_L1_CH1_DATA_U_IN__COUNT__SHIFT                                                                    0x0
#define GUS_L1_CH1_DATA_U_IN__COUNT_MASK                                                                      0xFFFFFFFFL
//GUS_L1_CH1_DATA_U_OUT
#define GUS_L1_CH1_DATA_U_OUT__COUNT__SHIFT                                                                   0x0
#define GUS_L1_CH1_DATA_U_OUT__COUNT_MASK                                                                     0xFFFFFFFFL
//GUS_L1_SA0_CMD_IN
#define GUS_L1_SA0_CMD_IN__COUNT__SHIFT                                                                       0x0
#define GUS_L1_SA0_CMD_IN__COUNT_MASK                                                                         0xFFFFFFFFL
//GUS_L1_SA0_CMD_OUT
#define GUS_L1_SA0_CMD_OUT__COUNT__SHIFT                                                                      0x0
#define GUS_L1_SA0_CMD_OUT__COUNT_MASK                                                                        0xFFFFFFFFL
//GUS_L1_SA0_DATA_IN
#define GUS_L1_SA0_DATA_IN__COUNT__SHIFT                                                                      0x0
#define GUS_L1_SA0_DATA_IN__COUNT_MASK                                                                        0xFFFFFFFFL
//GUS_L1_SA0_DATA_OUT
#define GUS_L1_SA0_DATA_OUT__COUNT__SHIFT                                                                     0x0
#define GUS_L1_SA0_DATA_OUT__COUNT_MASK                                                                       0xFFFFFFFFL
//GUS_L1_SA0_DATA_U_IN
#define GUS_L1_SA0_DATA_U_IN__COUNT__SHIFT                                                                    0x0
#define GUS_L1_SA0_DATA_U_IN__COUNT_MASK                                                                      0xFFFFFFFFL
//GUS_L1_SA0_DATA_U_OUT
#define GUS_L1_SA0_DATA_U_OUT__COUNT__SHIFT                                                                   0x0
#define GUS_L1_SA0_DATA_U_OUT__COUNT_MASK                                                                     0xFFFFFFFFL
//GUS_L1_SA1_CMD_IN
#define GUS_L1_SA1_CMD_IN__COUNT__SHIFT                                                                       0x0
#define GUS_L1_SA1_CMD_IN__COUNT_MASK                                                                         0xFFFFFFFFL
//GUS_L1_SA1_CMD_OUT
#define GUS_L1_SA1_CMD_OUT__COUNT__SHIFT                                                                      0x0
#define GUS_L1_SA1_CMD_OUT__COUNT_MASK                                                                        0xFFFFFFFFL
//GUS_L1_SA1_DATA_IN
#define GUS_L1_SA1_DATA_IN__COUNT__SHIFT                                                                      0x0
#define GUS_L1_SA1_DATA_IN__COUNT_MASK                                                                        0xFFFFFFFFL
//GUS_L1_SA1_DATA_OUT
#define GUS_L1_SA1_DATA_OUT__COUNT__SHIFT                                                                     0x0
#define GUS_L1_SA1_DATA_OUT__COUNT_MASK                                                                       0xFFFFFFFFL
//GUS_L1_SA1_DATA_U_IN
#define GUS_L1_SA1_DATA_U_IN__COUNT__SHIFT                                                                    0x0
#define GUS_L1_SA1_DATA_U_IN__COUNT_MASK                                                                      0xFFFFFFFFL
//GUS_L1_SA1_DATA_U_OUT
#define GUS_L1_SA1_DATA_U_OUT__COUNT__SHIFT                                                                   0x0
#define GUS_L1_SA1_DATA_U_OUT__COUNT_MASK                                                                     0xFFFFFFFFL
//GUS_L1_SA2_CMD_IN
#define GUS_L1_SA2_CMD_IN__COUNT__SHIFT                                                                       0x0
#define GUS_L1_SA2_CMD_IN__COUNT_MASK                                                                         0xFFFFFFFFL
//GUS_L1_SA2_CMD_OUT
#define GUS_L1_SA2_CMD_OUT__COUNT__SHIFT                                                                      0x0
#define GUS_L1_SA2_CMD_OUT__COUNT_MASK                                                                        0xFFFFFFFFL
//GUS_L1_SA2_DATA_IN
#define GUS_L1_SA2_DATA_IN__COUNT__SHIFT                                                                      0x0
#define GUS_L1_SA2_DATA_IN__COUNT_MASK                                                                        0xFFFFFFFFL
//GUS_L1_SA2_DATA_OUT
#define GUS_L1_SA2_DATA_OUT__COUNT__SHIFT                                                                     0x0
#define GUS_L1_SA2_DATA_OUT__COUNT_MASK                                                                       0xFFFFFFFFL
//GUS_L1_SA2_DATA_U_IN
#define GUS_L1_SA2_DATA_U_IN__COUNT__SHIFT                                                                    0x0
#define GUS_L1_SA2_DATA_U_IN__COUNT_MASK                                                                      0xFFFFFFFFL
//GUS_L1_SA2_DATA_U_OUT
#define GUS_L1_SA2_DATA_U_OUT__COUNT__SHIFT                                                                   0x0
#define GUS_L1_SA2_DATA_U_OUT__COUNT_MASK                                                                     0xFFFFFFFFL
//GUS_L1_SA3_CMD_IN
#define GUS_L1_SA3_CMD_IN__COUNT__SHIFT                                                                       0x0
#define GUS_L1_SA3_CMD_IN__COUNT_MASK                                                                         0xFFFFFFFFL
//GUS_L1_SA3_CMD_OUT
#define GUS_L1_SA3_CMD_OUT__COUNT__SHIFT                                                                      0x0
#define GUS_L1_SA3_CMD_OUT__COUNT_MASK                                                                        0xFFFFFFFFL
//GUS_L1_SA3_DATA_IN
#define GUS_L1_SA3_DATA_IN__COUNT__SHIFT                                                                      0x0
#define GUS_L1_SA3_DATA_IN__COUNT_MASK                                                                        0xFFFFFFFFL
//GUS_L1_SA3_DATA_OUT
#define GUS_L1_SA3_DATA_OUT__COUNT__SHIFT                                                                     0x0
#define GUS_L1_SA3_DATA_OUT__COUNT_MASK                                                                       0xFFFFFFFFL
//GUS_L1_SA3_DATA_U_IN
#define GUS_L1_SA3_DATA_U_IN__COUNT__SHIFT                                                                    0x0
#define GUS_L1_SA3_DATA_U_IN__COUNT_MASK                                                                      0xFFFFFFFFL
//GUS_L1_SA3_DATA_U_OUT
#define GUS_L1_SA3_DATA_U_OUT__COUNT__SHIFT                                                                   0x0
#define GUS_L1_SA3_DATA_U_OUT__COUNT_MASK                                                                     0xFFFFFFFFL
//GUS_MISC3
#define GUS_MISC3__FP_ATOMICS_LOG__SHIFT                                                                      0x0
#define GUS_MISC3__CLEAR_LOG__SHIFT                                                                           0x1
#define GUS_MISC3__FP_ATOMICS_LOG_MASK                                                                        0x00000001L
#define GUS_MISC3__CLEAR_LOG_MASK                                                                             0x00000002L
//GUS_WRRSP_FIFO_CNTL
#define GUS_WRRSP_FIFO_CNTL__THRESHOLD__SHIFT                                                                 0x0
#define GUS_WRRSP_FIFO_CNTL__THRESHOLD_MASK                                                                   0x0000003FL


// addressBlock: gc_gl1dec
//GL1_DRAM_BURST_MASK
#define GL1_DRAM_BURST_MASK__DRAM_BURST_ADDR_MASK__SHIFT                                                      0x0
#define GL1_DRAM_BURST_MASK__DRAM_BURST_ADDR_MASK_MASK                                                        0x000000FFL
//GL1_ARB_STATUS
#define GL1_ARB_STATUS__REQ_ARB_BUSY__SHIFT                                                                   0x0
#define GL1_ARB_STATUS__RET_ARB_BUSY__SHIFT                                                                   0x1
#define GL1_ARB_STATUS__REQ_ARB_BUSY_MASK                                                                     0x00000001L
#define GL1_ARB_STATUS__RET_ARB_BUSY_MASK                                                                     0x00000002L
//GL1_PIPE_STEER
#define GL1_PIPE_STEER__PIPE0__SHIFT                                                                          0x0
#define GL1_PIPE_STEER__PIPE1__SHIFT                                                                          0x2
#define GL1_PIPE_STEER__PIPE2__SHIFT                                                                          0x4
#define GL1_PIPE_STEER__PIPE3__SHIFT                                                                          0x6
#define GL1_PIPE_STEER__PIPE0_MASK                                                                            0x00000003L
#define GL1_PIPE_STEER__PIPE1_MASK                                                                            0x0000000CL
#define GL1_PIPE_STEER__PIPE2_MASK                                                                            0x00000030L
#define GL1_PIPE_STEER__PIPE3_MASK                                                                            0x000000C0L
//GL1C_STATUS
#define GL1C_STATUS__INPUT_BUFFER_VC0_FIFO_FULL__SHIFT                                                        0x0
#define GL1C_STATUS__OUTPUT_FIFOS_BUSY__SHIFT                                                                 0x1
#define GL1C_STATUS__SRC_DATA_FIFO_VC0_FULL__SHIFT                                                            0x2
#define GL1C_STATUS__GL2_REQ_VC0_STALL__SHIFT                                                                 0x3
#define GL1C_STATUS__GL2_DATA_VC0_STALL__SHIFT                                                                0x4
#define GL1C_STATUS__GL2_REQ_VC1_STALL__SHIFT                                                                 0x5
#define GL1C_STATUS__GL2_DATA_VC1_STALL__SHIFT                                                                0x6
#define GL1C_STATUS__INPUT_BUFFER_VC0_BUSY__SHIFT                                                             0x7
#define GL1C_STATUS__SRC_DATA_FIFO_VC0_BUSY__SHIFT                                                            0x8
#define GL1C_STATUS__GL2_RH_BUSY__SHIFT                                                                       0x9
#define GL1C_STATUS__NUM_REQ_PENDING_FROM_L2__SHIFT                                                           0xa
#define GL1C_STATUS__LATENCY_FIFO_FULL_STALL__SHIFT                                                           0x14
#define GL1C_STATUS__TAG_STALL__SHIFT                                                                         0x15
#define GL1C_STATUS__TAG_BUSY__SHIFT                                                                          0x16
#define GL1C_STATUS__TAG_ACK_STALL__SHIFT                                                                     0x17
#define GL1C_STATUS__TAG_GCR_INV_STALL__SHIFT                                                                 0x18
#define GL1C_STATUS__TAG_NO_AVAILABLE_LINE_TO_EVICT_STALL__SHIFT                                              0x19
#define GL1C_STATUS__TAG_EVICT__SHIFT                                                                         0x1a
#define GL1C_STATUS__TAG_REQUEST_STATE_OPERATION__SHIFT                                                       0x1b
#define GL1C_STATUS__TRACKER_LAST_SET_MATCHES_CURRENT_SET__SHIFT                                              0x1f
#define GL1C_STATUS__INPUT_BUFFER_VC0_FIFO_FULL_MASK                                                          0x00000001L
#define GL1C_STATUS__OUTPUT_FIFOS_BUSY_MASK                                                                   0x00000002L
#define GL1C_STATUS__SRC_DATA_FIFO_VC0_FULL_MASK                                                              0x00000004L
#define GL1C_STATUS__GL2_REQ_VC0_STALL_MASK                                                                   0x00000008L
#define GL1C_STATUS__GL2_DATA_VC0_STALL_MASK                                                                  0x00000010L
#define GL1C_STATUS__GL2_REQ_VC1_STALL_MASK                                                                   0x00000020L
#define GL1C_STATUS__GL2_DATA_VC1_STALL_MASK                                                                  0x00000040L
#define GL1C_STATUS__INPUT_BUFFER_VC0_BUSY_MASK                                                               0x00000080L
#define GL1C_STATUS__SRC_DATA_FIFO_VC0_BUSY_MASK                                                              0x00000100L
#define GL1C_STATUS__GL2_RH_BUSY_MASK                                                                         0x00000200L
#define GL1C_STATUS__NUM_REQ_PENDING_FROM_L2_MASK                                                             0x000FFC00L
#define GL1C_STATUS__LATENCY_FIFO_FULL_STALL_MASK                                                             0x00100000L
#define GL1C_STATUS__TAG_STALL_MASK                                                                           0x00200000L
#define GL1C_STATUS__TAG_BUSY_MASK                                                                            0x00400000L
#define GL1C_STATUS__TAG_ACK_STALL_MASK                                                                       0x00800000L
#define GL1C_STATUS__TAG_GCR_INV_STALL_MASK                                                                   0x01000000L
#define GL1C_STATUS__TAG_NO_AVAILABLE_LINE_TO_EVICT_STALL_MASK                                                0x02000000L
#define GL1C_STATUS__TAG_EVICT_MASK                                                                           0x04000000L
#define GL1C_STATUS__TAG_REQUEST_STATE_OPERATION_MASK                                                         0x78000000L
#define GL1C_STATUS__TRACKER_LAST_SET_MATCHES_CURRENT_SET_MASK                                                0x80000000L
//GL1C_UTCL0_CNTL2
#define GL1C_UTCL0_CNTL2__SPARE__SHIFT                                                                        0x0
#define GL1C_UTCL0_CNTL2__COMP_SYNC_DISABLE__SHIFT                                                            0x8
#define GL1C_UTCL0_CNTL2__MTYPE_OVRD_DIS__SHIFT                                                               0x9
#define GL1C_UTCL0_CNTL2__ANY_LINE_VALID__SHIFT                                                               0xa
#define GL1C_UTCL0_CNTL2__GPUVM_INV_MODE__SHIFT                                                               0xc
#define GL1C_UTCL0_CNTL2__FORCE_SNOOP__SHIFT                                                                  0xe
#define GL1C_UTCL0_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT                                                          0xf
#define GL1C_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT                                                         0x1a
#define GL1C_UTCL0_CNTL2__PERM_MODE_OVRD__SHIFT                                                               0x1b
#define GL1C_UTCL0_CNTL2__LINE_INVALIDATE_OPT__SHIFT                                                          0x1c
#define GL1C_UTCL0_CNTL2__GPUVM_16K_DEFAULT__SHIFT                                                            0x1d
#define GL1C_UTCL0_CNTL2__FGCG_DISABLE__SHIFT                                                                 0x1e
#define GL1C_UTCL0_CNTL2__BIG_PAGE_DISABLE__SHIFT                                                             0x1f
#define GL1C_UTCL0_CNTL2__SPARE_MASK                                                                          0x000000FFL
#define GL1C_UTCL0_CNTL2__COMP_SYNC_DISABLE_MASK                                                              0x00000100L
#define GL1C_UTCL0_CNTL2__MTYPE_OVRD_DIS_MASK                                                                 0x00000200L
#define GL1C_UTCL0_CNTL2__ANY_LINE_VALID_MASK                                                                 0x00000400L
#define GL1C_UTCL0_CNTL2__GPUVM_INV_MODE_MASK                                                                 0x00001000L
#define GL1C_UTCL0_CNTL2__FORCE_SNOOP_MASK                                                                    0x00004000L
#define GL1C_UTCL0_CNTL2__FORCE_GPUVM_INV_ACK_MASK                                                            0x00008000L
#define GL1C_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K_MASK                                                           0x04000000L
#define GL1C_UTCL0_CNTL2__PERM_MODE_OVRD_MASK                                                                 0x08000000L
#define GL1C_UTCL0_CNTL2__LINE_INVALIDATE_OPT_MASK                                                            0x10000000L
#define GL1C_UTCL0_CNTL2__GPUVM_16K_DEFAULT_MASK                                                              0x20000000L
#define GL1C_UTCL0_CNTL2__FGCG_DISABLE_MASK                                                                   0x40000000L
#define GL1C_UTCL0_CNTL2__BIG_PAGE_DISABLE_MASK                                                               0x80000000L
//GL1C_UTCL0_STATUS
#define GL1C_UTCL0_STATUS__FAULT_DETECTED__SHIFT                                                              0x0
#define GL1C_UTCL0_STATUS__RETRY_DETECTED__SHIFT                                                              0x1
#define GL1C_UTCL0_STATUS__PRT_DETECTED__SHIFT                                                                0x2
#define GL1C_UTCL0_STATUS__FAULT_DETECTED_MASK                                                                0x00000001L
#define GL1C_UTCL0_STATUS__RETRY_DETECTED_MASK                                                                0x00000002L
#define GL1C_UTCL0_STATUS__PRT_DETECTED_MASK                                                                  0x00000004L
//GL1C_UTCL0_RETRY
#define GL1C_UTCL0_RETRY__INCR__SHIFT                                                                         0x0
#define GL1C_UTCL0_RETRY__COUNT__SHIFT                                                                        0x8
#define GL1C_UTCL0_RETRY__INCR_MASK                                                                           0x000000FFL
#define GL1C_UTCL0_RETRY__COUNT_MASK                                                                          0x00000F00L


// addressBlock: gc_chdec
//CH_ARB_CTRL
#define CH_ARB_CTRL__NUM_MEM_PIPES__SHIFT                                                                     0x0
#define CH_ARB_CTRL__UC_IO_WR_PATH__SHIFT                                                                     0x2
#define CH_ARB_CTRL__FGCG_DISABLE__SHIFT                                                                      0x3
#define CH_ARB_CTRL__CHICKEN_BITS__SHIFT                                                                      0x4
#define CH_ARB_CTRL__NUM_MEM_PIPES_MASK                                                                       0x00000003L
#define CH_ARB_CTRL__UC_IO_WR_PATH_MASK                                                                       0x00000004L
#define CH_ARB_CTRL__FGCG_DISABLE_MASK                                                                        0x00000008L
#define CH_ARB_CTRL__CHICKEN_BITS_MASK                                                                        0x00000FF0L
//CH_DRAM_BURST_MASK
#define CH_DRAM_BURST_MASK__DRAM_BURST_ADDR_MASK__SHIFT                                                       0x0
#define CH_DRAM_BURST_MASK__DRAM_BURST_ADDR_MASK_MASK                                                         0x000000FFL
//CH_ARB_STATUS
#define CH_ARB_STATUS__REQ_ARB_BUSY__SHIFT                                                                    0x0
#define CH_ARB_STATUS__RET_ARB_BUSY__SHIFT                                                                    0x1
#define CH_ARB_STATUS__REQ_ARB_BUSY_MASK                                                                      0x00000001L
#define CH_ARB_STATUS__RET_ARB_BUSY_MASK                                                                      0x00000002L
//CH_DRAM_BURST_CTRL
#define CH_DRAM_BURST_CTRL__MAX_DRAM_BURST__SHIFT                                                             0x0
#define CH_DRAM_BURST_CTRL__BURST_DISABLE__SHIFT                                                              0x3
#define CH_DRAM_BURST_CTRL__GATHER_64B_MEMORY_BURST_DISABLE__SHIFT                                            0x4
#define CH_DRAM_BURST_CTRL__GATHER_64B_IO_BURST_DISABLE__SHIFT                                                0x5
#define CH_DRAM_BURST_CTRL__GATHER_32B_MEMORY_BURST_DISABLE__SHIFT                                            0x6
#define CH_DRAM_BURST_CTRL__GATHER_32B_IO_BURST_DISABLE__SHIFT                                                0x7
#define CH_DRAM_BURST_CTRL__WRITE_BURSTABLE_STALL_DISABLE__SHIFT                                              0x8
#define CH_DRAM_BURST_CTRL__MAX_DRAM_BURST_MASK                                                               0x00000007L
#define CH_DRAM_BURST_CTRL__BURST_DISABLE_MASK                                                                0x00000008L
#define CH_DRAM_BURST_CTRL__GATHER_64B_MEMORY_BURST_DISABLE_MASK                                              0x00000010L
#define CH_DRAM_BURST_CTRL__GATHER_64B_IO_BURST_DISABLE_MASK                                                  0x00000020L
#define CH_DRAM_BURST_CTRL__GATHER_32B_MEMORY_BURST_DISABLE_MASK                                              0x00000040L
#define CH_DRAM_BURST_CTRL__GATHER_32B_IO_BURST_DISABLE_MASK                                                  0x00000080L
#define CH_DRAM_BURST_CTRL__WRITE_BURSTABLE_STALL_DISABLE_MASK                                                0x00000100L
//CHA_CHC_CREDITS
#define CHA_CHC_CREDITS__CHC_REQ_CREDITS__SHIFT                                                               0x0
#define CHA_CHC_CREDITS__CHCG_REQ_CREDITS__SHIFT                                                              0x8
#define CHA_CHC_CREDITS__CHC_REQ_CREDITS_MASK                                                                 0x000000FFL
#define CHA_CHC_CREDITS__CHCG_REQ_CREDITS_MASK                                                                0x0000FF00L
//CHA_CLIENT_FREE_DELAY
#define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_0_FREE_DELAY__SHIFT                                                0x0
#define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_1_FREE_DELAY__SHIFT                                                0x3
#define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_2_FREE_DELAY__SHIFT                                                0x6
#define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_3_FREE_DELAY__SHIFT                                                0x9
#define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_4_FREE_DELAY__SHIFT                                                0xc
#define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_5_FREE_DELAY__SHIFT                                                0xf
#define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_6_FREE_DELAY__SHIFT                                                0x12
#define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_7_FREE_DELAY__SHIFT                                                0x15
#define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_8_FREE_DELAY__SHIFT                                                0x18
#define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_9_FREE_DELAY__SHIFT                                                0x1b
#define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_0_FREE_DELAY_MASK                                                  0x00000007L
#define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_1_FREE_DELAY_MASK                                                  0x00000038L
#define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_2_FREE_DELAY_MASK                                                  0x000001C0L
#define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_3_FREE_DELAY_MASK                                                  0x00000E00L
#define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_4_FREE_DELAY_MASK                                                  0x00007000L
#define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_5_FREE_DELAY_MASK                                                  0x00038000L
#define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_6_FREE_DELAY_MASK                                                  0x001C0000L
#define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_7_FREE_DELAY_MASK                                                  0x00E00000L
#define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_8_FREE_DELAY_MASK                                                  0x07000000L
#define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_9_FREE_DELAY_MASK                                                  0x38000000L
//CH_PIPE_STEER
#define CH_PIPE_STEER__PIPE0__SHIFT                                                                           0x0
#define CH_PIPE_STEER__PIPE1__SHIFT                                                                           0x2
#define CH_PIPE_STEER__PIPE2__SHIFT                                                                           0x4
#define CH_PIPE_STEER__PIPE3__SHIFT                                                                           0x6
#define CH_PIPE_STEER__PIPE0_MASK                                                                             0x00000003L
#define CH_PIPE_STEER__PIPE1_MASK                                                                             0x0000000CL
#define CH_PIPE_STEER__PIPE2_MASK                                                                             0x00000030L
#define CH_PIPE_STEER__PIPE3_MASK                                                                             0x000000C0L
//CH_VC5_ENABLE
#define CH_VC5_ENABLE__UTCL2_VC5_ENABLE__SHIFT                                                                0x1
#define CH_VC5_ENABLE__UTCL2_VC5_ENABLE_MASK                                                                  0x00000002L
//CHC_CTRL
#define CHC_CTRL__BUFFER_DEPTH_MAX__SHIFT                                                                     0x0
#define CHC_CTRL__GL2_REQ_CREDITS__SHIFT                                                                      0x4
#define CHC_CTRL__GL2_DATA_CREDITS__SHIFT                                                                     0xb
#define CHC_CTRL__TO_L1_REPEATER_FGCG_DISABLE__SHIFT                                                          0x12
#define CHC_CTRL__TO_L2_REPEATER_FGCG_DISABLE__SHIFT                                                          0x13
#define CHC_CTRL__BUFFER_DEPTH_MAX_MASK                                                                       0x0000000FL
#define CHC_CTRL__GL2_REQ_CREDITS_MASK                                                                        0x000007F0L
#define CHC_CTRL__GL2_DATA_CREDITS_MASK                                                                       0x0003F800L
#define CHC_CTRL__TO_L1_REPEATER_FGCG_DISABLE_MASK                                                            0x00040000L
#define CHC_CTRL__TO_L2_REPEATER_FGCG_DISABLE_MASK                                                            0x00080000L
//CHC_STATUS
#define CHC_STATUS__INPUT_BUFFER_VC0_FIFO_FULL__SHIFT                                                         0x0
#define CHC_STATUS__OUTPUT_FIFOS_BUSY__SHIFT                                                                  0x1
#define CHC_STATUS__SRC_DATA_FIFO_VC0_FULL__SHIFT                                                             0x2
#define CHC_STATUS__GL2_REQ_VC0_STALL__SHIFT                                                                  0x3
#define CHC_STATUS__GL2_DATA_VC0_STALL__SHIFT                                                                 0x4
#define CHC_STATUS__GL2_REQ_VC1_STALL__SHIFT                                                                  0x5
#define CHC_STATUS__GL2_DATA_VC1_STALL__SHIFT                                                                 0x6
#define CHC_STATUS__INPUT_BUFFER_VC0_BUSY__SHIFT                                                              0x7
#define CHC_STATUS__SRC_DATA_FIFO_VC0_BUSY__SHIFT                                                             0x8
#define CHC_STATUS__GL2_RH_BUSY__SHIFT                                                                        0x9
#define CHC_STATUS__NUM_REQ_PENDING_FROM_L2__SHIFT                                                            0xa
#define CHC_STATUS__VIRTUAL_FIFO_FULL_STALL__SHIFT                                                            0x14
#define CHC_STATUS__REQUEST_TRACKER_BUFFER_STALL__SHIFT                                                       0x15
#define CHC_STATUS__REQUEST_TRACKER_BUSY__SHIFT                                                               0x16
#define CHC_STATUS__BUFFER_FULL__SHIFT                                                                        0x17
#define CHC_STATUS__INPUT_BUFFER_VC0_FIFO_FULL_MASK                                                           0x00000001L
#define CHC_STATUS__OUTPUT_FIFOS_BUSY_MASK                                                                    0x00000002L
#define CHC_STATUS__SRC_DATA_FIFO_VC0_FULL_MASK                                                               0x00000004L
#define CHC_STATUS__GL2_REQ_VC0_STALL_MASK                                                                    0x00000008L
#define CHC_STATUS__GL2_DATA_VC0_STALL_MASK                                                                   0x00000010L
#define CHC_STATUS__GL2_REQ_VC1_STALL_MASK                                                                    0x00000020L
#define CHC_STATUS__GL2_DATA_VC1_STALL_MASK                                                                   0x00000040L
#define CHC_STATUS__INPUT_BUFFER_VC0_BUSY_MASK                                                                0x00000080L
#define CHC_STATUS__SRC_DATA_FIFO_VC0_BUSY_MASK                                                               0x00000100L
#define CHC_STATUS__GL2_RH_BUSY_MASK                                                                          0x00000200L
#define CHC_STATUS__NUM_REQ_PENDING_FROM_L2_MASK                                                              0x000FFC00L
#define CHC_STATUS__VIRTUAL_FIFO_FULL_STALL_MASK                                                              0x00100000L
#define CHC_STATUS__REQUEST_TRACKER_BUFFER_STALL_MASK                                                         0x00200000L
#define CHC_STATUS__REQUEST_TRACKER_BUSY_MASK                                                                 0x00400000L
#define CHC_STATUS__BUFFER_FULL_MASK                                                                          0x00800000L
//CHCG_CTRL
#define CHCG_CTRL__BUFFER_DEPTH_MAX__SHIFT                                                                    0x0
#define CHCG_CTRL__VC0_BUFFER_DEPTH_MAX__SHIFT                                                                0x4
#define CHCG_CTRL__GL2_REQ_CREDITS__SHIFT                                                                     0x8
#define CHCG_CTRL__GL2_DATA_CREDITS__SHIFT                                                                    0xf
#define CHCG_CTRL__TO_L1_REPEATER_FGCG_DISABLE__SHIFT                                                         0x16
#define CHCG_CTRL__TO_L2_REPEATER_FGCG_DISABLE__SHIFT                                                         0x17
#define CHCG_CTRL__BUFFER_DEPTH_MAX_MASK                                                                      0x0000000FL
#define CHCG_CTRL__VC0_BUFFER_DEPTH_MAX_MASK                                                                  0x000000F0L
#define CHCG_CTRL__GL2_REQ_CREDITS_MASK                                                                       0x00007F00L
#define CHCG_CTRL__GL2_DATA_CREDITS_MASK                                                                      0x003F8000L
#define CHCG_CTRL__TO_L1_REPEATER_FGCG_DISABLE_MASK                                                           0x00400000L
#define CHCG_CTRL__TO_L2_REPEATER_FGCG_DISABLE_MASK                                                           0x00800000L
//CHCG_STATUS
#define CHCG_STATUS__INPUT_BUFFER_VC0_FIFO_FULL__SHIFT                                                        0x0
#define CHCG_STATUS__OUTPUT_FIFOS_BUSY__SHIFT                                                                 0x1
#define CHCG_STATUS__SRC_DATA_FIFO_VC0_FULL__SHIFT                                                            0x2
#define CHCG_STATUS__GL2_REQ_VC0_STALL__SHIFT                                                                 0x3
#define CHCG_STATUS__GL2_DATA_VC0_STALL__SHIFT                                                                0x4
#define CHCG_STATUS__GL2_REQ_VC1_STALL__SHIFT                                                                 0x5
#define CHCG_STATUS__GL2_DATA_VC1_STALL__SHIFT                                                                0x6
#define CHCG_STATUS__INPUT_BUFFER_VC0_BUSY__SHIFT                                                             0x7
#define CHCG_STATUS__SRC_DATA_FIFO_VC0_BUSY__SHIFT                                                            0x8
#define CHCG_STATUS__GL2_RH_BUSY__SHIFT                                                                       0x9
#define CHCG_STATUS__NUM_REQ_PENDING_FROM_L2__SHIFT                                                           0xa
#define CHCG_STATUS__VIRTUAL_FIFO_FULL_STALL__SHIFT                                                           0x14
#define CHCG_STATUS__REQUEST_TRACKER_BUFFER_STALL__SHIFT                                                      0x15
#define CHCG_STATUS__REQUEST_TRACKER_BUSY__SHIFT                                                              0x16
#define CHCG_STATUS__BUFFER_FULL__SHIFT                                                                       0x17
#define CHCG_STATUS__INPUT_BUFFER_VC1_BUSY__SHIFT                                                             0x18
#define CHCG_STATUS__SRC_DATA_FIFO_VC1_BUSY__SHIFT                                                            0x19
#define CHCG_STATUS__INPUT_BUFFER_VC1_FIFO_FULL__SHIFT                                                        0x1a
#define CHCG_STATUS__SRC_DATA_FIFO_VC1_FULL__SHIFT                                                            0x1b
#define CHCG_STATUS__INPUT_BUFFER_VC0_FIFO_FULL_MASK                                                          0x00000001L
#define CHCG_STATUS__OUTPUT_FIFOS_BUSY_MASK                                                                   0x00000002L
#define CHCG_STATUS__SRC_DATA_FIFO_VC0_FULL_MASK                                                              0x00000004L
#define CHCG_STATUS__GL2_REQ_VC0_STALL_MASK                                                                   0x00000008L
#define CHCG_STATUS__GL2_DATA_VC0_STALL_MASK                                                                  0x00000010L
#define CHCG_STATUS__GL2_REQ_VC1_STALL_MASK                                                                   0x00000020L
#define CHCG_STATUS__GL2_DATA_VC1_STALL_MASK                                                                  0x00000040L
#define CHCG_STATUS__INPUT_BUFFER_VC0_BUSY_MASK                                                               0x00000080L
#define CHCG_STATUS__SRC_DATA_FIFO_VC0_BUSY_MASK                                                              0x00000100L
#define CHCG_STATUS__GL2_RH_BUSY_MASK                                                                         0x00000200L
#define CHCG_STATUS__NUM_REQ_PENDING_FROM_L2_MASK                                                             0x000FFC00L
#define CHCG_STATUS__VIRTUAL_FIFO_FULL_STALL_MASK                                                             0x00100000L
#define CHCG_STATUS__REQUEST_TRACKER_BUFFER_STALL_MASK                                                        0x00200000L
#define CHCG_STATUS__REQUEST_TRACKER_BUSY_MASK                                                                0x00400000L
#define CHCG_STATUS__BUFFER_FULL_MASK                                                                         0x00800000L
#define CHCG_STATUS__INPUT_BUFFER_VC1_BUSY_MASK                                                               0x01000000L
#define CHCG_STATUS__SRC_DATA_FIFO_VC1_BUSY_MASK                                                              0x02000000L
#define CHCG_STATUS__INPUT_BUFFER_VC1_FIFO_FULL_MASK                                                          0x04000000L
#define CHCG_STATUS__SRC_DATA_FIFO_VC1_FULL_MASK                                                              0x08000000L


// addressBlock: gc_gl2dec
//GL2C_CTRL
#define GL2C_CTRL__CACHE_SIZE__SHIFT                                                                          0x0
#define GL2C_CTRL__RATE__SHIFT                                                                                0x2
#define GL2C_CTRL__WRITEBACK_MARGIN__SHIFT                                                                    0x4
#define GL2C_CTRL__METADATA_LATENCY_FIFO_SIZE__SHIFT                                                          0x8
#define GL2C_CTRL__SRC_FIFO_SIZE__SHIFT                                                                       0xc
#define GL2C_CTRL__LATENCY_FIFO_SIZE__SHIFT                                                                   0x10
#define GL2C_CTRL__METADATA_TO_HI_PRIORITY__SHIFT                                                             0x14
#define GL2C_CTRL__FORCE_HIT_QUEUE_POP__SHIFT                                                                 0x16
#define GL2C_CTRL__MDC_SIZE__SHIFT                                                                            0x18
#define GL2C_CTRL__METADATA_TO_HIT_QUEUE__SHIFT                                                               0x1a
#define GL2C_CTRL__IGNORE_FULLY_WRITTEN__SHIFT                                                                0x1b
#define GL2C_CTRL__MDC_SIDEBAND_FIFO_SIZE__SHIFT                                                              0x1c
#define GL2C_CTRL__CACHE_SIZE_MASK                                                                            0x00000003L
#define GL2C_CTRL__RATE_MASK                                                                                  0x0000000CL
#define GL2C_CTRL__WRITEBACK_MARGIN_MASK                                                                      0x000000F0L
#define GL2C_CTRL__METADATA_LATENCY_FIFO_SIZE_MASK                                                            0x00000F00L
#define GL2C_CTRL__SRC_FIFO_SIZE_MASK                                                                         0x0000F000L
#define GL2C_CTRL__LATENCY_FIFO_SIZE_MASK                                                                     0x000F0000L
#define GL2C_CTRL__METADATA_TO_HI_PRIORITY_MASK                                                               0x00100000L
#define GL2C_CTRL__FORCE_HIT_QUEUE_POP_MASK                                                                   0x00C00000L
#define GL2C_CTRL__MDC_SIZE_MASK                                                                              0x03000000L
#define GL2C_CTRL__METADATA_TO_HIT_QUEUE_MASK                                                                 0x04000000L
#define GL2C_CTRL__IGNORE_FULLY_WRITTEN_MASK                                                                  0x08000000L
#define GL2C_CTRL__MDC_SIDEBAND_FIFO_SIZE_MASK                                                                0xF0000000L
//GL2C_CTRL2
#define GL2C_CTRL2__PROBE_FIFO_SIZE__SHIFT                                                                    0x0
#define GL2C_CTRL2__ADDR_MATCH_DISABLE__SHIFT                                                                 0x4
#define GL2C_CTRL2__FILL_SIZE_32__SHIFT                                                                       0x5
#define GL2C_CTRL2__RB_TO_HI_PRIORITY__SHIFT                                                                  0x6
#define GL2C_CTRL2__HIT_UNDER_MISS_DISABLE__SHIFT                                                             0x7
#define GL2C_CTRL2__RO_DISABLE__SHIFT                                                                         0x8
#define GL2C_CTRL2__FORCE_MDC_INV__SHIFT                                                                      0x9
#define GL2C_CTRL2__GCR_ARB_CTRL__SHIFT                                                                       0xa
#define GL2C_CTRL2__GCR_ALL_SET__SHIFT                                                                        0xd
#define GL2C_CTRL2__MDC_PF_BLOCK__SHIFT                                                                       0xe
#define GL2C_CTRL2__MDC_PF_MAX_SIZE__SHIFT                                                                    0x10
#define GL2C_CTRL2__FILL_SIZE_64__SHIFT                                                                       0x11
#define GL2C_CTRL2__USE_EA_EARLYWRRET_ON_WRITEBACK__SHIFT                                                     0x12
#define GL2C_CTRL2__WRITEBACK_ALL_WAIT_FOR_ALL_EA_WRITE_COMPLETE__SHIFT                                       0x13
#define GL2C_CTRL2__METADATA_VOLATILE_EN__SHIFT                                                               0x14
#define GL2C_CTRL2__RB_VOLATILE_EN__SHIFT                                                                     0x15
#define GL2C_CTRL2__PROBE_UNSHARED_EN__SHIFT                                                                  0x16
#define GL2C_CTRL2__MAX_MIN_CTRL__SHIFT                                                                       0x17
#define GL2C_CTRL2__MDC_PF_LINEAR_METADATA__SHIFT                                                             0x19
#define GL2C_CTRL2__MDC_UC_TO_C_RO_EN__SHIFT                                                                  0x1a
#define GL2C_CTRL2__MDC_PF_MIN_PAGE_SIZE__SHIFT                                                               0x1b
#define GL2C_CTRL2__MDC_PF_DISABLE__SHIFT                                                                     0x1d
#define GL2C_CTRL2__PROBE_FIFO_SIZE_MASK                                                                      0x0000000FL
#define GL2C_CTRL2__ADDR_MATCH_DISABLE_MASK                                                                   0x00000010L
#define GL2C_CTRL2__FILL_SIZE_32_MASK                                                                         0x00000020L
#define GL2C_CTRL2__RB_TO_HI_PRIORITY_MASK                                                                    0x00000040L
#define GL2C_CTRL2__HIT_UNDER_MISS_DISABLE_MASK                                                               0x00000080L
#define GL2C_CTRL2__RO_DISABLE_MASK                                                                           0x00000100L
#define GL2C_CTRL2__FORCE_MDC_INV_MASK                                                                        0x00000200L
#define GL2C_CTRL2__GCR_ARB_CTRL_MASK                                                                         0x00001C00L
#define GL2C_CTRL2__GCR_ALL_SET_MASK                                                                          0x00002000L
#define GL2C_CTRL2__MDC_PF_BLOCK_MASK                                                                         0x0000C000L
#define GL2C_CTRL2__MDC_PF_MAX_SIZE_MASK                                                                      0x00010000L
#define GL2C_CTRL2__FILL_SIZE_64_MASK                                                                         0x00020000L
#define GL2C_CTRL2__USE_EA_EARLYWRRET_ON_WRITEBACK_MASK                                                       0x00040000L
#define GL2C_CTRL2__WRITEBACK_ALL_WAIT_FOR_ALL_EA_WRITE_COMPLETE_MASK                                         0x00080000L
#define GL2C_CTRL2__METADATA_VOLATILE_EN_MASK                                                                 0x00100000L
#define GL2C_CTRL2__RB_VOLATILE_EN_MASK                                                                       0x00200000L
#define GL2C_CTRL2__PROBE_UNSHARED_EN_MASK                                                                    0x00400000L
#define GL2C_CTRL2__MAX_MIN_CTRL_MASK                                                                         0x01800000L
#define GL2C_CTRL2__MDC_PF_LINEAR_METADATA_MASK                                                               0x02000000L
#define GL2C_CTRL2__MDC_UC_TO_C_RO_EN_MASK                                                                    0x04000000L
#define GL2C_CTRL2__MDC_PF_MIN_PAGE_SIZE_MASK                                                                 0x18000000L
#define GL2C_CTRL2__MDC_PF_DISABLE_MASK                                                                       0xE0000000L
//GL2C_ADDR_MATCH_MASK
#define GL2C_ADDR_MATCH_MASK__ADDR_MASK__SHIFT                                                                0x0
#define GL2C_ADDR_MATCH_MASK__ADDR_MASK_MASK                                                                  0xFFFFFFFFL
//GL2C_ADDR_MATCH_SIZE
#define GL2C_ADDR_MATCH_SIZE__MAX_COUNT__SHIFT                                                                0x0
#define GL2C_ADDR_MATCH_SIZE__MAX_COUNT_MASK                                                                  0x00000007L
//GL2C_WBINVL2
#define GL2C_WBINVL2__DONE__SHIFT                                                                             0x4
#define GL2C_WBINVL2__DONE_MASK                                                                               0x00000010L
//GL2C_SOFT_RESET
#define GL2C_SOFT_RESET__HALT_FOR_RESET__SHIFT                                                                0x0
#define GL2C_SOFT_RESET__HALT_FOR_RESET_MASK                                                                  0x00000001L
//GL2C_CM_CTRL0
//GL2C_CM_CTRL1
#define GL2C_CM_CTRL1__BURST_TIMER__SHIFT                                                                     0x8
#define GL2C_CM_CTRL1__RVF_SIZE__SHIFT                                                                        0x10
#define GL2C_CM_CTRL1__WRITE_COH_MODE__SHIFT                                                                  0x17
#define GL2C_CM_CTRL1__MDC_ARB_MODE__SHIFT                                                                    0x19
#define GL2C_CM_CTRL1__READ_REQ_ONLY__SHIFT                                                                   0x1a
#define GL2C_CM_CTRL1__COMP_TO_CONSTANT_EN__SHIFT                                                             0x1b
#define GL2C_CM_CTRL1__COMP_TO_SINGLE_EN__SHIFT                                                               0x1c
#define GL2C_CM_CTRL1__BURST_MODE__SHIFT                                                                      0x1d
#define GL2C_CM_CTRL1__UNCOMP_READBACK_FILTER__SHIFT                                                          0x1e
#define GL2C_CM_CTRL1__WAIT_ATOMIC_RECOMP_WRITE__SHIFT                                                        0x1f
#define GL2C_CM_CTRL1__BURST_TIMER_MASK                                                                       0x0000FF00L
#define GL2C_CM_CTRL1__RVF_SIZE_MASK                                                                          0x000F0000L
#define GL2C_CM_CTRL1__WRITE_COH_MODE_MASK                                                                    0x01800000L
#define GL2C_CM_CTRL1__MDC_ARB_MODE_MASK                                                                      0x02000000L
#define GL2C_CM_CTRL1__READ_REQ_ONLY_MASK                                                                     0x04000000L
#define GL2C_CM_CTRL1__COMP_TO_CONSTANT_EN_MASK                                                               0x08000000L
#define GL2C_CM_CTRL1__COMP_TO_SINGLE_EN_MASK                                                                 0x10000000L
#define GL2C_CM_CTRL1__BURST_MODE_MASK                                                                        0x20000000L
#define GL2C_CM_CTRL1__UNCOMP_READBACK_FILTER_MASK                                                            0x40000000L
#define GL2C_CM_CTRL1__WAIT_ATOMIC_RECOMP_WRITE_MASK                                                          0x80000000L
//GL2C_CM_STALL
#define GL2C_CM_STALL__QUEUE__SHIFT                                                                           0x0
#define GL2C_CM_STALL__QUEUE_MASK                                                                             0xFFFFFFFFL
//GL2C_MDC_PF_FLAG_CTRL
#define GL2C_MDC_PF_FLAG_CTRL__TIMER__SHIFT                                                                   0x0
#define GL2C_MDC_PF_FLAG_CTRL__TIMER_MASK                                                                     0xFFFFFFFFL
//GL2C_LB_CTR_CTRL
#define GL2C_LB_CTR_CTRL__START__SHIFT                                                                        0x0
#define GL2C_LB_CTR_CTRL__LOAD__SHIFT                                                                         0x1
#define GL2C_LB_CTR_CTRL__CLEAR__SHIFT                                                                        0x2
#define GL2C_LB_CTR_CTRL__PERF_CNTR_EN_OVERRIDE__SHIFT                                                        0x1f
#define GL2C_LB_CTR_CTRL__START_MASK                                                                          0x00000001L
#define GL2C_LB_CTR_CTRL__LOAD_MASK                                                                           0x00000002L
#define GL2C_LB_CTR_CTRL__CLEAR_MASK                                                                          0x00000004L
#define GL2C_LB_CTR_CTRL__PERF_CNTR_EN_OVERRIDE_MASK                                                          0x80000000L
//GL2C_LB_DATA0
#define GL2C_LB_DATA0__DATA__SHIFT                                                                            0x0
#define GL2C_LB_DATA0__DATA_MASK                                                                              0xFFFFFFFFL
//GL2C_LB_DATA1
#define GL2C_LB_DATA1__DATA__SHIFT                                                                            0x0
#define GL2C_LB_DATA1__DATA_MASK                                                                              0xFFFFFFFFL
//GL2C_LB_DATA2
#define GL2C_LB_DATA2__DATA__SHIFT                                                                            0x0
#define GL2C_LB_DATA2__DATA_MASK                                                                              0xFFFFFFFFL
//GL2C_LB_DATA3
#define GL2C_LB_DATA3__DATA__SHIFT                                                                            0x0
#define GL2C_LB_DATA3__DATA_MASK                                                                              0xFFFFFFFFL
//GL2C_LB_CTR_SEL0
#define GL2C_LB_CTR_SEL0__SEL0__SHIFT                                                                         0x0
#define GL2C_LB_CTR_SEL0__DIV0__SHIFT                                                                         0xf
#define GL2C_LB_CTR_SEL0__SEL1__SHIFT                                                                         0x10
#define GL2C_LB_CTR_SEL0__DIV1__SHIFT                                                                         0x1f
#define GL2C_LB_CTR_SEL0__SEL0_MASK                                                                           0x000000FFL
#define GL2C_LB_CTR_SEL0__DIV0_MASK                                                                           0x00008000L
#define GL2C_LB_CTR_SEL0__SEL1_MASK                                                                           0x00FF0000L
#define GL2C_LB_CTR_SEL0__DIV1_MASK                                                                           0x80000000L
//GL2C_LB_CTR_SEL1
#define GL2C_LB_CTR_SEL1__SEL2__SHIFT                                                                         0x0
#define GL2C_LB_CTR_SEL1__DIV2__SHIFT                                                                         0xf
#define GL2C_LB_CTR_SEL1__SEL3__SHIFT                                                                         0x10
#define GL2C_LB_CTR_SEL1__DIV3__SHIFT                                                                         0x1f
#define GL2C_LB_CTR_SEL1__SEL2_MASK                                                                           0x000000FFL
#define GL2C_LB_CTR_SEL1__DIV2_MASK                                                                           0x00008000L
#define GL2C_LB_CTR_SEL1__SEL3_MASK                                                                           0x00FF0000L
#define GL2C_LB_CTR_SEL1__DIV3_MASK                                                                           0x80000000L
//GL2A_ADDR_MATCH_CTRL
#define GL2A_ADDR_MATCH_CTRL__DISABLE__SHIFT                                                                  0x0
#define GL2A_ADDR_MATCH_CTRL__DISABLE_MASK                                                                    0xFFFFFFFFL
//GL2A_ADDR_MATCH_MASK
#define GL2A_ADDR_MATCH_MASK__ADDR_MASK__SHIFT                                                                0x0
#define GL2A_ADDR_MATCH_MASK__ADDR_MASK_MASK                                                                  0xFFFFFFFFL
//GL2A_ADDR_MATCH_SIZE
#define GL2A_ADDR_MATCH_SIZE__MAX_COUNT__SHIFT                                                                0x0
#define GL2A_ADDR_MATCH_SIZE__MAX_COUNT_MASK                                                                  0x00000007L
//GL2A_PRIORITY_CTRL
#define GL2A_PRIORITY_CTRL__DISABLE__SHIFT                                                                    0x0
#define GL2A_PRIORITY_CTRL__DISABLE_MASK                                                                      0xFFFFFFFFL
//GL2_PIPE_STEER_0
#define GL2_PIPE_STEER_0__PIPE_0_TO_CHAN_IN_Q0__SHIFT                                                         0x0
#define GL2_PIPE_STEER_0__PIPE_1_TO_CHAN_IN_Q0__SHIFT                                                         0x4
#define GL2_PIPE_STEER_0__PIPE_2_TO_CHAN_IN_Q0__SHIFT                                                         0x8
#define GL2_PIPE_STEER_0__PIPE_3_TO_CHAN_IN_Q0__SHIFT                                                         0xc
#define GL2_PIPE_STEER_0__PIPE_0_TO_CHAN_IN_Q1__SHIFT                                                         0x10
#define GL2_PIPE_STEER_0__PIPE_1_TO_CHAN_IN_Q1__SHIFT                                                         0x14
#define GL2_PIPE_STEER_0__PIPE_2_TO_CHAN_IN_Q1__SHIFT                                                         0x18
#define GL2_PIPE_STEER_0__PIPE_3_TO_CHAN_IN_Q1__SHIFT                                                         0x1c
#define GL2_PIPE_STEER_0__PIPE_0_TO_CHAN_IN_Q0_MASK                                                           0x00000007L
#define GL2_PIPE_STEER_0__PIPE_1_TO_CHAN_IN_Q0_MASK                                                           0x00000070L
#define GL2_PIPE_STEER_0__PIPE_2_TO_CHAN_IN_Q0_MASK                                                           0x00000700L
#define GL2_PIPE_STEER_0__PIPE_3_TO_CHAN_IN_Q0_MASK                                                           0x00007000L
#define GL2_PIPE_STEER_0__PIPE_0_TO_CHAN_IN_Q1_MASK                                                           0x00070000L
#define GL2_PIPE_STEER_0__PIPE_1_TO_CHAN_IN_Q1_MASK                                                           0x00700000L
#define GL2_PIPE_STEER_0__PIPE_2_TO_CHAN_IN_Q1_MASK                                                           0x07000000L
#define GL2_PIPE_STEER_0__PIPE_3_TO_CHAN_IN_Q1_MASK                                                           0x70000000L
//GL2_PIPE_STEER_1
#define GL2_PIPE_STEER_1__PIPE_0_TO_CHAN_IN_Q2__SHIFT                                                         0x0
#define GL2_PIPE_STEER_1__PIPE_1_TO_CHAN_IN_Q2__SHIFT                                                         0x4
#define GL2_PIPE_STEER_1__PIPE_2_TO_CHAN_IN_Q2__SHIFT                                                         0x8
#define GL2_PIPE_STEER_1__PIPE_3_TO_CHAN_IN_Q2__SHIFT                                                         0xc
#define GL2_PIPE_STEER_1__PIPE_0_TO_CHAN_IN_Q3__SHIFT                                                         0x10
#define GL2_PIPE_STEER_1__PIPE_1_TO_CHAN_IN_Q3__SHIFT                                                         0x14
#define GL2_PIPE_STEER_1__PIPE_2_TO_CHAN_IN_Q3__SHIFT                                                         0x18
#define GL2_PIPE_STEER_1__PIPE_3_TO_CHAN_IN_Q3__SHIFT                                                         0x1c
#define GL2_PIPE_STEER_1__PIPE_0_TO_CHAN_IN_Q2_MASK                                                           0x00000007L
#define GL2_PIPE_STEER_1__PIPE_1_TO_CHAN_IN_Q2_MASK                                                           0x00000070L
#define GL2_PIPE_STEER_1__PIPE_2_TO_CHAN_IN_Q2_MASK                                                           0x00000700L
#define GL2_PIPE_STEER_1__PIPE_3_TO_CHAN_IN_Q2_MASK                                                           0x00007000L
#define GL2_PIPE_STEER_1__PIPE_0_TO_CHAN_IN_Q3_MASK                                                           0x00070000L
#define GL2_PIPE_STEER_1__PIPE_1_TO_CHAN_IN_Q3_MASK                                                           0x00700000L
#define GL2_PIPE_STEER_1__PIPE_2_TO_CHAN_IN_Q3_MASK                                                           0x07000000L
#define GL2_PIPE_STEER_1__PIPE_3_TO_CHAN_IN_Q3_MASK                                                           0x70000000L


// addressBlock: gc_perfddec
//CPG_PERFCOUNTER1_LO
#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
//CPG_PERFCOUNTER1_HI
#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
//CPG_PERFCOUNTER0_LO
#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
//CPG_PERFCOUNTER0_HI
#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
//CPC_PERFCOUNTER1_LO
#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
//CPC_PERFCOUNTER1_HI
#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
//CPC_PERFCOUNTER0_LO
#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
//CPC_PERFCOUNTER0_HI
#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
//CPF_PERFCOUNTER1_LO
#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
//CPF_PERFCOUNTER1_HI
#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
//CPF_PERFCOUNTER0_LO
#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
//CPF_PERFCOUNTER0_HI
#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
//CPF_LATENCY_STATS_DATA
#define CPF_LATENCY_STATS_DATA__DATA__SHIFT                                                                   0x0
#define CPF_LATENCY_STATS_DATA__DATA_MASK                                                                     0xFFFFFFFFL
//CPG_LATENCY_STATS_DATA
#define CPG_LATENCY_STATS_DATA__DATA__SHIFT                                                                   0x0
#define CPG_LATENCY_STATS_DATA__DATA_MASK                                                                     0xFFFFFFFFL
//CPC_LATENCY_STATS_DATA
#define CPC_LATENCY_STATS_DATA__DATA__SHIFT                                                                   0x0
#define CPC_LATENCY_STATS_DATA__DATA_MASK                                                                     0xFFFFFFFFL
//GRBM_PERFCOUNTER0_LO
#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                           0x0
#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                             0xFFFFFFFFL
//GRBM_PERFCOUNTER0_HI
#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                           0x0
#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                             0xFFFFFFFFL
//GRBM_PERFCOUNTER1_LO
#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                           0x0
#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                             0xFFFFFFFFL
//GRBM_PERFCOUNTER1_HI
#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                           0x0
#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                             0xFFFFFFFFL
//GRBM_SE0_PERFCOUNTER_LO
#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT                                                        0x0
#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK                                                          0xFFFFFFFFL
//GRBM_SE0_PERFCOUNTER_HI
#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT                                                        0x0
#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK                                                          0xFFFFFFFFL
//GRBM_SE1_PERFCOUNTER_LO
#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT                                                        0x0
#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK                                                          0xFFFFFFFFL
//GRBM_SE1_PERFCOUNTER_HI
#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT                                                        0x0
#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK                                                          0xFFFFFFFFL
//GRBM_SE2_PERFCOUNTER_LO
#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT                                                        0x0
#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK                                                          0xFFFFFFFFL
//GRBM_SE2_PERFCOUNTER_HI
#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT                                                        0x0
#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK                                                          0xFFFFFFFFL
//GRBM_SE3_PERFCOUNTER_LO
#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT                                                        0x0
#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK                                                          0xFFFFFFFFL
//GRBM_SE3_PERFCOUNTER_HI
#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT                                                        0x0
#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK                                                          0xFFFFFFFFL
//GE1_PERFCOUNTER0_LO
#define GE1_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
#define GE1_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
//GE1_PERFCOUNTER0_HI
#define GE1_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
#define GE1_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
//GE1_PERFCOUNTER1_LO
#define GE1_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
#define GE1_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
//GE1_PERFCOUNTER1_HI
#define GE1_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
#define GE1_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
//GE1_PERFCOUNTER2_LO
#define GE1_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
#define GE1_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
//GE1_PERFCOUNTER2_HI
#define GE1_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
#define GE1_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
//GE1_PERFCOUNTER3_LO
#define GE1_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
#define GE1_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
//GE1_PERFCOUNTER3_HI
#define GE1_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
#define GE1_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
//GE2_DIST_PERFCOUNTER0_LO
#define GE2_DIST_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                       0x0
#define GE2_DIST_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                         0xFFFFFFFFL
//GE2_DIST_PERFCOUNTER0_HI
#define GE2_DIST_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                       0x0
#define GE2_DIST_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                         0xFFFFFFFFL
//GE2_DIST_PERFCOUNTER1_LO
#define GE2_DIST_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                       0x0
#define GE2_DIST_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                         0xFFFFFFFFL
//GE2_DIST_PERFCOUNTER1_HI
#define GE2_DIST_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                       0x0
#define GE2_DIST_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                         0xFFFFFFFFL
//GE2_DIST_PERFCOUNTER2_LO
#define GE2_DIST_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                       0x0
#define GE2_DIST_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                         0xFFFFFFFFL
//GE2_DIST_PERFCOUNTER2_HI
#define GE2_DIST_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                       0x0
#define GE2_DIST_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                         0xFFFFFFFFL
//GE2_DIST_PERFCOUNTER3_LO
#define GE2_DIST_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                       0x0
#define GE2_DIST_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                         0xFFFFFFFFL
//GE2_DIST_PERFCOUNTER3_HI
#define GE2_DIST_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                       0x0
#define GE2_DIST_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                         0xFFFFFFFFL
//GE2_SE_PERFCOUNTER0_LO
#define GE2_SE_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                         0x0
#define GE2_SE_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                           0xFFFFFFFFL
//GE2_SE_PERFCOUNTER0_HI
#define GE2_SE_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                         0x0
#define GE2_SE_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                           0xFFFFFFFFL
//GE2_SE_PERFCOUNTER1_LO
#define GE2_SE_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                         0x0
#define GE2_SE_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                           0xFFFFFFFFL
//GE2_SE_PERFCOUNTER1_HI
#define GE2_SE_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                         0x0
#define GE2_SE_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                           0xFFFFFFFFL
//GE2_SE_PERFCOUNTER2_LO
#define GE2_SE_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                         0x0
#define GE2_SE_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                           0xFFFFFFFFL
//GE2_SE_PERFCOUNTER2_HI
#define GE2_SE_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                         0x0
#define GE2_SE_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                           0xFFFFFFFFL
//GE2_SE_PERFCOUNTER3_LO
#define GE2_SE_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                         0x0
#define GE2_SE_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                           0xFFFFFFFFL
//GE2_SE_PERFCOUNTER3_HI
#define GE2_SE_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                         0x0
#define GE2_SE_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                           0xFFFFFFFFL
//PA_SU_PERFCOUNTER0_LO
#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
//PA_SU_PERFCOUNTER0_HI
#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
//PA_SU_PERFCOUNTER1_LO
#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
//PA_SU_PERFCOUNTER1_HI
#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
//PA_SU_PERFCOUNTER2_LO
#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
//PA_SU_PERFCOUNTER2_HI
#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
//PA_SU_PERFCOUNTER3_LO
#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
//PA_SU_PERFCOUNTER3_HI
#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
//PA_SC_PERFCOUNTER0_LO
#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
//PA_SC_PERFCOUNTER0_HI
#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
//PA_SC_PERFCOUNTER1_LO
#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
//PA_SC_PERFCOUNTER1_HI
#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
//PA_SC_PERFCOUNTER2_LO
#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
//PA_SC_PERFCOUNTER2_HI
#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
//PA_SC_PERFCOUNTER3_LO
#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
//PA_SC_PERFCOUNTER3_HI
#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
//PA_SC_PERFCOUNTER4_LO
#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
//PA_SC_PERFCOUNTER4_HI
#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
//PA_SC_PERFCOUNTER5_LO
#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
//PA_SC_PERFCOUNTER5_HI
#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
//PA_SC_PERFCOUNTER6_LO
#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
//PA_SC_PERFCOUNTER6_HI
#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
//PA_SC_PERFCOUNTER7_LO
#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
//PA_SC_PERFCOUNTER7_HI
#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
//SPI_PERFCOUNTER0_HI
#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
//SPI_PERFCOUNTER0_LO
#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
//SPI_PERFCOUNTER1_HI
#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
//SPI_PERFCOUNTER1_LO
#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
//SPI_PERFCOUNTER2_HI
#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
//SPI_PERFCOUNTER2_LO
#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
//SPI_PERFCOUNTER3_HI
#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
//SPI_PERFCOUNTER3_LO
#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
//SPI_PERFCOUNTER4_HI
#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
//SPI_PERFCOUNTER4_LO
#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
//SPI_PERFCOUNTER5_HI
#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
//SPI_PERFCOUNTER5_LO
#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
//SQ_PERFCOUNTER0_LO
#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
//SQ_PERFCOUNTER0_HI
#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
//SQ_PERFCOUNTER1_LO
#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
//SQ_PERFCOUNTER1_HI
#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
//SQ_PERFCOUNTER2_LO
#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
//SQ_PERFCOUNTER2_HI
#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
//SQ_PERFCOUNTER3_LO
#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
//SQ_PERFCOUNTER3_HI
#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
//SQ_PERFCOUNTER4_LO
#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
//SQ_PERFCOUNTER4_HI
#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
//SQ_PERFCOUNTER5_LO
#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
//SQ_PERFCOUNTER5_HI
#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
//SQ_PERFCOUNTER6_LO
#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
//SQ_PERFCOUNTER6_HI
#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
//SQ_PERFCOUNTER7_LO
#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
//SQ_PERFCOUNTER7_HI
#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
//SQ_PERFCOUNTER8_LO
#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
//SQ_PERFCOUNTER8_HI
#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
//SQ_PERFCOUNTER9_LO
#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
//SQ_PERFCOUNTER9_HI
#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
//SQ_PERFCOUNTER10_LO
#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
//SQ_PERFCOUNTER10_HI
#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
//SQ_PERFCOUNTER11_LO
#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
//SQ_PERFCOUNTER11_HI
#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
//SQ_PERFCOUNTER12_LO
#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
//SQ_PERFCOUNTER12_HI
#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
//SQ_PERFCOUNTER13_LO
#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
//SQ_PERFCOUNTER13_HI
#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
//SQ_PERFCOUNTER14_LO
#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
//SQ_PERFCOUNTER14_HI
#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
//SQ_PERFCOUNTER15_LO
#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
//SQ_PERFCOUNTER15_HI
#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
//SX_PERFCOUNTER0_LO
#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
//SX_PERFCOUNTER0_HI
#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
//SX_PERFCOUNTER1_LO
#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
//SX_PERFCOUNTER1_HI
#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
//SX_PERFCOUNTER2_LO
#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
//SX_PERFCOUNTER2_HI
#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
//SX_PERFCOUNTER3_LO
#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
//SX_PERFCOUNTER3_HI
#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
//GCEA_PERFCOUNTER2_LO
#define GCEA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                           0x0
#define GCEA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                             0xFFFFFFFFL
//GCEA_PERFCOUNTER2_HI
#define GCEA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                           0x0
#define GCEA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                             0xFFFFFFFFL
//GCEA_PERFCOUNTER_LO
#define GCEA_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                                0x0
#define GCEA_PERFCOUNTER_LO__COUNTER_LO_MASK                                                                  0xFFFFFFFFL
//GCEA_PERFCOUNTER_HI
#define GCEA_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                                0x0
#define GCEA_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                             0x10
#define GCEA_PERFCOUNTER_HI__COUNTER_HI_MASK                                                                  0x0000FFFFL
#define GCEA_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                               0xFFFF0000L
//GDS_PERFCOUNTER0_LO
#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
//GDS_PERFCOUNTER0_HI
#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
//GDS_PERFCOUNTER1_LO
#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
//GDS_PERFCOUNTER1_HI
#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
//GDS_PERFCOUNTER2_LO
#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
//GDS_PERFCOUNTER2_HI
#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
//GDS_PERFCOUNTER3_LO
#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
//GDS_PERFCOUNTER3_HI
#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
//TA_PERFCOUNTER0_LO
#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
//TA_PERFCOUNTER0_HI
#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
//TA_PERFCOUNTER1_LO
#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
//TA_PERFCOUNTER1_HI
#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
//TD_PERFCOUNTER0_LO
#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
//TD_PERFCOUNTER0_HI
#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
//TD_PERFCOUNTER1_LO
#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
//TD_PERFCOUNTER1_HI
#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
//TCP_PERFCOUNTER0_LO
#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
//TCP_PERFCOUNTER0_HI
#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
//TCP_PERFCOUNTER1_LO
#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
//TCP_PERFCOUNTER1_HI
#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
//TCP_PERFCOUNTER2_LO
#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
//TCP_PERFCOUNTER2_HI
#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
//TCP_PERFCOUNTER3_LO
#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
//TCP_PERFCOUNTER3_HI
#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
//GL2C_PERFCOUNTER0_LO
#define GL2C_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                           0x0
#define GL2C_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                             0xFFFFFFFFL
//GL2C_PERFCOUNTER0_HI
#define GL2C_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                           0x0
#define GL2C_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                             0xFFFFFFFFL
//GL2C_PERFCOUNTER1_LO
#define GL2C_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                           0x0
#define GL2C_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                             0xFFFFFFFFL
//GL2C_PERFCOUNTER1_HI
#define GL2C_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                           0x0
#define GL2C_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                             0xFFFFFFFFL
//GL2C_PERFCOUNTER2_LO
#define GL2C_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                           0x0
#define GL2C_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                             0xFFFFFFFFL
//GL2C_PERFCOUNTER2_HI
#define GL2C_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                           0x0
#define GL2C_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                             0xFFFFFFFFL
//GL2C_PERFCOUNTER3_LO
#define GL2C_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                           0x0
#define GL2C_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                             0xFFFFFFFFL
//GL2C_PERFCOUNTER3_HI
#define GL2C_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                           0x0
#define GL2C_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                             0xFFFFFFFFL
//GL2A_PERFCOUNTER0_LO
#define GL2A_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                           0x0
#define GL2A_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                             0xFFFFFFFFL
//GL2A_PERFCOUNTER0_HI
#define GL2A_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                           0x0
#define GL2A_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                             0xFFFFFFFFL
//GL2A_PERFCOUNTER1_LO
#define GL2A_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                           0x0
#define GL2A_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                             0xFFFFFFFFL
//GL2A_PERFCOUNTER1_HI
#define GL2A_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                           0x0
#define GL2A_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                             0xFFFFFFFFL
//GL2A_PERFCOUNTER2_LO
#define GL2A_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                           0x0
#define GL2A_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                             0xFFFFFFFFL
//GL2A_PERFCOUNTER2_HI
#define GL2A_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                           0x0
#define GL2A_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                             0xFFFFFFFFL
//GL2A_PERFCOUNTER3_LO
#define GL2A_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                           0x0
#define GL2A_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                             0xFFFFFFFFL
//GL2A_PERFCOUNTER3_HI
#define GL2A_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                           0x0
#define GL2A_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                             0xFFFFFFFFL
//GL1C_PERFCOUNTER0_LO
#define GL1C_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                           0x0
#define GL1C_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                             0xFFFFFFFFL
//GL1C_PERFCOUNTER0_HI
#define GL1C_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                           0x0
#define GL1C_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                             0xFFFFFFFFL
//GL1C_PERFCOUNTER1_LO
#define GL1C_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                           0x0
#define GL1C_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                             0xFFFFFFFFL
//GL1C_PERFCOUNTER1_HI
#define GL1C_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                           0x0
#define GL1C_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                             0xFFFFFFFFL
//GL1C_PERFCOUNTER2_LO
#define GL1C_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                           0x0
#define GL1C_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                             0xFFFFFFFFL
//GL1C_PERFCOUNTER2_HI
#define GL1C_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                           0x0
#define GL1C_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                             0xFFFFFFFFL
//GL1C_PERFCOUNTER3_LO
#define GL1C_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                           0x0
#define GL1C_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                             0xFFFFFFFFL
//GL1C_PERFCOUNTER3_HI
#define GL1C_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                           0x0
#define GL1C_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                             0xFFFFFFFFL
//CHC_PERFCOUNTER0_LO
#define CHC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
#define CHC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
//CHC_PERFCOUNTER0_HI
#define CHC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
#define CHC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
//CHC_PERFCOUNTER1_LO
#define CHC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
#define CHC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
//CHC_PERFCOUNTER1_HI
#define CHC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
#define CHC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
//CHC_PERFCOUNTER2_LO
#define CHC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
#define CHC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
//CHC_PERFCOUNTER2_HI
#define CHC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
#define CHC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
//CHC_PERFCOUNTER3_LO
#define CHC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
#define CHC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
//CHC_PERFCOUNTER3_HI
#define CHC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
#define CHC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
//CHCG_PERFCOUNTER0_LO
#define CHCG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                           0x0
#define CHCG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                             0xFFFFFFFFL
//CHCG_PERFCOUNTER0_HI
#define CHCG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                           0x0
#define CHCG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                             0xFFFFFFFFL
//CHCG_PERFCOUNTER1_LO
#define CHCG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                           0x0
#define CHCG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                             0xFFFFFFFFL
//CHCG_PERFCOUNTER1_HI
#define CHCG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                           0x0
#define CHCG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                             0xFFFFFFFFL
//CHCG_PERFCOUNTER2_LO
#define CHCG_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                           0x0
#define CHCG_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                             0xFFFFFFFFL
//CHCG_PERFCOUNTER2_HI
#define CHCG_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                           0x0
#define CHCG_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                             0xFFFFFFFFL
//CHCG_PERFCOUNTER3_LO
#define CHCG_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                           0x0
#define CHCG_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                             0xFFFFFFFFL
//CHCG_PERFCOUNTER3_HI
#define CHCG_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                           0x0
#define CHCG_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                             0xFFFFFFFFL
//CB_PERFCOUNTER0_LO
#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
//CB_PERFCOUNTER0_HI
#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
//CB_PERFCOUNTER1_LO
#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
//CB_PERFCOUNTER1_HI
#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
//CB_PERFCOUNTER2_LO
#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
//CB_PERFCOUNTER2_HI
#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
//CB_PERFCOUNTER3_LO
#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
//CB_PERFCOUNTER3_HI
#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
//DB_PERFCOUNTER0_LO
#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
//DB_PERFCOUNTER0_HI
#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
//DB_PERFCOUNTER1_LO
#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
//DB_PERFCOUNTER1_HI
#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
//DB_PERFCOUNTER2_LO
#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
//DB_PERFCOUNTER2_HI
#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
//DB_PERFCOUNTER3_LO
#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
//DB_PERFCOUNTER3_HI
#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
//RLC_PERFCOUNTER0_LO
#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
//RLC_PERFCOUNTER0_HI
#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
//RLC_PERFCOUNTER1_LO
#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
//RLC_PERFCOUNTER1_HI
#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
//RMI_PERFCOUNTER0_LO
#define RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
#define RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
//RMI_PERFCOUNTER0_HI
#define RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
#define RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
//RMI_PERFCOUNTER1_LO
#define RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
#define RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
//RMI_PERFCOUNTER1_HI
#define RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
#define RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
//RMI_PERFCOUNTER2_LO
#define RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
#define RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
//RMI_PERFCOUNTER2_HI
#define RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
#define RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
//RMI_PERFCOUNTER3_LO
#define RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
#define RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
//RMI_PERFCOUNTER3_HI
#define RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
#define RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
//UTCL1_PERFCOUNTER0_LO
#define UTCL1_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
#define UTCL1_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
//UTCL1_PERFCOUNTER0_HI
#define UTCL1_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
#define UTCL1_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
//UTCL1_PERFCOUNTER1_LO
#define UTCL1_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
#define UTCL1_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
//UTCL1_PERFCOUNTER1_HI
#define UTCL1_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
#define UTCL1_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
//GCR_PERFCOUNTER0_LO
#define GCR_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
#define GCR_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
//GCR_PERFCOUNTER0_HI
#define GCR_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
#define GCR_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
//GCR_PERFCOUNTER1_LO
#define GCR_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
#define GCR_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
//GCR_PERFCOUNTER1_HI
#define GCR_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
#define GCR_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
//PA_PH_PERFCOUNTER0_LO
#define PA_PH_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
#define PA_PH_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
//PA_PH_PERFCOUNTER0_HI
#define PA_PH_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
#define PA_PH_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
//PA_PH_PERFCOUNTER1_LO
#define PA_PH_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
#define PA_PH_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
//PA_PH_PERFCOUNTER1_HI
#define PA_PH_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
#define PA_PH_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
//PA_PH_PERFCOUNTER2_LO
#define PA_PH_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
#define PA_PH_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
//PA_PH_PERFCOUNTER2_HI
#define PA_PH_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
#define PA_PH_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
//PA_PH_PERFCOUNTER3_LO
#define PA_PH_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
#define PA_PH_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
//PA_PH_PERFCOUNTER3_HI
#define PA_PH_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
#define PA_PH_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
//PA_PH_PERFCOUNTER4_LO
#define PA_PH_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
#define PA_PH_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
//PA_PH_PERFCOUNTER4_HI
#define PA_PH_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
#define PA_PH_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
//PA_PH_PERFCOUNTER5_LO
#define PA_PH_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
#define PA_PH_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
//PA_PH_PERFCOUNTER5_HI
#define PA_PH_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
#define PA_PH_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
//PA_PH_PERFCOUNTER6_LO
#define PA_PH_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
#define PA_PH_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
//PA_PH_PERFCOUNTER6_HI
#define PA_PH_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
#define PA_PH_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
//PA_PH_PERFCOUNTER7_LO
#define PA_PH_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
#define PA_PH_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
//PA_PH_PERFCOUNTER7_HI
#define PA_PH_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
#define PA_PH_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
//GL1A_PERFCOUNTER0_LO
#define GL1A_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                           0x0
#define GL1A_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                             0xFFFFFFFFL
//GL1A_PERFCOUNTER0_HI
#define GL1A_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                           0x0
#define GL1A_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                             0xFFFFFFFFL
//GL1A_PERFCOUNTER1_LO
#define GL1A_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                           0x0
#define GL1A_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                             0xFFFFFFFFL
//GL1A_PERFCOUNTER1_HI
#define GL1A_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                           0x0
#define GL1A_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                             0xFFFFFFFFL
//GL1A_PERFCOUNTER2_LO
#define GL1A_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                           0x0
#define GL1A_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                             0xFFFFFFFFL
//GL1A_PERFCOUNTER2_HI
#define GL1A_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                           0x0
#define GL1A_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                             0xFFFFFFFFL
//GL1A_PERFCOUNTER3_LO
#define GL1A_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                           0x0
#define GL1A_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                             0xFFFFFFFFL
//GL1A_PERFCOUNTER3_HI
#define GL1A_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                           0x0
#define GL1A_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                             0xFFFFFFFFL
//CHA_PERFCOUNTER0_LO
#define CHA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
#define CHA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
//CHA_PERFCOUNTER0_HI
#define CHA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
#define CHA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
//CHA_PERFCOUNTER1_LO
#define CHA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
#define CHA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
//CHA_PERFCOUNTER1_HI
#define CHA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
#define CHA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
//CHA_PERFCOUNTER2_LO
#define CHA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
#define CHA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
//CHA_PERFCOUNTER2_HI
#define CHA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
#define CHA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
//CHA_PERFCOUNTER3_LO
#define CHA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
#define CHA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
//CHA_PERFCOUNTER3_HI
#define CHA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
#define CHA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
//GUS_PERFCOUNTER2_LO
#define GUS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
#define GUS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
//GUS_PERFCOUNTER2_HI
#define GUS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
#define GUS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
//GUS_PERFCOUNTER_LO
#define GUS_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                                 0x0
#define GUS_PERFCOUNTER_LO__COUNTER_LO_MASK                                                                   0xFFFFFFFFL
//GUS_PERFCOUNTER_HI
#define GUS_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                                 0x0
#define GUS_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                              0x10
#define GUS_PERFCOUNTER_HI__COUNTER_HI_MASK                                                                   0x0000FFFFL
#define GUS_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                                0xFFFF0000L


// addressBlock: gc_gcvml2prdec
//GCMC_VM_L2_PERFCOUNTER_LO
#define GCMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                          0x0
#define GCMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK                                                            0xFFFFFFFFL
//GCMC_VM_L2_PERFCOUNTER_HI
#define GCMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                          0x0
#define GCMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                       0x10
#define GCMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK                                                            0x0000FFFFL
#define GCMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                         0xFFFF0000L
//GCUTCL2_PERFCOUNTER_LO
#define GCUTCL2_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                             0x0
#define GCUTCL2_PERFCOUNTER_LO__COUNTER_LO_MASK                                                               0xFFFFFFFFL
//GCUTCL2_PERFCOUNTER_HI
#define GCUTCL2_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                             0x0
#define GCUTCL2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                          0x10
#define GCUTCL2_PERFCOUNTER_HI__COUNTER_HI_MASK                                                               0x0000FFFFL
#define GCUTCL2_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                            0xFFFF0000L


// addressBlock: gc_gcvml2perfddec
//GCVML2_PERFCOUNTER2_0_LO
#define GCVML2_PERFCOUNTER2_0_LO__PERFCOUNTER_LO__SHIFT                                                       0x0
#define GCVML2_PERFCOUNTER2_0_LO__PERFCOUNTER_LO_MASK                                                         0xFFFFFFFFL
//GCVML2_PERFCOUNTER2_1_LO
#define GCVML2_PERFCOUNTER2_1_LO__PERFCOUNTER_LO__SHIFT                                                       0x0
#define GCVML2_PERFCOUNTER2_1_LO__PERFCOUNTER_LO_MASK                                                         0xFFFFFFFFL
//GCVML2_PERFCOUNTER2_0_HI
#define GCVML2_PERFCOUNTER2_0_HI__PERFCOUNTER_HI__SHIFT                                                       0x0
#define GCVML2_PERFCOUNTER2_0_HI__PERFCOUNTER_HI_MASK                                                         0xFFFFFFFFL
//GCVML2_PERFCOUNTER2_1_HI
#define GCVML2_PERFCOUNTER2_1_HI__PERFCOUNTER_HI__SHIFT                                                       0x0
#define GCVML2_PERFCOUNTER2_1_HI__PERFCOUNTER_HI_MASK                                                         0xFFFFFFFFL


// addressBlock: gc_sdma0_sdma0perfddec
//SDMA0_PERFCNT_PERFCOUNTER_LO
#define SDMA0_PERFCNT_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                       0x0
#define SDMA0_PERFCNT_PERFCOUNTER_LO__COUNTER_LO_MASK                                                         0xFFFFFFFFL
//SDMA0_PERFCNT_PERFCOUNTER_HI
#define SDMA0_PERFCNT_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                       0x0
#define SDMA0_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                    0x10
#define SDMA0_PERFCNT_PERFCOUNTER_HI__COUNTER_HI_MASK                                                         0x0000FFFFL
#define SDMA0_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                      0xFFFF0000L
//SDMA0_PERFCOUNTER0_LO
#define SDMA0_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
#define SDMA0_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
//SDMA0_PERFCOUNTER0_HI
#define SDMA0_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
#define SDMA0_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
//SDMA0_PERFCOUNTER1_LO
#define SDMA0_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
#define SDMA0_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
//SDMA0_PERFCOUNTER1_HI
#define SDMA0_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
#define SDMA0_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL


// addressBlock: gc_sdma1_sdma1perfddec
//SDMA1_PERFCNT_PERFCOUNTER_LO
#define SDMA1_PERFCNT_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                       0x0
#define SDMA1_PERFCNT_PERFCOUNTER_LO__COUNTER_LO_MASK                                                         0xFFFFFFFFL
//SDMA1_PERFCNT_PERFCOUNTER_HI
#define SDMA1_PERFCNT_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                       0x0
#define SDMA1_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                    0x10
#define SDMA1_PERFCNT_PERFCOUNTER_HI__COUNTER_HI_MASK                                                         0x0000FFFFL
#define SDMA1_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                      0xFFFF0000L
//SDMA1_PERFCOUNTER0_LO
#define SDMA1_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
#define SDMA1_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
//SDMA1_PERFCOUNTER0_HI
#define SDMA1_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
#define SDMA1_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
//SDMA1_PERFCOUNTER1_LO
#define SDMA1_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
#define SDMA1_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
//SDMA1_PERFCOUNTER1_HI
#define SDMA1_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
#define SDMA1_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL


// addressBlock: gc_sdma2_sdma2perfddec
//SDMA2_PERFCNT_PERFCOUNTER_LO
#define SDMA2_PERFCNT_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                       0x0
#define SDMA2_PERFCNT_PERFCOUNTER_LO__COUNTER_LO_MASK                                                         0xFFFFFFFFL
//SDMA2_PERFCNT_PERFCOUNTER_HI
#define SDMA2_PERFCNT_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                       0x0
#define SDMA2_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                    0x10
#define SDMA2_PERFCNT_PERFCOUNTER_HI__COUNTER_HI_MASK                                                         0x0000FFFFL
#define SDMA2_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                      0xFFFF0000L
//SDMA2_PERFCOUNTER0_LO
#define SDMA2_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
#define SDMA2_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
//SDMA2_PERFCOUNTER0_HI
#define SDMA2_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
#define SDMA2_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
//SDMA2_PERFCOUNTER1_LO
#define SDMA2_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
#define SDMA2_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
//SDMA2_PERFCOUNTER1_HI
#define SDMA2_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
#define SDMA2_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL


// addressBlock: gc_sdma3_sdma3perfddec
//SDMA3_PERFCNT_PERFCOUNTER_LO
#define SDMA3_PERFCNT_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                       0x0
#define SDMA3_PERFCNT_PERFCOUNTER_LO__COUNTER_LO_MASK                                                         0xFFFFFFFFL
//SDMA3_PERFCNT_PERFCOUNTER_HI
#define SDMA3_PERFCNT_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                       0x0
#define SDMA3_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                    0x10
#define SDMA3_PERFCNT_PERFCOUNTER_HI__COUNTER_HI_MASK                                                         0x0000FFFFL
#define SDMA3_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                      0xFFFF0000L
//SDMA3_PERFCOUNTER0_LO
#define SDMA3_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
#define SDMA3_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
//SDMA3_PERFCOUNTER0_HI
#define SDMA3_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
#define SDMA3_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
//SDMA3_PERFCOUNTER1_LO
#define SDMA3_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
#define SDMA3_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
//SDMA3_PERFCOUNTER1_HI
#define SDMA3_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
#define SDMA3_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL


// addressBlock: gc_perfsdec
//CPG_PERFCOUNTER1_SELECT
#define CPG_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                              0x0
#define CPG_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT                                                             0xa
#define CPG_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT                                                              0x14
#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT                                                            0x18
#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT                                                            0x1c
#define CPG_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                0x000003FFL
#define CPG_PERFCOUNTER1_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
#define CPG_PERFCOUNTER1_SELECT__SPM_MODE_MASK                                                                0x00F00000L
#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK                                                              0x0F000000L
#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK                                                              0xF0000000L
//CPG_PERFCOUNTER0_SELECT1
#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                            0x0
#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                            0xa
#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT                                                           0x18
#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT                                                           0x1c
#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK                                                             0x0F000000L
#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK                                                             0xF0000000L
//CPG_PERFCOUNTER0_SELECT
#define CPG_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                              0x0
#define CPG_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                             0xa
#define CPG_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT                                                              0x14
#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT                                                            0x18
#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT                                                            0x1c
#define CPG_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                0x000003FFL
#define CPG_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
#define CPG_PERFCOUNTER0_SELECT__SPM_MODE_MASK                                                                0x00F00000L
#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK                                                              0x0F000000L
#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK                                                              0xF0000000L
//CPC_PERFCOUNTER1_SELECT
#define CPC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                              0x0
#define CPC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT                                                             0xa
#define CPC_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT                                                              0x14
#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT                                                            0x18
#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT                                                            0x1c
#define CPC_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                0x000003FFL
#define CPC_PERFCOUNTER1_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
#define CPC_PERFCOUNTER1_SELECT__SPM_MODE_MASK                                                                0x00F00000L
#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK                                                              0x0F000000L
#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK                                                              0xF0000000L
//CPC_PERFCOUNTER0_SELECT1
#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                            0x0
#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                            0xa
#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT                                                           0x18
#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT                                                           0x1c
#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK                                                             0x0F000000L
#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK                                                             0xF0000000L
//CPF_PERFCOUNTER1_SELECT
#define CPF_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                              0x0
#define CPF_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT                                                             0xa
#define CPF_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT                                                              0x14
#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT                                                            0x18
#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT                                                            0x1c
#define CPF_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                0x000003FFL
#define CPF_PERFCOUNTER1_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
#define CPF_PERFCOUNTER1_SELECT__SPM_MODE_MASK                                                                0x00F00000L
#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK                                                              0x0F000000L
#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK                                                              0xF0000000L
//CPF_PERFCOUNTER0_SELECT1
#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                            0x0
#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                            0xa
#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT                                                           0x18
#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT                                                           0x1c
#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK                                                             0x0F000000L
#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK                                                             0xF0000000L
//CPF_PERFCOUNTER0_SELECT
#define CPF_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                              0x0
#define CPF_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                             0xa
#define CPF_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT                                                              0x14
#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT                                                            0x18
#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT                                                            0x1c
#define CPF_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                0x000003FFL
#define CPF_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
#define CPF_PERFCOUNTER0_SELECT__SPM_MODE_MASK                                                                0x00F00000L
#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK                                                              0x0F000000L
#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK                                                              0xF0000000L
//CP_PERFMON_CNTL
#define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                                 0x0
#define CP_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT                                                             0x4
#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT                                                           0x8
#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT                                                         0xa
#define CP_PERFMON_CNTL__PERFMON_STATE_MASK                                                                   0x0000000FL
#define CP_PERFMON_CNTL__SPM_PERFMON_STATE_MASK                                                               0x000000F0L
#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK                                                             0x00000300L
#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK                                                           0x00000400L
//CPC_PERFCOUNTER0_SELECT
#define CPC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                              0x0
#define CPC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                             0xa
#define CPC_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT                                                              0x14
#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT                                                            0x18
#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT                                                            0x1c
#define CPC_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                0x000003FFL
#define CPC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
#define CPC_PERFCOUNTER0_SELECT__SPM_MODE_MASK                                                                0x00F00000L
#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK                                                              0x0F000000L
#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK                                                              0xF0000000L
//CPF_TC_PERF_COUNTER_WINDOW_SELECT
#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT                                                       0x0
#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT                                                      0x1e
#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT                                                      0x1f
#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK                                                         0x00000007L
#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK                                                        0x40000000L
#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK                                                        0x80000000L
//CPG_TC_PERF_COUNTER_WINDOW_SELECT
#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT                                                       0x0
#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT                                                      0x1e
#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT                                                      0x1f
#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK                                                         0x0000001FL
#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK                                                        0x40000000L
#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK                                                        0x80000000L
//CPF_LATENCY_STATS_SELECT
#define CPF_LATENCY_STATS_SELECT__INDEX__SHIFT                                                                0x0
#define CPF_LATENCY_STATS_SELECT__CLEAR__SHIFT                                                                0x1e
#define CPF_LATENCY_STATS_SELECT__ENABLE__SHIFT                                                               0x1f
#define CPF_LATENCY_STATS_SELECT__INDEX_MASK                                                                  0x0000000FL
#define CPF_LATENCY_STATS_SELECT__CLEAR_MASK                                                                  0x40000000L
#define CPF_LATENCY_STATS_SELECT__ENABLE_MASK                                                                 0x80000000L
//CPG_LATENCY_STATS_SELECT
#define CPG_LATENCY_STATS_SELECT__INDEX__SHIFT                                                                0x0
#define CPG_LATENCY_STATS_SELECT__CLEAR__SHIFT                                                                0x1e
#define CPG_LATENCY_STATS_SELECT__ENABLE__SHIFT                                                               0x1f
#define CPG_LATENCY_STATS_SELECT__INDEX_MASK                                                                  0x0000001FL
#define CPG_LATENCY_STATS_SELECT__CLEAR_MASK                                                                  0x40000000L
#define CPG_LATENCY_STATS_SELECT__ENABLE_MASK                                                                 0x80000000L
//CPC_LATENCY_STATS_SELECT
#define CPC_LATENCY_STATS_SELECT__INDEX__SHIFT                                                                0x0
#define CPC_LATENCY_STATS_SELECT__CLEAR__SHIFT                                                                0x1e
#define CPC_LATENCY_STATS_SELECT__ENABLE__SHIFT                                                               0x1f
#define CPC_LATENCY_STATS_SELECT__INDEX_MASK                                                                  0x0000000FL
#define CPC_LATENCY_STATS_SELECT__CLEAR_MASK                                                                  0x40000000L
#define CPC_LATENCY_STATS_SELECT__ENABLE_MASK                                                                 0x80000000L
//CP_DRAW_OBJECT
#define CP_DRAW_OBJECT__OBJECT__SHIFT                                                                         0x0
#define CP_DRAW_OBJECT__OBJECT_MASK                                                                           0xFFFFFFFFL
//CP_DRAW_OBJECT_COUNTER
#define CP_DRAW_OBJECT_COUNTER__COUNT__SHIFT                                                                  0x0
#define CP_DRAW_OBJECT_COUNTER__COUNT_MASK                                                                    0x0000FFFFL
//CP_DRAW_WINDOW_MASK_HI
#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI__SHIFT                                                         0x0
#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI_MASK                                                           0xFFFFFFFFL
//CP_DRAW_WINDOW_HI
#define CP_DRAW_WINDOW_HI__WINDOW_HI__SHIFT                                                                   0x0
#define CP_DRAW_WINDOW_HI__WINDOW_HI_MASK                                                                     0xFFFFFFFFL
//CP_DRAW_WINDOW_LO
#define CP_DRAW_WINDOW_LO__MIN__SHIFT                                                                         0x0
#define CP_DRAW_WINDOW_LO__MAX__SHIFT                                                                         0x10
#define CP_DRAW_WINDOW_LO__MIN_MASK                                                                           0x0000FFFFL
#define CP_DRAW_WINDOW_LO__MAX_MASK                                                                           0xFFFF0000L
//CP_DRAW_WINDOW_CNTL
#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX__SHIFT                                                0x0
#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN__SHIFT                                                0x1
#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI__SHIFT                                                    0x2
#define CP_DRAW_WINDOW_CNTL__MODE__SHIFT                                                                      0x8
#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX_MASK                                                  0x00000001L
#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN_MASK                                                  0x00000002L
#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI_MASK                                                      0x00000004L
#define CP_DRAW_WINDOW_CNTL__MODE_MASK                                                                        0x00000100L
//GRBM_PERFCOUNTER0_SELECT
#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                             0x0
#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT                                           0xa
#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT                                           0xb
#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT                                            0xd
#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT                                            0xe
#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT                                           0x10
#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT                                            0x11
#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT                                            0x12
#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT                                          0x13
#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT                                            0x14
#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT                                            0x15
#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT                                            0x16
#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT                                           0x18
#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT                                           0x19
#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT                                           0x1a
#define GRBM_PERFCOUNTER0_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT                                           0x1b
#define GRBM_PERFCOUNTER0_SELECT__GE_BUSY_USER_DEFINED_MASK__SHIFT                                            0x1c
#define GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT                                         0x1d
#define GRBM_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT                                            0x1e
#define GRBM_PERFCOUNTER0_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT                                           0x1f
#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                               0x0000003FL
#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK                                             0x00000400L
#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK                                             0x00000800L
#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK                                              0x00002000L
#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK                                              0x00004000L
#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK                                             0x00010000L
#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK                                              0x00020000L
#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK                                              0x00040000L
#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK                                            0x00080000L
#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK                                              0x00100000L
#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK                                              0x00200000L
#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK                                              0x00400000L
#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK                                             0x01000000L
#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK                                             0x02000000L
#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK                                             0x04000000L
#define GRBM_PERFCOUNTER0_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK                                             0x08000000L
#define GRBM_PERFCOUNTER0_SELECT__GE_BUSY_USER_DEFINED_MASK_MASK                                              0x10000000L
#define GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK                                           0x20000000L
#define GRBM_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK                                              0x40000000L
#define GRBM_PERFCOUNTER0_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK                                             0x80000000L
//GRBM_PERFCOUNTER1_SELECT
#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                             0x0
#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT                                           0xa
#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT                                           0xb
#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT                                            0xd
#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT                                            0xe
#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT                                           0x10
#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT                                            0x11
#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT                                            0x12
#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT                                          0x13
#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT                                            0x14
#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT                                            0x15
#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT                                            0x16
#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT                                           0x18
#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT                                           0x19
#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT                                           0x1a
#define GRBM_PERFCOUNTER1_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT                                           0x1b
#define GRBM_PERFCOUNTER1_SELECT__GE_BUSY_USER_DEFINED_MASK__SHIFT                                            0x1c
#define GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT                                         0x1d
#define GRBM_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT                                            0x1e
#define GRBM_PERFCOUNTER1_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT                                           0x1f
#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                               0x0000003FL
#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK                                             0x00000400L
#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK                                             0x00000800L
#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK                                              0x00002000L
#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK                                              0x00004000L
#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK                                             0x00010000L
#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK                                              0x00020000L
#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK                                              0x00040000L
#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK                                            0x00080000L
#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK                                              0x00100000L
#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK                                              0x00200000L
#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK                                              0x00400000L
#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK                                             0x01000000L
#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK                                             0x02000000L
#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK                                             0x04000000L
#define GRBM_PERFCOUNTER1_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK                                             0x08000000L
#define GRBM_PERFCOUNTER1_SELECT__GE_BUSY_USER_DEFINED_MASK_MASK                                              0x10000000L
#define GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK                                           0x20000000L
#define GRBM_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK                                              0x40000000L
#define GRBM_PERFCOUNTER1_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK                                             0x80000000L
//GRBM_SE0_PERFCOUNTER_SELECT
#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL__SHIFT                                                          0x0
#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT                                        0xa
#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT                                        0xb
#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT                                         0xc
#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT                                         0xd
#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT                                        0xf
#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT                                         0x10
#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT                                         0x11
#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT                                         0x12
#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT                                         0x14
#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT                                        0x15
#define GRBM_SE0_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT                                        0x16
#define GRBM_SE0_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT                                      0x17
#define GRBM_SE0_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT                                        0x18
#define GRBM_SE0_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT                                      0x19
#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL_MASK                                                            0x0000003FL
#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK                                          0x00000400L
#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK                                          0x00000800L
#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK                                           0x00001000L
#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK                                           0x00002000L
#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK                                          0x00008000L
#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK                                           0x00010000L
#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK                                           0x00020000L
#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK                                           0x00040000L
#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK                                           0x00100000L
#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK                                          0x00200000L
#define GRBM_SE0_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK                                          0x00400000L
#define GRBM_SE0_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK_MASK                                        0x00800000L
#define GRBM_SE0_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK                                          0x01000000L
#define GRBM_SE0_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK_MASK                                        0x02000000L
//GRBM_SE1_PERFCOUNTER_SELECT
#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL__SHIFT                                                          0x0
#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT                                        0xa
#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT                                        0xb
#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT                                         0xc
#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT                                         0xd
#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT                                        0xf
#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT                                         0x10
#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT                                         0x11
#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT                                         0x12
#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT                                         0x14
#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT                                        0x15
#define GRBM_SE1_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT                                        0x16
#define GRBM_SE1_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT                                      0x17
#define GRBM_SE1_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT                                        0x18
#define GRBM_SE1_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT                                      0x19
#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL_MASK                                                            0x0000003FL
#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK                                          0x00000400L
#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK                                          0x00000800L
#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK                                           0x00001000L
#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK                                           0x00002000L
#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK                                          0x00008000L
#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK                                           0x00010000L
#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK                                           0x00020000L
#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK                                           0x00040000L
#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK                                           0x00100000L
#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK                                          0x00200000L
#define GRBM_SE1_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK                                          0x00400000L
#define GRBM_SE1_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK_MASK                                        0x00800000L
#define GRBM_SE1_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK                                          0x01000000L
#define GRBM_SE1_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK_MASK                                        0x02000000L
//GRBM_SE2_PERFCOUNTER_SELECT
#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL__SHIFT                                                          0x0
#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT                                        0xa
#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT                                        0xb
#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT                                         0xc
#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT                                         0xd
#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT                                        0xf
#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT                                         0x10
#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT                                         0x11
#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT                                         0x12
#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT                                         0x14
#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT                                        0x15
#define GRBM_SE2_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT                                        0x16
#define GRBM_SE2_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT                                      0x17
#define GRBM_SE2_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT                                        0x18
#define GRBM_SE2_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT                                      0x19
#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL_MASK                                                            0x0000003FL
#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK                                          0x00000400L
#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK                                          0x00000800L
#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK                                           0x00001000L
#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK                                           0x00002000L
#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK                                          0x00008000L
#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK                                           0x00010000L
#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK                                           0x00020000L
#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK                                           0x00040000L
#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK                                           0x00100000L
#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK                                          0x00200000L
#define GRBM_SE2_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK                                          0x00400000L
#define GRBM_SE2_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK_MASK                                        0x00800000L
#define GRBM_SE2_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK                                          0x01000000L
#define GRBM_SE2_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK_MASK                                        0x02000000L
//GRBM_SE3_PERFCOUNTER_SELECT
#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL__SHIFT                                                          0x0
#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT                                        0xa
#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT                                        0xb
#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT                                         0xc
#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT                                         0xd
#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT                                        0xf
#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT                                         0x10
#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT                                         0x11
#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT                                         0x12
#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT                                         0x14
#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT                                        0x15
#define GRBM_SE3_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT                                        0x16
#define GRBM_SE3_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT                                      0x17
#define GRBM_SE3_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT                                        0x18
#define GRBM_SE3_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT                                      0x19
#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL_MASK                                                            0x0000003FL
#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK                                          0x00000400L
#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK                                          0x00000800L
#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK                                           0x00001000L
#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK                                           0x00002000L
#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK                                          0x00008000L
#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK                                           0x00010000L
#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK                                           0x00020000L
#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK                                           0x00040000L
#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK                                           0x00100000L
#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK                                          0x00200000L
#define GRBM_SE3_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK                                          0x00400000L
#define GRBM_SE3_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK_MASK                                        0x00800000L
#define GRBM_SE3_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK                                          0x01000000L
#define GRBM_SE3_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK_MASK                                        0x02000000L
//GRBM_PERFCOUNTER0_SELECT_HI
#define GRBM_PERFCOUNTER0_SELECT_HI__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT                                      0x1
#define GRBM_PERFCOUNTER0_SELECT_HI__GL2CC_BUSY_USER_DEFINED_MASK__SHIFT                                      0x2
#define GRBM_PERFCOUNTER0_SELECT_HI__SDMA_BUSY_USER_DEFINED_MASK__SHIFT                                       0x3
#define GRBM_PERFCOUNTER0_SELECT_HI__CH_BUSY_USER_DEFINED_MASK__SHIFT                                         0x4
#define GRBM_PERFCOUNTER0_SELECT_HI__PH_BUSY_USER_DEFINED_MASK__SHIFT                                         0x5
#define GRBM_PERFCOUNTER0_SELECT_HI__PMM_BUSY_USER_DEFINED_MASK__SHIFT                                        0x6
#define GRBM_PERFCOUNTER0_SELECT_HI__GUS_BUSY_USER_DEFINED_MASK__SHIFT                                        0x7
#define GRBM_PERFCOUNTER0_SELECT_HI__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT                                      0x8
#define GRBM_PERFCOUNTER0_SELECT_HI__UTCL1_BUSY_USER_DEFINED_MASK_MASK                                        0x00000002L
#define GRBM_PERFCOUNTER0_SELECT_HI__GL2CC_BUSY_USER_DEFINED_MASK_MASK                                        0x00000004L
#define GRBM_PERFCOUNTER0_SELECT_HI__SDMA_BUSY_USER_DEFINED_MASK_MASK                                         0x00000008L
#define GRBM_PERFCOUNTER0_SELECT_HI__CH_BUSY_USER_DEFINED_MASK_MASK                                           0x00000010L
#define GRBM_PERFCOUNTER0_SELECT_HI__PH_BUSY_USER_DEFINED_MASK_MASK                                           0x00000020L
#define GRBM_PERFCOUNTER0_SELECT_HI__PMM_BUSY_USER_DEFINED_MASK_MASK                                          0x00000040L
#define GRBM_PERFCOUNTER0_SELECT_HI__GUS_BUSY_USER_DEFINED_MASK_MASK                                          0x00000080L
#define GRBM_PERFCOUNTER0_SELECT_HI__GL1CC_BUSY_USER_DEFINED_MASK_MASK                                        0x00000100L
//GRBM_PERFCOUNTER1_SELECT_HI
#define GRBM_PERFCOUNTER1_SELECT_HI__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT                                      0x1
#define GRBM_PERFCOUNTER1_SELECT_HI__GL2CC_BUSY_USER_DEFINED_MASK__SHIFT                                      0x2
#define GRBM_PERFCOUNTER1_SELECT_HI__SDMA_BUSY_USER_DEFINED_MASK__SHIFT                                       0x3
#define GRBM_PERFCOUNTER1_SELECT_HI__CH_BUSY_USER_DEFINED_MASK__SHIFT                                         0x4
#define GRBM_PERFCOUNTER1_SELECT_HI__PH_BUSY_USER_DEFINED_MASK__SHIFT                                         0x5
#define GRBM_PERFCOUNTER1_SELECT_HI__PMM_BUSY_USER_DEFINED_MASK__SHIFT                                        0x6
#define GRBM_PERFCOUNTER1_SELECT_HI__GUS_BUSY_USER_DEFINED_MASK__SHIFT                                        0x7
#define GRBM_PERFCOUNTER1_SELECT_HI__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT                                      0x8
#define GRBM_PERFCOUNTER1_SELECT_HI__UTCL1_BUSY_USER_DEFINED_MASK_MASK                                        0x00000002L
#define GRBM_PERFCOUNTER1_SELECT_HI__GL2CC_BUSY_USER_DEFINED_MASK_MASK                                        0x00000004L
#define GRBM_PERFCOUNTER1_SELECT_HI__SDMA_BUSY_USER_DEFINED_MASK_MASK                                         0x00000008L
#define GRBM_PERFCOUNTER1_SELECT_HI__CH_BUSY_USER_DEFINED_MASK_MASK                                           0x00000010L
#define GRBM_PERFCOUNTER1_SELECT_HI__PH_BUSY_USER_DEFINED_MASK_MASK                                           0x00000020L
#define GRBM_PERFCOUNTER1_SELECT_HI__PMM_BUSY_USER_DEFINED_MASK_MASK                                          0x00000040L
#define GRBM_PERFCOUNTER1_SELECT_HI__GUS_BUSY_USER_DEFINED_MASK_MASK                                          0x00000080L
#define GRBM_PERFCOUNTER1_SELECT_HI__GL1CC_BUSY_USER_DEFINED_MASK_MASK                                        0x00000100L
//GE1_PERFCOUNTER0_SELECT
#define GE1_PERFCOUNTER0_SELECT__PERF_SEL0__SHIFT                                                             0x0
#define GE1_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                             0xa
#define GE1_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                             0x14
#define GE1_PERFCOUNTER0_SELECT__PERF_MODE0__SHIFT                                                            0x18
#define GE1_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                            0x1c
#define GE1_PERFCOUNTER0_SELECT__PERF_SEL0_MASK                                                               0x000003FFL
#define GE1_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
#define GE1_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
#define GE1_PERFCOUNTER0_SELECT__PERF_MODE0_MASK                                                              0x0F000000L
#define GE1_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                              0xF0000000L
//GE1_PERFCOUNTER0_SELECT1
#define GE1_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                            0x0
#define GE1_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                            0xa
#define GE1_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                           0x18
#define GE1_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                           0x1c
#define GE1_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
#define GE1_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
#define GE1_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                             0x0F000000L
#define GE1_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                             0xF0000000L
//GE1_PERFCOUNTER1_SELECT
#define GE1_PERFCOUNTER1_SELECT__PERF_SEL0__SHIFT                                                             0x0
#define GE1_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT                                                             0xa
#define GE1_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                             0x14
#define GE1_PERFCOUNTER1_SELECT__PERF_MODE0__SHIFT                                                            0x18
#define GE1_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT                                                            0x1c
#define GE1_PERFCOUNTER1_SELECT__PERF_SEL0_MASK                                                               0x000003FFL
#define GE1_PERFCOUNTER1_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
#define GE1_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
#define GE1_PERFCOUNTER1_SELECT__PERF_MODE0_MASK                                                              0x0F000000L
#define GE1_PERFCOUNTER1_SELECT__PERF_MODE1_MASK                                                              0xF0000000L
//GE1_PERFCOUNTER1_SELECT1
#define GE1_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT                                                            0x0
#define GE1_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT                                                            0xa
#define GE1_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT                                                           0x18
#define GE1_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT                                                           0x1c
#define GE1_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
#define GE1_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
#define GE1_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK                                                             0x0F000000L
#define GE1_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK                                                             0xF0000000L
//GE1_PERFCOUNTER2_SELECT
#define GE1_PERFCOUNTER2_SELECT__PERF_SEL0__SHIFT                                                             0x0
#define GE1_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT                                                             0xa
#define GE1_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                             0x14
#define GE1_PERFCOUNTER2_SELECT__PERF_MODE0__SHIFT                                                            0x18
#define GE1_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT                                                            0x1c
#define GE1_PERFCOUNTER2_SELECT__PERF_SEL0_MASK                                                               0x000003FFL
#define GE1_PERFCOUNTER2_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
#define GE1_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
#define GE1_PERFCOUNTER2_SELECT__PERF_MODE0_MASK                                                              0x0F000000L
#define GE1_PERFCOUNTER2_SELECT__PERF_MODE1_MASK                                                              0xF0000000L
//GE1_PERFCOUNTER2_SELECT1
#define GE1_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT                                                            0x0
#define GE1_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT                                                            0xa
#define GE1_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT                                                           0x18
#define GE1_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT                                                           0x1c
#define GE1_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
#define GE1_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
#define GE1_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK                                                             0x0F000000L
#define GE1_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK                                                             0xF0000000L
//GE1_PERFCOUNTER3_SELECT
#define GE1_PERFCOUNTER3_SELECT__PERF_SEL0__SHIFT                                                             0x0
#define GE1_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT                                                             0xa
#define GE1_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT                                                             0x14
#define GE1_PERFCOUNTER3_SELECT__PERF_MODE0__SHIFT                                                            0x18
#define GE1_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT                                                            0x1c
#define GE1_PERFCOUNTER3_SELECT__PERF_SEL0_MASK                                                               0x000003FFL
#define GE1_PERFCOUNTER3_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
#define GE1_PERFCOUNTER3_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
#define GE1_PERFCOUNTER3_SELECT__PERF_MODE0_MASK                                                              0x0F000000L
#define GE1_PERFCOUNTER3_SELECT__PERF_MODE1_MASK                                                              0xF0000000L
//GE1_PERFCOUNTER3_SELECT1
#define GE1_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT                                                            0x0
#define GE1_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT                                                            0xa
#define GE1_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT                                                           0x18
#define GE1_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT                                                           0x1c
#define GE1_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
#define GE1_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
#define GE1_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK                                                             0x0F000000L
#define GE1_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK                                                             0xF0000000L
//GE2_DIST_PERFCOUNTER0_SELECT
#define GE2_DIST_PERFCOUNTER0_SELECT__PERF_SEL0__SHIFT                                                        0x0
#define GE2_DIST_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                        0xa
#define GE2_DIST_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                        0x14
#define GE2_DIST_PERFCOUNTER0_SELECT__PERF_MODE0__SHIFT                                                       0x18
#define GE2_DIST_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                       0x1c
#define GE2_DIST_PERFCOUNTER0_SELECT__PERF_SEL0_MASK                                                          0x000003FFL
#define GE2_DIST_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                          0x000FFC00L
#define GE2_DIST_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                          0x00F00000L
#define GE2_DIST_PERFCOUNTER0_SELECT__PERF_MODE0_MASK                                                         0x0F000000L
#define GE2_DIST_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                         0xF0000000L
//GE2_DIST_PERFCOUNTER0_SELECT1
#define GE2_DIST_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                       0x0
#define GE2_DIST_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                       0xa
#define GE2_DIST_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                      0x18
#define GE2_DIST_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                      0x1c
#define GE2_DIST_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                         0x000003FFL
#define GE2_DIST_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                         0x000FFC00L
#define GE2_DIST_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                        0x0F000000L
#define GE2_DIST_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                        0xF0000000L
//GE2_DIST_PERFCOUNTER1_SELECT
#define GE2_DIST_PERFCOUNTER1_SELECT__PERF_SEL0__SHIFT                                                        0x0
#define GE2_DIST_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT                                                        0xa
#define GE2_DIST_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                        0x14
#define GE2_DIST_PERFCOUNTER1_SELECT__PERF_MODE0__SHIFT                                                       0x18
#define GE2_DIST_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT                                                       0x1c
#define GE2_DIST_PERFCOUNTER1_SELECT__PERF_SEL0_MASK                                                          0x000003FFL
#define GE2_DIST_PERFCOUNTER1_SELECT__PERF_SEL1_MASK                                                          0x000FFC00L
#define GE2_DIST_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                          0x00F00000L
#define GE2_DIST_PERFCOUNTER1_SELECT__PERF_MODE0_MASK                                                         0x0F000000L
#define GE2_DIST_PERFCOUNTER1_SELECT__PERF_MODE1_MASK                                                         0xF0000000L
//GE2_DIST_PERFCOUNTER1_SELECT1
#define GE2_DIST_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT                                                       0x0
#define GE2_DIST_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT                                                       0xa
#define GE2_DIST_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT                                                      0x18
#define GE2_DIST_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT                                                      0x1c
#define GE2_DIST_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK                                                         0x000003FFL
#define GE2_DIST_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK                                                         0x000FFC00L
#define GE2_DIST_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK                                                        0x0F000000L
#define GE2_DIST_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK                                                        0xF0000000L
//GE2_DIST_PERFCOUNTER2_SELECT
#define GE2_DIST_PERFCOUNTER2_SELECT__PERF_SEL0__SHIFT                                                        0x0
#define GE2_DIST_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT                                                        0xa
#define GE2_DIST_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                        0x14
#define GE2_DIST_PERFCOUNTER2_SELECT__PERF_MODE0__SHIFT                                                       0x18
#define GE2_DIST_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT                                                       0x1c
#define GE2_DIST_PERFCOUNTER2_SELECT__PERF_SEL0_MASK                                                          0x000003FFL
#define GE2_DIST_PERFCOUNTER2_SELECT__PERF_SEL1_MASK                                                          0x000FFC00L
#define GE2_DIST_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                          0x00F00000L
#define GE2_DIST_PERFCOUNTER2_SELECT__PERF_MODE0_MASK                                                         0x0F000000L
#define GE2_DIST_PERFCOUNTER2_SELECT__PERF_MODE1_MASK                                                         0xF0000000L
//GE2_DIST_PERFCOUNTER2_SELECT1
#define GE2_DIST_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT                                                       0x0
#define GE2_DIST_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT                                                       0xa
#define GE2_DIST_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT                                                      0x18
#define GE2_DIST_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT                                                      0x1c
#define GE2_DIST_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK                                                         0x000003FFL
#define GE2_DIST_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK                                                         0x000FFC00L
#define GE2_DIST_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK                                                        0x0F000000L
#define GE2_DIST_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK                                                        0xF0000000L
//GE2_DIST_PERFCOUNTER3_SELECT
#define GE2_DIST_PERFCOUNTER3_SELECT__PERF_SEL0__SHIFT                                                        0x0
#define GE2_DIST_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT                                                        0xa
#define GE2_DIST_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT                                                        0x14
#define GE2_DIST_PERFCOUNTER3_SELECT__PERF_MODE0__SHIFT                                                       0x18
#define GE2_DIST_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT                                                       0x1c
#define GE2_DIST_PERFCOUNTER3_SELECT__PERF_SEL0_MASK                                                          0x000003FFL
#define GE2_DIST_PERFCOUNTER3_SELECT__PERF_SEL1_MASK                                                          0x000FFC00L
#define GE2_DIST_PERFCOUNTER3_SELECT__CNTR_MODE_MASK                                                          0x00F00000L
#define GE2_DIST_PERFCOUNTER3_SELECT__PERF_MODE0_MASK                                                         0x0F000000L
#define GE2_DIST_PERFCOUNTER3_SELECT__PERF_MODE1_MASK                                                         0xF0000000L
//GE2_DIST_PERFCOUNTER3_SELECT1
#define GE2_DIST_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT                                                       0x0
#define GE2_DIST_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT                                                       0xa
#define GE2_DIST_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT                                                      0x18
#define GE2_DIST_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT                                                      0x1c
#define GE2_DIST_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK                                                         0x000003FFL
#define GE2_DIST_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK                                                         0x000FFC00L
#define GE2_DIST_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK                                                        0x0F000000L
#define GE2_DIST_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK                                                        0xF0000000L
//GE2_SE_PERFCOUNTER0_SELECT
#define GE2_SE_PERFCOUNTER0_SELECT__PERF_SEL0__SHIFT                                                          0x0
#define GE2_SE_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                          0xa
#define GE2_SE_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                          0x14
#define GE2_SE_PERFCOUNTER0_SELECT__PERF_MODE0__SHIFT                                                         0x18
#define GE2_SE_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                         0x1c
#define GE2_SE_PERFCOUNTER0_SELECT__PERF_SEL0_MASK                                                            0x000003FFL
#define GE2_SE_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                            0x000FFC00L
#define GE2_SE_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                            0x00F00000L
#define GE2_SE_PERFCOUNTER0_SELECT__PERF_MODE0_MASK                                                           0x0F000000L
#define GE2_SE_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                           0xF0000000L
//GE2_SE_PERFCOUNTER0_SELECT1
#define GE2_SE_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                         0x0
#define GE2_SE_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                         0xa
#define GE2_SE_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                        0x18
#define GE2_SE_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                        0x1c
#define GE2_SE_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                           0x000003FFL
#define GE2_SE_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                           0x000FFC00L
#define GE2_SE_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                          0x0F000000L
#define GE2_SE_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                          0xF0000000L
//GE2_SE_PERFCOUNTER1_SELECT
#define GE2_SE_PERFCOUNTER1_SELECT__PERF_SEL0__SHIFT                                                          0x0
#define GE2_SE_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT                                                          0xa
#define GE2_SE_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                          0x14
#define GE2_SE_PERFCOUNTER1_SELECT__PERF_MODE0__SHIFT                                                         0x18
#define GE2_SE_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT                                                         0x1c
#define GE2_SE_PERFCOUNTER1_SELECT__PERF_SEL0_MASK                                                            0x000003FFL
#define GE2_SE_PERFCOUNTER1_SELECT__PERF_SEL1_MASK                                                            0x000FFC00L
#define GE2_SE_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                            0x00F00000L
#define GE2_SE_PERFCOUNTER1_SELECT__PERF_MODE0_MASK                                                           0x0F000000L
#define GE2_SE_PERFCOUNTER1_SELECT__PERF_MODE1_MASK                                                           0xF0000000L
//GE2_SE_PERFCOUNTER1_SELECT1
#define GE2_SE_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT                                                         0x0
#define GE2_SE_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT                                                         0xa
#define GE2_SE_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT                                                        0x18
#define GE2_SE_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT                                                        0x1c
#define GE2_SE_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK                                                           0x000003FFL
#define GE2_SE_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK                                                           0x000FFC00L
#define GE2_SE_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK                                                          0x0F000000L
#define GE2_SE_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK                                                          0xF0000000L
//GE2_SE_PERFCOUNTER2_SELECT
#define GE2_SE_PERFCOUNTER2_SELECT__PERF_SEL0__SHIFT                                                          0x0
#define GE2_SE_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT                                                          0xa
#define GE2_SE_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                          0x14
#define GE2_SE_PERFCOUNTER2_SELECT__PERF_MODE0__SHIFT                                                         0x18
#define GE2_SE_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT                                                         0x1c
#define GE2_SE_PERFCOUNTER2_SELECT__PERF_SEL0_MASK                                                            0x000003FFL
#define GE2_SE_PERFCOUNTER2_SELECT__PERF_SEL1_MASK                                                            0x000FFC00L
#define GE2_SE_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                            0x00F00000L
#define GE2_SE_PERFCOUNTER2_SELECT__PERF_MODE0_MASK                                                           0x0F000000L
#define GE2_SE_PERFCOUNTER2_SELECT__PERF_MODE1_MASK                                                           0xF0000000L
//GE2_SE_PERFCOUNTER2_SELECT1
#define GE2_SE_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT                                                         0x0
#define GE2_SE_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT                                                         0xa
#define GE2_SE_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT                                                        0x18
#define GE2_SE_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT                                                        0x1c
#define GE2_SE_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK                                                           0x000003FFL
#define GE2_SE_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK                                                           0x000FFC00L
#define GE2_SE_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK                                                          0x0F000000L
#define GE2_SE_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK                                                          0xF0000000L
//GE2_SE_PERFCOUNTER3_SELECT
#define GE2_SE_PERFCOUNTER3_SELECT__PERF_SEL0__SHIFT                                                          0x0
#define GE2_SE_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT                                                          0xa
#define GE2_SE_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT                                                          0x14
#define GE2_SE_PERFCOUNTER3_SELECT__PERF_MODE0__SHIFT                                                         0x18
#define GE2_SE_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT                                                         0x1c
#define GE2_SE_PERFCOUNTER3_SELECT__PERF_SEL0_MASK                                                            0x000003FFL
#define GE2_SE_PERFCOUNTER3_SELECT__PERF_SEL1_MASK                                                            0x000FFC00L
#define GE2_SE_PERFCOUNTER3_SELECT__CNTR_MODE_MASK                                                            0x00F00000L
#define GE2_SE_PERFCOUNTER3_SELECT__PERF_MODE0_MASK                                                           0x0F000000L
#define GE2_SE_PERFCOUNTER3_SELECT__PERF_MODE1_MASK                                                           0xF0000000L
//GE2_SE_PERFCOUNTER3_SELECT1
#define GE2_SE_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT                                                         0x0
#define GE2_SE_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT                                                         0xa
#define GE2_SE_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT                                                        0x18
#define GE2_SE_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT                                                        0x1c
#define GE2_SE_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK                                                           0x000003FFL
#define GE2_SE_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK                                                           0x000FFC00L
#define GE2_SE_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK                                                          0x0F000000L
#define GE2_SE_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK                                                          0xF0000000L
//PA_SU_PERFCOUNTER0_SELECT
#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                            0x0
#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                           0xa
#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                           0x14
#define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                          0x18
#define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                           0x1c
#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                              0x000003FFL
#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                             0x000FFC00L
#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                             0x00F00000L
#define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                            0x0F000000L
#define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                             0xF0000000L
//PA_SU_PERFCOUNTER0_SELECT1
#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                          0x0
#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                          0xa
#define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                         0x18
#define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                         0x1c
#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                            0x000003FFL
#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                            0x000FFC00L
#define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                           0x0F000000L
#define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                           0xF0000000L
//PA_SU_PERFCOUNTER1_SELECT
#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                            0x0
#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT                                                           0xa
#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                           0x14
#define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT                                                          0x18
#define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                           0x1c
#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                              0x000003FFL
#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1_MASK                                                             0x000FFC00L
#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                             0x00F00000L
#define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE1_MASK                                                            0x0F000000L
#define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                             0xF0000000L
//PA_SU_PERFCOUNTER1_SELECT1
#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT                                                          0x0
#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT                                                          0xa
#define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT                                                         0x18
#define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT                                                         0x1c
#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK                                                            0x000003FFL
#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK                                                            0x000FFC00L
#define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK                                                           0x0F000000L
#define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK                                                           0xF0000000L
//PA_SU_PERFCOUNTER2_SELECT
#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                            0x0
#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT                                                           0xa
#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                           0x14
#define PA_SU_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT                                                          0x18
#define PA_SU_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                           0x1c
#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                              0x000003FFL
#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL1_MASK                                                             0x000FFC00L
#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                             0x00F00000L
#define PA_SU_PERFCOUNTER2_SELECT__PERF_MODE1_MASK                                                            0x0F000000L
#define PA_SU_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                             0xF0000000L
//PA_SU_PERFCOUNTER2_SELECT1
#define PA_SU_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT                                                          0x0
#define PA_SU_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT                                                          0xa
#define PA_SU_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT                                                         0x18
#define PA_SU_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT                                                         0x1c
#define PA_SU_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK                                                            0x000003FFL
#define PA_SU_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK                                                            0x000FFC00L
#define PA_SU_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK                                                           0x0F000000L
#define PA_SU_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK                                                           0xF0000000L
//PA_SU_PERFCOUNTER3_SELECT
#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                            0x0
#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT                                                           0xa
#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT                                                           0x14
#define PA_SU_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT                                                          0x18
#define PA_SU_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                           0x1c
#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                              0x000003FFL
#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL1_MASK                                                             0x000FFC00L
#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE_MASK                                                             0x00F00000L
#define PA_SU_PERFCOUNTER3_SELECT__PERF_MODE1_MASK                                                            0x0F000000L
#define PA_SU_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                             0xF0000000L
//PA_SU_PERFCOUNTER3_SELECT1
#define PA_SU_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT                                                          0x0
#define PA_SU_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT                                                          0xa
#define PA_SU_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT                                                         0x18
#define PA_SU_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT                                                         0x1c
#define PA_SU_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK                                                            0x000003FFL
#define PA_SU_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK                                                            0x000FFC00L
#define PA_SU_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK                                                           0x0F000000L
#define PA_SU_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK                                                           0xF0000000L
//PA_SC_PERFCOUNTER0_SELECT
#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                            0x0
#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                           0xa
#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                           0x14
#define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                          0x18
#define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                           0x1c
#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                              0x000003FFL
#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                             0x000FFC00L
#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                             0x00F00000L
#define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                            0x0F000000L
#define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                             0xF0000000L
//PA_SC_PERFCOUNTER0_SELECT1
#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                          0x0
#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                          0xa
#define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                         0x18
#define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                         0x1c
#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                            0x000003FFL
#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                            0x000FFC00L
#define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                           0x0F000000L
#define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                           0xF0000000L
//PA_SC_PERFCOUNTER1_SELECT
#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                            0x0
#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                              0x000003FFL
//PA_SC_PERFCOUNTER2_SELECT
#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                            0x0
#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                              0x000003FFL
//PA_SC_PERFCOUNTER3_SELECT
#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                            0x0
#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                              0x000003FFL
//PA_SC_PERFCOUNTER4_SELECT
#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT                                                            0x0
#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL_MASK                                                              0x000003FFL
//PA_SC_PERFCOUNTER5_SELECT
#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT                                                            0x0
#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL_MASK                                                              0x000003FFL
//PA_SC_PERFCOUNTER6_SELECT
#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT                                                            0x0
#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL_MASK                                                              0x000003FFL
//PA_SC_PERFCOUNTER7_SELECT
#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT                                                            0x0
#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL_MASK                                                              0x000003FFL
//SPI_PERFCOUNTER0_SELECT
#define SPI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                              0x0
#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                             0xa
#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                             0x14
#define SPI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                            0x18
#define SPI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                             0x1c
#define SPI_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                0x000003FFL
#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
#define SPI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
#define SPI_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                               0xF0000000L
//SPI_PERFCOUNTER1_SELECT
#define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                              0x0
#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT                                                             0xa
#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                             0x14
#define SPI_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT                                                            0x18
#define SPI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                             0x1c
#define SPI_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                0x000003FFL
#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
#define SPI_PERFCOUNTER1_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
#define SPI_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                               0xF0000000L
//SPI_PERFCOUNTER2_SELECT
#define SPI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                              0x0
#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT                                                             0xa
#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                             0x14
#define SPI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT                                                            0x18
#define SPI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                             0x1c
#define SPI_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                                0x000003FFL
#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
#define SPI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
#define SPI_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                               0xF0000000L
//SPI_PERFCOUNTER3_SELECT
#define SPI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                              0x0
#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT                                                             0xa
#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT                                                             0x14
#define SPI_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT                                                            0x18
#define SPI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                             0x1c
#define SPI_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                                0x000003FFL
#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
#define SPI_PERFCOUNTER3_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
#define SPI_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                               0xF0000000L
//SPI_PERFCOUNTER0_SELECT1
#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                            0x0
#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                            0xa
#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                           0x18
#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                           0x1c
#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                             0x0F000000L
#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                             0xF0000000L
//SPI_PERFCOUNTER1_SELECT1
#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT                                                            0x0
#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT                                                            0xa
#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT                                                           0x18
#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT                                                           0x1c
#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK                                                             0x0F000000L
#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK                                                             0xF0000000L
//SPI_PERFCOUNTER2_SELECT1
#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT                                                            0x0
#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT                                                            0xa
#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT                                                           0x18
#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT                                                           0x1c
#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK                                                             0x0F000000L
#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK                                                             0xF0000000L
//SPI_PERFCOUNTER3_SELECT1
#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT                                                            0x0
#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT                                                            0xa
#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT                                                           0x18
#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT                                                           0x1c
#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK                                                             0x0F000000L
#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK                                                             0xF0000000L
//SPI_PERFCOUNTER4_SELECT
#define SPI_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT                                                              0x0
#define SPI_PERFCOUNTER4_SELECT__PERF_SEL_MASK                                                                0x000003FFL
//SPI_PERFCOUNTER5_SELECT
#define SPI_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT                                                              0x0
#define SPI_PERFCOUNTER5_SELECT__PERF_SEL_MASK                                                                0x000003FFL
//SPI_PERFCOUNTER_BINS
#define SPI_PERFCOUNTER_BINS__BIN0_MIN__SHIFT                                                                 0x0
#define SPI_PERFCOUNTER_BINS__BIN0_MAX__SHIFT                                                                 0x4
#define SPI_PERFCOUNTER_BINS__BIN1_MIN__SHIFT                                                                 0x8
#define SPI_PERFCOUNTER_BINS__BIN1_MAX__SHIFT                                                                 0xc
#define SPI_PERFCOUNTER_BINS__BIN2_MIN__SHIFT                                                                 0x10
#define SPI_PERFCOUNTER_BINS__BIN2_MAX__SHIFT                                                                 0x14
#define SPI_PERFCOUNTER_BINS__BIN3_MIN__SHIFT                                                                 0x18
#define SPI_PERFCOUNTER_BINS__BIN3_MAX__SHIFT                                                                 0x1c
#define SPI_PERFCOUNTER_BINS__BIN0_MIN_MASK                                                                   0x0000000FL
#define SPI_PERFCOUNTER_BINS__BIN0_MAX_MASK                                                                   0x000000F0L
#define SPI_PERFCOUNTER_BINS__BIN1_MIN_MASK                                                                   0x00000F00L
#define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK                                                                   0x0000F000L
#define SPI_PERFCOUNTER_BINS__BIN2_MIN_MASK                                                                   0x000F0000L
#define SPI_PERFCOUNTER_BINS__BIN2_MAX_MASK                                                                   0x00F00000L
#define SPI_PERFCOUNTER_BINS__BIN3_MIN_MASK                                                                   0x0F000000L
#define SPI_PERFCOUNTER_BINS__BIN3_MAX_MASK                                                                   0xF0000000L
//SQ_PERFCOUNTER0_SELECT
#define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                               0x0
#define SQ_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT                                                               0x14
#define SQ_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                              0x1c
#define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
#define SQ_PERFCOUNTER0_SELECT__SPM_MODE_MASK                                                                 0x00F00000L
#define SQ_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                                0xF0000000L
//SQ_PERFCOUNTER1_SELECT
#define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                               0x0
#define SQ_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT                                                               0x14
#define SQ_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                              0x1c
#define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
#define SQ_PERFCOUNTER1_SELECT__SPM_MODE_MASK                                                                 0x00F00000L
#define SQ_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                                0xF0000000L
//SQ_PERFCOUNTER2_SELECT
#define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                               0x0
#define SQ_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT                                                               0x14
#define SQ_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                              0x1c
#define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
#define SQ_PERFCOUNTER2_SELECT__SPM_MODE_MASK                                                                 0x00F00000L
#define SQ_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                                0xF0000000L
//SQ_PERFCOUNTER3_SELECT
#define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                               0x0
#define SQ_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT                                                               0x14
#define SQ_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                              0x1c
#define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
#define SQ_PERFCOUNTER3_SELECT__SPM_MODE_MASK                                                                 0x00F00000L
#define SQ_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                                0xF0000000L
//SQ_PERFCOUNTER4_SELECT
#define SQ_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT                                                               0x0
#define SQ_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT                                                               0x14
#define SQ_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT                                                              0x1c
#define SQ_PERFCOUNTER4_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
#define SQ_PERFCOUNTER4_SELECT__SPM_MODE_MASK                                                                 0x00F00000L
#define SQ_PERFCOUNTER4_SELECT__PERF_MODE_MASK                                                                0xF0000000L
//SQ_PERFCOUNTER5_SELECT
#define SQ_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT                                                               0x0
#define SQ_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT                                                               0x14
#define SQ_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT                                                              0x1c
#define SQ_PERFCOUNTER5_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
#define SQ_PERFCOUNTER5_SELECT__SPM_MODE_MASK                                                                 0x00F00000L
#define SQ_PERFCOUNTER5_SELECT__PERF_MODE_MASK                                                                0xF0000000L
//SQ_PERFCOUNTER6_SELECT
#define SQ_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT                                                               0x0
#define SQ_PERFCOUNTER6_SELECT__SPM_MODE__SHIFT                                                               0x14
#define SQ_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT                                                              0x1c
#define SQ_PERFCOUNTER6_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
#define SQ_PERFCOUNTER6_SELECT__SPM_MODE_MASK                                                                 0x00F00000L
#define SQ_PERFCOUNTER6_SELECT__PERF_MODE_MASK                                                                0xF0000000L
//SQ_PERFCOUNTER7_SELECT
#define SQ_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT                                                               0x0
#define SQ_PERFCOUNTER7_SELECT__SPM_MODE__SHIFT                                                               0x14
#define SQ_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT                                                              0x1c
#define SQ_PERFCOUNTER7_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
#define SQ_PERFCOUNTER7_SELECT__SPM_MODE_MASK                                                                 0x00F00000L
#define SQ_PERFCOUNTER7_SELECT__PERF_MODE_MASK                                                                0xF0000000L
//SQ_PERFCOUNTER8_SELECT
#define SQ_PERFCOUNTER8_SELECT__PERF_SEL__SHIFT                                                               0x0
#define SQ_PERFCOUNTER8_SELECT__SPM_MODE__SHIFT                                                               0x14
#define SQ_PERFCOUNTER8_SELECT__PERF_MODE__SHIFT                                                              0x1c
#define SQ_PERFCOUNTER8_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
#define SQ_PERFCOUNTER8_SELECT__SPM_MODE_MASK                                                                 0x00F00000L
#define SQ_PERFCOUNTER8_SELECT__PERF_MODE_MASK                                                                0xF0000000L
//SQ_PERFCOUNTER9_SELECT
#define SQ_PERFCOUNTER9_SELECT__PERF_SEL__SHIFT                                                               0x0
#define SQ_PERFCOUNTER9_SELECT__SPM_MODE__SHIFT                                                               0x14
#define SQ_PERFCOUNTER9_SELECT__PERF_MODE__SHIFT                                                              0x1c
#define SQ_PERFCOUNTER9_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
#define SQ_PERFCOUNTER9_SELECT__SPM_MODE_MASK                                                                 0x00F00000L
#define SQ_PERFCOUNTER9_SELECT__PERF_MODE_MASK                                                                0xF0000000L
//SQ_PERFCOUNTER10_SELECT
#define SQ_PERFCOUNTER10_SELECT__PERF_SEL__SHIFT                                                              0x0
#define SQ_PERFCOUNTER10_SELECT__SPM_MODE__SHIFT                                                              0x14
#define SQ_PERFCOUNTER10_SELECT__PERF_MODE__SHIFT                                                             0x1c
#define SQ_PERFCOUNTER10_SELECT__PERF_SEL_MASK                                                                0x000001FFL
#define SQ_PERFCOUNTER10_SELECT__SPM_MODE_MASK                                                                0x00F00000L
#define SQ_PERFCOUNTER10_SELECT__PERF_MODE_MASK                                                               0xF0000000L
//SQ_PERFCOUNTER11_SELECT
#define SQ_PERFCOUNTER11_SELECT__PERF_SEL__SHIFT                                                              0x0
#define SQ_PERFCOUNTER11_SELECT__SPM_MODE__SHIFT                                                              0x14
#define SQ_PERFCOUNTER11_SELECT__PERF_MODE__SHIFT                                                             0x1c
#define SQ_PERFCOUNTER11_SELECT__PERF_SEL_MASK                                                                0x000001FFL
#define SQ_PERFCOUNTER11_SELECT__SPM_MODE_MASK                                                                0x00F00000L
#define SQ_PERFCOUNTER11_SELECT__PERF_MODE_MASK                                                               0xF0000000L
//SQ_PERFCOUNTER12_SELECT
#define SQ_PERFCOUNTER12_SELECT__PERF_SEL__SHIFT                                                              0x0
#define SQ_PERFCOUNTER12_SELECT__SPM_MODE__SHIFT                                                              0x14
#define SQ_PERFCOUNTER12_SELECT__PERF_MODE__SHIFT                                                             0x1c
#define SQ_PERFCOUNTER12_SELECT__PERF_SEL_MASK                                                                0x000001FFL
#define SQ_PERFCOUNTER12_SELECT__SPM_MODE_MASK                                                                0x00F00000L
#define SQ_PERFCOUNTER12_SELECT__PERF_MODE_MASK                                                               0xF0000000L
//SQ_PERFCOUNTER13_SELECT
#define SQ_PERFCOUNTER13_SELECT__PERF_SEL__SHIFT                                                              0x0
#define SQ_PERFCOUNTER13_SELECT__SPM_MODE__SHIFT                                                              0x14
#define SQ_PERFCOUNTER13_SELECT__PERF_MODE__SHIFT                                                             0x1c
#define SQ_PERFCOUNTER13_SELECT__PERF_SEL_MASK                                                                0x000001FFL
#define SQ_PERFCOUNTER13_SELECT__SPM_MODE_MASK                                                                0x00F00000L
#define SQ_PERFCOUNTER13_SELECT__PERF_MODE_MASK                                                               0xF0000000L
//SQ_PERFCOUNTER14_SELECT
#define SQ_PERFCOUNTER14_SELECT__PERF_SEL__SHIFT                                                              0x0
#define SQ_PERFCOUNTER14_SELECT__SPM_MODE__SHIFT                                                              0x14
#define SQ_PERFCOUNTER14_SELECT__PERF_MODE__SHIFT                                                             0x1c
#define SQ_PERFCOUNTER14_SELECT__PERF_SEL_MASK                                                                0x000001FFL
#define SQ_PERFCOUNTER14_SELECT__SPM_MODE_MASK                                                                0x00F00000L
#define SQ_PERFCOUNTER14_SELECT__PERF_MODE_MASK                                                               0xF0000000L
//SQ_PERFCOUNTER15_SELECT
#define SQ_PERFCOUNTER15_SELECT__PERF_SEL__SHIFT                                                              0x0
#define SQ_PERFCOUNTER15_SELECT__SPM_MODE__SHIFT                                                              0x14
#define SQ_PERFCOUNTER15_SELECT__PERF_MODE__SHIFT                                                             0x1c
#define SQ_PERFCOUNTER15_SELECT__PERF_SEL_MASK                                                                0x000001FFL
#define SQ_PERFCOUNTER15_SELECT__SPM_MODE_MASK                                                                0x00F00000L
#define SQ_PERFCOUNTER15_SELECT__PERF_MODE_MASK                                                               0xF0000000L
//SQ_PERFCOUNTER_CTRL
#define SQ_PERFCOUNTER_CTRL__PS_EN__SHIFT                                                                     0x0
#define SQ_PERFCOUNTER_CTRL__VS_EN__SHIFT                                                                     0x1
#define SQ_PERFCOUNTER_CTRL__GS_EN__SHIFT                                                                     0x2
#define SQ_PERFCOUNTER_CTRL__ES_EN__SHIFT                                                                     0x3
#define SQ_PERFCOUNTER_CTRL__HS_EN__SHIFT                                                                     0x4
#define SQ_PERFCOUNTER_CTRL__LS_EN__SHIFT                                                                     0x5
#define SQ_PERFCOUNTER_CTRL__CS_EN__SHIFT                                                                     0x6
#define SQ_PERFCOUNTER_CTRL__CNTR_RATE__SHIFT                                                                 0x8
#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH__SHIFT                                                             0xd
#define SQ_PERFCOUNTER_CTRL__DISABLE_ME0PIPE0_PERF__SHIFT                                                     0xe
#define SQ_PERFCOUNTER_CTRL__DISABLE_ME0PIPE1_PERF__SHIFT                                                     0xf
#define SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE0_PERF__SHIFT                                                     0x10
#define SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE1_PERF__SHIFT                                                     0x11
#define SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE2_PERF__SHIFT                                                     0x12
#define SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE3_PERF__SHIFT                                                     0x13
#define SQ_PERFCOUNTER_CTRL__PS_EN_MASK                                                                       0x00000001L
#define SQ_PERFCOUNTER_CTRL__VS_EN_MASK                                                                       0x00000002L
#define SQ_PERFCOUNTER_CTRL__GS_EN_MASK                                                                       0x00000004L
#define SQ_PERFCOUNTER_CTRL__ES_EN_MASK                                                                       0x00000008L
#define SQ_PERFCOUNTER_CTRL__HS_EN_MASK                                                                       0x00000010L
#define SQ_PERFCOUNTER_CTRL__LS_EN_MASK                                                                       0x00000020L
#define SQ_PERFCOUNTER_CTRL__CS_EN_MASK                                                                       0x00000040L
#define SQ_PERFCOUNTER_CTRL__CNTR_RATE_MASK                                                                   0x00000300L
#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH_MASK                                                               0x00002000L
#define SQ_PERFCOUNTER_CTRL__DISABLE_ME0PIPE0_PERF_MASK                                                       0x00004000L
#define SQ_PERFCOUNTER_CTRL__DISABLE_ME0PIPE1_PERF_MASK                                                       0x00008000L
#define SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE0_PERF_MASK                                                       0x00010000L
#define SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE1_PERF_MASK                                                       0x00020000L
#define SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE2_PERF_MASK                                                       0x00040000L
#define SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE3_PERF_MASK                                                       0x00080000L
//SQ_PERFCOUNTER_CTRL2
#define SQ_PERFCOUNTER_CTRL2__FORCE_EN__SHIFT                                                                 0x0
#define SQ_PERFCOUNTER_CTRL2__FORCE_EN_MASK                                                                   0x00000001L
//GCEA_PERFCOUNTER2_SELECT
#define GCEA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                             0x0
#define GCEA_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT                                                            0xa
#define GCEA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                            0x14
#define GCEA_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT                                                           0x18
#define GCEA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                            0x1c
#define GCEA_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                               0x000003FFL
#define GCEA_PERFCOUNTER2_SELECT__PERF_SEL1_MASK                                                              0x000FFC00L
#define GCEA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                              0x00F00000L
#define GCEA_PERFCOUNTER2_SELECT__PERF_MODE1_MASK                                                             0x0F000000L
#define GCEA_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                              0xF0000000L
//GCEA_PERFCOUNTER2_SELECT1
#define GCEA_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT                                                           0x0
#define GCEA_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT                                                           0xa
#define GCEA_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT                                                          0x18
#define GCEA_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT                                                          0x1c
#define GCEA_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK                                                             0x000003FFL
#define GCEA_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK                                                             0x000FFC00L
#define GCEA_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK                                                            0x0F000000L
#define GCEA_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK                                                            0xF0000000L
//GCEA_PERFCOUNTER2_MODE
#define GCEA_PERFCOUNTER2_MODE__COMPARE_MODE0__SHIFT                                                          0x0
#define GCEA_PERFCOUNTER2_MODE__COMPARE_MODE1__SHIFT                                                          0x2
#define GCEA_PERFCOUNTER2_MODE__COMPARE_MODE2__SHIFT                                                          0x4
#define GCEA_PERFCOUNTER2_MODE__COMPARE_MODE3__SHIFT                                                          0x6
#define GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE0__SHIFT                                                         0x8
#define GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE1__SHIFT                                                         0xc
#define GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE2__SHIFT                                                         0x10
#define GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE3__SHIFT                                                         0x14
#define GCEA_PERFCOUNTER2_MODE__COMPARE_MODE0_MASK                                                            0x00000003L
#define GCEA_PERFCOUNTER2_MODE__COMPARE_MODE1_MASK                                                            0x0000000CL
#define GCEA_PERFCOUNTER2_MODE__COMPARE_MODE2_MASK                                                            0x00000030L
#define GCEA_PERFCOUNTER2_MODE__COMPARE_MODE3_MASK                                                            0x000000C0L
#define GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE0_MASK                                                           0x00000F00L
#define GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE1_MASK                                                           0x0000F000L
#define GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE2_MASK                                                           0x000F0000L
#define GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE3_MASK                                                           0x00F00000L
//GCEA_PERFCOUNTER0_CFG
#define GCEA_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                                0x0
#define GCEA_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                            0x8
#define GCEA_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                               0x18
#define GCEA_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                                  0x1c
#define GCEA_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                   0x1d
#define GCEA_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                                  0x000000FFL
#define GCEA_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                              0x0000FF00L
#define GCEA_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                                 0x0F000000L
#define GCEA_PERFCOUNTER0_CFG__ENABLE_MASK                                                                    0x10000000L
#define GCEA_PERFCOUNTER0_CFG__CLEAR_MASK                                                                     0x20000000L
//GCEA_PERFCOUNTER1_CFG
#define GCEA_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                                0x0
#define GCEA_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                            0x8
#define GCEA_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                               0x18
#define GCEA_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                                  0x1c
#define GCEA_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                   0x1d
#define GCEA_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                                  0x000000FFL
#define GCEA_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                              0x0000FF00L
#define GCEA_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                                 0x0F000000L
#define GCEA_PERFCOUNTER1_CFG__ENABLE_MASK                                                                    0x10000000L
#define GCEA_PERFCOUNTER1_CFG__CLEAR_MASK                                                                     0x20000000L
//GCEA_PERFCOUNTER_RSLT_CNTL
#define GCEA_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                                0x0
#define GCEA_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                      0x8
#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                       0x10
#define GCEA_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                         0x18
#define GCEA_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                          0x19
#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                               0x1a
#define GCEA_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                                  0x0000000FL
#define GCEA_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                        0x0000FF00L
#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                         0x00FF0000L
#define GCEA_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                           0x01000000L
#define GCEA_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                            0x02000000L
#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                                 0x04000000L
//SX_PERFCOUNTER0_SELECT
#define SX_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                               0x0
#define SX_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                              0xa
#define SX_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                              0x14
#define SX_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                             0x18
#define SX_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                              0x1c
#define SX_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                 0x000003FFL
#define SX_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                                0x000FFC00L
#define SX_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
#define SX_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                               0x0F000000L
#define SX_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                                0xF0000000L
//SX_PERFCOUNTER1_SELECT
#define SX_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                               0x0
#define SX_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT                                                              0xa
#define SX_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                              0x14
#define SX_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT                                                             0x18
#define SX_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                              0x1c
#define SX_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                 0x000003FFL
#define SX_PERFCOUNTER1_SELECT__PERF_SEL1_MASK                                                                0x000FFC00L
#define SX_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
#define SX_PERFCOUNTER1_SELECT__PERF_MODE1_MASK                                                               0x0F000000L
#define SX_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                                0xF0000000L
//SX_PERFCOUNTER2_SELECT
#define SX_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                               0x0
#define SX_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                              0x14
#define SX_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                              0x1c
#define SX_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                                 0x000003FFL
#define SX_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
#define SX_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                                0xF0000000L
//SX_PERFCOUNTER3_SELECT
#define SX_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                               0x0
#define SX_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT                                                              0x14
#define SX_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                              0x1c
#define SX_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                                 0x000003FFL
#define SX_PERFCOUNTER3_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
#define SX_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                                0xF0000000L
//SX_PERFCOUNTER0_SELECT1
#define SX_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                             0x0
#define SX_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                             0xa
#define SX_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                            0x18
#define SX_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                            0x1c
#define SX_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                               0x000003FFL
#define SX_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                               0x000FFC00L
#define SX_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                              0x0F000000L
#define SX_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                              0xF0000000L
//SX_PERFCOUNTER1_SELECT1
#define SX_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT                                                             0x0
#define SX_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT                                                             0xa
#define SX_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT                                                            0x18
#define SX_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT                                                            0x1c
#define SX_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK                                                               0x000003FFL
#define SX_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK                                                               0x000FFC00L
#define SX_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK                                                              0x0F000000L
#define SX_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK                                                              0xF0000000L
//GDS_PERFCOUNTER0_SELECT
#define GDS_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                              0x0
#define GDS_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                             0xa
#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                             0x14
#define GDS_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                            0x18
#define GDS_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                             0x1c
#define GDS_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                0x000003FFL
#define GDS_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
#define GDS_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
#define GDS_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                               0xF0000000L
//GDS_PERFCOUNTER1_SELECT
#define GDS_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                              0x0
#define GDS_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT                                                             0xa
#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                             0x14
#define GDS_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT                                                            0x18
#define GDS_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                             0x1c
#define GDS_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                0x000003FFL
#define GDS_PERFCOUNTER1_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
#define GDS_PERFCOUNTER1_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
#define GDS_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                               0xF0000000L
//GDS_PERFCOUNTER2_SELECT
#define GDS_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                              0x0
#define GDS_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT                                                             0xa
#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                             0x14
#define GDS_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT                                                            0x18
#define GDS_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                             0x1c
#define GDS_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                                0x000003FFL
#define GDS_PERFCOUNTER2_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
#define GDS_PERFCOUNTER2_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
#define GDS_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                               0xF0000000L
//GDS_PERFCOUNTER3_SELECT
#define GDS_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                              0x0
#define GDS_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT                                                             0xa
#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT                                                             0x14
#define GDS_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT                                                            0x18
#define GDS_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                             0x1c
#define GDS_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                                0x000003FFL
#define GDS_PERFCOUNTER3_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
#define GDS_PERFCOUNTER3_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
#define GDS_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                               0xF0000000L
//GDS_PERFCOUNTER0_SELECT1
#define GDS_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                            0x0
#define GDS_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                            0xa
#define GDS_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                           0x18
#define GDS_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                           0x1c
#define GDS_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
#define GDS_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
#define GDS_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                             0x0F000000L
#define GDS_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                             0xF0000000L
//GDS_PERFCOUNTER1_SELECT1
#define GDS_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT                                                            0x0
#define GDS_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT                                                            0xa
#define GDS_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT                                                           0x18
#define GDS_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT                                                           0x1c
#define GDS_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
#define GDS_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
#define GDS_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK                                                             0x0F000000L
#define GDS_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK                                                             0xF0000000L
//GDS_PERFCOUNTER2_SELECT1
#define GDS_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT                                                            0x0
#define GDS_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT                                                            0xa
#define GDS_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT                                                           0x18
#define GDS_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT                                                           0x1c
#define GDS_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
#define GDS_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
#define GDS_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK                                                             0x0F000000L
#define GDS_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK                                                             0xF0000000L
//GDS_PERFCOUNTER3_SELECT1
#define GDS_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT                                                            0x0
#define GDS_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT                                                            0xa
#define GDS_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT                                                           0x18
#define GDS_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT                                                           0x1c
#define GDS_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
#define GDS_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
#define GDS_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK                                                             0x0F000000L
#define GDS_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK                                                             0xF0000000L
//TA_PERFCOUNTER0_SELECT
#define TA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                               0x0
#define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                              0xa
#define TA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                              0x14
#define TA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                             0x18
#define TA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                              0x1c
#define TA_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                 0x000003FFL
#define TA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                                0x000FFC00L
#define TA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
#define TA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                               0x0F000000L
#define TA_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                                0xF0000000L
//TA_PERFCOUNTER0_SELECT1
#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                             0x0
#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                             0xa
#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                            0x18
#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                            0x1c
#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                               0x000003FFL
#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                               0x000FFC00L
#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                              0x0F000000L
#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                              0xF0000000L
//TA_PERFCOUNTER1_SELECT
#define TA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                               0x0
#define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                              0x14
#define TA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                              0x1c
#define TA_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                 0x000003FFL
#define TA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
#define TA_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                                0xF0000000L
//TD_PERFCOUNTER0_SELECT
#define TD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                               0x0
#define TD_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                              0xa
#define TD_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                              0x14
#define TD_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                             0x18
#define TD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                              0x1c
#define TD_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                 0x000003FFL
#define TD_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                                0x000FFC00L
#define TD_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
#define TD_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                               0x0F000000L
#define TD_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                                0xF0000000L
//TD_PERFCOUNTER0_SELECT1
#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                             0x0
#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                             0xa
#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                            0x18
#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                            0x1c
#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                               0x000003FFL
#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                               0x000FFC00L
#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                              0x0F000000L
#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                              0xF0000000L
//TD_PERFCOUNTER1_SELECT
#define TD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                               0x0
#define TD_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                              0x14
#define TD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                              0x1c
#define TD_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                 0x000003FFL
#define TD_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
#define TD_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                                0xF0000000L
//TCP_PERFCOUNTER0_SELECT
#define TCP_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                              0x0
#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                             0xa
#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                             0x14
#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                            0x18
#define TCP_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                             0x1c
#define TCP_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                0x000003FFL
#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
#define TCP_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                               0xF0000000L
//TCP_PERFCOUNTER0_SELECT1
#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                            0x0
#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                            0xa
#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                           0x18
#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                           0x1c
#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                             0x0F000000L
#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                             0xF0000000L
//TCP_PERFCOUNTER1_SELECT
#define TCP_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                              0x0
#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT                                                             0xa
#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                             0x14
#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT                                                            0x18
#define TCP_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                             0x1c
#define TCP_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                0x000003FFL
#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
#define TCP_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                               0xF0000000L
//TCP_PERFCOUNTER1_SELECT1
#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT                                                            0x0
#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT                                                            0xa
#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT                                                           0x18
#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT                                                           0x1c
#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK                                                             0x0F000000L
#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK                                                             0xF0000000L
//TCP_PERFCOUNTER2_SELECT
#define TCP_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                              0x0
#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                             0x14
#define TCP_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                             0x1c
#define TCP_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                                0x000003FFL
#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
#define TCP_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                               0xF0000000L
//TCP_PERFCOUNTER3_SELECT
#define TCP_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                              0x0
#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT                                                             0x14
#define TCP_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                             0x1c
#define TCP_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                                0x000003FFL
#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
#define TCP_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                               0xF0000000L
//GL2C_PERFCOUNTER0_SELECT
#define GL2C_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                             0x0
#define GL2C_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                            0xa
#define GL2C_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                            0x14
#define GL2C_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                           0x18
#define GL2C_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                            0x1c
#define GL2C_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                               0x000003FFL
#define GL2C_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                              0x000FFC00L
#define GL2C_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                              0x00F00000L
#define GL2C_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                             0x0F000000L
#define GL2C_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                              0xF0000000L
//GL2C_PERFCOUNTER0_SELECT1
#define GL2C_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                           0x0
#define GL2C_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                           0xa
#define GL2C_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                          0x18
#define GL2C_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                          0x1c
#define GL2C_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                             0x000003FFL
#define GL2C_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                             0x000FFC00L
#define GL2C_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                            0x0F000000L
#define GL2C_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                            0xF0000000L
//GL2C_PERFCOUNTER1_SELECT
#define GL2C_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                             0x0
#define GL2C_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT                                                            0xa
#define GL2C_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                            0x14
#define GL2C_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT                                                           0x18
#define GL2C_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                            0x1c
#define GL2C_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                               0x000003FFL
#define GL2C_PERFCOUNTER1_SELECT__PERF_SEL1_MASK                                                              0x000FFC00L
#define GL2C_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                              0x00F00000L
#define GL2C_PERFCOUNTER1_SELECT__PERF_MODE1_MASK                                                             0x0F000000L
#define GL2C_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                              0xF0000000L
//GL2C_PERFCOUNTER1_SELECT1
#define GL2C_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT                                                           0x0
#define GL2C_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT                                                           0xa
#define GL2C_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT                                                          0x18
#define GL2C_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT                                                          0x1c
#define GL2C_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK                                                             0x000003FFL
#define GL2C_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK                                                             0x000FFC00L
#define GL2C_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK                                                            0x0F000000L
#define GL2C_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK                                                            0xF0000000L
//GL2C_PERFCOUNTER2_SELECT
#define GL2C_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                             0x0
#define GL2C_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                            0x14
#define GL2C_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                            0x1c
#define GL2C_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                               0x000003FFL
#define GL2C_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                              0x00F00000L
#define GL2C_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                              0xF0000000L
//GL2C_PERFCOUNTER3_SELECT
#define GL2C_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                             0x0
#define GL2C_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT                                                            0x14
#define GL2C_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                            0x1c
#define GL2C_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                               0x000003FFL
#define GL2C_PERFCOUNTER3_SELECT__CNTR_MODE_MASK                                                              0x00F00000L
#define GL2C_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                              0xF0000000L
//GL2A_PERFCOUNTER0_SELECT
#define GL2A_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                             0x0
#define GL2A_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                            0xa
#define GL2A_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                            0x14
#define GL2A_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                           0x18
#define GL2A_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                            0x1c
#define GL2A_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                               0x000003FFL
#define GL2A_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                              0x000FFC00L
#define GL2A_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                              0x00F00000L
#define GL2A_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                             0x0F000000L
#define GL2A_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                              0xF0000000L
//GL2A_PERFCOUNTER0_SELECT1
#define GL2A_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                           0x0
#define GL2A_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                           0xa
#define GL2A_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                          0x18
#define GL2A_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                          0x1c
#define GL2A_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                             0x000003FFL
#define GL2A_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                             0x000FFC00L
#define GL2A_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                            0x0F000000L
#define GL2A_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                            0xF0000000L
//GL2A_PERFCOUNTER1_SELECT
#define GL2A_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                             0x0
#define GL2A_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT                                                            0xa
#define GL2A_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                            0x14
#define GL2A_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT                                                           0x18
#define GL2A_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                            0x1c
#define GL2A_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                               0x000003FFL
#define GL2A_PERFCOUNTER1_SELECT__PERF_SEL1_MASK                                                              0x000FFC00L
#define GL2A_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                              0x00F00000L
#define GL2A_PERFCOUNTER1_SELECT__PERF_MODE1_MASK                                                             0x0F000000L
#define GL2A_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                              0xF0000000L
//GL2A_PERFCOUNTER1_SELECT1
#define GL2A_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT                                                           0x0
#define GL2A_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT                                                           0xa
#define GL2A_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT                                                          0x18
#define GL2A_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT                                                          0x1c
#define GL2A_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK                                                             0x000003FFL
#define GL2A_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK                                                             0x000FFC00L
#define GL2A_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK                                                            0x0F000000L
#define GL2A_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK                                                            0xF0000000L
//GL2A_PERFCOUNTER2_SELECT
#define GL2A_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                             0x0
#define GL2A_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                            0x14
#define GL2A_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                            0x1c
#define GL2A_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                               0x000003FFL
#define GL2A_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                              0x00F00000L
#define GL2A_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                              0xF0000000L
//GL2A_PERFCOUNTER3_SELECT
#define GL2A_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                             0x0
#define GL2A_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT                                                            0x14
#define GL2A_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                            0x1c
#define GL2A_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                               0x000003FFL
#define GL2A_PERFCOUNTER3_SELECT__CNTR_MODE_MASK                                                              0x00F00000L
#define GL2A_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                              0xF0000000L
//GL1C_PERFCOUNTER0_SELECT
#define GL1C_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                             0x0
#define GL1C_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                            0xa
#define GL1C_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                            0x14
#define GL1C_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                           0x18
#define GL1C_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                            0x1c
#define GL1C_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                               0x000003FFL
#define GL1C_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                              0x000FFC00L
#define GL1C_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                              0x00F00000L
#define GL1C_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                             0x0F000000L
#define GL1C_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                              0xF0000000L
//GL1C_PERFCOUNTER0_SELECT1
#define GL1C_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                           0x0
#define GL1C_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                           0xa
#define GL1C_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                          0x18
#define GL1C_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                          0x1c
#define GL1C_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                             0x000003FFL
#define GL1C_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                             0x000FFC00L
#define GL1C_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                            0x0F000000L
#define GL1C_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                            0xF0000000L
//GL1C_PERFCOUNTER1_SELECT
#define GL1C_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                             0x0
#define GL1C_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                            0x14
#define GL1C_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                            0x1c
#define GL1C_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                               0x000003FFL
#define GL1C_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                              0x00F00000L
#define GL1C_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                              0xF0000000L
//GL1C_PERFCOUNTER2_SELECT
#define GL1C_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                             0x0
#define GL1C_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                            0x14
#define GL1C_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                            0x1c
#define GL1C_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                               0x000003FFL
#define GL1C_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                              0x00F00000L
#define GL1C_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                              0xF0000000L
//GL1C_PERFCOUNTER3_SELECT
#define GL1C_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                             0x0
#define GL1C_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT                                                            0x14
#define GL1C_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                            0x1c
#define GL1C_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                               0x000003FFL
#define GL1C_PERFCOUNTER3_SELECT__CNTR_MODE_MASK                                                              0x00F00000L
#define GL1C_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                              0xF0000000L
//CHC_PERFCOUNTER0_SELECT
#define CHC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                              0x0
#define CHC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                             0xa
#define CHC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                             0x14
#define CHC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                            0x18
#define CHC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                             0x1c
#define CHC_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                0x000003FFL
#define CHC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
#define CHC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
#define CHC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
#define CHC_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                               0xF0000000L
//CHC_PERFCOUNTER0_SELECT1
#define CHC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                            0x0
#define CHC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                            0xa
#define CHC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                           0x18
#define CHC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                           0x1c
#define CHC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
#define CHC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
#define CHC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                             0x0F000000L
#define CHC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                             0xF0000000L
//CHC_PERFCOUNTER1_SELECT
#define CHC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                              0x0
#define CHC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                             0x14
#define CHC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                             0x1c
#define CHC_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                0x000003FFL
#define CHC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
#define CHC_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                               0xF0000000L
//CHC_PERFCOUNTER2_SELECT
#define CHC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                              0x0
#define CHC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                             0x14
#define CHC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                             0x1c
#define CHC_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                                0x000003FFL
#define CHC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
#define CHC_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                               0xF0000000L
//CHC_PERFCOUNTER3_SELECT
#define CHC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                              0x0
#define CHC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT                                                             0x14
#define CHC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                             0x1c
#define CHC_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                                0x000003FFL
#define CHC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
#define CHC_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                               0xF0000000L
//CHCG_PERFCOUNTER0_SELECT
#define CHCG_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                             0x0
#define CHCG_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                            0xa
#define CHCG_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                            0x14
#define CHCG_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                           0x18
#define CHCG_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                            0x1c
#define CHCG_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                               0x000003FFL
#define CHCG_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                              0x000FFC00L
#define CHCG_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                              0x00F00000L
#define CHCG_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                             0x0F000000L
#define CHCG_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                              0xF0000000L
//CHCG_PERFCOUNTER0_SELECT1
#define CHCG_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                           0x0
#define CHCG_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                           0xa
#define CHCG_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                          0x18
#define CHCG_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                          0x1c
#define CHCG_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                             0x000003FFL
#define CHCG_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                             0x000FFC00L
#define CHCG_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                            0x0F000000L
#define CHCG_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                            0xF0000000L
//CHCG_PERFCOUNTER1_SELECT
#define CHCG_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                             0x0
#define CHCG_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                            0x14
#define CHCG_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                            0x1c
#define CHCG_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                               0x000003FFL
#define CHCG_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                              0x00F00000L
#define CHCG_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                              0xF0000000L
//CHCG_PERFCOUNTER2_SELECT
#define CHCG_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                             0x0
#define CHCG_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                            0x14
#define CHCG_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                            0x1c
#define CHCG_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                               0x000003FFL
#define CHCG_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                              0x00F00000L
#define CHCG_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                              0xF0000000L
//CHCG_PERFCOUNTER3_SELECT
#define CHCG_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                             0x0
#define CHCG_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT                                                            0x14
#define CHCG_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                            0x1c
#define CHCG_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                               0x000003FFL
#define CHCG_PERFCOUNTER3_SELECT__CNTR_MODE_MASK                                                              0x00F00000L
#define CHCG_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                              0xF0000000L
//CB_PERFCOUNTER_FILTER
#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE__SHIFT                                                        0x0
#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL__SHIFT                                                           0x1
#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE__SHIFT                                                    0x4
#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL__SHIFT                                                       0x5
#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE__SHIFT                                                     0xa
#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL__SHIFT                                                        0xb
#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE__SHIFT                                                       0xc
#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL__SHIFT                                                          0xd
#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE__SHIFT                                               0x11
#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL__SHIFT                                                  0x12
#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE__SHIFT                                             0x15
#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL__SHIFT                                                0x16
#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE_MASK                                                          0x00000001L
#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL_MASK                                                             0x0000000EL
#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE_MASK                                                      0x00000010L
#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL_MASK                                                         0x000003E0L
#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE_MASK                                                       0x00000400L
#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL_MASK                                                          0x00000800L
#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE_MASK                                                         0x00001000L
#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL_MASK                                                            0x0000E000L
#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE_MASK                                                 0x00020000L
#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL_MASK                                                    0x001C0000L
#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE_MASK                                               0x00200000L
#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL_MASK                                                  0x00C00000L
//CB_PERFCOUNTER0_SELECT
#define CB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                               0x0
#define CB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                              0xa
#define CB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                              0x14
#define CB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                             0x18
#define CB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                              0x1c
#define CB_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
#define CB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                                0x0007FC00L
#define CB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
#define CB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                               0x0F000000L
#define CB_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                                0xF0000000L
//CB_PERFCOUNTER0_SELECT1
#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                             0x0
#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                             0xa
#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                            0x18
#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                            0x1c
#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                               0x000001FFL
#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                               0x0007FC00L
#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                              0x0F000000L
#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                              0xF0000000L
//CB_PERFCOUNTER1_SELECT
#define CB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                               0x0
#define CB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                              0x1c
#define CB_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
#define CB_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                                0xF0000000L
//CB_PERFCOUNTER2_SELECT
#define CB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                               0x0
#define CB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                              0x1c
#define CB_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
#define CB_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                                0xF0000000L
//CB_PERFCOUNTER3_SELECT
#define CB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                               0x0
#define CB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                              0x1c
#define CB_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
#define CB_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                                0xF0000000L
//DB_PERFCOUNTER0_SELECT
#define DB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                               0x0
#define DB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                              0xa
#define DB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                              0x14
#define DB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                             0x18
#define DB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                              0x1c
#define DB_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                 0x000003FFL
#define DB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                                0x000FFC00L
#define DB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
#define DB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                               0x0F000000L
#define DB_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                                0xF0000000L
//DB_PERFCOUNTER0_SELECT1
#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                             0x0
#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                             0xa
#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                            0x18
#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                            0x1c
#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                               0x000003FFL
#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                               0x000FFC00L
#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                              0x0F000000L
#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                              0xF0000000L
//DB_PERFCOUNTER1_SELECT
#define DB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                               0x0
#define DB_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT                                                              0xa
#define DB_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                              0x14
#define DB_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT                                                             0x18
#define DB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                              0x1c
#define DB_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                 0x000003FFL
#define DB_PERFCOUNTER1_SELECT__PERF_SEL1_MASK                                                                0x000FFC00L
#define DB_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
#define DB_PERFCOUNTER1_SELECT__PERF_MODE1_MASK                                                               0x0F000000L
#define DB_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                                0xF0000000L
//DB_PERFCOUNTER1_SELECT1
#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT                                                             0x0
#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT                                                             0xa
#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT                                                            0x18
#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT                                                            0x1c
#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK                                                               0x000003FFL
#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK                                                               0x000FFC00L
#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK                                                              0x0F000000L
#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK                                                              0xF0000000L
//DB_PERFCOUNTER2_SELECT
#define DB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                               0x0
#define DB_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT                                                              0xa
#define DB_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                              0x14
#define DB_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT                                                             0x18
#define DB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                              0x1c
#define DB_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                                 0x000003FFL
#define DB_PERFCOUNTER2_SELECT__PERF_SEL1_MASK                                                                0x000FFC00L
#define DB_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
#define DB_PERFCOUNTER2_SELECT__PERF_MODE1_MASK                                                               0x0F000000L
#define DB_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                                0xF0000000L
//DB_PERFCOUNTER3_SELECT
#define DB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                               0x0
#define DB_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT                                                              0xa
#define DB_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT                                                              0x14
#define DB_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT                                                             0x18
#define DB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                              0x1c
#define DB_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                                 0x000003FFL
#define DB_PERFCOUNTER3_SELECT__PERF_SEL1_MASK                                                                0x000FFC00L
#define DB_PERFCOUNTER3_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
#define DB_PERFCOUNTER3_SELECT__PERF_MODE1_MASK                                                               0x0F000000L
#define DB_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                                0xF0000000L
//RLC_SPM_PERFMON_CNTL
#define RLC_SPM_PERFMON_CNTL__RESERVED1__SHIFT                                                                0x0
#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE__SHIFT                                                        0xc
#define RLC_SPM_PERFMON_CNTL__RESERVED__SHIFT                                                                 0xe
#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL__SHIFT                                                  0x10
#define RLC_SPM_PERFMON_CNTL__RESERVED1_MASK                                                                  0x00000FFFL
#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK                                                          0x00003000L
#define RLC_SPM_PERFMON_CNTL__RESERVED_MASK                                                                   0x0000C000L
#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL_MASK                                                    0xFFFF0000L
//RLC_SPM_PERFMON_RING_BASE_LO
#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO__SHIFT                                                     0x0
#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO_MASK                                                       0xFFFFFFFFL
//RLC_SPM_PERFMON_RING_BASE_HI
#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI__SHIFT                                                     0x0
#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED__SHIFT                                                         0x10
#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI_MASK                                                       0x0000FFFFL
#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED_MASK                                                           0xFFFF0000L
//RLC_SPM_PERFMON_RING_SIZE
#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE__SHIFT                                                      0x0
#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE_MASK                                                        0xFFFFFFFFL
//RLC_SPM_PERFMON_SEGMENT_SIZE
#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE__SHIFT                                             0x0
#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1__SHIFT                                                        0x8
#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE__SHIFT                                                  0xb
#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE__SHIFT                                                     0x10
#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE__SHIFT                                                     0x15
#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE__SHIFT                                                     0x1a
#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED__SHIFT                                                         0x1f
#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE_MASK                                               0x000000FFL
#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1_MASK                                                          0x00000700L
#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE_MASK                                                    0x0000F800L
#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE_MASK                                                       0x001F0000L
#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE_MASK                                                       0x03E00000L
#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE_MASK                                                       0x7C000000L
#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED_MASK                                                           0x80000000L
//RLC_SPM_RING_RDPTR
#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR__SHIFT                                                         0x0
#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR_MASK                                                           0xFFFFFFFFL
//RLC_SPM_SEGMENT_THRESHOLD
#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD__SHIFT                                               0x0
#define RLC_SPM_SEGMENT_THRESHOLD__RESERVED__SHIFT                                                            0x8
#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD_MASK                                                 0x000000FFL
#define RLC_SPM_SEGMENT_THRESHOLD__RESERVED_MASK                                                              0xFFFFFF00L
//RLC_SPM_SE_MUXSEL_ADDR
#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT                                                       0x0
#define RLC_SPM_SE_MUXSEL_ADDR__RESERVED__SHIFT                                                               0x9
#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK                                                         0x000001FFL
#define RLC_SPM_SE_MUXSEL_ADDR__RESERVED_MASK                                                                 0xFFFFFE00L
//RLC_SPM_SE_MUXSEL_DATA
#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT                                                       0x0
#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA_MASK                                                         0xFFFFFFFFL
//RLC_SPM_GLOBAL_MUXSEL_ADDR
#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT                                                   0x0
#define RLC_SPM_GLOBAL_MUXSEL_ADDR__RESERVED__SHIFT                                                           0x8
#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK                                                     0x000000FFL
#define RLC_SPM_GLOBAL_MUXSEL_ADDR__RESERVED_MASK                                                             0xFFFFFF00L
//RLC_SPM_GLOBAL_MUXSEL_DATA
#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT                                                   0x0
#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA_MASK                                                     0xFFFFFFFFL
//RLC_SPM_DESER_START_SKEW
#define RLC_SPM_DESER_START_SKEW__DESER_START_SKEW__SHIFT                                                     0x0
#define RLC_SPM_DESER_START_SKEW__RESERVED__SHIFT                                                             0x7
#define RLC_SPM_DESER_START_SKEW__DESER_START_SKEW_MASK                                                       0x0000007FL
#define RLC_SPM_DESER_START_SKEW__RESERVED_MASK                                                               0xFFFFFF80L
//RLC_SPM_GLOBALS_SAMPLE_SKEW
#define RLC_SPM_GLOBALS_SAMPLE_SKEW__GLOBALS_SAMPLE_SKEW__SHIFT                                               0x0
#define RLC_SPM_GLOBALS_SAMPLE_SKEW__RESERVED__SHIFT                                                          0x7
#define RLC_SPM_GLOBALS_SAMPLE_SKEW__GLOBALS_SAMPLE_SKEW_MASK                                                 0x0000007FL
#define RLC_SPM_GLOBALS_SAMPLE_SKEW__RESERVED_MASK                                                            0xFFFFFF80L
//RLC_SPM_GLOBALS_MUXSEL_SKEW
#define RLC_SPM_GLOBALS_MUXSEL_SKEW__GLOBALS_MUXSEL_SKEW__SHIFT                                               0x0
#define RLC_SPM_GLOBALS_MUXSEL_SKEW__RESERVED__SHIFT                                                          0x7
#define RLC_SPM_GLOBALS_MUXSEL_SKEW__GLOBALS_MUXSEL_SKEW_MASK                                                 0x0000007FL
#define RLC_SPM_GLOBALS_MUXSEL_SKEW__RESERVED_MASK                                                            0xFFFFFF80L
//RLC_SPM_SE_SAMPLE_SKEW
#define RLC_SPM_SE_SAMPLE_SKEW__SE_SAMPLE_SKEW__SHIFT                                                         0x0
#define RLC_SPM_SE_SAMPLE_SKEW__RESERVED__SHIFT                                                               0x7
#define RLC_SPM_SE_SAMPLE_SKEW__SE_SAMPLE_SKEW_MASK                                                           0x0000007FL
#define RLC_SPM_SE_SAMPLE_SKEW__RESERVED_MASK                                                                 0xFFFFFF80L
//RLC_SPM_SE_MUXSEL_SKEW
#define RLC_SPM_SE_MUXSEL_SKEW__SE_MUXSEL_SKEW__SHIFT                                                         0x0
#define RLC_SPM_SE_MUXSEL_SKEW__RESERVED__SHIFT                                                               0x7
#define RLC_SPM_SE_MUXSEL_SKEW__SE_MUXSEL_SKEW_MASK                                                           0x0000007FL
#define RLC_SPM_SE_MUXSEL_SKEW__RESERVED_MASK                                                                 0xFFFFFF80L
//RLC_SPM_GLB_SAMPLEDELAY_IND_ADDR
#define RLC_SPM_GLB_SAMPLEDELAY_IND_ADDR__GLB_SAMPLEDELAY_INDEX__SHIFT                                        0x0
#define RLC_SPM_GLB_SAMPLEDELAY_IND_ADDR__GLB_SAMPLEDELAY_INDEX_MASK                                          0xFFFFFFFFL
//RLC_SPM_GLB_SAMPLEDELAY_IND_DATA
#define RLC_SPM_GLB_SAMPLEDELAY_IND_DATA__data__SHIFT                                                         0x0
#define RLC_SPM_GLB_SAMPLEDELAY_IND_DATA__RESERVED__SHIFT                                                     0x7
#define RLC_SPM_GLB_SAMPLEDELAY_IND_DATA__data_MASK                                                           0x0000007FL
#define RLC_SPM_GLB_SAMPLEDELAY_IND_DATA__RESERVED_MASK                                                       0xFFFFFF80L
//RLC_SPM_SE_SAMPLEDELAY_IND_ADDR
#define RLC_SPM_SE_SAMPLEDELAY_IND_ADDR__SE_SAMPLEDELAY_INDEX__SHIFT                                          0x0
#define RLC_SPM_SE_SAMPLEDELAY_IND_ADDR__SE_SAMPLEDELAY_INDEX_MASK                                            0xFFFFFFFFL
//RLC_SPM_SE_SAMPLEDELAY_IND_DATA
#define RLC_SPM_SE_SAMPLEDELAY_IND_DATA__data__SHIFT                                                          0x0
#define RLC_SPM_SE_SAMPLEDELAY_IND_DATA__RESERVED__SHIFT                                                      0x7
#define RLC_SPM_SE_SAMPLEDELAY_IND_DATA__data_MASK                                                            0x0000007FL
#define RLC_SPM_SE_SAMPLEDELAY_IND_DATA__RESERVED_MASK                                                        0xFFFFFF80L
//RLC_SPM_RING_WRPTR
#define RLC_SPM_RING_WRPTR__RESERVED__SHIFT                                                                   0x0
#define RLC_SPM_RING_WRPTR__PERFMON_RING_WRPTR__SHIFT                                                         0x5
#define RLC_SPM_RING_WRPTR__RESERVED_MASK                                                                     0x0000001FL
#define RLC_SPM_RING_WRPTR__PERFMON_RING_WRPTR_MASK                                                           0xFFFFFFE0L
//RLC_SPM_ACCUM_DATARAM_ADDR
#define RLC_SPM_ACCUM_DATARAM_ADDR__addr__SHIFT                                                               0x0
#define RLC_SPM_ACCUM_DATARAM_ADDR__RESERVED__SHIFT                                                           0x7
#define RLC_SPM_ACCUM_DATARAM_ADDR__addr_MASK                                                                 0x0000007FL
#define RLC_SPM_ACCUM_DATARAM_ADDR__RESERVED_MASK                                                             0xFFFFFF80L
//RLC_SPM_ACCUM_DATARAM_DATA
#define RLC_SPM_ACCUM_DATARAM_DATA__data__SHIFT                                                               0x0
#define RLC_SPM_ACCUM_DATARAM_DATA__data_MASK                                                                 0xFFFFFFFFL
//RLC_SPM_ACCUM_CTRLRAM_ADDR
#define RLC_SPM_ACCUM_CTRLRAM_ADDR__addr__SHIFT                                                               0x0
#define RLC_SPM_ACCUM_CTRLRAM_ADDR__RESERVED__SHIFT                                                           0xb
#define RLC_SPM_ACCUM_CTRLRAM_ADDR__addr_MASK                                                                 0x000007FFL
#define RLC_SPM_ACCUM_CTRLRAM_ADDR__RESERVED_MASK                                                             0xFFFFF800L
//RLC_SPM_ACCUM_CTRLRAM_DATA
#define RLC_SPM_ACCUM_CTRLRAM_DATA__data__SHIFT                                                               0x0
#define RLC_SPM_ACCUM_CTRLRAM_DATA__RESERVED__SHIFT                                                           0x8
#define RLC_SPM_ACCUM_CTRLRAM_DATA__data_MASK                                                                 0x000000FFL
#define RLC_SPM_ACCUM_CTRLRAM_DATA__RESERVED_MASK                                                             0xFFFFFF00L
//RLC_SPM_ACCUM_STATUS
#define RLC_SPM_ACCUM_STATUS__NumbSamplesCompleted__SHIFT                                                     0x0
#define RLC_SPM_ACCUM_STATUS__AccumDone__SHIFT                                                                0x8
#define RLC_SPM_ACCUM_STATUS__SpmDone__SHIFT                                                                  0x9
#define RLC_SPM_ACCUM_STATUS__AccumOverflow__SHIFT                                                            0xa
#define RLC_SPM_ACCUM_STATUS__AccumArmed__SHIFT                                                               0xb
#define RLC_SPM_ACCUM_STATUS__SequenceInProgress__SHIFT                                                       0xc
#define RLC_SPM_ACCUM_STATUS__FinalSequenceInProgress__SHIFT                                                  0xd
#define RLC_SPM_ACCUM_STATUS__AllFifosEmpty__SHIFT                                                            0xe
#define RLC_SPM_ACCUM_STATUS__FSMIsIdle__SHIFT                                                                0xf
#define RLC_SPM_ACCUM_STATUS__SwaAccumDone__SHIFT                                                             0x10
#define RLC_SPM_ACCUM_STATUS__SwaSpmDone__SHIFT                                                               0x11
#define RLC_SPM_ACCUM_STATUS__SwaAccumOverflow__SHIFT                                                         0x12
#define RLC_SPM_ACCUM_STATUS__SwaAccumArmed__SHIFT                                                            0x13
#define RLC_SPM_ACCUM_STATUS__AllSegsDone__SHIFT                                                              0x14
#define RLC_SPM_ACCUM_STATUS__RearmSwaPending__SHIFT                                                          0x15
#define RLC_SPM_ACCUM_STATUS__RearmSppPending__SHIFT                                                          0x16
#define RLC_SPM_ACCUM_STATUS__RESERVED__SHIFT                                                                 0x17
#define RLC_SPM_ACCUM_STATUS__NumbSamplesCompleted_MASK                                                       0x000000FFL
#define RLC_SPM_ACCUM_STATUS__AccumDone_MASK                                                                  0x00000100L
#define RLC_SPM_ACCUM_STATUS__SpmDone_MASK                                                                    0x00000200L
#define RLC_SPM_ACCUM_STATUS__AccumOverflow_MASK                                                              0x00000400L
#define RLC_SPM_ACCUM_STATUS__AccumArmed_MASK                                                                 0x00000800L
#define RLC_SPM_ACCUM_STATUS__SequenceInProgress_MASK                                                         0x00001000L
#define RLC_SPM_ACCUM_STATUS__FinalSequenceInProgress_MASK                                                    0x00002000L
#define RLC_SPM_ACCUM_STATUS__AllFifosEmpty_MASK                                                              0x00004000L
#define RLC_SPM_ACCUM_STATUS__FSMIsIdle_MASK                                                                  0x00008000L
#define RLC_SPM_ACCUM_STATUS__SwaAccumDone_MASK                                                               0x00010000L
#define RLC_SPM_ACCUM_STATUS__SwaSpmDone_MASK                                                                 0x00020000L
#define RLC_SPM_ACCUM_STATUS__SwaAccumOverflow_MASK                                                           0x00040000L
#define RLC_SPM_ACCUM_STATUS__SwaAccumArmed_MASK                                                              0x00080000L
#define RLC_SPM_ACCUM_STATUS__AllSegsDone_MASK                                                                0x00100000L
#define RLC_SPM_ACCUM_STATUS__RearmSwaPending_MASK                                                            0x00200000L
#define RLC_SPM_ACCUM_STATUS__RearmSppPending_MASK                                                            0x00400000L
#define RLC_SPM_ACCUM_STATUS__RESERVED_MASK                                                                   0xFF800000L
//RLC_SPM_ACCUM_CTRL
#define RLC_SPM_ACCUM_CTRL__StrobeResetPerfMonitors__SHIFT                                                    0x0
#define RLC_SPM_ACCUM_CTRL__StrobeStartAccumulation__SHIFT                                                    0x1
#define RLC_SPM_ACCUM_CTRL__StrobeRearmAccum__SHIFT                                                           0x2
#define RLC_SPM_ACCUM_CTRL__StrobeResetSpmBlock__SHIFT                                                        0x3
#define RLC_SPM_ACCUM_CTRL__StrobeStartSpm__SHIFT                                                             0x4
#define RLC_SPM_ACCUM_CTRL__StrobeRearmSwaAccum__SHIFT                                                        0x8
#define RLC_SPM_ACCUM_CTRL__StrobeStartSwa__SHIFT                                                             0x9
#define RLC_SPM_ACCUM_CTRL__StrobePerfmonSampleWires__SHIFT                                                   0xa
#define RLC_SPM_ACCUM_CTRL__RESERVED__SHIFT                                                                   0xb
#define RLC_SPM_ACCUM_CTRL__StrobeResetPerfMonitors_MASK                                                      0x00000001L
#define RLC_SPM_ACCUM_CTRL__StrobeStartAccumulation_MASK                                                      0x00000002L
#define RLC_SPM_ACCUM_CTRL__StrobeRearmAccum_MASK                                                             0x00000004L
#define RLC_SPM_ACCUM_CTRL__StrobeResetSpmBlock_MASK                                                          0x00000008L
#define RLC_SPM_ACCUM_CTRL__StrobeStartSpm_MASK                                                               0x000000F0L
#define RLC_SPM_ACCUM_CTRL__StrobeRearmSwaAccum_MASK                                                          0x00000100L
#define RLC_SPM_ACCUM_CTRL__StrobeStartSwa_MASK                                                               0x00000200L
#define RLC_SPM_ACCUM_CTRL__StrobePerfmonSampleWires_MASK                                                     0x00000400L
#define RLC_SPM_ACCUM_CTRL__RESERVED_MASK                                                                     0xFFFFF800L
//RLC_SPM_ACCUM_MODE
#define RLC_SPM_ACCUM_MODE__EnableAccum__SHIFT                                                                0x0
#define RLC_SPM_ACCUM_MODE__EnableSpmWithAccumMode__SHIFT                                                     0x1
#define RLC_SPM_ACCUM_MODE__EnableSPPMode__SHIFT                                                              0x2
#define RLC_SPM_ACCUM_MODE__AutoResetPerfmonDisable__SHIFT                                                    0x3
#define RLC_SPM_ACCUM_MODE__SwaAutoResetPerfmonDisable__SHIFT                                                 0x4
#define RLC_SPM_ACCUM_MODE__AutoAccumEn__SHIFT                                                                0x5
#define RLC_SPM_ACCUM_MODE__SwaAutoAccumEn__SHIFT                                                             0x6
#define RLC_SPM_ACCUM_MODE__AutoSpmEn__SHIFT                                                                  0x7
#define RLC_SPM_ACCUM_MODE__SwaAutoSpmEn__SHIFT                                                               0x8
#define RLC_SPM_ACCUM_MODE__Globals_LoadOverride__SHIFT                                                       0x9
#define RLC_SPM_ACCUM_MODE__Globals_SwaLoadOverride__SHIFT                                                    0xa
#define RLC_SPM_ACCUM_MODE__SE0_LoadOverride__SHIFT                                                           0xb
#define RLC_SPM_ACCUM_MODE__SE0_SwaLoadOverride__SHIFT                                                        0xc
#define RLC_SPM_ACCUM_MODE__SE1_LoadOverride__SHIFT                                                           0xd
#define RLC_SPM_ACCUM_MODE__SE1_SwaLoadOverride__SHIFT                                                        0xe
#define RLC_SPM_ACCUM_MODE__SE2_LoadOverride__SHIFT                                                           0xf
#define RLC_SPM_ACCUM_MODE__SE2_SwaLoadOverride__SHIFT                                                        0x10
#define RLC_SPM_ACCUM_MODE__SE3_LoadOverride__SHIFT                                                           0x11
#define RLC_SPM_ACCUM_MODE__SE3_SwaLoadOverride__SHIFT                                                        0x12
#define RLC_SPM_ACCUM_MODE__EnableAccum_MASK                                                                  0x00000001L
#define RLC_SPM_ACCUM_MODE__EnableSpmWithAccumMode_MASK                                                       0x00000002L
#define RLC_SPM_ACCUM_MODE__EnableSPPMode_MASK                                                                0x00000004L
#define RLC_SPM_ACCUM_MODE__AutoResetPerfmonDisable_MASK                                                      0x00000008L
#define RLC_SPM_ACCUM_MODE__SwaAutoResetPerfmonDisable_MASK                                                   0x00000010L
#define RLC_SPM_ACCUM_MODE__AutoAccumEn_MASK                                                                  0x00000020L
#define RLC_SPM_ACCUM_MODE__SwaAutoAccumEn_MASK                                                               0x00000040L
#define RLC_SPM_ACCUM_MODE__AutoSpmEn_MASK                                                                    0x00000080L
#define RLC_SPM_ACCUM_MODE__SwaAutoSpmEn_MASK                                                                 0x00000100L
#define RLC_SPM_ACCUM_MODE__Globals_LoadOverride_MASK                                                         0x00000200L
#define RLC_SPM_ACCUM_MODE__Globals_SwaLoadOverride_MASK                                                      0x00000400L
#define RLC_SPM_ACCUM_MODE__SE0_LoadOverride_MASK                                                             0x00000800L
#define RLC_SPM_ACCUM_MODE__SE0_SwaLoadOverride_MASK                                                          0x00001000L
#define RLC_SPM_ACCUM_MODE__SE1_LoadOverride_MASK                                                             0x00002000L
#define RLC_SPM_ACCUM_MODE__SE1_SwaLoadOverride_MASK                                                          0x00004000L
#define RLC_SPM_ACCUM_MODE__SE2_LoadOverride_MASK                                                             0x00008000L
#define RLC_SPM_ACCUM_MODE__SE2_SwaLoadOverride_MASK                                                          0x00010000L
#define RLC_SPM_ACCUM_MODE__SE3_LoadOverride_MASK                                                             0x00020000L
#define RLC_SPM_ACCUM_MODE__SE3_SwaLoadOverride_MASK                                                          0x00040000L
//RLC_SPM_ACCUM_THRESHOLD
#define RLC_SPM_ACCUM_THRESHOLD__Threshold__SHIFT                                                             0x0
#define RLC_SPM_ACCUM_THRESHOLD__Threshold_MASK                                                               0x0000FFFFL
//RLC_SPM_ACCUM_SAMPLES_REQUESTED
#define RLC_SPM_ACCUM_SAMPLES_REQUESTED__SamplesRequested__SHIFT                                              0x0
#define RLC_SPM_ACCUM_SAMPLES_REQUESTED__SamplesRequested_MASK                                                0x000000FFL
//RLC_SPM_ACCUM_DATARAM_WRCOUNT
#define RLC_SPM_ACCUM_DATARAM_WRCOUNT__DataRamWrCount__SHIFT                                                  0x0
#define RLC_SPM_ACCUM_DATARAM_WRCOUNT__RESERVED__SHIFT                                                        0x13
#define RLC_SPM_ACCUM_DATARAM_WRCOUNT__DataRamWrCount_MASK                                                    0x0007FFFFL
#define RLC_SPM_ACCUM_DATARAM_WRCOUNT__RESERVED_MASK                                                          0xFFF80000L
//RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE
#define RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE__SE0_NUM_LINE__SHIFT                                              0x0
#define RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE__SE1_NUM_LINE__SHIFT                                              0x8
#define RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE__SE2_NUM_LINE__SHIFT                                              0x10
#define RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE__SE3_NUM_LINE__SHIFT                                              0x18
#define RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE__SE0_NUM_LINE_MASK                                                0x000000FFL
#define RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE__SE1_NUM_LINE_MASK                                                0x0000FF00L
#define RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE__SE2_NUM_LINE_MASK                                                0x00FF0000L
#define RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE__SE3_NUM_LINE_MASK                                                0xFF000000L
//RLC_SPM_PERFMON_GLB_SEGMENT_SIZE
#define RLC_SPM_PERFMON_GLB_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE__SHIFT                                         0x0
#define RLC_SPM_PERFMON_GLB_SEGMENT_SIZE__GLOBAL_NUM_LINE__SHIFT                                              0x8
#define RLC_SPM_PERFMON_GLB_SEGMENT_SIZE__RESERVED__SHIFT                                                     0x10
#define RLC_SPM_PERFMON_GLB_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE_MASK                                           0x000000FFL
#define RLC_SPM_PERFMON_GLB_SEGMENT_SIZE__GLOBAL_NUM_LINE_MASK                                                0x0000FF00L
#define RLC_SPM_PERFMON_GLB_SEGMENT_SIZE__RESERVED_MASK                                                       0xFFFF0000L
//RLC_SPM_VIRT_CTRL
#define RLC_SPM_VIRT_CTRL__PauseSpmSamplingRequest__SHIFT                                                     0x0
#define RLC_SPM_VIRT_CTRL__PauseSpmSamplingRequest_MASK                                                       0x00000001L
//RLC_SPM_PERFMON_SWA_SEGMENT_SIZE
#define RLC_SPM_PERFMON_SWA_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE__SHIFT                                         0x0
#define RLC_SPM_PERFMON_SWA_SEGMENT_SIZE__RESERVED1__SHIFT                                                    0x8
#define RLC_SPM_PERFMON_SWA_SEGMENT_SIZE__GLOBAL_NUM_LINE__SHIFT                                              0xb
#define RLC_SPM_PERFMON_SWA_SEGMENT_SIZE__SE0_NUM_LINE__SHIFT                                                 0x10
#define RLC_SPM_PERFMON_SWA_SEGMENT_SIZE__SE1_NUM_LINE__SHIFT                                                 0x15
#define RLC_SPM_PERFMON_SWA_SEGMENT_SIZE__SE2_NUM_LINE__SHIFT                                                 0x1a
#define RLC_SPM_PERFMON_SWA_SEGMENT_SIZE__RESERVED__SHIFT                                                     0x1f
#define RLC_SPM_PERFMON_SWA_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE_MASK                                           0x000000FFL
#define RLC_SPM_PERFMON_SWA_SEGMENT_SIZE__RESERVED1_MASK                                                      0x00000700L
#define RLC_SPM_PERFMON_SWA_SEGMENT_SIZE__GLOBAL_NUM_LINE_MASK                                                0x0000F800L
#define RLC_SPM_PERFMON_SWA_SEGMENT_SIZE__SE0_NUM_LINE_MASK                                                   0x001F0000L
#define RLC_SPM_PERFMON_SWA_SEGMENT_SIZE__SE1_NUM_LINE_MASK                                                   0x03E00000L
#define RLC_SPM_PERFMON_SWA_SEGMENT_SIZE__SE2_NUM_LINE_MASK                                                   0x7C000000L
#define RLC_SPM_PERFMON_SWA_SEGMENT_SIZE__RESERVED_MASK                                                       0x80000000L
//RLC_SPM_VIRT_STATUS
#define RLC_SPM_VIRT_STATUS__SpmSamplingPaused__SHIFT                                                         0x0
#define RLC_SPM_VIRT_STATUS__SpmSamplingPaused_MASK                                                           0x00000001L
//RLC_SPM_GFXCLOCK_HIGHCOUNT
#define RLC_SPM_GFXCLOCK_HIGHCOUNT__GFXCLOCK_HIGHCOUNT__SHIFT                                                 0x0
#define RLC_SPM_GFXCLOCK_HIGHCOUNT__GFXCLOCK_HIGHCOUNT_MASK                                                   0xFFFFFFFFL
//RLC_SPM_GFXCLOCK_LOWCOUNT
#define RLC_SPM_GFXCLOCK_LOWCOUNT__GFXCLOCK_LOWCOUNT__SHIFT                                                   0x0
#define RLC_SPM_GFXCLOCK_LOWCOUNT__GFXCLOCK_LOWCOUNT_MASK                                                     0xFFFFFFFFL
//RLC_SPM_PERFMON_SWA_SE3TO0_SEGMENT_SIZE
#define RLC_SPM_PERFMON_SWA_SE3TO0_SEGMENT_SIZE__SE0_NUM_LINE__SHIFT                                          0x0
#define RLC_SPM_PERFMON_SWA_SE3TO0_SEGMENT_SIZE__SE1_NUM_LINE__SHIFT                                          0x8
#define RLC_SPM_PERFMON_SWA_SE3TO0_SEGMENT_SIZE__SE2_NUM_LINE__SHIFT                                          0x10
#define RLC_SPM_PERFMON_SWA_SE3TO0_SEGMENT_SIZE__SE3_NUM_LINE__SHIFT                                          0x18
#define RLC_SPM_PERFMON_SWA_SE3TO0_SEGMENT_SIZE__SE0_NUM_LINE_MASK                                            0x000000FFL
#define RLC_SPM_PERFMON_SWA_SE3TO0_SEGMENT_SIZE__SE1_NUM_LINE_MASK                                            0x0000FF00L
#define RLC_SPM_PERFMON_SWA_SE3TO0_SEGMENT_SIZE__SE2_NUM_LINE_MASK                                            0x00FF0000L
#define RLC_SPM_PERFMON_SWA_SE3TO0_SEGMENT_SIZE__SE3_NUM_LINE_MASK                                            0xFF000000L
//RLC_SPM_GLOBAL_MUXSEL_ADDR_OFFSET
#define RLC_SPM_GLOBAL_MUXSEL_ADDR_OFFSET__OFFSET__SHIFT                                                      0x0
#define RLC_SPM_GLOBAL_MUXSEL_ADDR_OFFSET__RESERVED__SHIFT                                                    0x10
#define RLC_SPM_GLOBAL_MUXSEL_ADDR_OFFSET__OFFSET_MASK                                                        0x0000FFFFL
#define RLC_SPM_GLOBAL_MUXSEL_ADDR_OFFSET__RESERVED_MASK                                                      0xFFFF0000L
//RLC_SPM_SE_MUXSEL_ADDR_OFFSET
#define RLC_SPM_SE_MUXSEL_ADDR_OFFSET__OFFSET__SHIFT                                                          0x0
#define RLC_SPM_SE_MUXSEL_ADDR_OFFSET__RESERVED__SHIFT                                                        0x10
#define RLC_SPM_SE_MUXSEL_ADDR_OFFSET__OFFSET_MASK                                                            0x0000FFFFL
#define RLC_SPM_SE_MUXSEL_ADDR_OFFSET__RESERVED_MASK                                                          0xFFFF0000L
//RLC_SPM_ACCUM_SWA_DATARAM_ADDR
#define RLC_SPM_ACCUM_SWA_DATARAM_ADDR__addr__SHIFT                                                           0x0
#define RLC_SPM_ACCUM_SWA_DATARAM_ADDR__RESERVED__SHIFT                                                       0x7
#define RLC_SPM_ACCUM_SWA_DATARAM_ADDR__addr_MASK                                                             0x0000007FL
#define RLC_SPM_ACCUM_SWA_DATARAM_ADDR__RESERVED_MASK                                                         0xFFFFFF80L
//RLC_SPM_ACCUM_SWA_DATARAM_DATA
#define RLC_SPM_ACCUM_SWA_DATARAM_DATA__data__SHIFT                                                           0x0
#define RLC_SPM_ACCUM_SWA_DATARAM_DATA__data_MASK                                                             0xFFFFFFFFL
//RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET
#define RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET__global_offset__SHIFT                                               0x0
#define RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET__spmwithaccum_se_offset__SHIFT                                      0x8
#define RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET__spmwithaccum_global_offset__SHIFT                                  0x10
#define RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET__RESERVED__SHIFT                                                    0x18
#define RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET__global_offset_MASK                                                 0x000000FFL
#define RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET__spmwithaccum_se_offset_MASK                                        0x0000FF00L
#define RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET__spmwithaccum_global_offset_MASK                                    0x00FF0000L
#define RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET__RESERVED_MASK                                                      0xFF000000L
//RLC_SPM_PERFMON_SWA_GLB_SEGMENT_SIZE
#define RLC_SPM_PERFMON_SWA_GLB_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE__SHIFT                                     0x0
#define RLC_SPM_PERFMON_SWA_GLB_SEGMENT_SIZE__GLOBAL_NUM_LINE__SHIFT                                          0x8
#define RLC_SPM_PERFMON_SWA_GLB_SEGMENT_SIZE__RESERVED__SHIFT                                                 0x10
#define RLC_SPM_PERFMON_SWA_GLB_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE_MASK                                       0x000000FFL
#define RLC_SPM_PERFMON_SWA_GLB_SEGMENT_SIZE__GLOBAL_NUM_LINE_MASK                                            0x0000FF00L
#define RLC_SPM_PERFMON_SWA_GLB_SEGMENT_SIZE__RESERVED_MASK                                                   0xFFFF0000L
//RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS
#define RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS__spp_addr_region__SHIFT                                      0x0
#define RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS__swa_addr_region__SHIFT                                      0x8
#define RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS__RESERVED__SHIFT                                             0x10
#define RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS__spp_addr_region_MASK                                        0x000000FFL
#define RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS__swa_addr_region_MASK                                        0x0000FF00L
#define RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS__RESERVED_MASK                                               0xFFFF0000L
//RLC_PERFMON_CNTL
#define RLC_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                                0x0
#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT                                                        0xa
#define RLC_PERFMON_CNTL__PERFMON_STATE_MASK                                                                  0x00000007L
#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK                                                          0x00000400L
//RLC_PERFCOUNTER0_SELECT
#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT                                                    0x0
#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK                                                      0x000000FFL
//RLC_PERFCOUNTER1_SELECT
#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT                                                    0x0
#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK                                                      0x000000FFL
//RLC_GPU_IOV_PERF_CNT_CNTL
#define RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE__SHIFT                                                              0x0
#define RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT__SHIFT                                                         0x1
#define RLC_GPU_IOV_PERF_CNT_CNTL__RESET__SHIFT                                                               0x2
#define RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED__SHIFT                                                            0x3
#define RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE_MASK                                                                0x00000001L
#define RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT_MASK                                                           0x00000002L
#define RLC_GPU_IOV_PERF_CNT_CNTL__RESET_MASK                                                                 0x00000004L
#define RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED_MASK                                                              0xFFFFFFF8L
//RLC_GPU_IOV_PERF_CNT_WR_ADDR
#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID__SHIFT                                                             0x0
#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID__SHIFT                                                           0x4
#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED__SHIFT                                                         0x6
#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID_MASK                                                               0x0000000FL
#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID_MASK                                                             0x00000030L
#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED_MASK                                                           0xFFFFFFC0L
//RLC_GPU_IOV_PERF_CNT_WR_DATA
#define RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA__SHIFT                                                             0x0
#define RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA_MASK                                                               0xFFFFFFFFL
//RLC_GPU_IOV_PERF_CNT_RD_ADDR
#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID__SHIFT                                                             0x0
#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID__SHIFT                                                           0x4
#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED__SHIFT                                                         0x6
#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID_MASK                                                               0x0000000FL
#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID_MASK                                                             0x00000030L
#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED_MASK                                                           0xFFFFFFC0L
//RLC_GPU_IOV_PERF_CNT_RD_DATA
#define RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA__SHIFT                                                             0x0
#define RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA_MASK                                                               0xFFFFFFFFL
//RLC_PERFMON_CLK_CNTL
#define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE__SHIFT                                                      0x0
#define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK                                                        0x00000001L
//RMI_PERFCOUNTER0_SELECT
#define RMI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                              0x0
#define RMI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                             0xa
#define RMI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                             0x14
#define RMI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                            0x18
#define RMI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                             0x1c
#define RMI_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                0x000001FFL
#define RMI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                               0x0007FC00L
#define RMI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
#define RMI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
#define RMI_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                               0xF0000000L
//RMI_PERFCOUNTER0_SELECT1
#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                            0x0
#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                            0xa
#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                           0x18
#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                           0x1c
#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                              0x000001FFL
#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                              0x0007FC00L
#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                             0x0F000000L
#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                             0xF0000000L
//RMI_PERFCOUNTER1_SELECT
#define RMI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                              0x0
#define RMI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                             0x1c
#define RMI_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                0x000001FFL
#define RMI_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                               0xF0000000L
//RMI_PERFCOUNTER2_SELECT
#define RMI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                              0x0
#define RMI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT                                                             0xa
#define RMI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                             0x14
#define RMI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT                                                            0x18
#define RMI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                             0x1c
#define RMI_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                                0x000001FFL
#define RMI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK                                                               0x0007FC00L
#define RMI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
#define RMI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
#define RMI_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                               0xF0000000L
//RMI_PERFCOUNTER2_SELECT1
#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT                                                            0x0
#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT                                                            0xa
#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT                                                           0x18
#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT                                                           0x1c
#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK                                                              0x000001FFL
#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK                                                              0x0007FC00L
#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK                                                             0x0F000000L
#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK                                                             0xF0000000L
//RMI_PERFCOUNTER3_SELECT
#define RMI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                              0x0
#define RMI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                             0x1c
#define RMI_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                                0x000001FFL
#define RMI_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                               0xF0000000L
//RMI_PERF_COUNTER_CNTL
#define RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL__SHIFT                                                 0x0
#define RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL__SHIFT                                                 0x2
#define RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL__SHIFT                                                          0x4
#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0__SHIFT                                                 0x6
#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1__SHIFT                                                 0x8
#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID__SHIFT                                                        0xa
#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID__SHIFT                                                       0xe
#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD__SHIFT                                     0x13
#define RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET__SHIFT                                                         0x19
#define RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL__SHIFT                                                       0x1a
#define RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL_MASK                                                   0x00000003L
#define RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL_MASK                                                   0x0000000CL
#define RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL_MASK                                                            0x00000030L
#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0_MASK                                                   0x000000C0L
#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1_MASK                                                   0x00000300L
#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID_MASK                                                          0x00003C00L
#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID_MASK                                                         0x0007C000L
#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD_MASK                                       0x01F80000L
#define RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET_MASK                                                           0x02000000L
#define RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL_MASK                                                         0x04000000L
//GCR_PERFCOUNTER0_SELECT
#define GCR_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                              0x0
#define GCR_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                             0xa
#define GCR_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                             0x14
#define GCR_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                            0x18
#define GCR_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                             0x1c
#define GCR_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                0x000001FFL
#define GCR_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                               0x0007FC00L
#define GCR_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
#define GCR_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
#define GCR_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                               0xF0000000L
//GCR_PERFCOUNTER0_SELECT1
#define GCR_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                            0x0
#define GCR_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                            0xa
#define GCR_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                           0x18
#define GCR_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                           0x1c
#define GCR_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                              0x000001FFL
#define GCR_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                              0x0007FC00L
#define GCR_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                             0x0F000000L
#define GCR_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                             0xF0000000L
//GCR_PERFCOUNTER1_SELECT
#define GCR_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                              0x0
#define GCR_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                             0x18
#define GCR_PERFCOUNTER1_SELECT__CNTL_MODE__SHIFT                                                             0x1c
#define GCR_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                0x000001FFL
#define GCR_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                               0x0F000000L
#define GCR_PERFCOUNTER1_SELECT__CNTL_MODE_MASK                                                               0xF0000000L
//UTCL1_PERFCOUNTER0_SELECT
#define UTCL1_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                            0x0
#define UTCL1_PERFCOUNTER0_SELECT__COUNTER_MODE__SHIFT                                                        0x1c
#define UTCL1_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                              0x000003FFL
#define UTCL1_PERFCOUNTER0_SELECT__COUNTER_MODE_MASK                                                          0xF0000000L
//UTCL1_PERFCOUNTER1_SELECT
#define UTCL1_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                            0x0
#define UTCL1_PERFCOUNTER1_SELECT__COUNTER_MODE__SHIFT                                                        0x1c
#define UTCL1_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                              0x000003FFL
#define UTCL1_PERFCOUNTER1_SELECT__COUNTER_MODE_MASK                                                          0xF0000000L
//PA_PH_PERFCOUNTER0_SELECT
#define PA_PH_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                            0x0
#define PA_PH_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                           0xa
#define PA_PH_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                           0x14
#define PA_PH_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                          0x18
#define PA_PH_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                           0x1c
#define PA_PH_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                              0x000003FFL
#define PA_PH_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                             0x000FFC00L
#define PA_PH_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                             0x00F00000L
#define PA_PH_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                            0x0F000000L
#define PA_PH_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                             0xF0000000L
//PA_PH_PERFCOUNTER0_SELECT1
#define PA_PH_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                          0x0
#define PA_PH_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                          0xa
#define PA_PH_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                         0x18
#define PA_PH_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                         0x1c
#define PA_PH_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                            0x000003FFL
#define PA_PH_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                            0x000FFC00L
#define PA_PH_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                           0x0F000000L
#define PA_PH_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                           0xF0000000L
//PA_PH_PERFCOUNTER1_SELECT
#define PA_PH_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                            0x0
#define PA_PH_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT                                                           0xa
#define PA_PH_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                           0x14
#define PA_PH_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT                                                          0x18
#define PA_PH_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                           0x1c
#define PA_PH_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                              0x000003FFL
#define PA_PH_PERFCOUNTER1_SELECT__PERF_SEL1_MASK                                                             0x000FFC00L
#define PA_PH_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                             0x00F00000L
#define PA_PH_PERFCOUNTER1_SELECT__PERF_MODE1_MASK                                                            0x0F000000L
#define PA_PH_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                             0xF0000000L
//PA_PH_PERFCOUNTER2_SELECT
#define PA_PH_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                            0x0
#define PA_PH_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT                                                           0xa
#define PA_PH_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                           0x14
#define PA_PH_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT                                                          0x18
#define PA_PH_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                           0x1c
#define PA_PH_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                              0x000003FFL
#define PA_PH_PERFCOUNTER2_SELECT__PERF_SEL1_MASK                                                             0x000FFC00L
#define PA_PH_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                             0x00F00000L
#define PA_PH_PERFCOUNTER2_SELECT__PERF_MODE1_MASK                                                            0x0F000000L
#define PA_PH_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                             0xF0000000L
//PA_PH_PERFCOUNTER3_SELECT
#define PA_PH_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                            0x0
#define PA_PH_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT                                                           0xa
#define PA_PH_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT                                                           0x14
#define PA_PH_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT                                                          0x18
#define PA_PH_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                           0x1c
#define PA_PH_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                              0x000003FFL
#define PA_PH_PERFCOUNTER3_SELECT__PERF_SEL1_MASK                                                             0x000FFC00L
#define PA_PH_PERFCOUNTER3_SELECT__CNTR_MODE_MASK                                                             0x00F00000L
#define PA_PH_PERFCOUNTER3_SELECT__PERF_MODE1_MASK                                                            0x0F000000L
#define PA_PH_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                             0xF0000000L
//PA_PH_PERFCOUNTER4_SELECT
#define PA_PH_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT                                                            0x0
#define PA_PH_PERFCOUNTER4_SELECT__PERF_SEL_MASK                                                              0x000003FFL
//PA_PH_PERFCOUNTER5_SELECT
#define PA_PH_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT                                                            0x0
#define PA_PH_PERFCOUNTER5_SELECT__PERF_SEL_MASK                                                              0x000003FFL
//PA_PH_PERFCOUNTER6_SELECT
#define PA_PH_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT                                                            0x0
#define PA_PH_PERFCOUNTER6_SELECT__PERF_SEL_MASK                                                              0x000003FFL
//PA_PH_PERFCOUNTER7_SELECT
#define PA_PH_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT                                                            0x0
#define PA_PH_PERFCOUNTER7_SELECT__PERF_SEL_MASK                                                              0x000003FFL
//PA_PH_PERFCOUNTER1_SELECT1
#define PA_PH_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT                                                          0x0
#define PA_PH_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT                                                          0xa
#define PA_PH_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT                                                         0x18
#define PA_PH_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT                                                         0x1c
#define PA_PH_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK                                                            0x000003FFL
#define PA_PH_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK                                                            0x000FFC00L
#define PA_PH_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK                                                           0x0F000000L
#define PA_PH_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK                                                           0xF0000000L
//PA_PH_PERFCOUNTER2_SELECT1
#define PA_PH_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT                                                          0x0
#define PA_PH_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT                                                          0xa
#define PA_PH_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT                                                         0x18
#define PA_PH_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT                                                         0x1c
#define PA_PH_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK                                                            0x000003FFL
#define PA_PH_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK                                                            0x000FFC00L
#define PA_PH_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK                                                           0x0F000000L
#define PA_PH_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK                                                           0xF0000000L
//PA_PH_PERFCOUNTER3_SELECT1
#define PA_PH_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT                                                          0x0
#define PA_PH_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT                                                          0xa
#define PA_PH_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT                                                         0x18
#define PA_PH_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT                                                         0x1c
#define PA_PH_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK                                                            0x000003FFL
#define PA_PH_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK                                                            0x000FFC00L
#define PA_PH_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK                                                           0x0F000000L
#define PA_PH_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK                                                           0xF0000000L
//GL1A_PERFCOUNTER0_SELECT
#define GL1A_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                             0x0
#define GL1A_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                            0xa
#define GL1A_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                            0x14
#define GL1A_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                           0x18
#define GL1A_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                            0x1c
#define GL1A_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                               0x000003FFL
#define GL1A_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                              0x000FFC00L
#define GL1A_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                              0x00F00000L
#define GL1A_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                             0x0F000000L
#define GL1A_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                              0xF0000000L
//GL1A_PERFCOUNTER0_SELECT1
#define GL1A_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                           0x0
#define GL1A_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                           0xa
#define GL1A_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                          0x18
#define GL1A_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                          0x1c
#define GL1A_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                             0x000003FFL
#define GL1A_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                             0x000FFC00L
#define GL1A_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                            0x0F000000L
#define GL1A_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                            0xF0000000L
//GL1A_PERFCOUNTER1_SELECT
#define GL1A_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                             0x0
#define GL1A_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                            0x14
#define GL1A_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                            0x1c
#define GL1A_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                               0x000003FFL
#define GL1A_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                              0x00F00000L
#define GL1A_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                              0xF0000000L
//GL1A_PERFCOUNTER2_SELECT
#define GL1A_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                             0x0
#define GL1A_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                            0x14
#define GL1A_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                            0x1c
#define GL1A_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                               0x000003FFL
#define GL1A_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                              0x00F00000L
#define GL1A_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                              0xF0000000L
//GL1A_PERFCOUNTER3_SELECT
#define GL1A_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                             0x0
#define GL1A_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT                                                            0x14
#define GL1A_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                            0x1c
#define GL1A_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                               0x000003FFL
#define GL1A_PERFCOUNTER3_SELECT__CNTR_MODE_MASK                                                              0x00F00000L
#define GL1A_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                              0xF0000000L
//CHA_PERFCOUNTER0_SELECT
#define CHA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                              0x0
#define CHA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                             0xa
#define CHA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                             0x14
#define CHA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                            0x18
#define CHA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                             0x1c
#define CHA_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                0x000003FFL
#define CHA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
#define CHA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
#define CHA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
#define CHA_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                               0xF0000000L
//CHA_PERFCOUNTER0_SELECT1
#define CHA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                            0x0
#define CHA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                            0xa
#define CHA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                           0x18
#define CHA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                           0x1c
#define CHA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
#define CHA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
#define CHA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                             0x0F000000L
#define CHA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                             0xF0000000L
//CHA_PERFCOUNTER1_SELECT
#define CHA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                              0x0
#define CHA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                             0x14
#define CHA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                             0x1c
#define CHA_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                0x000003FFL
#define CHA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
#define CHA_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                               0xF0000000L
//CHA_PERFCOUNTER2_SELECT
#define CHA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                              0x0
#define CHA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                             0x14
#define CHA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                             0x1c
#define CHA_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                                0x000003FFL
#define CHA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
#define CHA_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                               0xF0000000L
//CHA_PERFCOUNTER3_SELECT
#define CHA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                              0x0
#define CHA_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT                                                             0x14
#define CHA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                             0x1c
#define CHA_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                                0x000003FFL
#define CHA_PERFCOUNTER3_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
#define CHA_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                               0xF0000000L
//GUS_PERFCOUNTER2_SELECT
#define GUS_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                              0x0
#define GUS_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT                                                             0xa
#define GUS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                             0x14
#define GUS_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT                                                            0x18
#define GUS_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                             0x1c
#define GUS_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                                0x000003FFL
#define GUS_PERFCOUNTER2_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
#define GUS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
#define GUS_PERFCOUNTER2_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
#define GUS_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                               0xF0000000L
//GUS_PERFCOUNTER2_SELECT1
#define GUS_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT                                                            0x0
#define GUS_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT                                                            0xa
#define GUS_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT                                                           0x18
#define GUS_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT                                                           0x1c
#define GUS_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
#define GUS_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
#define GUS_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK                                                             0x0F000000L
#define GUS_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK                                                             0xF0000000L
//GUS_PERFCOUNTER2_MODE
#define GUS_PERFCOUNTER2_MODE__COMPARE_MODE0__SHIFT                                                           0x0
#define GUS_PERFCOUNTER2_MODE__COMPARE_MODE1__SHIFT                                                           0x2
#define GUS_PERFCOUNTER2_MODE__COMPARE_MODE2__SHIFT                                                           0x4
#define GUS_PERFCOUNTER2_MODE__COMPARE_MODE3__SHIFT                                                           0x6
#define GUS_PERFCOUNTER2_MODE__COMPARE_VALUE0__SHIFT                                                          0x8
#define GUS_PERFCOUNTER2_MODE__COMPARE_VALUE1__SHIFT                                                          0xc
#define GUS_PERFCOUNTER2_MODE__COMPARE_VALUE2__SHIFT                                                          0x10
#define GUS_PERFCOUNTER2_MODE__COMPARE_VALUE3__SHIFT                                                          0x14
#define GUS_PERFCOUNTER2_MODE__COMPARE_MODE0_MASK                                                             0x00000003L
#define GUS_PERFCOUNTER2_MODE__COMPARE_MODE1_MASK                                                             0x0000000CL
#define GUS_PERFCOUNTER2_MODE__COMPARE_MODE2_MASK                                                             0x00000030L
#define GUS_PERFCOUNTER2_MODE__COMPARE_MODE3_MASK                                                             0x000000C0L
#define GUS_PERFCOUNTER2_MODE__COMPARE_VALUE0_MASK                                                            0x00000F00L
#define GUS_PERFCOUNTER2_MODE__COMPARE_VALUE1_MASK                                                            0x0000F000L
#define GUS_PERFCOUNTER2_MODE__COMPARE_VALUE2_MASK                                                            0x000F0000L
#define GUS_PERFCOUNTER2_MODE__COMPARE_VALUE3_MASK                                                            0x00F00000L
//GUS_PERFCOUNTER0_CFG
#define GUS_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                                 0x0
#define GUS_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                             0x8
#define GUS_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                                0x18
#define GUS_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                                   0x1c
#define GUS_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                    0x1d
#define GUS_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                                   0x000000FFL
#define GUS_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                               0x0000FF00L
#define GUS_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                                  0x0F000000L
#define GUS_PERFCOUNTER0_CFG__ENABLE_MASK                                                                     0x10000000L
#define GUS_PERFCOUNTER0_CFG__CLEAR_MASK                                                                      0x20000000L
//GUS_PERFCOUNTER1_CFG
#define GUS_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                                 0x0
#define GUS_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                             0x8
#define GUS_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                                0x18
#define GUS_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                                   0x1c
#define GUS_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                    0x1d
#define GUS_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                                   0x000000FFL
#define GUS_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                               0x0000FF00L
#define GUS_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                                  0x0F000000L
#define GUS_PERFCOUNTER1_CFG__ENABLE_MASK                                                                     0x10000000L
#define GUS_PERFCOUNTER1_CFG__CLEAR_MASK                                                                      0x20000000L
//GUS_PERFCOUNTER_RSLT_CNTL
#define GUS_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                                 0x0
#define GUS_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                       0x8
#define GUS_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                        0x10
#define GUS_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                          0x18
#define GUS_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                           0x19
#define GUS_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                                0x1a
#define GUS_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                                   0x0000000FL
#define GUS_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                         0x0000FF00L
#define GUS_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                          0x00FF0000L
#define GUS_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                            0x01000000L
#define GUS_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                             0x02000000L
#define GUS_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                                  0x04000000L


// addressBlock: gc_gcvml2pldec
//GCMC_VM_L2_PERFCOUNTER0_CFG
#define GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                          0x0
#define GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                      0x8
#define GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                         0x18
#define GCMC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                            0x1c
#define GCMC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                             0x1d
#define GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                            0x000000FFL
#define GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                        0x0000FF00L
#define GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                           0x0F000000L
#define GCMC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK                                                              0x10000000L
#define GCMC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK                                                               0x20000000L
//GCMC_VM_L2_PERFCOUNTER1_CFG
#define GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                          0x0
#define GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                      0x8
#define GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                         0x18
#define GCMC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                            0x1c
#define GCMC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                             0x1d
#define GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                            0x000000FFL
#define GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                        0x0000FF00L
#define GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                           0x0F000000L
#define GCMC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK                                                              0x10000000L
#define GCMC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK                                                               0x20000000L
//GCMC_VM_L2_PERFCOUNTER2_CFG
#define GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT                                                          0x0
#define GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT                                                      0x8
#define GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT                                                         0x18
#define GCMC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT                                                            0x1c
#define GCMC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT                                                             0x1d
#define GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK                                                            0x000000FFL
#define GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK                                                        0x0000FF00L
#define GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK                                                           0x0F000000L
#define GCMC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK                                                              0x10000000L
#define GCMC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK                                                               0x20000000L
//GCMC_VM_L2_PERFCOUNTER3_CFG
#define GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT                                                          0x0
#define GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT                                                      0x8
#define GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT                                                         0x18
#define GCMC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT                                                            0x1c
#define GCMC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT                                                             0x1d
#define GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK                                                            0x000000FFL
#define GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK                                                        0x0000FF00L
#define GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK                                                           0x0F000000L
#define GCMC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK                                                              0x10000000L
#define GCMC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK                                                               0x20000000L
//GCMC_VM_L2_PERFCOUNTER4_CFG
#define GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT                                                          0x0
#define GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT                                                      0x8
#define GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT                                                         0x18
#define GCMC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT                                                            0x1c
#define GCMC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT                                                             0x1d
#define GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK                                                            0x000000FFL
#define GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK                                                        0x0000FF00L
#define GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK                                                           0x0F000000L
#define GCMC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK                                                              0x10000000L
#define GCMC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK                                                               0x20000000L
//GCMC_VM_L2_PERFCOUNTER5_CFG
#define GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT                                                          0x0
#define GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT                                                      0x8
#define GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT                                                         0x18
#define GCMC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT                                                            0x1c
#define GCMC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT                                                             0x1d
#define GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK                                                            0x000000FFL
#define GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK                                                        0x0000FF00L
#define GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK                                                           0x0F000000L
#define GCMC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK                                                              0x10000000L
#define GCMC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK                                                               0x20000000L
//GCMC_VM_L2_PERFCOUNTER6_CFG
#define GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT                                                          0x0
#define GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT                                                      0x8
#define GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT                                                         0x18
#define GCMC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT                                                            0x1c
#define GCMC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT                                                             0x1d
#define GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK                                                            0x000000FFL
#define GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK                                                        0x0000FF00L
#define GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK                                                           0x0F000000L
#define GCMC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK                                                              0x10000000L
#define GCMC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK                                                               0x20000000L
//GCMC_VM_L2_PERFCOUNTER7_CFG
#define GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT                                                          0x0
#define GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT                                                      0x8
#define GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT                                                         0x18
#define GCMC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT                                                            0x1c
#define GCMC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT                                                             0x1d
#define GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK                                                            0x000000FFL
#define GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK                                                        0x0000FF00L
#define GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK                                                           0x0F000000L
#define GCMC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK                                                              0x10000000L
#define GCMC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK                                                               0x20000000L
//GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL
#define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                          0x0
#define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                0x8
#define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                 0x10
#define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                   0x18
#define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                    0x19
#define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                         0x1a
#define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                            0x0000000FL
#define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                  0x0000FF00L
#define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                   0x00FF0000L
#define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                     0x01000000L
#define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                      0x02000000L
#define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                           0x04000000L
//GCUTCL2_PERFCOUNTER0_CFG
#define GCUTCL2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                             0x0
#define GCUTCL2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                         0x8
#define GCUTCL2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                            0x18
#define GCUTCL2_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                               0x1c
#define GCUTCL2_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                0x1d
#define GCUTCL2_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                               0x000000FFL
#define GCUTCL2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                           0x0000FF00L
#define GCUTCL2_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                              0x0F000000L
#define GCUTCL2_PERFCOUNTER0_CFG__ENABLE_MASK                                                                 0x10000000L
#define GCUTCL2_PERFCOUNTER0_CFG__CLEAR_MASK                                                                  0x20000000L
//GCUTCL2_PERFCOUNTER1_CFG
#define GCUTCL2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                             0x0
#define GCUTCL2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                         0x8
#define GCUTCL2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                            0x18
#define GCUTCL2_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                               0x1c
#define GCUTCL2_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                0x1d
#define GCUTCL2_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                               0x000000FFL
#define GCUTCL2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                           0x0000FF00L
#define GCUTCL2_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                              0x0F000000L
#define GCUTCL2_PERFCOUNTER1_CFG__ENABLE_MASK                                                                 0x10000000L
#define GCUTCL2_PERFCOUNTER1_CFG__CLEAR_MASK                                                                  0x20000000L
//GCUTCL2_PERFCOUNTER2_CFG
#define GCUTCL2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT                                                             0x0
#define GCUTCL2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT                                                         0x8
#define GCUTCL2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT                                                            0x18
#define GCUTCL2_PERFCOUNTER2_CFG__ENABLE__SHIFT                                                               0x1c
#define GCUTCL2_PERFCOUNTER2_CFG__CLEAR__SHIFT                                                                0x1d
#define GCUTCL2_PERFCOUNTER2_CFG__PERF_SEL_MASK                                                               0x000000FFL
#define GCUTCL2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK                                                           0x0000FF00L
#define GCUTCL2_PERFCOUNTER2_CFG__PERF_MODE_MASK                                                              0x0F000000L
#define GCUTCL2_PERFCOUNTER2_CFG__ENABLE_MASK                                                                 0x10000000L
#define GCUTCL2_PERFCOUNTER2_CFG__CLEAR_MASK                                                                  0x20000000L
//GCUTCL2_PERFCOUNTER3_CFG
#define GCUTCL2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT                                                             0x0
#define GCUTCL2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT                                                         0x8
#define GCUTCL2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT                                                            0x18
#define GCUTCL2_PERFCOUNTER3_CFG__ENABLE__SHIFT                                                               0x1c
#define GCUTCL2_PERFCOUNTER3_CFG__CLEAR__SHIFT                                                                0x1d
#define GCUTCL2_PERFCOUNTER3_CFG__PERF_SEL_MASK                                                               0x000000FFL
#define GCUTCL2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK                                                           0x0000FF00L
#define GCUTCL2_PERFCOUNTER3_CFG__PERF_MODE_MASK                                                              0x0F000000L
#define GCUTCL2_PERFCOUNTER3_CFG__ENABLE_MASK                                                                 0x10000000L
#define GCUTCL2_PERFCOUNTER3_CFG__CLEAR_MASK                                                                  0x20000000L
//GCUTCL2_PERFCOUNTER_RSLT_CNTL
#define GCUTCL2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                             0x0
#define GCUTCL2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                   0x8
#define GCUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                    0x10
#define GCUTCL2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                      0x18
#define GCUTCL2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                       0x19
#define GCUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                            0x1a
#define GCUTCL2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                               0x0000000FL
#define GCUTCL2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                     0x0000FF00L
#define GCUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                      0x00FF0000L
#define GCUTCL2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                        0x01000000L
#define GCUTCL2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                         0x02000000L
#define GCUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                              0x04000000L


// addressBlock: gc_gcvml2perfsdec
//GCVML2_PERFCOUNTER2_0_SELECT
#define GCVML2_PERFCOUNTER2_0_SELECT__PERF_SEL__SHIFT                                                         0x0
#define GCVML2_PERFCOUNTER2_0_SELECT__PERF_SEL1__SHIFT                                                        0xa
#define GCVML2_PERFCOUNTER2_0_SELECT__CNTR_MODE__SHIFT                                                        0x14
#define GCVML2_PERFCOUNTER2_0_SELECT__PERF_MODE1__SHIFT                                                       0x18
#define GCVML2_PERFCOUNTER2_0_SELECT__PERF_MODE__SHIFT                                                        0x1c
#define GCVML2_PERFCOUNTER2_0_SELECT__PERF_SEL_MASK                                                           0x000003FFL
#define GCVML2_PERFCOUNTER2_0_SELECT__PERF_SEL1_MASK                                                          0x000FFC00L
#define GCVML2_PERFCOUNTER2_0_SELECT__CNTR_MODE_MASK                                                          0x00F00000L
#define GCVML2_PERFCOUNTER2_0_SELECT__PERF_MODE1_MASK                                                         0x0F000000L
#define GCVML2_PERFCOUNTER2_0_SELECT__PERF_MODE_MASK                                                          0xF0000000L
//GCVML2_PERFCOUNTER2_1_SELECT
#define GCVML2_PERFCOUNTER2_1_SELECT__PERF_SEL__SHIFT                                                         0x0
#define GCVML2_PERFCOUNTER2_1_SELECT__PERF_SEL1__SHIFT                                                        0xa
#define GCVML2_PERFCOUNTER2_1_SELECT__CNTR_MODE__SHIFT                                                        0x14
#define GCVML2_PERFCOUNTER2_1_SELECT__PERF_MODE1__SHIFT                                                       0x18
#define GCVML2_PERFCOUNTER2_1_SELECT__PERF_MODE__SHIFT                                                        0x1c
#define GCVML2_PERFCOUNTER2_1_SELECT__PERF_SEL_MASK                                                           0x000003FFL
#define GCVML2_PERFCOUNTER2_1_SELECT__PERF_SEL1_MASK                                                          0x000FFC00L
#define GCVML2_PERFCOUNTER2_1_SELECT__CNTR_MODE_MASK                                                          0x00F00000L
#define GCVML2_PERFCOUNTER2_1_SELECT__PERF_MODE1_MASK                                                         0x0F000000L
#define GCVML2_PERFCOUNTER2_1_SELECT__PERF_MODE_MASK                                                          0xF0000000L
//GCVML2_PERFCOUNTER2_0_SELECT1
#define GCVML2_PERFCOUNTER2_0_SELECT1__PERF_SEL2__SHIFT                                                       0x0
#define GCVML2_PERFCOUNTER2_0_SELECT1__PERF_SEL3__SHIFT                                                       0xa
#define GCVML2_PERFCOUNTER2_0_SELECT1__PERF_MODE3__SHIFT                                                      0x18
#define GCVML2_PERFCOUNTER2_0_SELECT1__PERF_MODE2__SHIFT                                                      0x1c
#define GCVML2_PERFCOUNTER2_0_SELECT1__PERF_SEL2_MASK                                                         0x000003FFL
#define GCVML2_PERFCOUNTER2_0_SELECT1__PERF_SEL3_MASK                                                         0x000FFC00L
#define GCVML2_PERFCOUNTER2_0_SELECT1__PERF_MODE3_MASK                                                        0x0F000000L
#define GCVML2_PERFCOUNTER2_0_SELECT1__PERF_MODE2_MASK                                                        0xF0000000L
//GCVML2_PERFCOUNTER2_1_SELECT1
#define GCVML2_PERFCOUNTER2_1_SELECT1__PERF_SEL2__SHIFT                                                       0x0
#define GCVML2_PERFCOUNTER2_1_SELECT1__PERF_SEL3__SHIFT                                                       0xa
#define GCVML2_PERFCOUNTER2_1_SELECT1__PERF_MODE3__SHIFT                                                      0x18
#define GCVML2_PERFCOUNTER2_1_SELECT1__PERF_MODE2__SHIFT                                                      0x1c
#define GCVML2_PERFCOUNTER2_1_SELECT1__PERF_SEL2_MASK                                                         0x000003FFL
#define GCVML2_PERFCOUNTER2_1_SELECT1__PERF_SEL3_MASK                                                         0x000FFC00L
#define GCVML2_PERFCOUNTER2_1_SELECT1__PERF_MODE3_MASK                                                        0x0F000000L
#define GCVML2_PERFCOUNTER2_1_SELECT1__PERF_MODE2_MASK                                                        0xF0000000L
//GCVML2_PERFCOUNTER2_0_MODE
#define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE0__SHIFT                                                      0x0
#define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE1__SHIFT                                                      0x2
#define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE2__SHIFT                                                      0x4
#define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE3__SHIFT                                                      0x6
#define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE0__SHIFT                                                     0x8
#define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE1__SHIFT                                                     0xc
#define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE2__SHIFT                                                     0x10
#define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE3__SHIFT                                                     0x14
#define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE0_MASK                                                        0x00000003L
#define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE1_MASK                                                        0x0000000CL
#define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE2_MASK                                                        0x00000030L
#define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE3_MASK                                                        0x000000C0L
#define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE0_MASK                                                       0x00000F00L
#define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE1_MASK                                                       0x0000F000L
#define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE2_MASK                                                       0x000F0000L
#define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE3_MASK                                                       0x00F00000L
//GCVML2_PERFCOUNTER2_1_MODE
#define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE0__SHIFT                                                      0x0
#define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE1__SHIFT                                                      0x2
#define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE2__SHIFT                                                      0x4
#define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE3__SHIFT                                                      0x6
#define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE0__SHIFT                                                     0x8
#define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE1__SHIFT                                                     0xc
#define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE2__SHIFT                                                     0x10
#define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE3__SHIFT                                                     0x14
#define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE0_MASK                                                        0x00000003L
#define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE1_MASK                                                        0x0000000CL
#define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE2_MASK                                                        0x00000030L
#define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE3_MASK                                                        0x000000C0L
#define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE0_MASK                                                       0x00000F00L
#define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE1_MASK                                                       0x0000F000L
#define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE2_MASK                                                       0x000F0000L
#define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE3_MASK                                                       0x00F00000L


// addressBlock: gc_sdma0_sdma0perfsdec
//SDMA0_PERFCNT_PERFCOUNTER0_CFG
#define SDMA0_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                       0x0
#define SDMA0_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                   0x8
#define SDMA0_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                      0x18
#define SDMA0_PERFCNT_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                         0x1c
#define SDMA0_PERFCNT_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                          0x1d
#define SDMA0_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                         0x000000FFL
#define SDMA0_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                     0x0000FF00L
#define SDMA0_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                        0x0F000000L
#define SDMA0_PERFCNT_PERFCOUNTER0_CFG__ENABLE_MASK                                                           0x10000000L
#define SDMA0_PERFCNT_PERFCOUNTER0_CFG__CLEAR_MASK                                                            0x20000000L
//SDMA0_PERFCNT_PERFCOUNTER1_CFG
#define SDMA0_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                       0x0
#define SDMA0_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                   0x8
#define SDMA0_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                      0x18
#define SDMA0_PERFCNT_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                         0x1c
#define SDMA0_PERFCNT_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                          0x1d
#define SDMA0_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                         0x000000FFL
#define SDMA0_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                     0x0000FF00L
#define SDMA0_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                        0x0F000000L
#define SDMA0_PERFCNT_PERFCOUNTER1_CFG__ENABLE_MASK                                                           0x10000000L
#define SDMA0_PERFCNT_PERFCOUNTER1_CFG__CLEAR_MASK                                                            0x20000000L
//SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL
#define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                       0x0
#define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                             0x8
#define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                              0x10
#define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                0x18
#define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                 0x19
#define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                      0x1a
#define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                         0x0000000FL
#define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                               0x0000FF00L
#define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                0x00FF0000L
#define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                  0x01000000L
#define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                   0x02000000L
#define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                        0x04000000L
//SDMA0_PERFCNT_MISC_CNTL
#define SDMA0_PERFCNT_MISC_CNTL__CMD_OP__SHIFT                                                                0x0
#define SDMA0_PERFCNT_MISC_CNTL__CMD_OP_MASK                                                                  0x0000FFFFL
//SDMA0_PERFCOUNTER0_SELECT
#define SDMA0_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                            0x0
#define SDMA0_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                           0xa
#define SDMA0_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                           0x14
#define SDMA0_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                          0x18
#define SDMA0_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                           0x1c
#define SDMA0_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                              0x000003FFL
#define SDMA0_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                             0x000FFC00L
#define SDMA0_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                             0x00F00000L
#define SDMA0_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                            0x0F000000L
#define SDMA0_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                             0xF0000000L
//SDMA0_PERFCOUNTER0_SELECT1
#define SDMA0_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                          0x0
#define SDMA0_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                          0xa
#define SDMA0_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                         0x18
#define SDMA0_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                         0x1c
#define SDMA0_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                            0x000003FFL
#define SDMA0_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                            0x000FFC00L
#define SDMA0_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                           0x0F000000L
#define SDMA0_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                           0xF0000000L
//SDMA0_PERFCOUNTER1_SELECT
#define SDMA0_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                            0x0
#define SDMA0_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT                                                           0xa
#define SDMA0_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                           0x14
#define SDMA0_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT                                                          0x18
#define SDMA0_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                           0x1c
#define SDMA0_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                              0x000003FFL
#define SDMA0_PERFCOUNTER1_SELECT__PERF_SEL1_MASK                                                             0x000FFC00L
#define SDMA0_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                             0x00F00000L
#define SDMA0_PERFCOUNTER1_SELECT__PERF_MODE1_MASK                                                            0x0F000000L
#define SDMA0_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                             0xF0000000L
//SDMA0_PERFCOUNTER1_SELECT1
#define SDMA0_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT                                                          0x0
#define SDMA0_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT                                                          0xa
#define SDMA0_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT                                                         0x18
#define SDMA0_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT                                                         0x1c
#define SDMA0_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK                                                            0x000003FFL
#define SDMA0_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK                                                            0x000FFC00L
#define SDMA0_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK                                                           0x0F000000L
#define SDMA0_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK                                                           0xF0000000L


// addressBlock: gc_sdma1_sdma1perfsdec
//SDMA1_PERFCNT_PERFCOUNTER0_CFG
#define SDMA1_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                       0x0
#define SDMA1_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                   0x8
#define SDMA1_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                      0x18
#define SDMA1_PERFCNT_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                         0x1c
#define SDMA1_PERFCNT_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                          0x1d
#define SDMA1_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                         0x000000FFL
#define SDMA1_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                     0x0000FF00L
#define SDMA1_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                        0x0F000000L
#define SDMA1_PERFCNT_PERFCOUNTER0_CFG__ENABLE_MASK                                                           0x10000000L
#define SDMA1_PERFCNT_PERFCOUNTER0_CFG__CLEAR_MASK                                                            0x20000000L
//SDMA1_PERFCNT_PERFCOUNTER1_CFG
#define SDMA1_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                       0x0
#define SDMA1_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                   0x8
#define SDMA1_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                      0x18
#define SDMA1_PERFCNT_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                         0x1c
#define SDMA1_PERFCNT_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                          0x1d
#define SDMA1_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                         0x000000FFL
#define SDMA1_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                     0x0000FF00L
#define SDMA1_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                        0x0F000000L
#define SDMA1_PERFCNT_PERFCOUNTER1_CFG__ENABLE_MASK                                                           0x10000000L
#define SDMA1_PERFCNT_PERFCOUNTER1_CFG__CLEAR_MASK                                                            0x20000000L
//SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL
#define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                       0x0
#define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                             0x8
#define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                              0x10
#define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                0x18
#define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                 0x19
#define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                      0x1a
#define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                         0x0000000FL
#define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                               0x0000FF00L
#define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                0x00FF0000L
#define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                  0x01000000L
#define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                   0x02000000L
#define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                        0x04000000L
//SDMA1_PERFCNT_MISC_CNTL
#define SDMA1_PERFCNT_MISC_CNTL__CMD_OP__SHIFT                                                                0x0
#define SDMA1_PERFCNT_MISC_CNTL__CMD_OP_MASK                                                                  0x0000FFFFL
//SDMA1_PERFCOUNTER0_SELECT
#define SDMA1_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                            0x0
#define SDMA1_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                           0xa
#define SDMA1_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                           0x14
#define SDMA1_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                          0x18
#define SDMA1_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                           0x1c
#define SDMA1_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                              0x000003FFL
#define SDMA1_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                             0x000FFC00L
#define SDMA1_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                             0x00F00000L
#define SDMA1_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                            0x0F000000L
#define SDMA1_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                             0xF0000000L
//SDMA1_PERFCOUNTER0_SELECT1
#define SDMA1_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                          0x0
#define SDMA1_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                          0xa
#define SDMA1_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                         0x18
#define SDMA1_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                         0x1c
#define SDMA1_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                            0x000003FFL
#define SDMA1_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                            0x000FFC00L
#define SDMA1_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                           0x0F000000L
#define SDMA1_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                           0xF0000000L
//SDMA1_PERFCOUNTER1_SELECT
#define SDMA1_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                            0x0
#define SDMA1_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT                                                           0xa
#define SDMA1_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                           0x14
#define SDMA1_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT                                                          0x18
#define SDMA1_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                           0x1c
#define SDMA1_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                              0x000003FFL
#define SDMA1_PERFCOUNTER1_SELECT__PERF_SEL1_MASK                                                             0x000FFC00L
#define SDMA1_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                             0x00F00000L
#define SDMA1_PERFCOUNTER1_SELECT__PERF_MODE1_MASK                                                            0x0F000000L
#define SDMA1_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                             0xF0000000L
//SDMA1_PERFCOUNTER1_SELECT1
#define SDMA1_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT                                                          0x0
#define SDMA1_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT                                                          0xa
#define SDMA1_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT                                                         0x18
#define SDMA1_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT                                                         0x1c
#define SDMA1_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK                                                            0x000003FFL
#define SDMA1_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK                                                            0x000FFC00L
#define SDMA1_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK                                                           0x0F000000L
#define SDMA1_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK                                                           0xF0000000L


// addressBlock: gc_sdma2_sdma2perfsdec
//SDMA2_PERFCNT_PERFCOUNTER0_CFG
#define SDMA2_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                       0x0
#define SDMA2_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                   0x8
#define SDMA2_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                      0x18
#define SDMA2_PERFCNT_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                         0x1c
#define SDMA2_PERFCNT_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                          0x1d
#define SDMA2_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                         0x000000FFL
#define SDMA2_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                     0x0000FF00L
#define SDMA2_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                        0x0F000000L
#define SDMA2_PERFCNT_PERFCOUNTER0_CFG__ENABLE_MASK                                                           0x10000000L
#define SDMA2_PERFCNT_PERFCOUNTER0_CFG__CLEAR_MASK                                                            0x20000000L
//SDMA2_PERFCNT_PERFCOUNTER1_CFG
#define SDMA2_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                       0x0
#define SDMA2_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                   0x8
#define SDMA2_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                      0x18
#define SDMA2_PERFCNT_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                         0x1c
#define SDMA2_PERFCNT_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                          0x1d
#define SDMA2_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                         0x000000FFL
#define SDMA2_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                     0x0000FF00L
#define SDMA2_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                        0x0F000000L
#define SDMA2_PERFCNT_PERFCOUNTER1_CFG__ENABLE_MASK                                                           0x10000000L
#define SDMA2_PERFCNT_PERFCOUNTER1_CFG__CLEAR_MASK                                                            0x20000000L
//SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL
#define SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                       0x0
#define SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                             0x8
#define SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                              0x10
#define SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                0x18
#define SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                 0x19
#define SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                      0x1a
#define SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                         0x0000000FL
#define SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                               0x0000FF00L
#define SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                0x00FF0000L
#define SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                  0x01000000L
#define SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                   0x02000000L
#define SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                        0x04000000L
//SDMA2_PERFCNT_MISC_CNTL
#define SDMA2_PERFCNT_MISC_CNTL__CMD_OP__SHIFT                                                                0x0
#define SDMA2_PERFCNT_MISC_CNTL__CMD_OP_MASK                                                                  0x0000FFFFL
//SDMA2_PERFCOUNTER0_SELECT
#define SDMA2_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                            0x0
#define SDMA2_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                           0xa
#define SDMA2_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                           0x14
#define SDMA2_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                          0x18
#define SDMA2_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                           0x1c
#define SDMA2_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                              0x000003FFL
#define SDMA2_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                             0x000FFC00L
#define SDMA2_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                             0x00F00000L
#define SDMA2_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                            0x0F000000L
#define SDMA2_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                             0xF0000000L
//SDMA2_PERFCOUNTER0_SELECT1
#define SDMA2_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                          0x0
#define SDMA2_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                          0xa
#define SDMA2_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                         0x18
#define SDMA2_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                         0x1c
#define SDMA2_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                            0x000003FFL
#define SDMA2_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                            0x000FFC00L
#define SDMA2_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                           0x0F000000L
#define SDMA2_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                           0xF0000000L
//SDMA2_PERFCOUNTER1_SELECT
#define SDMA2_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                            0x0
#define SDMA2_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT                                                           0xa
#define SDMA2_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                           0x14
#define SDMA2_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT                                                          0x18
#define SDMA2_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                           0x1c
#define SDMA2_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                              0x000003FFL
#define SDMA2_PERFCOUNTER1_SELECT__PERF_SEL1_MASK                                                             0x000FFC00L
#define SDMA2_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                             0x00F00000L
#define SDMA2_PERFCOUNTER1_SELECT__PERF_MODE1_MASK                                                            0x0F000000L
#define SDMA2_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                             0xF0000000L
//SDMA2_PERFCOUNTER1_SELECT1
#define SDMA2_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT                                                          0x0
#define SDMA2_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT                                                          0xa
#define SDMA2_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT                                                         0x18
#define SDMA2_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT                                                         0x1c
#define SDMA2_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK                                                            0x000003FFL
#define SDMA2_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK                                                            0x000FFC00L
#define SDMA2_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK                                                           0x0F000000L
#define SDMA2_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK                                                           0xF0000000L


// addressBlock: gc_sdma3_sdma3perfsdec
//SDMA3_PERFCNT_PERFCOUNTER0_CFG
#define SDMA3_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                       0x0
#define SDMA3_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                   0x8
#define SDMA3_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                      0x18
#define SDMA3_PERFCNT_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                         0x1c
#define SDMA3_PERFCNT_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                          0x1d
#define SDMA3_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                         0x000000FFL
#define SDMA3_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                     0x0000FF00L
#define SDMA3_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                        0x0F000000L
#define SDMA3_PERFCNT_PERFCOUNTER0_CFG__ENABLE_MASK                                                           0x10000000L
#define SDMA3_PERFCNT_PERFCOUNTER0_CFG__CLEAR_MASK                                                            0x20000000L
//SDMA3_PERFCNT_PERFCOUNTER1_CFG
#define SDMA3_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                       0x0
#define SDMA3_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                   0x8
#define SDMA3_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                      0x18
#define SDMA3_PERFCNT_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                         0x1c
#define SDMA3_PERFCNT_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                          0x1d
#define SDMA3_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                         0x000000FFL
#define SDMA3_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                     0x0000FF00L
#define SDMA3_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                        0x0F000000L
#define SDMA3_PERFCNT_PERFCOUNTER1_CFG__ENABLE_MASK                                                           0x10000000L
#define SDMA3_PERFCNT_PERFCOUNTER1_CFG__CLEAR_MASK                                                            0x20000000L
//SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL
#define SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                       0x0
#define SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                             0x8
#define SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                              0x10
#define SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                0x18
#define SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                 0x19
#define SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                      0x1a
#define SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                         0x0000000FL
#define SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                               0x0000FF00L
#define SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                0x00FF0000L
#define SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                  0x01000000L
#define SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                   0x02000000L
#define SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                        0x04000000L
//SDMA3_PERFCNT_MISC_CNTL
#define SDMA3_PERFCNT_MISC_CNTL__CMD_OP__SHIFT                                                                0x0
#define SDMA3_PERFCNT_MISC_CNTL__CMD_OP_MASK                                                                  0x0000FFFFL
//SDMA3_PERFCOUNTER0_SELECT
#define SDMA3_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                            0x0
#define SDMA3_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                           0xa
#define SDMA3_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                           0x14
#define SDMA3_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                          0x18
#define SDMA3_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                           0x1c
#define SDMA3_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                              0x000003FFL
#define SDMA3_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                             0x000FFC00L
#define SDMA3_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                             0x00F00000L
#define SDMA3_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                            0x0F000000L
#define SDMA3_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                             0xF0000000L
//SDMA3_PERFCOUNTER0_SELECT1
#define SDMA3_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                          0x0
#define SDMA3_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                          0xa
#define SDMA3_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                         0x18
#define SDMA3_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                         0x1c
#define SDMA3_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                            0x000003FFL
#define SDMA3_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                            0x000FFC00L
#define SDMA3_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                           0x0F000000L
#define SDMA3_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                           0xF0000000L
//SDMA3_PERFCOUNTER1_SELECT
#define SDMA3_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                            0x0
#define SDMA3_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT                                                           0xa
#define SDMA3_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                           0x14
#define SDMA3_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT                                                          0x18
#define SDMA3_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                           0x1c
#define SDMA3_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                              0x000003FFL
#define SDMA3_PERFCOUNTER1_SELECT__PERF_SEL1_MASK                                                             0x000FFC00L
#define SDMA3_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                             0x00F00000L
#define SDMA3_PERFCOUNTER1_SELECT__PERF_MODE1_MASK                                                            0x0F000000L
#define SDMA3_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                             0xF0000000L
//SDMA3_PERFCOUNTER1_SELECT1
#define SDMA3_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT                                                          0x0
#define SDMA3_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT                                                          0xa
#define SDMA3_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT                                                         0x18
#define SDMA3_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT                                                         0x1c
#define SDMA3_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK                                                            0x000003FFL
#define SDMA3_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK                                                            0x000FFC00L
#define SDMA3_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK                                                           0x0F000000L
#define SDMA3_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK                                                           0xF0000000L




// addressBlock: gc_grtavfsdec
//GRTAVFS_RTAVFS_REG_ADDR
#define GRTAVFS_RTAVFS_REG_ADDR__RTAVFSADDR__SHIFT                                                            0x0
#define GRTAVFS_RTAVFS_REG_ADDR__RTAVFSADDR_MASK                                                              0x000003FFL
//RTAVFS_RTAVFS_REG_ADDR
#define RTAVFS_RTAVFS_REG_ADDR__RTAVFSADDR__SHIFT                                                             0x0
#define RTAVFS_RTAVFS_REG_ADDR__RTAVFSADDR_MASK                                                               0x000003FFL
//GRTAVFS_RTAVFS_WR_DATA
#define GRTAVFS_RTAVFS_WR_DATA__RTAVFSDATA__SHIFT                                                             0x0
#define GRTAVFS_RTAVFS_WR_DATA__RTAVFSDATA_MASK                                                               0xFFFFFFFFL
//RTAVFS_RTAVFS_WR_DATA
#define RTAVFS_RTAVFS_WR_DATA__RTAVFSDATA__SHIFT                                                              0x0
#define RTAVFS_RTAVFS_WR_DATA__RTAVFSDATA_MASK                                                                0xFFFFFFFFL
//GRTAVFS_GENERAL_0
#define GRTAVFS_GENERAL_0__DATA__SHIFT                                                                        0x0
#define GRTAVFS_GENERAL_0__DATA_MASK                                                                          0xFFFFFFFFL
//GRTAVFS_RTAVFS_RD_DATA
#define GRTAVFS_RTAVFS_RD_DATA__RTAVFSDATA__SHIFT                                                             0x0
#define GRTAVFS_RTAVFS_RD_DATA__RTAVFSDATA_MASK                                                               0xFFFFFFFFL
//GRTAVFS_RTAVFS_REG_CTRL
#define GRTAVFS_RTAVFS_REG_CTRL__SET_WR_EN__SHIFT                                                             0x0
#define GRTAVFS_RTAVFS_REG_CTRL__SET_RD_EN__SHIFT                                                             0x1
#define GRTAVFS_RTAVFS_REG_CTRL__SET_WR_EN_MASK                                                               0x00000001L
#define GRTAVFS_RTAVFS_REG_CTRL__SET_RD_EN_MASK                                                               0x00000002L
//GRTAVFS_RTAVFS_REG_STATUS
#define GRTAVFS_RTAVFS_REG_STATUS__RTAVFS_WR_ACK__SHIFT                                                       0x0
#define GRTAVFS_RTAVFS_REG_STATUS__RTAVFS_RD_DATA_VALID__SHIFT                                                0x1
#define GRTAVFS_RTAVFS_REG_STATUS__RTAVFS_WR_ACK_MASK                                                         0x00000001L
#define GRTAVFS_RTAVFS_REG_STATUS__RTAVFS_RD_DATA_VALID_MASK                                                  0x00000002L
//GRTAVFS_TARG_FREQ
#define GRTAVFS_TARG_FREQ__TARGET_FREQUENCY__SHIFT                                                            0x0
#define GRTAVFS_TARG_FREQ__REQUEST__SHIFT                                                                     0x10
#define GRTAVFS_TARG_FREQ__RESERVED__SHIFT                                                                    0x11
#define GRTAVFS_TARG_FREQ__TARGET_FREQUENCY_MASK                                                              0x0000FFFFL
#define GRTAVFS_TARG_FREQ__REQUEST_MASK                                                                       0x00010000L
#define GRTAVFS_TARG_FREQ__RESERVED_MASK                                                                      0xFFFE0000L
//GRTAVFS_TARG_VOLT
#define GRTAVFS_TARG_VOLT__TARGET_VOLTAGE__SHIFT                                                              0x0
#define GRTAVFS_TARG_VOLT__VALID__SHIFT                                                                       0xa
#define GRTAVFS_TARG_VOLT__RESERVED__SHIFT                                                                    0xb
#define GRTAVFS_TARG_VOLT__TARGET_VOLTAGE_MASK                                                                0x000003FFL
#define GRTAVFS_TARG_VOLT__VALID_MASK                                                                         0x00000400L
#define GRTAVFS_TARG_VOLT__RESERVED_MASK                                                                      0xFFFFF800L
//GRTAVFS_SOFT_RESET
#define GRTAVFS_SOFT_RESET__RESETN_OVERRIDE__SHIFT                                                            0x0
#define GRTAVFS_SOFT_RESET__RESERVED__SHIFT                                                                   0x1
#define GRTAVFS_SOFT_RESET__RESETN_OVERRIDE_MASK                                                              0x00000001L
#define GRTAVFS_SOFT_RESET__RESERVED_MASK                                                                     0xFFFFFFFEL
//GRTAVFS_PSM_CNTL
#define GRTAVFS_PSM_CNTL__PSM_COUNT__SHIFT                                                                    0x0
#define GRTAVFS_PSM_CNTL__PSM_SAMPLE_EN__SHIFT                                                                0xe
#define GRTAVFS_PSM_CNTL__RESERVED__SHIFT                                                                     0xf
#define GRTAVFS_PSM_CNTL__PSM_COUNT_MASK                                                                      0x00003FFFL
#define GRTAVFS_PSM_CNTL__PSM_SAMPLE_EN_MASK                                                                  0x00004000L
#define GRTAVFS_PSM_CNTL__RESERVED_MASK                                                                       0xFFFF8000L
//GRTAVFS_CLK_CNTL
#define GRTAVFS_CLK_CNTL__GRTAVFS_MUX_CLK_SEL__SHIFT                                                          0x0
#define GRTAVFS_CLK_CNTL__FORCE_GRTAVFS_CLK_SEL__SHIFT                                                        0x1
#define GRTAVFS_CLK_CNTL__RESERVED__SHIFT                                                                     0x2
#define GRTAVFS_CLK_CNTL__GRTAVFS_MUX_CLK_SEL_MASK                                                            0x00000001L
#define GRTAVFS_CLK_CNTL__FORCE_GRTAVFS_CLK_SEL_MASK                                                          0x00000002L
#define GRTAVFS_CLK_CNTL__RESERVED_MASK                                                                       0xFFFFFFFCL


// addressBlock: gc_rlcdec
//RLC_CNTL
#define RLC_CNTL__RLC_ENABLE_F32__SHIFT                                                                       0x0
#define RLC_CNTL__FORCE_RETRY__SHIFT                                                                          0x1
#define RLC_CNTL__READ_CACHE_DISABLE__SHIFT                                                                   0x2
#define RLC_CNTL__RLC_STEP_F32__SHIFT                                                                         0x3
#define RLC_CNTL__RESERVED__SHIFT                                                                             0x4
#define RLC_CNTL__RLC_ENABLE_F32_MASK                                                                         0x00000001L
#define RLC_CNTL__FORCE_RETRY_MASK                                                                            0x00000002L
#define RLC_CNTL__READ_CACHE_DISABLE_MASK                                                                     0x00000004L
#define RLC_CNTL__RLC_STEP_F32_MASK                                                                           0x00000008L
#define RLC_CNTL__RESERVED_MASK                                                                               0xFFFFFFF0L
//RLC_F32_UCODE_VERSION
#define RLC_F32_UCODE_VERSION__THREAD0_VERSION__SHIFT                                                         0x0
#define RLC_F32_UCODE_VERSION__THREAD1_VERSION__SHIFT                                                         0xa
#define RLC_F32_UCODE_VERSION__THREAD2_VERSION__SHIFT                                                         0x14
#define RLC_F32_UCODE_VERSION__THREAD0_VERSION_MASK                                                           0x000003FFL
#define RLC_F32_UCODE_VERSION__THREAD1_VERSION_MASK                                                           0x000FFC00L
#define RLC_F32_UCODE_VERSION__THREAD2_VERSION_MASK                                                           0x3FF00000L
//RLC_STAT
#define RLC_STAT__RLC_BUSY__SHIFT                                                                             0x0
#define RLC_STAT__RLC_SRM_BUSY__SHIFT                                                                         0x1
#define RLC_STAT__RLC_GPM_BUSY__SHIFT                                                                         0x2
#define RLC_STAT__RLC_SPM_BUSY__SHIFT                                                                         0x3
#define RLC_STAT__MC_BUSY__SHIFT                                                                              0x4
#define RLC_STAT__RLC_THREAD_0_BUSY__SHIFT                                                                    0x5
#define RLC_STAT__RLC_THREAD_1_BUSY__SHIFT                                                                    0x6
#define RLC_STAT__RLC_THREAD_2_BUSY__SHIFT                                                                    0x7
#define RLC_STAT__RESERVED__SHIFT                                                                             0x8
#define RLC_STAT__RLC_BUSY_MASK                                                                               0x00000001L
#define RLC_STAT__RLC_SRM_BUSY_MASK                                                                           0x00000002L
#define RLC_STAT__RLC_GPM_BUSY_MASK                                                                           0x00000004L
#define RLC_STAT__RLC_SPM_BUSY_MASK                                                                           0x00000008L
#define RLC_STAT__MC_BUSY_MASK                                                                                0x00000010L
#define RLC_STAT__RLC_THREAD_0_BUSY_MASK                                                                      0x00000020L
#define RLC_STAT__RLC_THREAD_1_BUSY_MASK                                                                      0x00000040L
#define RLC_STAT__RLC_THREAD_2_BUSY_MASK                                                                      0x00000080L
#define RLC_STAT__RESERVED_MASK                                                                               0xFFFFFF00L
//RLC_MEM_SLP_CNTL
#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN__SHIFT                                                                0x0
#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN__SHIFT                                                                0x1
#define RLC_MEM_SLP_CNTL__RESERVED__SHIFT                                                                     0x2
#define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE__SHIFT                                                      0x7
#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY__SHIFT                                                          0x8
#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY__SHIFT                                                         0x10
#define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT                                                                    0x18
#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK                                                                  0x00000001L
#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK                                                                  0x00000002L
#define RLC_MEM_SLP_CNTL__RESERVED_MASK                                                                       0x0000007CL
#define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE_MASK                                                        0x00000080L
#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY_MASK                                                            0x0000FF00L
#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY_MASK                                                           0x00FF0000L
#define RLC_MEM_SLP_CNTL__RESERVED1_MASK                                                                      0xFF000000L
//SMU_RLC_RESPONSE
#define SMU_RLC_RESPONSE__RESP__SHIFT                                                                         0x0
#define SMU_RLC_RESPONSE__RESP_MASK                                                                           0xFFFFFFFFL
//RLC_RLCV_SAFE_MODE
#define RLC_RLCV_SAFE_MODE__CMD__SHIFT                                                                        0x0
#define RLC_RLCV_SAFE_MODE__MESSAGE__SHIFT                                                                    0x1
#define RLC_RLCV_SAFE_MODE__RESERVED1__SHIFT                                                                  0x5
#define RLC_RLCV_SAFE_MODE__RESPONSE__SHIFT                                                                   0x8
#define RLC_RLCV_SAFE_MODE__RESERVED__SHIFT                                                                   0xc
#define RLC_RLCV_SAFE_MODE__CMD_MASK                                                                          0x00000001L
#define RLC_RLCV_SAFE_MODE__MESSAGE_MASK                                                                      0x0000001EL
#define RLC_RLCV_SAFE_MODE__RESERVED1_MASK                                                                    0x000000E0L
#define RLC_RLCV_SAFE_MODE__RESPONSE_MASK                                                                     0x00000F00L
#define RLC_RLCV_SAFE_MODE__RESERVED_MASK                                                                     0xFFFFF000L
//RLC_SMU_SAFE_MODE
#define RLC_SMU_SAFE_MODE__CMD__SHIFT                                                                         0x0
#define RLC_SMU_SAFE_MODE__MESSAGE__SHIFT                                                                     0x1
#define RLC_SMU_SAFE_MODE__RESERVED1__SHIFT                                                                   0x5
#define RLC_SMU_SAFE_MODE__RESPONSE__SHIFT                                                                    0x8
#define RLC_SMU_SAFE_MODE__RESERVED__SHIFT                                                                    0xc
#define RLC_SMU_SAFE_MODE__CMD_MASK                                                                           0x00000001L
#define RLC_SMU_SAFE_MODE__MESSAGE_MASK                                                                       0x0000001EL
#define RLC_SMU_SAFE_MODE__RESERVED1_MASK                                                                     0x000000E0L
#define RLC_SMU_SAFE_MODE__RESPONSE_MASK                                                                      0x00000F00L
#define RLC_SMU_SAFE_MODE__RESERVED_MASK                                                                      0xFFFFF000L
//RLC_RLCV_COMMAND
#define RLC_RLCV_COMMAND__CMD__SHIFT                                                                          0x0
#define RLC_RLCV_COMMAND__RESERVED__SHIFT                                                                     0x4
#define RLC_RLCV_COMMAND__CMD_MASK                                                                            0x0000000FL
#define RLC_RLCV_COMMAND__RESERVED_MASK                                                                       0xFFFFFFF0L
//RLC_REFCLOCK_TIMESTAMP_LSB
#define RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB__SHIFT                                                      0x0
#define RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB_MASK                                                        0xFFFFFFFFL
//RLC_REFCLOCK_TIMESTAMP_MSB
#define RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB__SHIFT                                                      0x0
#define RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB_MASK                                                        0xFFFFFFFFL
//RLC_GPM_TIMER_INT_0
#define RLC_GPM_TIMER_INT_0__TIMER__SHIFT                                                                     0x0
#define RLC_GPM_TIMER_INT_0__TIMER_MASK                                                                       0xFFFFFFFFL
//RLC_GPM_TIMER_INT_1
#define RLC_GPM_TIMER_INT_1__TIMER__SHIFT                                                                     0x0
#define RLC_GPM_TIMER_INT_1__TIMER_MASK                                                                       0xFFFFFFFFL
//RLC_GPM_TIMER_INT_2
#define RLC_GPM_TIMER_INT_2__TIMER__SHIFT                                                                     0x0
#define RLC_GPM_TIMER_INT_2__TIMER_MASK                                                                       0xFFFFFFFFL
//RLC_GPM_TIMER_CTRL
#define RLC_GPM_TIMER_CTRL__TIMER_0_EN__SHIFT                                                                 0x0
#define RLC_GPM_TIMER_CTRL__TIMER_1_EN__SHIFT                                                                 0x1
#define RLC_GPM_TIMER_CTRL__TIMER_2_EN__SHIFT                                                                 0x2
#define RLC_GPM_TIMER_CTRL__TIMER_3_EN__SHIFT                                                                 0x3
#define RLC_GPM_TIMER_CTRL__TIMER_0_AUTO_REARM__SHIFT                                                         0x4
#define RLC_GPM_TIMER_CTRL__TIMER_1_AUTO_REARM__SHIFT                                                         0x5
#define RLC_GPM_TIMER_CTRL__TIMER_2_AUTO_REARM__SHIFT                                                         0x6
#define RLC_GPM_TIMER_CTRL__TIMER_3_AUTO_REARM__SHIFT                                                         0x7
#define RLC_GPM_TIMER_CTRL__TIMER_0_INT_CLEAR__SHIFT                                                          0x8
#define RLC_GPM_TIMER_CTRL__TIMER_1_INT_CLEAR__SHIFT                                                          0x9
#define RLC_GPM_TIMER_CTRL__TIMER_2_INT_CLEAR__SHIFT                                                          0xa
#define RLC_GPM_TIMER_CTRL__TIMER_3_INT_CLEAR__SHIFT                                                          0xb
#define RLC_GPM_TIMER_CTRL__TIMER_4_EN__SHIFT                                                                 0xc
#define RLC_GPM_TIMER_CTRL__TIMER_4_AUTO_REARM__SHIFT                                                         0xd
#define RLC_GPM_TIMER_CTRL__TIMER_4_INT_CLEAR__SHIFT                                                          0xe
#define RLC_GPM_TIMER_CTRL__RESERVED__SHIFT                                                                   0xf
#define RLC_GPM_TIMER_CTRL__TIMER_0_EN_MASK                                                                   0x00000001L
#define RLC_GPM_TIMER_CTRL__TIMER_1_EN_MASK                                                                   0x00000002L
#define RLC_GPM_TIMER_CTRL__TIMER_2_EN_MASK                                                                   0x00000004L
#define RLC_GPM_TIMER_CTRL__TIMER_3_EN_MASK                                                                   0x00000008L
#define RLC_GPM_TIMER_CTRL__TIMER_0_AUTO_REARM_MASK                                                           0x00000010L
#define RLC_GPM_TIMER_CTRL__TIMER_1_AUTO_REARM_MASK                                                           0x00000020L
#define RLC_GPM_TIMER_CTRL__TIMER_2_AUTO_REARM_MASK                                                           0x00000040L
#define RLC_GPM_TIMER_CTRL__TIMER_3_AUTO_REARM_MASK                                                           0x00000080L
#define RLC_GPM_TIMER_CTRL__TIMER_0_INT_CLEAR_MASK                                                            0x00000100L
#define RLC_GPM_TIMER_CTRL__TIMER_1_INT_CLEAR_MASK                                                            0x00000200L
#define RLC_GPM_TIMER_CTRL__TIMER_2_INT_CLEAR_MASK                                                            0x00000400L
#define RLC_GPM_TIMER_CTRL__TIMER_3_INT_CLEAR_MASK                                                            0x00000800L
#define RLC_GPM_TIMER_CTRL__TIMER_4_EN_MASK                                                                   0x00001000L
#define RLC_GPM_TIMER_CTRL__TIMER_4_AUTO_REARM_MASK                                                           0x00002000L
#define RLC_GPM_TIMER_CTRL__TIMER_4_INT_CLEAR_MASK                                                            0x00004000L
#define RLC_GPM_TIMER_CTRL__RESERVED_MASK                                                                     0xFFFF8000L
//RLC_LB_CNTR_MAX_1
#define RLC_LB_CNTR_MAX_1__LB_CNTR_MAX__SHIFT                                                                 0x0
#define RLC_LB_CNTR_MAX_1__LB_CNTR_MAX_MASK                                                                   0xFFFFFFFFL
//RLC_GPM_TIMER_STAT
#define RLC_GPM_TIMER_STAT__TIMER_0_STAT__SHIFT                                                               0x0
#define RLC_GPM_TIMER_STAT__TIMER_1_STAT__SHIFT                                                               0x1
#define RLC_GPM_TIMER_STAT__TIMER_2_STAT__SHIFT                                                               0x2
#define RLC_GPM_TIMER_STAT__TIMER_3_STAT__SHIFT                                                               0x3
#define RLC_GPM_TIMER_STAT__TIMER_4_STAT__SHIFT                                                               0x4
#define RLC_GPM_TIMER_STAT__TIMER_0_ENABLE_SYNC__SHIFT                                                        0x8
#define RLC_GPM_TIMER_STAT__TIMER_1_ENABLE_SYNC__SHIFT                                                        0x9
#define RLC_GPM_TIMER_STAT__TIMER_2_ENABLE_SYNC__SHIFT                                                        0xa
#define RLC_GPM_TIMER_STAT__TIMER_3_ENABLE_SYNC__SHIFT                                                        0xb
#define RLC_GPM_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC__SHIFT                                                    0xc
#define RLC_GPM_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC__SHIFT                                                    0xd
#define RLC_GPM_TIMER_STAT__TIMER_2_AUTO_REARM_SYNC__SHIFT                                                    0xe
#define RLC_GPM_TIMER_STAT__TIMER_3_AUTO_REARM_SYNC__SHIFT                                                    0xf
#define RLC_GPM_TIMER_STAT__TIMER_4_ENABLE_SYNC__SHIFT                                                        0x10
#define RLC_GPM_TIMER_STAT__TIMER_4_AUTO_REARM_SYNC__SHIFT                                                    0x11
#define RLC_GPM_TIMER_STAT__RESERVED__SHIFT                                                                   0x12
#define RLC_GPM_TIMER_STAT__TIMER_0_STAT_MASK                                                                 0x00000001L
#define RLC_GPM_TIMER_STAT__TIMER_1_STAT_MASK                                                                 0x00000002L
#define RLC_GPM_TIMER_STAT__TIMER_2_STAT_MASK                                                                 0x00000004L
#define RLC_GPM_TIMER_STAT__TIMER_3_STAT_MASK                                                                 0x00000008L
#define RLC_GPM_TIMER_STAT__TIMER_4_STAT_MASK                                                                 0x00000010L
#define RLC_GPM_TIMER_STAT__TIMER_0_ENABLE_SYNC_MASK                                                          0x00000100L
#define RLC_GPM_TIMER_STAT__TIMER_1_ENABLE_SYNC_MASK                                                          0x00000200L
#define RLC_GPM_TIMER_STAT__TIMER_2_ENABLE_SYNC_MASK                                                          0x00000400L
#define RLC_GPM_TIMER_STAT__TIMER_3_ENABLE_SYNC_MASK                                                          0x00000800L
#define RLC_GPM_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC_MASK                                                      0x00001000L
#define RLC_GPM_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC_MASK                                                      0x00002000L
#define RLC_GPM_TIMER_STAT__TIMER_2_AUTO_REARM_SYNC_MASK                                                      0x00004000L
#define RLC_GPM_TIMER_STAT__TIMER_3_AUTO_REARM_SYNC_MASK                                                      0x00008000L
#define RLC_GPM_TIMER_STAT__TIMER_4_ENABLE_SYNC_MASK                                                          0x00010000L
#define RLC_GPM_TIMER_STAT__TIMER_4_AUTO_REARM_SYNC_MASK                                                      0x00020000L
#define RLC_GPM_TIMER_STAT__RESERVED_MASK                                                                     0xFFFC0000L
//RLC_GPM_TIMER_INT_3
#define RLC_GPM_TIMER_INT_3__TIMER__SHIFT                                                                     0x0
#define RLC_GPM_TIMER_INT_3__TIMER_MASK                                                                       0xFFFFFFFFL
//RLC_GPM_LEGACY_INT_STAT
#define RLC_GPM_LEGACY_INT_STAT__SPP_PVT_INT_CHANGED__SHIFT                                                   0x0
#define RLC_GPM_LEGACY_INT_STAT__CP_RLC_STAT_INVAL_PEND_CHANGED__SHIFT                                        0x1
#define RLC_GPM_LEGACY_INT_STAT__RLC_EOF_INT_CHANGED__SHIFT                                                   0x2
#define RLC_GPM_LEGACY_INT_STAT__SPP_PVT_INT_CHANGED_MASK                                                     0x00000001L
#define RLC_GPM_LEGACY_INT_STAT__CP_RLC_STAT_INVAL_PEND_CHANGED_MASK                                          0x00000002L
#define RLC_GPM_LEGACY_INT_STAT__RLC_EOF_INT_CHANGED_MASK                                                     0x00000004L
//RLC_GPM_LEGACY_INT_CLEAR
#define RLC_GPM_LEGACY_INT_CLEAR__SPP_PVT_INT_CHANGED__SHIFT                                                  0x0
#define RLC_GPM_LEGACY_INT_CLEAR__CP_RLC_STAT_INVAL_PEND_CHANGED__SHIFT                                       0x1
#define RLC_GPM_LEGACY_INT_CLEAR__RLC_EOF_INT_CHANGED__SHIFT                                                  0x2
#define RLC_GPM_LEGACY_INT_CLEAR__SPP_PVT_INT_CHANGED_MASK                                                    0x00000001L
#define RLC_GPM_LEGACY_INT_CLEAR__CP_RLC_STAT_INVAL_PEND_CHANGED_MASK                                         0x00000002L
#define RLC_GPM_LEGACY_INT_CLEAR__RLC_EOF_INT_CHANGED_MASK                                                    0x00000004L
//RLC_INT_STAT
#define RLC_INT_STAT__LAST_CP_RLC_INT_ID__SHIFT                                                               0x0
#define RLC_INT_STAT__CP_RLC_INT_PENDING__SHIFT                                                               0x8
#define RLC_INT_STAT__RESERVED__SHIFT                                                                         0x9
#define RLC_INT_STAT__LAST_CP_RLC_INT_ID_MASK                                                                 0x000000FFL
#define RLC_INT_STAT__CP_RLC_INT_PENDING_MASK                                                                 0x00000100L
#define RLC_INT_STAT__RESERVED_MASK                                                                           0xFFFFFE00L
//RLC_LB_CNTL
#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE__SHIFT                                                               0x0
#define RLC_LB_CNTL__LB_CNT_CP_BUSY__SHIFT                                                                    0x1
#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE__SHIFT                                                                0x2
#define RLC_LB_CNTL__LB_CNT_REG_INC__SHIFT                                                                    0x3
#define RLC_LB_CNTL__RESERVED__SHIFT                                                                          0x4
#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK                                                                 0x00000001L
#define RLC_LB_CNTL__LB_CNT_CP_BUSY_MASK                                                                      0x00000002L
#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK                                                                  0x00000004L
#define RLC_LB_CNTL__LB_CNT_REG_INC_MASK                                                                      0x00000008L
#define RLC_LB_CNTL__RESERVED_MASK                                                                            0xFFFFFFF0L
//RLC_MGCG_CTRL
#define RLC_MGCG_CTRL__MGCG_EN__SHIFT                                                                         0x0
#define RLC_MGCG_CTRL__SILICON_EN__SHIFT                                                                      0x1
#define RLC_MGCG_CTRL__SIMULATION_EN__SHIFT                                                                   0x2
#define RLC_MGCG_CTRL__ON_DELAY__SHIFT                                                                        0x3
#define RLC_MGCG_CTRL__OFF_HYSTERESIS__SHIFT                                                                  0x7
#define RLC_MGCG_CTRL__GC_CAC_MGCG_CLK_CNTL__SHIFT                                                            0xf
#define RLC_MGCG_CTRL__SE_CAC_MGCG_CLK_CNTL__SHIFT                                                            0x10
#define RLC_MGCG_CTRL__SPARE__SHIFT                                                                           0x11
#define RLC_MGCG_CTRL__MGCG_EN_MASK                                                                           0x00000001L
#define RLC_MGCG_CTRL__SILICON_EN_MASK                                                                        0x00000002L
#define RLC_MGCG_CTRL__SIMULATION_EN_MASK                                                                     0x00000004L
#define RLC_MGCG_CTRL__ON_DELAY_MASK                                                                          0x00000078L
#define RLC_MGCG_CTRL__OFF_HYSTERESIS_MASK                                                                    0x00007F80L
#define RLC_MGCG_CTRL__GC_CAC_MGCG_CLK_CNTL_MASK                                                              0x00008000L
#define RLC_MGCG_CTRL__SE_CAC_MGCG_CLK_CNTL_MASK                                                              0x00010000L
#define RLC_MGCG_CTRL__SPARE_MASK                                                                             0xFFFE0000L
//RLC_LB_CNTR_INIT_1
#define RLC_LB_CNTR_INIT_1__LB_CNTR_INIT__SHIFT                                                               0x0
#define RLC_LB_CNTR_INIT_1__LB_CNTR_INIT_MASK                                                                 0xFFFFFFFFL
//RLC_LB_CNTR_1
#define RLC_LB_CNTR_1__RLC_LOAD_BALANCE_CNTR__SHIFT                                                           0x0
#define RLC_LB_CNTR_1__RLC_LOAD_BALANCE_CNTR_MASK                                                             0xFFFFFFFFL
//RLC_JUMP_TABLE_RESTORE
#define RLC_JUMP_TABLE_RESTORE__ADDR__SHIFT                                                                   0x0
#define RLC_JUMP_TABLE_RESTORE__ADDR_MASK                                                                     0xFFFFFFFFL
//RLC_PG_DELAY_2
#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE__SHIFT                                                           0x0
#define RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT                                                               0x8
#define RLC_PG_DELAY_2__PERWGP_TIMEOUT_VALUE__SHIFT                                                           0x10
#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE_MASK                                                             0x000000FFL
#define RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK                                                                 0x0000FF00L
#define RLC_PG_DELAY_2__PERWGP_TIMEOUT_VALUE_MASK                                                             0xFFFF0000L
//RLC_GPU_CLOCK_COUNT_LSB
#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB__SHIFT                                                        0x0
#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB_MASK                                                          0xFFFFFFFFL
//RLC_GPU_CLOCK_COUNT_MSB
#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB__SHIFT                                                        0x0
#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB_MASK                                                          0xFFFFFFFFL
//RLC_CAPTURE_GPU_CLOCK_COUNT
#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE__SHIFT                                                           0x0
#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED__SHIFT                                                          0x1
#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE_MASK                                                             0x00000001L
#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED_MASK                                                            0xFFFFFFFEL
//RLC_UCODE_CNTL
#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS__SHIFT                                                                0x0
#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS_MASK                                                                  0xFFFFFFFFL
//RLC_GPM_THREAD_RESET
#define RLC_GPM_THREAD_RESET__THREAD0_RESET__SHIFT                                                            0x0
#define RLC_GPM_THREAD_RESET__THREAD1_RESET__SHIFT                                                            0x1
#define RLC_GPM_THREAD_RESET__THREAD2_RESET__SHIFT                                                            0x2
#define RLC_GPM_THREAD_RESET__THREAD3_RESET__SHIFT                                                            0x3
#define RLC_GPM_THREAD_RESET__RESERVED__SHIFT                                                                 0x4
#define RLC_GPM_THREAD_RESET__THREAD0_RESET_MASK                                                              0x00000001L
#define RLC_GPM_THREAD_RESET__THREAD1_RESET_MASK                                                              0x00000002L
#define RLC_GPM_THREAD_RESET__THREAD2_RESET_MASK                                                              0x00000004L
#define RLC_GPM_THREAD_RESET__THREAD3_RESET_MASK                                                              0x00000008L
#define RLC_GPM_THREAD_RESET__RESERVED_MASK                                                                   0xFFFFFFF0L
//RLC_GPM_CP_DMA_COMPLETE_T0
#define RLC_GPM_CP_DMA_COMPLETE_T0__DATA__SHIFT                                                               0x0
#define RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED__SHIFT                                                           0x1
#define RLC_GPM_CP_DMA_COMPLETE_T0__DATA_MASK                                                                 0x00000001L
#define RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED_MASK                                                             0xFFFFFFFEL
//RLC_GPM_CP_DMA_COMPLETE_T1
#define RLC_GPM_CP_DMA_COMPLETE_T1__DATA__SHIFT                                                               0x0
#define RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED__SHIFT                                                           0x1
#define RLC_GPM_CP_DMA_COMPLETE_T1__DATA_MASK                                                                 0x00000001L
#define RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED_MASK                                                             0xFFFFFFFEL
//RLC_LB_CNTR_INIT_2
#define RLC_LB_CNTR_INIT_2__LB_CNTR_INIT__SHIFT                                                               0x0
#define RLC_LB_CNTR_INIT_2__LB_CNTR_INIT_MASK                                                                 0xFFFFFFFFL
//RLC_LB_CNTR_MAX_2
#define RLC_LB_CNTR_MAX_2__LB_CNTR_MAX__SHIFT                                                                 0x0
#define RLC_LB_CNTR_MAX_2__LB_CNTR_MAX_MASK                                                                   0xFFFFFFFFL
//RLC_LB_CONFIG_5
#define RLC_LB_CONFIG_5__DATA__SHIFT                                                                          0x0
#define RLC_LB_CONFIG_5__DATA_MASK                                                                            0xFFFFFFFFL
//RLC_GPM_TIMER_INT_4
#define RLC_GPM_TIMER_INT_4__TIMER__SHIFT                                                                     0x0
#define RLC_GPM_TIMER_INT_4__TIMER_MASK                                                                       0xFFFFFFFFL
//RLC_CLK_COUNT_GFXCLK_LSB
#define RLC_CLK_COUNT_GFXCLK_LSB__COUNTER__SHIFT                                                              0x0
#define RLC_CLK_COUNT_GFXCLK_LSB__COUNTER_MASK                                                                0xFFFFFFFFL
//RLC_CLK_COUNT_GFXCLK_MSB
#define RLC_CLK_COUNT_GFXCLK_MSB__COUNTER__SHIFT                                                              0x0
#define RLC_CLK_COUNT_GFXCLK_MSB__COUNTER_MASK                                                                0xFFFFFFFFL
//RLC_CLK_COUNT_REFCLK_LSB
#define RLC_CLK_COUNT_REFCLK_LSB__COUNTER__SHIFT                                                              0x0
#define RLC_CLK_COUNT_REFCLK_LSB__COUNTER_MASK                                                                0xFFFFFFFFL
//RLC_CLK_COUNT_REFCLK_MSB
#define RLC_CLK_COUNT_REFCLK_MSB__COUNTER__SHIFT                                                              0x0
#define RLC_CLK_COUNT_REFCLK_MSB__COUNTER_MASK                                                                0xFFFFFFFFL
//RLC_CLK_COUNT_CTRL
#define RLC_CLK_COUNT_CTRL__GFXCLK_RUN__SHIFT                                                                 0x0
#define RLC_CLK_COUNT_CTRL__GFXCLK_RESET__SHIFT                                                               0x1
#define RLC_CLK_COUNT_CTRL__GFXCLK_SAMPLE__SHIFT                                                              0x2
#define RLC_CLK_COUNT_CTRL__REFCLK_RUN__SHIFT                                                                 0x3
#define RLC_CLK_COUNT_CTRL__REFCLK_RESET__SHIFT                                                               0x4
#define RLC_CLK_COUNT_CTRL__REFCLK_SAMPLE__SHIFT                                                              0x5
#define RLC_CLK_COUNT_CTRL__GFXCLK_RUN_MASK                                                                   0x00000001L
#define RLC_CLK_COUNT_CTRL__GFXCLK_RESET_MASK                                                                 0x00000002L
#define RLC_CLK_COUNT_CTRL__GFXCLK_SAMPLE_MASK                                                                0x00000004L
#define RLC_CLK_COUNT_CTRL__REFCLK_RUN_MASK                                                                   0x00000008L
#define RLC_CLK_COUNT_CTRL__REFCLK_RESET_MASK                                                                 0x00000010L
#define RLC_CLK_COUNT_CTRL__REFCLK_SAMPLE_MASK                                                                0x00000020L
//RLC_CLK_COUNT_STAT
#define RLC_CLK_COUNT_STAT__GFXCLK_VALID__SHIFT                                                               0x0
#define RLC_CLK_COUNT_STAT__REFCLK_VALID__SHIFT                                                               0x1
#define RLC_CLK_COUNT_STAT__REFCLK_RUN_RESYNC__SHIFT                                                          0x2
#define RLC_CLK_COUNT_STAT__REFCLK_RESET_RESYNC__SHIFT                                                        0x3
#define RLC_CLK_COUNT_STAT__REFCLK_SAMPLE_RESYNC__SHIFT                                                       0x4
#define RLC_CLK_COUNT_STAT__RESERVED__SHIFT                                                                   0x5
#define RLC_CLK_COUNT_STAT__GFXCLK_VALID_MASK                                                                 0x00000001L
#define RLC_CLK_COUNT_STAT__REFCLK_VALID_MASK                                                                 0x00000002L
#define RLC_CLK_COUNT_STAT__REFCLK_RUN_RESYNC_MASK                                                            0x00000004L
#define RLC_CLK_COUNT_STAT__REFCLK_RESET_RESYNC_MASK                                                          0x00000008L
#define RLC_CLK_COUNT_STAT__REFCLK_SAMPLE_RESYNC_MASK                                                         0x00000010L
#define RLC_CLK_COUNT_STAT__RESERVED_MASK                                                                     0xFFFFFFE0L
//RLC_RLCG_DOORBELL_CNTL
#define RLC_RLCG_DOORBELL_CNTL__DOORBELL_0_MODE__SHIFT                                                        0x0
#define RLC_RLCG_DOORBELL_CNTL__DOORBELL_1_MODE__SHIFT                                                        0x2
#define RLC_RLCG_DOORBELL_CNTL__DOORBELL_2_MODE__SHIFT                                                        0x4
#define RLC_RLCG_DOORBELL_CNTL__DOORBELL_3_MODE__SHIFT                                                        0x6
#define RLC_RLCG_DOORBELL_CNTL__DOORBELL_ID__SHIFT                                                            0x10
#define RLC_RLCG_DOORBELL_CNTL__DOORBELL_ID_EN__SHIFT                                                         0x15
#define RLC_RLCG_DOORBELL_CNTL__DOORBELL_0_MODE_MASK                                                          0x00000003L
#define RLC_RLCG_DOORBELL_CNTL__DOORBELL_1_MODE_MASK                                                          0x0000000CL
#define RLC_RLCG_DOORBELL_CNTL__DOORBELL_2_MODE_MASK                                                          0x00000030L
#define RLC_RLCG_DOORBELL_CNTL__DOORBELL_3_MODE_MASK                                                          0x000000C0L
#define RLC_RLCG_DOORBELL_CNTL__DOORBELL_ID_MASK                                                              0x001F0000L
#define RLC_RLCG_DOORBELL_CNTL__DOORBELL_ID_EN_MASK                                                           0x00200000L
//RLC_RLCG_DOORBELL_STAT
#define RLC_RLCG_DOORBELL_STAT__DOORBELL_0_VALID__SHIFT                                                       0x0
#define RLC_RLCG_DOORBELL_STAT__DOORBELL_1_VALID__SHIFT                                                       0x1
#define RLC_RLCG_DOORBELL_STAT__DOORBELL_2_VALID__SHIFT                                                       0x2
#define RLC_RLCG_DOORBELL_STAT__DOORBELL_3_VALID__SHIFT                                                       0x3
#define RLC_RLCG_DOORBELL_STAT__DOORBELL_0_VALID_MASK                                                         0x00000001L
#define RLC_RLCG_DOORBELL_STAT__DOORBELL_1_VALID_MASK                                                         0x00000002L
#define RLC_RLCG_DOORBELL_STAT__DOORBELL_2_VALID_MASK                                                         0x00000004L
#define RLC_RLCG_DOORBELL_STAT__DOORBELL_3_VALID_MASK                                                         0x00000008L
//RLC_RLCG_DOORBELL_0_DATA_LO
#define RLC_RLCG_DOORBELL_0_DATA_LO__DATA__SHIFT                                                              0x0
#define RLC_RLCG_DOORBELL_0_DATA_LO__DATA_MASK                                                                0xFFFFFFFFL
//RLC_RLCG_DOORBELL_0_DATA_HI
#define RLC_RLCG_DOORBELL_0_DATA_HI__DATA__SHIFT                                                              0x0
#define RLC_RLCG_DOORBELL_0_DATA_HI__DATA_MASK                                                                0xFFFFFFFFL
//RLC_RLCG_DOORBELL_1_DATA_LO
#define RLC_RLCG_DOORBELL_1_DATA_LO__DATA__SHIFT                                                              0x0
#define RLC_RLCG_DOORBELL_1_DATA_LO__DATA_MASK                                                                0xFFFFFFFFL
//RLC_RLCG_DOORBELL_1_DATA_HI
#define RLC_RLCG_DOORBELL_1_DATA_HI__DATA__SHIFT                                                              0x0
#define RLC_RLCG_DOORBELL_1_DATA_HI__DATA_MASK                                                                0xFFFFFFFFL
//RLC_RLCG_DOORBELL_2_DATA_LO
#define RLC_RLCG_DOORBELL_2_DATA_LO__DATA__SHIFT                                                              0x0
#define RLC_RLCG_DOORBELL_2_DATA_LO__DATA_MASK                                                                0xFFFFFFFFL
//RLC_RLCG_DOORBELL_2_DATA_HI
#define RLC_RLCG_DOORBELL_2_DATA_HI__DATA__SHIFT                                                              0x0
#define RLC_RLCG_DOORBELL_2_DATA_HI__DATA_MASK                                                                0xFFFFFFFFL
//RLC_RLCG_DOORBELL_3_DATA_LO
#define RLC_RLCG_DOORBELL_3_DATA_LO__DATA__SHIFT                                                              0x0
#define RLC_RLCG_DOORBELL_3_DATA_LO__DATA_MASK                                                                0xFFFFFFFFL
//RLC_RLCG_DOORBELL_3_DATA_HI
#define RLC_RLCG_DOORBELL_3_DATA_HI__DATA__SHIFT                                                              0x0
#define RLC_RLCG_DOORBELL_3_DATA_HI__DATA_MASK                                                                0xFFFFFFFFL
//RLC_GPU_CLOCK_32_RES_SEL
#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT                                                              0x0
#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED__SHIFT                                                             0x6
#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK                                                                0x0000003FL
#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED_MASK                                                               0xFFFFFFC0L
//RLC_GPU_CLOCK_32
#define RLC_GPU_CLOCK_32__GPU_CLOCK_32__SHIFT                                                                 0x0
#define RLC_GPU_CLOCK_32__GPU_CLOCK_32_MASK                                                                   0xFFFFFFFFL
//RLC_PG_CNTL
#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE__SHIFT                                                           0x0
#define RLC_PG_CNTL__GFX_POWER_GATING_SRC__SHIFT                                                              0x1
#define RLC_PG_CNTL__DYN_PER_WGP_PG_ENABLE__SHIFT                                                             0x2
#define RLC_PG_CNTL__STATIC_PER_WGP_PG_ENABLE__SHIFT                                                          0x3
#define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE__SHIFT                                                            0x4
#define RLC_PG_CNTL__RESERVED__SHIFT                                                                          0x5
#define RLC_PG_CNTL__PG_OVERRIDE__SHIFT                                                                       0xe
#define RLC_PG_CNTL__CP_PG_DISABLE__SHIFT                                                                     0xf
#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE__SHIFT                                                             0x10
#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE__SHIFT                                                     0x11
#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE__SHIFT                                                     0x12
#define RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE__SHIFT                                                              0x13
#define RLC_PG_CNTL__RESERVED1__SHIFT                                                                         0x14
#define RLC_PG_CNTL__Ultra_Low_Voltage_Enable__SHIFT                                                          0x15
#define RLC_PG_CNTL__RESERVED2__SHIFT                                                                         0x16
#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK                                                             0x00000001L
#define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK                                                                0x00000002L
#define RLC_PG_CNTL__DYN_PER_WGP_PG_ENABLE_MASK                                                               0x00000004L
#define RLC_PG_CNTL__STATIC_PER_WGP_PG_ENABLE_MASK                                                            0x00000008L
#define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK                                                              0x00000010L
#define RLC_PG_CNTL__RESERVED_MASK                                                                            0x00003FE0L
#define RLC_PG_CNTL__PG_OVERRIDE_MASK                                                                         0x00004000L
#define RLC_PG_CNTL__CP_PG_DISABLE_MASK                                                                       0x00008000L
#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE_MASK                                                               0x00010000L
#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK                                                       0x00020000L
#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK                                                       0x00040000L
#define RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE_MASK                                                                0x00080000L
#define RLC_PG_CNTL__RESERVED1_MASK                                                                           0x00100000L
#define RLC_PG_CNTL__Ultra_Low_Voltage_Enable_MASK                                                            0x00200000L
#define RLC_PG_CNTL__RESERVED2_MASK                                                                           0x00C00000L
//RLC_GPM_THREAD_PRIORITY
#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY__SHIFT                                                      0x0
#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY__SHIFT                                                      0x8
#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY__SHIFT                                                      0x10
#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY__SHIFT                                                      0x18
#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY_MASK                                                        0x000000FFL
#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY_MASK                                                        0x0000FF00L
#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY_MASK                                                        0x00FF0000L
#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY_MASK                                                        0xFF000000L
//RLC_GPM_THREAD_ENABLE
#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE__SHIFT                                                          0x0
#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE__SHIFT                                                          0x1
#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE__SHIFT                                                          0x2
#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE__SHIFT                                                          0x3
#define RLC_GPM_THREAD_ENABLE__RESERVED__SHIFT                                                                0x4
#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE_MASK                                                            0x00000001L
#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE_MASK                                                            0x00000002L
#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE_MASK                                                            0x00000004L
#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE_MASK                                                            0x00000008L
#define RLC_GPM_THREAD_ENABLE__RESERVED_MASK                                                                  0xFFFFFFF0L
//RLC_RLCG_DOORBELL_RANGE
#define RLC_RLCG_DOORBELL_RANGE__LOWER_ADDR_RESERVED__SHIFT                                                   0x0
#define RLC_RLCG_DOORBELL_RANGE__LOWER_ADDR__SHIFT                                                            0x2
#define RLC_RLCG_DOORBELL_RANGE__UPPER_ADDR_RESERVED__SHIFT                                                   0x10
#define RLC_RLCG_DOORBELL_RANGE__UPPER_ADDR__SHIFT                                                            0x12
#define RLC_RLCG_DOORBELL_RANGE__LOWER_ADDR_RESERVED_MASK                                                     0x00000003L
#define RLC_RLCG_DOORBELL_RANGE__LOWER_ADDR_MASK                                                              0x00000FFCL
#define RLC_RLCG_DOORBELL_RANGE__UPPER_ADDR_RESERVED_MASK                                                     0x00030000L
#define RLC_RLCG_DOORBELL_RANGE__UPPER_ADDR_MASK                                                              0x0FFC0000L
//RLC_CGCG_CGLS_CTRL
#define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT                                                                    0x0
#define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT                                                                    0x1
#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT                                                   0x2
#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT                                                    0x8
#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER__SHIFT                                                            0x1b
#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL__SHIFT                                                              0x1c
#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE__SHIFT                                                                 0x1d
#define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN__SHIFT                                                             0x1f
#define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK                                                                      0x00000001L
#define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK                                                                      0x00000002L
#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK                                                     0x000000FCL
#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK                                                      0x07FFFF00L
#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER_MASK                                                              0x08000000L
#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK                                                                0x10000000L
#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE_MASK                                                                   0x60000000L
#define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN_MASK                                                               0x80000000L
//RLC_CGCG_RAMP_CTRL
#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT__SHIFT                                                        0x0
#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT__SHIFT                                                         0x4
#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT__SHIFT                                                          0x8
#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT__SHIFT                                                           0xc
#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT__SHIFT                                                             0x10
#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT__SHIFT                                                            0x1c
#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT_MASK                                                          0x0000000FL
#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT_MASK                                                           0x000000F0L
#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT_MASK                                                            0x00000F00L
#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT_MASK                                                             0x0000F000L
#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT_MASK                                                               0x0FFF0000L
#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT_MASK                                                              0xF0000000L
//RLC_DYN_PG_STATUS
#define RLC_DYN_PG_STATUS__PG_STATUS_WGP_MASK__SHIFT                                                          0x0
#define RLC_DYN_PG_STATUS__PG_STATUS_WGP_MASK_MASK                                                            0xFFFFFFFFL
//RLC_DYN_PG_REQUEST
#define RLC_DYN_PG_REQUEST__PG_REQUEST_WGP_MASK__SHIFT                                                        0x0
#define RLC_DYN_PG_REQUEST__PG_REQUEST_WGP_MASK_MASK                                                          0xFFFFFFFFL
//RLC_PG_DELAY
#define RLC_PG_DELAY__POWER_UP_DELAY__SHIFT                                                                   0x0
#define RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT                                                                 0x8
#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT                                                              0x10
#define RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT                                                                  0x18
#define RLC_PG_DELAY__POWER_UP_DELAY_MASK                                                                     0x000000FFL
#define RLC_PG_DELAY__POWER_DOWN_DELAY_MASK                                                                   0x0000FF00L
#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY_MASK                                                                0x00FF0000L
#define RLC_PG_DELAY__MEM_SLEEP_DELAY_MASK                                                                    0xFF000000L
//RLC_WGP_STATUS
#define RLC_WGP_STATUS__WORK_PENDING__SHIFT                                                                   0x0
#define RLC_WGP_STATUS__WORK_PENDING_MASK                                                                     0xFFFFFFFFL
//RLC_LB_INIT_WGP_MASK
#define RLC_LB_INIT_WGP_MASK__INIT_WGP_MASK__SHIFT                                                            0x0
#define RLC_LB_INIT_WGP_MASK__INIT_WGP_MASK_MASK                                                              0xFFFFFFFFL
//RLC_LB_ALWAYS_ACTIVE_WGP_MASK
#define RLC_LB_ALWAYS_ACTIVE_WGP_MASK__ALWAYS_ACTIVE_WGP_MASK__SHIFT                                          0x0
#define RLC_LB_ALWAYS_ACTIVE_WGP_MASK__ALWAYS_ACTIVE_WGP_MASK_MASK                                            0xFFFFFFFFL
//RLC_LB_PARAMS
#define RLC_LB_PARAMS__SKIP_L2_CHECK__SHIFT                                                                   0x0
#define RLC_LB_PARAMS__FIFO_SAMPLES__SHIFT                                                                    0x1
#define RLC_LB_PARAMS__PG_IDLE_SAMPLES__SHIFT                                                                 0x8
#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL__SHIFT                                                         0x10
#define RLC_LB_PARAMS__SKIP_L2_CHECK_MASK                                                                     0x00000001L
#define RLC_LB_PARAMS__FIFO_SAMPLES_MASK                                                                      0x000000FEL
#define RLC_LB_PARAMS__PG_IDLE_SAMPLES_MASK                                                                   0x0000FF00L
#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL_MASK                                                           0xFFFF0000L
//RLC_LB_DELAY
#define RLC_LB_DELAY__WGP_IDLE_DELAY__SHIFT                                                                   0x0
#define RLC_LB_DELAY__LBPW_INNER_LOOP_DELAY__SHIFT                                                            0x8
#define RLC_LB_DELAY__LBPW_OUTER_LOOP_DELAY__SHIFT                                                            0x10
#define RLC_LB_DELAY__SPARE__SHIFT                                                                            0x18
#define RLC_LB_DELAY__WGP_IDLE_DELAY_MASK                                                                     0x000000FFL
#define RLC_LB_DELAY__LBPW_INNER_LOOP_DELAY_MASK                                                              0x0000FF00L
#define RLC_LB_DELAY__LBPW_OUTER_LOOP_DELAY_MASK                                                              0x00FF0000L
#define RLC_LB_DELAY__SPARE_MASK                                                                              0xFF000000L
//RLC_PG_ALWAYS_ON_WGP_MASK
#define RLC_PG_ALWAYS_ON_WGP_MASK__AON_WGP_MASK__SHIFT                                                        0x0
#define RLC_PG_ALWAYS_ON_WGP_MASK__AON_WGP_MASK_MASK                                                          0xFFFFFFFFL
//RLC_MAX_PG_WGP
#define RLC_MAX_PG_WGP__MAX_POWERED_UP_WGP__SHIFT                                                             0x0
#define RLC_MAX_PG_WGP__SPARE__SHIFT                                                                          0x8
#define RLC_MAX_PG_WGP__MAX_POWERED_UP_WGP_MASK                                                               0x000000FFL
#define RLC_MAX_PG_WGP__SPARE_MASK                                                                            0xFFFFFF00L
//RLC_AUTO_PG_CTRL
#define RLC_AUTO_PG_CTRL__AUTO_PG_EN__SHIFT                                                                   0x0
#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN__SHIFT                                                0x1
#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN__SHIFT                                                              0x2
#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT                                             0x3
#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD__SHIFT                                             0x13
#define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK                                                                     0x00000001L
#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN_MASK                                                  0x00000002L
#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK                                                                0x00000004L
#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK                                               0x0007FFF8L
#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK                                               0xFFF80000L
//RLC_SMU_GRBM_REG_SAVE_CTRL
#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE__SHIFT                                                0x0
#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE__SHIFT                                                              0x1
#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE_MASK                                                  0x00000001L
#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE_MASK                                                                0xFFFFFFFEL
//RLC_SERDES_RD_INDEX
#define RLC_SERDES_RD_INDEX__DATA_REG_ID__SHIFT                                                               0x0
#define RLC_SERDES_RD_INDEX__SPARE__SHIFT                                                                     0x2
#define RLC_SERDES_RD_INDEX__DATA_REG_ID_MASK                                                                 0x00000003L
#define RLC_SERDES_RD_INDEX__SPARE_MASK                                                                       0xFFFFFFFCL
//RLC_SERDES_RD_DATA_0
#define RLC_SERDES_RD_DATA_0__DATA__SHIFT                                                                     0x0
#define RLC_SERDES_RD_DATA_0__DATA_MASK                                                                       0xFFFFFFFFL
//RLC_SERDES_RD_DATA_1
#define RLC_SERDES_RD_DATA_1__DATA__SHIFT                                                                     0x0
#define RLC_SERDES_RD_DATA_1__DATA_MASK                                                                       0xFFFFFFFFL
//RLC_SERDES_RD_DATA_2
#define RLC_SERDES_RD_DATA_2__DATA__SHIFT                                                                     0x0
#define RLC_SERDES_RD_DATA_2__DATA_MASK                                                                       0xFFFFFFFFL
//RLC_SERDES_RD_DATA_3
#define RLC_SERDES_RD_DATA_3__DATA__SHIFT                                                                     0x0
#define RLC_SERDES_RD_DATA_3__DATA_MASK                                                                       0xFFFFFFFFL
//RLC_SERDES_MASK
#define RLC_SERDES_MASK__GC_CENTER_HUB_0__SHIFT                                                               0x0
#define RLC_SERDES_MASK__GC_CENTER_HUB_1__SHIFT                                                               0x1
#define RLC_SERDES_MASK__RESERVED__SHIFT                                                                      0x2
#define RLC_SERDES_MASK__GC_SE_0__SHIFT                                                                       0x10
#define RLC_SERDES_MASK__GC_SE_1__SHIFT                                                                       0x11
#define RLC_SERDES_MASK__GC_SE_2__SHIFT                                                                       0x12
#define RLC_SERDES_MASK__GC_SE_3__SHIFT                                                                       0x13
#define RLC_SERDES_MASK__RESERVED_1__SHIFT                                                                    0x14
#define RLC_SERDES_MASK__GC_CENTER_HUB_0_MASK                                                                 0x00000001L
#define RLC_SERDES_MASK__GC_CENTER_HUB_1_MASK                                                                 0x00000002L
#define RLC_SERDES_MASK__RESERVED_MASK                                                                        0x0000FFFCL
#define RLC_SERDES_MASK__GC_SE_0_MASK                                                                         0x00010000L
#define RLC_SERDES_MASK__GC_SE_1_MASK                                                                         0x00020000L
#define RLC_SERDES_MASK__GC_SE_2_MASK                                                                         0x00040000L
#define RLC_SERDES_MASK__GC_SE_3_MASK                                                                         0x00080000L
#define RLC_SERDES_MASK__RESERVED_1_MASK                                                                      0xFFF00000L
//RLC_SERDES_CTRL
#define RLC_SERDES_CTRL__BPM_BROADCAST__SHIFT                                                                 0x0
#define RLC_SERDES_CTRL__BPM_REG_WRITE__SHIFT                                                                 0x1
#define RLC_SERDES_CTRL__BPM_LONG_CMD__SHIFT                                                                  0x2
#define RLC_SERDES_CTRL__BPM_ADDR__SHIFT                                                                      0x3
#define RLC_SERDES_CTRL__REG_ADDR__SHIFT                                                                      0x10
#define RLC_SERDES_CTRL__BPM_BROADCAST_MASK                                                                   0x000001L
#define RLC_SERDES_CTRL__BPM_REG_WRITE_MASK                                                                   0x000002L
#define RLC_SERDES_CTRL__BPM_LONG_CMD_MASK                                                                    0x000004L
#define RLC_SERDES_CTRL__BPM_ADDR_MASK                                                                        0x00FFF8L
#define RLC_SERDES_CTRL__REG_ADDR_MASK                                                                        0xFF0000L
//RLC_SERDES_DATA
#define RLC_SERDES_DATA__DATA__SHIFT                                                                          0x0
#define RLC_SERDES_DATA__DATA_MASK                                                                            0xFFFFFFFFL
//RLC_SERDES_BUSY
#define RLC_SERDES_BUSY__GC_CENTER_HUB_0__SHIFT                                                               0x0
#define RLC_SERDES_BUSY__GC_CENTER_HUB_1__SHIFT                                                               0x1
#define RLC_SERDES_BUSY__RESERVED__SHIFT                                                                      0x2
#define RLC_SERDES_BUSY__GC_SE_0__SHIFT                                                                       0x10
#define RLC_SERDES_BUSY__GC_SE_1__SHIFT                                                                       0x11
#define RLC_SERDES_BUSY__GC_SE_2__SHIFT                                                                       0x12
#define RLC_SERDES_BUSY__GC_SE_3__SHIFT                                                                       0x13
#define RLC_SERDES_BUSY__RESERVED_29_20__SHIFT                                                                0x14
#define RLC_SERDES_BUSY__RD_FIFO_NOT_EMPTY__SHIFT                                                             0x1e
#define RLC_SERDES_BUSY__RD_PENDING__SHIFT                                                                    0x1f
#define RLC_SERDES_BUSY__GC_CENTER_HUB_0_MASK                                                                 0x00000001L
#define RLC_SERDES_BUSY__GC_CENTER_HUB_1_MASK                                                                 0x00000002L
#define RLC_SERDES_BUSY__RESERVED_MASK                                                                        0x0000FFFCL
#define RLC_SERDES_BUSY__GC_SE_0_MASK                                                                         0x00010000L
#define RLC_SERDES_BUSY__GC_SE_1_MASK                                                                         0x00020000L
#define RLC_SERDES_BUSY__GC_SE_2_MASK                                                                         0x00040000L
#define RLC_SERDES_BUSY__GC_SE_3_MASK                                                                         0x00080000L
#define RLC_SERDES_BUSY__RESERVED_29_20_MASK                                                                  0x3FF00000L
#define RLC_SERDES_BUSY__RD_FIFO_NOT_EMPTY_MASK                                                               0x40000000L
#define RLC_SERDES_BUSY__RD_PENDING_MASK                                                                      0x80000000L
//RLC_GPM_GENERAL_0
#define RLC_GPM_GENERAL_0__DATA__SHIFT                                                                        0x0
#define RLC_GPM_GENERAL_0__DATA_MASK                                                                          0xFFFFFFFFL
//RLC_GPM_GENERAL_1
#define RLC_GPM_GENERAL_1__DATA__SHIFT                                                                        0x0
#define RLC_GPM_GENERAL_1__DATA_MASK                                                                          0xFFFFFFFFL
//RLC_GPM_GENERAL_2
#define RLC_GPM_GENERAL_2__DATA__SHIFT                                                                        0x0
#define RLC_GPM_GENERAL_2__DATA_MASK                                                                          0xFFFFFFFFL
//RLC_GPM_GENERAL_3
#define RLC_GPM_GENERAL_3__DATA__SHIFT                                                                        0x0
#define RLC_GPM_GENERAL_3__DATA_MASK                                                                          0xFFFFFFFFL
//RLC_GPM_GENERAL_4
#define RLC_GPM_GENERAL_4__DATA__SHIFT                                                                        0x0
#define RLC_GPM_GENERAL_4__DATA_MASK                                                                          0xFFFFFFFFL
//RLC_GPM_GENERAL_5
#define RLC_GPM_GENERAL_5__DATA__SHIFT                                                                        0x0
#define RLC_GPM_GENERAL_5__DATA_MASK                                                                          0xFFFFFFFFL
//RLC_GPM_GENERAL_6
#define RLC_GPM_GENERAL_6__DATA__SHIFT                                                                        0x0
#define RLC_GPM_GENERAL_6__DATA_MASK                                                                          0xFFFFFFFFL
//RLC_GPM_GENERAL_7
#define RLC_GPM_GENERAL_7__DATA__SHIFT                                                                        0x0
#define RLC_GPM_GENERAL_7__DATA_MASK                                                                          0xFFFFFFFFL
//RLC_STATIC_PG_STATUS
#define RLC_STATIC_PG_STATUS__PG_STATUS_WGP_MASK__SHIFT                                                       0x0
#define RLC_STATIC_PG_STATUS__PG_STATUS_WGP_MASK_MASK                                                         0xFFFFFFFFL
//RLC_SPM_INT_INFO_1
#define RLC_SPM_INT_INFO_1__INTERRUPT_INFO_1__SHIFT                                                           0x0
#define RLC_SPM_INT_INFO_1__INTERRUPT_INFO_1_MASK                                                             0xFFFFFFFFL
//RLC_SPM_INT_INFO_2
#define RLC_SPM_INT_INFO_2__INTERRUPT_INFO_2__SHIFT                                                           0x0
#define RLC_SPM_INT_INFO_2__INTERRUPT_ID__SHIFT                                                               0x10
#define RLC_SPM_INT_INFO_2__RESERVED__SHIFT                                                                   0x18
#define RLC_SPM_INT_INFO_2__INTERRUPT_INFO_2_MASK                                                             0x0000FFFFL
#define RLC_SPM_INT_INFO_2__INTERRUPT_ID_MASK                                                                 0x00FF0000L
#define RLC_SPM_INT_INFO_2__RESERVED_MASK                                                                     0xFF000000L
//RLC_SPM_MC_CNTL
#define RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT                                                                  0x0
#define RLC_SPM_MC_CNTL__RLC_SPM_POLICY__SHIFT                                                                0x4
#define RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR__SHIFT                                                             0x6
#define RLC_SPM_MC_CNTL__RLC_SPM_FED__SHIFT                                                                   0x7
#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER__SHIFT                                                            0x8
#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE__SHIFT                                                                 0x9
#define RLC_SPM_MC_CNTL__RLC_SPM_BC__SHIFT                                                                    0xc
#define RLC_SPM_MC_CNTL__RLC_SPM_RO__SHIFT                                                                    0xd
#define RLC_SPM_MC_CNTL__RLC_SPM_VOL__SHIFT                                                                   0xe
#define RLC_SPM_MC_CNTL__RLC_SPM_NOFILL__SHIFT                                                                0xf
#define RLC_SPM_MC_CNTL__RESERVED_3__SHIFT                                                                    0x10
#define RLC_SPM_MC_CNTL__RESERVED__SHIFT                                                                      0x14
#define RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK                                                                    0x0000000FL
#define RLC_SPM_MC_CNTL__RLC_SPM_POLICY_MASK                                                                  0x00000030L
#define RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR_MASK                                                               0x00000040L
#define RLC_SPM_MC_CNTL__RLC_SPM_FED_MASK                                                                     0x00000080L
#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER_MASK                                                              0x00000100L
#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_MASK                                                                   0x00000E00L
#define RLC_SPM_MC_CNTL__RLC_SPM_BC_MASK                                                                      0x00001000L
#define RLC_SPM_MC_CNTL__RLC_SPM_RO_MASK                                                                      0x00002000L
#define RLC_SPM_MC_CNTL__RLC_SPM_VOL_MASK                                                                     0x00004000L
#define RLC_SPM_MC_CNTL__RLC_SPM_NOFILL_MASK                                                                  0x00008000L
#define RLC_SPM_MC_CNTL__RESERVED_3_MASK                                                                      0x00030000L
#define RLC_SPM_MC_CNTL__RESERVED_MASK                                                                        0xFFF00000L
//RLC_SPM_INT_CNTL
#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL__SHIFT                                                             0x0
#define RLC_SPM_INT_CNTL__RESERVED__SHIFT                                                                     0x1
#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL_MASK                                                               0x00000001L
#define RLC_SPM_INT_CNTL__RESERVED_MASK                                                                       0xFFFFFFFEL
//RLC_SPM_INT_STATUS
#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS__SHIFT                                                         0x0
#define RLC_SPM_INT_STATUS__RESERVED__SHIFT                                                                   0x1
#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS_MASK                                                           0x00000001L
#define RLC_SPM_INT_STATUS__RESERVED_MASK                                                                     0xFFFFFFFEL
//RLC_SMU_MESSAGE
#define RLC_SMU_MESSAGE__CMD__SHIFT                                                                           0x0
#define RLC_SMU_MESSAGE__CMD_MASK                                                                             0xFFFFFFFFL
//RLC_GPM_LOG_SIZE
#define RLC_GPM_LOG_SIZE__SIZE__SHIFT                                                                         0x0
#define RLC_GPM_LOG_SIZE__SIZE_MASK                                                                           0xFFFFFFFFL
//RLC_PG_DELAY_3
#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT                                                        0x0
#define RLC_PG_DELAY_3__RESERVED__SHIFT                                                                       0x8
#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK                                                          0x000000FFL
#define RLC_PG_DELAY_3__RESERVED_MASK                                                                         0xFFFFFF00L
//RLC_GPR_REG1
#define RLC_GPR_REG1__DATA__SHIFT                                                                             0x0
#define RLC_GPR_REG1__DATA_MASK                                                                               0xFFFFFFFFL
//RLC_GPR_REG2
#define RLC_GPR_REG2__DATA__SHIFT                                                                             0x0
#define RLC_GPR_REG2__DATA_MASK                                                                               0xFFFFFFFFL
//RLC_GPM_LOG_CONT
#define RLC_GPM_LOG_CONT__CONT__SHIFT                                                                         0x0
#define RLC_GPM_LOG_CONT__CONT_MASK                                                                           0xFFFFFFFFL
//RLC_GPM_INT_DISABLE_TH0
#define RLC_GPM_INT_DISABLE_TH0__DISABLE_INT__SHIFT                                                           0x0
#define RLC_GPM_INT_DISABLE_TH0__DISABLE_INT_MASK                                                             0xFFFFFFFFL
//RLC_GPM_LEGACY_INT_DISABLE
#define RLC_GPM_LEGACY_INT_DISABLE__SPP_PVT_INT_CHANGED__SHIFT                                                0x0
#define RLC_GPM_LEGACY_INT_DISABLE__CP_RLC_STAT_INVAL_PEND_CHANGED__SHIFT                                     0x1
#define RLC_GPM_LEGACY_INT_DISABLE__RLC_EOF_INT_CHANGED__SHIFT                                                0x2
#define RLC_GPM_LEGACY_INT_DISABLE__SPP_PVT_INT_CHANGED_MASK                                                  0x00000001L
#define RLC_GPM_LEGACY_INT_DISABLE__CP_RLC_STAT_INVAL_PEND_CHANGED_MASK                                       0x00000002L
#define RLC_GPM_LEGACY_INT_DISABLE__RLC_EOF_INT_CHANGED_MASK                                                  0x00000004L
//RLC_GPM_INT_FORCE_TH0
#define RLC_GPM_INT_FORCE_TH0__FORCE_INT__SHIFT                                                               0x0
#define RLC_GPM_INT_FORCE_TH0__FORCE_INT_MASK                                                                 0xFFFFFFFFL
//RLC_SRM_CNTL
#define RLC_SRM_CNTL__SRM_ENABLE__SHIFT                                                                       0x0
#define RLC_SRM_CNTL__AUTO_INCR_ADDR__SHIFT                                                                   0x1
#define RLC_SRM_CNTL__RESERVED__SHIFT                                                                         0x2
#define RLC_SRM_CNTL__SRM_ENABLE_MASK                                                                         0x00000001L
#define RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK                                                                     0x00000002L
#define RLC_SRM_CNTL__RESERVED_MASK                                                                           0xFFFFFFFCL
//RLC_SRM_GPM_COMMAND
#define RLC_SRM_GPM_COMMAND__OP__SHIFT                                                                        0x0
#define RLC_SRM_GPM_COMMAND__INDEX_CNTL__SHIFT                                                                0x1
#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM__SHIFT                                                            0x2
#define RLC_SRM_GPM_COMMAND__SIZE__SHIFT                                                                      0x5
#define RLC_SRM_GPM_COMMAND__START_OFFSET__SHIFT                                                              0x11
#define RLC_SRM_GPM_COMMAND__RESERVED1__SHIFT                                                                 0x1d
#define RLC_SRM_GPM_COMMAND__DEST_MEMORY__SHIFT                                                               0x1f
#define RLC_SRM_GPM_COMMAND__OP_MASK                                                                          0x00000001L
#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_MASK                                                                  0x00000002L
#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM_MASK                                                              0x0000001CL
#define RLC_SRM_GPM_COMMAND__SIZE_MASK                                                                        0x0001FFE0L
#define RLC_SRM_GPM_COMMAND__START_OFFSET_MASK                                                                0x1FFE0000L
#define RLC_SRM_GPM_COMMAND__RESERVED1_MASK                                                                   0x60000000L
#define RLC_SRM_GPM_COMMAND__DEST_MEMORY_MASK                                                                 0x80000000L
//RLC_SRM_GPM_COMMAND_STATUS
#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY__SHIFT                                                         0x0
#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL__SHIFT                                                          0x1
#define RLC_SRM_GPM_COMMAND_STATUS__RESERVED__SHIFT                                                           0x2
#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY_MASK                                                           0x00000001L
#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL_MASK                                                            0x00000002L
#define RLC_SRM_GPM_COMMAND_STATUS__RESERVED_MASK                                                             0xFFFFFFFCL
//RLC_SRM_RLCV_COMMAND
#define RLC_SRM_RLCV_COMMAND__OP__SHIFT                                                                       0x0
#define RLC_SRM_RLCV_COMMAND__RESERVED__SHIFT                                                                 0x1
#define RLC_SRM_RLCV_COMMAND__SIZE__SHIFT                                                                     0x4
#define RLC_SRM_RLCV_COMMAND__START_OFFSET__SHIFT                                                             0x10
#define RLC_SRM_RLCV_COMMAND__RESERVED1__SHIFT                                                                0x1c
#define RLC_SRM_RLCV_COMMAND__DEST_MEMORY__SHIFT                                                              0x1f
#define RLC_SRM_RLCV_COMMAND__OP_MASK                                                                         0x00000001L
#define RLC_SRM_RLCV_COMMAND__RESERVED_MASK                                                                   0x0000000EL
#define RLC_SRM_RLCV_COMMAND__SIZE_MASK                                                                       0x0000FFF0L
#define RLC_SRM_RLCV_COMMAND__START_OFFSET_MASK                                                               0x0FFF0000L
#define RLC_SRM_RLCV_COMMAND__RESERVED1_MASK                                                                  0x70000000L
#define RLC_SRM_RLCV_COMMAND__DEST_MEMORY_MASK                                                                0x80000000L
//RLC_SRM_RLCV_COMMAND_STATUS
#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY__SHIFT                                                        0x0
#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL__SHIFT                                                         0x1
#define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED__SHIFT                                                          0x2
#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY_MASK                                                          0x00000001L
#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL_MASK                                                           0x00000002L
#define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED_MASK                                                            0xFFFFFFFCL
//RLC_SRM_INDEX_CNTL_ADDR_0
#define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS__SHIFT                                                             0x0
#define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED__SHIFT                                                            0x10
#define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS_MASK                                                               0x0000FFFFL
#define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED_MASK                                                              0xFFFF0000L
//RLC_SRM_INDEX_CNTL_ADDR_1
#define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS__SHIFT                                                             0x0
#define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED__SHIFT                                                            0x10
#define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS_MASK                                                               0x0000FFFFL
#define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED_MASK                                                              0xFFFF0000L
//RLC_SRM_INDEX_CNTL_ADDR_2
#define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS__SHIFT                                                             0x0
#define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED__SHIFT                                                            0x10
#define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS_MASK                                                               0x0000FFFFL
#define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED_MASK                                                              0xFFFF0000L
//RLC_SRM_INDEX_CNTL_ADDR_3
#define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS__SHIFT                                                             0x0
#define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED__SHIFT                                                            0x10
#define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS_MASK                                                               0x0000FFFFL
#define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED_MASK                                                              0xFFFF0000L
//RLC_SRM_INDEX_CNTL_ADDR_4
#define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS__SHIFT                                                             0x0
#define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED__SHIFT                                                            0x10
#define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS_MASK                                                               0x0000FFFFL
#define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED_MASK                                                              0xFFFF0000L
//RLC_SRM_INDEX_CNTL_ADDR_5
#define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS__SHIFT                                                             0x0
#define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED__SHIFT                                                            0x10
#define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS_MASK                                                               0x0000FFFFL
#define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED_MASK                                                              0xFFFF0000L
//RLC_SRM_INDEX_CNTL_ADDR_6
#define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS__SHIFT                                                             0x0
#define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED__SHIFT                                                            0x10
#define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS_MASK                                                               0x0000FFFFL
#define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED_MASK                                                              0xFFFF0000L
//RLC_SRM_INDEX_CNTL_ADDR_7
#define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS__SHIFT                                                             0x0
#define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED__SHIFT                                                            0x10
#define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS_MASK                                                               0x0000FFFFL
#define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED_MASK                                                              0xFFFF0000L
//RLC_SRM_INDEX_CNTL_DATA_0
#define RLC_SRM_INDEX_CNTL_DATA_0__DATA__SHIFT                                                                0x0
#define RLC_SRM_INDEX_CNTL_DATA_0__DATA_MASK                                                                  0xFFFFFFFFL
//RLC_SRM_INDEX_CNTL_DATA_1
#define RLC_SRM_INDEX_CNTL_DATA_1__DATA__SHIFT                                                                0x0
#define RLC_SRM_INDEX_CNTL_DATA_1__DATA_MASK                                                                  0xFFFFFFFFL
//RLC_SRM_INDEX_CNTL_DATA_2
#define RLC_SRM_INDEX_CNTL_DATA_2__DATA__SHIFT                                                                0x0
#define RLC_SRM_INDEX_CNTL_DATA_2__DATA_MASK                                                                  0xFFFFFFFFL
//RLC_SRM_INDEX_CNTL_DATA_3
#define RLC_SRM_INDEX_CNTL_DATA_3__DATA__SHIFT                                                                0x0
#define RLC_SRM_INDEX_CNTL_DATA_3__DATA_MASK                                                                  0xFFFFFFFFL
//RLC_SRM_INDEX_CNTL_DATA_4
#define RLC_SRM_INDEX_CNTL_DATA_4__DATA__SHIFT                                                                0x0
#define RLC_SRM_INDEX_CNTL_DATA_4__DATA_MASK                                                                  0xFFFFFFFFL
//RLC_SRM_INDEX_CNTL_DATA_5
#define RLC_SRM_INDEX_CNTL_DATA_5__DATA__SHIFT                                                                0x0
#define RLC_SRM_INDEX_CNTL_DATA_5__DATA_MASK                                                                  0xFFFFFFFFL
//RLC_SRM_INDEX_CNTL_DATA_6
#define RLC_SRM_INDEX_CNTL_DATA_6__DATA__SHIFT                                                                0x0
#define RLC_SRM_INDEX_CNTL_DATA_6__DATA_MASK                                                                  0xFFFFFFFFL
//RLC_SRM_INDEX_CNTL_DATA_7
#define RLC_SRM_INDEX_CNTL_DATA_7__DATA__SHIFT                                                                0x0
#define RLC_SRM_INDEX_CNTL_DATA_7__DATA_MASK                                                                  0xFFFFFFFFL
//RLC_SRM_STAT
#define RLC_SRM_STAT__SRM_BUSY__SHIFT                                                                         0x0
#define RLC_SRM_STAT__SRM_BUSY_DELAY__SHIFT                                                                   0x1
#define RLC_SRM_STAT__RESERVED__SHIFT                                                                         0x2
#define RLC_SRM_STAT__SRM_BUSY_MASK                                                                           0x00000001L
#define RLC_SRM_STAT__SRM_BUSY_DELAY_MASK                                                                     0x00000002L
#define RLC_SRM_STAT__RESERVED_MASK                                                                           0xFFFFFFFCL
//RLC_SRM_GPM_ABORT
#define RLC_SRM_GPM_ABORT__ABORT__SHIFT                                                                       0x0
#define RLC_SRM_GPM_ABORT__RESERVED__SHIFT                                                                    0x1
#define RLC_SRM_GPM_ABORT__ABORT_MASK                                                                         0x00000001L
#define RLC_SRM_GPM_ABORT__RESERVED_MASK                                                                      0xFFFFFFFEL
//RLC_SPARE_INT_2
#define RLC_SPARE_INT_2__DATA__SHIFT                                                                          0x0
#define RLC_SPARE_INT_2__PROCESSING__SHIFT                                                                    0x1e
#define RLC_SPARE_INT_2__COMPLETE__SHIFT                                                                      0x1f
#define RLC_SPARE_INT_2__DATA_MASK                                                                            0x3FFFFFFFL
#define RLC_SPARE_INT_2__PROCESSING_MASK                                                                      0x40000000L
#define RLC_SPARE_INT_2__COMPLETE_MASK                                                                        0x80000000L
//RLC_RLCV_SPARE_INT_1
#define RLC_RLCV_SPARE_INT_1__INTERRUPT__SHIFT                                                                0x0
#define RLC_RLCV_SPARE_INT_1__RESERVED__SHIFT                                                                 0x1
#define RLC_RLCV_SPARE_INT_1__INTERRUPT_MASK                                                                  0x00000001L
#define RLC_RLCV_SPARE_INT_1__RESERVED_MASK                                                                   0xFFFFFFFEL
//RLC_PACE_SPARE_INT_1
#define RLC_PACE_SPARE_INT_1__INTERRUPT__SHIFT                                                                0x0
#define RLC_PACE_SPARE_INT_1__RESERVED__SHIFT                                                                 0x1
#define RLC_PACE_SPARE_INT_1__INTERRUPT_MASK                                                                  0x00000001L
#define RLC_PACE_SPARE_INT_1__RESERVED_MASK                                                                   0xFFFFFFFEL
//RLC_SAFE_MODE
#define RLC_SAFE_MODE__CMD__SHIFT                                                                             0x0
#define RLC_SAFE_MODE__MESSAGE__SHIFT                                                                         0x1
#define RLC_SAFE_MODE__RESERVED1__SHIFT                                                                       0x5
#define RLC_SAFE_MODE__RESPONSE__SHIFT                                                                        0x8
#define RLC_SAFE_MODE__RESERVED__SHIFT                                                                        0xc
#define RLC_SAFE_MODE__CMD_MASK                                                                               0x00000001L
#define RLC_SAFE_MODE__MESSAGE_MASK                                                                           0x0000001EL
#define RLC_SAFE_MODE__RESERVED1_MASK                                                                         0x000000E0L
#define RLC_SAFE_MODE__RESPONSE_MASK                                                                          0x00000F00L
#define RLC_SAFE_MODE__RESERVED_MASK                                                                          0xFFFFF000L
//RLC_CP_SCHEDULERS
#define RLC_CP_SCHEDULERS__scheduler0__SHIFT                                                                  0x0
#define RLC_CP_SCHEDULERS__scheduler1__SHIFT                                                                  0x8
#define RLC_CP_SCHEDULERS__scheduler2__SHIFT                                                                  0x10
#define RLC_CP_SCHEDULERS__scheduler3__SHIFT                                                                  0x18
#define RLC_CP_SCHEDULERS__scheduler0_MASK                                                                    0x000000FFL
#define RLC_CP_SCHEDULERS__scheduler1_MASK                                                                    0x0000FF00L
#define RLC_CP_SCHEDULERS__scheduler2_MASK                                                                    0x00FF0000L
#define RLC_CP_SCHEDULERS__scheduler3_MASK                                                                    0xFF000000L
//RLC_CSIB_ADDR_LO
#define RLC_CSIB_ADDR_LO__ADDRESS__SHIFT                                                                      0x0
#define RLC_CSIB_ADDR_LO__ADDRESS_MASK                                                                        0xFFFFFFFFL
//RLC_CSIB_ADDR_HI
#define RLC_CSIB_ADDR_HI__ADDRESS__SHIFT                                                                      0x0
#define RLC_CSIB_ADDR_HI__ADDRESS_MASK                                                                        0x0000FFFFL
//RLC_CSIB_LENGTH
#define RLC_CSIB_LENGTH__LENGTH__SHIFT                                                                        0x0
#define RLC_CSIB_LENGTH__LENGTH_MASK                                                                          0xFFFFFFFFL
//RLC_SPARE_INT_0
#define RLC_SPARE_INT_0__DATA__SHIFT                                                                          0x0
#define RLC_SPARE_INT_0__PROCESSING__SHIFT                                                                    0x1e
#define RLC_SPARE_INT_0__COMPLETE__SHIFT                                                                      0x1f
#define RLC_SPARE_INT_0__DATA_MASK                                                                            0x3FFFFFFFL
#define RLC_SPARE_INT_0__PROCESSING_MASK                                                                      0x40000000L
#define RLC_SPARE_INT_0__COMPLETE_MASK                                                                        0x80000000L
//RLC_CP_EOF_INT_CNT
#define RLC_CP_EOF_INT_CNT__CNT__SHIFT                                                                        0x0
#define RLC_CP_EOF_INT_CNT__CNT_MASK                                                                          0xFFFFFFFFL
//RLC_CP_EOF_INT
#define RLC_CP_EOF_INT__INTERRUPT__SHIFT                                                                      0x0
#define RLC_CP_EOF_INT__RESERVED__SHIFT                                                                       0x1
#define RLC_CP_EOF_INT__INTERRUPT_MASK                                                                        0x00000001L
#define RLC_CP_EOF_INT__RESERVED_MASK                                                                         0xFFFFFFFEL
//RLC_SMU_COMMAND
#define RLC_SMU_COMMAND__CMD__SHIFT                                                                           0x0
#define RLC_SMU_COMMAND__CMD_MASK                                                                             0xFFFFFFFFL
//RLC_SMU_ARGUMENT_1
#define RLC_SMU_ARGUMENT_1__ARG__SHIFT                                                                        0x0
#define RLC_SMU_ARGUMENT_1__ARG_MASK                                                                          0xFFFFFFFFL
//RLC_SMU_ARGUMENT_2
#define RLC_SMU_ARGUMENT_2__ARG__SHIFT                                                                        0x0
#define RLC_SMU_ARGUMENT_2__ARG_MASK                                                                          0xFFFFFFFFL
//RLC_GPM_GENERAL_8
#define RLC_GPM_GENERAL_8__DATA__SHIFT                                                                        0x0
#define RLC_GPM_GENERAL_8__DATA_MASK                                                                          0xFFFFFFFFL
//RLC_GPM_GENERAL_9
#define RLC_GPM_GENERAL_9__DATA__SHIFT                                                                        0x0
#define RLC_GPM_GENERAL_9__DATA_MASK                                                                          0xFFFFFFFFL
//RLC_GPM_GENERAL_10
#define RLC_GPM_GENERAL_10__DATA__SHIFT                                                                       0x0
#define RLC_GPM_GENERAL_10__DATA_MASK                                                                         0xFFFFFFFFL
//RLC_GPM_GENERAL_11
#define RLC_GPM_GENERAL_11__DATA__SHIFT                                                                       0x0
#define RLC_GPM_GENERAL_11__DATA_MASK                                                                         0xFFFFFFFFL
//RLC_GPM_GENERAL_12
#define RLC_GPM_GENERAL_12__DATA__SHIFT                                                                       0x0
#define RLC_GPM_GENERAL_12__DATA_MASK                                                                         0xFFFFFFFFL
//RLC_GPM_UTCL1_CNTL_0
#define RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT__SHIFT                                                     0x0
#define RLC_GPM_UTCL1_CNTL_0__DROP_MODE__SHIFT                                                                0x18
#define RLC_GPM_UTCL1_CNTL_0__BYPASS__SHIFT                                                                   0x19
#define RLC_GPM_UTCL1_CNTL_0__INVALIDATE__SHIFT                                                               0x1a
#define RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE__SHIFT                                                          0x1b
#define RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP__SHIFT                                                              0x1c
#define RLC_GPM_UTCL1_CNTL_0__RESERVED__SHIFT                                                                 0x1e
#define RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT_MASK                                                       0x000FFFFFL
#define RLC_GPM_UTCL1_CNTL_0__DROP_MODE_MASK                                                                  0x01000000L
#define RLC_GPM_UTCL1_CNTL_0__BYPASS_MASK                                                                     0x02000000L
#define RLC_GPM_UTCL1_CNTL_0__INVALIDATE_MASK                                                                 0x04000000L
#define RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE_MASK                                                            0x08000000L
#define RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP_MASK                                                                0x10000000L
#define RLC_GPM_UTCL1_CNTL_0__RESERVED_MASK                                                                   0xC0000000L
//RLC_GPM_UTCL1_CNTL_1
#define RLC_GPM_UTCL1_CNTL_1__XNACK_REDO_TIMER_CNT__SHIFT                                                     0x0
#define RLC_GPM_UTCL1_CNTL_1__DROP_MODE__SHIFT                                                                0x18
#define RLC_GPM_UTCL1_CNTL_1__BYPASS__SHIFT                                                                   0x19
#define RLC_GPM_UTCL1_CNTL_1__INVALIDATE__SHIFT                                                               0x1a
#define RLC_GPM_UTCL1_CNTL_1__FRAG_LIMIT_MODE__SHIFT                                                          0x1b
#define RLC_GPM_UTCL1_CNTL_1__FORCE_SNOOP__SHIFT                                                              0x1c
#define RLC_GPM_UTCL1_CNTL_1__RESERVED__SHIFT                                                                 0x1e
#define RLC_GPM_UTCL1_CNTL_1__XNACK_REDO_TIMER_CNT_MASK                                                       0x000FFFFFL
#define RLC_GPM_UTCL1_CNTL_1__DROP_MODE_MASK                                                                  0x01000000L
#define RLC_GPM_UTCL1_CNTL_1__BYPASS_MASK                                                                     0x02000000L
#define RLC_GPM_UTCL1_CNTL_1__INVALIDATE_MASK                                                                 0x04000000L
#define RLC_GPM_UTCL1_CNTL_1__FRAG_LIMIT_MODE_MASK                                                            0x08000000L
#define RLC_GPM_UTCL1_CNTL_1__FORCE_SNOOP_MASK                                                                0x10000000L
#define RLC_GPM_UTCL1_CNTL_1__RESERVED_MASK                                                                   0xC0000000L
//RLC_GPM_UTCL1_CNTL_2
#define RLC_GPM_UTCL1_CNTL_2__XNACK_REDO_TIMER_CNT__SHIFT                                                     0x0
#define RLC_GPM_UTCL1_CNTL_2__DROP_MODE__SHIFT                                                                0x18
#define RLC_GPM_UTCL1_CNTL_2__BYPASS__SHIFT                                                                   0x19
#define RLC_GPM_UTCL1_CNTL_2__INVALIDATE__SHIFT                                                               0x1a
#define RLC_GPM_UTCL1_CNTL_2__FRAG_LIMIT_MODE__SHIFT                                                          0x1b
#define RLC_GPM_UTCL1_CNTL_2__FORCE_SNOOP__SHIFT                                                              0x1c
#define RLC_GPM_UTCL1_CNTL_2__RESERVED__SHIFT                                                                 0x1e
#define RLC_GPM_UTCL1_CNTL_2__XNACK_REDO_TIMER_CNT_MASK                                                       0x000FFFFFL
#define RLC_GPM_UTCL1_CNTL_2__DROP_MODE_MASK                                                                  0x01000000L
#define RLC_GPM_UTCL1_CNTL_2__BYPASS_MASK                                                                     0x02000000L
#define RLC_GPM_UTCL1_CNTL_2__INVALIDATE_MASK                                                                 0x04000000L
#define RLC_GPM_UTCL1_CNTL_2__FRAG_LIMIT_MODE_MASK                                                            0x08000000L
#define RLC_GPM_UTCL1_CNTL_2__FORCE_SNOOP_MASK                                                                0x10000000L
#define RLC_GPM_UTCL1_CNTL_2__RESERVED_MASK                                                                   0xC0000000L
//RLC_SPM_UTCL1_CNTL
#define RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT                                                       0x0
#define RLC_SPM_UTCL1_CNTL__DROP_MODE__SHIFT                                                                  0x18
#define RLC_SPM_UTCL1_CNTL__BYPASS__SHIFT                                                                     0x19
#define RLC_SPM_UTCL1_CNTL__INVALIDATE__SHIFT                                                                 0x1a
#define RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT                                                            0x1b
#define RLC_SPM_UTCL1_CNTL__FORCE_SNOOP__SHIFT                                                                0x1c
#define RLC_SPM_UTCL1_CNTL__RESERVED__SHIFT                                                                   0x1e
#define RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK                                                         0x000FFFFFL
#define RLC_SPM_UTCL1_CNTL__DROP_MODE_MASK                                                                    0x01000000L
#define RLC_SPM_UTCL1_CNTL__BYPASS_MASK                                                                       0x02000000L
#define RLC_SPM_UTCL1_CNTL__INVALIDATE_MASK                                                                   0x04000000L
#define RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK                                                              0x08000000L
#define RLC_SPM_UTCL1_CNTL__FORCE_SNOOP_MASK                                                                  0x10000000L
#define RLC_SPM_UTCL1_CNTL__RESERVED_MASK                                                                     0xC0000000L
//RLC_UTCL1_STATUS_2
#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY__SHIFT                                                         0x0
#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY__SHIFT                                                         0x1
#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY__SHIFT                                                         0x2
#define RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY__SHIFT                                                             0x3
#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_BUSY__SHIFT                                                       0x4
#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans__SHIFT                                                 0x5
#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans__SHIFT                                                 0x6
#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans__SHIFT                                                 0x7
#define RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans__SHIFT                                                     0x8
#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_StallOnTrans__SHIFT                                               0x9
#define RLC_UTCL1_STATUS_2__RESERVED__SHIFT                                                                   0xa
#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY_MASK                                                           0x00000001L
#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY_MASK                                                           0x00000002L
#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY_MASK                                                           0x00000004L
#define RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY_MASK                                                               0x00000008L
#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_BUSY_MASK                                                         0x00000010L
#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans_MASK                                                   0x00000020L
#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans_MASK                                                   0x00000040L
#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans_MASK                                                   0x00000080L
#define RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans_MASK                                                       0x00000100L
#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_StallOnTrans_MASK                                                 0x00000200L
#define RLC_UTCL1_STATUS_2__RESERVED_MASK                                                                     0xFFFFFC00L
//RLC_LB_CONFIG_2
#define RLC_LB_CONFIG_2__DATA__SHIFT                                                                          0x0
#define RLC_LB_CONFIG_2__DATA_MASK                                                                            0xFFFFFFFFL
//RLC_LB_CONFIG_3
#define RLC_LB_CONFIG_3__DATA__SHIFT                                                                          0x0
#define RLC_LB_CONFIG_3__DATA_MASK                                                                            0xFFFFFFFFL
//RLC_LB_CONFIG_4
#define RLC_LB_CONFIG_4__DATA__SHIFT                                                                          0x0
#define RLC_LB_CONFIG_4__DATA_MASK                                                                            0xFFFFFFFFL
//RLC_SPM_UTCL1_ERROR_1
#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqError__SHIFT                                                     0x0
#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid__SHIFT                                                 0x2
#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT                                             0x6
#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqError_MASK                                                       0x00000003L
#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid_MASK                                                   0x0000003CL
#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK                                               0x000003C0L
//RLC_SPM_UTCL1_ERROR_2
#define RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT                                             0x0
#define RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK                                               0xFFFFFFFFL
//RLC_GPM_UTCL1_TH0_ERROR_1
#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError__SHIFT                                                 0x0
#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid__SHIFT                                             0x2
#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT                                         0x6
#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError_MASK                                                   0x00000003L
#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid_MASK                                               0x0000003CL
#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB_MASK                                           0x000003C0L
//RLC_LB_CONFIG_1
#define RLC_LB_CONFIG_1__DATA__SHIFT                                                                          0x0
#define RLC_LB_CONFIG_1__DATA_MASK                                                                            0xFFFFFFFFL
//RLC_GPM_UTCL1_TH0_ERROR_2
#define RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT                                         0x0
#define RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB_MASK                                           0xFFFFFFFFL
//RLC_GPM_UTCL1_TH1_ERROR_1
#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqError__SHIFT                                                 0x0
#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorVmid__SHIFT                                             0x2
#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT                                         0x6
#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqError_MASK                                                   0x00000003L
#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorVmid_MASK                                               0x0000003CL
#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK                                           0x000003C0L
//RLC_GPM_UTCL1_TH1_ERROR_2
#define RLC_GPM_UTCL1_TH1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT                                         0x0
#define RLC_GPM_UTCL1_TH1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK                                           0xFFFFFFFFL
//RLC_GPM_UTCL1_TH2_ERROR_1
#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqError__SHIFT                                                 0x0
#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorVmid__SHIFT                                             0x2
#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT                                         0x6
#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqError_MASK                                                   0x00000003L
#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorVmid_MASK                                               0x0000003CL
#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorAddr_MSB_MASK                                           0x000003C0L
//RLC_GPM_UTCL1_TH2_ERROR_2
#define RLC_GPM_UTCL1_TH2_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT                                         0x0
#define RLC_GPM_UTCL1_TH2_ERROR_2__Translated_ReqErrorAddr_LSB_MASK                                           0xFFFFFFFFL
//RLC_CGCG_CGLS_CTRL_3D
#define RLC_CGCG_CGLS_CTRL_3D__CGCG_EN__SHIFT                                                                 0x0
#define RLC_CGCG_CGLS_CTRL_3D__CGLS_EN__SHIFT                                                                 0x1
#define RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT                                                0x2
#define RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT                                                 0x8
#define RLC_CGCG_CGLS_CTRL_3D__CGCG_CONTROLLER__SHIFT                                                         0x1b
#define RLC_CGCG_CGLS_CTRL_3D__CGCG_REG_CTRL__SHIFT                                                           0x1c
#define RLC_CGCG_CGLS_CTRL_3D__SLEEP_MODE__SHIFT                                                              0x1d
#define RLC_CGCG_CGLS_CTRL_3D__SIM_SILICON_EN__SHIFT                                                          0x1f
#define RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK                                                                   0x00000001L
#define RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK                                                                   0x00000002L
#define RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK                                                  0x000000FCL
#define RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK                                                   0x07FFFF00L
#define RLC_CGCG_CGLS_CTRL_3D__CGCG_CONTROLLER_MASK                                                           0x08000000L
#define RLC_CGCG_CGLS_CTRL_3D__CGCG_REG_CTRL_MASK                                                             0x10000000L
#define RLC_CGCG_CGLS_CTRL_3D__SLEEP_MODE_MASK                                                                0x60000000L
#define RLC_CGCG_CGLS_CTRL_3D__SIM_SILICON_EN_MASK                                                            0x80000000L
//RLC_CGCG_RAMP_CTRL_3D
#define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_START_UNIT__SHIFT                                                     0x0
#define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_STEP_UNIT__SHIFT                                                      0x4
#define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_START_UNIT__SHIFT                                                       0x8
#define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_STEP_UNIT__SHIFT                                                        0xc
#define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_CNT__SHIFT                                                          0x10
#define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_UNIT__SHIFT                                                         0x1c
#define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_START_UNIT_MASK                                                       0x0000000FL
#define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_STEP_UNIT_MASK                                                        0x000000F0L
#define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_START_UNIT_MASK                                                         0x00000F00L
#define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_STEP_UNIT_MASK                                                          0x0000F000L
#define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_CNT_MASK                                                            0x0FFF0000L
#define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_UNIT_MASK                                                           0xF0000000L
//RLC_SEMAPHORE_0
#define RLC_SEMAPHORE_0__CLIENT_ID__SHIFT                                                                     0x0
#define RLC_SEMAPHORE_0__RESERVED__SHIFT                                                                      0x5
#define RLC_SEMAPHORE_0__CLIENT_ID_MASK                                                                       0x0000001FL
#define RLC_SEMAPHORE_0__RESERVED_MASK                                                                        0xFFFFFFE0L
//RLC_SEMAPHORE_1
#define RLC_SEMAPHORE_1__CLIENT_ID__SHIFT                                                                     0x0
#define RLC_SEMAPHORE_1__RESERVED__SHIFT                                                                      0x5
#define RLC_SEMAPHORE_1__CLIENT_ID_MASK                                                                       0x0000001FL
#define RLC_SEMAPHORE_1__RESERVED_MASK                                                                        0xFFFFFFE0L
//RLC_PACE_INT_STAT
#define RLC_PACE_INT_STAT__STATUS__SHIFT                                                                      0x0
#define RLC_PACE_INT_STAT__STATUS_MASK                                                                        0xFFFFFFFFL
//RLC_PREWALKER_UTCL1_CNTL
#define RLC_PREWALKER_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT                                                 0x0
#define RLC_PREWALKER_UTCL1_CNTL__DROP_MODE__SHIFT                                                            0x18
#define RLC_PREWALKER_UTCL1_CNTL__BYPASS__SHIFT                                                               0x19
#define RLC_PREWALKER_UTCL1_CNTL__INVALIDATE__SHIFT                                                           0x1a
#define RLC_PREWALKER_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT                                                      0x1b
#define RLC_PREWALKER_UTCL1_CNTL__FORCE_SNOOP__SHIFT                                                          0x1c
#define RLC_PREWALKER_UTCL1_CNTL__RESERVED__SHIFT                                                             0x1e
#define RLC_PREWALKER_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK                                                   0x000FFFFFL
#define RLC_PREWALKER_UTCL1_CNTL__DROP_MODE_MASK                                                              0x01000000L
#define RLC_PREWALKER_UTCL1_CNTL__BYPASS_MASK                                                                 0x02000000L
#define RLC_PREWALKER_UTCL1_CNTL__INVALIDATE_MASK                                                             0x04000000L
#define RLC_PREWALKER_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK                                                        0x08000000L
#define RLC_PREWALKER_UTCL1_CNTL__FORCE_SNOOP_MASK                                                            0x10000000L
#define RLC_PREWALKER_UTCL1_CNTL__RESERVED_MASK                                                               0xC0000000L
//RLC_PREWALKER_UTCL1_TRIG
#define RLC_PREWALKER_UTCL1_TRIG__VALID__SHIFT                                                                0x0
#define RLC_PREWALKER_UTCL1_TRIG__VMID__SHIFT                                                                 0x1
#define RLC_PREWALKER_UTCL1_TRIG__PRIME_MODE__SHIFT                                                           0x5
#define RLC_PREWALKER_UTCL1_TRIG__READ_PERM__SHIFT                                                            0x6
#define RLC_PREWALKER_UTCL1_TRIG__WRITE_PERM__SHIFT                                                           0x7
#define RLC_PREWALKER_UTCL1_TRIG__EXEC_PERM__SHIFT                                                            0x8
#define RLC_PREWALKER_UTCL1_TRIG__RESERVED__SHIFT                                                             0x9
#define RLC_PREWALKER_UTCL1_TRIG__READY__SHIFT                                                                0x1f
#define RLC_PREWALKER_UTCL1_TRIG__VALID_MASK                                                                  0x00000001L
#define RLC_PREWALKER_UTCL1_TRIG__VMID_MASK                                                                   0x0000001EL
#define RLC_PREWALKER_UTCL1_TRIG__PRIME_MODE_MASK                                                             0x00000020L
#define RLC_PREWALKER_UTCL1_TRIG__READ_PERM_MASK                                                              0x00000040L
#define RLC_PREWALKER_UTCL1_TRIG__WRITE_PERM_MASK                                                             0x00000080L
#define RLC_PREWALKER_UTCL1_TRIG__EXEC_PERM_MASK                                                              0x00000100L
#define RLC_PREWALKER_UTCL1_TRIG__RESERVED_MASK                                                               0x7FFFFE00L
#define RLC_PREWALKER_UTCL1_TRIG__READY_MASK                                                                  0x80000000L
//RLC_PREWALKER_UTCL1_ADDR_LSB
#define RLC_PREWALKER_UTCL1_ADDR_LSB__ADDR_LSB__SHIFT                                                         0x0
#define RLC_PREWALKER_UTCL1_ADDR_LSB__ADDR_LSB_MASK                                                           0xFFFFFFFFL
//RLC_PREWALKER_UTCL1_ADDR_MSB
#define RLC_PREWALKER_UTCL1_ADDR_MSB__ADDR_MSB__SHIFT                                                         0x0
#define RLC_PREWALKER_UTCL1_ADDR_MSB__ADDR_MSB_MASK                                                           0x0000FFFFL
//RLC_PREWALKER_UTCL1_SIZE_LSB
#define RLC_PREWALKER_UTCL1_SIZE_LSB__SIZE_LSB__SHIFT                                                         0x0
#define RLC_PREWALKER_UTCL1_SIZE_LSB__SIZE_LSB_MASK                                                           0xFFFFFFFFL
//RLC_PREWALKER_UTCL1_SIZE_MSB
#define RLC_PREWALKER_UTCL1_SIZE_MSB__SIZE_MSB__SHIFT                                                         0x0
#define RLC_PREWALKER_UTCL1_SIZE_MSB__SIZE_MSB_MASK                                                           0x00000003L
//RLC_UTCL1_STATUS
#define RLC_UTCL1_STATUS__FAULT_DETECTED__SHIFT                                                               0x0
#define RLC_UTCL1_STATUS__RETRY_DETECTED__SHIFT                                                               0x1
#define RLC_UTCL1_STATUS__PRT_DETECTED__SHIFT                                                                 0x2
#define RLC_UTCL1_STATUS__RESERVED__SHIFT                                                                     0x3
#define RLC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT                                                                0x8
#define RLC_UTCL1_STATUS__RESERVED_1__SHIFT                                                                   0xe
#define RLC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT                                                                0x10
#define RLC_UTCL1_STATUS__RESERVED_2__SHIFT                                                                   0x16
#define RLC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT                                                                  0x18
#define RLC_UTCL1_STATUS__RESERVED_3__SHIFT                                                                   0x1e
#define RLC_UTCL1_STATUS__FAULT_DETECTED_MASK                                                                 0x00000001L
#define RLC_UTCL1_STATUS__RETRY_DETECTED_MASK                                                                 0x00000002L
#define RLC_UTCL1_STATUS__PRT_DETECTED_MASK                                                                   0x00000004L
#define RLC_UTCL1_STATUS__RESERVED_MASK                                                                       0x000000F8L
#define RLC_UTCL1_STATUS__FAULT_UTCL1ID_MASK                                                                  0x00003F00L
#define RLC_UTCL1_STATUS__RESERVED_1_MASK                                                                     0x0000C000L
#define RLC_UTCL1_STATUS__RETRY_UTCL1ID_MASK                                                                  0x003F0000L
#define RLC_UTCL1_STATUS__RESERVED_2_MASK                                                                     0x00C00000L
#define RLC_UTCL1_STATUS__PRT_UTCL1ID_MASK                                                                    0x3F000000L
#define RLC_UTCL1_STATUS__RESERVED_3_MASK                                                                     0xC0000000L
//RLC_R2I_CNTL_0
#define RLC_R2I_CNTL_0__Data__SHIFT                                                                           0x0
#define RLC_R2I_CNTL_0__Data_MASK                                                                             0xFFFFFFFFL
//RLC_R2I_CNTL_1
#define RLC_R2I_CNTL_1__Data__SHIFT                                                                           0x0
#define RLC_R2I_CNTL_1__Data_MASK                                                                             0xFFFFFFFFL
//RLC_R2I_CNTL_2
#define RLC_R2I_CNTL_2__Data__SHIFT                                                                           0x0
#define RLC_R2I_CNTL_2__Data_MASK                                                                             0xFFFFFFFFL
//RLC_R2I_CNTL_3
#define RLC_R2I_CNTL_3__Data__SHIFT                                                                           0x0
#define RLC_R2I_CNTL_3__Data_MASK                                                                             0xFFFFFFFFL
//RLC_LB_WGP_STAT
#define RLC_LB_WGP_STAT__MAX_WGP__SHIFT                                                                       0x0
#define RLC_LB_WGP_STAT__ON_WGP__SHIFT                                                                        0x10
#define RLC_LB_WGP_STAT__MAX_WGP_MASK                                                                         0x0000FFFFL
#define RLC_LB_WGP_STAT__ON_WGP_MASK                                                                          0xFFFF0000L
//RLC_GPM_INT_STAT_TH0
#define RLC_GPM_INT_STAT_TH0__STATUS__SHIFT                                                                   0x0
#define RLC_GPM_INT_STAT_TH0__STATUS_MASK                                                                     0xFFFFFFFFL
//RLC_GPM_GENERAL_13
#define RLC_GPM_GENERAL_13__DATA__SHIFT                                                                       0x0
#define RLC_GPM_GENERAL_13__DATA_MASK                                                                         0xFFFFFFFFL
//RLC_GPM_GENERAL_14
#define RLC_GPM_GENERAL_14__DATA__SHIFT                                                                       0x0
#define RLC_GPM_GENERAL_14__DATA_MASK                                                                         0xFFFFFFFFL
//RLC_GPM_GENERAL_15
#define RLC_GPM_GENERAL_15__DATA__SHIFT                                                                       0x0
#define RLC_GPM_GENERAL_15__DATA_MASK                                                                         0xFFFFFFFFL
//RLC_SPARE_INT_1
#define RLC_SPARE_INT_1__DATA__SHIFT                                                                          0x0
#define RLC_SPARE_INT_1__PROCESSING__SHIFT                                                                    0x1e
#define RLC_SPARE_INT_1__COMPLETE__SHIFT                                                                      0x1f
#define RLC_SPARE_INT_1__DATA_MASK                                                                            0x3FFFFFFFL
#define RLC_SPARE_INT_1__PROCESSING_MASK                                                                      0x40000000L
#define RLC_SPARE_INT_1__COMPLETE_MASK                                                                        0x80000000L
//RLC_SEMAPHORE_2
#define RLC_SEMAPHORE_2__CLIENT_ID__SHIFT                                                                     0x0
#define RLC_SEMAPHORE_2__RESERVED__SHIFT                                                                      0x5
#define RLC_SEMAPHORE_2__CLIENT_ID_MASK                                                                       0x0000001FL
#define RLC_SEMAPHORE_2__RESERVED_MASK                                                                        0xFFFFFFE0L
//RLC_SEMAPHORE_3
#define RLC_SEMAPHORE_3__CLIENT_ID__SHIFT                                                                     0x0
#define RLC_SEMAPHORE_3__RESERVED__SHIFT                                                                      0x5
#define RLC_SEMAPHORE_3__CLIENT_ID_MASK                                                                       0x0000001FL
#define RLC_SEMAPHORE_3__RESERVED_MASK                                                                        0xFFFFFFE0L
//RLC_SMU_ARGUMENT_3
#define RLC_SMU_ARGUMENT_3__ARG__SHIFT                                                                        0x0
#define RLC_SMU_ARGUMENT_3__ARG_MASK                                                                          0xFFFFFFFFL
//RLC_SMU_ARGUMENT_4
#define RLC_SMU_ARGUMENT_4__ARG__SHIFT                                                                        0x0
#define RLC_SMU_ARGUMENT_4__ARG_MASK                                                                          0xFFFFFFFFL
//RLC_GPU_CLOCK_COUNT_LSB_1
#define RLC_GPU_CLOCK_COUNT_LSB_1__GPU_CLOCKS_LSB__SHIFT                                                      0x0
#define RLC_GPU_CLOCK_COUNT_LSB_1__GPU_CLOCKS_LSB_MASK                                                        0xFFFFFFFFL
//RLC_GPU_CLOCK_COUNT_MSB_1
#define RLC_GPU_CLOCK_COUNT_MSB_1__GPU_CLOCKS_MSB__SHIFT                                                      0x0
#define RLC_GPU_CLOCK_COUNT_MSB_1__GPU_CLOCKS_MSB_MASK                                                        0xFFFFFFFFL
//RLC_CAPTURE_GPU_CLOCK_COUNT_1
#define RLC_CAPTURE_GPU_CLOCK_COUNT_1__CAPTURE__SHIFT                                                         0x0
#define RLC_CAPTURE_GPU_CLOCK_COUNT_1__RESERVED__SHIFT                                                        0x1
#define RLC_CAPTURE_GPU_CLOCK_COUNT_1__CAPTURE_MASK                                                           0x00000001L
#define RLC_CAPTURE_GPU_CLOCK_COUNT_1__RESERVED_MASK                                                          0xFFFFFFFEL
//RLC_GPU_CLOCK_COUNT_LSB_2
#define RLC_GPU_CLOCK_COUNT_LSB_2__GPU_CLOCKS_LSB__SHIFT                                                      0x0
#define RLC_GPU_CLOCK_COUNT_LSB_2__GPU_CLOCKS_LSB_MASK                                                        0xFFFFFFFFL
//RLC_GPU_CLOCK_COUNT_MSB_2
#define RLC_GPU_CLOCK_COUNT_MSB_2__GPU_CLOCKS_MSB__SHIFT                                                      0x0
#define RLC_GPU_CLOCK_COUNT_MSB_2__GPU_CLOCKS_MSB_MASK                                                        0xFFFFFFFFL
//RLC_PACE_INT_DISABLE
#define RLC_PACE_INT_DISABLE__DISABLE_INT__SHIFT                                                              0x0
#define RLC_PACE_INT_DISABLE__DISABLE_INT_MASK                                                                0xFFFFFFFFL
//RLC_CAPTURE_GPU_CLOCK_COUNT_2
#define RLC_CAPTURE_GPU_CLOCK_COUNT_2__CAPTURE__SHIFT                                                         0x0
#define RLC_CAPTURE_GPU_CLOCK_COUNT_2__RESERVED__SHIFT                                                        0x1
#define RLC_CAPTURE_GPU_CLOCK_COUNT_2__CAPTURE_MASK                                                           0x00000001L
#define RLC_CAPTURE_GPU_CLOCK_COUNT_2__RESERVED_MASK                                                          0xFFFFFFFEL
//RLC_RLCV_DOORBELL_RANGE
#define RLC_RLCV_DOORBELL_RANGE__LOWER_ADDR_RESERVED__SHIFT                                                   0x0
#define RLC_RLCV_DOORBELL_RANGE__LOWER_ADDR__SHIFT                                                            0x2
#define RLC_RLCV_DOORBELL_RANGE__UPPER_ADDR_RESERVED__SHIFT                                                   0x10
#define RLC_RLCV_DOORBELL_RANGE__UPPER_ADDR__SHIFT                                                            0x12
#define RLC_RLCV_DOORBELL_RANGE__LOWER_ADDR_RESERVED_MASK                                                     0x00000003L
#define RLC_RLCV_DOORBELL_RANGE__LOWER_ADDR_MASK                                                              0x00000FFCL
#define RLC_RLCV_DOORBELL_RANGE__UPPER_ADDR_RESERVED_MASK                                                     0x00030000L
#define RLC_RLCV_DOORBELL_RANGE__UPPER_ADDR_MASK                                                              0x0FFC0000L
//RLC_RLCV_DOORBELL_CNTL
#define RLC_RLCV_DOORBELL_CNTL__DOORBELL_0_MODE__SHIFT                                                        0x0
#define RLC_RLCV_DOORBELL_CNTL__DOORBELL_1_MODE__SHIFT                                                        0x2
#define RLC_RLCV_DOORBELL_CNTL__DOORBELL_2_MODE__SHIFT                                                        0x4
#define RLC_RLCV_DOORBELL_CNTL__DOORBELL_3_MODE__SHIFT                                                        0x6
#define RLC_RLCV_DOORBELL_CNTL__DOORBELL_ID__SHIFT                                                            0x10
#define RLC_RLCV_DOORBELL_CNTL__DOORBELL_ID_EN__SHIFT                                                         0x15
#define RLC_RLCV_DOORBELL_CNTL__DOORBELL_0_MODE_MASK                                                          0x00000003L
#define RLC_RLCV_DOORBELL_CNTL__DOORBELL_1_MODE_MASK                                                          0x0000000CL
#define RLC_RLCV_DOORBELL_CNTL__DOORBELL_2_MODE_MASK                                                          0x00000030L
#define RLC_RLCV_DOORBELL_CNTL__DOORBELL_3_MODE_MASK                                                          0x000000C0L
#define RLC_RLCV_DOORBELL_CNTL__DOORBELL_ID_MASK                                                              0x001F0000L
#define RLC_RLCV_DOORBELL_CNTL__DOORBELL_ID_EN_MASK                                                           0x00200000L
//RLC_RLCV_DOORBELL_STAT
#define RLC_RLCV_DOORBELL_STAT__DOORBELL_0_VALID__SHIFT                                                       0x0
#define RLC_RLCV_DOORBELL_STAT__DOORBELL_1_VALID__SHIFT                                                       0x1
#define RLC_RLCV_DOORBELL_STAT__DOORBELL_2_VALID__SHIFT                                                       0x2
#define RLC_RLCV_DOORBELL_STAT__DOORBELL_3_VALID__SHIFT                                                       0x3
#define RLC_RLCV_DOORBELL_STAT__DOORBELL_0_VALID_MASK                                                         0x00000001L
#define RLC_RLCV_DOORBELL_STAT__DOORBELL_1_VALID_MASK                                                         0x00000002L
#define RLC_RLCV_DOORBELL_STAT__DOORBELL_2_VALID_MASK                                                         0x00000004L
#define RLC_RLCV_DOORBELL_STAT__DOORBELL_3_VALID_MASK                                                         0x00000008L
//RLC_RLCV_DOORBELL_0_DATA_LO
#define RLC_RLCV_DOORBELL_0_DATA_LO__DATA__SHIFT                                                              0x0
#define RLC_RLCV_DOORBELL_0_DATA_LO__DATA_MASK                                                                0xFFFFFFFFL
//RLC_RLCV_DOORBELL_0_DATA_HI
#define RLC_RLCV_DOORBELL_0_DATA_HI__DATA__SHIFT                                                              0x0
#define RLC_RLCV_DOORBELL_0_DATA_HI__DATA_MASK                                                                0xFFFFFFFFL
//RLC_RLCV_DOORBELL_1_DATA_LO
#define RLC_RLCV_DOORBELL_1_DATA_LO__DATA__SHIFT                                                              0x0
#define RLC_RLCV_DOORBELL_1_DATA_LO__DATA_MASK                                                                0xFFFFFFFFL
//RLC_RLCV_DOORBELL_1_DATA_HI
#define RLC_RLCV_DOORBELL_1_DATA_HI__DATA__SHIFT                                                              0x0
#define RLC_RLCV_DOORBELL_1_DATA_HI__DATA_MASK                                                                0xFFFFFFFFL
//RLC_RLCV_DOORBELL_2_DATA_LO
#define RLC_RLCV_DOORBELL_2_DATA_LO__DATA__SHIFT                                                              0x0
#define RLC_RLCV_DOORBELL_2_DATA_LO__DATA_MASK                                                                0xFFFFFFFFL
//RLC_RLCV_DOORBELL_2_DATA_HI
#define RLC_RLCV_DOORBELL_2_DATA_HI__DATA__SHIFT                                                              0x0
#define RLC_RLCV_DOORBELL_2_DATA_HI__DATA_MASK                                                                0xFFFFFFFFL
//RLC_RLCV_DOORBELL_3_DATA_LO
#define RLC_RLCV_DOORBELL_3_DATA_LO__DATA__SHIFT                                                              0x0
#define RLC_RLCV_DOORBELL_3_DATA_LO__DATA_MASK                                                                0xFFFFFFFFL
//RLC_RLCV_DOORBELL_3_DATA_HI
#define RLC_RLCV_DOORBELL_3_DATA_HI__DATA__SHIFT                                                              0x0
#define RLC_RLCV_DOORBELL_3_DATA_HI__DATA_MASK                                                                0xFFFFFFFFL
//RLC_RLCV_SPARE_INT
#define RLC_RLCV_SPARE_INT__INTERRUPT__SHIFT                                                                  0x0
#define RLC_RLCV_SPARE_INT__RESERVED__SHIFT                                                                   0x1
#define RLC_RLCV_SPARE_INT__INTERRUPT_MASK                                                                    0x00000001L
#define RLC_RLCV_SPARE_INT__RESERVED_MASK                                                                     0xFFFFFFFEL
//RLC_PACE_TIMER_INT_0
#define RLC_PACE_TIMER_INT_0__TIMER__SHIFT                                                                    0x0
#define RLC_PACE_TIMER_INT_0__TIMER_MASK                                                                      0xFFFFFFFFL
//RLC_PACE_TIMER_CTRL
#define RLC_PACE_TIMER_CTRL__TIMER_0_EN__SHIFT                                                                0x0
#define RLC_PACE_TIMER_CTRL__TIMER_1_EN__SHIFT                                                                0x1
#define RLC_PACE_TIMER_CTRL__TIMER_0_AUTO_REARM__SHIFT                                                        0x2
#define RLC_PACE_TIMER_CTRL__TIMER_1_AUTO_REARM__SHIFT                                                        0x3
#define RLC_PACE_TIMER_CTRL__TIMER_0_INT_CLEAR__SHIFT                                                         0x4
#define RLC_PACE_TIMER_CTRL__TIMER_1_INT_CLEAR__SHIFT                                                         0x5
#define RLC_PACE_TIMER_CTRL__RESERVED__SHIFT                                                                  0x6
#define RLC_PACE_TIMER_CTRL__TIMER_0_EN_MASK                                                                  0x00000001L
#define RLC_PACE_TIMER_CTRL__TIMER_1_EN_MASK                                                                  0x00000002L
#define RLC_PACE_TIMER_CTRL__TIMER_0_AUTO_REARM_MASK                                                          0x00000004L
#define RLC_PACE_TIMER_CTRL__TIMER_1_AUTO_REARM_MASK                                                          0x00000008L
#define RLC_PACE_TIMER_CTRL__TIMER_0_INT_CLEAR_MASK                                                           0x00000010L
#define RLC_PACE_TIMER_CTRL__TIMER_1_INT_CLEAR_MASK                                                           0x00000020L
#define RLC_PACE_TIMER_CTRL__RESERVED_MASK                                                                    0xFFFFFFC0L
//RLC_PACE_TIMER_INT_1
#define RLC_PACE_TIMER_INT_1__TIMER__SHIFT                                                                    0x0
#define RLC_PACE_TIMER_INT_1__TIMER_MASK                                                                      0xFFFFFFFFL
//RLC_PACE_SPARE_INT
#define RLC_PACE_SPARE_INT__INTERRUPT__SHIFT                                                                  0x0
#define RLC_PACE_SPARE_INT__RESERVED__SHIFT                                                                   0x1
#define RLC_PACE_SPARE_INT__INTERRUPT_MASK                                                                    0x00000001L
#define RLC_PACE_SPARE_INT__RESERVED_MASK                                                                     0xFFFFFFFEL
//RLC_SMU_CLK_REQ
#define RLC_SMU_CLK_REQ__VALID__SHIFT                                                                         0x0
#define RLC_SMU_CLK_REQ__VALID_MASK                                                                           0x00000001L
//RLC_CP_STAT_INVAL_STAT
#define RLC_CP_STAT_INVAL_STAT__CPG_STAT_INVAL_PEND__SHIFT                                                    0x0
#define RLC_CP_STAT_INVAL_STAT__CPC_STAT_INVAL_PEND__SHIFT                                                    0x1
#define RLC_CP_STAT_INVAL_STAT__CPF_STAT_INVAL_PEND__SHIFT                                                    0x2
#define RLC_CP_STAT_INVAL_STAT__CPG_STAT_INVAL_PEND_CHANGED__SHIFT                                            0x3
#define RLC_CP_STAT_INVAL_STAT__CPC_STAT_INVAL_PEND_CHANGED__SHIFT                                            0x4
#define RLC_CP_STAT_INVAL_STAT__CPF_STAT_INVAL_PEND_CHANGED__SHIFT                                            0x5
#define RLC_CP_STAT_INVAL_STAT__CPG_STAT_INVAL_PEND_MASK                                                      0x00000001L
#define RLC_CP_STAT_INVAL_STAT__CPC_STAT_INVAL_PEND_MASK                                                      0x00000002L
#define RLC_CP_STAT_INVAL_STAT__CPF_STAT_INVAL_PEND_MASK                                                      0x00000004L
#define RLC_CP_STAT_INVAL_STAT__CPG_STAT_INVAL_PEND_CHANGED_MASK                                              0x00000008L
#define RLC_CP_STAT_INVAL_STAT__CPC_STAT_INVAL_PEND_CHANGED_MASK                                              0x00000010L
#define RLC_CP_STAT_INVAL_STAT__CPF_STAT_INVAL_PEND_CHANGED_MASK                                              0x00000020L
//RLC_CP_STAT_INVAL_CTRL
#define RLC_CP_STAT_INVAL_CTRL__CPG_STAT_INVAL_PEND_EN__SHIFT                                                 0x0
#define RLC_CP_STAT_INVAL_CTRL__CPC_STAT_INVAL_PEND_EN__SHIFT                                                 0x1
#define RLC_CP_STAT_INVAL_CTRL__CPF_STAT_INVAL_PEND_EN__SHIFT                                                 0x2
#define RLC_CP_STAT_INVAL_CTRL__CPG_STAT_INVAL_PEND_EN_MASK                                                   0x00000001L
#define RLC_CP_STAT_INVAL_CTRL__CPC_STAT_INVAL_PEND_EN_MASK                                                   0x00000002L
#define RLC_CP_STAT_INVAL_CTRL__CPF_STAT_INVAL_PEND_EN_MASK                                                   0x00000004L
//RLC_CLK_STATUS
#define RLC_CLK_STATUS__RLC_ALL_CLK_VALID__SHIFT                                                              0x0
#define RLC_CLK_STATUS__RLC_CMN_GPM_SCLK_DYN_VLD__SHIFT                                                       0x1
#define RLC_CLK_STATUS__RLC_CMN_TC_SCLK_DYN_VLD__SHIFT                                                        0x2
#define RLC_CLK_STATUS__RLC_CMN_SPP_SCLK_DYN_VLD__SHIFT                                                       0x3
#define RLC_CLK_STATUS__RLC_CMN_SRM_SCLK_DYN_VLD__SHIFT                                                       0x5
#define RLC_CLK_STATUS__RLC_SRM_CLK_BUSY__SHIFT                                                               0x6
#define RLC_CLK_STATUS__RLC_CMN_SPM_SCLK_DYN_VLD__SHIFT                                                       0x7
#define RLC_CLK_STATUS__RLC_SPM_CLK_BUSY__SHIFT                                                               0x8
#define RLC_CLK_STATUS__RESERVED__SHIFT                                                                       0x9
#define RLC_CLK_STATUS__RLC_ALL_CLK_VALID_MASK                                                                0x00000001L
#define RLC_CLK_STATUS__RLC_CMN_GPM_SCLK_DYN_VLD_MASK                                                         0x00000002L
#define RLC_CLK_STATUS__RLC_CMN_TC_SCLK_DYN_VLD_MASK                                                          0x00000004L
#define RLC_CLK_STATUS__RLC_CMN_SPP_SCLK_DYN_VLD_MASK                                                         0x00000008L
#define RLC_CLK_STATUS__RLC_CMN_SRM_SCLK_DYN_VLD_MASK                                                         0x00000020L
#define RLC_CLK_STATUS__RLC_SRM_CLK_BUSY_MASK                                                                 0x00000040L
#define RLC_CLK_STATUS__RLC_CMN_SPM_SCLK_DYN_VLD_MASK                                                         0x00000080L
#define RLC_CLK_STATUS__RLC_SPM_CLK_BUSY_MASK                                                                 0x00000100L
#define RLC_CLK_STATUS__RESERVED_MASK                                                                         0xFFFFFE00L
//RLC_SPP_CTRL
#define RLC_SPP_CTRL__ENABLE__SHIFT                                                                           0x0
#define RLC_SPP_CTRL__ENABLE_PPROF__SHIFT                                                                     0x1
#define RLC_SPP_CTRL__ENABLE_PWR_OPT__SHIFT                                                                   0x2
#define RLC_SPP_CTRL__PAUSE__SHIFT                                                                            0x3
#define RLC_SPP_CTRL__ENABLE_MASK                                                                             0x00000001L
#define RLC_SPP_CTRL__ENABLE_PPROF_MASK                                                                       0x00000002L
#define RLC_SPP_CTRL__ENABLE_PWR_OPT_MASK                                                                     0x00000004L
#define RLC_SPP_CTRL__PAUSE_MASK                                                                              0x00000008L
//RLC_SPP_SHADER_PROFILE_EN
#define RLC_SPP_SHADER_PROFILE_EN__PS_ENABLE__SHIFT                                                           0x0
#define RLC_SPP_SHADER_PROFILE_EN__VS_ENABLE__SHIFT                                                           0x1
#define RLC_SPP_SHADER_PROFILE_EN__GS_ENABLE__SHIFT                                                           0x2
#define RLC_SPP_SHADER_PROFILE_EN__HS_ENABLE__SHIFT                                                           0x3
#define RLC_SPP_SHADER_PROFILE_EN__CSG_ENABLE__SHIFT                                                          0x4
#define RLC_SPP_SHADER_PROFILE_EN__CS_ENABLE__SHIFT                                                           0x5
#define RLC_SPP_SHADER_PROFILE_EN__PS_STOP_CONDITION__SHIFT                                                   0x6
#define RLC_SPP_SHADER_PROFILE_EN__VS_STOP_CONDITION__SHIFT                                                   0x7
#define RLC_SPP_SHADER_PROFILE_EN__GS_STOP_CONDITION__SHIFT                                                   0x8
#define RLC_SPP_SHADER_PROFILE_EN__HS_STOP_CONDITION__SHIFT                                                   0x9
#define RLC_SPP_SHADER_PROFILE_EN__CSG_STOP_CONDITION__SHIFT                                                  0xa
#define RLC_SPP_SHADER_PROFILE_EN__CS_STOP_CONDITION__SHIFT                                                   0xb
#define RLC_SPP_SHADER_PROFILE_EN__PS_START_CONDITION__SHIFT                                                  0xc
#define RLC_SPP_SHADER_PROFILE_EN__CS_START_CONDITION__SHIFT                                                  0xd
#define RLC_SPP_SHADER_PROFILE_EN__FORCE_MISS__SHIFT                                                          0xe
#define RLC_SPP_SHADER_PROFILE_EN__FORCE_UNLOCKED__SHIFT                                                      0xf
#define RLC_SPP_SHADER_PROFILE_EN__ENABLE_PROF_INFO_LOCK__SHIFT                                               0x10
#define RLC_SPP_SHADER_PROFILE_EN__PS_ENABLE_MASK                                                             0x00000001L
#define RLC_SPP_SHADER_PROFILE_EN__VS_ENABLE_MASK                                                             0x00000002L
#define RLC_SPP_SHADER_PROFILE_EN__GS_ENABLE_MASK                                                             0x00000004L
#define RLC_SPP_SHADER_PROFILE_EN__HS_ENABLE_MASK                                                             0x00000008L
#define RLC_SPP_SHADER_PROFILE_EN__CSG_ENABLE_MASK                                                            0x00000010L
#define RLC_SPP_SHADER_PROFILE_EN__CS_ENABLE_MASK                                                             0x00000020L
#define RLC_SPP_SHADER_PROFILE_EN__PS_STOP_CONDITION_MASK                                                     0x00000040L
#define RLC_SPP_SHADER_PROFILE_EN__VS_STOP_CONDITION_MASK                                                     0x00000080L
#define RLC_SPP_SHADER_PROFILE_EN__GS_STOP_CONDITION_MASK                                                     0x00000100L
#define RLC_SPP_SHADER_PROFILE_EN__HS_STOP_CONDITION_MASK                                                     0x00000200L
#define RLC_SPP_SHADER_PROFILE_EN__CSG_STOP_CONDITION_MASK                                                    0x00000400L
#define RLC_SPP_SHADER_PROFILE_EN__CS_STOP_CONDITION_MASK                                                     0x00000800L
#define RLC_SPP_SHADER_PROFILE_EN__PS_START_CONDITION_MASK                                                    0x00001000L
#define RLC_SPP_SHADER_PROFILE_EN__CS_START_CONDITION_MASK                                                    0x00002000L
#define RLC_SPP_SHADER_PROFILE_EN__FORCE_MISS_MASK                                                            0x00004000L
#define RLC_SPP_SHADER_PROFILE_EN__FORCE_UNLOCKED_MASK                                                        0x00008000L
#define RLC_SPP_SHADER_PROFILE_EN__ENABLE_PROF_INFO_LOCK_MASK                                                 0x00010000L
//RLC_SPP_SSF_CAPTURE_EN
#define RLC_SPP_SSF_CAPTURE_EN__PS_ENABLE__SHIFT                                                              0x0
#define RLC_SPP_SSF_CAPTURE_EN__VS_ENABLE__SHIFT                                                              0x1
#define RLC_SPP_SSF_CAPTURE_EN__GS_ENABLE__SHIFT                                                              0x2
#define RLC_SPP_SSF_CAPTURE_EN__HS_ENABLE__SHIFT                                                              0x3
#define RLC_SPP_SSF_CAPTURE_EN__CSG_ENABLE__SHIFT                                                             0x4
#define RLC_SPP_SSF_CAPTURE_EN__CS_ENABLE__SHIFT                                                              0x5
#define RLC_SPP_SSF_CAPTURE_EN__PS_ENABLE_MASK                                                                0x00000001L
#define RLC_SPP_SSF_CAPTURE_EN__VS_ENABLE_MASK                                                                0x00000002L
#define RLC_SPP_SSF_CAPTURE_EN__GS_ENABLE_MASK                                                                0x00000004L
#define RLC_SPP_SSF_CAPTURE_EN__HS_ENABLE_MASK                                                                0x00000008L
#define RLC_SPP_SSF_CAPTURE_EN__CSG_ENABLE_MASK                                                               0x00000010L
#define RLC_SPP_SSF_CAPTURE_EN__CS_ENABLE_MASK                                                                0x00000020L
//RLC_SPP_SSF_THRESHOLD_0
#define RLC_SPP_SSF_THRESHOLD_0__PS_THRESHOLD__SHIFT                                                          0x0
#define RLC_SPP_SSF_THRESHOLD_0__VS_THRESHOLD__SHIFT                                                          0x10
#define RLC_SPP_SSF_THRESHOLD_0__PS_THRESHOLD_MASK                                                            0x0000FFFFL
#define RLC_SPP_SSF_THRESHOLD_0__VS_THRESHOLD_MASK                                                            0xFFFF0000L
//RLC_SPP_SSF_THRESHOLD_1
#define RLC_SPP_SSF_THRESHOLD_1__GS_THRESHOLD__SHIFT                                                          0x0
#define RLC_SPP_SSF_THRESHOLD_1__HS_THRESHOLD__SHIFT                                                          0x10
#define RLC_SPP_SSF_THRESHOLD_1__GS_THRESHOLD_MASK                                                            0x0000FFFFL
#define RLC_SPP_SSF_THRESHOLD_1__HS_THRESHOLD_MASK                                                            0xFFFF0000L
//RLC_SPP_SSF_THRESHOLD_2
#define RLC_SPP_SSF_THRESHOLD_2__CSG_THRESHOLD__SHIFT                                                         0x0
#define RLC_SPP_SSF_THRESHOLD_2__CS_THRESHOLD__SHIFT                                                          0x10
#define RLC_SPP_SSF_THRESHOLD_2__CSG_THRESHOLD_MASK                                                           0x0000FFFFL
#define RLC_SPP_SSF_THRESHOLD_2__CS_THRESHOLD_MASK                                                            0xFFFF0000L
//RLC_SPP_INFLIGHT_RD_ADDR
#define RLC_SPP_INFLIGHT_RD_ADDR__ADDR__SHIFT                                                                 0x0
#define RLC_SPP_INFLIGHT_RD_ADDR__ADDR_MASK                                                                   0x0000001FL
//RLC_SPP_INFLIGHT_RD_DATA
#define RLC_SPP_INFLIGHT_RD_DATA__DATA__SHIFT                                                                 0x0
#define RLC_SPP_INFLIGHT_RD_DATA__DATA_MASK                                                                   0xFFFFFFFFL
//RLC_GPM_GENERAL_16
#define RLC_GPM_GENERAL_16__DATA__SHIFT                                                                       0x0
#define RLC_GPM_GENERAL_16__DATA_MASK                                                                         0xFFFFFFFFL
//RLC_SPP_PROF_INFO_1
#define RLC_SPP_PROF_INFO_1__SH_ID__SHIFT                                                                     0x0
#define RLC_SPP_PROF_INFO_1__SH_ID_MASK                                                                       0xFFFFFFFFL
//RLC_SPP_PROF_INFO_2
#define RLC_SPP_PROF_INFO_2__SH_TYPE__SHIFT                                                                   0x0
#define RLC_SPP_PROF_INFO_2__CAM_HIT__SHIFT                                                                   0x4
#define RLC_SPP_PROF_INFO_2__CAM_LOCK__SHIFT                                                                  0x5
#define RLC_SPP_PROF_INFO_2__CAM_CONFLICT__SHIFT                                                              0x6
#define RLC_SPP_PROF_INFO_2__SH_TYPE_MASK                                                                     0x0000000FL
#define RLC_SPP_PROF_INFO_2__CAM_HIT_MASK                                                                     0x00000010L
#define RLC_SPP_PROF_INFO_2__CAM_LOCK_MASK                                                                    0x00000020L
#define RLC_SPP_PROF_INFO_2__CAM_CONFLICT_MASK                                                                0x00000040L
//RLC_SPP_GLOBAL_SH_ID
#define RLC_SPP_GLOBAL_SH_ID__SH_ID__SHIFT                                                                    0x0
#define RLC_SPP_GLOBAL_SH_ID__SH_ID_MASK                                                                      0xFFFFFFFFL
//RLC_SPP_GLOBAL_SH_ID_VALID
#define RLC_SPP_GLOBAL_SH_ID_VALID__VALID__SHIFT                                                              0x0
#define RLC_SPP_GLOBAL_SH_ID_VALID__VALID_MASK                                                                0x00000001L
//RLC_SPP_STATUS
#define RLC_SPP_STATUS__RESERVED_0__SHIFT                                                                     0x0
#define RLC_SPP_STATUS__SSF_BUSY__SHIFT                                                                       0x1
#define RLC_SPP_STATUS__EVENT_ARB_BUSY__SHIFT                                                                 0x2
#define RLC_SPP_STATUS__SPP_BUSY__SHIFT                                                                       0x1f
#define RLC_SPP_STATUS__RESERVED_0_MASK                                                                       0x00000001L
#define RLC_SPP_STATUS__SSF_BUSY_MASK                                                                         0x00000002L
#define RLC_SPP_STATUS__EVENT_ARB_BUSY_MASK                                                                   0x00000004L
#define RLC_SPP_STATUS__SPP_BUSY_MASK                                                                         0x80000000L
//RLC_SPP_PVT_STAT_0
#define RLC_SPP_PVT_STAT_0__LEVEL_0_COUNTER__SHIFT                                                            0x0
#define RLC_SPP_PVT_STAT_0__LEVEL_1_COUNTER__SHIFT                                                            0x6
#define RLC_SPP_PVT_STAT_0__LEVEL_2_COUNTER__SHIFT                                                            0xc
#define RLC_SPP_PVT_STAT_0__LEVEL_3_COUNTER__SHIFT                                                            0x12
#define RLC_SPP_PVT_STAT_0__LEVEL_4_COUNTER__SHIFT                                                            0x18
#define RLC_SPP_PVT_STAT_0__LEVEL_0_COUNTER_MASK                                                              0x0000003FL
#define RLC_SPP_PVT_STAT_0__LEVEL_1_COUNTER_MASK                                                              0x00000FC0L
#define RLC_SPP_PVT_STAT_0__LEVEL_2_COUNTER_MASK                                                              0x0003F000L
#define RLC_SPP_PVT_STAT_0__LEVEL_3_COUNTER_MASK                                                              0x00FC0000L
#define RLC_SPP_PVT_STAT_0__LEVEL_4_COUNTER_MASK                                                              0x7F000000L
//RLC_SPP_PVT_STAT_1
#define RLC_SPP_PVT_STAT_1__LEVEL_5_COUNTER__SHIFT                                                            0x0
#define RLC_SPP_PVT_STAT_1__LEVEL_6_COUNTER__SHIFT                                                            0x6
#define RLC_SPP_PVT_STAT_1__LEVEL_7_COUNTER__SHIFT                                                            0xc
#define RLC_SPP_PVT_STAT_1__LEVEL_8_COUNTER__SHIFT                                                            0x12
#define RLC_SPP_PVT_STAT_1__LEVEL_9_COUNTER__SHIFT                                                            0x18
#define RLC_SPP_PVT_STAT_1__LEVEL_5_COUNTER_MASK                                                              0x0000003FL
#define RLC_SPP_PVT_STAT_1__LEVEL_6_COUNTER_MASK                                                              0x00000FC0L
#define RLC_SPP_PVT_STAT_1__LEVEL_7_COUNTER_MASK                                                              0x0003F000L
#define RLC_SPP_PVT_STAT_1__LEVEL_8_COUNTER_MASK                                                              0x00FC0000L
#define RLC_SPP_PVT_STAT_1__LEVEL_9_COUNTER_MASK                                                              0x7F000000L
//RLC_SPP_PVT_STAT_2
#define RLC_SPP_PVT_STAT_2__LEVEL_10_COUNTER__SHIFT                                                           0x0
#define RLC_SPP_PVT_STAT_2__LEVEL_11_COUNTER__SHIFT                                                           0x6
#define RLC_SPP_PVT_STAT_2__LEVEL_12_COUNTER__SHIFT                                                           0xc
#define RLC_SPP_PVT_STAT_2__LEVEL_13_COUNTER__SHIFT                                                           0x12
#define RLC_SPP_PVT_STAT_2__LEVEL_14_COUNTER__SHIFT                                                           0x18
#define RLC_SPP_PVT_STAT_2__LEVEL_10_COUNTER_MASK                                                             0x0000003FL
#define RLC_SPP_PVT_STAT_2__LEVEL_11_COUNTER_MASK                                                             0x00000FC0L
#define RLC_SPP_PVT_STAT_2__LEVEL_12_COUNTER_MASK                                                             0x0003F000L
#define RLC_SPP_PVT_STAT_2__LEVEL_13_COUNTER_MASK                                                             0x00FC0000L
#define RLC_SPP_PVT_STAT_2__LEVEL_14_COUNTER_MASK                                                             0x7F000000L
//RLC_SPP_PVT_STAT_3
#define RLC_SPP_PVT_STAT_3__LEVEL_15_COUNTER__SHIFT                                                           0x0
#define RLC_SPP_PVT_STAT_3__LEVEL_15_COUNTER_MASK                                                             0x0000003FL
//RLC_SPP_PVT_LEVEL_MAX
#define RLC_SPP_PVT_LEVEL_MAX__LEVEL__SHIFT                                                                   0x0
#define RLC_SPP_PVT_LEVEL_MAX__LEVEL_MASK                                                                     0x0000000FL
//RLC_SPP_STALL_STATE_UPDATE
#define RLC_SPP_STALL_STATE_UPDATE__STALL__SHIFT                                                              0x0
#define RLC_SPP_STALL_STATE_UPDATE__ENABLE__SHIFT                                                             0x1
#define RLC_SPP_STALL_STATE_UPDATE__STALL_MASK                                                                0x00000001L
#define RLC_SPP_STALL_STATE_UPDATE__ENABLE_MASK                                                               0x00000002L
//RLC_SPP_PBB_INFO
#define RLC_SPP_PBB_INFO__PIPE0_OVERRIDE__SHIFT                                                               0x0
#define RLC_SPP_PBB_INFO__PIPE0_OVERRIDE_VALID__SHIFT                                                         0x1
#define RLC_SPP_PBB_INFO__PIPE1_OVERRIDE__SHIFT                                                               0x2
#define RLC_SPP_PBB_INFO__PIPE1_OVERRIDE_VALID__SHIFT                                                         0x3
#define RLC_SPP_PBB_INFO__PIPE0_OVERRIDE_MASK                                                                 0x00000001L
#define RLC_SPP_PBB_INFO__PIPE0_OVERRIDE_VALID_MASK                                                           0x00000002L
#define RLC_SPP_PBB_INFO__PIPE1_OVERRIDE_MASK                                                                 0x00000004L
#define RLC_SPP_PBB_INFO__PIPE1_OVERRIDE_VALID_MASK                                                           0x00000008L
//RLC_SPP_RESET
#define RLC_SPP_RESET__SSF_RESET__SHIFT                                                                       0x0
#define RLC_SPP_RESET__EVENT_ARB_RESET__SHIFT                                                                 0x1
#define RLC_SPP_RESET__CAM_RESET__SHIFT                                                                       0x2
#define RLC_SPP_RESET__PVT_RESET__SHIFT                                                                       0x3
#define RLC_SPP_RESET__SSF_RESET_MASK                                                                         0x00000001L
#define RLC_SPP_RESET__EVENT_ARB_RESET_MASK                                                                   0x00000002L
#define RLC_SPP_RESET__CAM_RESET_MASK                                                                         0x00000004L
#define RLC_SPP_RESET__PVT_RESET_MASK                                                                         0x00000008L
//RLC_SPM_SAMPLE_CNT
#define RLC_SPM_SAMPLE_CNT__COUNT__SHIFT                                                                      0x0
#define RLC_SPM_SAMPLE_CNT__COUNT_MASK                                                                        0xFFFFFFFFL
//RLC_RLCP_DOORBELL_RANGE
#define RLC_RLCP_DOORBELL_RANGE__LOWER_ADDR_RESERVED__SHIFT                                                   0x0
#define RLC_RLCP_DOORBELL_RANGE__LOWER_ADDR__SHIFT                                                            0x2
#define RLC_RLCP_DOORBELL_RANGE__UPPER_ADDR_RESERVED__SHIFT                                                   0x10
#define RLC_RLCP_DOORBELL_RANGE__UPPER_ADDR__SHIFT                                                            0x12
#define RLC_RLCP_DOORBELL_RANGE__LOWER_ADDR_RESERVED_MASK                                                     0x00000003L
#define RLC_RLCP_DOORBELL_RANGE__LOWER_ADDR_MASK                                                              0x00000FFCL
#define RLC_RLCP_DOORBELL_RANGE__UPPER_ADDR_RESERVED_MASK                                                     0x00030000L
#define RLC_RLCP_DOORBELL_RANGE__UPPER_ADDR_MASK                                                              0x0FFC0000L
//RLC_RLCP_DOORBELL_CNTL
#define RLC_RLCP_DOORBELL_CNTL__DOORBELL_0_MODE__SHIFT                                                        0x0
#define RLC_RLCP_DOORBELL_CNTL__DOORBELL_1_MODE__SHIFT                                                        0x2
#define RLC_RLCP_DOORBELL_CNTL__DOORBELL_2_MODE__SHIFT                                                        0x4
#define RLC_RLCP_DOORBELL_CNTL__DOORBELL_3_MODE__SHIFT                                                        0x6
#define RLC_RLCP_DOORBELL_CNTL__DOORBELL_ID__SHIFT                                                            0x10
#define RLC_RLCP_DOORBELL_CNTL__DOORBELL_ID_EN__SHIFT                                                         0x15
#define RLC_RLCP_DOORBELL_CNTL__DOORBELL_0_MODE_MASK                                                          0x00000003L
#define RLC_RLCP_DOORBELL_CNTL__DOORBELL_1_MODE_MASK                                                          0x0000000CL
#define RLC_RLCP_DOORBELL_CNTL__DOORBELL_2_MODE_MASK                                                          0x00000030L
#define RLC_RLCP_DOORBELL_CNTL__DOORBELL_3_MODE_MASK                                                          0x000000C0L
#define RLC_RLCP_DOORBELL_CNTL__DOORBELL_ID_MASK                                                              0x001F0000L
#define RLC_RLCP_DOORBELL_CNTL__DOORBELL_ID_EN_MASK                                                           0x00200000L
//RLC_RLCP_DOORBELL_STAT
#define RLC_RLCP_DOORBELL_STAT__DOORBELL_0_VALID__SHIFT                                                       0x0
#define RLC_RLCP_DOORBELL_STAT__DOORBELL_1_VALID__SHIFT                                                       0x1
#define RLC_RLCP_DOORBELL_STAT__DOORBELL_2_VALID__SHIFT                                                       0x2
#define RLC_RLCP_DOORBELL_STAT__DOORBELL_3_VALID__SHIFT                                                       0x3
#define RLC_RLCP_DOORBELL_STAT__DOORBELL_0_VALID_MASK                                                         0x00000001L
#define RLC_RLCP_DOORBELL_STAT__DOORBELL_1_VALID_MASK                                                         0x00000002L
#define RLC_RLCP_DOORBELL_STAT__DOORBELL_2_VALID_MASK                                                         0x00000004L
#define RLC_RLCP_DOORBELL_STAT__DOORBELL_3_VALID_MASK                                                         0x00000008L
//RLC_RLCP_DOORBELL_0_DATA_LO
#define RLC_RLCP_DOORBELL_0_DATA_LO__DATA__SHIFT                                                              0x0
#define RLC_RLCP_DOORBELL_0_DATA_LO__DATA_MASK                                                                0xFFFFFFFFL
//RLC_RLCP_DOORBELL_0_DATA_HI
#define RLC_RLCP_DOORBELL_0_DATA_HI__DATA__SHIFT                                                              0x0
#define RLC_RLCP_DOORBELL_0_DATA_HI__DATA_MASK                                                                0xFFFFFFFFL
//RLC_RLCP_DOORBELL_1_DATA_LO
#define RLC_RLCP_DOORBELL_1_DATA_LO__DATA__SHIFT                                                              0x0
#define RLC_RLCP_DOORBELL_1_DATA_LO__DATA_MASK                                                                0xFFFFFFFFL
//RLC_RLCP_DOORBELL_1_DATA_HI
#define RLC_RLCP_DOORBELL_1_DATA_HI__DATA__SHIFT                                                              0x0
#define RLC_RLCP_DOORBELL_1_DATA_HI__DATA_MASK                                                                0xFFFFFFFFL
//RLC_RLCP_DOORBELL_2_DATA_LO
#define RLC_RLCP_DOORBELL_2_DATA_LO__DATA__SHIFT                                                              0x0
#define RLC_RLCP_DOORBELL_2_DATA_LO__DATA_MASK                                                                0xFFFFFFFFL
//RLC_RLCP_DOORBELL_2_DATA_HI
#define RLC_RLCP_DOORBELL_2_DATA_HI__DATA__SHIFT                                                              0x0
#define RLC_RLCP_DOORBELL_2_DATA_HI__DATA_MASK                                                                0xFFFFFFFFL
//RLC_RLCP_DOORBELL_3_DATA_LO
#define RLC_RLCP_DOORBELL_3_DATA_LO__DATA__SHIFT                                                              0x0
#define RLC_RLCP_DOORBELL_3_DATA_LO__DATA_MASK                                                                0xFFFFFFFFL
//RLC_RLCP_DOORBELL_3_DATA_HI
#define RLC_RLCP_DOORBELL_3_DATA_HI__DATA__SHIFT                                                              0x0
#define RLC_RLCP_DOORBELL_3_DATA_HI__DATA_MASK                                                                0xFFFFFFFFL
//RLC_PCC_STRETCH_HYSTERESIS_CNTL
#define RLC_PCC_STRETCH_HYSTERESIS_CNTL__MAX_HYSTERESIS__SHIFT                                                0x0
#define RLC_PCC_STRETCH_HYSTERESIS_CNTL__HYSTERESIS_CNT__SHIFT                                                0x8
#define RLC_PCC_STRETCH_HYSTERESIS_CNTL__MAX_HYSTERESIS_MASK                                                  0x000000FFL
#define RLC_PCC_STRETCH_HYSTERESIS_CNTL__HYSTERESIS_CNT_MASK                                                  0x0000FF00L
//RLC_CAC_MASK_CNTL
#define RLC_CAC_MASK_CNTL__RLC_CAC_MASK__SHIFT                                                                0x0
#define RLC_CAC_MASK_CNTL__RLC_CAC_MASK_MASK                                                                  0xFFFFFFFFL
//RLC_GPU_CLOCK_COUNT_SPM_LSB
#define RLC_GPU_CLOCK_COUNT_SPM_LSB__GPU_CLOCKS_LSB__SHIFT                                                    0x0
#define RLC_GPU_CLOCK_COUNT_SPM_LSB__GPU_CLOCKS_LSB_MASK                                                      0xFFFFFFFFL
//RLC_GPU_CLOCK_COUNT_SPM_MSB
#define RLC_GPU_CLOCK_COUNT_SPM_MSB__GPU_CLOCKS_MSB__SHIFT                                                    0x0
#define RLC_GPU_CLOCK_COUNT_SPM_MSB__GPU_CLOCKS_MSB_MASK                                                      0xFFFFFFFFL
//RLC_SPM_THREAD_TRACE_CTRL
#define RLC_SPM_THREAD_TRACE_CTRL__THREAD_TRACE_INT_EN__SHIFT                                                 0x0
#define RLC_SPM_THREAD_TRACE_CTRL__THREAD_TRACE_INT_EN_MASK                                                   0x00000001L
//RLC_LB_CNTR_2
#define RLC_LB_CNTR_2__RLC_LOAD_BALANCE_CNTR__SHIFT                                                           0x0
#define RLC_LB_CNTR_2__RLC_LOAD_BALANCE_CNTR_MASK                                                             0xFFFFFFFFL
//RLC_CPAXI_DOORBELL_MON_CTRL
#define RLC_CPAXI_DOORBELL_MON_CTRL__EN__SHIFT                                                                0x0
#define RLC_CPAXI_DOORBELL_MON_CTRL__ID__SHIFT                                                                0x1
#define RLC_CPAXI_DOORBELL_MON_CTRL__EN_MASK                                                                  0x00000001L
#define RLC_CPAXI_DOORBELL_MON_CTRL__ID_MASK                                                                  0x0000003EL
//RLC_CPAXI_DOORBELL_MON_STAT
#define RLC_CPAXI_DOORBELL_MON_STAT__ID_MATCH__SHIFT                                                          0x0
#define RLC_CPAXI_DOORBELL_MON_STAT__MATCH_CLEAR__SHIFT                                                       0x1
#define RLC_CPAXI_DOORBELL_MON_STAT__ADDR__SHIFT                                                              0x2
#define RLC_CPAXI_DOORBELL_MON_STAT__ID_MATCH_MASK                                                            0x00000001L
#define RLC_CPAXI_DOORBELL_MON_STAT__MATCH_CLEAR_MASK                                                         0x00000002L
#define RLC_CPAXI_DOORBELL_MON_STAT__ADDR_MASK                                                                0x0FFFFFFCL
//RLC_CPAXI_DOORBELL_MON_DATA_LSB
#define RLC_CPAXI_DOORBELL_MON_DATA_LSB__DATA__SHIFT                                                          0x0
#define RLC_CPAXI_DOORBELL_MON_DATA_LSB__DATA_MASK                                                            0xFFFFFFFFL
//RLC_CPAXI_DOORBELL_MON_DATA_MSB
#define RLC_CPAXI_DOORBELL_MON_DATA_MSB__DATA__SHIFT                                                          0x0
#define RLC_CPAXI_DOORBELL_MON_DATA_MSB__DATA_MASK                                                            0xFFFFFFFFL
//RLC_XT_DOORBELL_RANGE
#define RLC_XT_DOORBELL_RANGE__LOWER_ADDR_RESERVED__SHIFT                                                     0x0
#define RLC_XT_DOORBELL_RANGE__LOWER_ADDR__SHIFT                                                              0x2
#define RLC_XT_DOORBELL_RANGE__UPPER_ADDR_RESERVED__SHIFT                                                     0x10
#define RLC_XT_DOORBELL_RANGE__UPPER_ADDR__SHIFT                                                              0x12
#define RLC_XT_DOORBELL_RANGE__LOWER_ADDR_RESERVED_MASK                                                       0x00000003L
#define RLC_XT_DOORBELL_RANGE__LOWER_ADDR_MASK                                                                0x00000FFCL
#define RLC_XT_DOORBELL_RANGE__UPPER_ADDR_RESERVED_MASK                                                       0x00030000L
#define RLC_XT_DOORBELL_RANGE__UPPER_ADDR_MASK                                                                0x0FFC0000L
//RLC_XT_DOORBELL_CNTL
#define RLC_XT_DOORBELL_CNTL__DOORBELL_0_MODE__SHIFT                                                          0x0
#define RLC_XT_DOORBELL_CNTL__DOORBELL_1_MODE__SHIFT                                                          0x2
#define RLC_XT_DOORBELL_CNTL__DOORBELL_2_MODE__SHIFT                                                          0x4
#define RLC_XT_DOORBELL_CNTL__DOORBELL_3_MODE__SHIFT                                                          0x6
#define RLC_XT_DOORBELL_CNTL__DOORBELL_ID__SHIFT                                                              0x10
#define RLC_XT_DOORBELL_CNTL__DOORBELL_ID_EN__SHIFT                                                           0x15
#define RLC_XT_DOORBELL_CNTL__DOORBELL_0_MODE_MASK                                                            0x00000003L
#define RLC_XT_DOORBELL_CNTL__DOORBELL_1_MODE_MASK                                                            0x0000000CL
#define RLC_XT_DOORBELL_CNTL__DOORBELL_2_MODE_MASK                                                            0x00000030L
#define RLC_XT_DOORBELL_CNTL__DOORBELL_3_MODE_MASK                                                            0x000000C0L
#define RLC_XT_DOORBELL_CNTL__DOORBELL_ID_MASK                                                                0x001F0000L
#define RLC_XT_DOORBELL_CNTL__DOORBELL_ID_EN_MASK                                                             0x00200000L
//RLC_XT_DOORBELL_STAT
#define RLC_XT_DOORBELL_STAT__DOORBELL_0_VALID__SHIFT                                                         0x0
#define RLC_XT_DOORBELL_STAT__DOORBELL_1_VALID__SHIFT                                                         0x1
#define RLC_XT_DOORBELL_STAT__DOORBELL_2_VALID__SHIFT                                                         0x2
#define RLC_XT_DOORBELL_STAT__DOORBELL_3_VALID__SHIFT                                                         0x3
#define RLC_XT_DOORBELL_STAT__DOORBELL_0_VALID_MASK                                                           0x00000001L
#define RLC_XT_DOORBELL_STAT__DOORBELL_1_VALID_MASK                                                           0x00000002L
#define RLC_XT_DOORBELL_STAT__DOORBELL_2_VALID_MASK                                                           0x00000004L
#define RLC_XT_DOORBELL_STAT__DOORBELL_3_VALID_MASK                                                           0x00000008L
//RLC_XT_DOORBELL_0_DATA_LO
#define RLC_XT_DOORBELL_0_DATA_LO__DATA__SHIFT                                                                0x0
#define RLC_XT_DOORBELL_0_DATA_LO__DATA_MASK                                                                  0xFFFFFFFFL
//RLC_XT_DOORBELL_0_DATA_HI
#define RLC_XT_DOORBELL_0_DATA_HI__DATA__SHIFT                                                                0x0
#define RLC_XT_DOORBELL_0_DATA_HI__DATA_MASK                                                                  0xFFFFFFFFL
//RLC_XT_DOORBELL_1_DATA_LO
#define RLC_XT_DOORBELL_1_DATA_LO__DATA__SHIFT                                                                0x0
#define RLC_XT_DOORBELL_1_DATA_LO__DATA_MASK                                                                  0xFFFFFFFFL
//RLC_XT_DOORBELL_1_DATA_HI
#define RLC_XT_DOORBELL_1_DATA_HI__DATA__SHIFT                                                                0x0
#define RLC_XT_DOORBELL_1_DATA_HI__DATA_MASK                                                                  0xFFFFFFFFL
//RLC_XT_DOORBELL_2_DATA_LO
#define RLC_XT_DOORBELL_2_DATA_LO__DATA__SHIFT                                                                0x0
#define RLC_XT_DOORBELL_2_DATA_LO__DATA_MASK                                                                  0xFFFFFFFFL
//RLC_XT_DOORBELL_2_DATA_HI
#define RLC_XT_DOORBELL_2_DATA_HI__DATA__SHIFT                                                                0x0
#define RLC_XT_DOORBELL_2_DATA_HI__DATA_MASK                                                                  0xFFFFFFFFL
//RLC_XT_DOORBELL_3_DATA_LO
#define RLC_XT_DOORBELL_3_DATA_LO__DATA__SHIFT                                                                0x0
#define RLC_XT_DOORBELL_3_DATA_LO__DATA_MASK                                                                  0xFFFFFFFFL
//RLC_XT_DOORBELL_3_DATA_HI
#define RLC_XT_DOORBELL_3_DATA_HI__DATA__SHIFT                                                                0x0
#define RLC_XT_DOORBELL_3_DATA_HI__DATA_MASK                                                                  0xFFFFFFFFL


// addressBlock: gc_rlcrdec
//RLC_SPP_CAM_ADDR
#define RLC_SPP_CAM_ADDR__ADDR__SHIFT                                                                         0x0
#define RLC_SPP_CAM_ADDR__ADDR_MASK                                                                           0x000000FFL
//RLC_SPP_CAM_DATA
#define RLC_SPP_CAM_DATA__DATA__SHIFT                                                                         0x0
#define RLC_SPP_CAM_DATA__TAG__SHIFT                                                                          0x8
#define RLC_SPP_CAM_DATA__DATA_MASK                                                                           0x000000FFL
#define RLC_SPP_CAM_DATA__TAG_MASK                                                                            0xFFFFFF00L
//RLC_SPP_CAM_EXT_ADDR
#define RLC_SPP_CAM_EXT_ADDR__ADDR__SHIFT                                                                     0x0
#define RLC_SPP_CAM_EXT_ADDR__ADDR_MASK                                                                       0x000000FFL
//RLC_SPP_CAM_EXT_DATA
#define RLC_SPP_CAM_EXT_DATA__VALID__SHIFT                                                                    0x0
#define RLC_SPP_CAM_EXT_DATA__LOCK__SHIFT                                                                     0x1
#define RLC_SPP_CAM_EXT_DATA__VALID_MASK                                                                      0x00000001L
#define RLC_SPP_CAM_EXT_DATA__LOCK_MASK                                                                       0x00000002L
//RLC_PACE_SCRATCH_ADDR
#define RLC_PACE_SCRATCH_ADDR__ADDR__SHIFT                                                                    0x0
#define RLC_PACE_SCRATCH_ADDR__ADDR_MASK                                                                      0x0000FFFFL
//RLC_PACE_SCRATCH_DATA
#define RLC_PACE_SCRATCH_DATA__DATA__SHIFT                                                                    0x0
#define RLC_PACE_SCRATCH_DATA__DATA_MASK                                                                      0xFFFFFFFFL


// addressBlock: gc_rlcsdec
//RLC_RLCS_DEC_START
//RLC_RLCS_DEC_DUMP_ADDR
//RLC_RLCS_EXCEPTION_REG_1
#define RLC_RLCS_EXCEPTION_REG_1__ADDR__SHIFT                                                                 0x0
#define RLC_RLCS_EXCEPTION_REG_1__RESERVED__SHIFT                                                             0x12
#define RLC_RLCS_EXCEPTION_REG_1__ADDR_MASK                                                                   0x0003FFFFL
#define RLC_RLCS_EXCEPTION_REG_1__RESERVED_MASK                                                               0xFFFC0000L
//RLC_RLCS_EXCEPTION_REG_2
#define RLC_RLCS_EXCEPTION_REG_2__ADDR__SHIFT                                                                 0x0
#define RLC_RLCS_EXCEPTION_REG_2__RESERVED__SHIFT                                                             0x12
#define RLC_RLCS_EXCEPTION_REG_2__ADDR_MASK                                                                   0x0003FFFFL
#define RLC_RLCS_EXCEPTION_REG_2__RESERVED_MASK                                                               0xFFFC0000L
//RLC_RLCS_EXCEPTION_REG_3
#define RLC_RLCS_EXCEPTION_REG_3__ADDR__SHIFT                                                                 0x0
#define RLC_RLCS_EXCEPTION_REG_3__RESERVED__SHIFT                                                             0x12
#define RLC_RLCS_EXCEPTION_REG_3__ADDR_MASK                                                                   0x0003FFFFL
#define RLC_RLCS_EXCEPTION_REG_3__RESERVED_MASK                                                               0xFFFC0000L
//RLC_RLCS_EXCEPTION_REG_4
#define RLC_RLCS_EXCEPTION_REG_4__ADDR__SHIFT                                                                 0x0
#define RLC_RLCS_EXCEPTION_REG_4__RESERVED__SHIFT                                                             0x12
#define RLC_RLCS_EXCEPTION_REG_4__ADDR_MASK                                                                   0x0003FFFFL
#define RLC_RLCS_EXCEPTION_REG_4__RESERVED_MASK                                                               0xFFFC0000L
//RLC_RLCS_GENERAL_6
#define RLC_RLCS_GENERAL_6__DATA__SHIFT                                                                       0x0
#define RLC_RLCS_GENERAL_6__DATA_MASK                                                                         0xFFFFFFFFL
//RLC_RLCS_GENERAL_7
#define RLC_RLCS_GENERAL_7__DATA__SHIFT                                                                       0x0
#define RLC_RLCS_GENERAL_7__DATA_MASK                                                                         0xFFFFFFFFL
//RLC_RLCS_CGCG_REQUEST
#define RLC_RLCS_CGCG_REQUEST__CGCG_REQUEST__SHIFT                                                            0x0
#define RLC_RLCS_CGCG_REQUEST__CGCG_REQUEST_3D__SHIFT                                                         0x1
#define RLC_RLCS_CGCG_REQUEST__RESERVED__SHIFT                                                                0x2
#define RLC_RLCS_CGCG_REQUEST__CGCG_REQUEST_MASK                                                              0x00000001L
#define RLC_RLCS_CGCG_REQUEST__CGCG_REQUEST_3D_MASK                                                           0x00000002L
#define RLC_RLCS_CGCG_REQUEST__RESERVED_MASK                                                                  0xFFFFFFFCL
//RLC_RLCS_CGCG_STATUS
#define RLC_RLCS_CGCG_STATUS__CGCG_RAMP_STATUS__SHIFT                                                         0x0
#define RLC_RLCS_CGCG_STATUS__GFX_CLK_STATUS__SHIFT                                                           0x2
#define RLC_RLCS_CGCG_STATUS__CGCG_RAMP_STATUS_3D__SHIFT                                                      0x3
#define RLC_RLCS_CGCG_STATUS__GFX_CLK_STATUS_3D__SHIFT                                                        0x5
#define RLC_RLCS_CGCG_STATUS__RESERVED__SHIFT                                                                 0x6
#define RLC_RLCS_CGCG_STATUS__CGCG_RAMP_STATUS_MASK                                                           0x00000003L
#define RLC_RLCS_CGCG_STATUS__GFX_CLK_STATUS_MASK                                                             0x00000004L
#define RLC_RLCS_CGCG_STATUS__CGCG_RAMP_STATUS_3D_MASK                                                        0x00000018L
#define RLC_RLCS_CGCG_STATUS__GFX_CLK_STATUS_3D_MASK                                                          0x00000020L
#define RLC_RLCS_CGCG_STATUS__RESERVED_MASK                                                                   0xFFFFFFC0L
//RLC_RLCS_SMU_GFXCLK_STATUS
#define RLC_RLCS_SMU_GFXCLK_STATUS__SMU_GFXCLK_DONETOG__SHIFT                                                 0x0
#define RLC_RLCS_SMU_GFXCLK_STATUS__SMU_GFXMUX_CUR_VALUE__SHIFT                                               0x1
#define RLC_RLCS_SMU_GFXCLK_STATUS__SMU_GFXCLK_STRETCH_PCC__SHIFT                                             0x2
#define RLC_RLCS_SMU_GFXCLK_STATUS__SMU_GFXCLK_PCC_CTRL__SHIFT                                                0x3
#define RLC_RLCS_SMU_GFXCLK_STATUS__SMU_GFXCLK_DONETOG_MASK                                                   0x00000001L
#define RLC_RLCS_SMU_GFXCLK_STATUS__SMU_GFXMUX_CUR_VALUE_MASK                                                 0x00000002L
#define RLC_RLCS_SMU_GFXCLK_STATUS__SMU_GFXCLK_STRETCH_PCC_MASK                                               0x00000004L
#define RLC_RLCS_SMU_GFXCLK_STATUS__SMU_GFXCLK_PCC_CTRL_MASK                                                  0x00000008L
//RLC_RLCS_SMU_GFXCLK_CONTROL
#define RLC_RLCS_SMU_GFXCLK_CONTROL__SMU_GFXCLK_CHGTOG__SHIFT                                                 0x0
#define RLC_RLCS_SMU_GFXCLK_CONTROL__SMU_GFXCLK_DIVIDER__SHIFT                                                0x1
#define RLC_RLCS_SMU_GFXCLK_CONTROL__SMU_GFXMUX_SEL__SHIFT                                                    0x8
#define RLC_RLCS_SMU_GFXCLK_CONTROL__RESERVED__SHIFT                                                          0x9
#define RLC_RLCS_SMU_GFXCLK_CONTROL__SMU_GFXCLK_CHGTOG_MASK                                                   0x00000001L
#define RLC_RLCS_SMU_GFXCLK_CONTROL__SMU_GFXCLK_DIVIDER_MASK                                                  0x000000FEL
#define RLC_RLCS_SMU_GFXCLK_CONTROL__SMU_GFXMUX_SEL_MASK                                                      0x00000100L
#define RLC_RLCS_SMU_GFXCLK_CONTROL__RESERVED_MASK                                                            0xFFFFFE00L
//RLC_RLCS_SOC_DS_CNTL
#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_ALLOW__SHIFT                                                         0x0
#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK__SHIFT                                                 0x1
#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK__SHIFT                                                  0x2
#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_GFX_PWR_STALLED_MASK__SHIFT                                          0x6
#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_NON3D_PWR_STALLED_MASK__SHIFT                                        0x7
#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_0_BUSY_MASK__SHIFT                                              0x10
#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_1_BUSY_MASK__SHIFT                                              0x11
#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_2_BUSY_MASK__SHIFT                                              0x12
#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_3_BUSY_MASK__SHIFT                                              0x13
#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_4_BUSY_MASK__SHIFT                                              0x14
#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_5_BUSY_MASK__SHIFT                                              0x15
#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_6_BUSY_MASK__SHIFT                                              0x16
#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_7_BUSY_MASK__SHIFT                                              0x17
#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_ALLOW_MASK                                                           0x00000001L
#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK_MASK                                                   0x00000002L
#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK_MASK                                                    0x00000004L
#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_GFX_PWR_STALLED_MASK_MASK                                            0x00000040L
#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_NON3D_PWR_STALLED_MASK_MASK                                          0x00000080L
#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_0_BUSY_MASK_MASK                                                0x00010000L
#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_1_BUSY_MASK_MASK                                                0x00020000L
#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_2_BUSY_MASK_MASK                                                0x00040000L
#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_3_BUSY_MASK_MASK                                                0x00080000L
#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_4_BUSY_MASK_MASK                                                0x00100000L
#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_5_BUSY_MASK_MASK                                                0x00200000L
#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_6_BUSY_MASK_MASK                                                0x00400000L
#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_7_BUSY_MASK_MASK                                                0x00800000L
//RLC_RLCS_GFX_DS_CNTL
#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_ALLOW__SHIFT                                                         0x0
#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK__SHIFT                                                 0x1
#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK__SHIFT                                                  0x2
#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_GFX_PWR_STALLED_MASK__SHIFT                                          0x6
#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_NON3D_PWR_STALLED_MASK__SHIFT                                        0x7
#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_0_BUSY_MASK__SHIFT                                              0x10
#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_1_BUSY_MASK__SHIFT                                              0x11
#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_2_BUSY_MASK__SHIFT                                              0x12
#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_3_BUSY_MASK__SHIFT                                              0x13
#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_4_BUSY_MASK__SHIFT                                              0x14
#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_5_BUSY_MASK__SHIFT                                              0x15
#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_6_BUSY_MASK__SHIFT                                              0x16
#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_7_BUSY_MASK__SHIFT                                              0x17
#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_ALLOW_MASK                                                           0x00000001L
#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK_MASK                                                   0x00000002L
#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK_MASK                                                    0x00000004L
#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_GFX_PWR_STALLED_MASK_MASK                                            0x00000040L
#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_NON3D_PWR_STALLED_MASK_MASK                                          0x00000080L
#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_0_BUSY_MASK_MASK                                                0x00010000L
#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_1_BUSY_MASK_MASK                                                0x00020000L
#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_2_BUSY_MASK_MASK                                                0x00040000L
#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_3_BUSY_MASK_MASK                                                0x00080000L
#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_4_BUSY_MASK_MASK                                                0x00100000L
#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_5_BUSY_MASK_MASK                                                0x00200000L
#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_6_BUSY_MASK_MASK                                                0x00400000L
#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_7_BUSY_MASK_MASK                                                0x00800000L
//RLC_GPM_STAT
#define RLC_GPM_STAT__RLC_BUSY__SHIFT                                                                         0x0
#define RLC_GPM_STAT__GFX_POWER_STATUS__SHIFT                                                                 0x1
#define RLC_GPM_STAT__GFX_CLOCK_STATUS__SHIFT                                                                 0x2
#define RLC_GPM_STAT__GFX_LS_STATUS__SHIFT                                                                    0x3
#define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS__SHIFT                                                        0x4
#define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED__SHIFT                                                        0x5
#define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED__SHIFT                                                        0x6
#define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED__SHIFT                                                         0x7
#define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED__SHIFT                                                         0x8
#define RLC_GPM_STAT__SAVING_REGISTERS__SHIFT                                                                 0x9
#define RLC_GPM_STAT__RESTORING_REGISTERS__SHIFT                                                              0xa
#define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE__SHIFT                                                0xb
#define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE__SHIFT                                                  0xc
#define RLC_GPM_STAT__STATIC_WGP_POWERING_UP__SHIFT                                                           0xd
#define RLC_GPM_STAT__STATIC_WGP_POWERING_DOWN__SHIFT                                                         0xe
#define RLC_GPM_STAT__DYN_WGP_POWERING_UP__SHIFT                                                              0xf
#define RLC_GPM_STAT__DYN_WGP_POWERING_DOWN__SHIFT                                                            0x10
#define RLC_GPM_STAT__ABORTED_PD_SEQUENCE__SHIFT                                                              0x11
#define RLC_GPM_STAT__CMP_power_status__SHIFT                                                                 0x12
#define RLC_GPM_STAT__GFX_LS_STATUS_3D__SHIFT                                                                 0x13
#define RLC_GPM_STAT__GFX_CLOCK_STATUS_3D__SHIFT                                                              0x14
#define RLC_GPM_STAT__MGCG_OVERRIDE_STATUS__SHIFT                                                             0x15
#define RLC_GPM_STAT__RLC_EXEC_ROM_CODE__SHIFT                                                                0x16
#define RLC_GPM_STAT__FGCG_OVERRIDE_STATUS__SHIFT                                                             0x17
#define RLC_GPM_STAT__PG_ERROR_STATUS__SHIFT                                                                  0x18
#define RLC_GPM_STAT__RLC_BUSY_MASK                                                                           0x00000001L
#define RLC_GPM_STAT__GFX_POWER_STATUS_MASK                                                                   0x00000002L
#define RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK                                                                   0x00000004L
#define RLC_GPM_STAT__GFX_LS_STATUS_MASK                                                                      0x00000008L
#define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK                                                          0x00000010L
#define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED_MASK                                                          0x00000020L
#define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED_MASK                                                          0x00000040L
#define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED_MASK                                                           0x00000080L
#define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED_MASK                                                           0x00000100L
#define RLC_GPM_STAT__SAVING_REGISTERS_MASK                                                                   0x00000200L
#define RLC_GPM_STAT__RESTORING_REGISTERS_MASK                                                                0x00000400L
#define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE_MASK                                                  0x00000800L
#define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE_MASK                                                    0x00001000L
#define RLC_GPM_STAT__STATIC_WGP_POWERING_UP_MASK                                                             0x00002000L
#define RLC_GPM_STAT__STATIC_WGP_POWERING_DOWN_MASK                                                           0x00004000L
#define RLC_GPM_STAT__DYN_WGP_POWERING_UP_MASK                                                                0x00008000L
#define RLC_GPM_STAT__DYN_WGP_POWERING_DOWN_MASK                                                              0x00010000L
#define RLC_GPM_STAT__ABORTED_PD_SEQUENCE_MASK                                                                0x00020000L
#define RLC_GPM_STAT__CMP_power_status_MASK                                                                   0x00040000L
#define RLC_GPM_STAT__GFX_LS_STATUS_3D_MASK                                                                   0x00080000L
#define RLC_GPM_STAT__GFX_CLOCK_STATUS_3D_MASK                                                                0x00100000L
#define RLC_GPM_STAT__MGCG_OVERRIDE_STATUS_MASK                                                               0x00200000L
#define RLC_GPM_STAT__RLC_EXEC_ROM_CODE_MASK                                                                  0x00400000L
#define RLC_GPM_STAT__FGCG_OVERRIDE_STATUS_MASK                                                               0x00800000L
#define RLC_GPM_STAT__PG_ERROR_STATUS_MASK                                                                    0xFF000000L
//RLC_RLCS_GPM_STAT
#define RLC_RLCS_GPM_STAT__RLC_BUSY__SHIFT                                                                    0x0
#define RLC_RLCS_GPM_STAT__GFX_POWER_STATUS__SHIFT                                                            0x1
#define RLC_RLCS_GPM_STAT__GFX_CLOCK_STATUS__SHIFT                                                            0x2
#define RLC_RLCS_GPM_STAT__GFX_LS_STATUS__SHIFT                                                               0x3
#define RLC_RLCS_GPM_STAT__GFX_PIPELINE_POWER_STATUS__SHIFT                                                   0x4
#define RLC_RLCS_GPM_STAT__CNTX_IDLE_BEING_PROCESSED__SHIFT                                                   0x5
#define RLC_RLCS_GPM_STAT__CNTX_BUSY_BEING_PROCESSED__SHIFT                                                   0x6
#define RLC_RLCS_GPM_STAT__GFX_IDLE_BEING_PROCESSED__SHIFT                                                    0x7
#define RLC_RLCS_GPM_STAT__CMP_BUSY_BEING_PROCESSED__SHIFT                                                    0x8
#define RLC_RLCS_GPM_STAT__SAVING_REGISTERS__SHIFT                                                            0x9
#define RLC_RLCS_GPM_STAT__RESTORING_REGISTERS__SHIFT                                                         0xa
#define RLC_RLCS_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE__SHIFT                                           0xb
#define RLC_RLCS_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE__SHIFT                                             0xc
#define RLC_RLCS_GPM_STAT__STATIC_WGP_POWERING_UP__SHIFT                                                      0xd
#define RLC_RLCS_GPM_STAT__STATIC_WGP_POWERING_DOWN__SHIFT                                                    0xe
#define RLC_RLCS_GPM_STAT__DYN_WGP_POWERING_UP__SHIFT                                                         0xf
#define RLC_RLCS_GPM_STAT__DYN_WGP_POWERING_DOWN__SHIFT                                                       0x10
#define RLC_RLCS_GPM_STAT__ABORTED_PD_SEQUENCE__SHIFT                                                         0x11
#define RLC_RLCS_GPM_STAT__CMP_POWER_STATUS__SHIFT                                                            0x12
#define RLC_RLCS_GPM_STAT__GFX_LS_STATUS_3D__SHIFT                                                            0x13
#define RLC_RLCS_GPM_STAT__GFX_CLOCK_STATUS_3D__SHIFT                                                         0x14
#define RLC_RLCS_GPM_STAT__MGCG_OVERRIDE_STATUS__SHIFT                                                        0x15
#define RLC_RLCS_GPM_STAT__RLC_EXEC_ROM_CODE__SHIFT                                                           0x16
#define RLC_RLCS_GPM_STAT__FGCG_OVERRIDE_STATUS__SHIFT                                                        0x17
#define RLC_RLCS_GPM_STAT__PG_ERROR_STATUS__SHIFT                                                             0x18
#define RLC_RLCS_GPM_STAT__RLC_BUSY_MASK                                                                      0x00000001L
#define RLC_RLCS_GPM_STAT__GFX_POWER_STATUS_MASK                                                              0x00000002L
#define RLC_RLCS_GPM_STAT__GFX_CLOCK_STATUS_MASK                                                              0x00000004L
#define RLC_RLCS_GPM_STAT__GFX_LS_STATUS_MASK                                                                 0x00000008L
#define RLC_RLCS_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK                                                     0x00000010L
#define RLC_RLCS_GPM_STAT__CNTX_IDLE_BEING_PROCESSED_MASK                                                     0x00000020L
#define RLC_RLCS_GPM_STAT__CNTX_BUSY_BEING_PROCESSED_MASK                                                     0x00000040L
#define RLC_RLCS_GPM_STAT__GFX_IDLE_BEING_PROCESSED_MASK                                                      0x00000080L
#define RLC_RLCS_GPM_STAT__CMP_BUSY_BEING_PROCESSED_MASK                                                      0x00000100L
#define RLC_RLCS_GPM_STAT__SAVING_REGISTERS_MASK                                                              0x00000200L
#define RLC_RLCS_GPM_STAT__RESTORING_REGISTERS_MASK                                                           0x00000400L
#define RLC_RLCS_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE_MASK                                             0x00000800L
#define RLC_RLCS_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE_MASK                                               0x00001000L
#define RLC_RLCS_GPM_STAT__STATIC_WGP_POWERING_UP_MASK                                                        0x00002000L
#define RLC_RLCS_GPM_STAT__STATIC_WGP_POWERING_DOWN_MASK                                                      0x00004000L
#define RLC_RLCS_GPM_STAT__DYN_WGP_POWERING_UP_MASK                                                           0x00008000L
#define RLC_RLCS_GPM_STAT__DYN_WGP_POWERING_DOWN_MASK                                                         0x00010000L
#define RLC_RLCS_GPM_STAT__ABORTED_PD_SEQUENCE_MASK                                                           0x00020000L
#define RLC_RLCS_GPM_STAT__CMP_POWER_STATUS_MASK                                                              0x00040000L
#define RLC_RLCS_GPM_STAT__GFX_LS_STATUS_3D_MASK                                                              0x00080000L
#define RLC_RLCS_GPM_STAT__GFX_CLOCK_STATUS_3D_MASK                                                           0x00100000L
#define RLC_RLCS_GPM_STAT__MGCG_OVERRIDE_STATUS_MASK                                                          0x00200000L
#define RLC_RLCS_GPM_STAT__RLC_EXEC_ROM_CODE_MASK                                                             0x00400000L
#define RLC_RLCS_GPM_STAT__FGCG_OVERRIDE_STATUS_MASK                                                          0x00800000L
#define RLC_RLCS_GPM_STAT__PG_ERROR_STATUS_MASK                                                               0xFF000000L
//RLC_RLCS_ABORTED_PD_SEQUENCE
#define RLC_RLCS_ABORTED_PD_SEQUENCE__APS__SHIFT                                                              0x0
#define RLC_RLCS_ABORTED_PD_SEQUENCE__RESERVED__SHIFT                                                         0x10
#define RLC_RLCS_ABORTED_PD_SEQUENCE__APS_MASK                                                                0x0000FFFFL
#define RLC_RLCS_ABORTED_PD_SEQUENCE__RESERVED_MASK                                                           0xFFFF0000L
//RLC_RLCS_DIDT_FORCE_STALL
#define RLC_RLCS_DIDT_FORCE_STALL__DFS__SHIFT                                                                 0x0
#define RLC_RLCS_DIDT_FORCE_STALL__RESERVED__SHIFT                                                            0x3
#define RLC_RLCS_DIDT_FORCE_STALL__DFS_MASK                                                                   0x00000007L
#define RLC_RLCS_DIDT_FORCE_STALL__RESERVED_MASK                                                              0xFFFFFFF8L
//RLC_RLCS_IOV_CMD_STATUS
#define RLC_RLCS_IOV_CMD_STATUS__DATA__SHIFT                                                                  0x0
#define RLC_RLCS_IOV_CMD_STATUS__DATA_MASK                                                                    0xFFFFFFFFL
//RLC_RLCS_IOV_CNTX_LOC_SIZE
#define RLC_RLCS_IOV_CNTX_LOC_SIZE__DATA__SHIFT                                                               0x0
#define RLC_RLCS_IOV_CNTX_LOC_SIZE__RESERVED__SHIFT                                                           0x8
#define RLC_RLCS_IOV_CNTX_LOC_SIZE__DATA_MASK                                                                 0x000000FFL
#define RLC_RLCS_IOV_CNTX_LOC_SIZE__RESERVED_MASK                                                             0xFFFFFF00L
//RLC_RLCS_IOV_SCH_BLOCK
#define RLC_RLCS_IOV_SCH_BLOCK__DATA__SHIFT                                                                   0x0
#define RLC_RLCS_IOV_SCH_BLOCK__DATA_MASK                                                                     0xFFFFFFFFL
//RLC_RLCS_IOV_VM_BUSY_STATUS
#define RLC_RLCS_IOV_VM_BUSY_STATUS__DATA__SHIFT                                                              0x0
#define RLC_RLCS_IOV_VM_BUSY_STATUS__DATA_MASK                                                                0xFFFFFFFFL
//RLC_RLCS_GPM_STAT_2
#define RLC_RLCS_GPM_STAT_2__TC_TRANS_ERROR__SHIFT                                                            0x0
#define RLC_RLCS_GPM_STAT_2__RLC_PWR_NON3D_STALLED__SHIFT                                                     0x1
#define RLC_RLCS_GPM_STAT_2__GFX_PWR_STALLED_STATUS__SHIFT                                                    0x2
#define RLC_RLCS_GPM_STAT_2__GFX_ULV_STATUS__SHIFT                                                            0x3
#define RLC_RLCS_GPM_STAT_2__GFX_GENERAL_STATUS__SHIFT                                                        0x4
#define RLC_RLCS_GPM_STAT_2__RESERVED__SHIFT                                                                  0x5
#define RLC_RLCS_GPM_STAT_2__TC_TRANS_ERROR_MASK                                                              0x00000001L
#define RLC_RLCS_GPM_STAT_2__RLC_PWR_NON3D_STALLED_MASK                                                       0x00000002L
#define RLC_RLCS_GPM_STAT_2__GFX_PWR_STALLED_STATUS_MASK                                                      0x00000004L
#define RLC_RLCS_GPM_STAT_2__GFX_ULV_STATUS_MASK                                                              0x00000008L
#define RLC_RLCS_GPM_STAT_2__GFX_GENERAL_STATUS_MASK                                                          0x00000010L
#define RLC_RLCS_GPM_STAT_2__RESERVED_MASK                                                                    0xFFFFFFE0L
//RLC_RLCS_GRBM_SOFT_RESET
#define RLC_RLCS_GRBM_SOFT_RESET__RESET__SHIFT                                                                0x0
#define RLC_RLCS_GRBM_SOFT_RESET__RESERVED__SHIFT                                                             0x1
#define RLC_RLCS_GRBM_SOFT_RESET__RESET_MASK                                                                  0x00000001L
#define RLC_RLCS_GRBM_SOFT_RESET__RESERVED_MASK                                                               0xFFFFFFFEL
//RLC_RLCS_PG_CHANGE_STATUS
#define RLC_RLCS_PG_CHANGE_STATUS__PG_CNTL_CHANGED__SHIFT                                                     0x0
#define RLC_RLCS_PG_CHANGE_STATUS__PG_REG_CHANGED__SHIFT                                                      0x1
#define RLC_RLCS_PG_CHANGE_STATUS__DYN_PG_STATUS_CHANGED__SHIFT                                               0x2
#define RLC_RLCS_PG_CHANGE_STATUS__DYN_PG_REQ_CHANGED__SHIFT                                                  0x3
#define RLC_RLCS_PG_CHANGE_STATUS__RESERVED__SHIFT                                                            0x4
#define RLC_RLCS_PG_CHANGE_STATUS__PG_CNTL_CHANGED_MASK                                                       0x00000001L
#define RLC_RLCS_PG_CHANGE_STATUS__PG_REG_CHANGED_MASK                                                        0x00000002L
#define RLC_RLCS_PG_CHANGE_STATUS__DYN_PG_STATUS_CHANGED_MASK                                                 0x00000004L
#define RLC_RLCS_PG_CHANGE_STATUS__DYN_PG_REQ_CHANGED_MASK                                                    0x00000008L
#define RLC_RLCS_PG_CHANGE_STATUS__RESERVED_MASK                                                              0xFFFFFFF0L
//RLC_RLCS_PG_CHANGE_READ
#define RLC_RLCS_PG_CHANGE_READ__PG_CNTL_CHANGED__SHIFT                                                       0x0
#define RLC_RLCS_PG_CHANGE_READ__PG_REG_CHANGED__SHIFT                                                        0x1
#define RLC_RLCS_PG_CHANGE_READ__DYN_PG_STATUS_CHANGED__SHIFT                                                 0x2
#define RLC_RLCS_PG_CHANGE_READ__DYN_PG_REQ_CHANGED__SHIFT                                                    0x3
#define RLC_RLCS_PG_CHANGE_READ__RESERVED__SHIFT                                                              0x4
#define RLC_RLCS_PG_CHANGE_READ__PG_CNTL_CHANGED_MASK                                                         0x00000001L
#define RLC_RLCS_PG_CHANGE_READ__PG_REG_CHANGED_MASK                                                          0x00000002L
#define RLC_RLCS_PG_CHANGE_READ__DYN_PG_STATUS_CHANGED_MASK                                                   0x00000004L
#define RLC_RLCS_PG_CHANGE_READ__DYN_PG_REQ_CHANGED_MASK                                                      0x00000008L
#define RLC_RLCS_PG_CHANGE_READ__RESERVED_MASK                                                                0xFFFFFFF0L
//RLC_RLCS_LB_STATUS
#define RLC_RLCS_LB_STATUS__LB_CNTR_START__SHIFT                                                              0x0
#define RLC_RLCS_LB_STATUS__LB_CNTR_STOP__SHIFT                                                               0x1
#define RLC_RLCS_LB_STATUS__LB_CNTR_1_MAX_FLAG__SHIFT                                                         0x2
#define RLC_RLCS_LB_STATUS__LB_CNTR_2_MAX_FLAG__SHIFT                                                         0x3
#define RLC_RLCS_LB_STATUS__LBPW_DISABLE_FLAG__SHIFT                                                          0x4
#define RLC_RLCS_LB_STATUS__RESERVED__SHIFT                                                                   0x5
#define RLC_RLCS_LB_STATUS__LB_CNTR_START_MASK                                                                0x00000001L
#define RLC_RLCS_LB_STATUS__LB_CNTR_STOP_MASK                                                                 0x00000002L
#define RLC_RLCS_LB_STATUS__LB_CNTR_1_MAX_FLAG_MASK                                                           0x00000004L
#define RLC_RLCS_LB_STATUS__LB_CNTR_2_MAX_FLAG_MASK                                                           0x00000008L
#define RLC_RLCS_LB_STATUS__LBPW_DISABLE_FLAG_MASK                                                            0x00000010L
#define RLC_RLCS_LB_STATUS__RESERVED_MASK                                                                     0xFFFFFFE0L
//RLC_RLCS_LB_READ
#define RLC_RLCS_LB_READ__LB_CNTR_START__SHIFT                                                                0x0
#define RLC_RLCS_LB_READ__LB_CNTR_STOP__SHIFT                                                                 0x1
#define RLC_RLCS_LB_READ__LB_CNTR_1_MAX_FLAG__SHIFT                                                           0x2
#define RLC_RLCS_LB_READ__LB_CNTR_2_MAX_FLAG__SHIFT                                                           0x3
#define RLC_RLCS_LB_READ__LBPW_DISABLE_FLAG__SHIFT                                                            0x4
#define RLC_RLCS_LB_READ__RESERVED__SHIFT                                                                     0x5
#define RLC_RLCS_LB_READ__LB_CNTR_START_MASK                                                                  0x00000001L
#define RLC_RLCS_LB_READ__LB_CNTR_STOP_MASK                                                                   0x00000002L
#define RLC_RLCS_LB_READ__LB_CNTR_1_MAX_FLAG_MASK                                                             0x00000004L
#define RLC_RLCS_LB_READ__LB_CNTR_2_MAX_FLAG_MASK                                                             0x00000008L
#define RLC_RLCS_LB_READ__LBPW_DISABLE_FLAG_MASK                                                              0x00000010L
#define RLC_RLCS_LB_READ__RESERVED_MASK                                                                       0xFFFFFFE0L
//RLC_RLCS_LB_CONTROL
#define RLC_RLCS_LB_CONTROL__NEW_LBPW_REQ__SHIFT                                                              0x0
#define RLC_RLCS_LB_CONTROL__LB_CNTR_INC_CP_BUSY__SHIFT                                                       0x1
#define RLC_RLCS_LB_CONTROL__RESERVED__SHIFT                                                                  0x2
#define RLC_RLCS_LB_CONTROL__NEW_LBPW_REQ_MASK                                                                0x00000001L
#define RLC_RLCS_LB_CONTROL__LB_CNTR_INC_CP_BUSY_MASK                                                         0x00000002L
#define RLC_RLCS_LB_CONTROL__RESERVED_MASK                                                                    0xFFFFFFFCL
//RLC_RLCS_IH_SEMAPHORE
#define RLC_RLCS_IH_SEMAPHORE__CLIENT_ID__SHIFT                                                               0x0
#define RLC_RLCS_IH_SEMAPHORE__RESERVED__SHIFT                                                                0x5
#define RLC_RLCS_IH_SEMAPHORE__CLIENT_ID_MASK                                                                 0x0000001FL
#define RLC_RLCS_IH_SEMAPHORE__RESERVED_MASK                                                                  0xFFFFFFE0L
//RLC_RLCS_IH_COOKIE_SEMAPHORE
#define RLC_RLCS_IH_COOKIE_SEMAPHORE__CLIENT_ID__SHIFT                                                        0x0
#define RLC_RLCS_IH_COOKIE_SEMAPHORE__RESERVED__SHIFT                                                         0x5
#define RLC_RLCS_IH_COOKIE_SEMAPHORE__CLIENT_ID_MASK                                                          0x0000001FL
#define RLC_RLCS_IH_COOKIE_SEMAPHORE__RESERVED_MASK                                                           0xFFFFFFE0L
//RLC_RLCS_IH_CTRL_1
#define RLC_RLCS_IH_CTRL_1__IH_CONTEXT_ID_1__SHIFT                                                            0x0
#define RLC_RLCS_IH_CTRL_1__IH_CONTEXT_ID_1_MASK                                                              0xFFFFFFFFL
//RLC_RLCS_IH_CTRL_2
#define RLC_RLCS_IH_CTRL_2__IH_CONTEXT_ID_2__SHIFT                                                            0x0
#define RLC_RLCS_IH_CTRL_2__IH_RING_ID__SHIFT                                                                 0x8
#define RLC_RLCS_IH_CTRL_2__IH_VM_ID__SHIFT                                                                   0x10
#define RLC_RLCS_IH_CTRL_2__RESERVED__SHIFT                                                                   0x14
#define RLC_RLCS_IH_CTRL_2__IH_CONTEXT_ID_2_MASK                                                              0x000000FFL
#define RLC_RLCS_IH_CTRL_2__IH_RING_ID_MASK                                                                   0x0000FF00L
#define RLC_RLCS_IH_CTRL_2__IH_VM_ID_MASK                                                                     0x000F0000L
#define RLC_RLCS_IH_CTRL_2__RESERVED_MASK                                                                     0xFFF00000L
//RLC_RLCS_IH_CTRL_3
#define RLC_RLCS_IH_CTRL_3__IH_SOURCE_ID__SHIFT                                                               0x0
#define RLC_RLCS_IH_CTRL_3__IH_VF_ID__SHIFT                                                                   0x8
#define RLC_RLCS_IH_CTRL_3__IH_VF__SHIFT                                                                      0xd
#define RLC_RLCS_IH_CTRL_3__RESERVED__SHIFT                                                                   0xe
#define RLC_RLCS_IH_CTRL_3__IH_SOURCE_ID_MASK                                                                 0x000000FFL
#define RLC_RLCS_IH_CTRL_3__IH_VF_ID_MASK                                                                     0x00001F00L
#define RLC_RLCS_IH_CTRL_3__IH_VF_MASK                                                                        0x00002000L
#define RLC_RLCS_IH_CTRL_3__RESERVED_MASK                                                                     0xFFFFC000L
//RLC_RLCS_IH_STATUS
#define RLC_RLCS_IH_STATUS__IH_CREDIT_COUNT__SHIFT                                                            0x0
#define RLC_RLCS_IH_STATUS__IH_BUSY__SHIFT                                                                    0x6
#define RLC_RLCS_IH_STATUS__RESERVED__SHIFT                                                                   0x7
#define RLC_RLCS_IH_STATUS__IH_CREDIT_COUNT_MASK                                                              0x0000003FL
#define RLC_RLCS_IH_STATUS__IH_BUSY_MASK                                                                      0x00000040L
#define RLC_RLCS_IH_STATUS__RESERVED_MASK                                                                     0xFFFFFF80L
//RLC_RLCS_WGP_STATUS
#define RLC_RLCS_WGP_STATUS__CS_WORK_ACTIVE__SHIFT                                                            0x0
#define RLC_RLCS_WGP_STATUS__STATIC_WGP_STATUS_CHANGED__SHIFT                                                 0x1
#define RLC_RLCS_WGP_STATUS__DYMANIC_WGP_STATUS_CHANGED__SHIFT                                                0x2
#define RLC_RLCS_WGP_STATUS__STATIC_PERWGP_PD_INCOMPLETE__SHIFT                                               0x3
#define RLC_RLCS_WGP_STATUS__RESERVED__SHIFT                                                                  0x4
#define RLC_RLCS_WGP_STATUS__CS_WORK_ACTIVE_MASK                                                              0x00000001L
#define RLC_RLCS_WGP_STATUS__STATIC_WGP_STATUS_CHANGED_MASK                                                   0x00000002L
#define RLC_RLCS_WGP_STATUS__DYMANIC_WGP_STATUS_CHANGED_MASK                                                  0x00000004L
#define RLC_RLCS_WGP_STATUS__STATIC_PERWGP_PD_INCOMPLETE_MASK                                                 0x00000008L
#define RLC_RLCS_WGP_STATUS__RESERVED_MASK                                                                    0xFFFFFFF0L
//RLC_RLCS_WGP_READ
#define RLC_RLCS_WGP_READ__CS_WORK_ACTIVE__SHIFT                                                              0x0
#define RLC_RLCS_WGP_READ__STATIC_WGP_STATUS_CHANGED__SHIFT                                                   0x1
#define RLC_RLCS_WGP_READ__DYMANIC_WGP_STATUS_CHANGED__SHIFT                                                  0x2
#define RLC_RLCS_WGP_READ__RESERVED__SHIFT                                                                    0x3
#define RLC_RLCS_WGP_READ__CS_WORK_ACTIVE_MASK                                                                0x00000001L
#define RLC_RLCS_WGP_READ__STATIC_WGP_STATUS_CHANGED_MASK                                                     0x00000002L
#define RLC_RLCS_WGP_READ__DYMANIC_WGP_STATUS_CHANGED_MASK                                                    0x00000004L
#define RLC_RLCS_WGP_READ__RESERVED_MASK                                                                      0xFFFFFFF8L
//RLC_RLCS_CP_INT_CTRL_1
#define RLC_RLCS_CP_INT_CTRL_1__INTERRUPT_ACK__SHIFT                                                          0x0
#define RLC_RLCS_CP_INT_CTRL_1__RESERVED__SHIFT                                                               0x1
#define RLC_RLCS_CP_INT_CTRL_1__INTERRUPT_ACK_MASK                                                            0x00000001L
#define RLC_RLCS_CP_INT_CTRL_1__RESERVED_MASK                                                                 0xFFFFFFFEL
//RLC_RLCS_CP_INT_CTRL_2
#define RLC_RLCS_CP_INT_CTRL_2__IDLE_AUTO_ACK_EN__SHIFT                                                       0x0
#define RLC_RLCS_CP_INT_CTRL_2__BUSY_AUTO_ACK_EN__SHIFT                                                       0x1
#define RLC_RLCS_CP_INT_CTRL_2__RESERVED__SHIFT                                                               0x2
#define RLC_RLCS_CP_INT_CTRL_2__IDLE_AUTO_ACK_EN_MASK                                                         0x00000001L
#define RLC_RLCS_CP_INT_CTRL_2__BUSY_AUTO_ACK_EN_MASK                                                         0x00000002L
#define RLC_RLCS_CP_INT_CTRL_2__RESERVED_MASK                                                                 0xFFFFFFFCL
//RLC_RLCS_CP_INT_INFO_1
#define RLC_RLCS_CP_INT_INFO_1__INTERRUPT_INFO_1__SHIFT                                                       0x0
#define RLC_RLCS_CP_INT_INFO_1__INTERRUPT_INFO_1_MASK                                                         0xFFFFFFFFL
//RLC_RLCS_CP_INT_INFO_2
#define RLC_RLCS_CP_INT_INFO_2__INTERRUPT_INFO_2__SHIFT                                                       0x0
#define RLC_RLCS_CP_INT_INFO_2__INTERRUPT_ID__SHIFT                                                           0x10
#define RLC_RLCS_CP_INT_INFO_2__RESERVED__SHIFT                                                               0x19
#define RLC_RLCS_CP_INT_INFO_2__INTERRUPT_INFO_2_MASK                                                         0x0000FFFFL
#define RLC_RLCS_CP_INT_INFO_2__INTERRUPT_ID_MASK                                                             0x01FF0000L
#define RLC_RLCS_CP_INT_INFO_2__RESERVED_MASK                                                                 0xFE000000L
//RLC_RLCS_SPM_INT_CTRL
#define RLC_RLCS_SPM_INT_CTRL__INTERRUPT_ACK__SHIFT                                                           0x0
#define RLC_RLCS_SPM_INT_CTRL__RESERVED__SHIFT                                                                0x1
#define RLC_RLCS_SPM_INT_CTRL__INTERRUPT_ACK_MASK                                                             0x00000001L
#define RLC_RLCS_SPM_INT_CTRL__RESERVED_MASK                                                                  0xFFFFFFFEL
//RLC_RLCS_SPM_INT_INFO_1
#define RLC_RLCS_SPM_INT_INFO_1__INTERRUPT_INFO_1__SHIFT                                                      0x0
#define RLC_RLCS_SPM_INT_INFO_1__INTERRUPT_INFO_1_MASK                                                        0xFFFFFFFFL
//RLC_RLCS_SPM_INT_INFO_2
#define RLC_RLCS_SPM_INT_INFO_2__INTERRUPT_INFO_2__SHIFT                                                      0x0
#define RLC_RLCS_SPM_INT_INFO_2__INTERRUPT_ID__SHIFT                                                          0x10
#define RLC_RLCS_SPM_INT_INFO_2__RESERVED__SHIFT                                                              0x19
#define RLC_RLCS_SPM_INT_INFO_2__INTERRUPT_INFO_2_MASK                                                        0x0000FFFFL
#define RLC_RLCS_SPM_INT_INFO_2__INTERRUPT_ID_MASK                                                            0x01FF0000L
#define RLC_RLCS_SPM_INT_INFO_2__RESERVED_MASK                                                                0xFE000000L
//RLC_RLCS_DSM_TRIG
#define RLC_RLCS_DSM_TRIG__START__SHIFT                                                                       0x0
#define RLC_RLCS_DSM_TRIG__RESERVED__SHIFT                                                                    0x1
#define RLC_RLCS_DSM_TRIG__START_MASK                                                                         0x00000001L
#define RLC_RLCS_DSM_TRIG__RESERVED_MASK                                                                      0xFFFFFFFEL
//RLC_RLCS_BOOTLOAD_STATUS
#define RLC_RLCS_BOOTLOAD_STATUS__RLC_RLCG_IRAM_LOADED__SHIFT                                                 0x0
#define RLC_RLCS_BOOTLOAD_STATUS__RESERVED__SHIFT                                                             0x1
#define RLC_RLCS_BOOTLOAD_STATUS__BOOTLOAD_COMPLETE__SHIFT                                                    0x1f
#define RLC_RLCS_BOOTLOAD_STATUS__RLC_RLCG_IRAM_LOADED_MASK                                                   0x00000001L
#define RLC_RLCS_BOOTLOAD_STATUS__RESERVED_MASK                                                               0x7FFFFFFEL
#define RLC_RLCS_BOOTLOAD_STATUS__BOOTLOAD_COMPLETE_MASK                                                      0x80000000L
//RLC_RLCS_POWER_BRAKE_CNTL
#define RLC_RLCS_POWER_BRAKE_CNTL__POWER_BRAKE__SHIFT                                                         0x0
#define RLC_RLCS_POWER_BRAKE_CNTL__INT_CLEAR__SHIFT                                                           0x1
#define RLC_RLCS_POWER_BRAKE_CNTL__MAX_HYSTERESIS__SHIFT                                                      0x2
#define RLC_RLCS_POWER_BRAKE_CNTL__HYSTERESIS_CNT__SHIFT                                                      0xa
#define RLC_RLCS_POWER_BRAKE_CNTL__RESERVED__SHIFT                                                            0x12
#define RLC_RLCS_POWER_BRAKE_CNTL__POWER_BRAKE_MASK                                                           0x00000001L
#define RLC_RLCS_POWER_BRAKE_CNTL__INT_CLEAR_MASK                                                             0x00000002L
#define RLC_RLCS_POWER_BRAKE_CNTL__MAX_HYSTERESIS_MASK                                                        0x000003FCL
#define RLC_RLCS_POWER_BRAKE_CNTL__HYSTERESIS_CNT_MASK                                                        0x0003FC00L
#define RLC_RLCS_POWER_BRAKE_CNTL__RESERVED_MASK                                                              0xFFFC0000L
//RLC_RLCS_GENERAL_0
#define RLC_RLCS_GENERAL_0__DATA__SHIFT                                                                       0x0
#define RLC_RLCS_GENERAL_0__DATA_MASK                                                                         0xFFFFFFFFL
//RLC_RLCS_GENERAL_1
#define RLC_RLCS_GENERAL_1__DATA__SHIFT                                                                       0x0
#define RLC_RLCS_GENERAL_1__DATA_MASK                                                                         0xFFFFFFFFL
//RLC_RLCS_GENERAL_2
#define RLC_RLCS_GENERAL_2__DATA__SHIFT                                                                       0x0
#define RLC_RLCS_GENERAL_2__DATA_MASK                                                                         0xFFFFFFFFL
//RLC_RLCS_GENERAL_3
#define RLC_RLCS_GENERAL_3__DATA__SHIFT                                                                       0x0
#define RLC_RLCS_GENERAL_3__DATA_MASK                                                                         0xFFFFFFFFL
//RLC_RLCS_GENERAL_4
#define RLC_RLCS_GENERAL_4__DATA__SHIFT                                                                       0x0
#define RLC_RLCS_GENERAL_4__DATA_MASK                                                                         0xFFFFFFFFL
//RLC_RLCS_GENERAL_5
#define RLC_RLCS_GENERAL_5__DATA__SHIFT                                                                       0x0
#define RLC_RLCS_GENERAL_5__DATA_MASK                                                                         0xFFFFFFFFL
//RLC_RLCS_GRBM_IDLE_BUSY_STAT
#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__GRBM_RLC_GC_STAT_IDLE__SHIFT                                            0x0
#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_0_BUSY__SHIFT                                                      0x10
#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_1_BUSY__SHIFT                                                      0x11
#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_2_BUSY__SHIFT                                                      0x12
#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_3_BUSY__SHIFT                                                      0x13
#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_4_BUSY__SHIFT                                                      0x14
#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_5_BUSY__SHIFT                                                      0x15
#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_6_BUSY__SHIFT                                                      0x16
#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_7_BUSY__SHIFT                                                      0x17
#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_0_BUSY_CHANGED__SHIFT                                              0x18
#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_1_BUSY_CHANGED__SHIFT                                              0x19
#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_2_BUSY_CHANGED__SHIFT                                              0x1a
#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_3_BUSY_CHANGED__SHIFT                                              0x1b
#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_4_BUSY_CHANGED__SHIFT                                              0x1c
#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_5_BUSY_CHANGED__SHIFT                                              0x1d
#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_6_BUSY_CHANGED__SHIFT                                              0x1e
#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_7_BUSY_CHANGED__SHIFT                                              0x1f
#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__GRBM_RLC_GC_STAT_IDLE_MASK                                              0x00000003L
#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_0_BUSY_MASK                                                        0x00010000L
#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_1_BUSY_MASK                                                        0x00020000L
#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_2_BUSY_MASK                                                        0x00040000L
#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_3_BUSY_MASK                                                        0x00080000L
#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_4_BUSY_MASK                                                        0x00100000L
#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_5_BUSY_MASK                                                        0x00200000L
#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_6_BUSY_MASK                                                        0x00400000L
#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_7_BUSY_MASK                                                        0x00800000L
#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_0_BUSY_CHANGED_MASK                                                0x01000000L
#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_1_BUSY_CHANGED_MASK                                                0x02000000L
#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_2_BUSY_CHANGED_MASK                                                0x04000000L
#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_3_BUSY_CHANGED_MASK                                                0x08000000L
#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_4_BUSY_CHANGED_MASK                                                0x10000000L
#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_5_BUSY_CHANGED_MASK                                                0x20000000L
#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_6_BUSY_CHANGED_MASK                                                0x40000000L
#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_7_BUSY_CHANGED_MASK                                                0x80000000L
//RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL
#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA0_BUSY_INT_CLEAR__SHIFT                                         0x0
#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA1_BUSY_INT_CLEAR__SHIFT                                         0x1
#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA2_BUSY_INT_CLEAR__SHIFT                                         0x2
#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA3_BUSY_INT_CLEAR__SHIFT                                         0x3
#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA4_BUSY_INT_CLEAR__SHIFT                                         0x4
#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA5_BUSY_INT_CLEAR__SHIFT                                         0x5
#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA6_BUSY_INT_CLEAR__SHIFT                                         0x6
#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA7_BUSY_INT_CLEAR__SHIFT                                         0x7
#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA0_BUSY_INT_CLEAR_MASK                                           0x00000001L
#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA1_BUSY_INT_CLEAR_MASK                                           0x00000002L
#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA2_BUSY_INT_CLEAR_MASK                                           0x00000004L
#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA3_BUSY_INT_CLEAR_MASK                                           0x00000008L
#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA4_BUSY_INT_CLEAR_MASK                                           0x00000010L
#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA5_BUSY_INT_CLEAR_MASK                                           0x00000020L
#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA6_BUSY_INT_CLEAR_MASK                                           0x00000040L
#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA7_BUSY_INT_CLEAR_MASK                                           0x00000080L
//RLC_RLCS_CMP_IDLE_CNTL
#define RLC_RLCS_CMP_IDLE_CNTL__INT_CLEAR__SHIFT                                                              0x0
#define RLC_RLCS_CMP_IDLE_CNTL__CMP_IDLE_HYST__SHIFT                                                          0x1
#define RLC_RLCS_CMP_IDLE_CNTL__CMP_IDLE__SHIFT                                                               0x2
#define RLC_RLCS_CMP_IDLE_CNTL__MAX_HYSTERESIS__SHIFT                                                         0x3
#define RLC_RLCS_CMP_IDLE_CNTL__HYSTERESIS_CNT__SHIFT                                                         0xb
#define RLC_RLCS_CMP_IDLE_CNTL__RESERVED__SHIFT                                                               0x13
#define RLC_RLCS_CMP_IDLE_CNTL__INT_CLEAR_MASK                                                                0x00000001L
#define RLC_RLCS_CMP_IDLE_CNTL__CMP_IDLE_HYST_MASK                                                            0x00000002L
#define RLC_RLCS_CMP_IDLE_CNTL__CMP_IDLE_MASK                                                                 0x00000004L
#define RLC_RLCS_CMP_IDLE_CNTL__MAX_HYSTERESIS_MASK                                                           0x000007F8L
#define RLC_RLCS_CMP_IDLE_CNTL__HYSTERESIS_CNT_MASK                                                           0x0007F800L
#define RLC_RLCS_CMP_IDLE_CNTL__RESERVED_MASK                                                                 0xFFF80000L
//RLC_RLCS_POWER_BRAKE_CNTL_TH1
#define RLC_RLCS_POWER_BRAKE_CNTL_TH1__POWER_BRAKE__SHIFT                                                     0x0
#define RLC_RLCS_POWER_BRAKE_CNTL_TH1__INT_CLEAR__SHIFT                                                       0x1
#define RLC_RLCS_POWER_BRAKE_CNTL_TH1__MAX_HYSTERESIS__SHIFT                                                  0x2
#define RLC_RLCS_POWER_BRAKE_CNTL_TH1__HYSTERESIS_CNT__SHIFT                                                  0xa
#define RLC_RLCS_POWER_BRAKE_CNTL_TH1__RESERVED__SHIFT                                                        0x12
#define RLC_RLCS_POWER_BRAKE_CNTL_TH1__POWER_BRAKE_MASK                                                       0x00000001L
#define RLC_RLCS_POWER_BRAKE_CNTL_TH1__INT_CLEAR_MASK                                                         0x00000002L
#define RLC_RLCS_POWER_BRAKE_CNTL_TH1__MAX_HYSTERESIS_MASK                                                    0x000003FCL
#define RLC_RLCS_POWER_BRAKE_CNTL_TH1__HYSTERESIS_CNT_MASK                                                    0x0003FC00L
#define RLC_RLCS_POWER_BRAKE_CNTL_TH1__RESERVED_MASK                                                          0xFFFC0000L
//RLC_RLCS_AUXILIARY_REG_1
#define RLC_RLCS_AUXILIARY_REG_1__ADDR__SHIFT                                                                 0x0
#define RLC_RLCS_AUXILIARY_REG_1__RESERVED__SHIFT                                                             0x12
#define RLC_RLCS_AUXILIARY_REG_1__ADDR_MASK                                                                   0x0003FFFFL
#define RLC_RLCS_AUXILIARY_REG_1__RESERVED_MASK                                                               0xFFFC0000L
//RLC_RLCS_AUXILIARY_REG_2
#define RLC_RLCS_AUXILIARY_REG_2__ADDR__SHIFT                                                                 0x0
#define RLC_RLCS_AUXILIARY_REG_2__RESERVED__SHIFT                                                             0x12
#define RLC_RLCS_AUXILIARY_REG_2__ADDR_MASK                                                                   0x0003FFFFL
#define RLC_RLCS_AUXILIARY_REG_2__RESERVED_MASK                                                               0xFFFC0000L
//RLC_RLCS_AUXILIARY_REG_3
#define RLC_RLCS_AUXILIARY_REG_3__ADDR__SHIFT                                                                 0x0
#define RLC_RLCS_AUXILIARY_REG_3__RESERVED__SHIFT                                                             0x12
#define RLC_RLCS_AUXILIARY_REG_3__ADDR_MASK                                                                   0x0003FFFFL
#define RLC_RLCS_AUXILIARY_REG_3__RESERVED_MASK                                                               0xFFFC0000L
//RLC_RLCS_AUXILIARY_REG_4
#define RLC_RLCS_AUXILIARY_REG_4__ADDR__SHIFT                                                                 0x0
#define RLC_RLCS_AUXILIARY_REG_4__RESERVED__SHIFT                                                             0x12
#define RLC_RLCS_AUXILIARY_REG_4__ADDR_MASK                                                                   0x0003FFFFL
#define RLC_RLCS_AUXILIARY_REG_4__RESERVED_MASK                                                               0xFFFC0000L
//RLC_RLCS_SPM_SQTT_MODE
#define RLC_RLCS_SPM_SQTT_MODE__MODE__SHIFT                                                                   0x0
#define RLC_RLCS_SPM_SQTT_MODE__MODE_MASK                                                                     0x00000001L
//RLC_RLCS_CP_DMA_SRCID_OVER
#define RLC_RLCS_CP_DMA_SRCID_OVER__SRCID_OVERRIDE__SHIFT                                                     0x0
#define RLC_RLCS_CP_DMA_SRCID_OVER__SRCID_OVERRIDE_MASK                                                       0x00000001L
//RLC_RLCS_UTCL2_CNTL
#define RLC_RLCS_UTCL2_CNTL__MTYPE_NO_PTE_MODE__SHIFT                                                         0x0
#define RLC_RLCS_UTCL2_CNTL__GPA_OVERRIDE__SHIFT                                                              0x1
#define RLC_RLCS_UTCL2_CNTL__VF_OVERRIDE__SHIFT                                                               0x2
#define RLC_RLCS_UTCL2_CNTL__GPA_OVERRIDE_VALUE__SHIFT                                                        0x3
#define RLC_RLCS_UTCL2_CNTL__VF_OVERRIDE_VALUE__SHIFT                                                         0x5
#define RLC_RLCS_UTCL2_CNTL__RESERVED__SHIFT                                                                  0x6
#define RLC_RLCS_UTCL2_CNTL__MTYPE_NO_PTE_MODE_MASK                                                           0x00000001L
#define RLC_RLCS_UTCL2_CNTL__GPA_OVERRIDE_MASK                                                                0x00000002L
#define RLC_RLCS_UTCL2_CNTL__VF_OVERRIDE_MASK                                                                 0x00000004L
#define RLC_RLCS_UTCL2_CNTL__GPA_OVERRIDE_VALUE_MASK                                                          0x00000018L
#define RLC_RLCS_UTCL2_CNTL__VF_OVERRIDE_VALUE_MASK                                                           0x00000020L
#define RLC_RLCS_UTCL2_CNTL__RESERVED_MASK                                                                    0xFFFFFFC0L
//RLC_RLCS_MP1_RLC_DOORBELL_CTRL
#define RLC_RLCS_MP1_RLC_DOORBELL_CTRL__INT_CLEAR__SHIFT                                                      0x0
#define RLC_RLCS_MP1_RLC_DOORBELL_CTRL__DOORBELL__SHIFT                                                       0x1
#define RLC_RLCS_MP1_RLC_DOORBELL_CTRL__RESERVED__SHIFT                                                       0x2
#define RLC_RLCS_MP1_RLC_DOORBELL_CTRL__INT_CLEAR_MASK                                                        0x00000001L
#define RLC_RLCS_MP1_RLC_DOORBELL_CTRL__DOORBELL_MASK                                                         0x00000002L
#define RLC_RLCS_MP1_RLC_DOORBELL_CTRL__RESERVED_MASK                                                         0xFFFFFFFCL
//RLC_RLCS_BOOTLOAD_ID_STATUS1
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_0_LOADED__SHIFT                                                      0x0
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_1_LOADED__SHIFT                                                      0x1
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_2_LOADED__SHIFT                                                      0x2
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_3_LOADED__SHIFT                                                      0x3
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_4_LOADED__SHIFT                                                      0x4
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_5_LOADED__SHIFT                                                      0x5
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_6_LOADED__SHIFT                                                      0x6
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_7_LOADED__SHIFT                                                      0x7
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_8_LOADED__SHIFT                                                      0x8
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_9_LOADED__SHIFT                                                      0x9
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_10_LOADED__SHIFT                                                     0xa
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_11_LOADED__SHIFT                                                     0xb
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_12_LOADED__SHIFT                                                     0xc
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_13_LOADED__SHIFT                                                     0xd
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_14_LOADED__SHIFT                                                     0xe
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_15_LOADED__SHIFT                                                     0xf
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_16_LOADED__SHIFT                                                     0x10
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_17_LOADED__SHIFT                                                     0x11
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_18_LOADED__SHIFT                                                     0x12
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_19_LOADED__SHIFT                                                     0x13
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_20_LOADED__SHIFT                                                     0x14
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_21_LOADED__SHIFT                                                     0x15
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_22_LOADED__SHIFT                                                     0x16
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_23_LOADED__SHIFT                                                     0x17
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_24_LOADED__SHIFT                                                     0x18
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_25_LOADED__SHIFT                                                     0x19
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_26_LOADED__SHIFT                                                     0x1a
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_27_LOADED__SHIFT                                                     0x1b
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_28_LOADED__SHIFT                                                     0x1c
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_29_LOADED__SHIFT                                                     0x1d
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_30_LOADED__SHIFT                                                     0x1e
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_31_LOADED__SHIFT                                                     0x1f
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_0_LOADED_MASK                                                        0x00000001L
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_1_LOADED_MASK                                                        0x00000002L
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_2_LOADED_MASK                                                        0x00000004L
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_3_LOADED_MASK                                                        0x00000008L
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_4_LOADED_MASK                                                        0x00000010L
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_5_LOADED_MASK                                                        0x00000020L
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_6_LOADED_MASK                                                        0x00000040L
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_7_LOADED_MASK                                                        0x00000080L
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_8_LOADED_MASK                                                        0x00000100L
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_9_LOADED_MASK                                                        0x00000200L
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_10_LOADED_MASK                                                       0x00000400L
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_11_LOADED_MASK                                                       0x00000800L
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_12_LOADED_MASK                                                       0x00001000L
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_13_LOADED_MASK                                                       0x00002000L
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_14_LOADED_MASK                                                       0x00004000L
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_15_LOADED_MASK                                                       0x00008000L
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_16_LOADED_MASK                                                       0x00010000L
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_17_LOADED_MASK                                                       0x00020000L
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_18_LOADED_MASK                                                       0x00040000L
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_19_LOADED_MASK                                                       0x00080000L
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_20_LOADED_MASK                                                       0x00100000L
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_21_LOADED_MASK                                                       0x00200000L
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_22_LOADED_MASK                                                       0x00400000L
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_23_LOADED_MASK                                                       0x00800000L
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_24_LOADED_MASK                                                       0x01000000L
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_25_LOADED_MASK                                                       0x02000000L
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_26_LOADED_MASK                                                       0x04000000L
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_27_LOADED_MASK                                                       0x08000000L
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_28_LOADED_MASK                                                       0x10000000L
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_29_LOADED_MASK                                                       0x20000000L
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_30_LOADED_MASK                                                       0x40000000L
#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_31_LOADED_MASK                                                       0x80000000L
//RLC_RLCS_BOOTLOAD_ID_STATUS2
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_32_LOADED__SHIFT                                                     0x0
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_33_LOADED__SHIFT                                                     0x1
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_34_LOADED__SHIFT                                                     0x2
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_35_LOADED__SHIFT                                                     0x3
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_36_LOADED__SHIFT                                                     0x4
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_37_LOADED__SHIFT                                                     0x5
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_38_LOADED__SHIFT                                                     0x6
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_39_LOADED__SHIFT                                                     0x7
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_40_LOADED__SHIFT                                                     0x8
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_41_LOADED__SHIFT                                                     0x9
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_42_LOADED__SHIFT                                                     0xa
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_43_LOADED__SHIFT                                                     0xb
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_44_LOADED__SHIFT                                                     0xc
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_45_LOADED__SHIFT                                                     0xd
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_46_LOADED__SHIFT                                                     0xe
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_47_LOADED__SHIFT                                                     0xf
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_48_LOADED__SHIFT                                                     0x10
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_49_LOADED__SHIFT                                                     0x11
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_50_LOADED__SHIFT                                                     0x12
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_51_LOADED__SHIFT                                                     0x13
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_52_LOADED__SHIFT                                                     0x14
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_53_LOADED__SHIFT                                                     0x15
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_54_LOADED__SHIFT                                                     0x16
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_55_LOADED__SHIFT                                                     0x17
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_56_LOADED__SHIFT                                                     0x18
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_57_LOADED__SHIFT                                                     0x19
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_58_LOADED__SHIFT                                                     0x1a
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_59_LOADED__SHIFT                                                     0x1b
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_60_LOADED__SHIFT                                                     0x1c
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_61_LOADED__SHIFT                                                     0x1d
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_62_LOADED__SHIFT                                                     0x1e
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_63_LOADED__SHIFT                                                     0x1f
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_32_LOADED_MASK                                                       0x00000001L
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_33_LOADED_MASK                                                       0x00000002L
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_34_LOADED_MASK                                                       0x00000004L
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_35_LOADED_MASK                                                       0x00000008L
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_36_LOADED_MASK                                                       0x00000010L
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_37_LOADED_MASK                                                       0x00000020L
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_38_LOADED_MASK                                                       0x00000040L
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_39_LOADED_MASK                                                       0x00000080L
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_40_LOADED_MASK                                                       0x00000100L
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_41_LOADED_MASK                                                       0x00000200L
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_42_LOADED_MASK                                                       0x00000400L
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_43_LOADED_MASK                                                       0x00000800L
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_44_LOADED_MASK                                                       0x00001000L
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_45_LOADED_MASK                                                       0x00002000L
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_46_LOADED_MASK                                                       0x00004000L
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_47_LOADED_MASK                                                       0x00008000L
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_48_LOADED_MASK                                                       0x00010000L
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_49_LOADED_MASK                                                       0x00020000L
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_50_LOADED_MASK                                                       0x00040000L
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_51_LOADED_MASK                                                       0x00080000L
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_52_LOADED_MASK                                                       0x00100000L
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_53_LOADED_MASK                                                       0x00200000L
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_54_LOADED_MASK                                                       0x00400000L
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_55_LOADED_MASK                                                       0x00800000L
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_56_LOADED_MASK                                                       0x01000000L
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_57_LOADED_MASK                                                       0x02000000L
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_58_LOADED_MASK                                                       0x04000000L
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_59_LOADED_MASK                                                       0x08000000L
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_60_LOADED_MASK                                                       0x10000000L
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_61_LOADED_MASK                                                       0x20000000L
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_62_LOADED_MASK                                                       0x40000000L
#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_63_LOADED_MASK                                                       0x80000000L
//RLC_RLCS_SMUIO_VIDCHG_CTRL
#define RLC_RLCS_SMUIO_VIDCHG_CTRL__REQ__SHIFT                                                                0x0
#define RLC_RLCS_SMUIO_VIDCHG_CTRL__DATA__SHIFT                                                               0x1
#define RLC_RLCS_SMUIO_VIDCHG_CTRL__PSIEN__SHIFT                                                              0xa
#define RLC_RLCS_SMUIO_VIDCHG_CTRL__ACK__SHIFT                                                                0xb
#define RLC_RLCS_SMUIO_VIDCHG_CTRL__REQ_MASK                                                                  0x00000001L
#define RLC_RLCS_SMUIO_VIDCHG_CTRL__DATA_MASK                                                                 0x000003FEL
#define RLC_RLCS_SMUIO_VIDCHG_CTRL__PSIEN_MASK                                                                0x00000400L
#define RLC_RLCS_SMUIO_VIDCHG_CTRL__ACK_MASK                                                                  0x00000800L
//RLC_RLCS_EDC_INT_CNTL
#define RLC_RLCS_EDC_INT_CNTL__EDC_EVENT_INT_CLEAR__SHIFT                                                     0x0
#define RLC_RLCS_EDC_INT_CNTL__EDC_EVENT_INT_CLEAR_MASK                                                       0x00000001L
//RLC_RLCS_KMD_LOG_CNTL1
#define RLC_RLCS_KMD_LOG_CNTL1__DATA__SHIFT                                                                   0x0
#define RLC_RLCS_KMD_LOG_CNTL1__DATA_MASK                                                                     0xFFFFFFFFL
//RLC_RLCS_KMD_LOG_CNTL2
#define RLC_RLCS_KMD_LOG_CNTL2__DATA__SHIFT                                                                   0x0
#define RLC_RLCS_KMD_LOG_CNTL2__DATA_MASK                                                                     0xFFFFFFFFL
//RLC_RLCS_GPM_LEGACY_INT_STAT
#define RLC_RLCS_GPM_LEGACY_INT_STAT__GC_CAC_EDC_EVENT_CHANGED__SHIFT                                         0x0
#define RLC_RLCS_GPM_LEGACY_INT_STAT__GFX_POWER_BRAKE_CHANGED__SHIFT                                          0x1
#define RLC_RLCS_GPM_LEGACY_INT_STAT__GC_CAC_EDC_EVENT_CHANGED_MASK                                           0x00000001L
#define RLC_RLCS_GPM_LEGACY_INT_STAT__GFX_POWER_BRAKE_CHANGED_MASK                                            0x00000002L
//RLC_RLCS_GPM_LEGACY_INT_DISABLE
#define RLC_RLCS_GPM_LEGACY_INT_DISABLE__GC_CAC_EDC_EVENT_CHANGED__SHIFT                                      0x0
#define RLC_RLCS_GPM_LEGACY_INT_DISABLE__GFX_POWER_BRAKE_CHANGED__SHIFT                                       0x1
#define RLC_RLCS_GPM_LEGACY_INT_DISABLE__GC_CAC_EDC_EVENT_CHANGED_MASK                                        0x00000001L
#define RLC_RLCS_GPM_LEGACY_INT_DISABLE__GFX_POWER_BRAKE_CHANGED_MASK                                         0x00000002L
//RLC_RLCS_SRM_SRCID_CNTL
#define RLC_RLCS_SRM_SRCID_CNTL__SRCID__SHIFT                                                                 0x0
#define RLC_RLCS_SRM_SRCID_CNTL__SRCID_MASK                                                                   0x00000007L
//RLC_RLCS_PERFMON_CLK_CNTL_UCODE
#define RLC_RLCS_PERFMON_CLK_CNTL_UCODE__PERFMON_CLOCK_STATE__SHIFT                                           0x0
#define RLC_RLCS_PERFMON_CLK_CNTL_UCODE__PERFMON_CLOCK_STATE_MASK                                             0x00000001L
//RLC_RLCS_DEC_END


// addressBlock: gc_pwrdec
//SQ_ALU_CLK_CTRL
#define SQ_ALU_CLK_CTRL__FORCE_WGP_ON_SA0__SHIFT                                                              0x0
#define SQ_ALU_CLK_CTRL__FORCE_WGP_ON_SA1__SHIFT                                                              0x10
#define SQ_ALU_CLK_CTRL__FORCE_WGP_ON_SA0_MASK                                                                0x0000FFFFL
#define SQ_ALU_CLK_CTRL__FORCE_WGP_ON_SA1_MASK                                                                0xFFFF0000L
//SQ_TEX_CLK_CTRL
#define SQ_TEX_CLK_CTRL__FORCE_WGP_ON_SA0__SHIFT                                                              0x0
#define SQ_TEX_CLK_CTRL__FORCE_WGP_ON_SA1__SHIFT                                                              0x10
#define SQ_TEX_CLK_CTRL__FORCE_WGP_ON_SA0_MASK                                                                0x0000FFFFL
#define SQ_TEX_CLK_CTRL__FORCE_WGP_ON_SA1_MASK                                                                0xFFFF0000L
//SQ_LDS_CLK_CTRL
#define SQ_LDS_CLK_CTRL__FORCE_WGP_ON_SA0__SHIFT                                                              0x0
#define SQ_LDS_CLK_CTRL__FORCE_WGP_ON_SA1__SHIFT                                                              0x10
#define SQ_LDS_CLK_CTRL__FORCE_WGP_ON_SA0_MASK                                                                0x0000FFFFL
#define SQ_LDS_CLK_CTRL__FORCE_WGP_ON_SA1_MASK                                                                0xFFFF0000L
//RLC_GFX_RM_CNTL
#define RLC_GFX_RM_CNTL__RLC_GFX_RM_VALID__SHIFT                                                              0x0
#define RLC_GFX_RM_CNTL__RESERVED__SHIFT                                                                      0x1
#define RLC_GFX_RM_CNTL__RLC_GFX_RM_VALID_MASK                                                                0x00000001L
#define RLC_GFX_RM_CNTL__RESERVED_MASK                                                                        0xFFFFFFFEL


// addressBlock: gc_hypdec
//CP_HYP_PFP_UCODE_ADDR
#define CP_HYP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT                                                              0x0
#define CP_HYP_PFP_UCODE_ADDR__UCODE_ADDR_MASK                                                                0x000FFFFFL
//CP_PFP_UCODE_ADDR
#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT                                                                  0x0
#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK                                                                    0x000FFFFFL
//CP_HYP_PFP_UCODE_DATA
#define CP_HYP_PFP_UCODE_DATA__UCODE_DATA__SHIFT                                                              0x0
#define CP_HYP_PFP_UCODE_DATA__UCODE_DATA_MASK                                                                0xFFFFFFFFL
//CP_PFP_UCODE_DATA
#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT                                                                  0x0
#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK                                                                    0xFFFFFFFFL
//CP_HYP_ME_UCODE_ADDR
#define CP_HYP_ME_UCODE_ADDR__UCODE_ADDR__SHIFT                                                               0x0
#define CP_HYP_ME_UCODE_ADDR__UCODE_ADDR_MASK                                                                 0x000FFFFFL
//CP_ME_RAM_RADDR
#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT                                                                  0x0
#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK                                                                    0x000FFFFFL
//CP_ME_RAM_WADDR
#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT                                                                  0x0
#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK                                                                    0x001FFFFFL
//CP_HYP_ME_UCODE_DATA
#define CP_HYP_ME_UCODE_DATA__UCODE_DATA__SHIFT                                                               0x0
#define CP_HYP_ME_UCODE_DATA__UCODE_DATA_MASK                                                                 0xFFFFFFFFL
//CP_ME_RAM_DATA
#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT                                                                    0x0
#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK                                                                      0xFFFFFFFFL
//CP_CE_UCODE_ADDR
#define CP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT                                                                   0x0
#define CP_CE_UCODE_ADDR__UCODE_ADDR_MASK                                                                     0x000FFFFFL
//CP_HYP_CE_UCODE_ADDR
#define CP_HYP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT                                                               0x0
#define CP_HYP_CE_UCODE_ADDR__UCODE_ADDR_MASK                                                                 0x000FFFFFL
//CP_CE_UCODE_DATA
#define CP_CE_UCODE_DATA__UCODE_DATA__SHIFT                                                                   0x0
#define CP_CE_UCODE_DATA__UCODE_DATA_MASK                                                                     0xFFFFFFFFL
//CP_HYP_CE_UCODE_DATA
#define CP_HYP_CE_UCODE_DATA__UCODE_DATA__SHIFT                                                               0x0
#define CP_HYP_CE_UCODE_DATA__UCODE_DATA_MASK                                                                 0xFFFFFFFFL
//CP_HYP_MEC1_UCODE_ADDR
#define CP_HYP_MEC1_UCODE_ADDR__UCODE_ADDR__SHIFT                                                             0x0
#define CP_HYP_MEC1_UCODE_ADDR__UCODE_ADDR_MASK                                                               0x000FFFFFL
//CP_MEC_ME1_UCODE_ADDR
#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR__SHIFT                                                              0x0
#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR_MASK                                                                0x000FFFFFL
//CP_HYP_MEC1_UCODE_DATA
#define CP_HYP_MEC1_UCODE_DATA__UCODE_DATA__SHIFT                                                             0x0
#define CP_HYP_MEC1_UCODE_DATA__UCODE_DATA_MASK                                                               0xFFFFFFFFL
//CP_MEC_ME1_UCODE_DATA
#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA__SHIFT                                                              0x0
#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA_MASK                                                                0xFFFFFFFFL
//CP_HYP_MEC2_UCODE_ADDR
#define CP_HYP_MEC2_UCODE_ADDR__UCODE_ADDR__SHIFT                                                             0x0
#define CP_HYP_MEC2_UCODE_ADDR__UCODE_ADDR_MASK                                                               0x000FFFFFL
//CP_MEC_ME2_UCODE_ADDR
#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR__SHIFT                                                              0x0
#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR_MASK                                                                0x000FFFFFL
//CP_HYP_MEC2_UCODE_DATA
#define CP_HYP_MEC2_UCODE_DATA__UCODE_DATA__SHIFT                                                             0x0
#define CP_HYP_MEC2_UCODE_DATA__UCODE_DATA_MASK                                                               0xFFFFFFFFL
//CP_MEC_ME2_UCODE_DATA
#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA__SHIFT                                                              0x0
#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA_MASK                                                                0xFFFFFFFFL
//CP_PFP_IC_BASE_LO
#define CP_PFP_IC_BASE_LO__IC_BASE_LO__SHIFT                                                                  0xc
#define CP_PFP_IC_BASE_LO__IC_BASE_LO_MASK                                                                    0xFFFFF000L
//CP_PFP_IC_BASE_HI
#define CP_PFP_IC_BASE_HI__IC_BASE_HI__SHIFT                                                                  0x0
#define CP_PFP_IC_BASE_HI__IC_BASE_HI_MASK                                                                    0x0000FFFFL
//CP_PFP_IC_BASE_CNTL
#define CP_PFP_IC_BASE_CNTL__VMID__SHIFT                                                                      0x0
#define CP_PFP_IC_BASE_CNTL__ADDRESS_CLAMP__SHIFT                                                             0x4
#define CP_PFP_IC_BASE_CNTL__EXE_DISABLE__SHIFT                                                               0x17
#define CP_PFP_IC_BASE_CNTL__CACHE_POLICY__SHIFT                                                              0x18
#define CP_PFP_IC_BASE_CNTL__VMID_MASK                                                                        0x0000000FL
#define CP_PFP_IC_BASE_CNTL__ADDRESS_CLAMP_MASK                                                               0x00000010L
#define CP_PFP_IC_BASE_CNTL__EXE_DISABLE_MASK                                                                 0x00800000L
#define CP_PFP_IC_BASE_CNTL__CACHE_POLICY_MASK                                                                0x03000000L
//CP_PFP_IC_OP_CNTL
#define CP_PFP_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT                                                            0x0
#define CP_PFP_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE__SHIFT                                                   0x1
#define CP_PFP_IC_OP_CNTL__PRIME_ICACHE__SHIFT                                                                0x4
#define CP_PFP_IC_OP_CNTL__ICACHE_PRIMED__SHIFT                                                               0x5
#define CP_PFP_IC_OP_CNTL__INVALIDATE_CACHE_MASK                                                              0x00000001L
#define CP_PFP_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE_MASK                                                     0x00000002L
#define CP_PFP_IC_OP_CNTL__PRIME_ICACHE_MASK                                                                  0x00000010L
#define CP_PFP_IC_OP_CNTL__ICACHE_PRIMED_MASK                                                                 0x00000020L
//CP_ME_IC_BASE_LO
#define CP_ME_IC_BASE_LO__IC_BASE_LO__SHIFT                                                                   0xc
#define CP_ME_IC_BASE_LO__IC_BASE_LO_MASK                                                                     0xFFFFF000L
//CP_ME_IC_BASE_HI
#define CP_ME_IC_BASE_HI__IC_BASE_HI__SHIFT                                                                   0x0
#define CP_ME_IC_BASE_HI__IC_BASE_HI_MASK                                                                     0x0000FFFFL
//CP_ME_IC_BASE_CNTL
#define CP_ME_IC_BASE_CNTL__VMID__SHIFT                                                                       0x0
#define CP_ME_IC_BASE_CNTL__ADDRESS_CLAMP__SHIFT                                                              0x4
#define CP_ME_IC_BASE_CNTL__EXE_DISABLE__SHIFT                                                                0x17
#define CP_ME_IC_BASE_CNTL__CACHE_POLICY__SHIFT                                                               0x18
#define CP_ME_IC_BASE_CNTL__VMID_MASK                                                                         0x0000000FL
#define CP_ME_IC_BASE_CNTL__ADDRESS_CLAMP_MASK                                                                0x00000010L
#define CP_ME_IC_BASE_CNTL__EXE_DISABLE_MASK                                                                  0x00800000L
#define CP_ME_IC_BASE_CNTL__CACHE_POLICY_MASK                                                                 0x03000000L
//CP_ME_IC_OP_CNTL
#define CP_ME_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT                                                             0x0
#define CP_ME_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE__SHIFT                                                    0x1
#define CP_ME_IC_OP_CNTL__PRIME_ICACHE__SHIFT                                                                 0x4
#define CP_ME_IC_OP_CNTL__ICACHE_PRIMED__SHIFT                                                                0x5
#define CP_ME_IC_OP_CNTL__INVALIDATE_CACHE_MASK                                                               0x00000001L
#define CP_ME_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE_MASK                                                      0x00000002L
#define CP_ME_IC_OP_CNTL__PRIME_ICACHE_MASK                                                                   0x00000010L
#define CP_ME_IC_OP_CNTL__ICACHE_PRIMED_MASK                                                                  0x00000020L
//CP_CE_IC_BASE_LO
#define CP_CE_IC_BASE_LO__IC_BASE_LO__SHIFT                                                                   0xc
#define CP_CE_IC_BASE_LO__IC_BASE_LO_MASK                                                                     0xFFFFF000L
//CP_CE_IC_BASE_HI
#define CP_CE_IC_BASE_HI__IC_BASE_HI__SHIFT                                                                   0x0
#define CP_CE_IC_BASE_HI__IC_BASE_HI_MASK                                                                     0x0000FFFFL
//CP_CE_IC_BASE_CNTL
#define CP_CE_IC_BASE_CNTL__VMID__SHIFT                                                                       0x0
#define CP_CE_IC_BASE_CNTL__ADDRESS_CLAMP__SHIFT                                                              0x4
#define CP_CE_IC_BASE_CNTL__EXE_DISABLE__SHIFT                                                                0x17
#define CP_CE_IC_BASE_CNTL__CACHE_POLICY__SHIFT                                                               0x18
#define CP_CE_IC_BASE_CNTL__VMID_MASK                                                                         0x0000000FL
#define CP_CE_IC_BASE_CNTL__ADDRESS_CLAMP_MASK                                                                0x00000010L
#define CP_CE_IC_BASE_CNTL__EXE_DISABLE_MASK                                                                  0x00800000L
#define CP_CE_IC_BASE_CNTL__CACHE_POLICY_MASK                                                                 0x03000000L
//CP_CE_IC_OP_CNTL
#define CP_CE_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT                                                             0x0
#define CP_CE_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE__SHIFT                                                    0x1
#define CP_CE_IC_OP_CNTL__PRIME_ICACHE__SHIFT                                                                 0x4
#define CP_CE_IC_OP_CNTL__ICACHE_PRIMED__SHIFT                                                                0x5
#define CP_CE_IC_OP_CNTL__INVALIDATE_CACHE_MASK                                                               0x00000001L
#define CP_CE_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE_MASK                                                      0x00000002L
#define CP_CE_IC_OP_CNTL__PRIME_ICACHE_MASK                                                                   0x00000010L
#define CP_CE_IC_OP_CNTL__ICACHE_PRIMED_MASK                                                                  0x00000020L
//CP_CPC_IC_BASE_LO
#define CP_CPC_IC_BASE_LO__IC_BASE_LO__SHIFT                                                                  0xc
#define CP_CPC_IC_BASE_LO__IC_BASE_LO_MASK                                                                    0xFFFFF000L
//CP_CPC_IC_BASE_HI
#define CP_CPC_IC_BASE_HI__IC_BASE_HI__SHIFT                                                                  0x0
#define CP_CPC_IC_BASE_HI__IC_BASE_HI_MASK                                                                    0x0000FFFFL
//CP_CPC_IC_BASE_CNTL
#define CP_CPC_IC_BASE_CNTL__VMID__SHIFT                                                                      0x0
#define CP_CPC_IC_BASE_CNTL__ADDRESS_CLAMP__SHIFT                                                             0x4
#define CP_CPC_IC_BASE_CNTL__EXE_DISABLE__SHIFT                                                               0x17
#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT                                                              0x18
#define CP_CPC_IC_BASE_CNTL__VMID_MASK                                                                        0x0000000FL
#define CP_CPC_IC_BASE_CNTL__ADDRESS_CLAMP_MASK                                                               0x00000010L
#define CP_CPC_IC_BASE_CNTL__EXE_DISABLE_MASK                                                                 0x00800000L
#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY_MASK                                                                0x03000000L
//CP_CPC_IC_OP_CNTL
#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT                                                            0x0
#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE__SHIFT                                                   0x1
#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE__SHIFT                                                                0x4
#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED__SHIFT                                                               0x5
#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_MASK                                                              0x00000001L
#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE_MASK                                                     0x00000002L
#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE_MASK                                                                  0x00000010L
#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED_MASK                                                                 0x00000020L
//CP_MES_IC_BASE_LO
#define CP_MES_IC_BASE_LO__IC_BASE_LO__SHIFT                                                                  0xc
#define CP_MES_IC_BASE_LO__IC_BASE_LO_MASK                                                                    0xFFFFF000L
//CP_MES_MIBASE_LO
#define CP_MES_MIBASE_LO__IC_BASE_LO__SHIFT                                                                   0xc
#define CP_MES_MIBASE_LO__IC_BASE_LO_MASK                                                                     0xFFFFF000L
//CP_MES_IC_BASE_HI
#define CP_MES_IC_BASE_HI__IC_BASE_HI__SHIFT                                                                  0x0
#define CP_MES_IC_BASE_HI__IC_BASE_HI_MASK                                                                    0x0000FFFFL
//CP_MES_MIBASE_HI
#define CP_MES_MIBASE_HI__IC_BASE_HI__SHIFT                                                                   0x0
#define CP_MES_MIBASE_HI__IC_BASE_HI_MASK                                                                     0x0000FFFFL
//CP_MES_IC_BASE_CNTL
#define CP_MES_IC_BASE_CNTL__VMID__SHIFT                                                                      0x0
#define CP_MES_IC_BASE_CNTL__EXE_DISABLE__SHIFT                                                               0x17
#define CP_MES_IC_BASE_CNTL__CACHE_POLICY__SHIFT                                                              0x18
#define CP_MES_IC_BASE_CNTL__VMID_MASK                                                                        0x0000000FL
#define CP_MES_IC_BASE_CNTL__EXE_DISABLE_MASK                                                                 0x00800000L
#define CP_MES_IC_BASE_CNTL__CACHE_POLICY_MASK                                                                0x03000000L
//CP_MES_DC_BASE_LO
#define CP_MES_DC_BASE_LO__DC_BASE_LO__SHIFT                                                                  0x10
#define CP_MES_DC_BASE_LO__DC_BASE_LO_MASK                                                                    0xFFFF0000L
//CP_MES_MDBASE_LO
#define CP_MES_MDBASE_LO__BASE_LO__SHIFT                                                                      0x10
#define CP_MES_MDBASE_LO__BASE_LO_MASK                                                                        0xFFFF0000L
//CP_MES_DC_BASE_HI
#define CP_MES_DC_BASE_HI__DC_BASE_HI__SHIFT                                                                  0x0
#define CP_MES_DC_BASE_HI__DC_BASE_HI_MASK                                                                    0x0000FFFFL
//CP_MES_MDBASE_HI
#define CP_MES_MDBASE_HI__BASE_HI__SHIFT                                                                      0x0
#define CP_MES_MDBASE_HI__BASE_HI_MASK                                                                        0x0000FFFFL
//CP_MES_LOCAL_BASE0_LO
#define CP_MES_LOCAL_BASE0_LO__BASE0_LO__SHIFT                                                                0x10
#define CP_MES_LOCAL_BASE0_LO__BASE0_LO_MASK                                                                  0xFFFF0000L
//CP_MES_LOCAL_BASE0_HI
#define CP_MES_LOCAL_BASE0_HI__BASE0_HI__SHIFT                                                                0x0
#define CP_MES_LOCAL_BASE0_HI__BASE0_HI_MASK                                                                  0x0000FFFFL
//CP_MES_LOCAL_MASK0_LO
#define CP_MES_LOCAL_MASK0_LO__MASK0_LO__SHIFT                                                                0x10
#define CP_MES_LOCAL_MASK0_LO__MASK0_LO_MASK                                                                  0xFFFF0000L
//CP_MES_LOCAL_MASK0_HI
#define CP_MES_LOCAL_MASK0_HI__MASK0_HI__SHIFT                                                                0x0
#define CP_MES_LOCAL_MASK0_HI__MASK0_HI_MASK                                                                  0x0000FFFFL
//CP_MES_LOCAL_APERTURE
#define CP_MES_LOCAL_APERTURE__APERTURE__SHIFT                                                                0x0
#define CP_MES_LOCAL_APERTURE__APERTURE_MASK                                                                  0x00000003L
//CP_MES_MIBOUND_LO
#define CP_MES_MIBOUND_LO__BOUND_LO__SHIFT                                                                    0x0
#define CP_MES_MIBOUND_LO__BOUND_LO_MASK                                                                      0xFFFFFFFFL
//CP_MES_MIBOUND_HI
#define CP_MES_MIBOUND_HI__BOUND_HI__SHIFT                                                                    0x0
#define CP_MES_MIBOUND_HI__BOUND_HI_MASK                                                                      0xFFFFFFFFL
//CP_MES_MDBOUND_LO
#define CP_MES_MDBOUND_LO__BOUND_LO__SHIFT                                                                    0x0
#define CP_MES_MDBOUND_LO__BOUND_LO_MASK                                                                      0xFFFFFFFFL
//CP_MES_MDBOUND_HI
#define CP_MES_MDBOUND_HI__BOUND_HI__SHIFT                                                                    0x0
#define CP_MES_MDBOUND_HI__BOUND_HI_MASK                                                                      0xFFFFFFFFL
//GFX_PIPE_PRIORITY
#define GFX_PIPE_PRIORITY__HP_PIPE_SELECT__SHIFT                                                              0x0
#define GFX_PIPE_PRIORITY__HP_PIPE_SELECT_MASK                                                                0x00000001L
//GRBM_GFX_INDEX_SR_SELECT
#define GRBM_GFX_INDEX_SR_SELECT__INDEX__SHIFT                                                                0x0
#define GRBM_GFX_INDEX_SR_SELECT__VF_PF__SHIFT                                                                0x1f
#define GRBM_GFX_INDEX_SR_SELECT__INDEX_MASK                                                                  0x00000007L
#define GRBM_GFX_INDEX_SR_SELECT__VF_PF_MASK                                                                  0x80000000L
//GRBM_GFX_INDEX_SR_DATA
#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX__SHIFT                                                         0x0
#define GRBM_GFX_INDEX_SR_DATA__SA_INDEX__SHIFT                                                               0x8
#define GRBM_GFX_INDEX_SR_DATA__SE_INDEX__SHIFT                                                               0x10
#define GRBM_GFX_INDEX_SR_DATA__SA_BROADCAST_WRITES__SHIFT                                                    0x1d
#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES__SHIFT                                              0x1e
#define GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES__SHIFT                                                    0x1f
#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX_MASK                                                           0x000000FFL
#define GRBM_GFX_INDEX_SR_DATA__SA_INDEX_MASK                                                                 0x0000FF00L
#define GRBM_GFX_INDEX_SR_DATA__SE_INDEX_MASK                                                                 0x00FF0000L
#define GRBM_GFX_INDEX_SR_DATA__SA_BROADCAST_WRITES_MASK                                                      0x20000000L
#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES_MASK                                                0x40000000L
#define GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES_MASK                                                      0x80000000L
//GRBM_GFX_CNTL_SR_SELECT
#define GRBM_GFX_CNTL_SR_SELECT__INDEX__SHIFT                                                                 0x0
#define GRBM_GFX_CNTL_SR_SELECT__VF_PF__SHIFT                                                                 0x1f
#define GRBM_GFX_CNTL_SR_SELECT__INDEX_MASK                                                                   0x00000007L
#define GRBM_GFX_CNTL_SR_SELECT__VF_PF_MASK                                                                   0x80000000L
//GRBM_GFX_CNTL_SR_DATA
#define GRBM_GFX_CNTL_SR_DATA__PIPEID__SHIFT                                                                  0x0
#define GRBM_GFX_CNTL_SR_DATA__MEID__SHIFT                                                                    0x2
#define GRBM_GFX_CNTL_SR_DATA__VMID__SHIFT                                                                    0x4
#define GRBM_GFX_CNTL_SR_DATA__QUEUEID__SHIFT                                                                 0x8
#define GRBM_GFX_CNTL_SR_DATA__PIPEID_MASK                                                                    0x00000003L
#define GRBM_GFX_CNTL_SR_DATA__MEID_MASK                                                                      0x0000000CL
#define GRBM_GFX_CNTL_SR_DATA__VMID_MASK                                                                      0x000000F0L
#define GRBM_GFX_CNTL_SR_DATA__QUEUEID_MASK                                                                   0x00000700L
//GRBM_CAM_INDEX
#define GRBM_CAM_INDEX__CAM_INDEX__SHIFT                                                                      0x0
#define GRBM_CAM_INDEX__CAM_INDEX_MASK                                                                        0x0000000FL
//GRBM_HYP_CAM_INDEX
#define GRBM_HYP_CAM_INDEX__CAM_INDEX__SHIFT                                                                  0x0
#define GRBM_HYP_CAM_INDEX__CAM_INDEX_MASK                                                                    0x0000000FL
//GRBM_CAM_DATA
#define GRBM_CAM_DATA__CAM_ADDR__SHIFT                                                                        0x0
#define GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT                                                                   0x10
#define GRBM_CAM_DATA__CAM_ADDR_MASK                                                                          0x0000FFFFL
#define GRBM_CAM_DATA__CAM_REMAPADDR_MASK                                                                     0xFFFF0000L
//GRBM_HYP_CAM_DATA
#define GRBM_HYP_CAM_DATA__CAM_ADDR__SHIFT                                                                    0x0
#define GRBM_HYP_CAM_DATA__CAM_REMAPADDR__SHIFT                                                               0x10
#define GRBM_HYP_CAM_DATA__CAM_ADDR_MASK                                                                      0x0000FFFFL
#define GRBM_HYP_CAM_DATA__CAM_REMAPADDR_MASK                                                                 0xFFFF0000L
//GRBM_CAM_DATA_UPPER
#define GRBM_CAM_DATA_UPPER__CAM_ADDR__SHIFT                                                                  0x0
#define GRBM_CAM_DATA_UPPER__CAM_REMAPADDR__SHIFT                                                             0x10
#define GRBM_CAM_DATA_UPPER__CAM_ADDR_MASK                                                                    0x00000003L
#define GRBM_CAM_DATA_UPPER__CAM_REMAPADDR_MASK                                                               0x00030000L
//GRBM_HYP_CAM_DATA_UPPER
#define GRBM_HYP_CAM_DATA_UPPER__CAM_ADDR__SHIFT                                                              0x0
#define GRBM_HYP_CAM_DATA_UPPER__CAM_REMAPADDR__SHIFT                                                         0x10
#define GRBM_HYP_CAM_DATA_UPPER__CAM_ADDR_MASK                                                                0x00000003L
#define GRBM_HYP_CAM_DATA_UPPER__CAM_REMAPADDR_MASK                                                           0x00030000L
//GC_IH_COOKIE_0_PTR
#define GC_IH_COOKIE_0_PTR__ADDR__SHIFT                                                                       0x0
#define GC_IH_COOKIE_0_PTR__ADDR_MASK                                                                         0x000FFFFFL
//GRBM_SE_REMAP_CNTL
#define GRBM_SE_REMAP_CNTL__SE0_REMAP_EN__SHIFT                                                               0x0
#define GRBM_SE_REMAP_CNTL__SE0_REMAP__SHIFT                                                                  0x1
#define GRBM_SE_REMAP_CNTL__SE1_REMAP_EN__SHIFT                                                               0x4
#define GRBM_SE_REMAP_CNTL__SE1_REMAP__SHIFT                                                                  0x5
#define GRBM_SE_REMAP_CNTL__SE2_REMAP_EN__SHIFT                                                               0x8
#define GRBM_SE_REMAP_CNTL__SE2_REMAP__SHIFT                                                                  0x9
#define GRBM_SE_REMAP_CNTL__SE3_REMAP_EN__SHIFT                                                               0xc
#define GRBM_SE_REMAP_CNTL__SE3_REMAP__SHIFT                                                                  0xd
#define GRBM_SE_REMAP_CNTL__SE4_REMAP_EN__SHIFT                                                               0x10
#define GRBM_SE_REMAP_CNTL__SE4_REMAP__SHIFT                                                                  0x11
#define GRBM_SE_REMAP_CNTL__SE5_REMAP_EN__SHIFT                                                               0x14
#define GRBM_SE_REMAP_CNTL__SE5_REMAP__SHIFT                                                                  0x15
#define GRBM_SE_REMAP_CNTL__SE6_REMAP_EN__SHIFT                                                               0x18
#define GRBM_SE_REMAP_CNTL__SE6_REMAP__SHIFT                                                                  0x19
#define GRBM_SE_REMAP_CNTL__SE7_REMAP_EN__SHIFT                                                               0x1c
#define GRBM_SE_REMAP_CNTL__SE7_REMAP__SHIFT                                                                  0x1d
#define GRBM_SE_REMAP_CNTL__SE0_REMAP_EN_MASK                                                                 0x00000001L
#define GRBM_SE_REMAP_CNTL__SE0_REMAP_MASK                                                                    0x0000000EL
#define GRBM_SE_REMAP_CNTL__SE1_REMAP_EN_MASK                                                                 0x00000010L
#define GRBM_SE_REMAP_CNTL__SE1_REMAP_MASK                                                                    0x000000E0L
#define GRBM_SE_REMAP_CNTL__SE2_REMAP_EN_MASK                                                                 0x00000100L
#define GRBM_SE_REMAP_CNTL__SE2_REMAP_MASK                                                                    0x00000E00L
#define GRBM_SE_REMAP_CNTL__SE3_REMAP_EN_MASK                                                                 0x00001000L
#define GRBM_SE_REMAP_CNTL__SE3_REMAP_MASK                                                                    0x0000E000L
#define GRBM_SE_REMAP_CNTL__SE4_REMAP_EN_MASK                                                                 0x00010000L
#define GRBM_SE_REMAP_CNTL__SE4_REMAP_MASK                                                                    0x000E0000L
#define GRBM_SE_REMAP_CNTL__SE5_REMAP_EN_MASK                                                                 0x00100000L
#define GRBM_SE_REMAP_CNTL__SE5_REMAP_MASK                                                                    0x00E00000L
#define GRBM_SE_REMAP_CNTL__SE6_REMAP_EN_MASK                                                                 0x01000000L
#define GRBM_SE_REMAP_CNTL__SE6_REMAP_MASK                                                                    0x0E000000L
#define GRBM_SE_REMAP_CNTL__SE7_REMAP_EN_MASK                                                                 0x10000000L
#define GRBM_SE_REMAP_CNTL__SE7_REMAP_MASK                                                                    0xE0000000L
//RLC_GPU_IOV_VF_ENABLE
#define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE__SHIFT                                                               0x0
#define RLC_GPU_IOV_VF_ENABLE__RESERVED__SHIFT                                                                0x1
#define RLC_GPU_IOV_VF_ENABLE__VF_NUM__SHIFT                                                                  0x10
#define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE_MASK                                                                 0x00000001L
#define RLC_GPU_IOV_VF_ENABLE__RESERVED_MASK                                                                  0x0000FFFEL
#define RLC_GPU_IOV_VF_ENABLE__VF_NUM_MASK                                                                    0xFFFF0000L
//RLC_GPU_IOV_CFG_REG6
#define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE__SHIFT                                                               0x0
#define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION__SHIFT                                                           0x7
#define RLC_GPU_IOV_CFG_REG6__RESERVED__SHIFT                                                                 0x8
#define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET__SHIFT                                                             0xa
#define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE_MASK                                                                 0x0000007FL
#define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION_MASK                                                             0x00000080L
#define RLC_GPU_IOV_CFG_REG6__RESERVED_MASK                                                                   0x00000300L
#define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET_MASK                                                               0xFFFFFC00L
//RLC_SDMA0_STATUS
#define RLC_SDMA0_STATUS__STATUS__SHIFT                                                                       0x0
#define RLC_SDMA0_STATUS__STATUS_MASK                                                                         0xFFFFFFFFL
//RLC_SDMA1_STATUS
#define RLC_SDMA1_STATUS__STATUS__SHIFT                                                                       0x0
#define RLC_SDMA1_STATUS__STATUS_MASK                                                                         0xFFFFFFFFL
//RLC_SDMA2_STATUS
#define RLC_SDMA2_STATUS__STATUS__SHIFT                                                                       0x0
#define RLC_SDMA2_STATUS__STATUS_MASK                                                                         0xFFFFFFFFL
//RLC_SDMA3_STATUS
#define RLC_SDMA3_STATUS__STATUS__SHIFT                                                                       0x0
#define RLC_SDMA3_STATUS__STATUS_MASK                                                                         0xFFFFFFFFL
//RLC_SDMA0_BUSY_STATUS
#define RLC_SDMA0_BUSY_STATUS__BUSY_STATUS__SHIFT                                                             0x0
#define RLC_SDMA0_BUSY_STATUS__BUSY_STATUS_MASK                                                               0xFFFFFFFFL
//RLC_SDMA1_BUSY_STATUS
#define RLC_SDMA1_BUSY_STATUS__BUSY_STATUS__SHIFT                                                             0x0
#define RLC_SDMA1_BUSY_STATUS__BUSY_STATUS_MASK                                                               0xFFFFFFFFL
//RLC_SDMA2_BUSY_STATUS
#define RLC_SDMA2_BUSY_STATUS__BUSY_STATUS__SHIFT                                                             0x0
#define RLC_SDMA2_BUSY_STATUS__BUSY_STATUS_MASK                                                               0xFFFFFFFFL
//RLC_SDMA3_BUSY_STATUS
#define RLC_SDMA3_BUSY_STATUS__BUSY_STATUS__SHIFT                                                             0x0
#define RLC_SDMA3_BUSY_STATUS__BUSY_STATUS_MASK                                                               0xFFFFFFFFL
//RLC_GPU_IOV_CFG_REG8
#define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS__SHIFT                                                           0x0
#define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS_MASK                                                             0xFFFFFFFFL
//RLC_RLCV_TIMER_INT_0
#define RLC_RLCV_TIMER_INT_0__TIMER__SHIFT                                                                    0x0
#define RLC_RLCV_TIMER_INT_0__TIMER_MASK                                                                      0xFFFFFFFFL
//RLC_RLCV_TIMER_CTRL
#define RLC_RLCV_TIMER_CTRL__TIMER_0_EN__SHIFT                                                                0x0
#define RLC_RLCV_TIMER_CTRL__TIMER_1_EN__SHIFT                                                                0x1
#define RLC_RLCV_TIMER_CTRL__TIMER_0_AUTO_REARM__SHIFT                                                        0x2
#define RLC_RLCV_TIMER_CTRL__TIMER_1_AUTO_REARM__SHIFT                                                        0x3
#define RLC_RLCV_TIMER_CTRL__TIMER_0_INT_CLEAR__SHIFT                                                         0x4
#define RLC_RLCV_TIMER_CTRL__TIMER_1_INT_CLEAR__SHIFT                                                         0x5
#define RLC_RLCV_TIMER_CTRL__RESERVED__SHIFT                                                                  0x6
#define RLC_RLCV_TIMER_CTRL__TIMER_0_EN_MASK                                                                  0x00000001L
#define RLC_RLCV_TIMER_CTRL__TIMER_1_EN_MASK                                                                  0x00000002L
#define RLC_RLCV_TIMER_CTRL__TIMER_0_AUTO_REARM_MASK                                                          0x00000004L
#define RLC_RLCV_TIMER_CTRL__TIMER_1_AUTO_REARM_MASK                                                          0x00000008L
#define RLC_RLCV_TIMER_CTRL__TIMER_0_INT_CLEAR_MASK                                                           0x00000010L
#define RLC_RLCV_TIMER_CTRL__TIMER_1_INT_CLEAR_MASK                                                           0x00000020L
#define RLC_RLCV_TIMER_CTRL__RESERVED_MASK                                                                    0xFFFFFFC0L
//RLC_RLCV_TIMER_STAT
#define RLC_RLCV_TIMER_STAT__TIMER_0_STAT__SHIFT                                                              0x0
#define RLC_RLCV_TIMER_STAT__TIMER_1_STAT__SHIFT                                                              0x1
#define RLC_RLCV_TIMER_STAT__RESERVED__SHIFT                                                                  0x2
#define RLC_RLCV_TIMER_STAT__TIMER_0_ENABLE_SYNC__SHIFT                                                       0x8
#define RLC_RLCV_TIMER_STAT__TIMER_1_ENABLE_SYNC__SHIFT                                                       0x9
#define RLC_RLCV_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC__SHIFT                                                   0xa
#define RLC_RLCV_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC__SHIFT                                                   0xb
#define RLC_RLCV_TIMER_STAT__TIMER_0_STAT_MASK                                                                0x00000001L
#define RLC_RLCV_TIMER_STAT__TIMER_1_STAT_MASK                                                                0x00000002L
#define RLC_RLCV_TIMER_STAT__RESERVED_MASK                                                                    0x000000FCL
#define RLC_RLCV_TIMER_STAT__TIMER_0_ENABLE_SYNC_MASK                                                         0x00000100L
#define RLC_RLCV_TIMER_STAT__TIMER_1_ENABLE_SYNC_MASK                                                         0x00000200L
#define RLC_RLCV_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC_MASK                                                     0x00000400L
#define RLC_RLCV_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC_MASK                                                     0x00000800L
//RLC_GPU_IOV_VF_DOORBELL_STATUS
#define RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS__SHIFT                                             0x0
#define RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS__SHIFT                                             0x1f
#define RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_MASK                                               0x7FFFFFFFL
#define RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS_MASK                                               0x80000000L
//RLC_GPU_IOV_VF_DOORBELL_STATUS_SET
#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET__SHIFT                                     0x0
#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET__SHIFT                                     0x1f
#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET_MASK                                       0x7FFFFFFFL
#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET_MASK                                       0x80000000L
//RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR
#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR__SHIFT                                     0x0
#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR__SHIFT                                     0x1f
#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR_MASK                                       0x7FFFFFFFL
#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR_MASK                                       0x80000000L
//RLC_GPU_IOV_VF_MASK
#define RLC_GPU_IOV_VF_MASK__VF_MASK__SHIFT                                                                   0x0
#define RLC_GPU_IOV_VF_MASK__VF_MASK_MASK                                                                     0x7FFFFFFFL
//RLC_HYP_SEMAPHORE_0
#define RLC_HYP_SEMAPHORE_0__CLIENT_ID__SHIFT                                                                 0x0
#define RLC_HYP_SEMAPHORE_0__RESERVED__SHIFT                                                                  0x5
#define RLC_HYP_SEMAPHORE_0__CLIENT_ID_MASK                                                                   0x0000001FL
#define RLC_HYP_SEMAPHORE_0__RESERVED_MASK                                                                    0xFFFFFFE0L
//RLC_HYP_SEMAPHORE_1
#define RLC_HYP_SEMAPHORE_1__CLIENT_ID__SHIFT                                                                 0x0
#define RLC_HYP_SEMAPHORE_1__RESERVED__SHIFT                                                                  0x5
#define RLC_HYP_SEMAPHORE_1__CLIENT_ID_MASK                                                                   0x0000001FL
#define RLC_HYP_SEMAPHORE_1__RESERVED_MASK                                                                    0xFFFFFFE0L
//RLC_BUSY_CLK_CNTL
#define RLC_BUSY_CLK_CNTL__BUSY_OFF_LATENCY__SHIFT                                                            0x0
#define RLC_BUSY_CLK_CNTL__BUSY_OFF_LATENCY_MASK                                                              0x0000003FL
//RLC_CLK_CNTL
#define RLC_CLK_CNTL__RLC_SRM_CLK_CNTL__SHIFT                                                                 0x0
#define RLC_CLK_CNTL__RLC_SPM_CLK_CNTL__SHIFT                                                                 0x2
#define RLC_CLK_CNTL__RLC_GPM_CLK_CNTL__SHIFT                                                                 0x4
#define RLC_CLK_CNTL__RLC_CMN_CLK_CNTL__SHIFT                                                                 0x5
#define RLC_CLK_CNTL__RLC_TC_CLK_CNTL__SHIFT                                                                  0x6
#define RLC_CLK_CNTL__RESERVED_7__SHIFT                                                                       0x7
#define RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE__SHIFT                                                      0x8
#define RLC_CLK_CNTL__RESERVED_9__SHIFT                                                                       0x9
#define RLC_CLK_CNTL__RLC_SPP_CLK_CNTL__SHIFT                                                                 0xa
#define RLC_CLK_CNTL__RLC_TC_FGCG_REP_OVERRIDE__SHIFT                                                         0xc
#define RLC_CLK_CNTL__RESERVED_15__SHIFT                                                                      0xf
#define RLC_CLK_CNTL__RLC_UTCL2_FGCG_OVERRIDE__SHIFT                                                          0x12
#define RLC_CLK_CNTL__RESERVED__SHIFT                                                                         0x13
#define RLC_CLK_CNTL__RLC_SRM_CLK_CNTL_MASK                                                                   0x00000003L
#define RLC_CLK_CNTL__RLC_SPM_CLK_CNTL_MASK                                                                   0x0000000CL
#define RLC_CLK_CNTL__RLC_GPM_CLK_CNTL_MASK                                                                   0x00000010L
#define RLC_CLK_CNTL__RLC_CMN_CLK_CNTL_MASK                                                                   0x00000020L
#define RLC_CLK_CNTL__RLC_TC_CLK_CNTL_MASK                                                                    0x00000040L
#define RLC_CLK_CNTL__RESERVED_7_MASK                                                                         0x00000080L
#define RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK                                                        0x00000100L
#define RLC_CLK_CNTL__RESERVED_9_MASK                                                                         0x00000200L
#define RLC_CLK_CNTL__RLC_SPP_CLK_CNTL_MASK                                                                   0x00000C00L
#define RLC_CLK_CNTL__RLC_TC_FGCG_REP_OVERRIDE_MASK                                                           0x00001000L
#define RLC_CLK_CNTL__RESERVED_15_MASK                                                                        0x00008000L
#define RLC_CLK_CNTL__RLC_UTCL2_FGCG_OVERRIDE_MASK                                                            0x00040000L
#define RLC_CLK_CNTL__RESERVED_MASK                                                                           0xFFF80000L
//RLC_PACE_TIMER_STAT
#define RLC_PACE_TIMER_STAT__TIMER_0_STAT__SHIFT                                                              0x0
#define RLC_PACE_TIMER_STAT__TIMER_1_STAT__SHIFT                                                              0x1
#define RLC_PACE_TIMER_STAT__RESERVED__SHIFT                                                                  0x2
#define RLC_PACE_TIMER_STAT__TIMER_0_ENABLE_SYNC__SHIFT                                                       0x8
#define RLC_PACE_TIMER_STAT__TIMER_1_ENABLE_SYNC__SHIFT                                                       0x9
#define RLC_PACE_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC__SHIFT                                                   0xa
#define RLC_PACE_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC__SHIFT                                                   0xb
#define RLC_PACE_TIMER_STAT__TIMER_0_STAT_MASK                                                                0x00000001L
#define RLC_PACE_TIMER_STAT__TIMER_1_STAT_MASK                                                                0x00000002L
#define RLC_PACE_TIMER_STAT__RESERVED_MASK                                                                    0x000000FCL
#define RLC_PACE_TIMER_STAT__TIMER_0_ENABLE_SYNC_MASK                                                         0x00000100L
#define RLC_PACE_TIMER_STAT__TIMER_1_ENABLE_SYNC_MASK                                                         0x00000200L
#define RLC_PACE_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC_MASK                                                     0x00000400L
#define RLC_PACE_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC_MASK                                                     0x00000800L
//RLC_GPU_IOV_SCH_BLOCK
#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID__SHIFT                                                            0x0
#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver__SHIFT                                                           0x4
#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size__SHIFT                                                          0x8
#define RLC_GPU_IOV_SCH_BLOCK__RESERVED__SHIFT                                                                0x10
#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID_MASK                                                              0x0000000FL
#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver_MASK                                                             0x000000F0L
#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size_MASK                                                            0x00007F00L
#define RLC_GPU_IOV_SCH_BLOCK__RESERVED_MASK                                                                  0x7FFF0000L
//RLC_GPU_IOV_CFG_REG1
#define RLC_GPU_IOV_CFG_REG1__CMD_TYPE__SHIFT                                                                 0x0
#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE__SHIFT                                                              0x4
#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN__SHIFT                                                      0x5
#define RLC_GPU_IOV_CFG_REG1__RESERVED__SHIFT                                                                 0x6
#define RLC_GPU_IOV_CFG_REG1__FCN_ID__SHIFT                                                                   0x8
#define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID__SHIFT                                                              0x10
#define RLC_GPU_IOV_CFG_REG1__RESERVED1__SHIFT                                                                0x18
#define RLC_GPU_IOV_CFG_REG1__CMD_TYPE_MASK                                                                   0x0000000FL
#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_MASK                                                                0x00000010L
#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN_MASK                                                        0x00000020L
#define RLC_GPU_IOV_CFG_REG1__RESERVED_MASK                                                                   0x000000C0L
#define RLC_GPU_IOV_CFG_REG1__FCN_ID_MASK                                                                     0x0000FF00L
#define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID_MASK                                                                0x00FF0000L
#define RLC_GPU_IOV_CFG_REG1__RESERVED1_MASK                                                                  0xFF000000L
//RLC_GPU_IOV_CFG_REG2
#define RLC_GPU_IOV_CFG_REG2__CMD_STATUS__SHIFT                                                               0x0
#define RLC_GPU_IOV_CFG_REG2__RESERVED__SHIFT                                                                 0x4
#define RLC_GPU_IOV_CFG_REG2__CMD_STATUS_MASK                                                                 0x0000000FL
#define RLC_GPU_IOV_CFG_REG2__RESERVED_MASK                                                                   0xFFFFFFF0L
//RLC_GPU_IOV_VM_BUSY_STATUS
#define RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS__SHIFT                                                     0x0
#define RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS_MASK                                                       0xFFFFFFFFL
//RLC_GPU_IOV_SCH_0
#define RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS__SHIFT                                                            0x0
#define RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS_MASK                                                              0xFFFFFFFFL
//RLC_GPU_IOV_ACTIVE_FCN_ID
#define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID__SHIFT                                                               0x0
#define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED__SHIFT                                                            0x5
#define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF__SHIFT                                                               0x1f
#define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID_MASK                                                                 0x0000001FL
#define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED_MASK                                                              0x7FFFFFE0L
#define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF_MASK                                                                 0x80000000L
//RLC_GPU_IOV_SCH_3
#define RLC_GPU_IOV_SCH_3__Time_Quanta_Def__SHIFT                                                             0x0
#define RLC_GPU_IOV_SCH_3__Time_Quanta_Def_MASK                                                               0xFFFFFFFFL
//RLC_GPU_IOV_SCH_1
#define RLC_GPU_IOV_SCH_1__DATA__SHIFT                                                                        0x0
#define RLC_GPU_IOV_SCH_1__DATA_MASK                                                                          0xFFFFFFFFL
//RLC_GPU_IOV_SCH_2
#define RLC_GPU_IOV_SCH_2__DATA__SHIFT                                                                        0x0
#define RLC_GPU_IOV_SCH_2__DATA_MASK                                                                          0xFFFFFFFFL
//RLC_PACE_INT_FORCE
#define RLC_PACE_INT_FORCE__FORCE_INT__SHIFT                                                                  0x0
#define RLC_PACE_INT_FORCE__FORCE_INT_MASK                                                                    0xFFFFFFFFL
//RLC_PACE_INT_CLEAR
#define RLC_PACE_INT_CLEAR__SMU_STRETCH_PCC_CLEAR__SHIFT                                                      0x0
#define RLC_PACE_INT_CLEAR__SMU_PCC_CLEAR__SHIFT                                                              0x1
#define RLC_PACE_INT_CLEAR__SMU_STRETCH_PCC_CLEAR_MASK                                                        0x00000001L
#define RLC_PACE_INT_CLEAR__SMU_PCC_CLEAR_MASK                                                                0x00000002L
//RLC_GPU_IOV_INT_STAT
#define RLC_GPU_IOV_INT_STAT__STATUS__SHIFT                                                                   0x0
#define RLC_GPU_IOV_INT_STAT__STATUS_MASK                                                                     0xFFFFFFFFL
//RLC_RLCV_TIMER_INT_1
#define RLC_RLCV_TIMER_INT_1__TIMER__SHIFT                                                                    0x0
#define RLC_RLCV_TIMER_INT_1__TIMER_MASK                                                                      0xFFFFFFFFL
//RLC_IH_COOKIE
#define RLC_IH_COOKIE__DATA__SHIFT                                                                            0x0
#define RLC_IH_COOKIE__DATA_MASK                                                                              0xFFFFFFFFL
//RLC_IH_COOKIE_CNTL
#define RLC_IH_COOKIE_CNTL__CREDIT__SHIFT                                                                     0x0
#define RLC_IH_COOKIE_CNTL__RESET_COUNTER__SHIFT                                                              0x2
#define RLC_IH_COOKIE_CNTL__CREDIT_MASK                                                                       0x00000003L
#define RLC_IH_COOKIE_CNTL__RESET_COUNTER_MASK                                                                0x00000004L
//RLC_HYP_RLCG_UCODE_CHKSUM
#define RLC_HYP_RLCG_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT                                                        0x0
#define RLC_HYP_RLCG_UCODE_CHKSUM__UCODE_CHKSUM_MASK                                                          0xFFFFFFFFL
//RLC_HYP_RLCP_UCODE_CHKSUM
#define RLC_HYP_RLCP_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT                                                        0x0
#define RLC_HYP_RLCP_UCODE_CHKSUM__UCODE_CHKSUM_MASK                                                          0xFFFFFFFFL
//RLC_HYP_RLCV_UCODE_CHKSUM
#define RLC_HYP_RLCV_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT                                                        0x0
#define RLC_HYP_RLCV_UCODE_CHKSUM__UCODE_CHKSUM_MASK                                                          0xFFFFFFFFL
//RLC_GPU_IOV_F32_CNTL
#define RLC_GPU_IOV_F32_CNTL__ENABLE__SHIFT                                                                   0x0
#define RLC_GPU_IOV_F32_CNTL__ENABLE_MASK                                                                     0x00000001L
//RLC_GPU_IOV_F32_RESET
#define RLC_GPU_IOV_F32_RESET__RESET__SHIFT                                                                   0x0
#define RLC_GPU_IOV_F32_RESET__RESET_MASK                                                                     0x00000001L
//RLC_GPU_IOV_SMU_RESPONSE
#define RLC_GPU_IOV_SMU_RESPONSE__RESP__SHIFT                                                                 0x0
#define RLC_GPU_IOV_SMU_RESPONSE__RESP_MASK                                                                   0xFFFFFFFFL
//RLC_GPU_IOV_VIRT_RESET_REQ
#define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR__SHIFT                                                             0x0
#define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR__SHIFT                                                        0x1f
#define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR_MASK                                                               0x7FFFFFFFL
#define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR_MASK                                                          0x80000000L
//RLC_GPU_IOV_RLC_RESPONSE
#define RLC_GPU_IOV_RLC_RESPONSE__RESP__SHIFT                                                                 0x0
#define RLC_GPU_IOV_RLC_RESPONSE__RESP_MASK                                                                   0xFFFFFFFFL
//RLC_GPU_IOV_INT_DISABLE
#define RLC_GPU_IOV_INT_DISABLE__DISABLE_INT__SHIFT                                                           0x0
#define RLC_GPU_IOV_INT_DISABLE__DISABLE_INT_MASK                                                             0xFFFFFFFFL
//RLC_GPU_IOV_INT_FORCE
#define RLC_GPU_IOV_INT_FORCE__FORCE_INT__SHIFT                                                               0x0
#define RLC_GPU_IOV_INT_FORCE__FORCE_INT_MASK                                                                 0xFFFFFFFFL
//RLC_HYP_SEMAPHORE_2
#define RLC_HYP_SEMAPHORE_2__CLIENT_ID__SHIFT                                                                 0x0
#define RLC_HYP_SEMAPHORE_2__RESERVED__SHIFT                                                                  0x5
#define RLC_HYP_SEMAPHORE_2__CLIENT_ID_MASK                                                                   0x0000001FL
#define RLC_HYP_SEMAPHORE_2__RESERVED_MASK                                                                    0xFFFFFFE0L
//RLC_HYP_SEMAPHORE_3
#define RLC_HYP_SEMAPHORE_3__CLIENT_ID__SHIFT                                                                 0x0
#define RLC_HYP_SEMAPHORE_3__RESERVED__SHIFT                                                                  0x5
#define RLC_HYP_SEMAPHORE_3__CLIENT_ID_MASK                                                                   0x0000001FL
#define RLC_HYP_SEMAPHORE_3__RESERVED_MASK                                                                    0xFFFFFFE0L
//RLC_HYP_RESET_VECTOR
#define RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT__SHIFT                                                           0x0
#define RLC_HYP_RESET_VECTOR__VDDGFX_EXIT__SHIFT                                                              0x1
#define RLC_HYP_RESET_VECTOR__WARM_RESET_EXIT__SHIFT                                                          0x2
#define RLC_HYP_RESET_VECTOR__VF_FLR_EXIT__SHIFT                                                              0x3
#define RLC_HYP_RESET_VECTOR__RESERVED_4__SHIFT                                                               0x4
#define RLC_HYP_RESET_VECTOR__RESERVED_5__SHIFT                                                               0x5
#define RLC_HYP_RESET_VECTOR__RESERVED_6__SHIFT                                                               0x6
#define RLC_HYP_RESET_VECTOR__RESERVED_7__SHIFT                                                               0x7
#define RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK                                                             0x00000001L
#define RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK                                                                0x00000002L
#define RLC_HYP_RESET_VECTOR__WARM_RESET_EXIT_MASK                                                            0x00000004L
#define RLC_HYP_RESET_VECTOR__VF_FLR_EXIT_MASK                                                                0x00000008L
#define RLC_HYP_RESET_VECTOR__RESERVED_4_MASK                                                                 0x00000010L
#define RLC_HYP_RESET_VECTOR__RESERVED_5_MASK                                                                 0x00000020L
#define RLC_HYP_RESET_VECTOR__RESERVED_6_MASK                                                                 0x00000040L
#define RLC_HYP_RESET_VECTOR__RESERVED_7_MASK                                                                 0x00000080L
//RLC_HYP_BOOTLOAD_SIZE
#define RLC_HYP_BOOTLOAD_SIZE__SIZE__SHIFT                                                                    0x0
#define RLC_HYP_BOOTLOAD_SIZE__SIZE_MASK                                                                      0x03FFFFFFL
//RLC_HYP_BOOTLOAD_ADDR_LO
#define RLC_HYP_BOOTLOAD_ADDR_LO__ADDR_LO__SHIFT                                                              0x0
#define RLC_HYP_BOOTLOAD_ADDR_LO__ADDR_LO_MASK                                                                0xFFFFFFFFL
//RLC_HYP_BOOTLOAD_ADDR_HI
#define RLC_HYP_BOOTLOAD_ADDR_HI__ADDR_HI__SHIFT                                                              0x0
#define RLC_HYP_BOOTLOAD_ADDR_HI__ADDR_HI_MASK                                                                0xFFFFFFFFL
//RLC_GPM_IRAM_ADDR
#define RLC_GPM_IRAM_ADDR__ADDR__SHIFT                                                                        0x0
#define RLC_GPM_IRAM_ADDR__ADDR_MASK                                                                          0xFFFFFFFFL
//RLC_GPM_IRAM_DATA
#define RLC_GPM_IRAM_DATA__DATA__SHIFT                                                                        0x0
#define RLC_GPM_IRAM_DATA__DATA_MASK                                                                          0xFFFFFFFFL
//RLC_GPM_UCODE_ADDR
#define RLC_GPM_UCODE_ADDR__UCODE_ADDR__SHIFT                                                                 0x0
#define RLC_GPM_UCODE_ADDR__RESERVED__SHIFT                                                                   0xe
#define RLC_GPM_UCODE_ADDR__UCODE_ADDR_MASK                                                                   0x00003FFFL
#define RLC_GPM_UCODE_ADDR__RESERVED_MASK                                                                     0xFFFFC000L
//RLC_GPM_UCODE_DATA
#define RLC_GPM_UCODE_DATA__UCODE_DATA__SHIFT                                                                 0x0
#define RLC_GPM_UCODE_DATA__UCODE_DATA_MASK                                                                   0xFFFFFFFFL
//RLC_PACE_UCODE_ADDR
#define RLC_PACE_UCODE_ADDR__UCODE_ADDR__SHIFT                                                                0x0
#define RLC_PACE_UCODE_ADDR__RESERVED__SHIFT                                                                  0xc
#define RLC_PACE_UCODE_ADDR__UCODE_ADDR_MASK                                                                  0x00000FFFL
#define RLC_PACE_UCODE_ADDR__RESERVED_MASK                                                                    0xFFFFF000L
//RLC_PACE_UCODE_DATA
#define RLC_PACE_UCODE_DATA__UCODE_DATA__SHIFT                                                                0x0
#define RLC_PACE_UCODE_DATA__UCODE_DATA_MASK                                                                  0xFFFFFFFFL
//RLC_GPU_IOV_UCODE_ADDR
#define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR__SHIFT                                                             0x0
#define RLC_GPU_IOV_UCODE_ADDR__RESERVED__SHIFT                                                               0xc
#define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR_MASK                                                               0x00000FFFL
#define RLC_GPU_IOV_UCODE_ADDR__RESERVED_MASK                                                                 0xFFFFF000L
//RLC_GPU_IOV_UCODE_DATA
#define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA__SHIFT                                                             0x0
#define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA_MASK                                                               0xFFFFFFFFL
//RLC_GPU_IOV_SCRATCH_ADDR
#define RLC_GPU_IOV_SCRATCH_ADDR__ADDR__SHIFT                                                                 0x0
#define RLC_GPU_IOV_SCRATCH_ADDR__ADDR_MASK                                                                   0x0000FFFFL
//RLC_GPU_IOV_SCRATCH_DATA
#define RLC_GPU_IOV_SCRATCH_DATA__DATA__SHIFT                                                                 0x0
#define RLC_GPU_IOV_SCRATCH_DATA__DATA_MASK                                                                   0xFFFFFFFFL
//RLC_RLCV_IRAM_ADDR
#define RLC_RLCV_IRAM_ADDR__ADDR__SHIFT                                                                       0x0
#define RLC_RLCV_IRAM_ADDR__ADDR_MASK                                                                         0xFFFFFFFFL
//RLC_RLCV_IRAM_DATA
#define RLC_RLCV_IRAM_DATA__DATA__SHIFT                                                                       0x0
#define RLC_RLCV_IRAM_DATA__DATA_MASK                                                                         0xFFFFFFFFL
//RLC_RLCP_IRAM_ADDR
#define RLC_RLCP_IRAM_ADDR__ADDR__SHIFT                                                                       0x0
#define RLC_RLCP_IRAM_ADDR__ADDR_MASK                                                                         0xFFFFFFFFL
//RLC_RLCP_IRAM_DATA
#define RLC_RLCP_IRAM_DATA__DATA__SHIFT                                                                       0x0
#define RLC_RLCP_IRAM_DATA__DATA_MASK                                                                         0xFFFFFFFFL
//RLC_SRM_DRAM_ADDR
#define RLC_SRM_DRAM_ADDR__ADDR__SHIFT                                                                        0x0
#define RLC_SRM_DRAM_ADDR__RESERVED__SHIFT                                                                    0xc
#define RLC_SRM_DRAM_ADDR__ADDR_MASK                                                                          0x00000FFFL
#define RLC_SRM_DRAM_ADDR__RESERVED_MASK                                                                      0xFFFFF000L
//RLC_SRM_DRAM_DATA
#define RLC_SRM_DRAM_DATA__DATA__SHIFT                                                                        0x0
#define RLC_SRM_DRAM_DATA__DATA_MASK                                                                          0xFFFFFFFFL
//RLC_SRM_ARAM_ADDR
#define RLC_SRM_ARAM_ADDR__ADDR__SHIFT                                                                        0x0
#define RLC_SRM_ARAM_ADDR__RESERVED__SHIFT                                                                    0xc
#define RLC_SRM_ARAM_ADDR__ADDR_MASK                                                                          0x00000FFFL
#define RLC_SRM_ARAM_ADDR__RESERVED_MASK                                                                      0xFFFFF000L
//RLC_SRM_ARAM_DATA
#define RLC_SRM_ARAM_DATA__DATA__SHIFT                                                                        0x0
#define RLC_SRM_ARAM_DATA__DATA_MASK                                                                          0xFFFFFFFFL
//RLC_GPM_SCRATCH_ADDR
#define RLC_GPM_SCRATCH_ADDR__ADDR__SHIFT                                                                     0x0
#define RLC_GPM_SCRATCH_ADDR__ADDR_MASK                                                                       0x0000FFFFL
//RLC_GPM_SCRATCH_DATA
#define RLC_GPM_SCRATCH_DATA__DATA__SHIFT                                                                     0x0
#define RLC_GPM_SCRATCH_DATA__DATA_MASK                                                                       0xFFFFFFFFL
//RLC_GTS_OFFSET_LSB
#define RLC_GTS_OFFSET_LSB__DATA__SHIFT                                                                       0x0
#define RLC_GTS_OFFSET_LSB__DATA_MASK                                                                         0xFFFFFFFFL
//RLC_GTS_OFFSET_MSB
#define RLC_GTS_OFFSET_MSB__DATA__SHIFT                                                                       0x0
#define RLC_GTS_OFFSET_MSB__DATA_MASK                                                                         0xFFFFFFFFL
//RLC_GPU_IOV_SDMA0_STATUS
#define RLC_GPU_IOV_SDMA0_STATUS__STATUS__SHIFT                                                               0x0
#define RLC_GPU_IOV_SDMA0_STATUS__STATUS_MASK                                                                 0xFFFFFFFFL
//RLC_GPU_IOV_SDMA1_STATUS
#define RLC_GPU_IOV_SDMA1_STATUS__STATUS__SHIFT                                                               0x0
#define RLC_GPU_IOV_SDMA1_STATUS__STATUS_MASK                                                                 0xFFFFFFFFL
//RLC_GPU_IOV_SDMA2_STATUS
#define RLC_GPU_IOV_SDMA2_STATUS__STATUS__SHIFT                                                               0x0
#define RLC_GPU_IOV_SDMA2_STATUS__STATUS_MASK                                                                 0xFFFFFFFFL
//RLC_GPU_IOV_SDMA3_STATUS
#define RLC_GPU_IOV_SDMA3_STATUS__STATUS__SHIFT                                                               0x0
#define RLC_GPU_IOV_SDMA3_STATUS__STATUS_MASK                                                                 0xFFFFFFFFL
//RLC_GPU_IOV_SDMA4_STATUS
#define RLC_GPU_IOV_SDMA4_STATUS__STATUS__SHIFT                                                               0x0
#define RLC_GPU_IOV_SDMA4_STATUS__STATUS_MASK                                                                 0xFFFFFFFFL
//RLC_GPU_IOV_SDMA5_STATUS
#define RLC_GPU_IOV_SDMA5_STATUS__STATUS__SHIFT                                                               0x0
#define RLC_GPU_IOV_SDMA5_STATUS__STATUS_MASK                                                                 0xFFFFFFFFL
//RLC_GPU_IOV_SDMA6_STATUS
#define RLC_GPU_IOV_SDMA6_STATUS__STATUS__SHIFT                                                               0x0
#define RLC_GPU_IOV_SDMA6_STATUS__STATUS_MASK                                                                 0xFFFFFFFFL
//RLC_GPU_IOV_SDMA7_STATUS
#define RLC_GPU_IOV_SDMA7_STATUS__STATUS__SHIFT                                                               0x0
#define RLC_GPU_IOV_SDMA7_STATUS__STATUS_MASK                                                                 0xFFFFFFFFL
//RLC_GPU_IOV_SDMA0_BUSY_STATUS
#define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS__SHIFT                                                  0x0
#define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS_MASK                                                    0xFFFFFFFFL
//RLC_GPU_IOV_SDMA1_BUSY_STATUS
#define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS__SHIFT                                                  0x0
#define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS_MASK                                                    0xFFFFFFFFL
//RLC_GPU_IOV_SDMA2_BUSY_STATUS
#define RLC_GPU_IOV_SDMA2_BUSY_STATUS__VM_BUSY_STATUS__SHIFT                                                  0x0
#define RLC_GPU_IOV_SDMA2_BUSY_STATUS__VM_BUSY_STATUS_MASK                                                    0xFFFFFFFFL
//RLC_GPU_IOV_SDMA3_BUSY_STATUS
#define RLC_GPU_IOV_SDMA3_BUSY_STATUS__VM_BUSY_STATUS__SHIFT                                                  0x0
#define RLC_GPU_IOV_SDMA3_BUSY_STATUS__VM_BUSY_STATUS_MASK                                                    0xFFFFFFFFL
//RLC_GPU_IOV_SDMA4_BUSY_STATUS
#define RLC_GPU_IOV_SDMA4_BUSY_STATUS__VM_BUSY_STATUS__SHIFT                                                  0x0
#define RLC_GPU_IOV_SDMA4_BUSY_STATUS__VM_BUSY_STATUS_MASK                                                    0xFFFFFFFFL
//RLC_GPU_IOV_SDMA5_BUSY_STATUS
#define RLC_GPU_IOV_SDMA5_BUSY_STATUS__VM_BUSY_STATUS__SHIFT                                                  0x0
#define RLC_GPU_IOV_SDMA5_BUSY_STATUS__VM_BUSY_STATUS_MASK                                                    0xFFFFFFFFL
//RLC_GPU_IOV_SDMA6_BUSY_STATUS
#define RLC_GPU_IOV_SDMA6_BUSY_STATUS__VM_BUSY_STATUS__SHIFT                                                  0x0
#define RLC_GPU_IOV_SDMA6_BUSY_STATUS__VM_BUSY_STATUS_MASK                                                    0xFFFFFFFFL
//RLC_GPU_IOV_SDMA7_BUSY_STATUS
#define RLC_GPU_IOV_SDMA7_BUSY_STATUS__VM_BUSY_STATUS__SHIFT                                                  0x0
#define RLC_GPU_IOV_SDMA7_BUSY_STATUS__VM_BUSY_STATUS_MASK                                                    0xFFFFFFFFL


// addressBlock: gc_sdma0_sdma0hypdec
//SDMA0_UCODE_ADDR
#define SDMA0_UCODE_ADDR__VALUE__SHIFT                                                                        0x0
#define SDMA0_UCODE_ADDR__VALUE_MASK                                                                          0x00003FFFL
//SDMA0_UCODE_DATA
#define SDMA0_UCODE_DATA__VALUE__SHIFT                                                                        0x0
#define SDMA0_UCODE_DATA__VALUE_MASK                                                                          0xFFFFFFFFL
//SDMA0_VM_CTX_LO
#define SDMA0_VM_CTX_LO__ADDR__SHIFT                                                                          0x2
#define SDMA0_VM_CTX_LO__ADDR_MASK                                                                            0xFFFFFFFCL
//SDMA0_VM_CTX_HI
#define SDMA0_VM_CTX_HI__ADDR__SHIFT                                                                          0x0
#define SDMA0_VM_CTX_HI__ADDR_MASK                                                                            0xFFFFFFFFL
//SDMA0_ACTIVE_FCN_ID
#define SDMA0_ACTIVE_FCN_ID__VFID__SHIFT                                                                      0x0
#define SDMA0_ACTIVE_FCN_ID__RESERVED__SHIFT                                                                  0x5
#define SDMA0_ACTIVE_FCN_ID__VF__SHIFT                                                                        0x1f
#define SDMA0_ACTIVE_FCN_ID__VFID_MASK                                                                        0x0000001FL
#define SDMA0_ACTIVE_FCN_ID__RESERVED_MASK                                                                    0x7FFFFFE0L
#define SDMA0_ACTIVE_FCN_ID__VF_MASK                                                                          0x80000000L
//SDMA0_VM_CTX_CNTL
#define SDMA0_VM_CTX_CNTL__PRIV__SHIFT                                                                        0x0
#define SDMA0_VM_CTX_CNTL__VMID__SHIFT                                                                        0x4
#define SDMA0_VM_CTX_CNTL__PRIV_MASK                                                                          0x00000001L
#define SDMA0_VM_CTX_CNTL__VMID_MASK                                                                          0x000000F0L
//SDMA0_VIRT_RESET_REQ
#define SDMA0_VIRT_RESET_REQ__VF__SHIFT                                                                       0x0
#define SDMA0_VIRT_RESET_REQ__PF__SHIFT                                                                       0x1f
#define SDMA0_VIRT_RESET_REQ__VF_MASK                                                                         0x7FFFFFFFL
#define SDMA0_VIRT_RESET_REQ__PF_MASK                                                                         0x80000000L
//SDMA0_VF_ENABLE
#define SDMA0_VF_ENABLE__VF_ENABLE__SHIFT                                                                     0x0
#define SDMA0_VF_ENABLE__VF_ENABLE_MASK                                                                       0x00000001L
//SDMA0_CONTEXT_REG_TYPE0
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL__SHIFT                                                     0x0
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE__SHIFT                                                     0x1
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI__SHIFT                                                  0x2
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR__SHIFT                                                     0x3
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI__SHIFT                                                  0x4
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR__SHIFT                                                     0x5
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI__SHIFT                                                  0x6
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL__SHIFT                                           0x7
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI__SHIFT                                             0x8
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO__SHIFT                                             0x9
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL__SHIFT                                                     0xa
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR__SHIFT                                                     0xb
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET__SHIFT                                                   0xc
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO__SHIFT                                                  0xd
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI__SHIFT                                                  0xe
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE__SHIFT                                                     0xf
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL__SHIFT                                                   0x10
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS__SHIFT                                              0x11
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL__SHIFT                                                    0x12
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL__SHIFT                                                0x13
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL_MASK                                                       0x00000001L
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_MASK                                                       0x00000002L
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI_MASK                                                    0x00000004L
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_MASK                                                       0x00000008L
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI_MASK                                                    0x00000010L
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_MASK                                                       0x00000020L
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI_MASK                                                    0x00000040L
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL_MASK                                             0x00000080L
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI_MASK                                               0x00000100L
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO_MASK                                               0x00000200L
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL_MASK                                                       0x00000400L
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR_MASK                                                       0x00000800L
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET_MASK                                                     0x00001000L
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO_MASK                                                    0x00002000L
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI_MASK                                                    0x00004000L
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE_MASK                                                       0x00008000L
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL_MASK                                                     0x00010000L
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS_MASK                                                0x00020000L
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL_MASK                                                      0x00040000L
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL_MASK                                                  0x00080000L
//SDMA0_CONTEXT_REG_TYPE1
#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS__SHIFT                                                      0x8
#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG__SHIFT                                                0x9
#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK__SHIFT                                                   0xa
#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET__SHIFT                                             0xb
#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO__SHIFT                                                 0xc
#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI__SHIFT                                                 0xd
#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT                                                             0xe
#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN__SHIFT                                               0xf
#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT__SHIFT                                                     0x10
#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG__SHIFT                                                   0x11
#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT                                        0x12
#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT                                        0x13
#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL__SHIFT                                                 0x14
#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE__SHIFT                                            0x15
#define SDMA0_CONTEXT_REG_TYPE1__RESERVED__SHIFT                                                              0x18
#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS_MASK                                                        0x00000100L
#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG_MASK                                                  0x00000200L
#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK_MASK                                                     0x00000400L
#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET_MASK                                               0x00000800L
#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO_MASK                                                   0x00001000L
#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI_MASK                                                   0x00002000L
#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2_MASK                                                               0x00004000L
#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN_MASK                                                 0x00008000L
#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT_MASK                                                       0x00010000L
#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG_MASK                                                     0x00020000L
#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI_MASK                                          0x00040000L
#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO_MASK                                          0x00080000L
#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL_MASK                                                   0x00100000L
#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE_MASK                                              0x00200000L
#define SDMA0_CONTEXT_REG_TYPE1__RESERVED_MASK                                                                0xFF000000L
//SDMA0_CONTEXT_REG_TYPE2
#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0__SHIFT                                                0x0
#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1__SHIFT                                                0x1
#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2__SHIFT                                                0x2
#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3__SHIFT                                                0x3
#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4__SHIFT                                                0x4
#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5__SHIFT                                                0x5
#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6__SHIFT                                                0x6
#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7__SHIFT                                                0x7
#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8__SHIFT                                                0x8
#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA9__SHIFT                                                0x9
#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA10__SHIFT                                               0xa
#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL__SHIFT                                                 0xb
#define SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT                                                              0xc
#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0_MASK                                                  0x00000001L
#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1_MASK                                                  0x00000002L
#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2_MASK                                                  0x00000004L
#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3_MASK                                                  0x00000008L
#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4_MASK                                                  0x00000010L
#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5_MASK                                                  0x00000020L
#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6_MASK                                                  0x00000040L
#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7_MASK                                                  0x00000080L
#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8_MASK                                                  0x00000100L
#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA9_MASK                                                  0x00000200L
#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA10_MASK                                                 0x00000400L
#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL_MASK                                                   0x00000800L
#define SDMA0_CONTEXT_REG_TYPE2__RESERVED_MASK                                                                0xFFFFF000L
//SDMA0_CONTEXT_REG_TYPE3
#define SDMA0_CONTEXT_REG_TYPE3__RESERVED__SHIFT                                                              0x0
#define SDMA0_CONTEXT_REG_TYPE3__RESERVED_MASK                                                                0xFFFFFFFFL
//SDMA0_PUB_REG_TYPE0
#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR__SHIFT                                                          0x0
#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA__SHIFT                                                          0x1
#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO__SHIFT                                                           0x2
#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI__SHIFT                                                           0x3
#define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID__SHIFT                                                       0x4
#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL__SHIFT                                                         0x5
#define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ__SHIFT                                                      0x6
#define SDMA0_PUB_REG_TYPE0__SDMA0_VF_ENABLE__SHIFT                                                           0x7
#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0__SHIFT                                                   0x8
#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1__SHIFT                                                   0x9
#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2__SHIFT                                                   0xa
#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3__SHIFT                                                   0xb
#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0__SHIFT                                                       0xc
#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1__SHIFT                                                       0xd
#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2__SHIFT                                                       0xe
#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3__SHIFT                                                       0xf
#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL__SHIFT                                                             0x13
#define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT                                           0x14
#define SDMA0_PUB_REG_TYPE0__SDMA0_PG_CNTL__SHIFT                                                             0x16
#define SDMA0_PUB_REG_TYPE0__SDMA0_PG_CTX_LO__SHIFT                                                           0x17
#define SDMA0_PUB_REG_TYPE0__SDMA0_PG_CTX_HI__SHIFT                                                           0x18
#define SDMA0_PUB_REG_TYPE0__SDMA0_PG_CTX_CNTL__SHIFT                                                         0x19
#define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL__SHIFT                                                          0x1a
#define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL__SHIFT                                                            0x1b
#define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL__SHIFT                                                                0x1c
#define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS__SHIFT                                                        0x1d
#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG__SHIFT                                                      0x1e
#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ__SHIFT                                                 0x1f
#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR_MASK                                                            0x00000001L
#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA_MASK                                                            0x00000002L
#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO_MASK                                                             0x00000004L
#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI_MASK                                                             0x00000008L
#define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID_MASK                                                         0x00000010L
#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL_MASK                                                           0x00000020L
#define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ_MASK                                                        0x00000040L
#define SDMA0_PUB_REG_TYPE0__SDMA0_VF_ENABLE_MASK                                                             0x00000080L
#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0_MASK                                                     0x00000100L
#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1_MASK                                                     0x00000200L
#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2_MASK                                                     0x00000400L
#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3_MASK                                                     0x00000800L
#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0_MASK                                                         0x00001000L
#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1_MASK                                                         0x00002000L
#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2_MASK                                                         0x00004000L
#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3_MASK                                                         0x00008000L
#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL_MASK                                                               0x00080000L
#define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK                                             0x00300000L
#define SDMA0_PUB_REG_TYPE0__SDMA0_PG_CNTL_MASK                                                               0x00400000L
#define SDMA0_PUB_REG_TYPE0__SDMA0_PG_CTX_LO_MASK                                                             0x00800000L
#define SDMA0_PUB_REG_TYPE0__SDMA0_PG_CTX_HI_MASK                                                             0x01000000L
#define SDMA0_PUB_REG_TYPE0__SDMA0_PG_CTX_CNTL_MASK                                                           0x02000000L
#define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL_MASK                                                            0x04000000L
#define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL_MASK                                                              0x08000000L
#define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL_MASK                                                                  0x10000000L
#define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS_MASK                                                          0x20000000L
#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_MASK                                                        0x40000000L
#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ_MASK                                                   0x80000000L
//SDMA0_PUB_REG_TYPE1
#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI__SHIFT                                                    0x0
#define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT                                            0x1
#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH__SHIFT                                                       0x2
#define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH__SHIFT                                                     0x3
#define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM__SHIFT                                                             0x4
#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG__SHIFT                                                          0x5
#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG__SHIFT                                                         0x6
#define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL__SHIFT                                                       0x7
#define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG__SHIFT                                                     0x8
#define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM__SHIFT                                                      0x9
#define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL__SHIFT                                                            0xa
#define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE__SHIFT                                                              0xb
#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM__SHIFT                                                      0xc
#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM__SHIFT                                                      0xd
#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG__SHIFT                                                          0x12
#define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD__SHIFT                                                        0x13
#define SDMA0_PUB_REG_TYPE1__SDMA0_ID__SHIFT                                                                  0x14
#define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION__SHIFT                                                             0x15
#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER__SHIFT                                                         0x16
#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR__SHIFT                                                   0x17
#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG__SHIFT                                                         0x18
#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL__SHIFT                                                         0x19
#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO__SHIFT                                                     0x1a
#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI__SHIFT                                                     0x1b
#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL__SHIFT                                                          0x1c
#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK__SHIFT                                                       0x1d
#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS__SHIFT                                                     0x1e
#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS__SHIFT                                                     0x1f
#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI_MASK                                                      0x00000001L
#define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL_MASK                                              0x00000002L
#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_MASK                                                         0x00000004L
#define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH_MASK                                                       0x00000008L
#define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM_MASK                                                               0x00000010L
#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG_MASK                                                            0x00000020L
#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG_MASK                                                           0x00000040L
#define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL_MASK                                                         0x00000080L
#define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG_MASK                                                       0x00000100L
#define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM_MASK                                                        0x00000200L
#define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL_MASK                                                              0x00000400L
#define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE_MASK                                                                0x00000800L
#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM_MASK                                                        0x00001000L
#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM_MASK                                                        0x00002000L
#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG_MASK                                                            0x00040000L
#define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD_MASK                                                          0x00080000L
#define SDMA0_PUB_REG_TYPE1__SDMA0_ID_MASK                                                                    0x00100000L
#define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION_MASK                                                               0x00200000L
#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_MASK                                                           0x00400000L
#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR_MASK                                                     0x00800000L
#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG_MASK                                                           0x01000000L
#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL_MASK                                                           0x02000000L
#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO_MASK                                                       0x04000000L
#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI_MASK                                                       0x08000000L
#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL_MASK                                                            0x10000000L
#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK_MASK                                                         0x20000000L
#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS_MASK                                                       0x40000000L
#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS_MASK                                                       0x80000000L
//SDMA0_PUB_REG_TYPE2
#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0__SHIFT                                                          0x0
#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1__SHIFT                                                          0x1
#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2__SHIFT                                                          0x2
#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0__SHIFT                                                     0x3
#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1__SHIFT                                                     0x4
#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0__SHIFT                                                     0x5
#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1__SHIFT                                                     0x6
#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT__SHIFT                                                       0x7
#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE__SHIFT                                                          0x8
#define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT__SHIFT                                                  0xa
#define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2__SHIFT                                                      0xb
#define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG__SHIFT                                                         0xc
#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO__SHIFT                                                    0xd
#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI__SHIFT                                                    0xe
#define SDMA0_PUB_REG_TYPE2__SDMA0_PHASE2_QUANTUM__SHIFT                                                      0xf
#define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG__SHIFT                                                           0x10
#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0__SHIFT                                                      0x11
#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1__SHIFT                                                      0x12
#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2__SHIFT                                                      0x13
#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3__SHIFT                                                      0x14
#define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER__SHIFT                                                         0x15
#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCNT_PERFCOUNTER0_CFG__SHIFT                                            0x17
#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCNT_PERFCOUNTER1_CFG__SHIFT                                            0x18
#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__SHIFT                                       0x19
#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCNT_MISC_CNTL__SHIFT                                                   0x1a
#define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL__SHIFT                                                            0x1b
#define SDMA0_PUB_REG_TYPE2__SDMA0_AQL_STATUS__SHIFT                                                          0x1f
#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0_MASK                                                            0x00000001L
#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1_MASK                                                            0x00000002L
#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2_MASK                                                            0x00000004L
#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0_MASK                                                       0x00000008L
#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1_MASK                                                       0x00000010L
#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0_MASK                                                       0x00000020L
#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1_MASK                                                       0x00000040L
#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT_MASK                                                         0x00000080L
#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE_MASK                                                            0x00000100L
#define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT_MASK                                                    0x00000400L
#define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2_MASK                                                        0x00000800L
#define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG_MASK                                                           0x00001000L
#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO_MASK                                                      0x00002000L
#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI_MASK                                                      0x00004000L
#define SDMA0_PUB_REG_TYPE2__SDMA0_PHASE2_QUANTUM_MASK                                                        0x00008000L
#define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG_MASK                                                             0x00010000L
#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0_MASK                                                        0x00020000L
#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1_MASK                                                        0x00040000L
#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2_MASK                                                        0x00080000L
#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3_MASK                                                        0x00100000L
#define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER_MASK                                                           0x00200000L
#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCNT_PERFCOUNTER0_CFG_MASK                                              0x00800000L
#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCNT_PERFCOUNTER1_CFG_MASK                                              0x01000000L
#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL_MASK                                         0x02000000L
#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCNT_MISC_CNTL_MASK                                                     0x04000000L
#define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL_MASK                                                              0x08000000L
#define SDMA0_PUB_REG_TYPE2__SDMA0_AQL_STATUS_MASK                                                            0x80000000L
//SDMA0_PUB_REG_TYPE3
#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA__SHIFT                                                   0x0
#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX__SHIFT                                                  0x1
#define SDMA0_PUB_REG_TYPE3__SDMA0_TLBI_GCR_CNTL__SHIFT                                                       0x2
#define SDMA0_PUB_REG_TYPE3__SDMA0_TILING_CONFIG__SHIFT                                                       0x3
#define SDMA0_PUB_REG_TYPE3__SDMA0_PERFCOUNTER0_SELECT__SHIFT                                                 0x8
#define SDMA0_PUB_REG_TYPE3__SDMA0_PERFCOUNTER0_SELECT1__SHIFT                                                0x9
#define SDMA0_PUB_REG_TYPE3__SDMA0_PERFCOUNTER0_LO__SHIFT                                                     0xa
#define SDMA0_PUB_REG_TYPE3__SDMA0_PERFCOUNTER0_HI__SHIFT                                                     0xb
#define SDMA0_PUB_REG_TYPE3__SDMA0_PERFCOUNTER1_SELECT__SHIFT                                                 0xc
#define SDMA0_PUB_REG_TYPE3__SDMA0_PERFCOUNTER1_SELECT1__SHIFT                                                0xd
#define SDMA0_PUB_REG_TYPE3__SDMA0_PERFCOUNTER1_LO__SHIFT                                                     0xe
#define SDMA0_PUB_REG_TYPE3__SDMA0_PERFCOUNTER1_HI__SHIFT                                                     0xf
#define SDMA0_PUB_REG_TYPE3__SDMA0_INT_STATUS__SHIFT                                                          0x10
#define SDMA0_PUB_REG_TYPE3__SDMA0_HOLE_ADDR_LO__SHIFT                                                        0x12
#define SDMA0_PUB_REG_TYPE3__SDMA0_HOLE_ADDR_HI__SHIFT                                                        0x13
#define SDMA0_PUB_REG_TYPE3__SDMA0_CLOCK_GATING_REG__SHIFT                                                    0x15
#define SDMA0_PUB_REG_TYPE3__SDMA0_STATUS4_REG__SHIFT                                                         0x16
#define SDMA0_PUB_REG_TYPE3__SDMA0_SCRATCH_RAM_DATA__SHIFT                                                    0x17
#define SDMA0_PUB_REG_TYPE3__SDMA0_SCRATCH_RAM_ADDR__SHIFT                                                    0x18
#define SDMA0_PUB_REG_TYPE3__SDMA0_TIMESTAMP_CNTL__SHIFT                                                      0x19
#define SDMA0_PUB_REG_TYPE3__SDMA0_PERFCNT_PERFCOUNTER_LO__SHIFT                                              0x1a
#define SDMA0_PUB_REG_TYPE3__SDMA0_PERFCNT_PERFCOUNTER_HI__SHIFT                                              0x1b
#define SDMA0_PUB_REG_TYPE3__SDMA0_STATUS5_REG__SHIFT                                                         0x1c
#define SDMA0_PUB_REG_TYPE3__SDMA0_QUEUE_RESET_REQ__SHIFT                                                     0x1d
#define SDMA0_PUB_REG_TYPE3__RESERVED__SHIFT                                                                  0x1e
#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA_MASK                                                     0x00000001L
#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX_MASK                                                    0x00000002L
#define SDMA0_PUB_REG_TYPE3__SDMA0_TLBI_GCR_CNTL_MASK                                                         0x00000004L
#define SDMA0_PUB_REG_TYPE3__SDMA0_TILING_CONFIG_MASK                                                         0x00000008L
#define SDMA0_PUB_REG_TYPE3__SDMA0_PERFCOUNTER0_SELECT_MASK                                                   0x00000100L
#define SDMA0_PUB_REG_TYPE3__SDMA0_PERFCOUNTER0_SELECT1_MASK                                                  0x00000200L
#define SDMA0_PUB_REG_TYPE3__SDMA0_PERFCOUNTER0_LO_MASK                                                       0x00000400L
#define SDMA0_PUB_REG_TYPE3__SDMA0_PERFCOUNTER0_HI_MASK                                                       0x00000800L
#define SDMA0_PUB_REG_TYPE3__SDMA0_PERFCOUNTER1_SELECT_MASK                                                   0x00001000L
#define SDMA0_PUB_REG_TYPE3__SDMA0_PERFCOUNTER1_SELECT1_MASK                                                  0x00002000L
#define SDMA0_PUB_REG_TYPE3__SDMA0_PERFCOUNTER1_LO_MASK                                                       0x00004000L
#define SDMA0_PUB_REG_TYPE3__SDMA0_PERFCOUNTER1_HI_MASK                                                       0x00008000L
#define SDMA0_PUB_REG_TYPE3__SDMA0_INT_STATUS_MASK                                                            0x00010000L
#define SDMA0_PUB_REG_TYPE3__SDMA0_HOLE_ADDR_LO_MASK                                                          0x00040000L
#define SDMA0_PUB_REG_TYPE3__SDMA0_HOLE_ADDR_HI_MASK                                                          0x00080000L
#define SDMA0_PUB_REG_TYPE3__SDMA0_CLOCK_GATING_REG_MASK                                                      0x00200000L
#define SDMA0_PUB_REG_TYPE3__SDMA0_STATUS4_REG_MASK                                                           0x00400000L
#define SDMA0_PUB_REG_TYPE3__SDMA0_SCRATCH_RAM_DATA_MASK                                                      0x00800000L
#define SDMA0_PUB_REG_TYPE3__SDMA0_SCRATCH_RAM_ADDR_MASK                                                      0x01000000L
#define SDMA0_PUB_REG_TYPE3__SDMA0_TIMESTAMP_CNTL_MASK                                                        0x02000000L
#define SDMA0_PUB_REG_TYPE3__SDMA0_PERFCNT_PERFCOUNTER_LO_MASK                                                0x04000000L
#define SDMA0_PUB_REG_TYPE3__SDMA0_PERFCNT_PERFCOUNTER_HI_MASK                                                0x08000000L
#define SDMA0_PUB_REG_TYPE3__SDMA0_STATUS5_REG_MASK                                                           0x10000000L
#define SDMA0_PUB_REG_TYPE3__SDMA0_QUEUE_RESET_REQ_MASK                                                       0x20000000L
#define SDMA0_PUB_REG_TYPE3__RESERVED_MASK                                                                    0xC0000000L
//SDMA0_VM_CNTL
#define SDMA0_VM_CNTL__CMD__SHIFT                                                                             0x0
#define SDMA0_VM_CNTL__CMD_MASK                                                                               0x0000000FL
//SDMA0_BROADCAST_UCODE_ADDR
#define SDMA0_BROADCAST_UCODE_ADDR__VALUE__SHIFT                                                              0x0
#define SDMA0_BROADCAST_UCODE_ADDR__VALUE_MASK                                                                0x00003FFFL
//SDMA0_BROADCAST_UCODE_DATA
#define SDMA0_BROADCAST_UCODE_DATA__VALUE__SHIFT                                                              0x0
#define SDMA0_BROADCAST_UCODE_DATA__VALUE_MASK                                                                0xFFFFFFFFL


// addressBlock: gc_sdma1_sdma1hypdec
//SDMA1_UCODE_ADDR
#define SDMA1_UCODE_ADDR__VALUE__SHIFT                                                                        0x0
#define SDMA1_UCODE_ADDR__VALUE_MASK                                                                          0x00003FFFL
//SDMA1_UCODE_DATA
#define SDMA1_UCODE_DATA__VALUE__SHIFT                                                                        0x0
#define SDMA1_UCODE_DATA__VALUE_MASK                                                                          0xFFFFFFFFL
//SDMA1_VM_CTX_LO
#define SDMA1_VM_CTX_LO__ADDR__SHIFT                                                                          0x2
#define SDMA1_VM_CTX_LO__ADDR_MASK                                                                            0xFFFFFFFCL
//SDMA1_VM_CTX_HI
#define SDMA1_VM_CTX_HI__ADDR__SHIFT                                                                          0x0
#define SDMA1_VM_CTX_HI__ADDR_MASK                                                                            0xFFFFFFFFL
//SDMA1_ACTIVE_FCN_ID
#define SDMA1_ACTIVE_FCN_ID__VFID__SHIFT                                                                      0x0
#define SDMA1_ACTIVE_FCN_ID__RESERVED__SHIFT                                                                  0x5
#define SDMA1_ACTIVE_FCN_ID__VF__SHIFT                                                                        0x1f
#define SDMA1_ACTIVE_FCN_ID__VFID_MASK                                                                        0x0000001FL
#define SDMA1_ACTIVE_FCN_ID__RESERVED_MASK                                                                    0x7FFFFFE0L
#define SDMA1_ACTIVE_FCN_ID__VF_MASK                                                                          0x80000000L
//SDMA1_VM_CTX_CNTL
#define SDMA1_VM_CTX_CNTL__PRIV__SHIFT                                                                        0x0
#define SDMA1_VM_CTX_CNTL__VMID__SHIFT                                                                        0x4
#define SDMA1_VM_CTX_CNTL__PRIV_MASK                                                                          0x00000001L
#define SDMA1_VM_CTX_CNTL__VMID_MASK                                                                          0x000000F0L
//SDMA1_VIRT_RESET_REQ
#define SDMA1_VIRT_RESET_REQ__VF__SHIFT                                                                       0x0
#define SDMA1_VIRT_RESET_REQ__PF__SHIFT                                                                       0x1f
#define SDMA1_VIRT_RESET_REQ__VF_MASK                                                                         0x7FFFFFFFL
#define SDMA1_VIRT_RESET_REQ__PF_MASK                                                                         0x80000000L
//SDMA1_VF_ENABLE
#define SDMA1_VF_ENABLE__VF_ENABLE__SHIFT                                                                     0x0
#define SDMA1_VF_ENABLE__VF_ENABLE_MASK                                                                       0x00000001L
//SDMA1_CONTEXT_REG_TYPE0
#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL__SHIFT                                                     0x0
#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE__SHIFT                                                     0x1
#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI__SHIFT                                                  0x2
#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR__SHIFT                                                     0x3
#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_HI__SHIFT                                                  0x4
#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR__SHIFT                                                     0x5
#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_HI__SHIFT                                                  0x6
#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL__SHIFT                                           0x7
#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI__SHIFT                                             0x8
#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO__SHIFT                                             0x9
#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL__SHIFT                                                     0xa
#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR__SHIFT                                                     0xb
#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET__SHIFT                                                   0xc
#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO__SHIFT                                                  0xd
#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI__SHIFT                                                  0xe
#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE__SHIFT                                                     0xf
#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL__SHIFT                                                   0x10
#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS__SHIFT                                              0x11
#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL__SHIFT                                                    0x12
#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL__SHIFT                                                0x13
#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL_MASK                                                       0x00000001L
#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_MASK                                                       0x00000002L
#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI_MASK                                                    0x00000004L
#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_MASK                                                       0x00000008L
#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_HI_MASK                                                    0x00000010L
#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_MASK                                                       0x00000020L
#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_HI_MASK                                                    0x00000040L
#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL_MASK                                             0x00000080L
#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI_MASK                                               0x00000100L
#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO_MASK                                               0x00000200L
#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL_MASK                                                       0x00000400L
#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR_MASK                                                       0x00000800L
#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET_MASK                                                     0x00001000L
#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO_MASK                                                    0x00002000L
#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI_MASK                                                    0x00004000L
#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE_MASK                                                       0x00008000L
#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL_MASK                                                     0x00010000L
#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS_MASK                                                0x00020000L
#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL_MASK                                                      0x00040000L
#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL_MASK                                                  0x00080000L
//SDMA1_CONTEXT_REG_TYPE1
#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_STATUS__SHIFT                                                      0x8
#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG__SHIFT                                                0x9
#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK__SHIFT                                                   0xa
#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_OFFSET__SHIFT                                             0xb
#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO__SHIFT                                                 0xc
#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI__SHIFT                                                 0xd
#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT                                                             0xe
#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN__SHIFT                                               0xf
#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT__SHIFT                                                     0x10
#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG__SHIFT                                                   0x11
#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT                                        0x12
#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT                                        0x13
#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_AQL_CNTL__SHIFT                                                 0x14
#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_MINOR_PTR_UPDATE__SHIFT                                            0x15
#define SDMA1_CONTEXT_REG_TYPE1__RESERVED__SHIFT                                                              0x18
#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_STATUS_MASK                                                        0x00000100L
#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG_MASK                                                  0x00000200L
#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK_MASK                                                     0x00000400L
#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_OFFSET_MASK                                               0x00000800L
#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO_MASK                                                   0x00001000L
#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI_MASK                                                   0x00002000L
#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2_MASK                                                               0x00004000L
#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN_MASK                                                 0x00008000L
#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT_MASK                                                       0x00010000L
#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG_MASK                                                     0x00020000L
#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI_MASK                                          0x00040000L
#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO_MASK                                          0x00080000L
#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_AQL_CNTL_MASK                                                   0x00100000L
#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_MINOR_PTR_UPDATE_MASK                                              0x00200000L
#define SDMA1_CONTEXT_REG_TYPE1__RESERVED_MASK                                                                0xFF000000L
//SDMA1_CONTEXT_REG_TYPE2
#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0__SHIFT                                                0x0
#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1__SHIFT                                                0x1
#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2__SHIFT                                                0x2
#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3__SHIFT                                                0x3
#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4__SHIFT                                                0x4
#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5__SHIFT                                                0x5
#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA6__SHIFT                                                0x6
#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA7__SHIFT                                                0x7
#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA8__SHIFT                                                0x8
#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA9__SHIFT                                                0x9
#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA10__SHIFT                                               0xa
#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL__SHIFT                                                 0xb
#define SDMA1_CONTEXT_REG_TYPE2__RESERVED__SHIFT                                                              0xc
#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0_MASK                                                  0x00000001L
#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1_MASK                                                  0x00000002L
#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2_MASK                                                  0x00000004L
#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3_MASK                                                  0x00000008L
#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4_MASK                                                  0x00000010L
#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5_MASK                                                  0x00000020L
#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA6_MASK                                                  0x00000040L
#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA7_MASK                                                  0x00000080L
#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA8_MASK                                                  0x00000100L
#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA9_MASK                                                  0x00000200L
#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA10_MASK                                                 0x00000400L
#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL_MASK                                                   0x00000800L
#define SDMA1_CONTEXT_REG_TYPE2__RESERVED_MASK                                                                0xFFFFF000L
//SDMA1_CONTEXT_REG_TYPE3
#define SDMA1_CONTEXT_REG_TYPE3__RESERVED__SHIFT                                                              0x0
#define SDMA1_CONTEXT_REG_TYPE3__RESERVED_MASK                                                                0xFFFFFFFFL
//SDMA1_PUB_REG_TYPE0
#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR__SHIFT                                                          0x0
#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA__SHIFT                                                          0x1
#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_LO__SHIFT                                                           0x2
#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_HI__SHIFT                                                           0x3
#define SDMA1_PUB_REG_TYPE0__SDMA1_ACTIVE_FCN_ID__SHIFT                                                       0x4
#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_CNTL__SHIFT                                                         0x5
#define SDMA1_PUB_REG_TYPE0__SDMA1_VIRT_RESET_REQ__SHIFT                                                      0x6
#define SDMA1_PUB_REG_TYPE0__SDMA1_VF_ENABLE__SHIFT                                                           0x7
#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE0__SHIFT                                                   0x8
#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE1__SHIFT                                                   0x9
#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE2__SHIFT                                                   0xa
#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE3__SHIFT                                                   0xb
#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE0__SHIFT                                                       0xc
#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE1__SHIFT                                                       0xd
#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE2__SHIFT                                                       0xe
#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE3__SHIFT                                                       0xf
#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CNTL__SHIFT                                                             0x13
#define SDMA1_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT                                           0x14
#define SDMA1_PUB_REG_TYPE0__SDMA1_PG_CNTL__SHIFT                                                             0x16
#define SDMA1_PUB_REG_TYPE0__SDMA1_PG_CTX_LO__SHIFT                                                           0x17
#define SDMA1_PUB_REG_TYPE0__SDMA1_PG_CTX_HI__SHIFT                                                           0x18
#define SDMA1_PUB_REG_TYPE0__SDMA1_PG_CTX_CNTL__SHIFT                                                         0x19
#define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL__SHIFT                                                          0x1a
#define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL__SHIFT                                                            0x1b
#define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL__SHIFT                                                                0x1c
#define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS__SHIFT                                                        0x1d
#define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG__SHIFT                                                      0x1e
#define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_READ__SHIFT                                                 0x1f
#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR_MASK                                                            0x00000001L
#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA_MASK                                                            0x00000002L
#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_LO_MASK                                                             0x00000004L
#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_HI_MASK                                                             0x00000008L
#define SDMA1_PUB_REG_TYPE0__SDMA1_ACTIVE_FCN_ID_MASK                                                         0x00000010L
#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_CNTL_MASK                                                           0x00000020L
#define SDMA1_PUB_REG_TYPE0__SDMA1_VIRT_RESET_REQ_MASK                                                        0x00000040L
#define SDMA1_PUB_REG_TYPE0__SDMA1_VF_ENABLE_MASK                                                             0x00000080L
#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE0_MASK                                                     0x00000100L
#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE1_MASK                                                     0x00000200L
#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE2_MASK                                                     0x00000400L
#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE3_MASK                                                     0x00000800L
#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE0_MASK                                                         0x00001000L
#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE1_MASK                                                         0x00002000L
#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE2_MASK                                                         0x00004000L
#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE3_MASK                                                         0x00008000L
#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CNTL_MASK                                                               0x00080000L
#define SDMA1_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK                                             0x00300000L
#define SDMA1_PUB_REG_TYPE0__SDMA1_PG_CNTL_MASK                                                               0x00400000L
#define SDMA1_PUB_REG_TYPE0__SDMA1_PG_CTX_LO_MASK                                                             0x00800000L
#define SDMA1_PUB_REG_TYPE0__SDMA1_PG_CTX_HI_MASK                                                             0x01000000L
#define SDMA1_PUB_REG_TYPE0__SDMA1_PG_CTX_CNTL_MASK                                                           0x02000000L
#define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL_MASK                                                            0x04000000L
#define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL_MASK                                                              0x08000000L
#define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL_MASK                                                                  0x10000000L
#define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS_MASK                                                          0x20000000L
#define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_MASK                                                        0x40000000L
#define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_READ_MASK                                                   0x80000000L
//SDMA1_PUB_REG_TYPE1
#define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_HI__SHIFT                                                    0x0
#define SDMA1_PUB_REG_TYPE1__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT                                            0x1
#define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH__SHIFT                                                       0x2
#define SDMA1_PUB_REG_TYPE1__SDMA1_IB_OFFSET_FETCH__SHIFT                                                     0x3
#define SDMA1_PUB_REG_TYPE1__SDMA1_PROGRAM__SHIFT                                                             0x4
#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS_REG__SHIFT                                                          0x5
#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS1_REG__SHIFT                                                         0x6
#define SDMA1_PUB_REG_TYPE1__SDMA1_RD_BURST_CNTL__SHIFT                                                       0x7
#define SDMA1_PUB_REG_TYPE1__SDMA1_HBM_PAGE_CONFIG__SHIFT                                                     0x8
#define SDMA1_PUB_REG_TYPE1__SDMA1_UCODE_CHECKSUM__SHIFT                                                      0x9
#define SDMA1_PUB_REG_TYPE1__SDMA1_F32_CNTL__SHIFT                                                            0xa
#define SDMA1_PUB_REG_TYPE1__SDMA1_FREEZE__SHIFT                                                              0xb
#define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE0_QUANTUM__SHIFT                                                      0xc
#define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE1_QUANTUM__SHIFT                                                      0xd
#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_CONFIG__SHIFT                                                          0x12
#define SDMA1_PUB_REG_TYPE1__SDMA1_BA_THRESHOLD__SHIFT                                                        0x13
#define SDMA1_PUB_REG_TYPE1__SDMA1_ID__SHIFT                                                                  0x14
#define SDMA1_PUB_REG_TYPE1__SDMA1_VERSION__SHIFT                                                             0x15
#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER__SHIFT                                                         0x16
#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_CLEAR__SHIFT                                                   0x17
#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG__SHIFT                                                         0x18
#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL__SHIFT                                                         0x19
#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO__SHIFT                                                     0x1a
#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI__SHIFT                                                     0x1b
#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_CNTL__SHIFT                                                          0x1c
#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WATERMK__SHIFT                                                       0x1d
#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_RD_STATUS__SHIFT                                                     0x1e
#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WR_STATUS__SHIFT                                                     0x1f
#define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_HI_MASK                                                      0x00000001L
#define SDMA1_PUB_REG_TYPE1__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL_MASK                                              0x00000002L
#define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_MASK                                                         0x00000004L
#define SDMA1_PUB_REG_TYPE1__SDMA1_IB_OFFSET_FETCH_MASK                                                       0x00000008L
#define SDMA1_PUB_REG_TYPE1__SDMA1_PROGRAM_MASK                                                               0x00000010L
#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS_REG_MASK                                                            0x00000020L
#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS1_REG_MASK                                                           0x00000040L
#define SDMA1_PUB_REG_TYPE1__SDMA1_RD_BURST_CNTL_MASK                                                         0x00000080L
#define SDMA1_PUB_REG_TYPE1__SDMA1_HBM_PAGE_CONFIG_MASK                                                       0x00000100L
#define SDMA1_PUB_REG_TYPE1__SDMA1_UCODE_CHECKSUM_MASK                                                        0x00000200L
#define SDMA1_PUB_REG_TYPE1__SDMA1_F32_CNTL_MASK                                                              0x00000400L
#define SDMA1_PUB_REG_TYPE1__SDMA1_FREEZE_MASK                                                                0x00000800L
#define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE0_QUANTUM_MASK                                                        0x00001000L
#define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE1_QUANTUM_MASK                                                        0x00002000L
#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_CONFIG_MASK                                                            0x00040000L
#define SDMA1_PUB_REG_TYPE1__SDMA1_BA_THRESHOLD_MASK                                                          0x00080000L
#define SDMA1_PUB_REG_TYPE1__SDMA1_ID_MASK                                                                    0x00100000L
#define SDMA1_PUB_REG_TYPE1__SDMA1_VERSION_MASK                                                               0x00200000L
#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_MASK                                                           0x00400000L
#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_CLEAR_MASK                                                     0x00800000L
#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG_MASK                                                           0x01000000L
#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL_MASK                                                           0x02000000L
#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO_MASK                                                       0x04000000L
#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI_MASK                                                       0x08000000L
#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_CNTL_MASK                                                            0x10000000L
#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WATERMK_MASK                                                         0x20000000L
#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_RD_STATUS_MASK                                                       0x40000000L
#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WR_STATUS_MASK                                                       0x80000000L
//SDMA1_PUB_REG_TYPE2
#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV0__SHIFT                                                          0x0
#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV1__SHIFT                                                          0x1
#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV2__SHIFT                                                          0x2
#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK0__SHIFT                                                     0x3
#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK1__SHIFT                                                     0x4
#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK0__SHIFT                                                     0x5
#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK1__SHIFT                                                     0x6
#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_TIMEOUT__SHIFT                                                       0x7
#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_PAGE__SHIFT                                                          0x8
#define SDMA1_PUB_REG_TYPE2__SDMA1_RELAX_ORDERING_LUT__SHIFT                                                  0xa
#define SDMA1_PUB_REG_TYPE2__SDMA1_CHICKEN_BITS_2__SHIFT                                                      0xb
#define SDMA1_PUB_REG_TYPE2__SDMA1_STATUS3_REG__SHIFT                                                         0xc
#define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_LO__SHIFT                                                    0xd
#define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_HI__SHIFT                                                    0xe
#define SDMA1_PUB_REG_TYPE2__SDMA1_PHASE2_QUANTUM__SHIFT                                                      0xf
#define SDMA1_PUB_REG_TYPE2__SDMA1_ERROR_LOG__SHIFT                                                           0x10
#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG0__SHIFT                                                      0x11
#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG1__SHIFT                                                      0x12
#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG2__SHIFT                                                      0x13
#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG3__SHIFT                                                      0x14
#define SDMA1_PUB_REG_TYPE2__SDMA1_F32_COUNTER__SHIFT                                                         0x15
#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCNT_PERFCOUNTER0_CFG__SHIFT                                            0x17
#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCNT_PERFCOUNTER1_CFG__SHIFT                                            0x18
#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__SHIFT                                       0x19
#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCNT_MISC_CNTL__SHIFT                                                   0x1a
#define SDMA1_PUB_REG_TYPE2__SDMA1_CRD_CNTL__SHIFT                                                            0x1b
#define SDMA1_PUB_REG_TYPE2__SDMA1_AQL_STATUS__SHIFT                                                          0x1f
#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV0_MASK                                                            0x00000001L
#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV1_MASK                                                            0x00000002L
#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV2_MASK                                                            0x00000004L
#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK0_MASK                                                       0x00000008L
#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK1_MASK                                                       0x00000010L
#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK0_MASK                                                       0x00000020L
#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK1_MASK                                                       0x00000040L
#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_TIMEOUT_MASK                                                         0x00000080L
#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_PAGE_MASK                                                            0x00000100L
#define SDMA1_PUB_REG_TYPE2__SDMA1_RELAX_ORDERING_LUT_MASK                                                    0x00000400L
#define SDMA1_PUB_REG_TYPE2__SDMA1_CHICKEN_BITS_2_MASK                                                        0x00000800L
#define SDMA1_PUB_REG_TYPE2__SDMA1_STATUS3_REG_MASK                                                           0x00001000L
#define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_LO_MASK                                                      0x00002000L
#define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_HI_MASK                                                      0x00004000L
#define SDMA1_PUB_REG_TYPE2__SDMA1_PHASE2_QUANTUM_MASK                                                        0x00008000L
#define SDMA1_PUB_REG_TYPE2__SDMA1_ERROR_LOG_MASK                                                             0x00010000L
#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG0_MASK                                                        0x00020000L
#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG1_MASK                                                        0x00040000L
#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG2_MASK                                                        0x00080000L
#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG3_MASK                                                        0x00100000L
#define SDMA1_PUB_REG_TYPE2__SDMA1_F32_COUNTER_MASK                                                           0x00200000L
#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCNT_PERFCOUNTER0_CFG_MASK                                              0x00800000L
#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCNT_PERFCOUNTER1_CFG_MASK                                              0x01000000L
#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL_MASK                                         0x02000000L
#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCNT_MISC_CNTL_MASK                                                     0x04000000L
#define SDMA1_PUB_REG_TYPE2__SDMA1_CRD_CNTL_MASK                                                              0x08000000L
#define SDMA1_PUB_REG_TYPE2__SDMA1_AQL_STATUS_MASK                                                            0x80000000L
//SDMA1_PUB_REG_TYPE3
#define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_DATA__SHIFT                                                   0x0
#define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_INDEX__SHIFT                                                  0x1
#define SDMA1_PUB_REG_TYPE3__SDMA1_TLBI_GCR_CNTL__SHIFT                                                       0x2
#define SDMA1_PUB_REG_TYPE3__SDMA1_TILING_CONFIG__SHIFT                                                       0x3
#define SDMA1_PUB_REG_TYPE3__SDMA1_PERFCOUNTER0_SELECT__SHIFT                                                 0x8
#define SDMA1_PUB_REG_TYPE3__SDMA1_PERFCOUNTER0_SELECT1__SHIFT                                                0x9
#define SDMA1_PUB_REG_TYPE3__SDMA1_PERFCOUNTER0_LO__SHIFT                                                     0xa
#define SDMA1_PUB_REG_TYPE3__SDMA1_PERFCOUNTER0_HI__SHIFT                                                     0xb
#define SDMA1_PUB_REG_TYPE3__SDMA1_PERFCOUNTER1_SELECT__SHIFT                                                 0xc
#define SDMA1_PUB_REG_TYPE3__SDMA1_PERFCOUNTER1_SELECT1__SHIFT                                                0xd
#define SDMA1_PUB_REG_TYPE3__SDMA1_PERFCOUNTER1_LO__SHIFT                                                     0xe
#define SDMA1_PUB_REG_TYPE3__SDMA1_PERFCOUNTER1_HI__SHIFT                                                     0xf
#define SDMA1_PUB_REG_TYPE3__SDMA1_INT_STATUS__SHIFT                                                          0x10
#define SDMA1_PUB_REG_TYPE3__SDMA1_HOLE_ADDR_LO__SHIFT                                                        0x12
#define SDMA1_PUB_REG_TYPE3__SDMA1_HOLE_ADDR_HI__SHIFT                                                        0x13
#define SDMA1_PUB_REG_TYPE3__SDMA1_CLOCK_GATING_REG__SHIFT                                                    0x15
#define SDMA1_PUB_REG_TYPE3__SDMA1_STATUS4_REG__SHIFT                                                         0x16
#define SDMA1_PUB_REG_TYPE3__SDMA1_SCRATCH_RAM_DATA__SHIFT                                                    0x17
#define SDMA1_PUB_REG_TYPE3__SDMA1_SCRATCH_RAM_ADDR__SHIFT                                                    0x18
#define SDMA1_PUB_REG_TYPE3__SDMA1_TIMESTAMP_CNTL__SHIFT                                                      0x19
#define SDMA1_PUB_REG_TYPE3__SDMA1_PERFCNT_PERFCOUNTER_LO__SHIFT                                              0x1a
#define SDMA1_PUB_REG_TYPE3__SDMA1_PERFCNT_PERFCOUNTER_HI__SHIFT                                              0x1b
#define SDMA1_PUB_REG_TYPE3__SDMA1_STATUS5_REG__SHIFT                                                         0x1c
#define SDMA1_PUB_REG_TYPE3__SDMA1_QUEUE_RESET_REQ__SHIFT                                                     0x1d
#define SDMA1_PUB_REG_TYPE3__RESERVED__SHIFT                                                                  0x1e
#define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_DATA_MASK                                                     0x00000001L
#define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_INDEX_MASK                                                    0x00000002L
#define SDMA1_PUB_REG_TYPE3__SDMA1_TLBI_GCR_CNTL_MASK                                                         0x00000004L
#define SDMA1_PUB_REG_TYPE3__SDMA1_TILING_CONFIG_MASK                                                         0x00000008L
#define SDMA1_PUB_REG_TYPE3__SDMA1_PERFCOUNTER0_SELECT_MASK                                                   0x00000100L
#define SDMA1_PUB_REG_TYPE3__SDMA1_PERFCOUNTER0_SELECT1_MASK                                                  0x00000200L
#define SDMA1_PUB_REG_TYPE3__SDMA1_PERFCOUNTER0_LO_MASK                                                       0x00000400L
#define SDMA1_PUB_REG_TYPE3__SDMA1_PERFCOUNTER0_HI_MASK                                                       0x00000800L
#define SDMA1_PUB_REG_TYPE3__SDMA1_PERFCOUNTER1_SELECT_MASK                                                   0x00001000L
#define SDMA1_PUB_REG_TYPE3__SDMA1_PERFCOUNTER1_SELECT1_MASK                                                  0x00002000L
#define SDMA1_PUB_REG_TYPE3__SDMA1_PERFCOUNTER1_LO_MASK                                                       0x00004000L
#define SDMA1_PUB_REG_TYPE3__SDMA1_PERFCOUNTER1_HI_MASK                                                       0x00008000L
#define SDMA1_PUB_REG_TYPE3__SDMA1_INT_STATUS_MASK                                                            0x00010000L
#define SDMA1_PUB_REG_TYPE3__SDMA1_HOLE_ADDR_LO_MASK                                                          0x00040000L
#define SDMA1_PUB_REG_TYPE3__SDMA1_HOLE_ADDR_HI_MASK                                                          0x00080000L
#define SDMA1_PUB_REG_TYPE3__SDMA1_CLOCK_GATING_REG_MASK                                                      0x00200000L
#define SDMA1_PUB_REG_TYPE3__SDMA1_STATUS4_REG_MASK                                                           0x00400000L
#define SDMA1_PUB_REG_TYPE3__SDMA1_SCRATCH_RAM_DATA_MASK                                                      0x00800000L
#define SDMA1_PUB_REG_TYPE3__SDMA1_SCRATCH_RAM_ADDR_MASK                                                      0x01000000L
#define SDMA1_PUB_REG_TYPE3__SDMA1_TIMESTAMP_CNTL_MASK                                                        0x02000000L
#define SDMA1_PUB_REG_TYPE3__SDMA1_PERFCNT_PERFCOUNTER_LO_MASK                                                0x04000000L
#define SDMA1_PUB_REG_TYPE3__SDMA1_PERFCNT_PERFCOUNTER_HI_MASK                                                0x08000000L
#define SDMA1_PUB_REG_TYPE3__SDMA1_STATUS5_REG_MASK                                                           0x10000000L
#define SDMA1_PUB_REG_TYPE3__SDMA1_QUEUE_RESET_REQ_MASK                                                       0x20000000L
#define SDMA1_PUB_REG_TYPE3__RESERVED_MASK                                                                    0xC0000000L
//SDMA1_VM_CNTL
#define SDMA1_VM_CNTL__CMD__SHIFT                                                                             0x0
#define SDMA1_VM_CNTL__CMD_MASK                                                                               0x0000000FL


// addressBlock: gc_sdma2_sdma2hypdec
//SDMA2_UCODE_ADDR
#define SDMA2_UCODE_ADDR__VALUE__SHIFT                                                                        0x0
#define SDMA2_UCODE_ADDR__VALUE_MASK                                                                          0x00003FFFL
//SDMA2_UCODE_DATA
#define SDMA2_UCODE_DATA__VALUE__SHIFT                                                                        0x0
#define SDMA2_UCODE_DATA__VALUE_MASK                                                                          0xFFFFFFFFL
//SDMA2_VM_CTX_LO
#define SDMA2_VM_CTX_LO__ADDR__SHIFT                                                                          0x2
#define SDMA2_VM_CTX_LO__ADDR_MASK                                                                            0xFFFFFFFCL
//SDMA2_VM_CTX_HI
#define SDMA2_VM_CTX_HI__ADDR__SHIFT                                                                          0x0
#define SDMA2_VM_CTX_HI__ADDR_MASK                                                                            0xFFFFFFFFL
//SDMA2_ACTIVE_FCN_ID
#define SDMA2_ACTIVE_FCN_ID__VFID__SHIFT                                                                      0x0
#define SDMA2_ACTIVE_FCN_ID__RESERVED__SHIFT                                                                  0x5
#define SDMA2_ACTIVE_FCN_ID__VF__SHIFT                                                                        0x1f
#define SDMA2_ACTIVE_FCN_ID__VFID_MASK                                                                        0x0000001FL
#define SDMA2_ACTIVE_FCN_ID__RESERVED_MASK                                                                    0x7FFFFFE0L
#define SDMA2_ACTIVE_FCN_ID__VF_MASK                                                                          0x80000000L
//SDMA2_VM_CTX_CNTL
#define SDMA2_VM_CTX_CNTL__PRIV__SHIFT                                                                        0x0
#define SDMA2_VM_CTX_CNTL__VMID__SHIFT                                                                        0x4
#define SDMA2_VM_CTX_CNTL__PRIV_MASK                                                                          0x00000001L
#define SDMA2_VM_CTX_CNTL__VMID_MASK                                                                          0x000000F0L
//SDMA2_VIRT_RESET_REQ
#define SDMA2_VIRT_RESET_REQ__VF__SHIFT                                                                       0x0
#define SDMA2_VIRT_RESET_REQ__PF__SHIFT                                                                       0x1f
#define SDMA2_VIRT_RESET_REQ__VF_MASK                                                                         0x7FFFFFFFL
#define SDMA2_VIRT_RESET_REQ__PF_MASK                                                                         0x80000000L
//SDMA2_VF_ENABLE
#define SDMA2_VF_ENABLE__VF_ENABLE__SHIFT                                                                     0x0
#define SDMA2_VF_ENABLE__VF_ENABLE_MASK                                                                       0x00000001L
//SDMA2_CONTEXT_REG_TYPE0
#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_CNTL__SHIFT                                                     0x0
#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_BASE__SHIFT                                                     0x1
#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_BASE_HI__SHIFT                                                  0x2
#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_RPTR__SHIFT                                                     0x3
#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_RPTR_HI__SHIFT                                                  0x4
#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_WPTR__SHIFT                                                     0x5
#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_WPTR_HI__SHIFT                                                  0x6
#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_WPTR_POLL_CNTL__SHIFT                                           0x7
#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_RPTR_ADDR_HI__SHIFT                                             0x8
#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_RPTR_ADDR_LO__SHIFT                                             0x9
#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_CNTL__SHIFT                                                     0xa
#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_RPTR__SHIFT                                                     0xb
#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_OFFSET__SHIFT                                                   0xc
#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_BASE_LO__SHIFT                                                  0xd
#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_BASE_HI__SHIFT                                                  0xe
#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_SIZE__SHIFT                                                     0xf
#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_SKIP_CNTL__SHIFT                                                   0x10
#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_CONTEXT_STATUS__SHIFT                                              0x11
#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_DOORBELL__SHIFT                                                    0x12
#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_CONTEXT_CNTL__SHIFT                                                0x13
#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_CNTL_MASK                                                       0x00000001L
#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_BASE_MASK                                                       0x00000002L
#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_BASE_HI_MASK                                                    0x00000004L
#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_RPTR_MASK                                                       0x00000008L
#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_RPTR_HI_MASK                                                    0x00000010L
#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_WPTR_MASK                                                       0x00000020L
#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_WPTR_HI_MASK                                                    0x00000040L
#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_WPTR_POLL_CNTL_MASK                                             0x00000080L
#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_RPTR_ADDR_HI_MASK                                               0x00000100L
#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_RPTR_ADDR_LO_MASK                                               0x00000200L
#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_CNTL_MASK                                                       0x00000400L
#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_RPTR_MASK                                                       0x00000800L
#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_OFFSET_MASK                                                     0x00001000L
#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_BASE_LO_MASK                                                    0x00002000L
#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_BASE_HI_MASK                                                    0x00004000L
#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_SIZE_MASK                                                       0x00008000L
#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_SKIP_CNTL_MASK                                                     0x00010000L
#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_CONTEXT_STATUS_MASK                                                0x00020000L
#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_DOORBELL_MASK                                                      0x00040000L
#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_CONTEXT_CNTL_MASK                                                  0x00080000L
//SDMA2_CONTEXT_REG_TYPE1
#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_STATUS__SHIFT                                                      0x8
#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_DOORBELL_LOG__SHIFT                                                0x9
#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_WATERMARK__SHIFT                                                   0xa
#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_DOORBELL_OFFSET__SHIFT                                             0xb
#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_CSA_ADDR_LO__SHIFT                                                 0xc
#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_CSA_ADDR_HI__SHIFT                                                 0xd
#define SDMA2_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT                                                             0xe
#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_IB_SUB_REMAIN__SHIFT                                               0xf
#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_PREEMPT__SHIFT                                                     0x10
#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_DUMMY_REG__SHIFT                                                   0x11
#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT                                        0x12
#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT                                        0x13
#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_RB_AQL_CNTL__SHIFT                                                 0x14
#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_MINOR_PTR_UPDATE__SHIFT                                            0x15
#define SDMA2_CONTEXT_REG_TYPE1__RESERVED__SHIFT                                                              0x18
#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_STATUS_MASK                                                        0x00000100L
#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_DOORBELL_LOG_MASK                                                  0x00000200L
#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_WATERMARK_MASK                                                     0x00000400L
#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_DOORBELL_OFFSET_MASK                                               0x00000800L
#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_CSA_ADDR_LO_MASK                                                   0x00001000L
#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_CSA_ADDR_HI_MASK                                                   0x00002000L
#define SDMA2_CONTEXT_REG_TYPE1__VOID_REG2_MASK                                                               0x00004000L
#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_IB_SUB_REMAIN_MASK                                                 0x00008000L
#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_PREEMPT_MASK                                                       0x00010000L
#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_DUMMY_REG_MASK                                                     0x00020000L
#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_RB_WPTR_POLL_ADDR_HI_MASK                                          0x00040000L
#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_RB_WPTR_POLL_ADDR_LO_MASK                                          0x00080000L
#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_RB_AQL_CNTL_MASK                                                   0x00100000L
#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_MINOR_PTR_UPDATE_MASK                                              0x00200000L
#define SDMA2_CONTEXT_REG_TYPE1__RESERVED_MASK                                                                0xFF000000L
//SDMA2_CONTEXT_REG_TYPE2
#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA0__SHIFT                                                0x0
#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA1__SHIFT                                                0x1
#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA2__SHIFT                                                0x2
#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA3__SHIFT                                                0x3
#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA4__SHIFT                                                0x4
#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA5__SHIFT                                                0x5
#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA6__SHIFT                                                0x6
#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA7__SHIFT                                                0x7
#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA8__SHIFT                                                0x8
#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA9__SHIFT                                                0x9
#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA10__SHIFT                                               0xa
#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_CNTL__SHIFT                                                 0xb
#define SDMA2_CONTEXT_REG_TYPE2__RESERVED__SHIFT                                                              0xc
#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA0_MASK                                                  0x00000001L
#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA1_MASK                                                  0x00000002L
#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA2_MASK                                                  0x00000004L
#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA3_MASK                                                  0x00000008L
#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA4_MASK                                                  0x00000010L
#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA5_MASK                                                  0x00000020L
#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA6_MASK                                                  0x00000040L
#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA7_MASK                                                  0x00000080L
#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA8_MASK                                                  0x00000100L
#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA9_MASK                                                  0x00000200L
#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA10_MASK                                                 0x00000400L
#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_CNTL_MASK                                                   0x00000800L
#define SDMA2_CONTEXT_REG_TYPE2__RESERVED_MASK                                                                0xFFFFF000L
//SDMA2_CONTEXT_REG_TYPE3
#define SDMA2_CONTEXT_REG_TYPE3__RESERVED__SHIFT                                                              0x0
#define SDMA2_CONTEXT_REG_TYPE3__RESERVED_MASK                                                                0xFFFFFFFFL
//SDMA2_PUB_REG_TYPE0
#define SDMA2_PUB_REG_TYPE0__SDMA2_UCODE_ADDR__SHIFT                                                          0x0
#define SDMA2_PUB_REG_TYPE0__SDMA2_UCODE_DATA__SHIFT                                                          0x1
#define SDMA2_PUB_REG_TYPE0__SDMA2_VM_CTX_LO__SHIFT                                                           0x2
#define SDMA2_PUB_REG_TYPE0__SDMA2_VM_CTX_HI__SHIFT                                                           0x3
#define SDMA2_PUB_REG_TYPE0__SDMA2_ACTIVE_FCN_ID__SHIFT                                                       0x4
#define SDMA2_PUB_REG_TYPE0__SDMA2_VM_CTX_CNTL__SHIFT                                                         0x5
#define SDMA2_PUB_REG_TYPE0__SDMA2_VIRT_RESET_REQ__SHIFT                                                      0x6
#define SDMA2_PUB_REG_TYPE0__SDMA2_VF_ENABLE__SHIFT                                                           0x7
#define SDMA2_PUB_REG_TYPE0__SDMA2_CONTEXT_REG_TYPE0__SHIFT                                                   0x8
#define SDMA2_PUB_REG_TYPE0__SDMA2_CONTEXT_REG_TYPE1__SHIFT                                                   0x9
#define SDMA2_PUB_REG_TYPE0__SDMA2_CONTEXT_REG_TYPE2__SHIFT                                                   0xa
#define SDMA2_PUB_REG_TYPE0__SDMA2_CONTEXT_REG_TYPE3__SHIFT                                                   0xb
#define SDMA2_PUB_REG_TYPE0__SDMA2_PUB_REG_TYPE0__SHIFT                                                       0xc
#define SDMA2_PUB_REG_TYPE0__SDMA2_PUB_REG_TYPE1__SHIFT                                                       0xd
#define SDMA2_PUB_REG_TYPE0__SDMA2_PUB_REG_TYPE2__SHIFT                                                       0xe
#define SDMA2_PUB_REG_TYPE0__SDMA2_PUB_REG_TYPE3__SHIFT                                                       0xf
#define SDMA2_PUB_REG_TYPE0__SDMA2_VM_CNTL__SHIFT                                                             0x13
#define SDMA2_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT                                           0x14
#define SDMA2_PUB_REG_TYPE0__SDMA2_PG_CNTL__SHIFT                                                             0x16
#define SDMA2_PUB_REG_TYPE0__SDMA2_PG_CTX_LO__SHIFT                                                           0x17
#define SDMA2_PUB_REG_TYPE0__SDMA2_PG_CTX_HI__SHIFT                                                           0x18
#define SDMA2_PUB_REG_TYPE0__SDMA2_PG_CTX_CNTL__SHIFT                                                         0x19
#define SDMA2_PUB_REG_TYPE0__SDMA2_POWER_CNTL__SHIFT                                                          0x1a
#define SDMA2_PUB_REG_TYPE0__SDMA2_CLK_CTRL__SHIFT                                                            0x1b
#define SDMA2_PUB_REG_TYPE0__SDMA2_CNTL__SHIFT                                                                0x1c
#define SDMA2_PUB_REG_TYPE0__SDMA2_CHICKEN_BITS__SHIFT                                                        0x1d
#define SDMA2_PUB_REG_TYPE0__SDMA2_GB_ADDR_CONFIG__SHIFT                                                      0x1e
#define SDMA2_PUB_REG_TYPE0__SDMA2_GB_ADDR_CONFIG_READ__SHIFT                                                 0x1f
#define SDMA2_PUB_REG_TYPE0__SDMA2_UCODE_ADDR_MASK                                                            0x00000001L
#define SDMA2_PUB_REG_TYPE0__SDMA2_UCODE_DATA_MASK                                                            0x00000002L
#define SDMA2_PUB_REG_TYPE0__SDMA2_VM_CTX_LO_MASK                                                             0x00000004L
#define SDMA2_PUB_REG_TYPE0__SDMA2_VM_CTX_HI_MASK                                                             0x00000008L
#define SDMA2_PUB_REG_TYPE0__SDMA2_ACTIVE_FCN_ID_MASK                                                         0x00000010L
#define SDMA2_PUB_REG_TYPE0__SDMA2_VM_CTX_CNTL_MASK                                                           0x00000020L
#define SDMA2_PUB_REG_TYPE0__SDMA2_VIRT_RESET_REQ_MASK                                                        0x00000040L
#define SDMA2_PUB_REG_TYPE0__SDMA2_VF_ENABLE_MASK                                                             0x00000080L
#define SDMA2_PUB_REG_TYPE0__SDMA2_CONTEXT_REG_TYPE0_MASK                                                     0x00000100L
#define SDMA2_PUB_REG_TYPE0__SDMA2_CONTEXT_REG_TYPE1_MASK                                                     0x00000200L
#define SDMA2_PUB_REG_TYPE0__SDMA2_CONTEXT_REG_TYPE2_MASK                                                     0x00000400L
#define SDMA2_PUB_REG_TYPE0__SDMA2_CONTEXT_REG_TYPE3_MASK                                                     0x00000800L
#define SDMA2_PUB_REG_TYPE0__SDMA2_PUB_REG_TYPE0_MASK                                                         0x00001000L
#define SDMA2_PUB_REG_TYPE0__SDMA2_PUB_REG_TYPE1_MASK                                                         0x00002000L
#define SDMA2_PUB_REG_TYPE0__SDMA2_PUB_REG_TYPE2_MASK                                                         0x00004000L
#define SDMA2_PUB_REG_TYPE0__SDMA2_PUB_REG_TYPE3_MASK                                                         0x00008000L
#define SDMA2_PUB_REG_TYPE0__SDMA2_VM_CNTL_MASK                                                               0x00080000L
#define SDMA2_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK                                             0x00300000L
#define SDMA2_PUB_REG_TYPE0__SDMA2_PG_CNTL_MASK                                                               0x00400000L
#define SDMA2_PUB_REG_TYPE0__SDMA2_PG_CTX_LO_MASK                                                             0x00800000L
#define SDMA2_PUB_REG_TYPE0__SDMA2_PG_CTX_HI_MASK                                                             0x01000000L
#define SDMA2_PUB_REG_TYPE0__SDMA2_PG_CTX_CNTL_MASK                                                           0x02000000L
#define SDMA2_PUB_REG_TYPE0__SDMA2_POWER_CNTL_MASK                                                            0x04000000L
#define SDMA2_PUB_REG_TYPE0__SDMA2_CLK_CTRL_MASK                                                              0x08000000L
#define SDMA2_PUB_REG_TYPE0__SDMA2_CNTL_MASK                                                                  0x10000000L
#define SDMA2_PUB_REG_TYPE0__SDMA2_CHICKEN_BITS_MASK                                                          0x20000000L
#define SDMA2_PUB_REG_TYPE0__SDMA2_GB_ADDR_CONFIG_MASK                                                        0x40000000L
#define SDMA2_PUB_REG_TYPE0__SDMA2_GB_ADDR_CONFIG_READ_MASK                                                   0x80000000L
//SDMA2_PUB_REG_TYPE1
#define SDMA2_PUB_REG_TYPE1__SDMA2_RB_RPTR_FETCH_HI__SHIFT                                                    0x0
#define SDMA2_PUB_REG_TYPE1__SDMA2_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT                                            0x1
#define SDMA2_PUB_REG_TYPE1__SDMA2_RB_RPTR_FETCH__SHIFT                                                       0x2
#define SDMA2_PUB_REG_TYPE1__SDMA2_IB_OFFSET_FETCH__SHIFT                                                     0x3
#define SDMA2_PUB_REG_TYPE1__SDMA2_PROGRAM__SHIFT                                                             0x4
#define SDMA2_PUB_REG_TYPE1__SDMA2_STATUS_REG__SHIFT                                                          0x5
#define SDMA2_PUB_REG_TYPE1__SDMA2_STATUS1_REG__SHIFT                                                         0x6
#define SDMA2_PUB_REG_TYPE1__SDMA2_RD_BURST_CNTL__SHIFT                                                       0x7
#define SDMA2_PUB_REG_TYPE1__SDMA2_HBM_PAGE_CONFIG__SHIFT                                                     0x8
#define SDMA2_PUB_REG_TYPE1__SDMA2_UCODE_CHECKSUM__SHIFT                                                      0x9
#define SDMA2_PUB_REG_TYPE1__SDMA2_F32_CNTL__SHIFT                                                            0xa
#define SDMA2_PUB_REG_TYPE1__SDMA2_FREEZE__SHIFT                                                              0xb
#define SDMA2_PUB_REG_TYPE1__SDMA2_PHASE0_QUANTUM__SHIFT                                                      0xc
#define SDMA2_PUB_REG_TYPE1__SDMA2_PHASE1_QUANTUM__SHIFT                                                      0xd
#define SDMA2_PUB_REG_TYPE1__SDMA2_EDC_CONFIG__SHIFT                                                          0x12
#define SDMA2_PUB_REG_TYPE1__SDMA2_BA_THRESHOLD__SHIFT                                                        0x13
#define SDMA2_PUB_REG_TYPE1__SDMA2_ID__SHIFT                                                                  0x14
#define SDMA2_PUB_REG_TYPE1__SDMA2_VERSION__SHIFT                                                             0x15
#define SDMA2_PUB_REG_TYPE1__SDMA2_EDC_COUNTER__SHIFT                                                         0x16
#define SDMA2_PUB_REG_TYPE1__SDMA2_EDC_COUNTER_CLEAR__SHIFT                                                   0x17
#define SDMA2_PUB_REG_TYPE1__SDMA2_STATUS2_REG__SHIFT                                                         0x18
#define SDMA2_PUB_REG_TYPE1__SDMA2_ATOMIC_CNTL__SHIFT                                                         0x19
#define SDMA2_PUB_REG_TYPE1__SDMA2_ATOMIC_PREOP_LO__SHIFT                                                     0x1a
#define SDMA2_PUB_REG_TYPE1__SDMA2_ATOMIC_PREOP_HI__SHIFT                                                     0x1b
#define SDMA2_PUB_REG_TYPE1__SDMA2_UTCL1_CNTL__SHIFT                                                          0x1c
#define SDMA2_PUB_REG_TYPE1__SDMA2_UTCL1_WATERMK__SHIFT                                                       0x1d
#define SDMA2_PUB_REG_TYPE1__SDMA2_UTCL1_RD_STATUS__SHIFT                                                     0x1e
#define SDMA2_PUB_REG_TYPE1__SDMA2_UTCL1_WR_STATUS__SHIFT                                                     0x1f
#define SDMA2_PUB_REG_TYPE1__SDMA2_RB_RPTR_FETCH_HI_MASK                                                      0x00000001L
#define SDMA2_PUB_REG_TYPE1__SDMA2_SEM_WAIT_FAIL_TIMER_CNTL_MASK                                              0x00000002L
#define SDMA2_PUB_REG_TYPE1__SDMA2_RB_RPTR_FETCH_MASK                                                         0x00000004L
#define SDMA2_PUB_REG_TYPE1__SDMA2_IB_OFFSET_FETCH_MASK                                                       0x00000008L
#define SDMA2_PUB_REG_TYPE1__SDMA2_PROGRAM_MASK                                                               0x00000010L
#define SDMA2_PUB_REG_TYPE1__SDMA2_STATUS_REG_MASK                                                            0x00000020L
#define SDMA2_PUB_REG_TYPE1__SDMA2_STATUS1_REG_MASK                                                           0x00000040L
#define SDMA2_PUB_REG_TYPE1__SDMA2_RD_BURST_CNTL_MASK                                                         0x00000080L
#define SDMA2_PUB_REG_TYPE1__SDMA2_HBM_PAGE_CONFIG_MASK                                                       0x00000100L
#define SDMA2_PUB_REG_TYPE1__SDMA2_UCODE_CHECKSUM_MASK                                                        0x00000200L
#define SDMA2_PUB_REG_TYPE1__SDMA2_F32_CNTL_MASK                                                              0x00000400L
#define SDMA2_PUB_REG_TYPE1__SDMA2_FREEZE_MASK                                                                0x00000800L
#define SDMA2_PUB_REG_TYPE1__SDMA2_PHASE0_QUANTUM_MASK                                                        0x00001000L
#define SDMA2_PUB_REG_TYPE1__SDMA2_PHASE1_QUANTUM_MASK                                                        0x00002000L
#define SDMA2_PUB_REG_TYPE1__SDMA2_EDC_CONFIG_MASK                                                            0x00040000L
#define SDMA2_PUB_REG_TYPE1__SDMA2_BA_THRESHOLD_MASK                                                          0x00080000L
#define SDMA2_PUB_REG_TYPE1__SDMA2_ID_MASK                                                                    0x00100000L
#define SDMA2_PUB_REG_TYPE1__SDMA2_VERSION_MASK                                                               0x00200000L
#define SDMA2_PUB_REG_TYPE1__SDMA2_EDC_COUNTER_MASK                                                           0x00400000L
#define SDMA2_PUB_REG_TYPE1__SDMA2_EDC_COUNTER_CLEAR_MASK                                                     0x00800000L
#define SDMA2_PUB_REG_TYPE1__SDMA2_STATUS2_REG_MASK                                                           0x01000000L
#define SDMA2_PUB_REG_TYPE1__SDMA2_ATOMIC_CNTL_MASK                                                           0x02000000L
#define SDMA2_PUB_REG_TYPE1__SDMA2_ATOMIC_PREOP_LO_MASK                                                       0x04000000L
#define SDMA2_PUB_REG_TYPE1__SDMA2_ATOMIC_PREOP_HI_MASK                                                       0x08000000L
#define SDMA2_PUB_REG_TYPE1__SDMA2_UTCL1_CNTL_MASK                                                            0x10000000L
#define SDMA2_PUB_REG_TYPE1__SDMA2_UTCL1_WATERMK_MASK                                                         0x20000000L
#define SDMA2_PUB_REG_TYPE1__SDMA2_UTCL1_RD_STATUS_MASK                                                       0x40000000L
#define SDMA2_PUB_REG_TYPE1__SDMA2_UTCL1_WR_STATUS_MASK                                                       0x80000000L
//SDMA2_PUB_REG_TYPE2
#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_INV0__SHIFT                                                          0x0
#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_INV1__SHIFT                                                          0x1
#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_INV2__SHIFT                                                          0x2
#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_RD_XNACK0__SHIFT                                                     0x3
#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_RD_XNACK1__SHIFT                                                     0x4
#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_WR_XNACK0__SHIFT                                                     0x5
#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_WR_XNACK1__SHIFT                                                     0x6
#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_TIMEOUT__SHIFT                                                       0x7
#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_PAGE__SHIFT                                                          0x8
#define SDMA2_PUB_REG_TYPE2__SDMA2_RELAX_ORDERING_LUT__SHIFT                                                  0xa
#define SDMA2_PUB_REG_TYPE2__SDMA2_CHICKEN_BITS_2__SHIFT                                                      0xb
#define SDMA2_PUB_REG_TYPE2__SDMA2_STATUS3_REG__SHIFT                                                         0xc
#define SDMA2_PUB_REG_TYPE2__SDMA2_PHYSICAL_ADDR_LO__SHIFT                                                    0xd
#define SDMA2_PUB_REG_TYPE2__SDMA2_PHYSICAL_ADDR_HI__SHIFT                                                    0xe
#define SDMA2_PUB_REG_TYPE2__SDMA2_PHASE2_QUANTUM__SHIFT                                                      0xf
#define SDMA2_PUB_REG_TYPE2__SDMA2_ERROR_LOG__SHIFT                                                           0x10
#define SDMA2_PUB_REG_TYPE2__SDMA2_PUB_DUMMY_REG0__SHIFT                                                      0x11
#define SDMA2_PUB_REG_TYPE2__SDMA2_PUB_DUMMY_REG1__SHIFT                                                      0x12
#define SDMA2_PUB_REG_TYPE2__SDMA2_PUB_DUMMY_REG2__SHIFT                                                      0x13
#define SDMA2_PUB_REG_TYPE2__SDMA2_PUB_DUMMY_REG3__SHIFT                                                      0x14
#define SDMA2_PUB_REG_TYPE2__SDMA2_F32_COUNTER__SHIFT                                                         0x15
#define SDMA2_PUB_REG_TYPE2__SDMA2_PERFCNT_PERFCOUNTER0_CFG__SHIFT                                            0x17
#define SDMA2_PUB_REG_TYPE2__SDMA2_PERFCNT_PERFCOUNTER1_CFG__SHIFT                                            0x18
#define SDMA2_PUB_REG_TYPE2__SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL__SHIFT                                       0x19
#define SDMA2_PUB_REG_TYPE2__SDMA2_PERFCNT_MISC_CNTL__SHIFT                                                   0x1a
#define SDMA2_PUB_REG_TYPE2__SDMA2_CRD_CNTL__SHIFT                                                            0x1b
#define SDMA2_PUB_REG_TYPE2__SDMA2_AQL_STATUS__SHIFT                                                          0x1f
#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_INV0_MASK                                                            0x00000001L
#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_INV1_MASK                                                            0x00000002L
#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_INV2_MASK                                                            0x00000004L
#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_RD_XNACK0_MASK                                                       0x00000008L
#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_RD_XNACK1_MASK                                                       0x00000010L
#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_WR_XNACK0_MASK                                                       0x00000020L
#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_WR_XNACK1_MASK                                                       0x00000040L
#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_TIMEOUT_MASK                                                         0x00000080L
#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_PAGE_MASK                                                            0x00000100L
#define SDMA2_PUB_REG_TYPE2__SDMA2_RELAX_ORDERING_LUT_MASK                                                    0x00000400L
#define SDMA2_PUB_REG_TYPE2__SDMA2_CHICKEN_BITS_2_MASK                                                        0x00000800L
#define SDMA2_PUB_REG_TYPE2__SDMA2_STATUS3_REG_MASK                                                           0x00001000L
#define SDMA2_PUB_REG_TYPE2__SDMA2_PHYSICAL_ADDR_LO_MASK                                                      0x00002000L
#define SDMA2_PUB_REG_TYPE2__SDMA2_PHYSICAL_ADDR_HI_MASK                                                      0x00004000L
#define SDMA2_PUB_REG_TYPE2__SDMA2_PHASE2_QUANTUM_MASK                                                        0x00008000L
#define SDMA2_PUB_REG_TYPE2__SDMA2_ERROR_LOG_MASK                                                             0x00010000L
#define SDMA2_PUB_REG_TYPE2__SDMA2_PUB_DUMMY_REG0_MASK                                                        0x00020000L
#define SDMA2_PUB_REG_TYPE2__SDMA2_PUB_DUMMY_REG1_MASK                                                        0x00040000L
#define SDMA2_PUB_REG_TYPE2__SDMA2_PUB_DUMMY_REG2_MASK                                                        0x00080000L
#define SDMA2_PUB_REG_TYPE2__SDMA2_PUB_DUMMY_REG3_MASK                                                        0x00100000L
#define SDMA2_PUB_REG_TYPE2__SDMA2_F32_COUNTER_MASK                                                           0x00200000L
#define SDMA2_PUB_REG_TYPE2__SDMA2_PERFCNT_PERFCOUNTER0_CFG_MASK                                              0x00800000L
#define SDMA2_PUB_REG_TYPE2__SDMA2_PERFCNT_PERFCOUNTER1_CFG_MASK                                              0x01000000L
#define SDMA2_PUB_REG_TYPE2__SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL_MASK                                         0x02000000L
#define SDMA2_PUB_REG_TYPE2__SDMA2_PERFCNT_MISC_CNTL_MASK                                                     0x04000000L
#define SDMA2_PUB_REG_TYPE2__SDMA2_CRD_CNTL_MASK                                                              0x08000000L
#define SDMA2_PUB_REG_TYPE2__SDMA2_AQL_STATUS_MASK                                                            0x80000000L
//SDMA2_PUB_REG_TYPE3
#define SDMA2_PUB_REG_TYPE3__SDMA2_EA_DBIT_ADDR_DATA__SHIFT                                                   0x0
#define SDMA2_PUB_REG_TYPE3__SDMA2_EA_DBIT_ADDR_INDEX__SHIFT                                                  0x1
#define SDMA2_PUB_REG_TYPE3__SDMA2_TLBI_GCR_CNTL__SHIFT                                                       0x2
#define SDMA2_PUB_REG_TYPE3__SDMA2_TILING_CONFIG__SHIFT                                                       0x3
#define SDMA2_PUB_REG_TYPE3__SDMA2_PERFCOUNTER0_SELECT__SHIFT                                                 0x8
#define SDMA2_PUB_REG_TYPE3__SDMA2_PERFCOUNTER0_SELECT1__SHIFT                                                0x9
#define SDMA2_PUB_REG_TYPE3__SDMA2_PERFCOUNTER0_LO__SHIFT                                                     0xa
#define SDMA2_PUB_REG_TYPE3__SDMA2_PERFCOUNTER0_HI__SHIFT                                                     0xb
#define SDMA2_PUB_REG_TYPE3__SDMA2_PERFCOUNTER1_SELECT__SHIFT                                                 0xc
#define SDMA2_PUB_REG_TYPE3__SDMA2_PERFCOUNTER1_SELECT1__SHIFT                                                0xd
#define SDMA2_PUB_REG_TYPE3__SDMA2_PERFCOUNTER1_LO__SHIFT                                                     0xe
#define SDMA2_PUB_REG_TYPE3__SDMA2_PERFCOUNTER1_HI__SHIFT                                                     0xf
#define SDMA2_PUB_REG_TYPE3__SDMA2_INT_STATUS__SHIFT                                                          0x10
#define SDMA2_PUB_REG_TYPE3__SDMA2_HOLE_ADDR_LO__SHIFT                                                        0x12
#define SDMA2_PUB_REG_TYPE3__SDMA2_HOLE_ADDR_HI__SHIFT                                                        0x13
#define SDMA2_PUB_REG_TYPE3__SDMA2_CLOCK_GATING_REG__SHIFT                                                    0x15
#define SDMA2_PUB_REG_TYPE3__SDMA2_STATUS4_REG__SHIFT                                                         0x16
#define SDMA2_PUB_REG_TYPE3__SDMA2_SCRATCH_RAM_DATA__SHIFT                                                    0x17
#define SDMA2_PUB_REG_TYPE3__SDMA2_SCRATCH_RAM_ADDR__SHIFT                                                    0x18
#define SDMA2_PUB_REG_TYPE3__SDMA2_TIMESTAMP_CNTL__SHIFT                                                      0x19
#define SDMA2_PUB_REG_TYPE3__SDMA2_PERFCNT_PERFCOUNTER_LO__SHIFT                                              0x1a
#define SDMA2_PUB_REG_TYPE3__SDMA2_PERFCNT_PERFCOUNTER_HI__SHIFT                                              0x1b
#define SDMA2_PUB_REG_TYPE3__SDMA2_STATUS5_REG__SHIFT                                                         0x1c
#define SDMA2_PUB_REG_TYPE3__SDMA2_QUEUE_RESET_REQ__SHIFT                                                     0x1d
#define SDMA2_PUB_REG_TYPE3__RESERVED__SHIFT                                                                  0x1e
#define SDMA2_PUB_REG_TYPE3__SDMA2_EA_DBIT_ADDR_DATA_MASK                                                     0x00000001L
#define SDMA2_PUB_REG_TYPE3__SDMA2_EA_DBIT_ADDR_INDEX_MASK                                                    0x00000002L
#define SDMA2_PUB_REG_TYPE3__SDMA2_TLBI_GCR_CNTL_MASK                                                         0x00000004L
#define SDMA2_PUB_REG_TYPE3__SDMA2_TILING_CONFIG_MASK                                                         0x00000008L
#define SDMA2_PUB_REG_TYPE3__SDMA2_PERFCOUNTER0_SELECT_MASK                                                   0x00000100L
#define SDMA2_PUB_REG_TYPE3__SDMA2_PERFCOUNTER0_SELECT1_MASK                                                  0x00000200L
#define SDMA2_PUB_REG_TYPE3__SDMA2_PERFCOUNTER0_LO_MASK                                                       0x00000400L
#define SDMA2_PUB_REG_TYPE3__SDMA2_PERFCOUNTER0_HI_MASK                                                       0x00000800L
#define SDMA2_PUB_REG_TYPE3__SDMA2_PERFCOUNTER1_SELECT_MASK                                                   0x00001000L
#define SDMA2_PUB_REG_TYPE3__SDMA2_PERFCOUNTER1_SELECT1_MASK                                                  0x00002000L
#define SDMA2_PUB_REG_TYPE3__SDMA2_PERFCOUNTER1_LO_MASK                                                       0x00004000L
#define SDMA2_PUB_REG_TYPE3__SDMA2_PERFCOUNTER1_HI_MASK                                                       0x00008000L
#define SDMA2_PUB_REG_TYPE3__SDMA2_INT_STATUS_MASK                                                            0x00010000L
#define SDMA2_PUB_REG_TYPE3__SDMA2_HOLE_ADDR_LO_MASK                                                          0x00040000L
#define SDMA2_PUB_REG_TYPE3__SDMA2_HOLE_ADDR_HI_MASK                                                          0x00080000L
#define SDMA2_PUB_REG_TYPE3__SDMA2_CLOCK_GATING_REG_MASK                                                      0x00200000L
#define SDMA2_PUB_REG_TYPE3__SDMA2_STATUS4_REG_MASK                                                           0x00400000L
#define SDMA2_PUB_REG_TYPE3__SDMA2_SCRATCH_RAM_DATA_MASK                                                      0x00800000L
#define SDMA2_PUB_REG_TYPE3__SDMA2_SCRATCH_RAM_ADDR_MASK                                                      0x01000000L
#define SDMA2_PUB_REG_TYPE3__SDMA2_TIMESTAMP_CNTL_MASK                                                        0x02000000L
#define SDMA2_PUB_REG_TYPE3__SDMA2_PERFCNT_PERFCOUNTER_LO_MASK                                                0x04000000L
#define SDMA2_PUB_REG_TYPE3__SDMA2_PERFCNT_PERFCOUNTER_HI_MASK                                                0x08000000L
#define SDMA2_PUB_REG_TYPE3__SDMA2_STATUS5_REG_MASK                                                           0x10000000L
#define SDMA2_PUB_REG_TYPE3__SDMA2_QUEUE_RESET_REQ_MASK                                                       0x20000000L
#define SDMA2_PUB_REG_TYPE3__RESERVED_MASK                                                                    0xC0000000L
//SDMA2_VM_CNTL
#define SDMA2_VM_CNTL__CMD__SHIFT                                                                             0x0
#define SDMA2_VM_CNTL__CMD_MASK                                                                               0x0000000FL


// addressBlock: gc_sdma3_sdma3hypdec
//SDMA3_UCODE_ADDR
#define SDMA3_UCODE_ADDR__VALUE__SHIFT                                                                        0x0
#define SDMA3_UCODE_ADDR__VALUE_MASK                                                                          0x00003FFFL
//SDMA3_UCODE_DATA
#define SDMA3_UCODE_DATA__VALUE__SHIFT                                                                        0x0
#define SDMA3_UCODE_DATA__VALUE_MASK                                                                          0xFFFFFFFFL
//SDMA3_VM_CTX_LO
#define SDMA3_VM_CTX_LO__ADDR__SHIFT                                                                          0x2
#define SDMA3_VM_CTX_LO__ADDR_MASK                                                                            0xFFFFFFFCL
//SDMA3_VM_CTX_HI
#define SDMA3_VM_CTX_HI__ADDR__SHIFT                                                                          0x0
#define SDMA3_VM_CTX_HI__ADDR_MASK                                                                            0xFFFFFFFFL
//SDMA3_ACTIVE_FCN_ID
#define SDMA3_ACTIVE_FCN_ID__VFID__SHIFT                                                                      0x0
#define SDMA3_ACTIVE_FCN_ID__RESERVED__SHIFT                                                                  0x5
#define SDMA3_ACTIVE_FCN_ID__VF__SHIFT                                                                        0x1f
#define SDMA3_ACTIVE_FCN_ID__VFID_MASK                                                                        0x0000001FL
#define SDMA3_ACTIVE_FCN_ID__RESERVED_MASK                                                                    0x7FFFFFE0L
#define SDMA3_ACTIVE_FCN_ID__VF_MASK                                                                          0x80000000L
//SDMA3_VM_CTX_CNTL
#define SDMA3_VM_CTX_CNTL__PRIV__SHIFT                                                                        0x0
#define SDMA3_VM_CTX_CNTL__VMID__SHIFT                                                                        0x4
#define SDMA3_VM_CTX_CNTL__PRIV_MASK                                                                          0x00000001L
#define SDMA3_VM_CTX_CNTL__VMID_MASK                                                                          0x000000F0L
//SDMA3_VIRT_RESET_REQ
#define SDMA3_VIRT_RESET_REQ__VF__SHIFT                                                                       0x0
#define SDMA3_VIRT_RESET_REQ__PF__SHIFT                                                                       0x1f
#define SDMA3_VIRT_RESET_REQ__VF_MASK                                                                         0x7FFFFFFFL
#define SDMA3_VIRT_RESET_REQ__PF_MASK                                                                         0x80000000L
//SDMA3_VF_ENABLE
#define SDMA3_VF_ENABLE__VF_ENABLE__SHIFT                                                                     0x0
#define SDMA3_VF_ENABLE__VF_ENABLE_MASK                                                                       0x00000001L
//SDMA3_CONTEXT_REG_TYPE0
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_CNTL__SHIFT                                                     0x0
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_BASE__SHIFT                                                     0x1
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_BASE_HI__SHIFT                                                  0x2
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_RPTR__SHIFT                                                     0x3
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_RPTR_HI__SHIFT                                                  0x4
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_WPTR__SHIFT                                                     0x5
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_WPTR_HI__SHIFT                                                  0x6
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_WPTR_POLL_CNTL__SHIFT                                           0x7
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_RPTR_ADDR_HI__SHIFT                                             0x8
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_RPTR_ADDR_LO__SHIFT                                             0x9
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_CNTL__SHIFT                                                     0xa
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_RPTR__SHIFT                                                     0xb
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_OFFSET__SHIFT                                                   0xc
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_BASE_LO__SHIFT                                                  0xd
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_BASE_HI__SHIFT                                                  0xe
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_SIZE__SHIFT                                                     0xf
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_SKIP_CNTL__SHIFT                                                   0x10
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_CONTEXT_STATUS__SHIFT                                              0x11
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_DOORBELL__SHIFT                                                    0x12
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_CONTEXT_CNTL__SHIFT                                                0x13
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_CNTL_MASK                                                       0x00000001L
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_BASE_MASK                                                       0x00000002L
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_BASE_HI_MASK                                                    0x00000004L
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_RPTR_MASK                                                       0x00000008L
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_RPTR_HI_MASK                                                    0x00000010L
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_WPTR_MASK                                                       0x00000020L
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_WPTR_HI_MASK                                                    0x00000040L
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_WPTR_POLL_CNTL_MASK                                             0x00000080L
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_RPTR_ADDR_HI_MASK                                               0x00000100L
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_RPTR_ADDR_LO_MASK                                               0x00000200L
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_CNTL_MASK                                                       0x00000400L
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_RPTR_MASK                                                       0x00000800L
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_OFFSET_MASK                                                     0x00001000L
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_BASE_LO_MASK                                                    0x00002000L
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_BASE_HI_MASK                                                    0x00004000L
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_SIZE_MASK                                                       0x00008000L
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_SKIP_CNTL_MASK                                                     0x00010000L
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_CONTEXT_STATUS_MASK                                                0x00020000L
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_DOORBELL_MASK                                                      0x00040000L
#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_CONTEXT_CNTL_MASK                                                  0x00080000L
//SDMA3_CONTEXT_REG_TYPE1
#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_STATUS__SHIFT                                                      0x8
#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_DOORBELL_LOG__SHIFT                                                0x9
#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_WATERMARK__SHIFT                                                   0xa
#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_DOORBELL_OFFSET__SHIFT                                             0xb
#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_CSA_ADDR_LO__SHIFT                                                 0xc
#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_CSA_ADDR_HI__SHIFT                                                 0xd
#define SDMA3_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT                                                             0xe
#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_IB_SUB_REMAIN__SHIFT                                               0xf
#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_PREEMPT__SHIFT                                                     0x10
#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_DUMMY_REG__SHIFT                                                   0x11
#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT                                        0x12
#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT                                        0x13
#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_RB_AQL_CNTL__SHIFT                                                 0x14
#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_MINOR_PTR_UPDATE__SHIFT                                            0x15
#define SDMA3_CONTEXT_REG_TYPE1__RESERVED__SHIFT                                                              0x18
#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_STATUS_MASK                                                        0x00000100L
#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_DOORBELL_LOG_MASK                                                  0x00000200L
#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_WATERMARK_MASK                                                     0x00000400L
#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_DOORBELL_OFFSET_MASK                                               0x00000800L
#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_CSA_ADDR_LO_MASK                                                   0x00001000L
#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_CSA_ADDR_HI_MASK                                                   0x00002000L
#define SDMA3_CONTEXT_REG_TYPE1__VOID_REG2_MASK                                                               0x00004000L
#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_IB_SUB_REMAIN_MASK                                                 0x00008000L
#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_PREEMPT_MASK                                                       0x00010000L
#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_DUMMY_REG_MASK                                                     0x00020000L
#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_RB_WPTR_POLL_ADDR_HI_MASK                                          0x00040000L
#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_RB_WPTR_POLL_ADDR_LO_MASK                                          0x00080000L
#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_RB_AQL_CNTL_MASK                                                   0x00100000L
#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_MINOR_PTR_UPDATE_MASK                                              0x00200000L
#define SDMA3_CONTEXT_REG_TYPE1__RESERVED_MASK                                                                0xFF000000L
//SDMA3_CONTEXT_REG_TYPE2
#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA0__SHIFT                                                0x0
#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA1__SHIFT                                                0x1
#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA2__SHIFT                                                0x2
#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA3__SHIFT                                                0x3
#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA4__SHIFT                                                0x4
#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA5__SHIFT                                                0x5
#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA6__SHIFT                                                0x6
#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA7__SHIFT                                                0x7
#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA8__SHIFT                                                0x8
#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA9__SHIFT                                                0x9
#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA10__SHIFT                                               0xa
#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_CNTL__SHIFT                                                 0xb
#define SDMA3_CONTEXT_REG_TYPE2__RESERVED__SHIFT                                                              0xc
#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA0_MASK                                                  0x00000001L
#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA1_MASK                                                  0x00000002L
#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA2_MASK                                                  0x00000004L
#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA3_MASK                                                  0x00000008L
#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA4_MASK                                                  0x00000010L
#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA5_MASK                                                  0x00000020L
#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA6_MASK                                                  0x00000040L
#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA7_MASK                                                  0x00000080L
#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA8_MASK                                                  0x00000100L
#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA9_MASK                                                  0x00000200L
#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA10_MASK                                                 0x00000400L
#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_CNTL_MASK                                                   0x00000800L
#define SDMA3_CONTEXT_REG_TYPE2__RESERVED_MASK                                                                0xFFFFF000L
//SDMA3_CONTEXT_REG_TYPE3
#define SDMA3_CONTEXT_REG_TYPE3__RESERVED__SHIFT                                                              0x0
#define SDMA3_CONTEXT_REG_TYPE3__RESERVED_MASK                                                                0xFFFFFFFFL
//SDMA3_PUB_REG_TYPE0
#define SDMA3_PUB_REG_TYPE0__SDMA3_UCODE_ADDR__SHIFT                                                          0x0
#define SDMA3_PUB_REG_TYPE0__SDMA3_UCODE_DATA__SHIFT                                                          0x1
#define SDMA3_PUB_REG_TYPE0__SDMA3_VM_CTX_LO__SHIFT                                                           0x2
#define SDMA3_PUB_REG_TYPE0__SDMA3_VM_CTX_HI__SHIFT                                                           0x3
#define SDMA3_PUB_REG_TYPE0__SDMA3_ACTIVE_FCN_ID__SHIFT                                                       0x4
#define SDMA3_PUB_REG_TYPE0__SDMA3_VM_CTX_CNTL__SHIFT                                                         0x5
#define SDMA3_PUB_REG_TYPE0__SDMA3_VIRT_RESET_REQ__SHIFT                                                      0x6
#define SDMA3_PUB_REG_TYPE0__SDMA3_VF_ENABLE__SHIFT                                                           0x7
#define SDMA3_PUB_REG_TYPE0__SDMA3_CONTEXT_REG_TYPE0__SHIFT                                                   0x8
#define SDMA3_PUB_REG_TYPE0__SDMA3_CONTEXT_REG_TYPE1__SHIFT                                                   0x9
#define SDMA3_PUB_REG_TYPE0__SDMA3_CONTEXT_REG_TYPE2__SHIFT                                                   0xa
#define SDMA3_PUB_REG_TYPE0__SDMA3_CONTEXT_REG_TYPE3__SHIFT                                                   0xb
#define SDMA3_PUB_REG_TYPE0__SDMA3_PUB_REG_TYPE0__SHIFT                                                       0xc
#define SDMA3_PUB_REG_TYPE0__SDMA3_PUB_REG_TYPE1__SHIFT                                                       0xd
#define SDMA3_PUB_REG_TYPE0__SDMA3_PUB_REG_TYPE2__SHIFT                                                       0xe
#define SDMA3_PUB_REG_TYPE0__SDMA3_PUB_REG_TYPE3__SHIFT                                                       0xf
#define SDMA3_PUB_REG_TYPE0__SDMA3_VM_CNTL__SHIFT                                                             0x13
#define SDMA3_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT                                           0x14
#define SDMA3_PUB_REG_TYPE0__SDMA3_PG_CNTL__SHIFT                                                             0x16
#define SDMA3_PUB_REG_TYPE0__SDMA3_PG_CTX_LO__SHIFT                                                           0x17
#define SDMA3_PUB_REG_TYPE0__SDMA3_PG_CTX_HI__SHIFT                                                           0x18
#define SDMA3_PUB_REG_TYPE0__SDMA3_PG_CTX_CNTL__SHIFT                                                         0x19
#define SDMA3_PUB_REG_TYPE0__SDMA3_POWER_CNTL__SHIFT                                                          0x1a
#define SDMA3_PUB_REG_TYPE0__SDMA3_CLK_CTRL__SHIFT                                                            0x1b
#define SDMA3_PUB_REG_TYPE0__SDMA3_CNTL__SHIFT                                                                0x1c
#define SDMA3_PUB_REG_TYPE0__SDMA3_CHICKEN_BITS__SHIFT                                                        0x1d
#define SDMA3_PUB_REG_TYPE0__SDMA3_GB_ADDR_CONFIG__SHIFT                                                      0x1e
#define SDMA3_PUB_REG_TYPE0__SDMA3_GB_ADDR_CONFIG_READ__SHIFT                                                 0x1f
#define SDMA3_PUB_REG_TYPE0__SDMA3_UCODE_ADDR_MASK                                                            0x00000001L
#define SDMA3_PUB_REG_TYPE0__SDMA3_UCODE_DATA_MASK                                                            0x00000002L
#define SDMA3_PUB_REG_TYPE0__SDMA3_VM_CTX_LO_MASK                                                             0x00000004L
#define SDMA3_PUB_REG_TYPE0__SDMA3_VM_CTX_HI_MASK                                                             0x00000008L
#define SDMA3_PUB_REG_TYPE0__SDMA3_ACTIVE_FCN_ID_MASK                                                         0x00000010L
#define SDMA3_PUB_REG_TYPE0__SDMA3_VM_CTX_CNTL_MASK                                                           0x00000020L
#define SDMA3_PUB_REG_TYPE0__SDMA3_VIRT_RESET_REQ_MASK                                                        0x00000040L
#define SDMA3_PUB_REG_TYPE0__SDMA3_VF_ENABLE_MASK                                                             0x00000080L
#define SDMA3_PUB_REG_TYPE0__SDMA3_CONTEXT_REG_TYPE0_MASK                                                     0x00000100L
#define SDMA3_PUB_REG_TYPE0__SDMA3_CONTEXT_REG_TYPE1_MASK                                                     0x00000200L
#define SDMA3_PUB_REG_TYPE0__SDMA3_CONTEXT_REG_TYPE2_MASK                                                     0x00000400L
#define SDMA3_PUB_REG_TYPE0__SDMA3_CONTEXT_REG_TYPE3_MASK                                                     0x00000800L
#define SDMA3_PUB_REG_TYPE0__SDMA3_PUB_REG_TYPE0_MASK                                                         0x00001000L
#define SDMA3_PUB_REG_TYPE0__SDMA3_PUB_REG_TYPE1_MASK                                                         0x00002000L
#define SDMA3_PUB_REG_TYPE0__SDMA3_PUB_REG_TYPE2_MASK                                                         0x00004000L
#define SDMA3_PUB_REG_TYPE0__SDMA3_PUB_REG_TYPE3_MASK                                                         0x00008000L
#define SDMA3_PUB_REG_TYPE0__SDMA3_VM_CNTL_MASK                                                               0x00080000L
#define SDMA3_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK                                             0x00300000L
#define SDMA3_PUB_REG_TYPE0__SDMA3_PG_CNTL_MASK                                                               0x00400000L
#define SDMA3_PUB_REG_TYPE0__SDMA3_PG_CTX_LO_MASK                                                             0x00800000L
#define SDMA3_PUB_REG_TYPE0__SDMA3_PG_CTX_HI_MASK                                                             0x01000000L
#define SDMA3_PUB_REG_TYPE0__SDMA3_PG_CTX_CNTL_MASK                                                           0x02000000L
#define SDMA3_PUB_REG_TYPE0__SDMA3_POWER_CNTL_MASK                                                            0x04000000L
#define SDMA3_PUB_REG_TYPE0__SDMA3_CLK_CTRL_MASK                                                              0x08000000L
#define SDMA3_PUB_REG_TYPE0__SDMA3_CNTL_MASK                                                                  0x10000000L
#define SDMA3_PUB_REG_TYPE0__SDMA3_CHICKEN_BITS_MASK                                                          0x20000000L
#define SDMA3_PUB_REG_TYPE0__SDMA3_GB_ADDR_CONFIG_MASK                                                        0x40000000L
#define SDMA3_PUB_REG_TYPE0__SDMA3_GB_ADDR_CONFIG_READ_MASK                                                   0x80000000L
//SDMA3_PUB_REG_TYPE1
#define SDMA3_PUB_REG_TYPE1__SDMA3_RB_RPTR_FETCH_HI__SHIFT                                                    0x0
#define SDMA3_PUB_REG_TYPE1__SDMA3_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT                                            0x1
#define SDMA3_PUB_REG_TYPE1__SDMA3_RB_RPTR_FETCH__SHIFT                                                       0x2
#define SDMA3_PUB_REG_TYPE1__SDMA3_IB_OFFSET_FETCH__SHIFT                                                     0x3
#define SDMA3_PUB_REG_TYPE1__SDMA3_PROGRAM__SHIFT                                                             0x4
#define SDMA3_PUB_REG_TYPE1__SDMA3_STATUS_REG__SHIFT                                                          0x5
#define SDMA3_PUB_REG_TYPE1__SDMA3_STATUS1_REG__SHIFT                                                         0x6
#define SDMA3_PUB_REG_TYPE1__SDMA3_RD_BURST_CNTL__SHIFT                                                       0x7
#define SDMA3_PUB_REG_TYPE1__SDMA3_HBM_PAGE_CONFIG__SHIFT                                                     0x8
#define SDMA3_PUB_REG_TYPE1__SDMA3_UCODE_CHECKSUM__SHIFT                                                      0x9
#define SDMA3_PUB_REG_TYPE1__SDMA3_F32_CNTL__SHIFT                                                            0xa
#define SDMA3_PUB_REG_TYPE1__SDMA3_FREEZE__SHIFT                                                              0xb
#define SDMA3_PUB_REG_TYPE1__SDMA3_PHASE0_QUANTUM__SHIFT                                                      0xc
#define SDMA3_PUB_REG_TYPE1__SDMA3_PHASE1_QUANTUM__SHIFT                                                      0xd
#define SDMA3_PUB_REG_TYPE1__SDMA3_EDC_CONFIG__SHIFT                                                          0x12
#define SDMA3_PUB_REG_TYPE1__SDMA3_BA_THRESHOLD__SHIFT                                                        0x13
#define SDMA3_PUB_REG_TYPE1__SDMA3_ID__SHIFT                                                                  0x14
#define SDMA3_PUB_REG_TYPE1__SDMA3_VERSION__SHIFT                                                             0x15
#define SDMA3_PUB_REG_TYPE1__SDMA3_EDC_COUNTER__SHIFT                                                         0x16
#define SDMA3_PUB_REG_TYPE1__SDMA3_EDC_COUNTER_CLEAR__SHIFT                                                   0x17
#define SDMA3_PUB_REG_TYPE1__SDMA3_STATUS2_REG__SHIFT                                                         0x18
#define SDMA3_PUB_REG_TYPE1__SDMA3_ATOMIC_CNTL__SHIFT                                                         0x19
#define SDMA3_PUB_REG_TYPE1__SDMA3_ATOMIC_PREOP_LO__SHIFT                                                     0x1a
#define SDMA3_PUB_REG_TYPE1__SDMA3_ATOMIC_PREOP_HI__SHIFT                                                     0x1b
#define SDMA3_PUB_REG_TYPE1__SDMA3_UTCL1_CNTL__SHIFT                                                          0x1c
#define SDMA3_PUB_REG_TYPE1__SDMA3_UTCL1_WATERMK__SHIFT                                                       0x1d
#define SDMA3_PUB_REG_TYPE1__SDMA3_UTCL1_RD_STATUS__SHIFT                                                     0x1e
#define SDMA3_PUB_REG_TYPE1__SDMA3_UTCL1_WR_STATUS__SHIFT                                                     0x1f
#define SDMA3_PUB_REG_TYPE1__SDMA3_RB_RPTR_FETCH_HI_MASK                                                      0x00000001L
#define SDMA3_PUB_REG_TYPE1__SDMA3_SEM_WAIT_FAIL_TIMER_CNTL_MASK                                              0x00000002L
#define SDMA3_PUB_REG_TYPE1__SDMA3_RB_RPTR_FETCH_MASK                                                         0x00000004L
#define SDMA3_PUB_REG_TYPE1__SDMA3_IB_OFFSET_FETCH_MASK                                                       0x00000008L
#define SDMA3_PUB_REG_TYPE1__SDMA3_PROGRAM_MASK                                                               0x00000010L
#define SDMA3_PUB_REG_TYPE1__SDMA3_STATUS_REG_MASK                                                            0x00000020L
#define SDMA3_PUB_REG_TYPE1__SDMA3_STATUS1_REG_MASK                                                           0x00000040L
#define SDMA3_PUB_REG_TYPE1__SDMA3_RD_BURST_CNTL_MASK                                                         0x00000080L
#define SDMA3_PUB_REG_TYPE1__SDMA3_HBM_PAGE_CONFIG_MASK                                                       0x00000100L
#define SDMA3_PUB_REG_TYPE1__SDMA3_UCODE_CHECKSUM_MASK                                                        0x00000200L
#define SDMA3_PUB_REG_TYPE1__SDMA3_F32_CNTL_MASK                                                              0x00000400L
#define SDMA3_PUB_REG_TYPE1__SDMA3_FREEZE_MASK                                                                0x00000800L
#define SDMA3_PUB_REG_TYPE1__SDMA3_PHASE0_QUANTUM_MASK                                                        0x00001000L
#define SDMA3_PUB_REG_TYPE1__SDMA3_PHASE1_QUANTUM_MASK                                                        0x00002000L
#define SDMA3_PUB_REG_TYPE1__SDMA3_EDC_CONFIG_MASK                                                            0x00040000L
#define SDMA3_PUB_REG_TYPE1__SDMA3_BA_THRESHOLD_MASK                                                          0x00080000L
#define SDMA3_PUB_REG_TYPE1__SDMA3_ID_MASK                                                                    0x00100000L
#define SDMA3_PUB_REG_TYPE1__SDMA3_VERSION_MASK                                                               0x00200000L
#define SDMA3_PUB_REG_TYPE1__SDMA3_EDC_COUNTER_MASK                                                           0x00400000L
#define SDMA3_PUB_REG_TYPE1__SDMA3_EDC_COUNTER_CLEAR_MASK                                                     0x00800000L
#define SDMA3_PUB_REG_TYPE1__SDMA3_STATUS2_REG_MASK                                                           0x01000000L
#define SDMA3_PUB_REG_TYPE1__SDMA3_ATOMIC_CNTL_MASK                                                           0x02000000L
#define SDMA3_PUB_REG_TYPE1__SDMA3_ATOMIC_PREOP_LO_MASK                                                       0x04000000L
#define SDMA3_PUB_REG_TYPE1__SDMA3_ATOMIC_PREOP_HI_MASK                                                       0x08000000L
#define SDMA3_PUB_REG_TYPE1__SDMA3_UTCL1_CNTL_MASK                                                            0x10000000L
#define SDMA3_PUB_REG_TYPE1__SDMA3_UTCL1_WATERMK_MASK                                                         0x20000000L
#define SDMA3_PUB_REG_TYPE1__SDMA3_UTCL1_RD_STATUS_MASK                                                       0x40000000L
#define SDMA3_PUB_REG_TYPE1__SDMA3_UTCL1_WR_STATUS_MASK                                                       0x80000000L
//SDMA3_PUB_REG_TYPE2
#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_INV0__SHIFT                                                          0x0
#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_INV1__SHIFT                                                          0x1
#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_INV2__SHIFT                                                          0x2
#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_RD_XNACK0__SHIFT                                                     0x3
#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_RD_XNACK1__SHIFT                                                     0x4
#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_WR_XNACK0__SHIFT                                                     0x5
#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_WR_XNACK1__SHIFT                                                     0x6
#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_TIMEOUT__SHIFT                                                       0x7
#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_PAGE__SHIFT                                                          0x8
#define SDMA3_PUB_REG_TYPE2__SDMA3_RELAX_ORDERING_LUT__SHIFT                                                  0xa
#define SDMA3_PUB_REG_TYPE2__SDMA3_CHICKEN_BITS_2__SHIFT                                                      0xb
#define SDMA3_PUB_REG_TYPE2__SDMA3_STATUS3_REG__SHIFT                                                         0xc
#define SDMA3_PUB_REG_TYPE2__SDMA3_PHYSICAL_ADDR_LO__SHIFT                                                    0xd
#define SDMA3_PUB_REG_TYPE2__SDMA3_PHYSICAL_ADDR_HI__SHIFT                                                    0xe
#define SDMA3_PUB_REG_TYPE2__SDMA3_PHASE2_QUANTUM__SHIFT                                                      0xf
#define SDMA3_PUB_REG_TYPE2__SDMA3_ERROR_LOG__SHIFT                                                           0x10
#define SDMA3_PUB_REG_TYPE2__SDMA3_PUB_DUMMY_REG0__SHIFT                                                      0x11
#define SDMA3_PUB_REG_TYPE2__SDMA3_PUB_DUMMY_REG1__SHIFT                                                      0x12
#define SDMA3_PUB_REG_TYPE2__SDMA3_PUB_DUMMY_REG2__SHIFT                                                      0x13
#define SDMA3_PUB_REG_TYPE2__SDMA3_PUB_DUMMY_REG3__SHIFT                                                      0x14
#define SDMA3_PUB_REG_TYPE2__SDMA3_F32_COUNTER__SHIFT                                                         0x15
#define SDMA3_PUB_REG_TYPE2__SDMA3_PERFCNT_PERFCOUNTER0_CFG__SHIFT                                            0x17
#define SDMA3_PUB_REG_TYPE2__SDMA3_PERFCNT_PERFCOUNTER1_CFG__SHIFT                                            0x18
#define SDMA3_PUB_REG_TYPE2__SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL__SHIFT                                       0x19
#define SDMA3_PUB_REG_TYPE2__SDMA3_PERFCNT_MISC_CNTL__SHIFT                                                   0x1a
#define SDMA3_PUB_REG_TYPE2__SDMA3_CRD_CNTL__SHIFT                                                            0x1b
#define SDMA3_PUB_REG_TYPE2__SDMA3_AQL_STATUS__SHIFT                                                          0x1f
#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_INV0_MASK                                                            0x00000001L
#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_INV1_MASK                                                            0x00000002L
#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_INV2_MASK                                                            0x00000004L
#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_RD_XNACK0_MASK                                                       0x00000008L
#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_RD_XNACK1_MASK                                                       0x00000010L
#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_WR_XNACK0_MASK                                                       0x00000020L
#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_WR_XNACK1_MASK                                                       0x00000040L
#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_TIMEOUT_MASK                                                         0x00000080L
#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_PAGE_MASK                                                            0x00000100L
#define SDMA3_PUB_REG_TYPE2__SDMA3_RELAX_ORDERING_LUT_MASK                                                    0x00000400L
#define SDMA3_PUB_REG_TYPE2__SDMA3_CHICKEN_BITS_2_MASK                                                        0x00000800L
#define SDMA3_PUB_REG_TYPE2__SDMA3_STATUS3_REG_MASK                                                           0x00001000L
#define SDMA3_PUB_REG_TYPE2__SDMA3_PHYSICAL_ADDR_LO_MASK                                                      0x00002000L
#define SDMA3_PUB_REG_TYPE2__SDMA3_PHYSICAL_ADDR_HI_MASK                                                      0x00004000L
#define SDMA3_PUB_REG_TYPE2__SDMA3_PHASE2_QUANTUM_MASK                                                        0x00008000L
#define SDMA3_PUB_REG_TYPE2__SDMA3_ERROR_LOG_MASK                                                             0x00010000L
#define SDMA3_PUB_REG_TYPE2__SDMA3_PUB_DUMMY_REG0_MASK                                                        0x00020000L
#define SDMA3_PUB_REG_TYPE2__SDMA3_PUB_DUMMY_REG1_MASK                                                        0x00040000L
#define SDMA3_PUB_REG_TYPE2__SDMA3_PUB_DUMMY_REG2_MASK                                                        0x00080000L
#define SDMA3_PUB_REG_TYPE2__SDMA3_PUB_DUMMY_REG3_MASK                                                        0x00100000L
#define SDMA3_PUB_REG_TYPE2__SDMA3_F32_COUNTER_MASK                                                           0x00200000L
#define SDMA3_PUB_REG_TYPE2__SDMA3_PERFCNT_PERFCOUNTER0_CFG_MASK                                              0x00800000L
#define SDMA3_PUB_REG_TYPE2__SDMA3_PERFCNT_PERFCOUNTER1_CFG_MASK                                              0x01000000L
#define SDMA3_PUB_REG_TYPE2__SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL_MASK                                         0x02000000L
#define SDMA3_PUB_REG_TYPE2__SDMA3_PERFCNT_MISC_CNTL_MASK                                                     0x04000000L
#define SDMA3_PUB_REG_TYPE2__SDMA3_CRD_CNTL_MASK                                                              0x08000000L
#define SDMA3_PUB_REG_TYPE2__SDMA3_AQL_STATUS_MASK                                                            0x80000000L
//SDMA3_PUB_REG_TYPE3
#define SDMA3_PUB_REG_TYPE3__SDMA3_EA_DBIT_ADDR_DATA__SHIFT                                                   0x0
#define SDMA3_PUB_REG_TYPE3__SDMA3_EA_DBIT_ADDR_INDEX__SHIFT                                                  0x1
#define SDMA3_PUB_REG_TYPE3__SDMA3_TLBI_GCR_CNTL__SHIFT                                                       0x2
#define SDMA3_PUB_REG_TYPE3__SDMA3_TILING_CONFIG__SHIFT                                                       0x3
#define SDMA3_PUB_REG_TYPE3__SDMA3_PERFCOUNTER0_SELECT__SHIFT                                                 0x8
#define SDMA3_PUB_REG_TYPE3__SDMA3_PERFCOUNTER0_SELECT1__SHIFT                                                0x9
#define SDMA3_PUB_REG_TYPE3__SDMA3_PERFCOUNTER0_LO__SHIFT                                                     0xa
#define SDMA3_PUB_REG_TYPE3__SDMA3_PERFCOUNTER0_HI__SHIFT                                                     0xb
#define SDMA3_PUB_REG_TYPE3__SDMA3_PERFCOUNTER1_SELECT__SHIFT                                                 0xc
#define SDMA3_PUB_REG_TYPE3__SDMA3_PERFCOUNTER1_SELECT1__SHIFT                                                0xd
#define SDMA3_PUB_REG_TYPE3__SDMA3_PERFCOUNTER1_LO__SHIFT                                                     0xe
#define SDMA3_PUB_REG_TYPE3__SDMA3_PERFCOUNTER1_HI__SHIFT                                                     0xf
#define SDMA3_PUB_REG_TYPE3__SDMA3_INT_STATUS__SHIFT                                                          0x10
#define SDMA3_PUB_REG_TYPE3__SDMA3_HOLE_ADDR_LO__SHIFT                                                        0x12
#define SDMA3_PUB_REG_TYPE3__SDMA3_HOLE_ADDR_HI__SHIFT                                                        0x13
#define SDMA3_PUB_REG_TYPE3__SDMA3_CLOCK_GATING_REG__SHIFT                                                    0x15
#define SDMA3_PUB_REG_TYPE3__SDMA3_STATUS4_REG__SHIFT                                                         0x16
#define SDMA3_PUB_REG_TYPE3__SDMA3_SCRATCH_RAM_DATA__SHIFT                                                    0x17
#define SDMA3_PUB_REG_TYPE3__SDMA3_SCRATCH_RAM_ADDR__SHIFT                                                    0x18
#define SDMA3_PUB_REG_TYPE3__SDMA3_TIMESTAMP_CNTL__SHIFT                                                      0x19
#define SDMA3_PUB_REG_TYPE3__SDMA3_PERFCNT_PERFCOUNTER_LO__SHIFT                                              0x1a
#define SDMA3_PUB_REG_TYPE3__SDMA3_PERFCNT_PERFCOUNTER_HI__SHIFT                                              0x1b
#define SDMA3_PUB_REG_TYPE3__SDMA3_STATUS5_REG__SHIFT                                                         0x1c
#define SDMA3_PUB_REG_TYPE3__SDMA3_QUEUE_RESET_REQ__SHIFT                                                     0x1d
#define SDMA3_PUB_REG_TYPE3__RESERVED__SHIFT                                                                  0x1e
#define SDMA3_PUB_REG_TYPE3__SDMA3_EA_DBIT_ADDR_DATA_MASK                                                     0x00000001L
#define SDMA3_PUB_REG_TYPE3__SDMA3_EA_DBIT_ADDR_INDEX_MASK                                                    0x00000002L
#define SDMA3_PUB_REG_TYPE3__SDMA3_TLBI_GCR_CNTL_MASK                                                         0x00000004L
#define SDMA3_PUB_REG_TYPE3__SDMA3_TILING_CONFIG_MASK                                                         0x00000008L
#define SDMA3_PUB_REG_TYPE3__SDMA3_PERFCOUNTER0_SELECT_MASK                                                   0x00000100L
#define SDMA3_PUB_REG_TYPE3__SDMA3_PERFCOUNTER0_SELECT1_MASK                                                  0x00000200L
#define SDMA3_PUB_REG_TYPE3__SDMA3_PERFCOUNTER0_LO_MASK                                                       0x00000400L
#define SDMA3_PUB_REG_TYPE3__SDMA3_PERFCOUNTER0_HI_MASK                                                       0x00000800L
#define SDMA3_PUB_REG_TYPE3__SDMA3_PERFCOUNTER1_SELECT_MASK                                                   0x00001000L
#define SDMA3_PUB_REG_TYPE3__SDMA3_PERFCOUNTER1_SELECT1_MASK                                                  0x00002000L
#define SDMA3_PUB_REG_TYPE3__SDMA3_PERFCOUNTER1_LO_MASK                                                       0x00004000L
#define SDMA3_PUB_REG_TYPE3__SDMA3_PERFCOUNTER1_HI_MASK                                                       0x00008000L
#define SDMA3_PUB_REG_TYPE3__SDMA3_INT_STATUS_MASK                                                            0x00010000L
#define SDMA3_PUB_REG_TYPE3__SDMA3_HOLE_ADDR_LO_MASK                                                          0x00040000L
#define SDMA3_PUB_REG_TYPE3__SDMA3_HOLE_ADDR_HI_MASK                                                          0x00080000L
#define SDMA3_PUB_REG_TYPE3__SDMA3_CLOCK_GATING_REG_MASK                                                      0x00200000L
#define SDMA3_PUB_REG_TYPE3__SDMA3_STATUS4_REG_MASK                                                           0x00400000L
#define SDMA3_PUB_REG_TYPE3__SDMA3_SCRATCH_RAM_DATA_MASK                                                      0x00800000L
#define SDMA3_PUB_REG_TYPE3__SDMA3_SCRATCH_RAM_ADDR_MASK                                                      0x01000000L
#define SDMA3_PUB_REG_TYPE3__SDMA3_TIMESTAMP_CNTL_MASK                                                        0x02000000L
#define SDMA3_PUB_REG_TYPE3__SDMA3_PERFCNT_PERFCOUNTER_LO_MASK                                                0x04000000L
#define SDMA3_PUB_REG_TYPE3__SDMA3_PERFCNT_PERFCOUNTER_HI_MASK                                                0x08000000L
#define SDMA3_PUB_REG_TYPE3__SDMA3_STATUS5_REG_MASK                                                           0x10000000L
#define SDMA3_PUB_REG_TYPE3__SDMA3_QUEUE_RESET_REQ_MASK                                                       0x20000000L
#define SDMA3_PUB_REG_TYPE3__RESERVED_MASK                                                                    0xC0000000L
//SDMA3_VM_CNTL
#define SDMA3_VM_CNTL__CMD__SHIFT                                                                             0x0
#define SDMA3_VM_CNTL__CMD_MASK                                                                               0x0000000FL


// addressBlock: gc_gcvmsharedhvdec
//GCMC_VM_FB_SIZE_OFFSET_VF0
#define GCMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT                                                         0x0
#define GCMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT                                                       0x10
#define GCMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK                                                           0x0000FFFFL
#define GCMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK                                                         0xFFFF0000L
//GCMC_VM_FB_SIZE_OFFSET_VF1
#define GCMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT                                                         0x0
#define GCMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT                                                       0x10
#define GCMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK                                                           0x0000FFFFL
#define GCMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK                                                         0xFFFF0000L
//GCMC_VM_FB_SIZE_OFFSET_VF2
#define GCMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT                                                         0x0
#define GCMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT                                                       0x10
#define GCMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK                                                           0x0000FFFFL
#define GCMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK                                                         0xFFFF0000L
//GCMC_VM_FB_SIZE_OFFSET_VF3
#define GCMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT                                                         0x0
#define GCMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT                                                       0x10
#define GCMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK                                                           0x0000FFFFL
#define GCMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK                                                         0xFFFF0000L
//GCMC_VM_FB_SIZE_OFFSET_VF4
#define GCMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT                                                         0x0
#define GCMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT                                                       0x10
#define GCMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK                                                           0x0000FFFFL
#define GCMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK                                                         0xFFFF0000L
//GCMC_VM_FB_SIZE_OFFSET_VF5
#define GCMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT                                                         0x0
#define GCMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT                                                       0x10
#define GCMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK                                                           0x0000FFFFL
#define GCMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK                                                         0xFFFF0000L
//GCMC_VM_FB_SIZE_OFFSET_VF6
#define GCMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT                                                         0x0
#define GCMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT                                                       0x10
#define GCMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK                                                           0x0000FFFFL
#define GCMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK                                                         0xFFFF0000L
//GCMC_VM_FB_SIZE_OFFSET_VF7
#define GCMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT                                                         0x0
#define GCMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT                                                       0x10
#define GCMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK                                                           0x0000FFFFL
#define GCMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK                                                         0xFFFF0000L
//GCMC_VM_FB_SIZE_OFFSET_VF8
#define GCMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT                                                         0x0
#define GCMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT                                                       0x10
#define GCMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK                                                           0x0000FFFFL
#define GCMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK                                                         0xFFFF0000L
//GCMC_VM_FB_SIZE_OFFSET_VF9
#define GCMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT                                                         0x0
#define GCMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT                                                       0x10
#define GCMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK                                                           0x0000FFFFL
#define GCMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK                                                         0xFFFF0000L
//GCMC_VM_FB_SIZE_OFFSET_VF10
#define GCMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT                                                        0x0
#define GCMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT                                                      0x10
#define GCMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK                                                          0x0000FFFFL
#define GCMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
//GCMC_VM_FB_SIZE_OFFSET_VF11
#define GCMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT                                                        0x0
#define GCMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT                                                      0x10
#define GCMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK                                                          0x0000FFFFL
#define GCMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
//GCMC_VM_FB_SIZE_OFFSET_VF12
#define GCMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT                                                        0x0
#define GCMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT                                                      0x10
#define GCMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK                                                          0x0000FFFFL
#define GCMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
//GCMC_VM_FB_SIZE_OFFSET_VF13
#define GCMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT                                                        0x0
#define GCMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT                                                      0x10
#define GCMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK                                                          0x0000FFFFL
#define GCMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
//GCMC_VM_FB_SIZE_OFFSET_VF14
#define GCMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT                                                        0x0
#define GCMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT                                                      0x10
#define GCMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK                                                          0x0000FFFFL
#define GCMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
//GCMC_VM_FB_SIZE_OFFSET_VF15
#define GCMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT                                                        0x0
#define GCMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT                                                      0x10
#define GCMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK                                                          0x0000FFFFL
#define GCMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
//GCMC_VM_FB_SIZE_OFFSET_VF16
#define GCMC_VM_FB_SIZE_OFFSET_VF16__VF_FB_SIZE__SHIFT                                                        0x0
#define GCMC_VM_FB_SIZE_OFFSET_VF16__VF_FB_OFFSET__SHIFT                                                      0x10
#define GCMC_VM_FB_SIZE_OFFSET_VF16__VF_FB_SIZE_MASK                                                          0x0000FFFFL
#define GCMC_VM_FB_SIZE_OFFSET_VF16__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
//GCMC_VM_FB_SIZE_OFFSET_VF17
#define GCMC_VM_FB_SIZE_OFFSET_VF17__VF_FB_SIZE__SHIFT                                                        0x0
#define GCMC_VM_FB_SIZE_OFFSET_VF17__VF_FB_OFFSET__SHIFT                                                      0x10
#define GCMC_VM_FB_SIZE_OFFSET_VF17__VF_FB_SIZE_MASK                                                          0x0000FFFFL
#define GCMC_VM_FB_SIZE_OFFSET_VF17__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
//GCMC_VM_FB_SIZE_OFFSET_VF18
#define GCMC_VM_FB_SIZE_OFFSET_VF18__VF_FB_SIZE__SHIFT                                                        0x0
#define GCMC_VM_FB_SIZE_OFFSET_VF18__VF_FB_OFFSET__SHIFT                                                      0x10
#define GCMC_VM_FB_SIZE_OFFSET_VF18__VF_FB_SIZE_MASK                                                          0x0000FFFFL
#define GCMC_VM_FB_SIZE_OFFSET_VF18__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
//GCMC_VM_FB_SIZE_OFFSET_VF19
#define GCMC_VM_FB_SIZE_OFFSET_VF19__VF_FB_SIZE__SHIFT                                                        0x0
#define GCMC_VM_FB_SIZE_OFFSET_VF19__VF_FB_OFFSET__SHIFT                                                      0x10
#define GCMC_VM_FB_SIZE_OFFSET_VF19__VF_FB_SIZE_MASK                                                          0x0000FFFFL
#define GCMC_VM_FB_SIZE_OFFSET_VF19__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
//GCMC_VM_FB_SIZE_OFFSET_VF20
#define GCMC_VM_FB_SIZE_OFFSET_VF20__VF_FB_SIZE__SHIFT                                                        0x0
#define GCMC_VM_FB_SIZE_OFFSET_VF20__VF_FB_OFFSET__SHIFT                                                      0x10
#define GCMC_VM_FB_SIZE_OFFSET_VF20__VF_FB_SIZE_MASK                                                          0x0000FFFFL
#define GCMC_VM_FB_SIZE_OFFSET_VF20__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
//GCMC_VM_FB_SIZE_OFFSET_VF21
#define GCMC_VM_FB_SIZE_OFFSET_VF21__VF_FB_SIZE__SHIFT                                                        0x0
#define GCMC_VM_FB_SIZE_OFFSET_VF21__VF_FB_OFFSET__SHIFT                                                      0x10
#define GCMC_VM_FB_SIZE_OFFSET_VF21__VF_FB_SIZE_MASK                                                          0x0000FFFFL
#define GCMC_VM_FB_SIZE_OFFSET_VF21__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
//GCMC_VM_FB_SIZE_OFFSET_VF22
#define GCMC_VM_FB_SIZE_OFFSET_VF22__VF_FB_SIZE__SHIFT                                                        0x0
#define GCMC_VM_FB_SIZE_OFFSET_VF22__VF_FB_OFFSET__SHIFT                                                      0x10
#define GCMC_VM_FB_SIZE_OFFSET_VF22__VF_FB_SIZE_MASK                                                          0x0000FFFFL
#define GCMC_VM_FB_SIZE_OFFSET_VF22__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
//GCMC_VM_FB_SIZE_OFFSET_VF23
#define GCMC_VM_FB_SIZE_OFFSET_VF23__VF_FB_SIZE__SHIFT                                                        0x0
#define GCMC_VM_FB_SIZE_OFFSET_VF23__VF_FB_OFFSET__SHIFT                                                      0x10
#define GCMC_VM_FB_SIZE_OFFSET_VF23__VF_FB_SIZE_MASK                                                          0x0000FFFFL
#define GCMC_VM_FB_SIZE_OFFSET_VF23__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
//GCMC_VM_FB_SIZE_OFFSET_VF24
#define GCMC_VM_FB_SIZE_OFFSET_VF24__VF_FB_SIZE__SHIFT                                                        0x0
#define GCMC_VM_FB_SIZE_OFFSET_VF24__VF_FB_OFFSET__SHIFT                                                      0x10
#define GCMC_VM_FB_SIZE_OFFSET_VF24__VF_FB_SIZE_MASK                                                          0x0000FFFFL
#define GCMC_VM_FB_SIZE_OFFSET_VF24__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
//GCMC_VM_FB_SIZE_OFFSET_VF25
#define GCMC_VM_FB_SIZE_OFFSET_VF25__VF_FB_SIZE__SHIFT                                                        0x0
#define GCMC_VM_FB_SIZE_OFFSET_VF25__VF_FB_OFFSET__SHIFT                                                      0x10
#define GCMC_VM_FB_SIZE_OFFSET_VF25__VF_FB_SIZE_MASK                                                          0x0000FFFFL
#define GCMC_VM_FB_SIZE_OFFSET_VF25__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
//GCMC_VM_FB_SIZE_OFFSET_VF26
#define GCMC_VM_FB_SIZE_OFFSET_VF26__VF_FB_SIZE__SHIFT                                                        0x0
#define GCMC_VM_FB_SIZE_OFFSET_VF26__VF_FB_OFFSET__SHIFT                                                      0x10
#define GCMC_VM_FB_SIZE_OFFSET_VF26__VF_FB_SIZE_MASK                                                          0x0000FFFFL
#define GCMC_VM_FB_SIZE_OFFSET_VF26__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
//GCMC_VM_FB_SIZE_OFFSET_VF27
#define GCMC_VM_FB_SIZE_OFFSET_VF27__VF_FB_SIZE__SHIFT                                                        0x0
#define GCMC_VM_FB_SIZE_OFFSET_VF27__VF_FB_OFFSET__SHIFT                                                      0x10
#define GCMC_VM_FB_SIZE_OFFSET_VF27__VF_FB_SIZE_MASK                                                          0x0000FFFFL
#define GCMC_VM_FB_SIZE_OFFSET_VF27__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
//GCMC_VM_FB_SIZE_OFFSET_VF28
#define GCMC_VM_FB_SIZE_OFFSET_VF28__VF_FB_SIZE__SHIFT                                                        0x0
#define GCMC_VM_FB_SIZE_OFFSET_VF28__VF_FB_OFFSET__SHIFT                                                      0x10
#define GCMC_VM_FB_SIZE_OFFSET_VF28__VF_FB_SIZE_MASK                                                          0x0000FFFFL
#define GCMC_VM_FB_SIZE_OFFSET_VF28__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
//GCMC_VM_FB_SIZE_OFFSET_VF29
#define GCMC_VM_FB_SIZE_OFFSET_VF29__VF_FB_SIZE__SHIFT                                                        0x0
#define GCMC_VM_FB_SIZE_OFFSET_VF29__VF_FB_OFFSET__SHIFT                                                      0x10
#define GCMC_VM_FB_SIZE_OFFSET_VF29__VF_FB_SIZE_MASK                                                          0x0000FFFFL
#define GCMC_VM_FB_SIZE_OFFSET_VF29__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
//GCMC_VM_FB_SIZE_OFFSET_VF30
#define GCMC_VM_FB_SIZE_OFFSET_VF30__VF_FB_SIZE__SHIFT                                                        0x0
#define GCMC_VM_FB_SIZE_OFFSET_VF30__VF_FB_OFFSET__SHIFT                                                      0x10
#define GCMC_VM_FB_SIZE_OFFSET_VF30__VF_FB_SIZE_MASK                                                          0x0000FFFFL
#define GCMC_VM_FB_SIZE_OFFSET_VF30__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
//GCMC_VM_FB_SIZE_OFFSET_VF31
#define GCMC_VM_FB_SIZE_OFFSET_VF31__VF_FB_SIZE__SHIFT                                                        0x0
#define GCMC_VM_FB_SIZE_OFFSET_VF31__VF_FB_OFFSET__SHIFT                                                      0x10
#define GCMC_VM_FB_SIZE_OFFSET_VF31__VF_FB_SIZE_MASK                                                          0x0000FFFFL
#define GCMC_VM_FB_SIZE_OFFSET_VF31__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
//GCVM_IOMMU_MMIO_CNTRL_1
#define GCVM_IOMMU_MMIO_CNTRL_1__MARC_EN__SHIFT                                                               0x8
#define GCVM_IOMMU_MMIO_CNTRL_1__MARC_EN_MASK                                                                 0x00000100L
//GCMC_VM_MARC_BASE_LO_0
#define GCMC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT                                                         0xc
#define GCMC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK                                                           0xFFFFF000L
//GCMC_VM_MARC_BASE_LO_1
#define GCMC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT                                                         0xc
#define GCMC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK                                                           0xFFFFF000L
//GCMC_VM_MARC_BASE_LO_2
#define GCMC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT                                                         0xc
#define GCMC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK                                                           0xFFFFF000L
//GCMC_VM_MARC_BASE_LO_3
#define GCMC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT                                                         0xc
#define GCMC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK                                                           0xFFFFF000L
//GCMC_VM_MARC_BASE_HI_0
#define GCMC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT                                                         0x0
#define GCMC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK                                                           0x000FFFFFL
//GCMC_VM_MARC_BASE_HI_1
#define GCMC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT                                                         0x0
#define GCMC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK                                                           0x000FFFFFL
//GCMC_VM_MARC_BASE_HI_2
#define GCMC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT                                                         0x0
#define GCMC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK                                                           0x000FFFFFL
//GCMC_VM_MARC_BASE_HI_3
#define GCMC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT                                                         0x0
#define GCMC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK                                                           0x000FFFFFL
//GCMC_VM_MARC_RELOC_LO_0
#define GCMC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT                                                         0x0
#define GCMC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT                                                       0x1
#define GCMC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT                                                       0xc
#define GCMC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK                                                           0x00000001L
#define GCMC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK                                                         0x00000002L
#define GCMC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK                                                         0xFFFFF000L
//GCMC_VM_MARC_RELOC_LO_1
#define GCMC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT                                                         0x0
#define GCMC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT                                                       0x1
#define GCMC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT                                                       0xc
#define GCMC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK                                                           0x00000001L
#define GCMC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK                                                         0x00000002L
#define GCMC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK                                                         0xFFFFF000L
//GCMC_VM_MARC_RELOC_LO_2
#define GCMC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT                                                         0x0
#define GCMC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT                                                       0x1
#define GCMC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT                                                       0xc
#define GCMC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK                                                           0x00000001L
#define GCMC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK                                                         0x00000002L
#define GCMC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK                                                         0xFFFFF000L
//GCMC_VM_MARC_RELOC_LO_3
#define GCMC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT                                                         0x0
#define GCMC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT                                                       0x1
#define GCMC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT                                                       0xc
#define GCMC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK                                                           0x00000001L
#define GCMC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK                                                         0x00000002L
#define GCMC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK                                                         0xFFFFF000L
//GCMC_VM_MARC_RELOC_HI_0
#define GCMC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT                                                       0x0
#define GCMC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK                                                         0x000FFFFFL
//GCMC_VM_MARC_RELOC_HI_1
#define GCMC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT                                                       0x0
#define GCMC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK                                                         0x000FFFFFL
//GCMC_VM_MARC_RELOC_HI_2
#define GCMC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT                                                       0x0
#define GCMC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK                                                         0x000FFFFFL
//GCMC_VM_MARC_RELOC_HI_3
#define GCMC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT                                                       0x0
#define GCMC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK                                                         0x000FFFFFL
//GCMC_VM_MARC_LEN_LO_0
#define GCMC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT                                                           0xc
#define GCMC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK                                                             0xFFFFF000L
//GCMC_VM_MARC_LEN_LO_1
#define GCMC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT                                                           0xc
#define GCMC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK                                                             0xFFFFF000L
//GCMC_VM_MARC_LEN_LO_2
#define GCMC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT                                                           0xc
#define GCMC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK                                                             0xFFFFF000L
//GCMC_VM_MARC_LEN_LO_3
#define GCMC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT                                                           0xc
#define GCMC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK                                                             0xFFFFF000L
//GCMC_VM_MARC_LEN_HI_0
#define GCMC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT                                                           0x0
#define GCMC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK                                                             0x000FFFFFL
//GCMC_VM_MARC_LEN_HI_1
#define GCMC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT                                                           0x0
#define GCMC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK                                                             0x000FFFFFL
//GCMC_VM_MARC_LEN_HI_2
#define GCMC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT                                                           0x0
#define GCMC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK                                                             0x000FFFFFL
//GCMC_VM_MARC_LEN_HI_3
#define GCMC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT                                                           0x0
#define GCMC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK                                                             0x000FFFFFL
//GCVM_IOMMU_CONTROL_REGISTER
#define GCVM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT                                                           0x0
#define GCVM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK                                                             0x00000001L
//GCVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER
#define GCVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT                                0xd
#define GCVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK                                  0x00002000L
//GCMC_VM_XGMI_GPUIOV_ENABLE
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0__SHIFT                                                         0x0
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1__SHIFT                                                         0x1
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2__SHIFT                                                         0x2
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3__SHIFT                                                         0x3
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4__SHIFT                                                         0x4
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5__SHIFT                                                         0x5
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6__SHIFT                                                         0x6
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7__SHIFT                                                         0x7
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF8__SHIFT                                                         0x8
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF9__SHIFT                                                         0x9
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF10__SHIFT                                                        0xa
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF11__SHIFT                                                        0xb
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF12__SHIFT                                                        0xc
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF13__SHIFT                                                        0xd
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF14__SHIFT                                                        0xe
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF15__SHIFT                                                        0xf
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF16__SHIFT                                                        0x10
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF17__SHIFT                                                        0x11
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF18__SHIFT                                                        0x12
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF19__SHIFT                                                        0x13
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF20__SHIFT                                                        0x14
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF21__SHIFT                                                        0x15
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF22__SHIFT                                                        0x16
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF23__SHIFT                                                        0x17
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF24__SHIFT                                                        0x18
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF25__SHIFT                                                        0x19
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF26__SHIFT                                                        0x1a
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF27__SHIFT                                                        0x1b
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF28__SHIFT                                                        0x1c
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF29__SHIFT                                                        0x1d
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF30__SHIFT                                                        0x1e
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF__SHIFT                                                          0x1f
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0_MASK                                                           0x00000001L
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1_MASK                                                           0x00000002L
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2_MASK                                                           0x00000004L
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3_MASK                                                           0x00000008L
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4_MASK                                                           0x00000010L
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5_MASK                                                           0x00000020L
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6_MASK                                                           0x00000040L
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7_MASK                                                           0x00000080L
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF8_MASK                                                           0x00000100L
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF9_MASK                                                           0x00000200L
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF10_MASK                                                          0x00000400L
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF11_MASK                                                          0x00000800L
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF12_MASK                                                          0x00001000L
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF13_MASK                                                          0x00002000L
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF14_MASK                                                          0x00004000L
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF15_MASK                                                          0x00008000L
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF16_MASK                                                          0x00010000L
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF17_MASK                                                          0x00020000L
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF18_MASK                                                          0x00040000L
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF19_MASK                                                          0x00080000L
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF20_MASK                                                          0x00100000L
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF21_MASK                                                          0x00200000L
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF22_MASK                                                          0x00400000L
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF23_MASK                                                          0x00800000L
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF24_MASK                                                          0x01000000L
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF25_MASK                                                          0x02000000L
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF26_MASK                                                          0x04000000L
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF27_MASK                                                          0x08000000L
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF28_MASK                                                          0x10000000L
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF29_MASK                                                          0x20000000L
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF30_MASK                                                          0x40000000L
#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF_MASK                                                            0x80000000L


// addressBlock: gc_pspdec
#define CPG_PSP_DEBUG__GPA_OVERRIDE__SHIFT                                                                    0x3
#define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK                                                                      0x00000008L
#define CPC_PSP_DEBUG__GPA_OVERRIDE__SHIFT                                                                    0x3
#define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK                                                                      0x00000008L
//GRBM_SEC_CNTL
//RLC_FWL_FIRST_VIOL_ADDR
#define RLC_FWL_FIRST_VIOL_ADDR__VIOL_ADDR__SHIFT                                                             0x0
#define RLC_FWL_FIRST_VIOL_ADDR__VIOL_APERTURE_ID__SHIFT                                                      0x12
#define RLC_FWL_FIRST_VIOL_ADDR__VIOL_OP__SHIFT                                                               0x1e
#define RLC_FWL_FIRST_VIOL_ADDR__RESERVED__SHIFT                                                              0x1f
#define RLC_FWL_FIRST_VIOL_ADDR__VIOL_ADDR_MASK                                                               0x0003FFFFL
#define RLC_FWL_FIRST_VIOL_ADDR__VIOL_APERTURE_ID_MASK                                                        0x3FFC0000L
#define RLC_FWL_FIRST_VIOL_ADDR__VIOL_OP_MASK                                                                 0x40000000L
#define RLC_FWL_FIRST_VIOL_ADDR__RESERVED_MASK                                                                0x80000000L
//RLC_SRM_FWL_FIRST_VIOL_ADDR
#define RLC_SRM_FWL_FIRST_VIOL_ADDR__VIOL_ADDR__SHIFT                                                         0x0
#define RLC_SRM_FWL_FIRST_VIOL_ADDR__VIOL_OP__SHIFT                                                           0x12
#define RLC_SRM_FWL_FIRST_VIOL_ADDR__RESERVED__SHIFT                                                          0x13
#define RLC_SRM_FWL_FIRST_VIOL_ADDR__VIOL_ADDR_MASK                                                           0x0003FFFFL
#define RLC_SRM_FWL_FIRST_VIOL_ADDR__VIOL_OP_MASK                                                             0x00040000L
#define RLC_SRM_FWL_FIRST_VIOL_ADDR__RESERVED_MASK                                                            0xFFF80000L


// addressBlock: gc_gcvml2pspdec
//GCVM_L2_ID_CTRL0
#define GCVM_L2_ID_CTRL0__VMID0_EN__SHIFT                                                                     0x0
#define GCVM_L2_ID_CTRL0__VMID1_EN__SHIFT                                                                     0x10
#define GCVM_L2_ID_CTRL0__VMID0_EN_MASK                                                                       0x0000FFFFL
#define GCVM_L2_ID_CTRL0__VMID1_EN_MASK                                                                       0xFFFF0000L
//GCVM_L2_ID_CTRL1
#define GCVM_L2_ID_CTRL1__VMID0_EN__SHIFT                                                                     0x0
#define GCVM_L2_ID_CTRL1__VMID1_EN__SHIFT                                                                     0x10
#define GCVM_L2_ID_CTRL1__VMID0_EN_MASK                                                                       0x0000FFFFL
#define GCVM_L2_ID_CTRL1__VMID1_EN_MASK                                                                       0xFFFF0000L
//GCVM_L2_ID_CTRL2
#define GCVM_L2_ID_CTRL2__VMID0_EN__SHIFT                                                                     0x0
#define GCVM_L2_ID_CTRL2__VMID1_EN__SHIFT                                                                     0x10
#define GCVM_L2_ID_CTRL2__VMID0_EN_MASK                                                                       0x0000FFFFL
#define GCVM_L2_ID_CTRL2__VMID1_EN_MASK                                                                       0xFFFF0000L
//GCVM_L2_ID_CTRL3
#define GCVM_L2_ID_CTRL3__VMID0_EN__SHIFT                                                                     0x0
#define GCVM_L2_ID_CTRL3__VMID1_EN__SHIFT                                                                     0x10
#define GCVM_L2_ID_CTRL3__VMID0_EN_MASK                                                                       0x0000FFFFL
#define GCVM_L2_ID_CTRL3__VMID1_EN_MASK                                                                       0xFFFF0000L
//GCVM_L2_ID_CTRL4
#define GCVM_L2_ID_CTRL4__VMID0_EN__SHIFT                                                                     0x0
#define GCVM_L2_ID_CTRL4__VMID1_EN__SHIFT                                                                     0x10
#define GCVM_L2_ID_CTRL4__VMID0_EN_MASK                                                                       0x0000FFFFL
#define GCVM_L2_ID_CTRL4__VMID1_EN_MASK                                                                       0xFFFF0000L
//GCVM_L2_ID_CTRL5
#define GCVM_L2_ID_CTRL5__VMID0_EN__SHIFT                                                                     0x0
#define GCVM_L2_ID_CTRL5__VMID1_EN__SHIFT                                                                     0x10
#define GCVM_L2_ID_CTRL5__VMID0_EN_MASK                                                                       0x0000FFFFL
#define GCVM_L2_ID_CTRL5__VMID1_EN_MASK                                                                       0xFFFF0000L
//GCVM_L2_ID_CTRL6
#define GCVM_L2_ID_CTRL6__VMID0_EN__SHIFT                                                                     0x0
#define GCVM_L2_ID_CTRL6__VMID1_EN__SHIFT                                                                     0x10
#define GCVM_L2_ID_CTRL6__VMID0_EN_MASK                                                                       0x0000FFFFL
#define GCVM_L2_ID_CTRL6__VMID1_EN_MASK                                                                       0xFFFF0000L
//GCVM_L2_ID_CTRL7
#define GCVM_L2_ID_CTRL7__VMID0_EN__SHIFT                                                                     0x0
#define GCVM_L2_ID_CTRL7__VMID1_EN__SHIFT                                                                     0x10
#define GCVM_L2_ID_CTRL7__VMID0_EN_MASK                                                                       0x0000FFFFL
#define GCVM_L2_ID_CTRL7__VMID1_EN_MASK                                                                       0xFFFF0000L
//GCVM_L2_ID_CTRL_HI
#define GCVM_L2_ID_CTRL_HI__VMID_EN_HI__SHIFT                                                                 0x0
#define GCVM_L2_ID_CTRL_HI__VMID_EN_HI_MASK                                                                   0x0000FFFFL
//GCVM_L2_ID_STATUS
#define GCVM_L2_ID_STATUS__VMID_FAULT__SHIFT                                                                  0x0
#define GCVM_L2_ID_STATUS__CLIENTID_FAULT__SHIFT                                                              0x4
#define GCVM_L2_ID_STATUS__GRPID_FAULT__SHIFT                                                                 0xd
#define GCVM_L2_ID_STATUS__VMID_INTR_ON__SHIFT                                                                0x1f
#define GCVM_L2_ID_STATUS__VMID_FAULT_MASK                                                                    0x0000000FL
#define GCVM_L2_ID_STATUS__CLIENTID_FAULT_MASK                                                                0x00001FF0L
#define GCVM_L2_ID_STATUS__GRPID_FAULT_MASK                                                                   0x0001E000L
#define GCVM_L2_ID_STATUS__VMID_INTR_ON_MASK                                                                  0x80000000L
//GCUTCL2_TRANSLATION_BYPASS_BY_VMID
#define GCUTCL2_TRANSLATION_BYPASS_BY_VMID__TRANS_BYPASS_VMIDS__SHIFT                                         0x0
#define GCUTCL2_TRANSLATION_BYPASS_BY_VMID__GPA_MODE_VMIDS__SHIFT                                             0x10
#define GCUTCL2_TRANSLATION_BYPASS_BY_VMID__TRANS_BYPASS_VMIDS_MASK                                           0x0000FFFFL
#define GCUTCL2_TRANSLATION_BYPASS_BY_VMID__GPA_MODE_VMIDS_MASK                                               0xFFFF0000L
//GCVM_IOMMU_GPU_HOST_TRANSLATION_ENABLE
#define GCVM_IOMMU_GPU_HOST_TRANSLATION_ENABLE__GPU_HOST_TRANSLATION_ENABLE__SHIFT                            0x0
#define GCVM_IOMMU_GPU_HOST_TRANSLATION_ENABLE__GPU_HOST_TRANSLATION_ENABLE_MASK                              0x00000001L
//GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO
#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR__SHIFT                                           0x0
#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR_MASK                                             0xFFFFFFFFL
//GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI
#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR__SHIFT                                           0x0
#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID__SHIFT                                           0x4
#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID__SHIFT                                           0x8
#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF__SHIFT                                             0xd
#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA__SHIFT                                            0xe
#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM__SHIFT                                        0x10
#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM__SHIFT                                        0x11
#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM__SHIFT                                        0x12
#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID__SHIFT                                      0x13
#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ__SHIFT                                            0x1f
#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR_MASK                                             0x0000000FL
#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID_MASK                                             0x000000F0L
#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID_MASK                                             0x00001F00L
#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF_MASK                                               0x00002000L
#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA_MASK                                              0x0000C000L
#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM_MASK                                          0x00010000L
#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM_MASK                                          0x00020000L
#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM_MASK                                          0x00040000L
#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID_MASK                                        0x0FF80000L
#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ_MASK                                              0x80000000L
//GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO
#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR__SHIFT                                          0x0
#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR_MASK                                            0xFFFFFFFFL
//GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI
#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR__SHIFT                                          0x0
#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS__SHIFT                                         0x4
#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE__SHIFT                                 0x7
#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP__SHIFT                                         0xd
#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA__SHIFT                                           0xe
#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO__SHIFT                                            0xf
#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE__SHIFT                                        0x11
#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE__SHIFT                                         0x12
#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG__SHIFT                                        0x15
#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK__SHIFT                                          0x16
#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK__SHIFT                                           0x1f
#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR_MASK                                            0x0000000FL
#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS_MASK                                           0x00000070L
#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE_MASK                                   0x00001F80L
#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP_MASK                                           0x00002000L
#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA_MASK                                             0x00004000L
#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO_MASK                                              0x00008000L
#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE_MASK                                          0x00020000L
#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE_MASK                                           0x001C0000L
#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG_MASK                                          0x00200000L
#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK_MASK                                            0x00C00000L
#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK_MASK                                             0x80000000L


// addressBlock: gc_sdma2_sdma2dec
//SDMA2_DEC_START
#define SDMA2_DEC_START__START__SHIFT                                                                         0x0
#define SDMA2_DEC_START__START_MASK                                                                           0xFFFFFFFFL
//SDMA2_GLOBAL_TIMESTAMP_LO
#define SDMA2_GLOBAL_TIMESTAMP_LO__DATA__SHIFT                                                                0x0
#define SDMA2_GLOBAL_TIMESTAMP_LO__DATA_MASK                                                                  0xFFFFFFFFL
//SDMA2_GLOBAL_TIMESTAMP_HI
#define SDMA2_GLOBAL_TIMESTAMP_HI__DATA__SHIFT                                                                0x0
#define SDMA2_GLOBAL_TIMESTAMP_HI__DATA_MASK                                                                  0xFFFFFFFFL
//SDMA2_PG_CNTL
#define SDMA2_PG_CNTL__CMD__SHIFT                                                                             0x0
#define SDMA2_PG_CNTL__STATUS__SHIFT                                                                          0x10
#define SDMA2_PG_CNTL__CMD_MASK                                                                               0x0000000FL
#define SDMA2_PG_CNTL__STATUS_MASK                                                                            0x000F0000L
//SDMA2_PG_CTX_LO
#define SDMA2_PG_CTX_LO__ADDR__SHIFT                                                                          0x0
#define SDMA2_PG_CTX_LO__ADDR_MASK                                                                            0xFFFFFFFFL
//SDMA2_PG_CTX_HI
#define SDMA2_PG_CTX_HI__ADDR__SHIFT                                                                          0x0
#define SDMA2_PG_CTX_HI__ADDR_MASK                                                                            0xFFFFFFFFL
//SDMA2_PG_CTX_CNTL
#define SDMA2_PG_CTX_CNTL__VMID__SHIFT                                                                        0x4
#define SDMA2_PG_CTX_CNTL__VMID_MASK                                                                          0x000000F0L
//SDMA2_POWER_CNTL
#define SDMA2_POWER_CNTL__PG_CNTL_ENABLE__SHIFT                                                               0x0
#define SDMA2_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT                                                          0x1
#define SDMA2_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT                                                         0x2
#define SDMA2_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME__SHIFT                                                   0x3
#define SDMA2_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT                                                           0x8
#define SDMA2_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME__SHIFT                                                  0x1a
#define SDMA2_POWER_CNTL__PG_CNTL_ENABLE_MASK                                                                 0x00000001L
#define SDMA2_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK                                                            0x00000002L
#define SDMA2_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK                                                           0x00000004L
#define SDMA2_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK                                                     0x000000F8L
#define SDMA2_POWER_CNTL__MEM_POWER_OVERRIDE_MASK                                                             0x00000100L
#define SDMA2_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK                                                    0xFC000000L
//SDMA2_CLK_CTRL
#define SDMA2_CLK_CTRL__ON_DELAY__SHIFT                                                                       0x0
#define SDMA2_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                                 0x4
#define SDMA2_CLK_CTRL__RESERVED_24_12__SHIFT                                                                 0xc
#define SDMA2_CLK_CTRL__CGCG_EN_OVERRIDE__SHIFT                                                               0x19
#define SDMA2_CLK_CTRL__SOFT_OVERRIDE4__SHIFT                                                                 0x1a
#define SDMA2_CLK_CTRL__SOFT_OVERRIDE3__SHIFT                                                                 0x1b
#define SDMA2_CLK_CTRL__SOFT_OVERRIDE2__SHIFT                                                                 0x1c
#define SDMA2_CLK_CTRL__SOFT_OVERRIDE1__SHIFT                                                                 0x1d
#define SDMA2_CLK_CTRL__SOFT_OVERRIDE0__SHIFT                                                                 0x1e
#define SDMA2_CLK_CTRL__SOFT_OVERRIDER_REG__SHIFT                                                             0x1f
#define SDMA2_CLK_CTRL__ON_DELAY_MASK                                                                         0x0000000FL
#define SDMA2_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                   0x00000FF0L
#define SDMA2_CLK_CTRL__RESERVED_24_12_MASK                                                                   0x01FFF000L
#define SDMA2_CLK_CTRL__CGCG_EN_OVERRIDE_MASK                                                                 0x02000000L
#define SDMA2_CLK_CTRL__SOFT_OVERRIDE4_MASK                                                                   0x04000000L
#define SDMA2_CLK_CTRL__SOFT_OVERRIDE3_MASK                                                                   0x08000000L
#define SDMA2_CLK_CTRL__SOFT_OVERRIDE2_MASK                                                                   0x10000000L
#define SDMA2_CLK_CTRL__SOFT_OVERRIDE1_MASK                                                                   0x20000000L
#define SDMA2_CLK_CTRL__SOFT_OVERRIDE0_MASK                                                                   0x40000000L
#define SDMA2_CLK_CTRL__SOFT_OVERRIDER_REG_MASK                                                               0x80000000L
//SDMA2_CNTL
#define SDMA2_CNTL__TRAP_ENABLE__SHIFT                                                                        0x0
#define SDMA2_CNTL__UTC_L1_ENABLE__SHIFT                                                                      0x1
#define SDMA2_CNTL__SEM_WAIT_INT_ENABLE__SHIFT                                                                0x2
#define SDMA2_CNTL__DATA_SWAP_ENABLE__SHIFT                                                                   0x3
#define SDMA2_CNTL__FENCE_SWAP_ENABLE__SHIFT                                                                  0x4
#define SDMA2_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                              0x5
#define SDMA2_CNTL__PAGE_INT_ENABLE__SHIFT                                                                    0x7
#define SDMA2_CNTL__CH_PERFCNT_ENABLE__SHIFT                                                                  0x10
#define SDMA2_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT                                                          0x11
#define SDMA2_CNTL__AUTO_CTXSW_ENABLE__SHIFT                                                                  0x12
#define SDMA2_CNTL__CTXEMPTY_INT_ENABLE__SHIFT                                                                0x1c
#define SDMA2_CNTL__FROZEN_INT_ENABLE__SHIFT                                                                  0x1d
#define SDMA2_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT                                                              0x1e
#define SDMA2_CNTL__TRAP_ENABLE_MASK                                                                          0x00000001L
#define SDMA2_CNTL__UTC_L1_ENABLE_MASK                                                                        0x00000002L
#define SDMA2_CNTL__SEM_WAIT_INT_ENABLE_MASK                                                                  0x00000004L
#define SDMA2_CNTL__DATA_SWAP_ENABLE_MASK                                                                     0x00000008L
#define SDMA2_CNTL__FENCE_SWAP_ENABLE_MASK                                                                    0x00000010L
#define SDMA2_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                                0x00000020L
#define SDMA2_CNTL__PAGE_INT_ENABLE_MASK                                                                      0x00000080L
#define SDMA2_CNTL__CH_PERFCNT_ENABLE_MASK                                                                    0x00010000L
#define SDMA2_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK                                                            0x00020000L
#define SDMA2_CNTL__AUTO_CTXSW_ENABLE_MASK                                                                    0x00040000L
#define SDMA2_CNTL__CTXEMPTY_INT_ENABLE_MASK                                                                  0x10000000L
#define SDMA2_CNTL__FROZEN_INT_ENABLE_MASK                                                                    0x20000000L
#define SDMA2_CNTL__IB_PREEMPT_INT_ENABLE_MASK                                                                0x40000000L
//SDMA2_CHICKEN_BITS
#define SDMA2_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT                                                     0x0
#define SDMA2_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT                                                 0x1
#define SDMA2_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT                                        0x2
#define SDMA2_CHICKEN_BITS__SOFT_OVERRIDE_DCGE__SHIFT                                                         0x4
#define SDMA2_CHICKEN_BITS__SOFT_OVERRIDE_SDMA_GRBM_FGCG__SHIFT                                               0x5
#define SDMA2_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT                                                         0x8
#define SDMA2_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT                                                     0xa
#define SDMA2_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT                                                        0x10
#define SDMA2_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT                                                           0x11
#define SDMA2_CHICKEN_BITS__T2L_256B_ENABLE__SHIFT                                                            0x12
#define SDMA2_CHICKEN_BITS__GCR_FGCG_ENABLE__SHIFT                                                            0x13
#define SDMA2_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT                                                         0x14
#define SDMA2_CHICKEN_BITS__CH_FGCG_ENABLE__SHIFT                                                             0x15
#define SDMA2_CHICKEN_BITS__UTCL2_INVREQ_FGCG_ENABLE__SHIFT                                                   0x16
#define SDMA2_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT                                                           0x17
#define SDMA2_CHICKEN_BITS__UTCL1_FGCG_ENABLE__SHIFT                                                          0x18
#define SDMA2_CHICKEN_BITS__TIME_BASED_QOS__SHIFT                                                             0x19
#define SDMA2_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT                                                         0x1a
#define SDMA2_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT                                                         0x1c
#define SDMA2_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT                                                         0x1e
#define SDMA2_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK                                                       0x00000001L
#define SDMA2_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK                                                   0x00000002L
#define SDMA2_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK                                          0x00000004L
#define SDMA2_CHICKEN_BITS__SOFT_OVERRIDE_DCGE_MASK                                                           0x00000010L
#define SDMA2_CHICKEN_BITS__SOFT_OVERRIDE_SDMA_GRBM_FGCG_MASK                                                 0x00000020L
#define SDMA2_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK                                                           0x00000300L
#define SDMA2_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK                                                       0x00001C00L
#define SDMA2_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK                                                          0x00010000L
#define SDMA2_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK                                                             0x00020000L
#define SDMA2_CHICKEN_BITS__T2L_256B_ENABLE_MASK                                                              0x00040000L
#define SDMA2_CHICKEN_BITS__GCR_FGCG_ENABLE_MASK                                                              0x00080000L
#define SDMA2_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK                                                           0x00100000L
#define SDMA2_CHICKEN_BITS__CH_FGCG_ENABLE_MASK                                                               0x00200000L
#define SDMA2_CHICKEN_BITS__UTCL2_INVREQ_FGCG_ENABLE_MASK                                                     0x00400000L
#define SDMA2_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK                                                             0x00800000L
#define SDMA2_CHICKEN_BITS__UTCL1_FGCG_ENABLE_MASK                                                            0x01000000L
#define SDMA2_CHICKEN_BITS__TIME_BASED_QOS_MASK                                                               0x02000000L
#define SDMA2_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK                                                           0x0C000000L
#define SDMA2_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK                                                           0x30000000L
#define SDMA2_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK                                                           0xC0000000L
//SDMA2_GB_ADDR_CONFIG
#define SDMA2_GB_ADDR_CONFIG__NUM_PIPES__SHIFT                                                                0x0
#define SDMA2_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT                                                     0x3
#define SDMA2_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                     0x6
#define SDMA2_GB_ADDR_CONFIG__NUM_PKRS__SHIFT                                                                 0x8
#define SDMA2_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT                                                       0x13
#define SDMA2_GB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT                                                            0x1a
#define SDMA2_GB_ADDR_CONFIG__NUM_PIPES_MASK                                                                  0x00000007L
#define SDMA2_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK                                                       0x00000038L
#define SDMA2_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                       0x000000C0L
#define SDMA2_GB_ADDR_CONFIG__NUM_PKRS_MASK                                                                   0x00000700L
#define SDMA2_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK                                                         0x00180000L
#define SDMA2_GB_ADDR_CONFIG__NUM_RB_PER_SE_MASK                                                              0x0C000000L
//SDMA2_GB_ADDR_CONFIG_READ
#define SDMA2_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT                                                           0x0
#define SDMA2_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT                                                0x3
#define SDMA2_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT                                                0x6
#define SDMA2_GB_ADDR_CONFIG_READ__NUM_PKRS__SHIFT                                                            0x8
#define SDMA2_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT                                                  0x13
#define SDMA2_GB_ADDR_CONFIG_READ__NUM_RB_PER_SE__SHIFT                                                       0x1a
#define SDMA2_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK                                                             0x00000007L
#define SDMA2_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK                                                  0x00000038L
#define SDMA2_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK                                                  0x000000C0L
#define SDMA2_GB_ADDR_CONFIG_READ__NUM_PKRS_MASK                                                              0x00000700L
#define SDMA2_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK                                                    0x00180000L
#define SDMA2_GB_ADDR_CONFIG_READ__NUM_RB_PER_SE_MASK                                                         0x0C000000L
//SDMA2_RB_RPTR_FETCH_HI
#define SDMA2_RB_RPTR_FETCH_HI__OFFSET__SHIFT                                                                 0x0
#define SDMA2_RB_RPTR_FETCH_HI__OFFSET_MASK                                                                   0xFFFFFFFFL
//SDMA2_SEM_WAIT_FAIL_TIMER_CNTL
#define SDMA2_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT                                                          0x0
#define SDMA2_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK                                                            0xFFFFFFFFL
//SDMA2_RB_RPTR_FETCH
#define SDMA2_RB_RPTR_FETCH__OFFSET__SHIFT                                                                    0x2
#define SDMA2_RB_RPTR_FETCH__OFFSET_MASK                                                                      0xFFFFFFFCL
//SDMA2_IB_OFFSET_FETCH
#define SDMA2_IB_OFFSET_FETCH__OFFSET__SHIFT                                                                  0x2
#define SDMA2_IB_OFFSET_FETCH__OFFSET_MASK                                                                    0x003FFFFCL
//SDMA2_PROGRAM
#define SDMA2_PROGRAM__STREAM__SHIFT                                                                          0x0
#define SDMA2_PROGRAM__STREAM_MASK                                                                            0xFFFFFFFFL
//SDMA2_STATUS_REG
#define SDMA2_STATUS_REG__IDLE__SHIFT                                                                         0x0
#define SDMA2_STATUS_REG__REG_IDLE__SHIFT                                                                     0x1
#define SDMA2_STATUS_REG__RB_EMPTY__SHIFT                                                                     0x2
#define SDMA2_STATUS_REG__RB_FULL__SHIFT                                                                      0x3
#define SDMA2_STATUS_REG__RB_CMD_IDLE__SHIFT                                                                  0x4
#define SDMA2_STATUS_REG__RB_CMD_FULL__SHIFT                                                                  0x5
#define SDMA2_STATUS_REG__IB_CMD_IDLE__SHIFT                                                                  0x6
#define SDMA2_STATUS_REG__IB_CMD_FULL__SHIFT                                                                  0x7
#define SDMA2_STATUS_REG__BLOCK_IDLE__SHIFT                                                                   0x8
#define SDMA2_STATUS_REG__INSIDE_IB__SHIFT                                                                    0x9
#define SDMA2_STATUS_REG__EX_IDLE__SHIFT                                                                      0xa
#define SDMA2_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT                                                    0xb
#define SDMA2_STATUS_REG__PACKET_READY__SHIFT                                                                 0xc
#define SDMA2_STATUS_REG__MC_WR_IDLE__SHIFT                                                                   0xd
#define SDMA2_STATUS_REG__SRBM_IDLE__SHIFT                                                                    0xe
#define SDMA2_STATUS_REG__CONTEXT_EMPTY__SHIFT                                                                0xf
#define SDMA2_STATUS_REG__DELTA_RPTR_FULL__SHIFT                                                              0x10
#define SDMA2_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT                                                              0x11
#define SDMA2_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT                                                              0x12
#define SDMA2_STATUS_REG__MC_RD_IDLE__SHIFT                                                                   0x13
#define SDMA2_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT                                                             0x14
#define SDMA2_STATUS_REG__MC_RD_RET_STALL__SHIFT                                                              0x15
#define SDMA2_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT                                                           0x16
#define SDMA2_STATUS_REG__PREV_CMD_IDLE__SHIFT                                                                0x19
#define SDMA2_STATUS_REG__SEM_IDLE__SHIFT                                                                     0x1a
#define SDMA2_STATUS_REG__SEM_REQ_STALL__SHIFT                                                                0x1b
#define SDMA2_STATUS_REG__SEM_RESP_STATE__SHIFT                                                               0x1c
#define SDMA2_STATUS_REG__INT_IDLE__SHIFT                                                                     0x1e
#define SDMA2_STATUS_REG__INT_REQ_STALL__SHIFT                                                                0x1f
#define SDMA2_STATUS_REG__IDLE_MASK                                                                           0x00000001L
#define SDMA2_STATUS_REG__REG_IDLE_MASK                                                                       0x00000002L
#define SDMA2_STATUS_REG__RB_EMPTY_MASK                                                                       0x00000004L
#define SDMA2_STATUS_REG__RB_FULL_MASK                                                                        0x00000008L
#define SDMA2_STATUS_REG__RB_CMD_IDLE_MASK                                                                    0x00000010L
#define SDMA2_STATUS_REG__RB_CMD_FULL_MASK                                                                    0x00000020L
#define SDMA2_STATUS_REG__IB_CMD_IDLE_MASK                                                                    0x00000040L
#define SDMA2_STATUS_REG__IB_CMD_FULL_MASK                                                                    0x00000080L
#define SDMA2_STATUS_REG__BLOCK_IDLE_MASK                                                                     0x00000100L
#define SDMA2_STATUS_REG__INSIDE_IB_MASK                                                                      0x00000200L
#define SDMA2_STATUS_REG__EX_IDLE_MASK                                                                        0x00000400L
#define SDMA2_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK                                                      0x00000800L
#define SDMA2_STATUS_REG__PACKET_READY_MASK                                                                   0x00001000L
#define SDMA2_STATUS_REG__MC_WR_IDLE_MASK                                                                     0x00002000L
#define SDMA2_STATUS_REG__SRBM_IDLE_MASK                                                                      0x00004000L
#define SDMA2_STATUS_REG__CONTEXT_EMPTY_MASK                                                                  0x00008000L
#define SDMA2_STATUS_REG__DELTA_RPTR_FULL_MASK                                                                0x00010000L
#define SDMA2_STATUS_REG__RB_MC_RREQ_IDLE_MASK                                                                0x00020000L
#define SDMA2_STATUS_REG__IB_MC_RREQ_IDLE_MASK                                                                0x00040000L
#define SDMA2_STATUS_REG__MC_RD_IDLE_MASK                                                                     0x00080000L
#define SDMA2_STATUS_REG__DELTA_RPTR_EMPTY_MASK                                                               0x00100000L
#define SDMA2_STATUS_REG__MC_RD_RET_STALL_MASK                                                                0x00200000L
#define SDMA2_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK                                                             0x00400000L
#define SDMA2_STATUS_REG__PREV_CMD_IDLE_MASK                                                                  0x02000000L
#define SDMA2_STATUS_REG__SEM_IDLE_MASK                                                                       0x04000000L
#define SDMA2_STATUS_REG__SEM_REQ_STALL_MASK                                                                  0x08000000L
#define SDMA2_STATUS_REG__SEM_RESP_STATE_MASK                                                                 0x30000000L
#define SDMA2_STATUS_REG__INT_IDLE_MASK                                                                       0x40000000L
#define SDMA2_STATUS_REG__INT_REQ_STALL_MASK                                                                  0x80000000L
//SDMA2_STATUS1_REG
#define SDMA2_STATUS1_REG__CE_WREQ_IDLE__SHIFT                                                                0x0
#define SDMA2_STATUS1_REG__CE_WR_IDLE__SHIFT                                                                  0x1
#define SDMA2_STATUS1_REG__CE_SPLIT_IDLE__SHIFT                                                               0x2
#define SDMA2_STATUS1_REG__CE_RREQ_IDLE__SHIFT                                                                0x3
#define SDMA2_STATUS1_REG__CE_OUT_IDLE__SHIFT                                                                 0x4
#define SDMA2_STATUS1_REG__CE_IN_IDLE__SHIFT                                                                  0x5
#define SDMA2_STATUS1_REG__CE_DST_IDLE__SHIFT                                                                 0x6
#define SDMA2_STATUS1_REG__CE_CMD_IDLE__SHIFT                                                                 0x9
#define SDMA2_STATUS1_REG__CE_AFIFO_FULL__SHIFT                                                               0xa
#define SDMA2_STATUS1_REG__CE_INFO_FULL__SHIFT                                                                0xd
#define SDMA2_STATUS1_REG__CE_INFO1_FULL__SHIFT                                                               0xe
#define SDMA2_STATUS1_REG__EX_START__SHIFT                                                                    0xf
#define SDMA2_STATUS1_REG__CE_RD_STALL__SHIFT                                                                 0x11
#define SDMA2_STATUS1_REG__CE_WR_STALL__SHIFT                                                                 0x12
#define SDMA2_STATUS1_REG__CE_WREQ_IDLE_MASK                                                                  0x00000001L
#define SDMA2_STATUS1_REG__CE_WR_IDLE_MASK                                                                    0x00000002L
#define SDMA2_STATUS1_REG__CE_SPLIT_IDLE_MASK                                                                 0x00000004L
#define SDMA2_STATUS1_REG__CE_RREQ_IDLE_MASK                                                                  0x00000008L
#define SDMA2_STATUS1_REG__CE_OUT_IDLE_MASK                                                                   0x00000010L
#define SDMA2_STATUS1_REG__CE_IN_IDLE_MASK                                                                    0x00000020L
#define SDMA2_STATUS1_REG__CE_DST_IDLE_MASK                                                                   0x00000040L
#define SDMA2_STATUS1_REG__CE_CMD_IDLE_MASK                                                                   0x00000200L
#define SDMA2_STATUS1_REG__CE_AFIFO_FULL_MASK                                                                 0x00000400L
#define SDMA2_STATUS1_REG__CE_INFO_FULL_MASK                                                                  0x00002000L
#define SDMA2_STATUS1_REG__CE_INFO1_FULL_MASK                                                                 0x00004000L
#define SDMA2_STATUS1_REG__EX_START_MASK                                                                      0x00008000L
#define SDMA2_STATUS1_REG__CE_RD_STALL_MASK                                                                   0x00020000L
#define SDMA2_STATUS1_REG__CE_WR_STALL_MASK                                                                   0x00040000L
//SDMA2_RD_BURST_CNTL
#define SDMA2_RD_BURST_CNTL__RD_BURST__SHIFT                                                                  0x0
#define SDMA2_RD_BURST_CNTL__RD_BURST_MASK                                                                    0x00000003L
//SDMA2_HBM_PAGE_CONFIG
#define SDMA2_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT                                                      0x0
#define SDMA2_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK                                                        0x00000001L
//SDMA2_UCODE_CHECKSUM
#define SDMA2_UCODE_CHECKSUM__DATA__SHIFT                                                                     0x0
#define SDMA2_UCODE_CHECKSUM__DATA_MASK                                                                       0xFFFFFFFFL
//SDMA2_F32_CNTL
#define SDMA2_F32_CNTL__HALT__SHIFT                                                                           0x0
#define SDMA2_F32_CNTL__STEP__SHIFT                                                                           0x1
#define SDMA2_F32_CNTL__CHECKSUM_CLR__SHIFT                                                                   0x8
#define SDMA2_F32_CNTL__RESET__SHIFT                                                                          0x9
#define SDMA2_F32_CNTL__HALT_MASK                                                                             0x00000001L
#define SDMA2_F32_CNTL__STEP_MASK                                                                             0x00000002L
#define SDMA2_F32_CNTL__CHECKSUM_CLR_MASK                                                                     0x00000100L
#define SDMA2_F32_CNTL__RESET_MASK                                                                            0x00000200L
//SDMA2_FREEZE
#define SDMA2_FREEZE__PREEMPT__SHIFT                                                                          0x0
#define SDMA2_FREEZE__FORCE_PREEMPT__SHIFT                                                                    0x1
#define SDMA2_FREEZE__FREEZE__SHIFT                                                                           0x4
#define SDMA2_FREEZE__FROZEN__SHIFT                                                                           0x5
#define SDMA2_FREEZE__F32_FREEZE__SHIFT                                                                       0x6
#define SDMA2_FREEZE__PREEMPT_MASK                                                                            0x00000001L
#define SDMA2_FREEZE__FORCE_PREEMPT_MASK                                                                      0x00000002L
#define SDMA2_FREEZE__FREEZE_MASK                                                                             0x00000010L
#define SDMA2_FREEZE__FROZEN_MASK                                                                             0x00000020L
#define SDMA2_FREEZE__F32_FREEZE_MASK                                                                         0x00000040L
//SDMA2_PHASE0_QUANTUM
#define SDMA2_PHASE0_QUANTUM__UNIT__SHIFT                                                                     0x0
#define SDMA2_PHASE0_QUANTUM__VALUE__SHIFT                                                                    0x8
#define SDMA2_PHASE0_QUANTUM__PREFER__SHIFT                                                                   0x1e
#define SDMA2_PHASE0_QUANTUM__UNIT_MASK                                                                       0x0000000FL
#define SDMA2_PHASE0_QUANTUM__VALUE_MASK                                                                      0x00FFFF00L
#define SDMA2_PHASE0_QUANTUM__PREFER_MASK                                                                     0x40000000L
//SDMA2_PHASE1_QUANTUM
#define SDMA2_PHASE1_QUANTUM__UNIT__SHIFT                                                                     0x0
#define SDMA2_PHASE1_QUANTUM__VALUE__SHIFT                                                                    0x8
#define SDMA2_PHASE1_QUANTUM__PREFER__SHIFT                                                                   0x1e
#define SDMA2_PHASE1_QUANTUM__UNIT_MASK                                                                       0x0000000FL
#define SDMA2_PHASE1_QUANTUM__VALUE_MASK                                                                      0x00FFFF00L
#define SDMA2_PHASE1_QUANTUM__PREFER_MASK                                                                     0x40000000L
//SDMA2_EDC_CONFIG
#define SDMA2_EDC_CONFIG__DIS_EDC__SHIFT                                                                      0x1
#define SDMA2_EDC_CONFIG__ECC_INT_ENABLE__SHIFT                                                               0x2
#define SDMA2_EDC_CONFIG__DIS_EDC_MASK                                                                        0x00000002L
#define SDMA2_EDC_CONFIG__ECC_INT_ENABLE_MASK                                                                 0x00000004L
//SDMA2_BA_THRESHOLD
#define SDMA2_BA_THRESHOLD__READ_THRES__SHIFT                                                                 0x0
#define SDMA2_BA_THRESHOLD__WRITE_THRES__SHIFT                                                                0x10
#define SDMA2_BA_THRESHOLD__READ_THRES_MASK                                                                   0x000003FFL
#define SDMA2_BA_THRESHOLD__WRITE_THRES_MASK                                                                  0x03FF0000L
//SDMA2_ID
#define SDMA2_ID__DEVICE_ID__SHIFT                                                                            0x0
#define SDMA2_ID__DEVICE_ID_MASK                                                                              0x000000FFL
//SDMA2_VERSION
#define SDMA2_VERSION__MINVER__SHIFT                                                                          0x0
#define SDMA2_VERSION__MAJVER__SHIFT                                                                          0x8
#define SDMA2_VERSION__REV__SHIFT                                                                             0x10
#define SDMA2_VERSION__MINVER_MASK                                                                            0x0000007FL
#define SDMA2_VERSION__MAJVER_MASK                                                                            0x00007F00L
#define SDMA2_VERSION__REV_MASK                                                                               0x003F0000L
//SDMA2_EDC_COUNTER
#define SDMA2_EDC_COUNTER__SDMA_UCODE_BUF_DED__SHIFT                                                          0x0
#define SDMA2_EDC_COUNTER__SDMA_UCODE_BUF_SEC__SHIFT                                                          0x1
#define SDMA2_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT                                                         0x2
#define SDMA2_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT                                                         0x3
#define SDMA2_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT                                                      0x4
#define SDMA2_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT                                                   0x5
#define SDMA2_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT                                                      0x6
#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT                                                    0x7
#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT                                                    0x8
#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT                                                    0x9
#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT                                                    0xa
#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT                                                    0xb
#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT                                                    0xc
#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT                                                    0xd
#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT                                                    0xe
#define SDMA2_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT                                                      0xf
#define SDMA2_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT                                                    0x10
#define SDMA2_EDC_COUNTER__SDMA_UCODE_BUF_DED_MASK                                                            0x00000001L
#define SDMA2_EDC_COUNTER__SDMA_UCODE_BUF_SEC_MASK                                                            0x00000002L
#define SDMA2_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK                                                           0x00000004L
#define SDMA2_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK                                                           0x00000008L
#define SDMA2_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK                                                        0x00000010L
#define SDMA2_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK                                                     0x00000020L
#define SDMA2_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK                                                        0x00000040L
#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK                                                      0x00000080L
#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK                                                      0x00000100L
#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK                                                      0x00000200L
#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK                                                      0x00000400L
#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK                                                      0x00000800L
#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK                                                      0x00001000L
#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK                                                      0x00002000L
#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK                                                      0x00004000L
#define SDMA2_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK                                                        0x00008000L
#define SDMA2_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK                                                      0x00010000L
//SDMA2_EDC_COUNTER_CLEAR
#define SDMA2_EDC_COUNTER_CLEAR__DUMMY__SHIFT                                                                 0x0
#define SDMA2_EDC_COUNTER_CLEAR__DUMMY_MASK                                                                   0x00000001L
//SDMA2_STATUS2_REG
#define SDMA2_STATUS2_REG__ID__SHIFT                                                                          0x0
#define SDMA2_STATUS2_REG__F32_INSTR_PTR__SHIFT                                                               0x2
#define SDMA2_STATUS2_REG__CMD_OP__SHIFT                                                                      0x10
#define SDMA2_STATUS2_REG__ID_MASK                                                                            0x00000003L
#define SDMA2_STATUS2_REG__F32_INSTR_PTR_MASK                                                                 0x0000FFFCL
#define SDMA2_STATUS2_REG__CMD_OP_MASK                                                                        0xFFFF0000L
//SDMA2_ATOMIC_CNTL
#define SDMA2_ATOMIC_CNTL__LOOP_TIMER__SHIFT                                                                  0x0
#define SDMA2_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT                                                       0x1f
#define SDMA2_ATOMIC_CNTL__LOOP_TIMER_MASK                                                                    0x7FFFFFFFL
#define SDMA2_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK                                                         0x80000000L
//SDMA2_ATOMIC_PREOP_LO
#define SDMA2_ATOMIC_PREOP_LO__DATA__SHIFT                                                                    0x0
#define SDMA2_ATOMIC_PREOP_LO__DATA_MASK                                                                      0xFFFFFFFFL
//SDMA2_ATOMIC_PREOP_HI
#define SDMA2_ATOMIC_PREOP_HI__DATA__SHIFT                                                                    0x0
#define SDMA2_ATOMIC_PREOP_HI__DATA_MASK                                                                      0xFFFFFFFFL
//SDMA2_UTCL1_CNTL
#define SDMA2_UTCL1_CNTL__REDO_ENABLE__SHIFT                                                                  0x0
#define SDMA2_UTCL1_CNTL__REDO_DELAY__SHIFT                                                                   0x1
#define SDMA2_UTCL1_CNTL__REDO_WATERMK__SHIFT                                                                 0x6
#define SDMA2_UTCL1_CNTL__RESP_MODE__SHIFT                                                                    0x9
#define SDMA2_UTCL1_CNTL__FORCE_INVALIDATION__SHIFT                                                           0xe
#define SDMA2_UTCL1_CNTL__FORCE_INVREQ_HEAVY__SHIFT                                                           0xf
#define SDMA2_UTCL1_CNTL__INVACK_DELAY__SHIFT                                                                 0x10
#define SDMA2_UTCL1_CNTL__REQL2_CREDIT__SHIFT                                                                 0x18
#define SDMA2_UTCL1_CNTL__VADDR_WATERMK__SHIFT                                                                0x1d
#define SDMA2_UTCL1_CNTL__REDO_ENABLE_MASK                                                                    0x00000001L
#define SDMA2_UTCL1_CNTL__REDO_DELAY_MASK                                                                     0x0000003EL
#define SDMA2_UTCL1_CNTL__REDO_WATERMK_MASK                                                                   0x000001C0L
#define SDMA2_UTCL1_CNTL__RESP_MODE_MASK                                                                      0x00000E00L
#define SDMA2_UTCL1_CNTL__FORCE_INVALIDATION_MASK                                                             0x00004000L
#define SDMA2_UTCL1_CNTL__FORCE_INVREQ_HEAVY_MASK                                                             0x00008000L
#define SDMA2_UTCL1_CNTL__INVACK_DELAY_MASK                                                                   0x00FF0000L
#define SDMA2_UTCL1_CNTL__REQL2_CREDIT_MASK                                                                   0x1F000000L
#define SDMA2_UTCL1_CNTL__VADDR_WATERMK_MASK                                                                  0xE0000000L
//SDMA2_UTCL1_WATERMK
#define SDMA2_UTCL1_WATERMK__REQMC_WATERMK__SHIFT                                                             0x0
#define SDMA2_UTCL1_WATERMK__REQPG_WATERMK__SHIFT                                                             0xa
#define SDMA2_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT                                                            0x12
#define SDMA2_UTCL1_WATERMK__XNACK_WATERMK__SHIFT                                                             0x1a
#define SDMA2_UTCL1_WATERMK__REQMC_WATERMK_MASK                                                               0x000003FFL
#define SDMA2_UTCL1_WATERMK__REQPG_WATERMK_MASK                                                               0x0003FC00L
#define SDMA2_UTCL1_WATERMK__INVREQ_WATERMK_MASK                                                              0x03FC0000L
#define SDMA2_UTCL1_WATERMK__XNACK_WATERMK_MASK                                                               0xFC000000L
//SDMA2_UTCL1_RD_STATUS
#define SDMA2_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT                                                0x0
#define SDMA2_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT                                                 0x1
#define SDMA2_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT                                                     0x2
#define SDMA2_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT                                                      0x3
#define SDMA2_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT                                                      0x4
#define SDMA2_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT                                                       0x5
#define SDMA2_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT                                                   0x6
#define SDMA2_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT                                                    0x7
#define SDMA2_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT                                                    0x8
#define SDMA2_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT                                                     0x9
#define SDMA2_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT                                                 0xa
#define SDMA2_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT                                                  0xb
#define SDMA2_UTCL1_RD_STATUS__REDO_ARR_EMPTY__SHIFT                                                          0xc
#define SDMA2_UTCL1_RD_STATUS__REDO_ARR_FULL__SHIFT                                                           0xd
#define SDMA2_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT                                                              0xe
#define SDMA2_UTCL1_RD_STATUS__PAGE_NULL__SHIFT                                                               0xf
#define SDMA2_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT                                                              0x10
#define SDMA2_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT                                                          0x11
#define SDMA2_UTCL1_RD_STATUS__MERGE_STATE__SHIFT                                                             0x15
#define SDMA2_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT                                                             0x18
#define SDMA2_UTCL1_RD_STATUS__RD_XNACK_TIMEOUT__SHIFT                                                        0x19
#define SDMA2_UTCL1_RD_STATUS__PAGE_NULL_SW__SHIFT                                                            0x1a
#define SDMA2_UTCL1_RD_STATUS__HIT_CACHE__SHIFT                                                               0x1b
#define SDMA2_UTCL1_RD_STATUS__RD_DCC_ENABLE__SHIFT                                                           0x1c
#define SDMA2_UTCL1_RD_STATUS__NACK_TIMEOUT_SW__SHIFT                                                         0x1d
#define SDMA2_UTCL1_RD_STATUS__DCC_PAGE_FAULT__SHIFT                                                          0x1e
#define SDMA2_UTCL1_RD_STATUS__DCC_PAGE_NULL__SHIFT                                                           0x1f
#define SDMA2_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK                                                  0x00000001L
#define SDMA2_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK                                                   0x00000002L
#define SDMA2_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK                                                       0x00000004L
#define SDMA2_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK                                                        0x00000008L
#define SDMA2_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK                                                        0x00000010L
#define SDMA2_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK                                                         0x00000020L
#define SDMA2_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK                                                     0x00000040L
#define SDMA2_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK                                                      0x00000080L
#define SDMA2_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK                                                      0x00000100L
#define SDMA2_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK                                                       0x00000200L
#define SDMA2_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK                                                   0x00000400L
#define SDMA2_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK                                                    0x00000800L
#define SDMA2_UTCL1_RD_STATUS__REDO_ARR_EMPTY_MASK                                                            0x00001000L
#define SDMA2_UTCL1_RD_STATUS__REDO_ARR_FULL_MASK                                                             0x00002000L
#define SDMA2_UTCL1_RD_STATUS__PAGE_FAULT_MASK                                                                0x00004000L
#define SDMA2_UTCL1_RD_STATUS__PAGE_NULL_MASK                                                                 0x00008000L
#define SDMA2_UTCL1_RD_STATUS__REQL2_IDLE_MASK                                                                0x00010000L
#define SDMA2_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK                                                            0x001E0000L
#define SDMA2_UTCL1_RD_STATUS__MERGE_STATE_MASK                                                               0x00E00000L
#define SDMA2_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK                                                               0x01000000L
#define SDMA2_UTCL1_RD_STATUS__RD_XNACK_TIMEOUT_MASK                                                          0x02000000L
#define SDMA2_UTCL1_RD_STATUS__PAGE_NULL_SW_MASK                                                              0x04000000L
#define SDMA2_UTCL1_RD_STATUS__HIT_CACHE_MASK                                                                 0x08000000L
#define SDMA2_UTCL1_RD_STATUS__RD_DCC_ENABLE_MASK                                                             0x10000000L
#define SDMA2_UTCL1_RD_STATUS__NACK_TIMEOUT_SW_MASK                                                           0x20000000L
#define SDMA2_UTCL1_RD_STATUS__DCC_PAGE_FAULT_MASK                                                            0x40000000L
#define SDMA2_UTCL1_RD_STATUS__DCC_PAGE_NULL_MASK                                                             0x80000000L
//SDMA2_UTCL1_WR_STATUS
#define SDMA2_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT                                                0x0
#define SDMA2_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT                                                 0x1
#define SDMA2_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT                                                     0x2
#define SDMA2_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT                                                      0x3
#define SDMA2_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT                                                      0x4
#define SDMA2_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT                                                       0x5
#define SDMA2_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT                                                   0x6
#define SDMA2_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT                                                    0x7
#define SDMA2_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT                                                    0x8
#define SDMA2_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT                                                     0x9
#define SDMA2_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT                                                 0xa
#define SDMA2_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT                                                  0xb
#define SDMA2_UTCL1_WR_STATUS__REDO_ARR_EMPTY__SHIFT                                                          0xc
#define SDMA2_UTCL1_WR_STATUS__REDO_ARR_FULL__SHIFT                                                           0xd
#define SDMA2_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT                                                              0xe
#define SDMA2_UTCL1_WR_STATUS__PAGE_NULL__SHIFT                                                               0xf
#define SDMA2_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT                                                              0x10
#define SDMA2_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT                                                          0x11
#define SDMA2_UTCL1_WR_STATUS__MERGE_STATE__SHIFT                                                             0x15
#define SDMA2_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT                                                              0x18
#define SDMA2_UTCL1_WR_STATUS__WR_XNACK_TIMEOUT__SHIFT                                                        0x19
#define SDMA2_UTCL1_WR_STATUS__PAGE_NULL_SW__SHIFT                                                            0x1a
#define SDMA2_UTCL1_WR_STATUS__ATOMIC_OP__SHIFT                                                               0x1b
#define SDMA2_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT                                                    0x1c
#define SDMA2_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT                                                     0x1d
#define SDMA2_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT                                                   0x1e
#define SDMA2_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT                                                    0x1f
#define SDMA2_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK                                                  0x00000001L
#define SDMA2_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK                                                   0x00000002L
#define SDMA2_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK                                                       0x00000004L
#define SDMA2_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK                                                        0x00000008L
#define SDMA2_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK                                                        0x00000010L
#define SDMA2_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK                                                         0x00000020L
#define SDMA2_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK                                                     0x00000040L
#define SDMA2_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK                                                      0x00000080L
#define SDMA2_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK                                                      0x00000100L
#define SDMA2_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK                                                       0x00000200L
#define SDMA2_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK                                                   0x00000400L
#define SDMA2_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK                                                    0x00000800L
#define SDMA2_UTCL1_WR_STATUS__REDO_ARR_EMPTY_MASK                                                            0x00001000L
#define SDMA2_UTCL1_WR_STATUS__REDO_ARR_FULL_MASK                                                             0x00002000L
#define SDMA2_UTCL1_WR_STATUS__PAGE_FAULT_MASK                                                                0x00004000L
#define SDMA2_UTCL1_WR_STATUS__PAGE_NULL_MASK                                                                 0x00008000L
#define SDMA2_UTCL1_WR_STATUS__REQL2_IDLE_MASK                                                                0x00010000L
#define SDMA2_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK                                                            0x001E0000L
#define SDMA2_UTCL1_WR_STATUS__MERGE_STATE_MASK                                                               0x00E00000L
#define SDMA2_UTCL1_WR_STATUS__F32_WR_RTR_MASK                                                                0x01000000L
#define SDMA2_UTCL1_WR_STATUS__WR_XNACK_TIMEOUT_MASK                                                          0x02000000L
#define SDMA2_UTCL1_WR_STATUS__PAGE_NULL_SW_MASK                                                              0x04000000L
#define SDMA2_UTCL1_WR_STATUS__ATOMIC_OP_MASK                                                                 0x08000000L
#define SDMA2_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK                                                      0x10000000L
#define SDMA2_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK                                                       0x20000000L
#define SDMA2_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK                                                     0x40000000L
#define SDMA2_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK                                                      0x80000000L
//SDMA2_UTCL1_INV0
#define SDMA2_UTCL1_INV0__CPF_INVREQ_EN__SHIFT                                                                0x0
#define SDMA2_UTCL1_INV0__GPUVM_INVREQ_EN__SHIFT                                                              0x1
#define SDMA2_UTCL1_INV0__CPF_GPA_INVREQ__SHIFT                                                               0x2
#define SDMA2_UTCL1_INV0__GPUVM_INVREQ_LOW__SHIFT                                                             0x3
#define SDMA2_UTCL1_INV0__GPUVM_INVREQ_HIGH__SHIFT                                                            0x4
#define SDMA2_UTCL1_INV0__INVREQ_SIZE__SHIFT                                                                  0x5
#define SDMA2_UTCL1_INV0__INVREQ_IDLE__SHIFT                                                                  0xb
#define SDMA2_UTCL1_INV0__VMINV_PEND_CNT__SHIFT                                                               0xc
#define SDMA2_UTCL1_INV0__GPUVM_LO_INV_VMID__SHIFT                                                            0x10
#define SDMA2_UTCL1_INV0__GPUVM_HI_INV_VMID__SHIFT                                                            0x14
#define SDMA2_UTCL1_INV0__GPUVM_INV_MODE__SHIFT                                                               0x18
#define SDMA2_UTCL1_INV0__INVREQ_IS_HEAVY__SHIFT                                                              0x1a
#define SDMA2_UTCL1_INV0__INVREQ_FROM_CPF__SHIFT                                                              0x1b
#define SDMA2_UTCL1_INV0__GPUVM_INVREQ_TAG__SHIFT                                                             0x1c
#define SDMA2_UTCL1_INV0__CPF_INVREQ_EN_MASK                                                                  0x00000001L
#define SDMA2_UTCL1_INV0__GPUVM_INVREQ_EN_MASK                                                                0x00000002L
#define SDMA2_UTCL1_INV0__CPF_GPA_INVREQ_MASK                                                                 0x00000004L
#define SDMA2_UTCL1_INV0__GPUVM_INVREQ_LOW_MASK                                                               0x00000008L
#define SDMA2_UTCL1_INV0__GPUVM_INVREQ_HIGH_MASK                                                              0x00000010L
#define SDMA2_UTCL1_INV0__INVREQ_SIZE_MASK                                                                    0x000007E0L
#define SDMA2_UTCL1_INV0__INVREQ_IDLE_MASK                                                                    0x00000800L
#define SDMA2_UTCL1_INV0__VMINV_PEND_CNT_MASK                                                                 0x0000F000L
#define SDMA2_UTCL1_INV0__GPUVM_LO_INV_VMID_MASK                                                              0x000F0000L
#define SDMA2_UTCL1_INV0__GPUVM_HI_INV_VMID_MASK                                                              0x00F00000L
#define SDMA2_UTCL1_INV0__GPUVM_INV_MODE_MASK                                                                 0x03000000L
#define SDMA2_UTCL1_INV0__INVREQ_IS_HEAVY_MASK                                                                0x04000000L
#define SDMA2_UTCL1_INV0__INVREQ_FROM_CPF_MASK                                                                0x08000000L
#define SDMA2_UTCL1_INV0__GPUVM_INVREQ_TAG_MASK                                                               0xF0000000L
//SDMA2_UTCL1_INV1
#define SDMA2_UTCL1_INV1__INV_ADDR_LO__SHIFT                                                                  0x0
#define SDMA2_UTCL1_INV1__INV_ADDR_LO_MASK                                                                    0xFFFFFFFFL
//SDMA2_UTCL1_INV2
#define SDMA2_UTCL1_INV2__INV_VMID_VEC__SHIFT                                                                 0x0
#define SDMA2_UTCL1_INV2__RESERVED__SHIFT                                                                     0x10
#define SDMA2_UTCL1_INV2__INV_VMID_VEC_MASK                                                                   0x0000FFFFL
#define SDMA2_UTCL1_INV2__RESERVED_MASK                                                                       0xFFFF0000L
//SDMA2_UTCL1_RD_XNACK0
#define SDMA2_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT                                                           0x0
#define SDMA2_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK                                                             0xFFFFFFFFL
//SDMA2_UTCL1_RD_XNACK1
#define SDMA2_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT                                                           0x0
#define SDMA2_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT                                                              0x4
#define SDMA2_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT                                                            0x8
#define SDMA2_UTCL1_RD_XNACK1__IS_XNACK__SHIFT                                                                0x1a
#define SDMA2_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK                                                             0x0000000FL
#define SDMA2_UTCL1_RD_XNACK1__XNACK_VMID_MASK                                                                0x000000F0L
#define SDMA2_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK                                                              0x03FFFF00L
#define SDMA2_UTCL1_RD_XNACK1__IS_XNACK_MASK                                                                  0x0C000000L
//SDMA2_UTCL1_WR_XNACK0
#define SDMA2_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT                                                           0x0
#define SDMA2_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK                                                             0xFFFFFFFFL
//SDMA2_UTCL1_WR_XNACK1
#define SDMA2_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT                                                           0x0
#define SDMA2_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT                                                              0x4
#define SDMA2_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT                                                            0x8
#define SDMA2_UTCL1_WR_XNACK1__IS_XNACK__SHIFT                                                                0x1a
#define SDMA2_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK                                                             0x0000000FL
#define SDMA2_UTCL1_WR_XNACK1__XNACK_VMID_MASK                                                                0x000000F0L
#define SDMA2_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK                                                              0x03FFFF00L
#define SDMA2_UTCL1_WR_XNACK1__IS_XNACK_MASK                                                                  0x0C000000L
//SDMA2_UTCL1_TIMEOUT
#define SDMA2_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT                                                            0x0
#define SDMA2_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT                                                            0x10
#define SDMA2_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK                                                              0x0000FFFFL
#define SDMA2_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK                                                              0xFFFF0000L
//SDMA2_UTCL1_PAGE
#define SDMA2_UTCL1_PAGE__VM_HOLE__SHIFT                                                                      0x0
#define SDMA2_UTCL1_PAGE__REQ_TYPE__SHIFT                                                                     0x1
#define SDMA2_UTCL1_PAGE__USE_MTYPE__SHIFT                                                                    0x6
#define SDMA2_UTCL1_PAGE__USE_PT_SNOOP__SHIFT                                                                 0xa
#define SDMA2_UTCL1_PAGE__USE_IO__SHIFT                                                                       0xb
#define SDMA2_UTCL1_PAGE__RD_L2_POLICY__SHIFT                                                                 0xc
#define SDMA2_UTCL1_PAGE__WR_L2_POLICY__SHIFT                                                                 0xe
#define SDMA2_UTCL1_PAGE__DMA_PAGE_SIZE__SHIFT                                                                0x10
#define SDMA2_UTCL1_PAGE__USE_BC__SHIFT                                                                       0x16
#define SDMA2_UTCL1_PAGE__ADDR_IS_PA__SHIFT                                                                   0x17
#define SDMA2_UTCL1_PAGE__VM_HOLE_MASK                                                                        0x00000001L
#define SDMA2_UTCL1_PAGE__REQ_TYPE_MASK                                                                       0x0000001EL
#define SDMA2_UTCL1_PAGE__USE_MTYPE_MASK                                                                      0x000003C0L
#define SDMA2_UTCL1_PAGE__USE_PT_SNOOP_MASK                                                                   0x00000400L
#define SDMA2_UTCL1_PAGE__USE_IO_MASK                                                                         0x00000800L
#define SDMA2_UTCL1_PAGE__RD_L2_POLICY_MASK                                                                   0x00003000L
#define SDMA2_UTCL1_PAGE__WR_L2_POLICY_MASK                                                                   0x0000C000L
#define SDMA2_UTCL1_PAGE__DMA_PAGE_SIZE_MASK                                                                  0x003F0000L
#define SDMA2_UTCL1_PAGE__USE_BC_MASK                                                                         0x00400000L
#define SDMA2_UTCL1_PAGE__ADDR_IS_PA_MASK                                                                     0x00800000L
//SDMA2_RELAX_ORDERING_LUT
#define SDMA2_RELAX_ORDERING_LUT__RESERVED0__SHIFT                                                            0x0
#define SDMA2_RELAX_ORDERING_LUT__COPY__SHIFT                                                                 0x1
#define SDMA2_RELAX_ORDERING_LUT__WRITE__SHIFT                                                                0x2
#define SDMA2_RELAX_ORDERING_LUT__RESERVED3__SHIFT                                                            0x3
#define SDMA2_RELAX_ORDERING_LUT__RESERVED4__SHIFT                                                            0x4
#define SDMA2_RELAX_ORDERING_LUT__FENCE__SHIFT                                                                0x5
#define SDMA2_RELAX_ORDERING_LUT__RESERVED76__SHIFT                                                           0x6
#define SDMA2_RELAX_ORDERING_LUT__POLL_MEM__SHIFT                                                             0x8
#define SDMA2_RELAX_ORDERING_LUT__COND_EXE__SHIFT                                                             0x9
#define SDMA2_RELAX_ORDERING_LUT__ATOMIC__SHIFT                                                               0xa
#define SDMA2_RELAX_ORDERING_LUT__CONST_FILL__SHIFT                                                           0xb
#define SDMA2_RELAX_ORDERING_LUT__PTEPDE__SHIFT                                                               0xc
#define SDMA2_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT                                                            0xd
#define SDMA2_RELAX_ORDERING_LUT__RESERVED__SHIFT                                                             0xe
#define SDMA2_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT                                                         0x1b
#define SDMA2_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT                                                             0x1c
#define SDMA2_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT                                                            0x1d
#define SDMA2_RELAX_ORDERING_LUT__IB_FETCH__SHIFT                                                             0x1e
#define SDMA2_RELAX_ORDERING_LUT__RB_FETCH__SHIFT                                                             0x1f
#define SDMA2_RELAX_ORDERING_LUT__RESERVED0_MASK                                                              0x00000001L
#define SDMA2_RELAX_ORDERING_LUT__COPY_MASK                                                                   0x00000002L
#define SDMA2_RELAX_ORDERING_LUT__WRITE_MASK                                                                  0x00000004L
#define SDMA2_RELAX_ORDERING_LUT__RESERVED3_MASK                                                              0x00000008L
#define SDMA2_RELAX_ORDERING_LUT__RESERVED4_MASK                                                              0x00000010L
#define SDMA2_RELAX_ORDERING_LUT__FENCE_MASK                                                                  0x00000020L
#define SDMA2_RELAX_ORDERING_LUT__RESERVED76_MASK                                                             0x000000C0L
#define SDMA2_RELAX_ORDERING_LUT__POLL_MEM_MASK                                                               0x00000100L
#define SDMA2_RELAX_ORDERING_LUT__COND_EXE_MASK                                                               0x00000200L
#define SDMA2_RELAX_ORDERING_LUT__ATOMIC_MASK                                                                 0x00000400L
#define SDMA2_RELAX_ORDERING_LUT__CONST_FILL_MASK                                                             0x00000800L
#define SDMA2_RELAX_ORDERING_LUT__PTEPDE_MASK                                                                 0x00001000L
#define SDMA2_RELAX_ORDERING_LUT__TIMESTAMP_MASK                                                              0x00002000L
#define SDMA2_RELAX_ORDERING_LUT__RESERVED_MASK                                                               0x07FFC000L
#define SDMA2_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK                                                           0x08000000L
#define SDMA2_RELAX_ORDERING_LUT__RPTR_WRB_MASK                                                               0x10000000L
#define SDMA2_RELAX_ORDERING_LUT__WPTR_POLL_MASK                                                              0x20000000L
#define SDMA2_RELAX_ORDERING_LUT__IB_FETCH_MASK                                                               0x40000000L
#define SDMA2_RELAX_ORDERING_LUT__RB_FETCH_MASK                                                               0x80000000L
//SDMA2_CHICKEN_BITS_2
#define SDMA2_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT                                                       0x0
#define SDMA2_CHICKEN_BITS_2__CE_BACKWARDS_SIZE_SEL__SHIFT                                                    0x4
#define SDMA2_CHICKEN_BITS_2__CE_DCC_READ_128B_ENABLE__SHIFT                                                  0x5
#define SDMA2_CHICKEN_BITS_2__UTCL1_FORCE_INV_RET_FIFO_FULL_EN__SHIFT                                         0x6
#define SDMA2_CHICKEN_BITS_2__RESERVED0__SHIFT                                                                0x7
#define SDMA2_CHICKEN_BITS_2__LUT_FIFO_AFULL_MARGIN__SHIFT                                                    0xb
#define SDMA2_CHICKEN_BITS_2__LEGACY_WPTR_POLL_BEHAVIOR__SHIFT                                                0xf
#define SDMA2_CHICKEN_BITS_2__RB_FIFO_WATERMARK__SHIFT                                                        0x10
#define SDMA2_CHICKEN_BITS_2__IB_FIFO_WATERMARK__SHIFT                                                        0x12
#define SDMA2_CHICKEN_BITS_2__REPEATER_FGCG_EN__SHIFT                                                         0x14
#define SDMA2_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN__SHIFT                                                     0x15
#define SDMA2_CHICKEN_BITS_2__RESERVED__SHIFT                                                                 0x16
#define SDMA2_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK                                                         0x0000000FL
#define SDMA2_CHICKEN_BITS_2__CE_BACKWARDS_SIZE_SEL_MASK                                                      0x00000010L
#define SDMA2_CHICKEN_BITS_2__CE_DCC_READ_128B_ENABLE_MASK                                                    0x00000020L
#define SDMA2_CHICKEN_BITS_2__UTCL1_FORCE_INV_RET_FIFO_FULL_EN_MASK                                           0x00000040L
#define SDMA2_CHICKEN_BITS_2__RESERVED0_MASK                                                                  0x00000780L
#define SDMA2_CHICKEN_BITS_2__LUT_FIFO_AFULL_MARGIN_MASK                                                      0x00007800L
#define SDMA2_CHICKEN_BITS_2__LEGACY_WPTR_POLL_BEHAVIOR_MASK                                                  0x00008000L
#define SDMA2_CHICKEN_BITS_2__RB_FIFO_WATERMARK_MASK                                                          0x00030000L
#define SDMA2_CHICKEN_BITS_2__IB_FIFO_WATERMARK_MASK                                                          0x000C0000L
#define SDMA2_CHICKEN_BITS_2__REPEATER_FGCG_EN_MASK                                                           0x00100000L
#define SDMA2_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN_MASK                                                       0x00200000L
#define SDMA2_CHICKEN_BITS_2__RESERVED_MASK                                                                   0xFFC00000L
//SDMA2_STATUS3_REG
#define SDMA2_STATUS3_REG__CMD_OP_STATUS__SHIFT                                                               0x0
#define SDMA2_STATUS3_REG__PREV_VM_CMD__SHIFT                                                                 0x10
#define SDMA2_STATUS3_REG__EXCEPTION_IDLE__SHIFT                                                              0x14
#define SDMA2_STATUS3_REG__AQL_PREV_CMD_IDLE__SHIFT                                                           0x15
#define SDMA2_STATUS3_REG__TLBI_IDLE__SHIFT                                                                   0x16
#define SDMA2_STATUS3_REG__GCR_IDLE__SHIFT                                                                    0x17
#define SDMA2_STATUS3_REG__INVREQ_IDLE__SHIFT                                                                 0x18
#define SDMA2_STATUS3_REG__QUEUE_ID_MATCH__SHIFT                                                              0x19
#define SDMA2_STATUS3_REG__INT_QUEUE_ID__SHIFT                                                                0x1a
#define SDMA2_STATUS3_REG__CMD_OP_STATUS_MASK                                                                 0x0000FFFFL
#define SDMA2_STATUS3_REG__PREV_VM_CMD_MASK                                                                   0x000F0000L
#define SDMA2_STATUS3_REG__EXCEPTION_IDLE_MASK                                                                0x00100000L
#define SDMA2_STATUS3_REG__AQL_PREV_CMD_IDLE_MASK                                                             0x00200000L
#define SDMA2_STATUS3_REG__TLBI_IDLE_MASK                                                                     0x00400000L
#define SDMA2_STATUS3_REG__GCR_IDLE_MASK                                                                      0x00800000L
#define SDMA2_STATUS3_REG__INVREQ_IDLE_MASK                                                                   0x01000000L
#define SDMA2_STATUS3_REG__QUEUE_ID_MATCH_MASK                                                                0x02000000L
#define SDMA2_STATUS3_REG__INT_QUEUE_ID_MASK                                                                  0x3C000000L
//SDMA2_PHYSICAL_ADDR_LO
#define SDMA2_PHYSICAL_ADDR_LO__D_VALID__SHIFT                                                                0x0
#define SDMA2_PHYSICAL_ADDR_LO__DIRTY__SHIFT                                                                  0x1
#define SDMA2_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT                                                              0x2
#define SDMA2_PHYSICAL_ADDR_LO__ADDR__SHIFT                                                                   0xc
#define SDMA2_PHYSICAL_ADDR_LO__D_VALID_MASK                                                                  0x00000001L
#define SDMA2_PHYSICAL_ADDR_LO__DIRTY_MASK                                                                    0x00000002L
#define SDMA2_PHYSICAL_ADDR_LO__PHY_VALID_MASK                                                                0x00000004L
#define SDMA2_PHYSICAL_ADDR_LO__ADDR_MASK                                                                     0xFFFFF000L
//SDMA2_PHYSICAL_ADDR_HI
#define SDMA2_PHYSICAL_ADDR_HI__ADDR__SHIFT                                                                   0x0
#define SDMA2_PHYSICAL_ADDR_HI__ADDR_MASK                                                                     0x0000FFFFL
//SDMA2_PHASE2_QUANTUM
#define SDMA2_PHASE2_QUANTUM__UNIT__SHIFT                                                                     0x0
#define SDMA2_PHASE2_QUANTUM__VALUE__SHIFT                                                                    0x8
#define SDMA2_PHASE2_QUANTUM__PREFER__SHIFT                                                                   0x1e
#define SDMA2_PHASE2_QUANTUM__UNIT_MASK                                                                       0x0000000FL
#define SDMA2_PHASE2_QUANTUM__VALUE_MASK                                                                      0x00FFFF00L
#define SDMA2_PHASE2_QUANTUM__PREFER_MASK                                                                     0x40000000L
//SDMA2_ERROR_LOG
#define SDMA2_ERROR_LOG__OVERRIDE__SHIFT                                                                      0x0
#define SDMA2_ERROR_LOG__STATUS__SHIFT                                                                        0x10
#define SDMA2_ERROR_LOG__OVERRIDE_MASK                                                                        0x0000FFFFL
#define SDMA2_ERROR_LOG__STATUS_MASK                                                                          0xFFFF0000L
//SDMA2_PUB_DUMMY_REG0
#define SDMA2_PUB_DUMMY_REG0__VALUE__SHIFT                                                                    0x0
#define SDMA2_PUB_DUMMY_REG0__VALUE_MASK                                                                      0xFFFFFFFFL
//SDMA2_PUB_DUMMY_REG1
#define SDMA2_PUB_DUMMY_REG1__VALUE__SHIFT                                                                    0x0
#define SDMA2_PUB_DUMMY_REG1__VALUE_MASK                                                                      0xFFFFFFFFL
//SDMA2_PUB_DUMMY_REG2
#define SDMA2_PUB_DUMMY_REG2__VALUE__SHIFT                                                                    0x0
#define SDMA2_PUB_DUMMY_REG2__VALUE_MASK                                                                      0xFFFFFFFFL
//SDMA2_PUB_DUMMY_REG3
#define SDMA2_PUB_DUMMY_REG3__VALUE__SHIFT                                                                    0x0
#define SDMA2_PUB_DUMMY_REG3__VALUE_MASK                                                                      0xFFFFFFFFL
//SDMA2_F32_COUNTER
#define SDMA2_F32_COUNTER__VALUE__SHIFT                                                                       0x0
#define SDMA2_F32_COUNTER__VALUE_MASK                                                                         0xFFFFFFFFL
//SDMA2_CRD_CNTL
#define SDMA2_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT                                                                0x7
#define SDMA2_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT                                                                0xd
#define SDMA2_CRD_CNTL__CH_WRREQ_CREDIT__SHIFT                                                                0x13
#define SDMA2_CRD_CNTL__CH_RDREQ_CREDIT__SHIFT                                                                0x19
#define SDMA2_CRD_CNTL__MC_WRREQ_CREDIT_MASK                                                                  0x00001F80L
#define SDMA2_CRD_CNTL__MC_RDREQ_CREDIT_MASK                                                                  0x0007E000L
#define SDMA2_CRD_CNTL__CH_WRREQ_CREDIT_MASK                                                                  0x01F80000L
#define SDMA2_CRD_CNTL__CH_RDREQ_CREDIT_MASK                                                                  0x7E000000L
//SDMA2_AQL_STATUS
#define SDMA2_AQL_STATUS__COMPLETE_SIGNAL_EMPTY__SHIFT                                                        0x0
#define SDMA2_AQL_STATUS__INVALID_CMD_EMPTY__SHIFT                                                            0x1
#define SDMA2_AQL_STATUS__COMPLETE_SIGNAL_EMPTY_MASK                                                          0x00000001L
#define SDMA2_AQL_STATUS__INVALID_CMD_EMPTY_MASK                                                              0x00000002L
//SDMA2_EA_DBIT_ADDR_DATA
#define SDMA2_EA_DBIT_ADDR_DATA__VALUE__SHIFT                                                                 0x0
#define SDMA2_EA_DBIT_ADDR_DATA__VALUE_MASK                                                                   0xFFFFFFFFL
//SDMA2_EA_DBIT_ADDR_INDEX
#define SDMA2_EA_DBIT_ADDR_INDEX__VALUE__SHIFT                                                                0x0
#define SDMA2_EA_DBIT_ADDR_INDEX__VALUE_MASK                                                                  0x00000007L
//SDMA2_TLBI_GCR_CNTL
#define SDMA2_TLBI_GCR_CNTL__TLBI_CMD_DW__SHIFT                                                               0x0
#define SDMA2_TLBI_GCR_CNTL__GCR_CMD_DW__SHIFT                                                                0x4
#define SDMA2_TLBI_GCR_CNTL__GCR_CLKEN_CYCLE__SHIFT                                                           0x8
#define SDMA2_TLBI_GCR_CNTL__TLBI_CREDIT__SHIFT                                                               0x10
#define SDMA2_TLBI_GCR_CNTL__GCR_CREDIT__SHIFT                                                                0x18
#define SDMA2_TLBI_GCR_CNTL__TLBI_CMD_DW_MASK                                                                 0x0000000FL
#define SDMA2_TLBI_GCR_CNTL__GCR_CMD_DW_MASK                                                                  0x000000F0L
#define SDMA2_TLBI_GCR_CNTL__GCR_CLKEN_CYCLE_MASK                                                             0x00000F00L
#define SDMA2_TLBI_GCR_CNTL__TLBI_CREDIT_MASK                                                                 0x00FF0000L
#define SDMA2_TLBI_GCR_CNTL__GCR_CREDIT_MASK                                                                  0xFF000000L
//SDMA2_TILING_CONFIG
#define SDMA2_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT                                                      0x4
#define SDMA2_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK                                                        0x00000070L
//SDMA2_INT_STATUS
#define SDMA2_INT_STATUS__DATA__SHIFT                                                                         0x0
#define SDMA2_INT_STATUS__DATA_MASK                                                                           0xFFFFFFFFL
//SDMA2_HOLE_ADDR_LO
#define SDMA2_HOLE_ADDR_LO__VALUE__SHIFT                                                                      0x0
#define SDMA2_HOLE_ADDR_LO__VALUE_MASK                                                                        0xFFFFFFFFL
//SDMA2_HOLE_ADDR_HI
#define SDMA2_HOLE_ADDR_HI__VALUE__SHIFT                                                                      0x0
#define SDMA2_HOLE_ADDR_HI__VALUE_MASK                                                                        0xFFFFFFFFL
//SDMA2_CLOCK_GATING_REG
#define SDMA2_CLOCK_GATING_REG__DYN_CLK_GATE_STATUS__SHIFT                                                    0x0
#define SDMA2_CLOCK_GATING_REG__PTR_CLK_GATE_STATUS__SHIFT                                                    0x1
#define SDMA2_CLOCK_GATING_REG__CE_CLK_GATE_STATUS__SHIFT                                                     0x2
#define SDMA2_CLOCK_GATING_REG__CE_BC_CLK_GATE_STATUS__SHIFT                                                  0x3
#define SDMA2_CLOCK_GATING_REG__CE_NBC_CLK_GATE_STATUS__SHIFT                                                 0x4
#define SDMA2_CLOCK_GATING_REG__REG_CLK_GATE_STATUS__SHIFT                                                    0x5
#define SDMA2_CLOCK_GATING_REG__DYN_CLK_GATE_STATUS_MASK                                                      0x00000001L
#define SDMA2_CLOCK_GATING_REG__PTR_CLK_GATE_STATUS_MASK                                                      0x00000002L
#define SDMA2_CLOCK_GATING_REG__CE_CLK_GATE_STATUS_MASK                                                       0x00000004L
#define SDMA2_CLOCK_GATING_REG__CE_BC_CLK_GATE_STATUS_MASK                                                    0x00000008L
#define SDMA2_CLOCK_GATING_REG__CE_NBC_CLK_GATE_STATUS_MASK                                                   0x00000010L
#define SDMA2_CLOCK_GATING_REG__REG_CLK_GATE_STATUS_MASK                                                      0x00000020L
//SDMA2_STATUS4_REG
#define SDMA2_STATUS4_REG__IDLE__SHIFT                                                                        0x0
#define SDMA2_STATUS4_REG__IH_OUTSTANDING__SHIFT                                                              0x2
#define SDMA2_STATUS4_REG__SEM_OUTSTANDING__SHIFT                                                             0x3
#define SDMA2_STATUS4_REG__CH_RD_OUTSTANDING__SHIFT                                                           0x4
#define SDMA2_STATUS4_REG__CH_WR_OUTSTANDING__SHIFT                                                           0x5
#define SDMA2_STATUS4_REG__GCR_OUTSTANDING__SHIFT                                                             0x6
#define SDMA2_STATUS4_REG__TLBI_OUTSTANDING__SHIFT                                                            0x7
#define SDMA2_STATUS4_REG__UTCL2_RD_OUTSTANDING__SHIFT                                                        0x8
#define SDMA2_STATUS4_REG__UTCL2_WR_OUTSTANDING__SHIFT                                                        0x9
#define SDMA2_STATUS4_REG__REG_POLLING__SHIFT                                                                 0xa
#define SDMA2_STATUS4_REG__MEM_POLLING__SHIFT                                                                 0xb
#define SDMA2_STATUS4_REG__UTCL2_RD_XNACK__SHIFT                                                              0xc
#define SDMA2_STATUS4_REG__UTCL2_WR_XNACK__SHIFT                                                              0xe
#define SDMA2_STATUS4_REG__ACTIVE_QUEUE_ID__SHIFT                                                             0x10
#define SDMA2_STATUS4_REG__SRIOV_WATING_RLCV_CMD__SHIFT                                                       0x14
#define SDMA2_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD__SHIFT                                                    0x15
#define SDMA2_STATUS4_REG__IDLE_MASK                                                                          0x00000001L
#define SDMA2_STATUS4_REG__IH_OUTSTANDING_MASK                                                                0x00000004L
#define SDMA2_STATUS4_REG__SEM_OUTSTANDING_MASK                                                               0x00000008L
#define SDMA2_STATUS4_REG__CH_RD_OUTSTANDING_MASK                                                             0x00000010L
#define SDMA2_STATUS4_REG__CH_WR_OUTSTANDING_MASK                                                             0x00000020L
#define SDMA2_STATUS4_REG__GCR_OUTSTANDING_MASK                                                               0x00000040L
#define SDMA2_STATUS4_REG__TLBI_OUTSTANDING_MASK                                                              0x00000080L
#define SDMA2_STATUS4_REG__UTCL2_RD_OUTSTANDING_MASK                                                          0x00000100L
#define SDMA2_STATUS4_REG__UTCL2_WR_OUTSTANDING_MASK                                                          0x00000200L
#define SDMA2_STATUS4_REG__REG_POLLING_MASK                                                                   0x00000400L
#define SDMA2_STATUS4_REG__MEM_POLLING_MASK                                                                   0x00000800L
#define SDMA2_STATUS4_REG__UTCL2_RD_XNACK_MASK                                                                0x00003000L
#define SDMA2_STATUS4_REG__UTCL2_WR_XNACK_MASK                                                                0x0000C000L
#define SDMA2_STATUS4_REG__ACTIVE_QUEUE_ID_MASK                                                               0x000F0000L
#define SDMA2_STATUS4_REG__SRIOV_WATING_RLCV_CMD_MASK                                                         0x00100000L
#define SDMA2_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD_MASK                                                      0x00200000L
//SDMA2_SCRATCH_RAM_DATA
#define SDMA2_SCRATCH_RAM_DATA__DATA__SHIFT                                                                   0x0
#define SDMA2_SCRATCH_RAM_DATA__DATA_MASK                                                                     0xFFFFFFFFL
//SDMA2_SCRATCH_RAM_ADDR
#define SDMA2_SCRATCH_RAM_ADDR__ADDR__SHIFT                                                                   0x0
#define SDMA2_SCRATCH_RAM_ADDR__ADDR_MASK                                                                     0x000003FFL
//SDMA2_TIMESTAMP_CNTL
#define SDMA2_TIMESTAMP_CNTL__CAPTURE__SHIFT                                                                  0x0
#define SDMA2_TIMESTAMP_CNTL__CAPTURE_MASK                                                                    0x00000001L
//SDMA2_STATUS5_REG
#define SDMA2_STATUS5_REG__GFX_RB_ENABLE_STATUS__SHIFT                                                        0x0
#define SDMA2_STATUS5_REG__PAGE_RB_ENABLE_STATUS__SHIFT                                                       0x1
#define SDMA2_STATUS5_REG__RLC0_RB_ENABLE_STATUS__SHIFT                                                       0x2
#define SDMA2_STATUS5_REG__RLC1_RB_ENABLE_STATUS__SHIFT                                                       0x3
#define SDMA2_STATUS5_REG__RLC2_RB_ENABLE_STATUS__SHIFT                                                       0x4
#define SDMA2_STATUS5_REG__RLC3_RB_ENABLE_STATUS__SHIFT                                                       0x5
#define SDMA2_STATUS5_REG__RLC4_RB_ENABLE_STATUS__SHIFT                                                       0x6
#define SDMA2_STATUS5_REG__RLC5_RB_ENABLE_STATUS__SHIFT                                                       0x7
#define SDMA2_STATUS5_REG__RLC6_RB_ENABLE_STATUS__SHIFT                                                       0x8
#define SDMA2_STATUS5_REG__RLC7_RB_ENABLE_STATUS__SHIFT                                                       0x9
#define SDMA2_STATUS5_REG__ACTIVE_QUEUE_ID__SHIFT                                                             0x10
#define SDMA2_STATUS5_REG__GFX_RB_ENABLE_STATUS_MASK                                                          0x00000001L
#define SDMA2_STATUS5_REG__PAGE_RB_ENABLE_STATUS_MASK                                                         0x00000002L
#define SDMA2_STATUS5_REG__RLC0_RB_ENABLE_STATUS_MASK                                                         0x00000004L
#define SDMA2_STATUS5_REG__RLC1_RB_ENABLE_STATUS_MASK                                                         0x00000008L
#define SDMA2_STATUS5_REG__RLC2_RB_ENABLE_STATUS_MASK                                                         0x00000010L
#define SDMA2_STATUS5_REG__RLC3_RB_ENABLE_STATUS_MASK                                                         0x00000020L
#define SDMA2_STATUS5_REG__RLC4_RB_ENABLE_STATUS_MASK                                                         0x00000040L
#define SDMA2_STATUS5_REG__RLC5_RB_ENABLE_STATUS_MASK                                                         0x00000080L
#define SDMA2_STATUS5_REG__RLC6_RB_ENABLE_STATUS_MASK                                                         0x00000100L
#define SDMA2_STATUS5_REG__RLC7_RB_ENABLE_STATUS_MASK                                                         0x00000200L
#define SDMA2_STATUS5_REG__ACTIVE_QUEUE_ID_MASK                                                               0x000F0000L
//SDMA2_QUEUE_RESET_REQ
#define SDMA2_QUEUE_RESET_REQ__GFX_QUEUE_RESET__SHIFT                                                         0x0
#define SDMA2_QUEUE_RESET_REQ__PAGE_QUEUE_RESET__SHIFT                                                        0x1
#define SDMA2_QUEUE_RESET_REQ__RLC0_QUEUE_RESET__SHIFT                                                        0x2
#define SDMA2_QUEUE_RESET_REQ__RLC1_QUEUE_RESET__SHIFT                                                        0x3
#define SDMA2_QUEUE_RESET_REQ__RLC2_QUEUE_RESET__SHIFT                                                        0x4
#define SDMA2_QUEUE_RESET_REQ__RLC3_QUEUE_RESET__SHIFT                                                        0x5
#define SDMA2_QUEUE_RESET_REQ__RLC4_QUEUE_RESET__SHIFT                                                        0x6
#define SDMA2_QUEUE_RESET_REQ__RLC5_QUEUE_RESET__SHIFT                                                        0x7
#define SDMA2_QUEUE_RESET_REQ__RLC6_QUEUE_RESET__SHIFT                                                        0x8
#define SDMA2_QUEUE_RESET_REQ__RLC7_QUEUE_RESET__SHIFT                                                        0x9
#define SDMA2_QUEUE_RESET_REQ__RESERVED__SHIFT                                                                0xa
#define SDMA2_QUEUE_RESET_REQ__GFX_QUEUE_RESET_MASK                                                           0x00000001L
#define SDMA2_QUEUE_RESET_REQ__PAGE_QUEUE_RESET_MASK                                                          0x00000002L
#define SDMA2_QUEUE_RESET_REQ__RLC0_QUEUE_RESET_MASK                                                          0x00000004L
#define SDMA2_QUEUE_RESET_REQ__RLC1_QUEUE_RESET_MASK                                                          0x00000008L
#define SDMA2_QUEUE_RESET_REQ__RLC2_QUEUE_RESET_MASK                                                          0x00000010L
#define SDMA2_QUEUE_RESET_REQ__RLC3_QUEUE_RESET_MASK                                                          0x00000020L
#define SDMA2_QUEUE_RESET_REQ__RLC4_QUEUE_RESET_MASK                                                          0x00000040L
#define SDMA2_QUEUE_RESET_REQ__RLC5_QUEUE_RESET_MASK                                                          0x00000080L
#define SDMA2_QUEUE_RESET_REQ__RLC6_QUEUE_RESET_MASK                                                          0x00000100L
#define SDMA2_QUEUE_RESET_REQ__RLC7_QUEUE_RESET_MASK                                                          0x00000200L
#define SDMA2_QUEUE_RESET_REQ__RESERVED_MASK                                                                  0xFFFFFC00L
//SDMA2_GFX_RB_CNTL
#define SDMA2_GFX_RB_CNTL__RB_ENABLE__SHIFT                                                                   0x0
#define SDMA2_GFX_RB_CNTL__RB_SIZE__SHIFT                                                                     0x1
#define SDMA2_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                              0x9
#define SDMA2_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                       0xc
#define SDMA2_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                  0xd
#define SDMA2_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                        0x10
#define SDMA2_GFX_RB_CNTL__RB_PRIV__SHIFT                                                                     0x17
#define SDMA2_GFX_RB_CNTL__RB_VMID__SHIFT                                                                     0x18
#define SDMA2_GFX_RB_CNTL__RPTR_WB_IDLE__SHIFT                                                                0x1f
#define SDMA2_GFX_RB_CNTL__RB_ENABLE_MASK                                                                     0x00000001L
#define SDMA2_GFX_RB_CNTL__RB_SIZE_MASK                                                                       0x0000003EL
#define SDMA2_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK                                                                0x00000200L
#define SDMA2_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                         0x00001000L
#define SDMA2_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                    0x00002000L
#define SDMA2_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                          0x001F0000L
#define SDMA2_GFX_RB_CNTL__RB_PRIV_MASK                                                                       0x00800000L
#define SDMA2_GFX_RB_CNTL__RB_VMID_MASK                                                                       0x0F000000L
#define SDMA2_GFX_RB_CNTL__RPTR_WB_IDLE_MASK                                                                  0x80000000L
//SDMA2_GFX_RB_BASE
#define SDMA2_GFX_RB_BASE__ADDR__SHIFT                                                                        0x0
#define SDMA2_GFX_RB_BASE__ADDR_MASK                                                                          0xFFFFFFFFL
//SDMA2_GFX_RB_BASE_HI
#define SDMA2_GFX_RB_BASE_HI__ADDR__SHIFT                                                                     0x0
#define SDMA2_GFX_RB_BASE_HI__ADDR_MASK                                                                       0x00FFFFFFL
//SDMA2_GFX_RB_RPTR
#define SDMA2_GFX_RB_RPTR__OFFSET__SHIFT                                                                      0x0
#define SDMA2_GFX_RB_RPTR__OFFSET_MASK                                                                        0xFFFFFFFFL
//SDMA2_GFX_RB_RPTR_HI
#define SDMA2_GFX_RB_RPTR_HI__OFFSET__SHIFT                                                                   0x0
#define SDMA2_GFX_RB_RPTR_HI__OFFSET_MASK                                                                     0xFFFFFFFFL
//SDMA2_GFX_RB_WPTR
#define SDMA2_GFX_RB_WPTR__OFFSET__SHIFT                                                                      0x0
#define SDMA2_GFX_RB_WPTR__OFFSET_MASK                                                                        0xFFFFFFFFL
//SDMA2_GFX_RB_WPTR_HI
#define SDMA2_GFX_RB_WPTR_HI__OFFSET__SHIFT                                                                   0x0
#define SDMA2_GFX_RB_WPTR_HI__OFFSET_MASK                                                                     0xFFFFFFFFL
//SDMA2_GFX_RB_WPTR_POLL_CNTL
#define SDMA2_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                            0x0
#define SDMA2_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                       0x1
#define SDMA2_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                   0x2
#define SDMA2_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                         0x4
#define SDMA2_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                   0x10
#define SDMA2_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                              0x00000001L
#define SDMA2_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                         0x00000002L
#define SDMA2_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                     0x00000004L
#define SDMA2_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                           0x0000FFF0L
#define SDMA2_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                     0xFFFF0000L
//SDMA2_GFX_RB_RPTR_ADDR_HI
#define SDMA2_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                                0x0
#define SDMA2_GFX_RB_RPTR_ADDR_HI__ADDR_MASK                                                                  0xFFFFFFFFL
//SDMA2_GFX_RB_RPTR_ADDR_LO
#define SDMA2_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                                0x2
#define SDMA2_GFX_RB_RPTR_ADDR_LO__ADDR_MASK                                                                  0xFFFFFFFCL
//SDMA2_GFX_IB_CNTL
#define SDMA2_GFX_IB_CNTL__IB_ENABLE__SHIFT                                                                   0x0
#define SDMA2_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                              0x4
#define SDMA2_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                            0x8
#define SDMA2_GFX_IB_CNTL__CMD_VMID__SHIFT                                                                    0x10
#define SDMA2_GFX_IB_CNTL__IB_ENABLE_MASK                                                                     0x00000001L
#define SDMA2_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK                                                                0x00000010L
#define SDMA2_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                              0x00000100L
#define SDMA2_GFX_IB_CNTL__CMD_VMID_MASK                                                                      0x000F0000L
//SDMA2_GFX_IB_RPTR
#define SDMA2_GFX_IB_RPTR__OFFSET__SHIFT                                                                      0x2
#define SDMA2_GFX_IB_RPTR__OFFSET_MASK                                                                        0x003FFFFCL
//SDMA2_GFX_IB_OFFSET
#define SDMA2_GFX_IB_OFFSET__OFFSET__SHIFT                                                                    0x2
#define SDMA2_GFX_IB_OFFSET__OFFSET_MASK                                                                      0x003FFFFCL
//SDMA2_GFX_IB_BASE_LO
#define SDMA2_GFX_IB_BASE_LO__ADDR__SHIFT                                                                     0x5
#define SDMA2_GFX_IB_BASE_LO__ADDR_MASK                                                                       0xFFFFFFE0L
//SDMA2_GFX_IB_BASE_HI
#define SDMA2_GFX_IB_BASE_HI__ADDR__SHIFT                                                                     0x0
#define SDMA2_GFX_IB_BASE_HI__ADDR_MASK                                                                       0xFFFFFFFFL
//SDMA2_GFX_IB_SIZE
#define SDMA2_GFX_IB_SIZE__SIZE__SHIFT                                                                        0x0
#define SDMA2_GFX_IB_SIZE__SIZE_MASK                                                                          0x000FFFFFL
//SDMA2_GFX_SKIP_CNTL
#define SDMA2_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT                                                                0x0
#define SDMA2_GFX_SKIP_CNTL__SKIP_COUNT_MASK                                                                  0x000FFFFFL
//SDMA2_GFX_CONTEXT_STATUS
#define SDMA2_GFX_CONTEXT_STATUS__SELECTED__SHIFT                                                             0x0
#define SDMA2_GFX_CONTEXT_STATUS__IDLE__SHIFT                                                                 0x2
#define SDMA2_GFX_CONTEXT_STATUS__EXPIRED__SHIFT                                                              0x3
#define SDMA2_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT                                                            0x4
#define SDMA2_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                           0x7
#define SDMA2_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                          0x8
#define SDMA2_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT                                                            0x9
#define SDMA2_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                      0xa
#define SDMA2_GFX_CONTEXT_STATUS__SELECTED_MASK                                                               0x00000001L
#define SDMA2_GFX_CONTEXT_STATUS__IDLE_MASK                                                                   0x00000004L
#define SDMA2_GFX_CONTEXT_STATUS__EXPIRED_MASK                                                                0x00000008L
#define SDMA2_GFX_CONTEXT_STATUS__EXCEPTION_MASK                                                              0x00000070L
#define SDMA2_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                             0x00000080L
#define SDMA2_GFX_CONTEXT_STATUS__CTXSW_READY_MASK                                                            0x00000100L
#define SDMA2_GFX_CONTEXT_STATUS__PREEMPTED_MASK                                                              0x00000200L
#define SDMA2_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                        0x00000400L
//SDMA2_GFX_DOORBELL
#define SDMA2_GFX_DOORBELL__ENABLE__SHIFT                                                                     0x1c
#define SDMA2_GFX_DOORBELL__CAPTURED__SHIFT                                                                   0x1e
#define SDMA2_GFX_DOORBELL__ENABLE_MASK                                                                       0x10000000L
#define SDMA2_GFX_DOORBELL__CAPTURED_MASK                                                                     0x40000000L
//SDMA2_GFX_CONTEXT_CNTL
#define SDMA2_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT                                                             0x10
#define SDMA2_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT                                                            0x18
#define SDMA2_GFX_CONTEXT_CNTL__RESUME_CTX_MASK                                                               0x00010000L
#define SDMA2_GFX_CONTEXT_CNTL__SESSION_SEL_MASK                                                              0x0F000000L
//SDMA2_GFX_STATUS
#define SDMA2_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                       0x0
#define SDMA2_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                          0x8
#define SDMA2_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                         0x000000FFL
#define SDMA2_GFX_STATUS__WPTR_UPDATE_PENDING_MASK                                                            0x00000100L
//SDMA2_GFX_DOORBELL_LOG
#define SDMA2_GFX_DOORBELL_LOG__BE_ERROR__SHIFT                                                               0x0
#define SDMA2_GFX_DOORBELL_LOG__DATA__SHIFT                                                                   0x2
#define SDMA2_GFX_DOORBELL_LOG__BE_ERROR_MASK                                                                 0x00000001L
#define SDMA2_GFX_DOORBELL_LOG__DATA_MASK                                                                     0xFFFFFFFCL
//SDMA2_GFX_WATERMARK
#define SDMA2_GFX_WATERMARK__RD_OUTSTANDING__SHIFT                                                            0x0
#define SDMA2_GFX_WATERMARK__WR_OUTSTANDING__SHIFT                                                            0x10
#define SDMA2_GFX_WATERMARK__RD_OUTSTANDING_MASK                                                              0x00000FFFL
#define SDMA2_GFX_WATERMARK__WR_OUTSTANDING_MASK                                                              0x03FF0000L
//SDMA2_GFX_DOORBELL_OFFSET
#define SDMA2_GFX_DOORBELL_OFFSET__OFFSET__SHIFT                                                              0x2
#define SDMA2_GFX_DOORBELL_OFFSET__OFFSET_MASK                                                                0x0FFFFFFCL
//SDMA2_GFX_CSA_ADDR_LO
#define SDMA2_GFX_CSA_ADDR_LO__ADDR__SHIFT                                                                    0x2
#define SDMA2_GFX_CSA_ADDR_LO__ADDR_MASK                                                                      0xFFFFFFFCL
//SDMA2_GFX_CSA_ADDR_HI
#define SDMA2_GFX_CSA_ADDR_HI__ADDR__SHIFT                                                                    0x0
#define SDMA2_GFX_CSA_ADDR_HI__ADDR_MASK                                                                      0xFFFFFFFFL
//SDMA2_GFX_IB_SUB_REMAIN
#define SDMA2_GFX_IB_SUB_REMAIN__SIZE__SHIFT                                                                  0x0
#define SDMA2_GFX_IB_SUB_REMAIN__SIZE_MASK                                                                    0x00003FFFL
//SDMA2_GFX_PREEMPT
#define SDMA2_GFX_PREEMPT__IB_PREEMPT__SHIFT                                                                  0x0
#define SDMA2_GFX_PREEMPT__IB_PREEMPT_MASK                                                                    0x00000001L
//SDMA2_GFX_DUMMY_REG
#define SDMA2_GFX_DUMMY_REG__DUMMY__SHIFT                                                                     0x0
#define SDMA2_GFX_DUMMY_REG__DUMMY_MASK                                                                       0xFFFFFFFFL
//SDMA2_GFX_RB_WPTR_POLL_ADDR_HI
#define SDMA2_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                           0x0
#define SDMA2_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                             0xFFFFFFFFL
//SDMA2_GFX_RB_WPTR_POLL_ADDR_LO
#define SDMA2_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                           0x2
#define SDMA2_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                             0xFFFFFFFCL
//SDMA2_GFX_RB_AQL_CNTL
#define SDMA2_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                              0x0
#define SDMA2_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                         0x1
#define SDMA2_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                             0x8
#define SDMA2_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                   0x10
#define SDMA2_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT                                             0x11
#define SDMA2_GFX_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT                                                          0x12
#define SDMA2_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK                                                                0x00000001L
#define SDMA2_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                           0x000000FEL
#define SDMA2_GFX_RB_AQL_CNTL__PACKET_STEP_MASK                                                               0x0000FF00L
#define SDMA2_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                     0x00010000L
#define SDMA2_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK                                               0x00020000L
#define SDMA2_GFX_RB_AQL_CNTL__OVERLAP_ENABLE_MASK                                                            0x00040000L
//SDMA2_GFX_MINOR_PTR_UPDATE
#define SDMA2_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                             0x0
#define SDMA2_GFX_MINOR_PTR_UPDATE__ENABLE_MASK                                                               0x00000001L
//SDMA2_GFX_MIDCMD_DATA0
#define SDMA2_GFX_MIDCMD_DATA0__DATA0__SHIFT                                                                  0x0
#define SDMA2_GFX_MIDCMD_DATA0__DATA0_MASK                                                                    0xFFFFFFFFL
//SDMA2_GFX_MIDCMD_DATA1
#define SDMA2_GFX_MIDCMD_DATA1__DATA1__SHIFT                                                                  0x0
#define SDMA2_GFX_MIDCMD_DATA1__DATA1_MASK                                                                    0xFFFFFFFFL
//SDMA2_GFX_MIDCMD_DATA2
#define SDMA2_GFX_MIDCMD_DATA2__DATA2__SHIFT                                                                  0x0
#define SDMA2_GFX_MIDCMD_DATA2__DATA2_MASK                                                                    0xFFFFFFFFL
//SDMA2_GFX_MIDCMD_DATA3
#define SDMA2_GFX_MIDCMD_DATA3__DATA3__SHIFT                                                                  0x0
#define SDMA2_GFX_MIDCMD_DATA3__DATA3_MASK                                                                    0xFFFFFFFFL
//SDMA2_GFX_MIDCMD_DATA4
#define SDMA2_GFX_MIDCMD_DATA4__DATA4__SHIFT                                                                  0x0
#define SDMA2_GFX_MIDCMD_DATA4__DATA4_MASK                                                                    0xFFFFFFFFL
//SDMA2_GFX_MIDCMD_DATA5
#define SDMA2_GFX_MIDCMD_DATA5__DATA5__SHIFT                                                                  0x0
#define SDMA2_GFX_MIDCMD_DATA5__DATA5_MASK                                                                    0xFFFFFFFFL
//SDMA2_GFX_MIDCMD_DATA6
#define SDMA2_GFX_MIDCMD_DATA6__DATA6__SHIFT                                                                  0x0
#define SDMA2_GFX_MIDCMD_DATA6__DATA6_MASK                                                                    0xFFFFFFFFL
//SDMA2_GFX_MIDCMD_DATA7
#define SDMA2_GFX_MIDCMD_DATA7__DATA7__SHIFT                                                                  0x0
#define SDMA2_GFX_MIDCMD_DATA7__DATA7_MASK                                                                    0xFFFFFFFFL
//SDMA2_GFX_MIDCMD_DATA8
#define SDMA2_GFX_MIDCMD_DATA8__DATA8__SHIFT                                                                  0x0
#define SDMA2_GFX_MIDCMD_DATA8__DATA8_MASK                                                                    0xFFFFFFFFL
//SDMA2_GFX_MIDCMD_DATA9
#define SDMA2_GFX_MIDCMD_DATA9__DATA9__SHIFT                                                                  0x0
#define SDMA2_GFX_MIDCMD_DATA9__DATA9_MASK                                                                    0xFFFFFFFFL
//SDMA2_GFX_MIDCMD_DATA10
#define SDMA2_GFX_MIDCMD_DATA10__DATA10__SHIFT                                                                0x0
#define SDMA2_GFX_MIDCMD_DATA10__DATA10_MASK                                                                  0xFFFFFFFFL
//SDMA2_GFX_MIDCMD_CNTL
#define SDMA2_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT                                                              0x0
#define SDMA2_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT                                                               0x1
#define SDMA2_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                             0x4
#define SDMA2_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                           0x8
#define SDMA2_GFX_MIDCMD_CNTL__DATA_VALID_MASK                                                                0x00000001L
#define SDMA2_GFX_MIDCMD_CNTL__COPY_MODE_MASK                                                                 0x00000002L
#define SDMA2_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK                                                               0x000000F0L
#define SDMA2_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                             0x00000100L
//SDMA2_PAGE_RB_CNTL
#define SDMA2_PAGE_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
#define SDMA2_PAGE_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
#define SDMA2_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
#define SDMA2_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
#define SDMA2_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
#define SDMA2_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
#define SDMA2_PAGE_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
#define SDMA2_PAGE_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
#define SDMA2_PAGE_RB_CNTL__RPTR_WB_IDLE__SHIFT                                                               0x1f
#define SDMA2_PAGE_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
#define SDMA2_PAGE_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
#define SDMA2_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
#define SDMA2_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
#define SDMA2_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
#define SDMA2_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
#define SDMA2_PAGE_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
#define SDMA2_PAGE_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
#define SDMA2_PAGE_RB_CNTL__RPTR_WB_IDLE_MASK                                                                 0x80000000L
//SDMA2_PAGE_RB_BASE
#define SDMA2_PAGE_RB_BASE__ADDR__SHIFT                                                                       0x0
#define SDMA2_PAGE_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
//SDMA2_PAGE_RB_BASE_HI
#define SDMA2_PAGE_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA2_PAGE_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
//SDMA2_PAGE_RB_RPTR
#define SDMA2_PAGE_RB_RPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA2_PAGE_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA2_PAGE_RB_RPTR_HI
#define SDMA2_PAGE_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA2_PAGE_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA2_PAGE_RB_WPTR
#define SDMA2_PAGE_RB_WPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA2_PAGE_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA2_PAGE_RB_WPTR_HI
#define SDMA2_PAGE_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA2_PAGE_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA2_PAGE_RB_WPTR_POLL_CNTL
#define SDMA2_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
#define SDMA2_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
#define SDMA2_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
#define SDMA2_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
#define SDMA2_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
#define SDMA2_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
#define SDMA2_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
#define SDMA2_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
#define SDMA2_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
#define SDMA2_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
//SDMA2_PAGE_RB_RPTR_ADDR_HI
#define SDMA2_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
#define SDMA2_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
//SDMA2_PAGE_RB_RPTR_ADDR_LO
#define SDMA2_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
#define SDMA2_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
//SDMA2_PAGE_IB_CNTL
#define SDMA2_PAGE_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
#define SDMA2_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
#define SDMA2_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
#define SDMA2_PAGE_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
#define SDMA2_PAGE_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
#define SDMA2_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
#define SDMA2_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
#define SDMA2_PAGE_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
//SDMA2_PAGE_IB_RPTR
#define SDMA2_PAGE_IB_RPTR__OFFSET__SHIFT                                                                     0x2
#define SDMA2_PAGE_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
//SDMA2_PAGE_IB_OFFSET
#define SDMA2_PAGE_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
#define SDMA2_PAGE_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
//SDMA2_PAGE_IB_BASE_LO
#define SDMA2_PAGE_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
#define SDMA2_PAGE_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
//SDMA2_PAGE_IB_BASE_HI
#define SDMA2_PAGE_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA2_PAGE_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
//SDMA2_PAGE_IB_SIZE
#define SDMA2_PAGE_IB_SIZE__SIZE__SHIFT                                                                       0x0
#define SDMA2_PAGE_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
//SDMA2_PAGE_SKIP_CNTL
#define SDMA2_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
#define SDMA2_PAGE_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
//SDMA2_PAGE_CONTEXT_STATUS
#define SDMA2_PAGE_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
#define SDMA2_PAGE_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
#define SDMA2_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
#define SDMA2_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
#define SDMA2_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
#define SDMA2_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
#define SDMA2_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
#define SDMA2_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
#define SDMA2_PAGE_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
#define SDMA2_PAGE_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
#define SDMA2_PAGE_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
#define SDMA2_PAGE_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
#define SDMA2_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
#define SDMA2_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
#define SDMA2_PAGE_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
#define SDMA2_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
//SDMA2_PAGE_DOORBELL
#define SDMA2_PAGE_DOORBELL__ENABLE__SHIFT                                                                    0x1c
#define SDMA2_PAGE_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
#define SDMA2_PAGE_DOORBELL__ENABLE_MASK                                                                      0x10000000L
#define SDMA2_PAGE_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
//SDMA2_PAGE_STATUS
#define SDMA2_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
#define SDMA2_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
#define SDMA2_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
#define SDMA2_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
//SDMA2_PAGE_DOORBELL_LOG
#define SDMA2_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
#define SDMA2_PAGE_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
#define SDMA2_PAGE_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
#define SDMA2_PAGE_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
//SDMA2_PAGE_WATERMARK
#define SDMA2_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
#define SDMA2_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
#define SDMA2_PAGE_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
#define SDMA2_PAGE_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
//SDMA2_PAGE_DOORBELL_OFFSET
#define SDMA2_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
#define SDMA2_PAGE_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
//SDMA2_PAGE_CSA_ADDR_LO
#define SDMA2_PAGE_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
#define SDMA2_PAGE_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
//SDMA2_PAGE_CSA_ADDR_HI
#define SDMA2_PAGE_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
#define SDMA2_PAGE_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
//SDMA2_PAGE_IB_SUB_REMAIN
#define SDMA2_PAGE_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
#define SDMA2_PAGE_IB_SUB_REMAIN__SIZE_MASK                                                                   0x00003FFFL
//SDMA2_PAGE_PREEMPT
#define SDMA2_PAGE_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
#define SDMA2_PAGE_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
//SDMA2_PAGE_DUMMY_REG
#define SDMA2_PAGE_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
#define SDMA2_PAGE_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
//SDMA2_PAGE_RB_WPTR_POLL_ADDR_HI
#define SDMA2_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
#define SDMA2_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
//SDMA2_PAGE_RB_WPTR_POLL_ADDR_LO
#define SDMA2_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
#define SDMA2_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
//SDMA2_PAGE_RB_AQL_CNTL
#define SDMA2_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
#define SDMA2_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
#define SDMA2_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
#define SDMA2_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                  0x10
#define SDMA2_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT                                            0x11
#define SDMA2_PAGE_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT                                                         0x12
#define SDMA2_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
#define SDMA2_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
#define SDMA2_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
#define SDMA2_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                    0x00010000L
#define SDMA2_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK                                              0x00020000L
#define SDMA2_PAGE_RB_AQL_CNTL__OVERLAP_ENABLE_MASK                                                           0x00040000L
//SDMA2_PAGE_MINOR_PTR_UPDATE
#define SDMA2_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
#define SDMA2_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
//SDMA2_PAGE_MIDCMD_DATA0
#define SDMA2_PAGE_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
#define SDMA2_PAGE_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
//SDMA2_PAGE_MIDCMD_DATA1
#define SDMA2_PAGE_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
#define SDMA2_PAGE_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
//SDMA2_PAGE_MIDCMD_DATA2
#define SDMA2_PAGE_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
#define SDMA2_PAGE_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
//SDMA2_PAGE_MIDCMD_DATA3
#define SDMA2_PAGE_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
#define SDMA2_PAGE_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
//SDMA2_PAGE_MIDCMD_DATA4
#define SDMA2_PAGE_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
#define SDMA2_PAGE_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
//SDMA2_PAGE_MIDCMD_DATA5
#define SDMA2_PAGE_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
#define SDMA2_PAGE_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
//SDMA2_PAGE_MIDCMD_DATA6
#define SDMA2_PAGE_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
#define SDMA2_PAGE_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
//SDMA2_PAGE_MIDCMD_DATA7
#define SDMA2_PAGE_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
#define SDMA2_PAGE_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
//SDMA2_PAGE_MIDCMD_DATA8
#define SDMA2_PAGE_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
#define SDMA2_PAGE_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
//SDMA2_PAGE_MIDCMD_DATA9
#define SDMA2_PAGE_MIDCMD_DATA9__DATA9__SHIFT                                                                 0x0
#define SDMA2_PAGE_MIDCMD_DATA9__DATA9_MASK                                                                   0xFFFFFFFFL
//SDMA2_PAGE_MIDCMD_DATA10
#define SDMA2_PAGE_MIDCMD_DATA10__DATA10__SHIFT                                                               0x0
#define SDMA2_PAGE_MIDCMD_DATA10__DATA10_MASK                                                                 0xFFFFFFFFL
//SDMA2_PAGE_MIDCMD_CNTL
#define SDMA2_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
#define SDMA2_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
#define SDMA2_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
#define SDMA2_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
#define SDMA2_PAGE_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
#define SDMA2_PAGE_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
#define SDMA2_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
#define SDMA2_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
//SDMA2_RLC0_RB_CNTL
#define SDMA2_RLC0_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
#define SDMA2_RLC0_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
#define SDMA2_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
#define SDMA2_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
#define SDMA2_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
#define SDMA2_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
#define SDMA2_RLC0_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
#define SDMA2_RLC0_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
#define SDMA2_RLC0_RB_CNTL__RPTR_WB_IDLE__SHIFT                                                               0x1f
#define SDMA2_RLC0_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
#define SDMA2_RLC0_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
#define SDMA2_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
#define SDMA2_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
#define SDMA2_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
#define SDMA2_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
#define SDMA2_RLC0_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
#define SDMA2_RLC0_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
#define SDMA2_RLC0_RB_CNTL__RPTR_WB_IDLE_MASK                                                                 0x80000000L
//SDMA2_RLC0_RB_BASE
#define SDMA2_RLC0_RB_BASE__ADDR__SHIFT                                                                       0x0
#define SDMA2_RLC0_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
//SDMA2_RLC0_RB_BASE_HI
#define SDMA2_RLC0_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA2_RLC0_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
//SDMA2_RLC0_RB_RPTR
#define SDMA2_RLC0_RB_RPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA2_RLC0_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA2_RLC0_RB_RPTR_HI
#define SDMA2_RLC0_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA2_RLC0_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA2_RLC0_RB_WPTR
#define SDMA2_RLC0_RB_WPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA2_RLC0_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA2_RLC0_RB_WPTR_HI
#define SDMA2_RLC0_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA2_RLC0_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA2_RLC0_RB_WPTR_POLL_CNTL
#define SDMA2_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
#define SDMA2_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
#define SDMA2_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
#define SDMA2_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
#define SDMA2_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
#define SDMA2_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
#define SDMA2_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
#define SDMA2_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
#define SDMA2_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
#define SDMA2_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
//SDMA2_RLC0_RB_RPTR_ADDR_HI
#define SDMA2_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
#define SDMA2_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
//SDMA2_RLC0_RB_RPTR_ADDR_LO
#define SDMA2_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
#define SDMA2_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
//SDMA2_RLC0_IB_CNTL
#define SDMA2_RLC0_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
#define SDMA2_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
#define SDMA2_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
#define SDMA2_RLC0_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
#define SDMA2_RLC0_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
#define SDMA2_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
#define SDMA2_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
#define SDMA2_RLC0_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
//SDMA2_RLC0_IB_RPTR
#define SDMA2_RLC0_IB_RPTR__OFFSET__SHIFT                                                                     0x2
#define SDMA2_RLC0_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
//SDMA2_RLC0_IB_OFFSET
#define SDMA2_RLC0_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
#define SDMA2_RLC0_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
//SDMA2_RLC0_IB_BASE_LO
#define SDMA2_RLC0_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
#define SDMA2_RLC0_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
//SDMA2_RLC0_IB_BASE_HI
#define SDMA2_RLC0_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA2_RLC0_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
//SDMA2_RLC0_IB_SIZE
#define SDMA2_RLC0_IB_SIZE__SIZE__SHIFT                                                                       0x0
#define SDMA2_RLC0_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
//SDMA2_RLC0_SKIP_CNTL
#define SDMA2_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
#define SDMA2_RLC0_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
//SDMA2_RLC0_CONTEXT_STATUS
#define SDMA2_RLC0_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
#define SDMA2_RLC0_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
#define SDMA2_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
#define SDMA2_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
#define SDMA2_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
#define SDMA2_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
#define SDMA2_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
#define SDMA2_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
#define SDMA2_RLC0_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
#define SDMA2_RLC0_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
#define SDMA2_RLC0_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
#define SDMA2_RLC0_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
#define SDMA2_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
#define SDMA2_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
#define SDMA2_RLC0_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
#define SDMA2_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
//SDMA2_RLC0_DOORBELL
#define SDMA2_RLC0_DOORBELL__ENABLE__SHIFT                                                                    0x1c
#define SDMA2_RLC0_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
#define SDMA2_RLC0_DOORBELL__ENABLE_MASK                                                                      0x10000000L
#define SDMA2_RLC0_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
//SDMA2_RLC0_STATUS
#define SDMA2_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
#define SDMA2_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
#define SDMA2_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
#define SDMA2_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
//SDMA2_RLC0_DOORBELL_LOG
#define SDMA2_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
#define SDMA2_RLC0_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
#define SDMA2_RLC0_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
#define SDMA2_RLC0_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
//SDMA2_RLC0_WATERMARK
#define SDMA2_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
#define SDMA2_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
#define SDMA2_RLC0_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
#define SDMA2_RLC0_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
//SDMA2_RLC0_DOORBELL_OFFSET
#define SDMA2_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
#define SDMA2_RLC0_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
//SDMA2_RLC0_CSA_ADDR_LO
#define SDMA2_RLC0_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
#define SDMA2_RLC0_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
//SDMA2_RLC0_CSA_ADDR_HI
#define SDMA2_RLC0_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
#define SDMA2_RLC0_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
//SDMA2_RLC0_IB_SUB_REMAIN
#define SDMA2_RLC0_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
#define SDMA2_RLC0_IB_SUB_REMAIN__SIZE_MASK                                                                   0x00003FFFL
//SDMA2_RLC0_PREEMPT
#define SDMA2_RLC0_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
#define SDMA2_RLC0_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
//SDMA2_RLC0_DUMMY_REG
#define SDMA2_RLC0_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
#define SDMA2_RLC0_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
//SDMA2_RLC0_RB_WPTR_POLL_ADDR_HI
#define SDMA2_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
#define SDMA2_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
//SDMA2_RLC0_RB_WPTR_POLL_ADDR_LO
#define SDMA2_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
#define SDMA2_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
//SDMA2_RLC0_RB_AQL_CNTL
#define SDMA2_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
#define SDMA2_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
#define SDMA2_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
#define SDMA2_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                  0x10
#define SDMA2_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT                                            0x11
#define SDMA2_RLC0_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT                                                         0x12
#define SDMA2_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
#define SDMA2_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
#define SDMA2_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
#define SDMA2_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                    0x00010000L
#define SDMA2_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK                                              0x00020000L
#define SDMA2_RLC0_RB_AQL_CNTL__OVERLAP_ENABLE_MASK                                                           0x00040000L
//SDMA2_RLC0_MINOR_PTR_UPDATE
#define SDMA2_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
#define SDMA2_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
//SDMA2_RLC0_MIDCMD_DATA0
#define SDMA2_RLC0_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
#define SDMA2_RLC0_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC0_MIDCMD_DATA1
#define SDMA2_RLC0_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
#define SDMA2_RLC0_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC0_MIDCMD_DATA2
#define SDMA2_RLC0_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
#define SDMA2_RLC0_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC0_MIDCMD_DATA3
#define SDMA2_RLC0_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
#define SDMA2_RLC0_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC0_MIDCMD_DATA4
#define SDMA2_RLC0_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
#define SDMA2_RLC0_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC0_MIDCMD_DATA5
#define SDMA2_RLC0_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
#define SDMA2_RLC0_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC0_MIDCMD_DATA6
#define SDMA2_RLC0_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
#define SDMA2_RLC0_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC0_MIDCMD_DATA7
#define SDMA2_RLC0_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
#define SDMA2_RLC0_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC0_MIDCMD_DATA8
#define SDMA2_RLC0_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
#define SDMA2_RLC0_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC0_MIDCMD_DATA9
#define SDMA2_RLC0_MIDCMD_DATA9__DATA9__SHIFT                                                                 0x0
#define SDMA2_RLC0_MIDCMD_DATA9__DATA9_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC0_MIDCMD_DATA10
#define SDMA2_RLC0_MIDCMD_DATA10__DATA10__SHIFT                                                               0x0
#define SDMA2_RLC0_MIDCMD_DATA10__DATA10_MASK                                                                 0xFFFFFFFFL
//SDMA2_RLC0_MIDCMD_CNTL
#define SDMA2_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
#define SDMA2_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
#define SDMA2_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
#define SDMA2_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
#define SDMA2_RLC0_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
#define SDMA2_RLC0_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
#define SDMA2_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
#define SDMA2_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
//SDMA2_RLC1_RB_CNTL
#define SDMA2_RLC1_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
#define SDMA2_RLC1_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
#define SDMA2_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
#define SDMA2_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
#define SDMA2_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
#define SDMA2_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
#define SDMA2_RLC1_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
#define SDMA2_RLC1_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
#define SDMA2_RLC1_RB_CNTL__RPTR_WB_IDLE__SHIFT                                                               0x1f
#define SDMA2_RLC1_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
#define SDMA2_RLC1_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
#define SDMA2_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
#define SDMA2_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
#define SDMA2_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
#define SDMA2_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
#define SDMA2_RLC1_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
#define SDMA2_RLC1_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
#define SDMA2_RLC1_RB_CNTL__RPTR_WB_IDLE_MASK                                                                 0x80000000L
//SDMA2_RLC1_RB_BASE
#define SDMA2_RLC1_RB_BASE__ADDR__SHIFT                                                                       0x0
#define SDMA2_RLC1_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
//SDMA2_RLC1_RB_BASE_HI
#define SDMA2_RLC1_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA2_RLC1_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
//SDMA2_RLC1_RB_RPTR
#define SDMA2_RLC1_RB_RPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA2_RLC1_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA2_RLC1_RB_RPTR_HI
#define SDMA2_RLC1_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA2_RLC1_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA2_RLC1_RB_WPTR
#define SDMA2_RLC1_RB_WPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA2_RLC1_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA2_RLC1_RB_WPTR_HI
#define SDMA2_RLC1_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA2_RLC1_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA2_RLC1_RB_WPTR_POLL_CNTL
#define SDMA2_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
#define SDMA2_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
#define SDMA2_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
#define SDMA2_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
#define SDMA2_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
#define SDMA2_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
#define SDMA2_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
#define SDMA2_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
#define SDMA2_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
#define SDMA2_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
//SDMA2_RLC1_RB_RPTR_ADDR_HI
#define SDMA2_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
#define SDMA2_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
//SDMA2_RLC1_RB_RPTR_ADDR_LO
#define SDMA2_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
#define SDMA2_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
//SDMA2_RLC1_IB_CNTL
#define SDMA2_RLC1_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
#define SDMA2_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
#define SDMA2_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
#define SDMA2_RLC1_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
#define SDMA2_RLC1_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
#define SDMA2_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
#define SDMA2_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
#define SDMA2_RLC1_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
//SDMA2_RLC1_IB_RPTR
#define SDMA2_RLC1_IB_RPTR__OFFSET__SHIFT                                                                     0x2
#define SDMA2_RLC1_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
//SDMA2_RLC1_IB_OFFSET
#define SDMA2_RLC1_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
#define SDMA2_RLC1_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
//SDMA2_RLC1_IB_BASE_LO
#define SDMA2_RLC1_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
#define SDMA2_RLC1_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
//SDMA2_RLC1_IB_BASE_HI
#define SDMA2_RLC1_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA2_RLC1_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
//SDMA2_RLC1_IB_SIZE
#define SDMA2_RLC1_IB_SIZE__SIZE__SHIFT                                                                       0x0
#define SDMA2_RLC1_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
//SDMA2_RLC1_SKIP_CNTL
#define SDMA2_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
#define SDMA2_RLC1_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
//SDMA2_RLC1_CONTEXT_STATUS
#define SDMA2_RLC1_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
#define SDMA2_RLC1_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
#define SDMA2_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
#define SDMA2_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
#define SDMA2_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
#define SDMA2_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
#define SDMA2_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
#define SDMA2_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
#define SDMA2_RLC1_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
#define SDMA2_RLC1_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
#define SDMA2_RLC1_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
#define SDMA2_RLC1_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
#define SDMA2_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
#define SDMA2_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
#define SDMA2_RLC1_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
#define SDMA2_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
//SDMA2_RLC1_DOORBELL
#define SDMA2_RLC1_DOORBELL__ENABLE__SHIFT                                                                    0x1c
#define SDMA2_RLC1_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
#define SDMA2_RLC1_DOORBELL__ENABLE_MASK                                                                      0x10000000L
#define SDMA2_RLC1_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
//SDMA2_RLC1_STATUS
#define SDMA2_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
#define SDMA2_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
#define SDMA2_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
#define SDMA2_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
//SDMA2_RLC1_DOORBELL_LOG
#define SDMA2_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
#define SDMA2_RLC1_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
#define SDMA2_RLC1_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
#define SDMA2_RLC1_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
//SDMA2_RLC1_WATERMARK
#define SDMA2_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
#define SDMA2_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
#define SDMA2_RLC1_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
#define SDMA2_RLC1_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
//SDMA2_RLC1_DOORBELL_OFFSET
#define SDMA2_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
#define SDMA2_RLC1_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
//SDMA2_RLC1_CSA_ADDR_LO
#define SDMA2_RLC1_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
#define SDMA2_RLC1_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
//SDMA2_RLC1_CSA_ADDR_HI
#define SDMA2_RLC1_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
#define SDMA2_RLC1_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
//SDMA2_RLC1_IB_SUB_REMAIN
#define SDMA2_RLC1_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
#define SDMA2_RLC1_IB_SUB_REMAIN__SIZE_MASK                                                                   0x00003FFFL
//SDMA2_RLC1_PREEMPT
#define SDMA2_RLC1_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
#define SDMA2_RLC1_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
//SDMA2_RLC1_DUMMY_REG
#define SDMA2_RLC1_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
#define SDMA2_RLC1_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
//SDMA2_RLC1_RB_WPTR_POLL_ADDR_HI
#define SDMA2_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
#define SDMA2_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
//SDMA2_RLC1_RB_WPTR_POLL_ADDR_LO
#define SDMA2_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
#define SDMA2_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
//SDMA2_RLC1_RB_AQL_CNTL
#define SDMA2_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
#define SDMA2_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
#define SDMA2_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
#define SDMA2_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                  0x10
#define SDMA2_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT                                            0x11
#define SDMA2_RLC1_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT                                                         0x12
#define SDMA2_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
#define SDMA2_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
#define SDMA2_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
#define SDMA2_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                    0x00010000L
#define SDMA2_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK                                              0x00020000L
#define SDMA2_RLC1_RB_AQL_CNTL__OVERLAP_ENABLE_MASK                                                           0x00040000L
//SDMA2_RLC1_MINOR_PTR_UPDATE
#define SDMA2_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
#define SDMA2_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
//SDMA2_RLC1_MIDCMD_DATA0
#define SDMA2_RLC1_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
#define SDMA2_RLC1_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC1_MIDCMD_DATA1
#define SDMA2_RLC1_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
#define SDMA2_RLC1_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC1_MIDCMD_DATA2
#define SDMA2_RLC1_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
#define SDMA2_RLC1_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC1_MIDCMD_DATA3
#define SDMA2_RLC1_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
#define SDMA2_RLC1_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC1_MIDCMD_DATA4
#define SDMA2_RLC1_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
#define SDMA2_RLC1_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC1_MIDCMD_DATA5
#define SDMA2_RLC1_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
#define SDMA2_RLC1_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC1_MIDCMD_DATA6
#define SDMA2_RLC1_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
#define SDMA2_RLC1_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC1_MIDCMD_DATA7
#define SDMA2_RLC1_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
#define SDMA2_RLC1_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC1_MIDCMD_DATA8
#define SDMA2_RLC1_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
#define SDMA2_RLC1_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC1_MIDCMD_DATA9
#define SDMA2_RLC1_MIDCMD_DATA9__DATA9__SHIFT                                                                 0x0
#define SDMA2_RLC1_MIDCMD_DATA9__DATA9_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC1_MIDCMD_DATA10
#define SDMA2_RLC1_MIDCMD_DATA10__DATA10__SHIFT                                                               0x0
#define SDMA2_RLC1_MIDCMD_DATA10__DATA10_MASK                                                                 0xFFFFFFFFL
//SDMA2_RLC1_MIDCMD_CNTL
#define SDMA2_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
#define SDMA2_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
#define SDMA2_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
#define SDMA2_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
#define SDMA2_RLC1_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
#define SDMA2_RLC1_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
#define SDMA2_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
#define SDMA2_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
//SDMA2_RLC2_RB_CNTL
#define SDMA2_RLC2_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
#define SDMA2_RLC2_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
#define SDMA2_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
#define SDMA2_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
#define SDMA2_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
#define SDMA2_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
#define SDMA2_RLC2_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
#define SDMA2_RLC2_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
#define SDMA2_RLC2_RB_CNTL__RPTR_WB_IDLE__SHIFT                                                               0x1f
#define SDMA2_RLC2_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
#define SDMA2_RLC2_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
#define SDMA2_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
#define SDMA2_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
#define SDMA2_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
#define SDMA2_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
#define SDMA2_RLC2_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
#define SDMA2_RLC2_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
#define SDMA2_RLC2_RB_CNTL__RPTR_WB_IDLE_MASK                                                                 0x80000000L
//SDMA2_RLC2_RB_BASE
#define SDMA2_RLC2_RB_BASE__ADDR__SHIFT                                                                       0x0
#define SDMA2_RLC2_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
//SDMA2_RLC2_RB_BASE_HI
#define SDMA2_RLC2_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA2_RLC2_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
//SDMA2_RLC2_RB_RPTR
#define SDMA2_RLC2_RB_RPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA2_RLC2_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA2_RLC2_RB_RPTR_HI
#define SDMA2_RLC2_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA2_RLC2_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA2_RLC2_RB_WPTR
#define SDMA2_RLC2_RB_WPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA2_RLC2_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA2_RLC2_RB_WPTR_HI
#define SDMA2_RLC2_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA2_RLC2_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA2_RLC2_RB_WPTR_POLL_CNTL
#define SDMA2_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
#define SDMA2_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
#define SDMA2_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
#define SDMA2_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
#define SDMA2_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
#define SDMA2_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
#define SDMA2_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
#define SDMA2_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
#define SDMA2_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
#define SDMA2_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
//SDMA2_RLC2_RB_RPTR_ADDR_HI
#define SDMA2_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
#define SDMA2_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
//SDMA2_RLC2_RB_RPTR_ADDR_LO
#define SDMA2_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
#define SDMA2_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
//SDMA2_RLC2_IB_CNTL
#define SDMA2_RLC2_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
#define SDMA2_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
#define SDMA2_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
#define SDMA2_RLC2_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
#define SDMA2_RLC2_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
#define SDMA2_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
#define SDMA2_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
#define SDMA2_RLC2_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
//SDMA2_RLC2_IB_RPTR
#define SDMA2_RLC2_IB_RPTR__OFFSET__SHIFT                                                                     0x2
#define SDMA2_RLC2_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
//SDMA2_RLC2_IB_OFFSET
#define SDMA2_RLC2_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
#define SDMA2_RLC2_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
//SDMA2_RLC2_IB_BASE_LO
#define SDMA2_RLC2_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
#define SDMA2_RLC2_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
//SDMA2_RLC2_IB_BASE_HI
#define SDMA2_RLC2_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA2_RLC2_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
//SDMA2_RLC2_IB_SIZE
#define SDMA2_RLC2_IB_SIZE__SIZE__SHIFT                                                                       0x0
#define SDMA2_RLC2_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
//SDMA2_RLC2_SKIP_CNTL
#define SDMA2_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
#define SDMA2_RLC2_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
//SDMA2_RLC2_CONTEXT_STATUS
#define SDMA2_RLC2_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
#define SDMA2_RLC2_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
#define SDMA2_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
#define SDMA2_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
#define SDMA2_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
#define SDMA2_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
#define SDMA2_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
#define SDMA2_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
#define SDMA2_RLC2_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
#define SDMA2_RLC2_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
#define SDMA2_RLC2_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
#define SDMA2_RLC2_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
#define SDMA2_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
#define SDMA2_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
#define SDMA2_RLC2_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
#define SDMA2_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
//SDMA2_RLC2_DOORBELL
#define SDMA2_RLC2_DOORBELL__ENABLE__SHIFT                                                                    0x1c
#define SDMA2_RLC2_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
#define SDMA2_RLC2_DOORBELL__ENABLE_MASK                                                                      0x10000000L
#define SDMA2_RLC2_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
//SDMA2_RLC2_STATUS
#define SDMA2_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
#define SDMA2_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
#define SDMA2_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
#define SDMA2_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
//SDMA2_RLC2_DOORBELL_LOG
#define SDMA2_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
#define SDMA2_RLC2_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
#define SDMA2_RLC2_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
#define SDMA2_RLC2_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
//SDMA2_RLC2_WATERMARK
#define SDMA2_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
#define SDMA2_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
#define SDMA2_RLC2_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
#define SDMA2_RLC2_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
//SDMA2_RLC2_DOORBELL_OFFSET
#define SDMA2_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
#define SDMA2_RLC2_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
//SDMA2_RLC2_CSA_ADDR_LO
#define SDMA2_RLC2_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
#define SDMA2_RLC2_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
//SDMA2_RLC2_CSA_ADDR_HI
#define SDMA2_RLC2_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
#define SDMA2_RLC2_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
//SDMA2_RLC2_IB_SUB_REMAIN
#define SDMA2_RLC2_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
#define SDMA2_RLC2_IB_SUB_REMAIN__SIZE_MASK                                                                   0x00003FFFL
//SDMA2_RLC2_PREEMPT
#define SDMA2_RLC2_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
#define SDMA2_RLC2_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
//SDMA2_RLC2_DUMMY_REG
#define SDMA2_RLC2_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
#define SDMA2_RLC2_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
//SDMA2_RLC2_RB_WPTR_POLL_ADDR_HI
#define SDMA2_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
#define SDMA2_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
//SDMA2_RLC2_RB_WPTR_POLL_ADDR_LO
#define SDMA2_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
#define SDMA2_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
//SDMA2_RLC2_RB_AQL_CNTL
#define SDMA2_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
#define SDMA2_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
#define SDMA2_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
#define SDMA2_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                  0x10
#define SDMA2_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT                                            0x11
#define SDMA2_RLC2_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT                                                         0x12
#define SDMA2_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
#define SDMA2_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
#define SDMA2_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
#define SDMA2_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                    0x00010000L
#define SDMA2_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK                                              0x00020000L
#define SDMA2_RLC2_RB_AQL_CNTL__OVERLAP_ENABLE_MASK                                                           0x00040000L
//SDMA2_RLC2_MINOR_PTR_UPDATE
#define SDMA2_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
#define SDMA2_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
//SDMA2_RLC2_MIDCMD_DATA0
#define SDMA2_RLC2_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
#define SDMA2_RLC2_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC2_MIDCMD_DATA1
#define SDMA2_RLC2_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
#define SDMA2_RLC2_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC2_MIDCMD_DATA2
#define SDMA2_RLC2_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
#define SDMA2_RLC2_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC2_MIDCMD_DATA3
#define SDMA2_RLC2_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
#define SDMA2_RLC2_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC2_MIDCMD_DATA4
#define SDMA2_RLC2_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
#define SDMA2_RLC2_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC2_MIDCMD_DATA5
#define SDMA2_RLC2_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
#define SDMA2_RLC2_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC2_MIDCMD_DATA6
#define SDMA2_RLC2_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
#define SDMA2_RLC2_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC2_MIDCMD_DATA7
#define SDMA2_RLC2_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
#define SDMA2_RLC2_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC2_MIDCMD_DATA8
#define SDMA2_RLC2_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
#define SDMA2_RLC2_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC2_MIDCMD_DATA9
#define SDMA2_RLC2_MIDCMD_DATA9__DATA9__SHIFT                                                                 0x0
#define SDMA2_RLC2_MIDCMD_DATA9__DATA9_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC2_MIDCMD_DATA10
#define SDMA2_RLC2_MIDCMD_DATA10__DATA10__SHIFT                                                               0x0
#define SDMA2_RLC2_MIDCMD_DATA10__DATA10_MASK                                                                 0xFFFFFFFFL
//SDMA2_RLC2_MIDCMD_CNTL
#define SDMA2_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
#define SDMA2_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
#define SDMA2_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
#define SDMA2_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
#define SDMA2_RLC2_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
#define SDMA2_RLC2_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
#define SDMA2_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
#define SDMA2_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
//SDMA2_RLC3_RB_CNTL
#define SDMA2_RLC3_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
#define SDMA2_RLC3_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
#define SDMA2_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
#define SDMA2_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
#define SDMA2_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
#define SDMA2_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
#define SDMA2_RLC3_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
#define SDMA2_RLC3_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
#define SDMA2_RLC3_RB_CNTL__RPTR_WB_IDLE__SHIFT                                                               0x1f
#define SDMA2_RLC3_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
#define SDMA2_RLC3_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
#define SDMA2_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
#define SDMA2_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
#define SDMA2_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
#define SDMA2_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
#define SDMA2_RLC3_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
#define SDMA2_RLC3_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
#define SDMA2_RLC3_RB_CNTL__RPTR_WB_IDLE_MASK                                                                 0x80000000L
//SDMA2_RLC3_RB_BASE
#define SDMA2_RLC3_RB_BASE__ADDR__SHIFT                                                                       0x0
#define SDMA2_RLC3_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
//SDMA2_RLC3_RB_BASE_HI
#define SDMA2_RLC3_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA2_RLC3_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
//SDMA2_RLC3_RB_RPTR
#define SDMA2_RLC3_RB_RPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA2_RLC3_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA2_RLC3_RB_RPTR_HI
#define SDMA2_RLC3_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA2_RLC3_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA2_RLC3_RB_WPTR
#define SDMA2_RLC3_RB_WPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA2_RLC3_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA2_RLC3_RB_WPTR_HI
#define SDMA2_RLC3_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA2_RLC3_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA2_RLC3_RB_WPTR_POLL_CNTL
#define SDMA2_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
#define SDMA2_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
#define SDMA2_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
#define SDMA2_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
#define SDMA2_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
#define SDMA2_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
#define SDMA2_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
#define SDMA2_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
#define SDMA2_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
#define SDMA2_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
//SDMA2_RLC3_RB_RPTR_ADDR_HI
#define SDMA2_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
#define SDMA2_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
//SDMA2_RLC3_RB_RPTR_ADDR_LO
#define SDMA2_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
#define SDMA2_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
//SDMA2_RLC3_IB_CNTL
#define SDMA2_RLC3_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
#define SDMA2_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
#define SDMA2_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
#define SDMA2_RLC3_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
#define SDMA2_RLC3_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
#define SDMA2_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
#define SDMA2_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
#define SDMA2_RLC3_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
//SDMA2_RLC3_IB_RPTR
#define SDMA2_RLC3_IB_RPTR__OFFSET__SHIFT                                                                     0x2
#define SDMA2_RLC3_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
//SDMA2_RLC3_IB_OFFSET
#define SDMA2_RLC3_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
#define SDMA2_RLC3_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
//SDMA2_RLC3_IB_BASE_LO
#define SDMA2_RLC3_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
#define SDMA2_RLC3_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
//SDMA2_RLC3_IB_BASE_HI
#define SDMA2_RLC3_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA2_RLC3_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
//SDMA2_RLC3_IB_SIZE
#define SDMA2_RLC3_IB_SIZE__SIZE__SHIFT                                                                       0x0
#define SDMA2_RLC3_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
//SDMA2_RLC3_SKIP_CNTL
#define SDMA2_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
#define SDMA2_RLC3_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
//SDMA2_RLC3_CONTEXT_STATUS
#define SDMA2_RLC3_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
#define SDMA2_RLC3_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
#define SDMA2_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
#define SDMA2_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
#define SDMA2_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
#define SDMA2_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
#define SDMA2_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
#define SDMA2_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
#define SDMA2_RLC3_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
#define SDMA2_RLC3_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
#define SDMA2_RLC3_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
#define SDMA2_RLC3_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
#define SDMA2_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
#define SDMA2_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
#define SDMA2_RLC3_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
#define SDMA2_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
//SDMA2_RLC3_DOORBELL
#define SDMA2_RLC3_DOORBELL__ENABLE__SHIFT                                                                    0x1c
#define SDMA2_RLC3_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
#define SDMA2_RLC3_DOORBELL__ENABLE_MASK                                                                      0x10000000L
#define SDMA2_RLC3_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
//SDMA2_RLC3_STATUS
#define SDMA2_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
#define SDMA2_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
#define SDMA2_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
#define SDMA2_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
//SDMA2_RLC3_DOORBELL_LOG
#define SDMA2_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
#define SDMA2_RLC3_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
#define SDMA2_RLC3_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
#define SDMA2_RLC3_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
//SDMA2_RLC3_WATERMARK
#define SDMA2_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
#define SDMA2_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
#define SDMA2_RLC3_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
#define SDMA2_RLC3_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
//SDMA2_RLC3_DOORBELL_OFFSET
#define SDMA2_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
#define SDMA2_RLC3_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
//SDMA2_RLC3_CSA_ADDR_LO
#define SDMA2_RLC3_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
#define SDMA2_RLC3_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
//SDMA2_RLC3_CSA_ADDR_HI
#define SDMA2_RLC3_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
#define SDMA2_RLC3_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
//SDMA2_RLC3_IB_SUB_REMAIN
#define SDMA2_RLC3_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
#define SDMA2_RLC3_IB_SUB_REMAIN__SIZE_MASK                                                                   0x00003FFFL
//SDMA2_RLC3_PREEMPT
#define SDMA2_RLC3_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
#define SDMA2_RLC3_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
//SDMA2_RLC3_DUMMY_REG
#define SDMA2_RLC3_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
#define SDMA2_RLC3_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
//SDMA2_RLC3_RB_WPTR_POLL_ADDR_HI
#define SDMA2_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
#define SDMA2_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
//SDMA2_RLC3_RB_WPTR_POLL_ADDR_LO
#define SDMA2_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
#define SDMA2_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
//SDMA2_RLC3_RB_AQL_CNTL
#define SDMA2_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
#define SDMA2_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
#define SDMA2_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
#define SDMA2_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                  0x10
#define SDMA2_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT                                            0x11
#define SDMA2_RLC3_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT                                                         0x12
#define SDMA2_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
#define SDMA2_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
#define SDMA2_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
#define SDMA2_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                    0x00010000L
#define SDMA2_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK                                              0x00020000L
#define SDMA2_RLC3_RB_AQL_CNTL__OVERLAP_ENABLE_MASK                                                           0x00040000L
//SDMA2_RLC3_MINOR_PTR_UPDATE
#define SDMA2_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
#define SDMA2_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
//SDMA2_RLC3_MIDCMD_DATA0
#define SDMA2_RLC3_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
#define SDMA2_RLC3_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC3_MIDCMD_DATA1
#define SDMA2_RLC3_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
#define SDMA2_RLC3_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC3_MIDCMD_DATA2
#define SDMA2_RLC3_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
#define SDMA2_RLC3_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC3_MIDCMD_DATA3
#define SDMA2_RLC3_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
#define SDMA2_RLC3_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC3_MIDCMD_DATA4
#define SDMA2_RLC3_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
#define SDMA2_RLC3_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC3_MIDCMD_DATA5
#define SDMA2_RLC3_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
#define SDMA2_RLC3_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC3_MIDCMD_DATA6
#define SDMA2_RLC3_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
#define SDMA2_RLC3_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC3_MIDCMD_DATA7
#define SDMA2_RLC3_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
#define SDMA2_RLC3_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC3_MIDCMD_DATA8
#define SDMA2_RLC3_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
#define SDMA2_RLC3_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC3_MIDCMD_DATA9
#define SDMA2_RLC3_MIDCMD_DATA9__DATA9__SHIFT                                                                 0x0
#define SDMA2_RLC3_MIDCMD_DATA9__DATA9_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC3_MIDCMD_DATA10
#define SDMA2_RLC3_MIDCMD_DATA10__DATA10__SHIFT                                                               0x0
#define SDMA2_RLC3_MIDCMD_DATA10__DATA10_MASK                                                                 0xFFFFFFFFL
//SDMA2_RLC3_MIDCMD_CNTL
#define SDMA2_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
#define SDMA2_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
#define SDMA2_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
#define SDMA2_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
#define SDMA2_RLC3_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
#define SDMA2_RLC3_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
#define SDMA2_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
#define SDMA2_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
//SDMA2_RLC4_RB_CNTL
#define SDMA2_RLC4_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
#define SDMA2_RLC4_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
#define SDMA2_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
#define SDMA2_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
#define SDMA2_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
#define SDMA2_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
#define SDMA2_RLC4_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
#define SDMA2_RLC4_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
#define SDMA2_RLC4_RB_CNTL__RPTR_WB_IDLE__SHIFT                                                               0x1f
#define SDMA2_RLC4_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
#define SDMA2_RLC4_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
#define SDMA2_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
#define SDMA2_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
#define SDMA2_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
#define SDMA2_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
#define SDMA2_RLC4_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
#define SDMA2_RLC4_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
#define SDMA2_RLC4_RB_CNTL__RPTR_WB_IDLE_MASK                                                                 0x80000000L
//SDMA2_RLC4_RB_BASE
#define SDMA2_RLC4_RB_BASE__ADDR__SHIFT                                                                       0x0
#define SDMA2_RLC4_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
//SDMA2_RLC4_RB_BASE_HI
#define SDMA2_RLC4_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA2_RLC4_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
//SDMA2_RLC4_RB_RPTR
#define SDMA2_RLC4_RB_RPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA2_RLC4_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA2_RLC4_RB_RPTR_HI
#define SDMA2_RLC4_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA2_RLC4_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA2_RLC4_RB_WPTR
#define SDMA2_RLC4_RB_WPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA2_RLC4_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA2_RLC4_RB_WPTR_HI
#define SDMA2_RLC4_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA2_RLC4_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA2_RLC4_RB_WPTR_POLL_CNTL
#define SDMA2_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
#define SDMA2_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
#define SDMA2_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
#define SDMA2_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
#define SDMA2_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
#define SDMA2_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
#define SDMA2_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
#define SDMA2_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
#define SDMA2_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
#define SDMA2_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
//SDMA2_RLC4_RB_RPTR_ADDR_HI
#define SDMA2_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
#define SDMA2_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
//SDMA2_RLC4_RB_RPTR_ADDR_LO
#define SDMA2_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
#define SDMA2_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
//SDMA2_RLC4_IB_CNTL
#define SDMA2_RLC4_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
#define SDMA2_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
#define SDMA2_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
#define SDMA2_RLC4_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
#define SDMA2_RLC4_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
#define SDMA2_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
#define SDMA2_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
#define SDMA2_RLC4_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
//SDMA2_RLC4_IB_RPTR
#define SDMA2_RLC4_IB_RPTR__OFFSET__SHIFT                                                                     0x2
#define SDMA2_RLC4_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
//SDMA2_RLC4_IB_OFFSET
#define SDMA2_RLC4_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
#define SDMA2_RLC4_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
//SDMA2_RLC4_IB_BASE_LO
#define SDMA2_RLC4_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
#define SDMA2_RLC4_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
//SDMA2_RLC4_IB_BASE_HI
#define SDMA2_RLC4_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA2_RLC4_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
//SDMA2_RLC4_IB_SIZE
#define SDMA2_RLC4_IB_SIZE__SIZE__SHIFT                                                                       0x0
#define SDMA2_RLC4_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
//SDMA2_RLC4_SKIP_CNTL
#define SDMA2_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
#define SDMA2_RLC4_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
//SDMA2_RLC4_CONTEXT_STATUS
#define SDMA2_RLC4_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
#define SDMA2_RLC4_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
#define SDMA2_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
#define SDMA2_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
#define SDMA2_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
#define SDMA2_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
#define SDMA2_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
#define SDMA2_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
#define SDMA2_RLC4_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
#define SDMA2_RLC4_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
#define SDMA2_RLC4_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
#define SDMA2_RLC4_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
#define SDMA2_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
#define SDMA2_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
#define SDMA2_RLC4_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
#define SDMA2_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
//SDMA2_RLC4_DOORBELL
#define SDMA2_RLC4_DOORBELL__ENABLE__SHIFT                                                                    0x1c
#define SDMA2_RLC4_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
#define SDMA2_RLC4_DOORBELL__ENABLE_MASK                                                                      0x10000000L
#define SDMA2_RLC4_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
//SDMA2_RLC4_STATUS
#define SDMA2_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
#define SDMA2_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
#define SDMA2_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
#define SDMA2_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
//SDMA2_RLC4_DOORBELL_LOG
#define SDMA2_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
#define SDMA2_RLC4_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
#define SDMA2_RLC4_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
#define SDMA2_RLC4_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
//SDMA2_RLC4_WATERMARK
#define SDMA2_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
#define SDMA2_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
#define SDMA2_RLC4_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
#define SDMA2_RLC4_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
//SDMA2_RLC4_DOORBELL_OFFSET
#define SDMA2_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
#define SDMA2_RLC4_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
//SDMA2_RLC4_CSA_ADDR_LO
#define SDMA2_RLC4_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
#define SDMA2_RLC4_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
//SDMA2_RLC4_CSA_ADDR_HI
#define SDMA2_RLC4_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
#define SDMA2_RLC4_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
//SDMA2_RLC4_IB_SUB_REMAIN
#define SDMA2_RLC4_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
#define SDMA2_RLC4_IB_SUB_REMAIN__SIZE_MASK                                                                   0x00003FFFL
//SDMA2_RLC4_PREEMPT
#define SDMA2_RLC4_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
#define SDMA2_RLC4_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
//SDMA2_RLC4_DUMMY_REG
#define SDMA2_RLC4_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
#define SDMA2_RLC4_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
//SDMA2_RLC4_RB_WPTR_POLL_ADDR_HI
#define SDMA2_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
#define SDMA2_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
//SDMA2_RLC4_RB_WPTR_POLL_ADDR_LO
#define SDMA2_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
#define SDMA2_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
//SDMA2_RLC4_RB_AQL_CNTL
#define SDMA2_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
#define SDMA2_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
#define SDMA2_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
#define SDMA2_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                  0x10
#define SDMA2_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT                                            0x11
#define SDMA2_RLC4_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT                                                         0x12
#define SDMA2_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
#define SDMA2_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
#define SDMA2_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
#define SDMA2_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                    0x00010000L
#define SDMA2_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK                                              0x00020000L
#define SDMA2_RLC4_RB_AQL_CNTL__OVERLAP_ENABLE_MASK                                                           0x00040000L
//SDMA2_RLC4_MINOR_PTR_UPDATE
#define SDMA2_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
#define SDMA2_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
//SDMA2_RLC4_MIDCMD_DATA0
#define SDMA2_RLC4_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
#define SDMA2_RLC4_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC4_MIDCMD_DATA1
#define SDMA2_RLC4_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
#define SDMA2_RLC4_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC4_MIDCMD_DATA2
#define SDMA2_RLC4_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
#define SDMA2_RLC4_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC4_MIDCMD_DATA3
#define SDMA2_RLC4_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
#define SDMA2_RLC4_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC4_MIDCMD_DATA4
#define SDMA2_RLC4_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
#define SDMA2_RLC4_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC4_MIDCMD_DATA5
#define SDMA2_RLC4_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
#define SDMA2_RLC4_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC4_MIDCMD_DATA6
#define SDMA2_RLC4_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
#define SDMA2_RLC4_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC4_MIDCMD_DATA7
#define SDMA2_RLC4_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
#define SDMA2_RLC4_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC4_MIDCMD_DATA8
#define SDMA2_RLC4_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
#define SDMA2_RLC4_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC4_MIDCMD_DATA9
#define SDMA2_RLC4_MIDCMD_DATA9__DATA9__SHIFT                                                                 0x0
#define SDMA2_RLC4_MIDCMD_DATA9__DATA9_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC4_MIDCMD_DATA10
#define SDMA2_RLC4_MIDCMD_DATA10__DATA10__SHIFT                                                               0x0
#define SDMA2_RLC4_MIDCMD_DATA10__DATA10_MASK                                                                 0xFFFFFFFFL
//SDMA2_RLC4_MIDCMD_CNTL
#define SDMA2_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
#define SDMA2_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
#define SDMA2_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
#define SDMA2_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
#define SDMA2_RLC4_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
#define SDMA2_RLC4_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
#define SDMA2_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
#define SDMA2_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
//SDMA2_RLC5_RB_CNTL
#define SDMA2_RLC5_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
#define SDMA2_RLC5_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
#define SDMA2_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
#define SDMA2_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
#define SDMA2_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
#define SDMA2_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
#define SDMA2_RLC5_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
#define SDMA2_RLC5_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
#define SDMA2_RLC5_RB_CNTL__RPTR_WB_IDLE__SHIFT                                                               0x1f
#define SDMA2_RLC5_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
#define SDMA2_RLC5_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
#define SDMA2_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
#define SDMA2_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
#define SDMA2_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
#define SDMA2_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
#define SDMA2_RLC5_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
#define SDMA2_RLC5_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
#define SDMA2_RLC5_RB_CNTL__RPTR_WB_IDLE_MASK                                                                 0x80000000L
//SDMA2_RLC5_RB_BASE
#define SDMA2_RLC5_RB_BASE__ADDR__SHIFT                                                                       0x0
#define SDMA2_RLC5_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
//SDMA2_RLC5_RB_BASE_HI
#define SDMA2_RLC5_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA2_RLC5_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
//SDMA2_RLC5_RB_RPTR
#define SDMA2_RLC5_RB_RPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA2_RLC5_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA2_RLC5_RB_RPTR_HI
#define SDMA2_RLC5_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA2_RLC5_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA2_RLC5_RB_WPTR
#define SDMA2_RLC5_RB_WPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA2_RLC5_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA2_RLC5_RB_WPTR_HI
#define SDMA2_RLC5_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA2_RLC5_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA2_RLC5_RB_WPTR_POLL_CNTL
#define SDMA2_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
#define SDMA2_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
#define SDMA2_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
#define SDMA2_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
#define SDMA2_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
#define SDMA2_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
#define SDMA2_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
#define SDMA2_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
#define SDMA2_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
#define SDMA2_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
//SDMA2_RLC5_RB_RPTR_ADDR_HI
#define SDMA2_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
#define SDMA2_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
//SDMA2_RLC5_RB_RPTR_ADDR_LO
#define SDMA2_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
#define SDMA2_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
//SDMA2_RLC5_IB_CNTL
#define SDMA2_RLC5_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
#define SDMA2_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
#define SDMA2_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
#define SDMA2_RLC5_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
#define SDMA2_RLC5_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
#define SDMA2_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
#define SDMA2_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
#define SDMA2_RLC5_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
//SDMA2_RLC5_IB_RPTR
#define SDMA2_RLC5_IB_RPTR__OFFSET__SHIFT                                                                     0x2
#define SDMA2_RLC5_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
//SDMA2_RLC5_IB_OFFSET
#define SDMA2_RLC5_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
#define SDMA2_RLC5_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
//SDMA2_RLC5_IB_BASE_LO
#define SDMA2_RLC5_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
#define SDMA2_RLC5_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
//SDMA2_RLC5_IB_BASE_HI
#define SDMA2_RLC5_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA2_RLC5_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
//SDMA2_RLC5_IB_SIZE
#define SDMA2_RLC5_IB_SIZE__SIZE__SHIFT                                                                       0x0
#define SDMA2_RLC5_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
//SDMA2_RLC5_SKIP_CNTL
#define SDMA2_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
#define SDMA2_RLC5_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
//SDMA2_RLC5_CONTEXT_STATUS
#define SDMA2_RLC5_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
#define SDMA2_RLC5_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
#define SDMA2_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
#define SDMA2_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
#define SDMA2_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
#define SDMA2_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
#define SDMA2_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
#define SDMA2_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
#define SDMA2_RLC5_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
#define SDMA2_RLC5_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
#define SDMA2_RLC5_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
#define SDMA2_RLC5_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
#define SDMA2_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
#define SDMA2_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
#define SDMA2_RLC5_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
#define SDMA2_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
//SDMA2_RLC5_DOORBELL
#define SDMA2_RLC5_DOORBELL__ENABLE__SHIFT                                                                    0x1c
#define SDMA2_RLC5_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
#define SDMA2_RLC5_DOORBELL__ENABLE_MASK                                                                      0x10000000L
#define SDMA2_RLC5_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
//SDMA2_RLC5_STATUS
#define SDMA2_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
#define SDMA2_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
#define SDMA2_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
#define SDMA2_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
//SDMA2_RLC5_DOORBELL_LOG
#define SDMA2_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
#define SDMA2_RLC5_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
#define SDMA2_RLC5_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
#define SDMA2_RLC5_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
//SDMA2_RLC5_WATERMARK
#define SDMA2_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
#define SDMA2_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
#define SDMA2_RLC5_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
#define SDMA2_RLC5_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
//SDMA2_RLC5_DOORBELL_OFFSET
#define SDMA2_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
#define SDMA2_RLC5_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
//SDMA2_RLC5_CSA_ADDR_LO
#define SDMA2_RLC5_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
#define SDMA2_RLC5_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
//SDMA2_RLC5_CSA_ADDR_HI
#define SDMA2_RLC5_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
#define SDMA2_RLC5_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
//SDMA2_RLC5_IB_SUB_REMAIN
#define SDMA2_RLC5_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
#define SDMA2_RLC5_IB_SUB_REMAIN__SIZE_MASK                                                                   0x00003FFFL
//SDMA2_RLC5_PREEMPT
#define SDMA2_RLC5_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
#define SDMA2_RLC5_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
//SDMA2_RLC5_DUMMY_REG
#define SDMA2_RLC5_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
#define SDMA2_RLC5_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
//SDMA2_RLC5_RB_WPTR_POLL_ADDR_HI
#define SDMA2_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
#define SDMA2_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
//SDMA2_RLC5_RB_WPTR_POLL_ADDR_LO
#define SDMA2_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
#define SDMA2_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
//SDMA2_RLC5_RB_AQL_CNTL
#define SDMA2_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
#define SDMA2_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
#define SDMA2_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
#define SDMA2_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                  0x10
#define SDMA2_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT                                            0x11
#define SDMA2_RLC5_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT                                                         0x12
#define SDMA2_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
#define SDMA2_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
#define SDMA2_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
#define SDMA2_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                    0x00010000L
#define SDMA2_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK                                              0x00020000L
#define SDMA2_RLC5_RB_AQL_CNTL__OVERLAP_ENABLE_MASK                                                           0x00040000L
//SDMA2_RLC5_MINOR_PTR_UPDATE
#define SDMA2_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
#define SDMA2_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
//SDMA2_RLC5_MIDCMD_DATA0
#define SDMA2_RLC5_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
#define SDMA2_RLC5_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC5_MIDCMD_DATA1
#define SDMA2_RLC5_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
#define SDMA2_RLC5_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC5_MIDCMD_DATA2
#define SDMA2_RLC5_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
#define SDMA2_RLC5_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC5_MIDCMD_DATA3
#define SDMA2_RLC5_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
#define SDMA2_RLC5_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC5_MIDCMD_DATA4
#define SDMA2_RLC5_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
#define SDMA2_RLC5_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC5_MIDCMD_DATA5
#define SDMA2_RLC5_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
#define SDMA2_RLC5_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC5_MIDCMD_DATA6
#define SDMA2_RLC5_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
#define SDMA2_RLC5_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC5_MIDCMD_DATA7
#define SDMA2_RLC5_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
#define SDMA2_RLC5_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC5_MIDCMD_DATA8
#define SDMA2_RLC5_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
#define SDMA2_RLC5_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC5_MIDCMD_DATA9
#define SDMA2_RLC5_MIDCMD_DATA9__DATA9__SHIFT                                                                 0x0
#define SDMA2_RLC5_MIDCMD_DATA9__DATA9_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC5_MIDCMD_DATA10
#define SDMA2_RLC5_MIDCMD_DATA10__DATA10__SHIFT                                                               0x0
#define SDMA2_RLC5_MIDCMD_DATA10__DATA10_MASK                                                                 0xFFFFFFFFL
//SDMA2_RLC5_MIDCMD_CNTL
#define SDMA2_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
#define SDMA2_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
#define SDMA2_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
#define SDMA2_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
#define SDMA2_RLC5_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
#define SDMA2_RLC5_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
#define SDMA2_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
#define SDMA2_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
//SDMA2_RLC6_RB_CNTL
#define SDMA2_RLC6_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
#define SDMA2_RLC6_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
#define SDMA2_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
#define SDMA2_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
#define SDMA2_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
#define SDMA2_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
#define SDMA2_RLC6_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
#define SDMA2_RLC6_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
#define SDMA2_RLC6_RB_CNTL__RPTR_WB_IDLE__SHIFT                                                               0x1f
#define SDMA2_RLC6_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
#define SDMA2_RLC6_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
#define SDMA2_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
#define SDMA2_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
#define SDMA2_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
#define SDMA2_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
#define SDMA2_RLC6_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
#define SDMA2_RLC6_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
#define SDMA2_RLC6_RB_CNTL__RPTR_WB_IDLE_MASK                                                                 0x80000000L
//SDMA2_RLC6_RB_BASE
#define SDMA2_RLC6_RB_BASE__ADDR__SHIFT                                                                       0x0
#define SDMA2_RLC6_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
//SDMA2_RLC6_RB_BASE_HI
#define SDMA2_RLC6_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA2_RLC6_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
//SDMA2_RLC6_RB_RPTR
#define SDMA2_RLC6_RB_RPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA2_RLC6_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA2_RLC6_RB_RPTR_HI
#define SDMA2_RLC6_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA2_RLC6_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA2_RLC6_RB_WPTR
#define SDMA2_RLC6_RB_WPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA2_RLC6_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA2_RLC6_RB_WPTR_HI
#define SDMA2_RLC6_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA2_RLC6_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA2_RLC6_RB_WPTR_POLL_CNTL
#define SDMA2_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
#define SDMA2_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
#define SDMA2_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
#define SDMA2_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
#define SDMA2_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
#define SDMA2_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
#define SDMA2_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
#define SDMA2_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
#define SDMA2_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
#define SDMA2_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
//SDMA2_RLC6_RB_RPTR_ADDR_HI
#define SDMA2_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
#define SDMA2_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
//SDMA2_RLC6_RB_RPTR_ADDR_LO
#define SDMA2_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
#define SDMA2_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
//SDMA2_RLC6_IB_CNTL
#define SDMA2_RLC6_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
#define SDMA2_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
#define SDMA2_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
#define SDMA2_RLC6_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
#define SDMA2_RLC6_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
#define SDMA2_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
#define SDMA2_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
#define SDMA2_RLC6_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
//SDMA2_RLC6_IB_RPTR
#define SDMA2_RLC6_IB_RPTR__OFFSET__SHIFT                                                                     0x2
#define SDMA2_RLC6_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
//SDMA2_RLC6_IB_OFFSET
#define SDMA2_RLC6_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
#define SDMA2_RLC6_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
//SDMA2_RLC6_IB_BASE_LO
#define SDMA2_RLC6_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
#define SDMA2_RLC6_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
//SDMA2_RLC6_IB_BASE_HI
#define SDMA2_RLC6_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA2_RLC6_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
//SDMA2_RLC6_IB_SIZE
#define SDMA2_RLC6_IB_SIZE__SIZE__SHIFT                                                                       0x0
#define SDMA2_RLC6_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
//SDMA2_RLC6_SKIP_CNTL
#define SDMA2_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
#define SDMA2_RLC6_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
//SDMA2_RLC6_CONTEXT_STATUS
#define SDMA2_RLC6_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
#define SDMA2_RLC6_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
#define SDMA2_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
#define SDMA2_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
#define SDMA2_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
#define SDMA2_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
#define SDMA2_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
#define SDMA2_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
#define SDMA2_RLC6_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
#define SDMA2_RLC6_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
#define SDMA2_RLC6_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
#define SDMA2_RLC6_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
#define SDMA2_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
#define SDMA2_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
#define SDMA2_RLC6_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
#define SDMA2_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
//SDMA2_RLC6_DOORBELL
#define SDMA2_RLC6_DOORBELL__ENABLE__SHIFT                                                                    0x1c
#define SDMA2_RLC6_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
#define SDMA2_RLC6_DOORBELL__ENABLE_MASK                                                                      0x10000000L
#define SDMA2_RLC6_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
//SDMA2_RLC6_STATUS
#define SDMA2_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
#define SDMA2_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
#define SDMA2_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
#define SDMA2_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
//SDMA2_RLC6_DOORBELL_LOG
#define SDMA2_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
#define SDMA2_RLC6_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
#define SDMA2_RLC6_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
#define SDMA2_RLC6_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
//SDMA2_RLC6_WATERMARK
#define SDMA2_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
#define SDMA2_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
#define SDMA2_RLC6_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
#define SDMA2_RLC6_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
//SDMA2_RLC6_DOORBELL_OFFSET
#define SDMA2_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
#define SDMA2_RLC6_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
//SDMA2_RLC6_CSA_ADDR_LO
#define SDMA2_RLC6_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
#define SDMA2_RLC6_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
//SDMA2_RLC6_CSA_ADDR_HI
#define SDMA2_RLC6_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
#define SDMA2_RLC6_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
//SDMA2_RLC6_IB_SUB_REMAIN
#define SDMA2_RLC6_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
#define SDMA2_RLC6_IB_SUB_REMAIN__SIZE_MASK                                                                   0x00003FFFL
//SDMA2_RLC6_PREEMPT
#define SDMA2_RLC6_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
#define SDMA2_RLC6_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
//SDMA2_RLC6_DUMMY_REG
#define SDMA2_RLC6_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
#define SDMA2_RLC6_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
//SDMA2_RLC6_RB_WPTR_POLL_ADDR_HI
#define SDMA2_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
#define SDMA2_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
//SDMA2_RLC6_RB_WPTR_POLL_ADDR_LO
#define SDMA2_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
#define SDMA2_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
//SDMA2_RLC6_RB_AQL_CNTL
#define SDMA2_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
#define SDMA2_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
#define SDMA2_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
#define SDMA2_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                  0x10
#define SDMA2_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT                                            0x11
#define SDMA2_RLC6_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT                                                         0x12
#define SDMA2_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
#define SDMA2_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
#define SDMA2_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
#define SDMA2_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                    0x00010000L
#define SDMA2_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK                                              0x00020000L
#define SDMA2_RLC6_RB_AQL_CNTL__OVERLAP_ENABLE_MASK                                                           0x00040000L
//SDMA2_RLC6_MINOR_PTR_UPDATE
#define SDMA2_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
#define SDMA2_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
//SDMA2_RLC6_MIDCMD_DATA0
#define SDMA2_RLC6_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
#define SDMA2_RLC6_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC6_MIDCMD_DATA1
#define SDMA2_RLC6_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
#define SDMA2_RLC6_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC6_MIDCMD_DATA2
#define SDMA2_RLC6_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
#define SDMA2_RLC6_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC6_MIDCMD_DATA3
#define SDMA2_RLC6_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
#define SDMA2_RLC6_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC6_MIDCMD_DATA4
#define SDMA2_RLC6_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
#define SDMA2_RLC6_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC6_MIDCMD_DATA5
#define SDMA2_RLC6_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
#define SDMA2_RLC6_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC6_MIDCMD_DATA6
#define SDMA2_RLC6_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
#define SDMA2_RLC6_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC6_MIDCMD_DATA7
#define SDMA2_RLC6_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
#define SDMA2_RLC6_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC6_MIDCMD_DATA8
#define SDMA2_RLC6_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
#define SDMA2_RLC6_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC6_MIDCMD_DATA9
#define SDMA2_RLC6_MIDCMD_DATA9__DATA9__SHIFT                                                                 0x0
#define SDMA2_RLC6_MIDCMD_DATA9__DATA9_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC6_MIDCMD_DATA10
#define SDMA2_RLC6_MIDCMD_DATA10__DATA10__SHIFT                                                               0x0
#define SDMA2_RLC6_MIDCMD_DATA10__DATA10_MASK                                                                 0xFFFFFFFFL
//SDMA2_RLC6_MIDCMD_CNTL
#define SDMA2_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
#define SDMA2_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
#define SDMA2_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
#define SDMA2_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
#define SDMA2_RLC6_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
#define SDMA2_RLC6_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
#define SDMA2_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
#define SDMA2_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
//SDMA2_RLC7_RB_CNTL
#define SDMA2_RLC7_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
#define SDMA2_RLC7_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
#define SDMA2_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
#define SDMA2_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
#define SDMA2_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
#define SDMA2_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
#define SDMA2_RLC7_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
#define SDMA2_RLC7_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
#define SDMA2_RLC7_RB_CNTL__RPTR_WB_IDLE__SHIFT                                                               0x1f
#define SDMA2_RLC7_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
#define SDMA2_RLC7_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
#define SDMA2_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
#define SDMA2_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
#define SDMA2_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
#define SDMA2_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
#define SDMA2_RLC7_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
#define SDMA2_RLC7_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
#define SDMA2_RLC7_RB_CNTL__RPTR_WB_IDLE_MASK                                                                 0x80000000L
//SDMA2_RLC7_RB_BASE
#define SDMA2_RLC7_RB_BASE__ADDR__SHIFT                                                                       0x0
#define SDMA2_RLC7_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
//SDMA2_RLC7_RB_BASE_HI
#define SDMA2_RLC7_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA2_RLC7_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
//SDMA2_RLC7_RB_RPTR
#define SDMA2_RLC7_RB_RPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA2_RLC7_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA2_RLC7_RB_RPTR_HI
#define SDMA2_RLC7_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA2_RLC7_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA2_RLC7_RB_WPTR
#define SDMA2_RLC7_RB_WPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA2_RLC7_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA2_RLC7_RB_WPTR_HI
#define SDMA2_RLC7_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA2_RLC7_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA2_RLC7_RB_WPTR_POLL_CNTL
#define SDMA2_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
#define SDMA2_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
#define SDMA2_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
#define SDMA2_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
#define SDMA2_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
#define SDMA2_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
#define SDMA2_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
#define SDMA2_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
#define SDMA2_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
#define SDMA2_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
//SDMA2_RLC7_RB_RPTR_ADDR_HI
#define SDMA2_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
#define SDMA2_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
//SDMA2_RLC7_RB_RPTR_ADDR_LO
#define SDMA2_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
#define SDMA2_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
//SDMA2_RLC7_IB_CNTL
#define SDMA2_RLC7_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
#define SDMA2_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
#define SDMA2_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
#define SDMA2_RLC7_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
#define SDMA2_RLC7_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
#define SDMA2_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
#define SDMA2_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
#define SDMA2_RLC7_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
//SDMA2_RLC7_IB_RPTR
#define SDMA2_RLC7_IB_RPTR__OFFSET__SHIFT                                                                     0x2
#define SDMA2_RLC7_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
//SDMA2_RLC7_IB_OFFSET
#define SDMA2_RLC7_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
#define SDMA2_RLC7_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
//SDMA2_RLC7_IB_BASE_LO
#define SDMA2_RLC7_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
#define SDMA2_RLC7_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
//SDMA2_RLC7_IB_BASE_HI
#define SDMA2_RLC7_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA2_RLC7_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
//SDMA2_RLC7_IB_SIZE
#define SDMA2_RLC7_IB_SIZE__SIZE__SHIFT                                                                       0x0
#define SDMA2_RLC7_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
//SDMA2_RLC7_SKIP_CNTL
#define SDMA2_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
#define SDMA2_RLC7_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
//SDMA2_RLC7_CONTEXT_STATUS
#define SDMA2_RLC7_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
#define SDMA2_RLC7_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
#define SDMA2_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
#define SDMA2_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
#define SDMA2_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
#define SDMA2_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
#define SDMA2_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
#define SDMA2_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
#define SDMA2_RLC7_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
#define SDMA2_RLC7_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
#define SDMA2_RLC7_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
#define SDMA2_RLC7_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
#define SDMA2_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
#define SDMA2_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
#define SDMA2_RLC7_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
#define SDMA2_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
//SDMA2_RLC7_DOORBELL
#define SDMA2_RLC7_DOORBELL__ENABLE__SHIFT                                                                    0x1c
#define SDMA2_RLC7_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
#define SDMA2_RLC7_DOORBELL__ENABLE_MASK                                                                      0x10000000L
#define SDMA2_RLC7_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
//SDMA2_RLC7_STATUS
#define SDMA2_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
#define SDMA2_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
#define SDMA2_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
#define SDMA2_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
//SDMA2_RLC7_DOORBELL_LOG
#define SDMA2_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
#define SDMA2_RLC7_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
#define SDMA2_RLC7_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
#define SDMA2_RLC7_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
//SDMA2_RLC7_WATERMARK
#define SDMA2_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
#define SDMA2_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
#define SDMA2_RLC7_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
#define SDMA2_RLC7_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
//SDMA2_RLC7_DOORBELL_OFFSET
#define SDMA2_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
#define SDMA2_RLC7_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
//SDMA2_RLC7_CSA_ADDR_LO
#define SDMA2_RLC7_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
#define SDMA2_RLC7_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
//SDMA2_RLC7_CSA_ADDR_HI
#define SDMA2_RLC7_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
#define SDMA2_RLC7_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
//SDMA2_RLC7_IB_SUB_REMAIN
#define SDMA2_RLC7_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
#define SDMA2_RLC7_IB_SUB_REMAIN__SIZE_MASK                                                                   0x00003FFFL
//SDMA2_RLC7_PREEMPT
#define SDMA2_RLC7_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
#define SDMA2_RLC7_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
//SDMA2_RLC7_DUMMY_REG
#define SDMA2_RLC7_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
#define SDMA2_RLC7_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
//SDMA2_RLC7_RB_WPTR_POLL_ADDR_HI
#define SDMA2_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
#define SDMA2_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
//SDMA2_RLC7_RB_WPTR_POLL_ADDR_LO
#define SDMA2_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
#define SDMA2_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
//SDMA2_RLC7_RB_AQL_CNTL
#define SDMA2_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
#define SDMA2_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
#define SDMA2_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
#define SDMA2_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                  0x10
#define SDMA2_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT                                            0x11
#define SDMA2_RLC7_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT                                                         0x12
#define SDMA2_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
#define SDMA2_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
#define SDMA2_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
#define SDMA2_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                    0x00010000L
#define SDMA2_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK                                              0x00020000L
#define SDMA2_RLC7_RB_AQL_CNTL__OVERLAP_ENABLE_MASK                                                           0x00040000L
//SDMA2_RLC7_MINOR_PTR_UPDATE
#define SDMA2_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
#define SDMA2_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
//SDMA2_RLC7_MIDCMD_DATA0
#define SDMA2_RLC7_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
#define SDMA2_RLC7_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC7_MIDCMD_DATA1
#define SDMA2_RLC7_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
#define SDMA2_RLC7_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC7_MIDCMD_DATA2
#define SDMA2_RLC7_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
#define SDMA2_RLC7_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC7_MIDCMD_DATA3
#define SDMA2_RLC7_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
#define SDMA2_RLC7_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC7_MIDCMD_DATA4
#define SDMA2_RLC7_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
#define SDMA2_RLC7_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC7_MIDCMD_DATA5
#define SDMA2_RLC7_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
#define SDMA2_RLC7_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC7_MIDCMD_DATA6
#define SDMA2_RLC7_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
#define SDMA2_RLC7_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC7_MIDCMD_DATA7
#define SDMA2_RLC7_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
#define SDMA2_RLC7_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC7_MIDCMD_DATA8
#define SDMA2_RLC7_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
#define SDMA2_RLC7_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC7_MIDCMD_DATA9
#define SDMA2_RLC7_MIDCMD_DATA9__DATA9__SHIFT                                                                 0x0
#define SDMA2_RLC7_MIDCMD_DATA9__DATA9_MASK                                                                   0xFFFFFFFFL
//SDMA2_RLC7_MIDCMD_DATA10
#define SDMA2_RLC7_MIDCMD_DATA10__DATA10__SHIFT                                                               0x0
#define SDMA2_RLC7_MIDCMD_DATA10__DATA10_MASK                                                                 0xFFFFFFFFL
//SDMA2_RLC7_MIDCMD_CNTL
#define SDMA2_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
#define SDMA2_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
#define SDMA2_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
#define SDMA2_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
#define SDMA2_RLC7_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
#define SDMA2_RLC7_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
#define SDMA2_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
#define SDMA2_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L


// addressBlock: gc_sdma3_sdma3dec
//SDMA3_DEC_START
#define SDMA3_DEC_START__START__SHIFT                                                                         0x0
#define SDMA3_DEC_START__START_MASK                                                                           0xFFFFFFFFL
//SDMA3_GLOBAL_TIMESTAMP_LO
#define SDMA3_GLOBAL_TIMESTAMP_LO__DATA__SHIFT                                                                0x0
#define SDMA3_GLOBAL_TIMESTAMP_LO__DATA_MASK                                                                  0xFFFFFFFFL
//SDMA3_GLOBAL_TIMESTAMP_HI
#define SDMA3_GLOBAL_TIMESTAMP_HI__DATA__SHIFT                                                                0x0
#define SDMA3_GLOBAL_TIMESTAMP_HI__DATA_MASK                                                                  0xFFFFFFFFL
//SDMA3_PG_CNTL
#define SDMA3_PG_CNTL__CMD__SHIFT                                                                             0x0
#define SDMA3_PG_CNTL__STATUS__SHIFT                                                                          0x10
#define SDMA3_PG_CNTL__CMD_MASK                                                                               0x0000000FL
#define SDMA3_PG_CNTL__STATUS_MASK                                                                            0x000F0000L
//SDMA3_PG_CTX_LO
#define SDMA3_PG_CTX_LO__ADDR__SHIFT                                                                          0x0
#define SDMA3_PG_CTX_LO__ADDR_MASK                                                                            0xFFFFFFFFL
//SDMA3_PG_CTX_HI
#define SDMA3_PG_CTX_HI__ADDR__SHIFT                                                                          0x0
#define SDMA3_PG_CTX_HI__ADDR_MASK                                                                            0xFFFFFFFFL
//SDMA3_PG_CTX_CNTL
#define SDMA3_PG_CTX_CNTL__VMID__SHIFT                                                                        0x4
#define SDMA3_PG_CTX_CNTL__VMID_MASK                                                                          0x000000F0L
//SDMA3_POWER_CNTL
#define SDMA3_POWER_CNTL__PG_CNTL_ENABLE__SHIFT                                                               0x0
#define SDMA3_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT                                                          0x1
#define SDMA3_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT                                                         0x2
#define SDMA3_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME__SHIFT                                                   0x3
#define SDMA3_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT                                                           0x8
#define SDMA3_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME__SHIFT                                                  0x1a
#define SDMA3_POWER_CNTL__PG_CNTL_ENABLE_MASK                                                                 0x00000001L
#define SDMA3_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK                                                            0x00000002L
#define SDMA3_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK                                                           0x00000004L
#define SDMA3_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK                                                     0x000000F8L
#define SDMA3_POWER_CNTL__MEM_POWER_OVERRIDE_MASK                                                             0x00000100L
#define SDMA3_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK                                                    0xFC000000L
//SDMA3_CLK_CTRL
#define SDMA3_CLK_CTRL__ON_DELAY__SHIFT                                                                       0x0
#define SDMA3_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                                 0x4
#define SDMA3_CLK_CTRL__RESERVED_24_12__SHIFT                                                                 0xc
#define SDMA3_CLK_CTRL__CGCG_EN_OVERRIDE__SHIFT                                                               0x19
#define SDMA3_CLK_CTRL__SOFT_OVERRIDE4__SHIFT                                                                 0x1a
#define SDMA3_CLK_CTRL__SOFT_OVERRIDE3__SHIFT                                                                 0x1b
#define SDMA3_CLK_CTRL__SOFT_OVERRIDE2__SHIFT                                                                 0x1c
#define SDMA3_CLK_CTRL__SOFT_OVERRIDE1__SHIFT                                                                 0x1d
#define SDMA3_CLK_CTRL__SOFT_OVERRIDE0__SHIFT                                                                 0x1e
#define SDMA3_CLK_CTRL__SOFT_OVERRIDER_REG__SHIFT                                                             0x1f
#define SDMA3_CLK_CTRL__ON_DELAY_MASK                                                                         0x0000000FL
#define SDMA3_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                   0x00000FF0L
#define SDMA3_CLK_CTRL__RESERVED_24_12_MASK                                                                   0x01FFF000L
#define SDMA3_CLK_CTRL__CGCG_EN_OVERRIDE_MASK                                                                 0x02000000L
#define SDMA3_CLK_CTRL__SOFT_OVERRIDE4_MASK                                                                   0x04000000L
#define SDMA3_CLK_CTRL__SOFT_OVERRIDE3_MASK                                                                   0x08000000L
#define SDMA3_CLK_CTRL__SOFT_OVERRIDE2_MASK                                                                   0x10000000L
#define SDMA3_CLK_CTRL__SOFT_OVERRIDE1_MASK                                                                   0x20000000L
#define SDMA3_CLK_CTRL__SOFT_OVERRIDE0_MASK                                                                   0x40000000L
#define SDMA3_CLK_CTRL__SOFT_OVERRIDER_REG_MASK                                                               0x80000000L
//SDMA3_CNTL
#define SDMA3_CNTL__TRAP_ENABLE__SHIFT                                                                        0x0
#define SDMA3_CNTL__UTC_L1_ENABLE__SHIFT                                                                      0x1
#define SDMA3_CNTL__SEM_WAIT_INT_ENABLE__SHIFT                                                                0x2
#define SDMA3_CNTL__DATA_SWAP_ENABLE__SHIFT                                                                   0x3
#define SDMA3_CNTL__FENCE_SWAP_ENABLE__SHIFT                                                                  0x4
#define SDMA3_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                              0x5
#define SDMA3_CNTL__PAGE_INT_ENABLE__SHIFT                                                                    0x7
#define SDMA3_CNTL__CH_PERFCNT_ENABLE__SHIFT                                                                  0x10
#define SDMA3_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT                                                          0x11
#define SDMA3_CNTL__AUTO_CTXSW_ENABLE__SHIFT                                                                  0x12
#define SDMA3_CNTL__CTXEMPTY_INT_ENABLE__SHIFT                                                                0x1c
#define SDMA3_CNTL__FROZEN_INT_ENABLE__SHIFT                                                                  0x1d
#define SDMA3_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT                                                              0x1e
#define SDMA3_CNTL__TRAP_ENABLE_MASK                                                                          0x00000001L
#define SDMA3_CNTL__UTC_L1_ENABLE_MASK                                                                        0x00000002L
#define SDMA3_CNTL__SEM_WAIT_INT_ENABLE_MASK                                                                  0x00000004L
#define SDMA3_CNTL__DATA_SWAP_ENABLE_MASK                                                                     0x00000008L
#define SDMA3_CNTL__FENCE_SWAP_ENABLE_MASK                                                                    0x00000010L
#define SDMA3_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                                0x00000020L
#define SDMA3_CNTL__PAGE_INT_ENABLE_MASK                                                                      0x00000080L
#define SDMA3_CNTL__CH_PERFCNT_ENABLE_MASK                                                                    0x00010000L
#define SDMA3_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK                                                            0x00020000L
#define SDMA3_CNTL__AUTO_CTXSW_ENABLE_MASK                                                                    0x00040000L
#define SDMA3_CNTL__CTXEMPTY_INT_ENABLE_MASK                                                                  0x10000000L
#define SDMA3_CNTL__FROZEN_INT_ENABLE_MASK                                                                    0x20000000L
#define SDMA3_CNTL__IB_PREEMPT_INT_ENABLE_MASK                                                                0x40000000L
//SDMA3_CHICKEN_BITS
#define SDMA3_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT                                                     0x0
#define SDMA3_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT                                                 0x1
#define SDMA3_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT                                        0x2
#define SDMA3_CHICKEN_BITS__SOFT_OVERRIDE_DCGE__SHIFT                                                         0x4
#define SDMA3_CHICKEN_BITS__SOFT_OVERRIDE_SDMA_GRBM_FGCG__SHIFT                                               0x5
#define SDMA3_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT                                                         0x8
#define SDMA3_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT                                                     0xa
#define SDMA3_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT                                                        0x10
#define SDMA3_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT                                                           0x11
#define SDMA3_CHICKEN_BITS__T2L_256B_ENABLE__SHIFT                                                            0x12
#define SDMA3_CHICKEN_BITS__GCR_FGCG_ENABLE__SHIFT                                                            0x13
#define SDMA3_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT                                                         0x14
#define SDMA3_CHICKEN_BITS__CH_FGCG_ENABLE__SHIFT                                                             0x15
#define SDMA3_CHICKEN_BITS__UTCL2_INVREQ_FGCG_ENABLE__SHIFT                                                   0x16
#define SDMA3_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT                                                           0x17
#define SDMA3_CHICKEN_BITS__UTCL1_FGCG_ENABLE__SHIFT                                                          0x18
#define SDMA3_CHICKEN_BITS__TIME_BASED_QOS__SHIFT                                                             0x19
#define SDMA3_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT                                                         0x1a
#define SDMA3_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT                                                         0x1c
#define SDMA3_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT                                                         0x1e
#define SDMA3_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK                                                       0x00000001L
#define SDMA3_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK                                                   0x00000002L
#define SDMA3_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK                                          0x00000004L
#define SDMA3_CHICKEN_BITS__SOFT_OVERRIDE_DCGE_MASK                                                           0x00000010L
#define SDMA3_CHICKEN_BITS__SOFT_OVERRIDE_SDMA_GRBM_FGCG_MASK                                                 0x00000020L
#define SDMA3_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK                                                           0x00000300L
#define SDMA3_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK                                                       0x00001C00L
#define SDMA3_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK                                                          0x00010000L
#define SDMA3_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK                                                             0x00020000L
#define SDMA3_CHICKEN_BITS__T2L_256B_ENABLE_MASK                                                              0x00040000L
#define SDMA3_CHICKEN_BITS__GCR_FGCG_ENABLE_MASK                                                              0x00080000L
#define SDMA3_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK                                                           0x00100000L
#define SDMA3_CHICKEN_BITS__CH_FGCG_ENABLE_MASK                                                               0x00200000L
#define SDMA3_CHICKEN_BITS__UTCL2_INVREQ_FGCG_ENABLE_MASK                                                     0x00400000L
#define SDMA3_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK                                                             0x00800000L
#define SDMA3_CHICKEN_BITS__UTCL1_FGCG_ENABLE_MASK                                                            0x01000000L
#define SDMA3_CHICKEN_BITS__TIME_BASED_QOS_MASK                                                               0x02000000L
#define SDMA3_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK                                                           0x0C000000L
#define SDMA3_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK                                                           0x30000000L
#define SDMA3_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK                                                           0xC0000000L
//SDMA3_GB_ADDR_CONFIG
#define SDMA3_GB_ADDR_CONFIG__NUM_PIPES__SHIFT                                                                0x0
#define SDMA3_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT                                                     0x3
#define SDMA3_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                     0x6
#define SDMA3_GB_ADDR_CONFIG__NUM_PKRS__SHIFT                                                                 0x8
#define SDMA3_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT                                                       0x13
#define SDMA3_GB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT                                                            0x1a
#define SDMA3_GB_ADDR_CONFIG__NUM_PIPES_MASK                                                                  0x00000007L
#define SDMA3_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK                                                       0x00000038L
#define SDMA3_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                       0x000000C0L
#define SDMA3_GB_ADDR_CONFIG__NUM_PKRS_MASK                                                                   0x00000700L
#define SDMA3_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK                                                         0x00180000L
#define SDMA3_GB_ADDR_CONFIG__NUM_RB_PER_SE_MASK                                                              0x0C000000L
//SDMA3_GB_ADDR_CONFIG_READ
#define SDMA3_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT                                                           0x0
#define SDMA3_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT                                                0x3
#define SDMA3_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT                                                0x6
#define SDMA3_GB_ADDR_CONFIG_READ__NUM_PKRS__SHIFT                                                            0x8
#define SDMA3_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT                                                  0x13
#define SDMA3_GB_ADDR_CONFIG_READ__NUM_RB_PER_SE__SHIFT                                                       0x1a
#define SDMA3_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK                                                             0x00000007L
#define SDMA3_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK                                                  0x00000038L
#define SDMA3_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK                                                  0x000000C0L
#define SDMA3_GB_ADDR_CONFIG_READ__NUM_PKRS_MASK                                                              0x00000700L
#define SDMA3_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK                                                    0x00180000L
#define SDMA3_GB_ADDR_CONFIG_READ__NUM_RB_PER_SE_MASK                                                         0x0C000000L
//SDMA3_RB_RPTR_FETCH_HI
#define SDMA3_RB_RPTR_FETCH_HI__OFFSET__SHIFT                                                                 0x0
#define SDMA3_RB_RPTR_FETCH_HI__OFFSET_MASK                                                                   0xFFFFFFFFL
//SDMA3_SEM_WAIT_FAIL_TIMER_CNTL
#define SDMA3_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT                                                          0x0
#define SDMA3_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK                                                            0xFFFFFFFFL
//SDMA3_RB_RPTR_FETCH
#define SDMA3_RB_RPTR_FETCH__OFFSET__SHIFT                                                                    0x2
#define SDMA3_RB_RPTR_FETCH__OFFSET_MASK                                                                      0xFFFFFFFCL
//SDMA3_IB_OFFSET_FETCH
#define SDMA3_IB_OFFSET_FETCH__OFFSET__SHIFT                                                                  0x2
#define SDMA3_IB_OFFSET_FETCH__OFFSET_MASK                                                                    0x003FFFFCL
//SDMA3_PROGRAM
#define SDMA3_PROGRAM__STREAM__SHIFT                                                                          0x0
#define SDMA3_PROGRAM__STREAM_MASK                                                                            0xFFFFFFFFL
//SDMA3_STATUS_REG
#define SDMA3_STATUS_REG__IDLE__SHIFT                                                                         0x0
#define SDMA3_STATUS_REG__REG_IDLE__SHIFT                                                                     0x1
#define SDMA3_STATUS_REG__RB_EMPTY__SHIFT                                                                     0x2
#define SDMA3_STATUS_REG__RB_FULL__SHIFT                                                                      0x3
#define SDMA3_STATUS_REG__RB_CMD_IDLE__SHIFT                                                                  0x4
#define SDMA3_STATUS_REG__RB_CMD_FULL__SHIFT                                                                  0x5
#define SDMA3_STATUS_REG__IB_CMD_IDLE__SHIFT                                                                  0x6
#define SDMA3_STATUS_REG__IB_CMD_FULL__SHIFT                                                                  0x7
#define SDMA3_STATUS_REG__BLOCK_IDLE__SHIFT                                                                   0x8
#define SDMA3_STATUS_REG__INSIDE_IB__SHIFT                                                                    0x9
#define SDMA3_STATUS_REG__EX_IDLE__SHIFT                                                                      0xa
#define SDMA3_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT                                                    0xb
#define SDMA3_STATUS_REG__PACKET_READY__SHIFT                                                                 0xc
#define SDMA3_STATUS_REG__MC_WR_IDLE__SHIFT                                                                   0xd
#define SDMA3_STATUS_REG__SRBM_IDLE__SHIFT                                                                    0xe
#define SDMA3_STATUS_REG__CONTEXT_EMPTY__SHIFT                                                                0xf
#define SDMA3_STATUS_REG__DELTA_RPTR_FULL__SHIFT                                                              0x10
#define SDMA3_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT                                                              0x11
#define SDMA3_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT                                                              0x12
#define SDMA3_STATUS_REG__MC_RD_IDLE__SHIFT                                                                   0x13
#define SDMA3_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT                                                             0x14
#define SDMA3_STATUS_REG__MC_RD_RET_STALL__SHIFT                                                              0x15
#define SDMA3_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT                                                           0x16
#define SDMA3_STATUS_REG__PREV_CMD_IDLE__SHIFT                                                                0x19
#define SDMA3_STATUS_REG__SEM_IDLE__SHIFT                                                                     0x1a
#define SDMA3_STATUS_REG__SEM_REQ_STALL__SHIFT                                                                0x1b
#define SDMA3_STATUS_REG__SEM_RESP_STATE__SHIFT                                                               0x1c
#define SDMA3_STATUS_REG__INT_IDLE__SHIFT                                                                     0x1e
#define SDMA3_STATUS_REG__INT_REQ_STALL__SHIFT                                                                0x1f
#define SDMA3_STATUS_REG__IDLE_MASK                                                                           0x00000001L
#define SDMA3_STATUS_REG__REG_IDLE_MASK                                                                       0x00000002L
#define SDMA3_STATUS_REG__RB_EMPTY_MASK                                                                       0x00000004L
#define SDMA3_STATUS_REG__RB_FULL_MASK                                                                        0x00000008L
#define SDMA3_STATUS_REG__RB_CMD_IDLE_MASK                                                                    0x00000010L
#define SDMA3_STATUS_REG__RB_CMD_FULL_MASK                                                                    0x00000020L
#define SDMA3_STATUS_REG__IB_CMD_IDLE_MASK                                                                    0x00000040L
#define SDMA3_STATUS_REG__IB_CMD_FULL_MASK                                                                    0x00000080L
#define SDMA3_STATUS_REG__BLOCK_IDLE_MASK                                                                     0x00000100L
#define SDMA3_STATUS_REG__INSIDE_IB_MASK                                                                      0x00000200L
#define SDMA3_STATUS_REG__EX_IDLE_MASK                                                                        0x00000400L
#define SDMA3_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK                                                      0x00000800L
#define SDMA3_STATUS_REG__PACKET_READY_MASK                                                                   0x00001000L
#define SDMA3_STATUS_REG__MC_WR_IDLE_MASK                                                                     0x00002000L
#define SDMA3_STATUS_REG__SRBM_IDLE_MASK                                                                      0x00004000L
#define SDMA3_STATUS_REG__CONTEXT_EMPTY_MASK                                                                  0x00008000L
#define SDMA3_STATUS_REG__DELTA_RPTR_FULL_MASK                                                                0x00010000L
#define SDMA3_STATUS_REG__RB_MC_RREQ_IDLE_MASK                                                                0x00020000L
#define SDMA3_STATUS_REG__IB_MC_RREQ_IDLE_MASK                                                                0x00040000L
#define SDMA3_STATUS_REG__MC_RD_IDLE_MASK                                                                     0x00080000L
#define SDMA3_STATUS_REG__DELTA_RPTR_EMPTY_MASK                                                               0x00100000L
#define SDMA3_STATUS_REG__MC_RD_RET_STALL_MASK                                                                0x00200000L
#define SDMA3_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK                                                             0x00400000L
#define SDMA3_STATUS_REG__PREV_CMD_IDLE_MASK                                                                  0x02000000L
#define SDMA3_STATUS_REG__SEM_IDLE_MASK                                                                       0x04000000L
#define SDMA3_STATUS_REG__SEM_REQ_STALL_MASK                                                                  0x08000000L
#define SDMA3_STATUS_REG__SEM_RESP_STATE_MASK                                                                 0x30000000L
#define SDMA3_STATUS_REG__INT_IDLE_MASK                                                                       0x40000000L
#define SDMA3_STATUS_REG__INT_REQ_STALL_MASK                                                                  0x80000000L
//SDMA3_STATUS1_REG
#define SDMA3_STATUS1_REG__CE_WREQ_IDLE__SHIFT                                                                0x0
#define SDMA3_STATUS1_REG__CE_WR_IDLE__SHIFT                                                                  0x1
#define SDMA3_STATUS1_REG__CE_SPLIT_IDLE__SHIFT                                                               0x2
#define SDMA3_STATUS1_REG__CE_RREQ_IDLE__SHIFT                                                                0x3
#define SDMA3_STATUS1_REG__CE_OUT_IDLE__SHIFT                                                                 0x4
#define SDMA3_STATUS1_REG__CE_IN_IDLE__SHIFT                                                                  0x5
#define SDMA3_STATUS1_REG__CE_DST_IDLE__SHIFT                                                                 0x6
#define SDMA3_STATUS1_REG__CE_CMD_IDLE__SHIFT                                                                 0x9
#define SDMA3_STATUS1_REG__CE_AFIFO_FULL__SHIFT                                                               0xa
#define SDMA3_STATUS1_REG__CE_INFO_FULL__SHIFT                                                                0xd
#define SDMA3_STATUS1_REG__CE_INFO1_FULL__SHIFT                                                               0xe
#define SDMA3_STATUS1_REG__EX_START__SHIFT                                                                    0xf
#define SDMA3_STATUS1_REG__CE_RD_STALL__SHIFT                                                                 0x11
#define SDMA3_STATUS1_REG__CE_WR_STALL__SHIFT                                                                 0x12
#define SDMA3_STATUS1_REG__CE_WREQ_IDLE_MASK                                                                  0x00000001L
#define SDMA3_STATUS1_REG__CE_WR_IDLE_MASK                                                                    0x00000002L
#define SDMA3_STATUS1_REG__CE_SPLIT_IDLE_MASK                                                                 0x00000004L
#define SDMA3_STATUS1_REG__CE_RREQ_IDLE_MASK                                                                  0x00000008L
#define SDMA3_STATUS1_REG__CE_OUT_IDLE_MASK                                                                   0x00000010L
#define SDMA3_STATUS1_REG__CE_IN_IDLE_MASK                                                                    0x00000020L
#define SDMA3_STATUS1_REG__CE_DST_IDLE_MASK                                                                   0x00000040L
#define SDMA3_STATUS1_REG__CE_CMD_IDLE_MASK                                                                   0x00000200L
#define SDMA3_STATUS1_REG__CE_AFIFO_FULL_MASK                                                                 0x00000400L
#define SDMA3_STATUS1_REG__CE_INFO_FULL_MASK                                                                  0x00002000L
#define SDMA3_STATUS1_REG__CE_INFO1_FULL_MASK                                                                 0x00004000L
#define SDMA3_STATUS1_REG__EX_START_MASK                                                                      0x00008000L
#define SDMA3_STATUS1_REG__CE_RD_STALL_MASK                                                                   0x00020000L
#define SDMA3_STATUS1_REG__CE_WR_STALL_MASK                                                                   0x00040000L
//SDMA3_RD_BURST_CNTL
#define SDMA3_RD_BURST_CNTL__RD_BURST__SHIFT                                                                  0x0
#define SDMA3_RD_BURST_CNTL__RD_BURST_MASK                                                                    0x00000003L
//SDMA3_HBM_PAGE_CONFIG
#define SDMA3_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT                                                      0x0
#define SDMA3_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK                                                        0x00000001L
//SDMA3_UCODE_CHECKSUM
#define SDMA3_UCODE_CHECKSUM__DATA__SHIFT                                                                     0x0
#define SDMA3_UCODE_CHECKSUM__DATA_MASK                                                                       0xFFFFFFFFL
//SDMA3_F32_CNTL
#define SDMA3_F32_CNTL__HALT__SHIFT                                                                           0x0
#define SDMA3_F32_CNTL__STEP__SHIFT                                                                           0x1
#define SDMA3_F32_CNTL__CHECKSUM_CLR__SHIFT                                                                   0x8
#define SDMA3_F32_CNTL__RESET__SHIFT                                                                          0x9
#define SDMA3_F32_CNTL__HALT_MASK                                                                             0x00000001L
#define SDMA3_F32_CNTL__STEP_MASK                                                                             0x00000002L
#define SDMA3_F32_CNTL__CHECKSUM_CLR_MASK                                                                     0x00000100L
#define SDMA3_F32_CNTL__RESET_MASK                                                                            0x00000200L
//SDMA3_FREEZE
#define SDMA3_FREEZE__PREEMPT__SHIFT                                                                          0x0
#define SDMA3_FREEZE__FORCE_PREEMPT__SHIFT                                                                    0x1
#define SDMA3_FREEZE__FREEZE__SHIFT                                                                           0x4
#define SDMA3_FREEZE__FROZEN__SHIFT                                                                           0x5
#define SDMA3_FREEZE__F32_FREEZE__SHIFT                                                                       0x6
#define SDMA3_FREEZE__PREEMPT_MASK                                                                            0x00000001L
#define SDMA3_FREEZE__FORCE_PREEMPT_MASK                                                                      0x00000002L
#define SDMA3_FREEZE__FREEZE_MASK                                                                             0x00000010L
#define SDMA3_FREEZE__FROZEN_MASK                                                                             0x00000020L
#define SDMA3_FREEZE__F32_FREEZE_MASK                                                                         0x00000040L
//SDMA3_PHASE0_QUANTUM
#define SDMA3_PHASE0_QUANTUM__UNIT__SHIFT                                                                     0x0
#define SDMA3_PHASE0_QUANTUM__VALUE__SHIFT                                                                    0x8
#define SDMA3_PHASE0_QUANTUM__PREFER__SHIFT                                                                   0x1e
#define SDMA3_PHASE0_QUANTUM__UNIT_MASK                                                                       0x0000000FL
#define SDMA3_PHASE0_QUANTUM__VALUE_MASK                                                                      0x00FFFF00L
#define SDMA3_PHASE0_QUANTUM__PREFER_MASK                                                                     0x40000000L
//SDMA3_PHASE1_QUANTUM
#define SDMA3_PHASE1_QUANTUM__UNIT__SHIFT                                                                     0x0
#define SDMA3_PHASE1_QUANTUM__VALUE__SHIFT                                                                    0x8
#define SDMA3_PHASE1_QUANTUM__PREFER__SHIFT                                                                   0x1e
#define SDMA3_PHASE1_QUANTUM__UNIT_MASK                                                                       0x0000000FL
#define SDMA3_PHASE1_QUANTUM__VALUE_MASK                                                                      0x00FFFF00L
#define SDMA3_PHASE1_QUANTUM__PREFER_MASK                                                                     0x40000000L
//SDMA3_EDC_CONFIG
#define SDMA3_EDC_CONFIG__DIS_EDC__SHIFT                                                                      0x1
#define SDMA3_EDC_CONFIG__ECC_INT_ENABLE__SHIFT                                                               0x2
#define SDMA3_EDC_CONFIG__DIS_EDC_MASK                                                                        0x00000002L
#define SDMA3_EDC_CONFIG__ECC_INT_ENABLE_MASK                                                                 0x00000004L
//SDMA3_BA_THRESHOLD
#define SDMA3_BA_THRESHOLD__READ_THRES__SHIFT                                                                 0x0
#define SDMA3_BA_THRESHOLD__WRITE_THRES__SHIFT                                                                0x10
#define SDMA3_BA_THRESHOLD__READ_THRES_MASK                                                                   0x000003FFL
#define SDMA3_BA_THRESHOLD__WRITE_THRES_MASK                                                                  0x03FF0000L
//SDMA3_ID
#define SDMA3_ID__DEVICE_ID__SHIFT                                                                            0x0
#define SDMA3_ID__DEVICE_ID_MASK                                                                              0x000000FFL
//SDMA3_VERSION
#define SDMA3_VERSION__MINVER__SHIFT                                                                          0x0
#define SDMA3_VERSION__MAJVER__SHIFT                                                                          0x8
#define SDMA3_VERSION__REV__SHIFT                                                                             0x10
#define SDMA3_VERSION__MINVER_MASK                                                                            0x0000007FL
#define SDMA3_VERSION__MAJVER_MASK                                                                            0x00007F00L
#define SDMA3_VERSION__REV_MASK                                                                               0x003F0000L
//SDMA3_EDC_COUNTER
#define SDMA3_EDC_COUNTER__SDMA_UCODE_BUF_DED__SHIFT                                                          0x0
#define SDMA3_EDC_COUNTER__SDMA_UCODE_BUF_SEC__SHIFT                                                          0x1
#define SDMA3_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT                                                         0x2
#define SDMA3_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT                                                         0x3
#define SDMA3_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT                                                      0x4
#define SDMA3_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT                                                   0x5
#define SDMA3_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT                                                      0x6
#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT                                                    0x7
#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT                                                    0x8
#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT                                                    0x9
#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT                                                    0xa
#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT                                                    0xb
#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT                                                    0xc
#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT                                                    0xd
#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT                                                    0xe
#define SDMA3_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT                                                      0xf
#define SDMA3_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT                                                    0x10
#define SDMA3_EDC_COUNTER__SDMA_UCODE_BUF_DED_MASK                                                            0x00000001L
#define SDMA3_EDC_COUNTER__SDMA_UCODE_BUF_SEC_MASK                                                            0x00000002L
#define SDMA3_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK                                                           0x00000004L
#define SDMA3_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK                                                           0x00000008L
#define SDMA3_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK                                                        0x00000010L
#define SDMA3_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK                                                     0x00000020L
#define SDMA3_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK                                                        0x00000040L
#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK                                                      0x00000080L
#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK                                                      0x00000100L
#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK                                                      0x00000200L
#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK                                                      0x00000400L
#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK                                                      0x00000800L
#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK                                                      0x00001000L
#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK                                                      0x00002000L
#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK                                                      0x00004000L
#define SDMA3_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK                                                        0x00008000L
#define SDMA3_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK                                                      0x00010000L
//SDMA3_EDC_COUNTER_CLEAR
#define SDMA3_EDC_COUNTER_CLEAR__DUMMY__SHIFT                                                                 0x0
#define SDMA3_EDC_COUNTER_CLEAR__DUMMY_MASK                                                                   0x00000001L
//SDMA3_STATUS2_REG
#define SDMA3_STATUS2_REG__ID__SHIFT                                                                          0x0
#define SDMA3_STATUS2_REG__F32_INSTR_PTR__SHIFT                                                               0x2
#define SDMA3_STATUS2_REG__CMD_OP__SHIFT                                                                      0x10
#define SDMA3_STATUS2_REG__ID_MASK                                                                            0x00000003L
#define SDMA3_STATUS2_REG__F32_INSTR_PTR_MASK                                                                 0x0000FFFCL
#define SDMA3_STATUS2_REG__CMD_OP_MASK                                                                        0xFFFF0000L
//SDMA3_ATOMIC_CNTL
#define SDMA3_ATOMIC_CNTL__LOOP_TIMER__SHIFT                                                                  0x0
#define SDMA3_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT                                                       0x1f
#define SDMA3_ATOMIC_CNTL__LOOP_TIMER_MASK                                                                    0x7FFFFFFFL
#define SDMA3_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK                                                         0x80000000L
//SDMA3_ATOMIC_PREOP_LO
#define SDMA3_ATOMIC_PREOP_LO__DATA__SHIFT                                                                    0x0
#define SDMA3_ATOMIC_PREOP_LO__DATA_MASK                                                                      0xFFFFFFFFL
//SDMA3_ATOMIC_PREOP_HI
#define SDMA3_ATOMIC_PREOP_HI__DATA__SHIFT                                                                    0x0
#define SDMA3_ATOMIC_PREOP_HI__DATA_MASK                                                                      0xFFFFFFFFL
//SDMA3_UTCL1_CNTL
#define SDMA3_UTCL1_CNTL__REDO_ENABLE__SHIFT                                                                  0x0
#define SDMA3_UTCL1_CNTL__REDO_DELAY__SHIFT                                                                   0x1
#define SDMA3_UTCL1_CNTL__REDO_WATERMK__SHIFT                                                                 0x6
#define SDMA3_UTCL1_CNTL__RESP_MODE__SHIFT                                                                    0x9
#define SDMA3_UTCL1_CNTL__FORCE_INVALIDATION__SHIFT                                                           0xe
#define SDMA3_UTCL1_CNTL__FORCE_INVREQ_HEAVY__SHIFT                                                           0xf
#define SDMA3_UTCL1_CNTL__INVACK_DELAY__SHIFT                                                                 0x10
#define SDMA3_UTCL1_CNTL__REQL2_CREDIT__SHIFT                                                                 0x18
#define SDMA3_UTCL1_CNTL__VADDR_WATERMK__SHIFT                                                                0x1d
#define SDMA3_UTCL1_CNTL__REDO_ENABLE_MASK                                                                    0x00000001L
#define SDMA3_UTCL1_CNTL__REDO_DELAY_MASK                                                                     0x0000003EL
#define SDMA3_UTCL1_CNTL__REDO_WATERMK_MASK                                                                   0x000001C0L
#define SDMA3_UTCL1_CNTL__RESP_MODE_MASK                                                                      0x00000E00L
#define SDMA3_UTCL1_CNTL__FORCE_INVALIDATION_MASK                                                             0x00004000L
#define SDMA3_UTCL1_CNTL__FORCE_INVREQ_HEAVY_MASK                                                             0x00008000L
#define SDMA3_UTCL1_CNTL__INVACK_DELAY_MASK                                                                   0x00FF0000L
#define SDMA3_UTCL1_CNTL__REQL2_CREDIT_MASK                                                                   0x1F000000L
#define SDMA3_UTCL1_CNTL__VADDR_WATERMK_MASK                                                                  0xE0000000L
//SDMA3_UTCL1_WATERMK
#define SDMA3_UTCL1_WATERMK__REQMC_WATERMK__SHIFT                                                             0x0
#define SDMA3_UTCL1_WATERMK__REQPG_WATERMK__SHIFT                                                             0xa
#define SDMA3_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT                                                            0x12
#define SDMA3_UTCL1_WATERMK__XNACK_WATERMK__SHIFT                                                             0x1a
#define SDMA3_UTCL1_WATERMK__REQMC_WATERMK_MASK                                                               0x000003FFL
#define SDMA3_UTCL1_WATERMK__REQPG_WATERMK_MASK                                                               0x0003FC00L
#define SDMA3_UTCL1_WATERMK__INVREQ_WATERMK_MASK                                                              0x03FC0000L
#define SDMA3_UTCL1_WATERMK__XNACK_WATERMK_MASK                                                               0xFC000000L
//SDMA3_UTCL1_RD_STATUS
#define SDMA3_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT                                                0x0
#define SDMA3_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT                                                 0x1
#define SDMA3_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT                                                     0x2
#define SDMA3_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT                                                      0x3
#define SDMA3_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT                                                      0x4
#define SDMA3_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT                                                       0x5
#define SDMA3_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT                                                   0x6
#define SDMA3_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT                                                    0x7
#define SDMA3_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT                                                    0x8
#define SDMA3_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT                                                     0x9
#define SDMA3_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT                                                 0xa
#define SDMA3_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT                                                  0xb
#define SDMA3_UTCL1_RD_STATUS__REDO_ARR_EMPTY__SHIFT                                                          0xc
#define SDMA3_UTCL1_RD_STATUS__REDO_ARR_FULL__SHIFT                                                           0xd
#define SDMA3_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT                                                              0xe
#define SDMA3_UTCL1_RD_STATUS__PAGE_NULL__SHIFT                                                               0xf
#define SDMA3_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT                                                              0x10
#define SDMA3_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT                                                          0x11
#define SDMA3_UTCL1_RD_STATUS__MERGE_STATE__SHIFT                                                             0x15
#define SDMA3_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT                                                             0x18
#define SDMA3_UTCL1_RD_STATUS__RD_XNACK_TIMEOUT__SHIFT                                                        0x19
#define SDMA3_UTCL1_RD_STATUS__PAGE_NULL_SW__SHIFT                                                            0x1a
#define SDMA3_UTCL1_RD_STATUS__HIT_CACHE__SHIFT                                                               0x1b
#define SDMA3_UTCL1_RD_STATUS__RD_DCC_ENABLE__SHIFT                                                           0x1c
#define SDMA3_UTCL1_RD_STATUS__NACK_TIMEOUT_SW__SHIFT                                                         0x1d
#define SDMA3_UTCL1_RD_STATUS__DCC_PAGE_FAULT__SHIFT                                                          0x1e
#define SDMA3_UTCL1_RD_STATUS__DCC_PAGE_NULL__SHIFT                                                           0x1f
#define SDMA3_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK                                                  0x00000001L
#define SDMA3_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK                                                   0x00000002L
#define SDMA3_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK                                                       0x00000004L
#define SDMA3_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK                                                        0x00000008L
#define SDMA3_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK                                                        0x00000010L
#define SDMA3_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK                                                         0x00000020L
#define SDMA3_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK                                                     0x00000040L
#define SDMA3_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK                                                      0x00000080L
#define SDMA3_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK                                                      0x00000100L
#define SDMA3_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK                                                       0x00000200L
#define SDMA3_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK                                                   0x00000400L
#define SDMA3_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK                                                    0x00000800L
#define SDMA3_UTCL1_RD_STATUS__REDO_ARR_EMPTY_MASK                                                            0x00001000L
#define SDMA3_UTCL1_RD_STATUS__REDO_ARR_FULL_MASK                                                             0x00002000L
#define SDMA3_UTCL1_RD_STATUS__PAGE_FAULT_MASK                                                                0x00004000L
#define SDMA3_UTCL1_RD_STATUS__PAGE_NULL_MASK                                                                 0x00008000L
#define SDMA3_UTCL1_RD_STATUS__REQL2_IDLE_MASK                                                                0x00010000L
#define SDMA3_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK                                                            0x001E0000L
#define SDMA3_UTCL1_RD_STATUS__MERGE_STATE_MASK                                                               0x00E00000L
#define SDMA3_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK                                                               0x01000000L
#define SDMA3_UTCL1_RD_STATUS__RD_XNACK_TIMEOUT_MASK                                                          0x02000000L
#define SDMA3_UTCL1_RD_STATUS__PAGE_NULL_SW_MASK                                                              0x04000000L
#define SDMA3_UTCL1_RD_STATUS__HIT_CACHE_MASK                                                                 0x08000000L
#define SDMA3_UTCL1_RD_STATUS__RD_DCC_ENABLE_MASK                                                             0x10000000L
#define SDMA3_UTCL1_RD_STATUS__NACK_TIMEOUT_SW_MASK                                                           0x20000000L
#define SDMA3_UTCL1_RD_STATUS__DCC_PAGE_FAULT_MASK                                                            0x40000000L
#define SDMA3_UTCL1_RD_STATUS__DCC_PAGE_NULL_MASK                                                             0x80000000L
//SDMA3_UTCL1_WR_STATUS
#define SDMA3_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT                                                0x0
#define SDMA3_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT                                                 0x1
#define SDMA3_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT                                                     0x2
#define SDMA3_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT                                                      0x3
#define SDMA3_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT                                                      0x4
#define SDMA3_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT                                                       0x5
#define SDMA3_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT                                                   0x6
#define SDMA3_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT                                                    0x7
#define SDMA3_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT                                                    0x8
#define SDMA3_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT                                                     0x9
#define SDMA3_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT                                                 0xa
#define SDMA3_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT                                                  0xb
#define SDMA3_UTCL1_WR_STATUS__REDO_ARR_EMPTY__SHIFT                                                          0xc
#define SDMA3_UTCL1_WR_STATUS__REDO_ARR_FULL__SHIFT                                                           0xd
#define SDMA3_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT                                                              0xe
#define SDMA3_UTCL1_WR_STATUS__PAGE_NULL__SHIFT                                                               0xf
#define SDMA3_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT                                                              0x10
#define SDMA3_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT                                                          0x11
#define SDMA3_UTCL1_WR_STATUS__MERGE_STATE__SHIFT                                                             0x15
#define SDMA3_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT                                                              0x18
#define SDMA3_UTCL1_WR_STATUS__WR_XNACK_TIMEOUT__SHIFT                                                        0x19
#define SDMA3_UTCL1_WR_STATUS__PAGE_NULL_SW__SHIFT                                                            0x1a
#define SDMA3_UTCL1_WR_STATUS__ATOMIC_OP__SHIFT                                                               0x1b
#define SDMA3_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT                                                    0x1c
#define SDMA3_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT                                                     0x1d
#define SDMA3_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT                                                   0x1e
#define SDMA3_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT                                                    0x1f
#define SDMA3_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK                                                  0x00000001L
#define SDMA3_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK                                                   0x00000002L
#define SDMA3_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK                                                       0x00000004L
#define SDMA3_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK                                                        0x00000008L
#define SDMA3_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK                                                        0x00000010L
#define SDMA3_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK                                                         0x00000020L
#define SDMA3_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK                                                     0x00000040L
#define SDMA3_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK                                                      0x00000080L
#define SDMA3_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK                                                      0x00000100L
#define SDMA3_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK                                                       0x00000200L
#define SDMA3_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK                                                   0x00000400L
#define SDMA3_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK                                                    0x00000800L
#define SDMA3_UTCL1_WR_STATUS__REDO_ARR_EMPTY_MASK                                                            0x00001000L
#define SDMA3_UTCL1_WR_STATUS__REDO_ARR_FULL_MASK                                                             0x00002000L
#define SDMA3_UTCL1_WR_STATUS__PAGE_FAULT_MASK                                                                0x00004000L
#define SDMA3_UTCL1_WR_STATUS__PAGE_NULL_MASK                                                                 0x00008000L
#define SDMA3_UTCL1_WR_STATUS__REQL2_IDLE_MASK                                                                0x00010000L
#define SDMA3_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK                                                            0x001E0000L
#define SDMA3_UTCL1_WR_STATUS__MERGE_STATE_MASK                                                               0x00E00000L
#define SDMA3_UTCL1_WR_STATUS__F32_WR_RTR_MASK                                                                0x01000000L
#define SDMA3_UTCL1_WR_STATUS__WR_XNACK_TIMEOUT_MASK                                                          0x02000000L
#define SDMA3_UTCL1_WR_STATUS__PAGE_NULL_SW_MASK                                                              0x04000000L
#define SDMA3_UTCL1_WR_STATUS__ATOMIC_OP_MASK                                                                 0x08000000L
#define SDMA3_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK                                                      0x10000000L
#define SDMA3_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK                                                       0x20000000L
#define SDMA3_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK                                                     0x40000000L
#define SDMA3_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK                                                      0x80000000L
//SDMA3_UTCL1_INV0
#define SDMA3_UTCL1_INV0__CPF_INVREQ_EN__SHIFT                                                                0x0
#define SDMA3_UTCL1_INV0__GPUVM_INVREQ_EN__SHIFT                                                              0x1
#define SDMA3_UTCL1_INV0__CPF_GPA_INVREQ__SHIFT                                                               0x2
#define SDMA3_UTCL1_INV0__GPUVM_INVREQ_LOW__SHIFT                                                             0x3
#define SDMA3_UTCL1_INV0__GPUVM_INVREQ_HIGH__SHIFT                                                            0x4
#define SDMA3_UTCL1_INV0__INVREQ_SIZE__SHIFT                                                                  0x5
#define SDMA3_UTCL1_INV0__INVREQ_IDLE__SHIFT                                                                  0xb
#define SDMA3_UTCL1_INV0__VMINV_PEND_CNT__SHIFT                                                               0xc
#define SDMA3_UTCL1_INV0__GPUVM_LO_INV_VMID__SHIFT                                                            0x10
#define SDMA3_UTCL1_INV0__GPUVM_HI_INV_VMID__SHIFT                                                            0x14
#define SDMA3_UTCL1_INV0__GPUVM_INV_MODE__SHIFT                                                               0x18
#define SDMA3_UTCL1_INV0__INVREQ_IS_HEAVY__SHIFT                                                              0x1a
#define SDMA3_UTCL1_INV0__INVREQ_FROM_CPF__SHIFT                                                              0x1b
#define SDMA3_UTCL1_INV0__GPUVM_INVREQ_TAG__SHIFT                                                             0x1c
#define SDMA3_UTCL1_INV0__CPF_INVREQ_EN_MASK                                                                  0x00000001L
#define SDMA3_UTCL1_INV0__GPUVM_INVREQ_EN_MASK                                                                0x00000002L
#define SDMA3_UTCL1_INV0__CPF_GPA_INVREQ_MASK                                                                 0x00000004L
#define SDMA3_UTCL1_INV0__GPUVM_INVREQ_LOW_MASK                                                               0x00000008L
#define SDMA3_UTCL1_INV0__GPUVM_INVREQ_HIGH_MASK                                                              0x00000010L
#define SDMA3_UTCL1_INV0__INVREQ_SIZE_MASK                                                                    0x000007E0L
#define SDMA3_UTCL1_INV0__INVREQ_IDLE_MASK                                                                    0x00000800L
#define SDMA3_UTCL1_INV0__VMINV_PEND_CNT_MASK                                                                 0x0000F000L
#define SDMA3_UTCL1_INV0__GPUVM_LO_INV_VMID_MASK                                                              0x000F0000L
#define SDMA3_UTCL1_INV0__GPUVM_HI_INV_VMID_MASK                                                              0x00F00000L
#define SDMA3_UTCL1_INV0__GPUVM_INV_MODE_MASK                                                                 0x03000000L
#define SDMA3_UTCL1_INV0__INVREQ_IS_HEAVY_MASK                                                                0x04000000L
#define SDMA3_UTCL1_INV0__INVREQ_FROM_CPF_MASK                                                                0x08000000L
#define SDMA3_UTCL1_INV0__GPUVM_INVREQ_TAG_MASK                                                               0xF0000000L
//SDMA3_UTCL1_INV1
#define SDMA3_UTCL1_INV1__INV_ADDR_LO__SHIFT                                                                  0x0
#define SDMA3_UTCL1_INV1__INV_ADDR_LO_MASK                                                                    0xFFFFFFFFL
//SDMA3_UTCL1_INV2
#define SDMA3_UTCL1_INV2__INV_VMID_VEC__SHIFT                                                                 0x0
#define SDMA3_UTCL1_INV2__RESERVED__SHIFT                                                                     0x10
#define SDMA3_UTCL1_INV2__INV_VMID_VEC_MASK                                                                   0x0000FFFFL
#define SDMA3_UTCL1_INV2__RESERVED_MASK                                                                       0xFFFF0000L
//SDMA3_UTCL1_RD_XNACK0
#define SDMA3_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT                                                           0x0
#define SDMA3_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK                                                             0xFFFFFFFFL
//SDMA3_UTCL1_RD_XNACK1
#define SDMA3_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT                                                           0x0
#define SDMA3_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT                                                              0x4
#define SDMA3_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT                                                            0x8
#define SDMA3_UTCL1_RD_XNACK1__IS_XNACK__SHIFT                                                                0x1a
#define SDMA3_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK                                                             0x0000000FL
#define SDMA3_UTCL1_RD_XNACK1__XNACK_VMID_MASK                                                                0x000000F0L
#define SDMA3_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK                                                              0x03FFFF00L
#define SDMA3_UTCL1_RD_XNACK1__IS_XNACK_MASK                                                                  0x0C000000L
//SDMA3_UTCL1_WR_XNACK0
#define SDMA3_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT                                                           0x0
#define SDMA3_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK                                                             0xFFFFFFFFL
//SDMA3_UTCL1_WR_XNACK1
#define SDMA3_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT                                                           0x0
#define SDMA3_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT                                                              0x4
#define SDMA3_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT                                                            0x8
#define SDMA3_UTCL1_WR_XNACK1__IS_XNACK__SHIFT                                                                0x1a
#define SDMA3_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK                                                             0x0000000FL
#define SDMA3_UTCL1_WR_XNACK1__XNACK_VMID_MASK                                                                0x000000F0L
#define SDMA3_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK                                                              0x03FFFF00L
#define SDMA3_UTCL1_WR_XNACK1__IS_XNACK_MASK                                                                  0x0C000000L
//SDMA3_UTCL1_TIMEOUT
#define SDMA3_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT                                                            0x0
#define SDMA3_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT                                                            0x10
#define SDMA3_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK                                                              0x0000FFFFL
#define SDMA3_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK                                                              0xFFFF0000L
//SDMA3_UTCL1_PAGE
#define SDMA3_UTCL1_PAGE__VM_HOLE__SHIFT                                                                      0x0
#define SDMA3_UTCL1_PAGE__REQ_TYPE__SHIFT                                                                     0x1
#define SDMA3_UTCL1_PAGE__USE_MTYPE__SHIFT                                                                    0x6
#define SDMA3_UTCL1_PAGE__USE_PT_SNOOP__SHIFT                                                                 0xa
#define SDMA3_UTCL1_PAGE__USE_IO__SHIFT                                                                       0xb
#define SDMA3_UTCL1_PAGE__RD_L2_POLICY__SHIFT                                                                 0xc
#define SDMA3_UTCL1_PAGE__WR_L2_POLICY__SHIFT                                                                 0xe
#define SDMA3_UTCL1_PAGE__DMA_PAGE_SIZE__SHIFT                                                                0x10
#define SDMA3_UTCL1_PAGE__USE_BC__SHIFT                                                                       0x16
#define SDMA3_UTCL1_PAGE__ADDR_IS_PA__SHIFT                                                                   0x17
#define SDMA3_UTCL1_PAGE__VM_HOLE_MASK                                                                        0x00000001L
#define SDMA3_UTCL1_PAGE__REQ_TYPE_MASK                                                                       0x0000001EL
#define SDMA3_UTCL1_PAGE__USE_MTYPE_MASK                                                                      0x000003C0L
#define SDMA3_UTCL1_PAGE__USE_PT_SNOOP_MASK                                                                   0x00000400L
#define SDMA3_UTCL1_PAGE__USE_IO_MASK                                                                         0x00000800L
#define SDMA3_UTCL1_PAGE__RD_L2_POLICY_MASK                                                                   0x00003000L
#define SDMA3_UTCL1_PAGE__WR_L2_POLICY_MASK                                                                   0x0000C000L
#define SDMA3_UTCL1_PAGE__DMA_PAGE_SIZE_MASK                                                                  0x003F0000L
#define SDMA3_UTCL1_PAGE__USE_BC_MASK                                                                         0x00400000L
#define SDMA3_UTCL1_PAGE__ADDR_IS_PA_MASK                                                                     0x00800000L
//SDMA3_RELAX_ORDERING_LUT
#define SDMA3_RELAX_ORDERING_LUT__RESERVED0__SHIFT                                                            0x0
#define SDMA3_RELAX_ORDERING_LUT__COPY__SHIFT                                                                 0x1
#define SDMA3_RELAX_ORDERING_LUT__WRITE__SHIFT                                                                0x2
#define SDMA3_RELAX_ORDERING_LUT__RESERVED3__SHIFT                                                            0x3
#define SDMA3_RELAX_ORDERING_LUT__RESERVED4__SHIFT                                                            0x4
#define SDMA3_RELAX_ORDERING_LUT__FENCE__SHIFT                                                                0x5
#define SDMA3_RELAX_ORDERING_LUT__RESERVED76__SHIFT                                                           0x6
#define SDMA3_RELAX_ORDERING_LUT__POLL_MEM__SHIFT                                                             0x8
#define SDMA3_RELAX_ORDERING_LUT__COND_EXE__SHIFT                                                             0x9
#define SDMA3_RELAX_ORDERING_LUT__ATOMIC__SHIFT                                                               0xa
#define SDMA3_RELAX_ORDERING_LUT__CONST_FILL__SHIFT                                                           0xb
#define SDMA3_RELAX_ORDERING_LUT__PTEPDE__SHIFT                                                               0xc
#define SDMA3_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT                                                            0xd
#define SDMA3_RELAX_ORDERING_LUT__RESERVED__SHIFT                                                             0xe
#define SDMA3_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT                                                         0x1b
#define SDMA3_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT                                                             0x1c
#define SDMA3_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT                                                            0x1d
#define SDMA3_RELAX_ORDERING_LUT__IB_FETCH__SHIFT                                                             0x1e
#define SDMA3_RELAX_ORDERING_LUT__RB_FETCH__SHIFT                                                             0x1f
#define SDMA3_RELAX_ORDERING_LUT__RESERVED0_MASK                                                              0x00000001L
#define SDMA3_RELAX_ORDERING_LUT__COPY_MASK                                                                   0x00000002L
#define SDMA3_RELAX_ORDERING_LUT__WRITE_MASK                                                                  0x00000004L
#define SDMA3_RELAX_ORDERING_LUT__RESERVED3_MASK                                                              0x00000008L
#define SDMA3_RELAX_ORDERING_LUT__RESERVED4_MASK                                                              0x00000010L
#define SDMA3_RELAX_ORDERING_LUT__FENCE_MASK                                                                  0x00000020L
#define SDMA3_RELAX_ORDERING_LUT__RESERVED76_MASK                                                             0x000000C0L
#define SDMA3_RELAX_ORDERING_LUT__POLL_MEM_MASK                                                               0x00000100L
#define SDMA3_RELAX_ORDERING_LUT__COND_EXE_MASK                                                               0x00000200L
#define SDMA3_RELAX_ORDERING_LUT__ATOMIC_MASK                                                                 0x00000400L
#define SDMA3_RELAX_ORDERING_LUT__CONST_FILL_MASK                                                             0x00000800L
#define SDMA3_RELAX_ORDERING_LUT__PTEPDE_MASK                                                                 0x00001000L
#define SDMA3_RELAX_ORDERING_LUT__TIMESTAMP_MASK                                                              0x00002000L
#define SDMA3_RELAX_ORDERING_LUT__RESERVED_MASK                                                               0x07FFC000L
#define SDMA3_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK                                                           0x08000000L
#define SDMA3_RELAX_ORDERING_LUT__RPTR_WRB_MASK                                                               0x10000000L
#define SDMA3_RELAX_ORDERING_LUT__WPTR_POLL_MASK                                                              0x20000000L
#define SDMA3_RELAX_ORDERING_LUT__IB_FETCH_MASK                                                               0x40000000L
#define SDMA3_RELAX_ORDERING_LUT__RB_FETCH_MASK                                                               0x80000000L
//SDMA3_CHICKEN_BITS_2
#define SDMA3_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT                                                       0x0
#define SDMA3_CHICKEN_BITS_2__CE_BACKWARDS_SIZE_SEL__SHIFT                                                    0x4
#define SDMA3_CHICKEN_BITS_2__CE_DCC_READ_128B_ENABLE__SHIFT                                                  0x5
#define SDMA3_CHICKEN_BITS_2__UTCL1_FORCE_INV_RET_FIFO_FULL_EN__SHIFT                                         0x6
#define SDMA3_CHICKEN_BITS_2__RESERVED0__SHIFT                                                                0x7
#define SDMA3_CHICKEN_BITS_2__LUT_FIFO_AFULL_MARGIN__SHIFT                                                    0xb
#define SDMA3_CHICKEN_BITS_2__LEGACY_WPTR_POLL_BEHAVIOR__SHIFT                                                0xf
#define SDMA3_CHICKEN_BITS_2__RB_FIFO_WATERMARK__SHIFT                                                        0x10
#define SDMA3_CHICKEN_BITS_2__IB_FIFO_WATERMARK__SHIFT                                                        0x12
#define SDMA3_CHICKEN_BITS_2__REPEATER_FGCG_EN__SHIFT                                                         0x14
#define SDMA3_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN__SHIFT                                                     0x15
#define SDMA3_CHICKEN_BITS_2__RESERVED__SHIFT                                                                 0x16
#define SDMA3_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK                                                         0x0000000FL
#define SDMA3_CHICKEN_BITS_2__CE_BACKWARDS_SIZE_SEL_MASK                                                      0x00000010L
#define SDMA3_CHICKEN_BITS_2__CE_DCC_READ_128B_ENABLE_MASK                                                    0x00000020L
#define SDMA3_CHICKEN_BITS_2__UTCL1_FORCE_INV_RET_FIFO_FULL_EN_MASK                                           0x00000040L
#define SDMA3_CHICKEN_BITS_2__RESERVED0_MASK                                                                  0x00000780L
#define SDMA3_CHICKEN_BITS_2__LUT_FIFO_AFULL_MARGIN_MASK                                                      0x00007800L
#define SDMA3_CHICKEN_BITS_2__LEGACY_WPTR_POLL_BEHAVIOR_MASK                                                  0x00008000L
#define SDMA3_CHICKEN_BITS_2__RB_FIFO_WATERMARK_MASK                                                          0x00030000L
#define SDMA3_CHICKEN_BITS_2__IB_FIFO_WATERMARK_MASK                                                          0x000C0000L
#define SDMA3_CHICKEN_BITS_2__REPEATER_FGCG_EN_MASK                                                           0x00100000L
#define SDMA3_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN_MASK                                                       0x00200000L
#define SDMA3_CHICKEN_BITS_2__RESERVED_MASK                                                                   0xFFC00000L
//SDMA3_STATUS3_REG
#define SDMA3_STATUS3_REG__CMD_OP_STATUS__SHIFT                                                               0x0
#define SDMA3_STATUS3_REG__PREV_VM_CMD__SHIFT                                                                 0x10
#define SDMA3_STATUS3_REG__EXCEPTION_IDLE__SHIFT                                                              0x14
#define SDMA3_STATUS3_REG__AQL_PREV_CMD_IDLE__SHIFT                                                           0x15
#define SDMA3_STATUS3_REG__TLBI_IDLE__SHIFT                                                                   0x16
#define SDMA3_STATUS3_REG__GCR_IDLE__SHIFT                                                                    0x17
#define SDMA3_STATUS3_REG__INVREQ_IDLE__SHIFT                                                                 0x18
#define SDMA3_STATUS3_REG__QUEUE_ID_MATCH__SHIFT                                                              0x19
#define SDMA3_STATUS3_REG__INT_QUEUE_ID__SHIFT                                                                0x1a
#define SDMA3_STATUS3_REG__CMD_OP_STATUS_MASK                                                                 0x0000FFFFL
#define SDMA3_STATUS3_REG__PREV_VM_CMD_MASK                                                                   0x000F0000L
#define SDMA3_STATUS3_REG__EXCEPTION_IDLE_MASK                                                                0x00100000L
#define SDMA3_STATUS3_REG__AQL_PREV_CMD_IDLE_MASK                                                             0x00200000L
#define SDMA3_STATUS3_REG__TLBI_IDLE_MASK                                                                     0x00400000L
#define SDMA3_STATUS3_REG__GCR_IDLE_MASK                                                                      0x00800000L
#define SDMA3_STATUS3_REG__INVREQ_IDLE_MASK                                                                   0x01000000L
#define SDMA3_STATUS3_REG__QUEUE_ID_MATCH_MASK                                                                0x02000000L
#define SDMA3_STATUS3_REG__INT_QUEUE_ID_MASK                                                                  0x3C000000L
//SDMA3_PHYSICAL_ADDR_LO
#define SDMA3_PHYSICAL_ADDR_LO__D_VALID__SHIFT                                                                0x0
#define SDMA3_PHYSICAL_ADDR_LO__DIRTY__SHIFT                                                                  0x1
#define SDMA3_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT                                                              0x2
#define SDMA3_PHYSICAL_ADDR_LO__ADDR__SHIFT                                                                   0xc
#define SDMA3_PHYSICAL_ADDR_LO__D_VALID_MASK                                                                  0x00000001L
#define SDMA3_PHYSICAL_ADDR_LO__DIRTY_MASK                                                                    0x00000002L
#define SDMA3_PHYSICAL_ADDR_LO__PHY_VALID_MASK                                                                0x00000004L
#define SDMA3_PHYSICAL_ADDR_LO__ADDR_MASK                                                                     0xFFFFF000L
//SDMA3_PHYSICAL_ADDR_HI
#define SDMA3_PHYSICAL_ADDR_HI__ADDR__SHIFT                                                                   0x0
#define SDMA3_PHYSICAL_ADDR_HI__ADDR_MASK                                                                     0x0000FFFFL
//SDMA3_PHASE2_QUANTUM
#define SDMA3_PHASE2_QUANTUM__UNIT__SHIFT                                                                     0x0
#define SDMA3_PHASE2_QUANTUM__VALUE__SHIFT                                                                    0x8
#define SDMA3_PHASE2_QUANTUM__PREFER__SHIFT                                                                   0x1e
#define SDMA3_PHASE2_QUANTUM__UNIT_MASK                                                                       0x0000000FL
#define SDMA3_PHASE2_QUANTUM__VALUE_MASK                                                                      0x00FFFF00L
#define SDMA3_PHASE2_QUANTUM__PREFER_MASK                                                                     0x40000000L
//SDMA3_ERROR_LOG
#define SDMA3_ERROR_LOG__OVERRIDE__SHIFT                                                                      0x0
#define SDMA3_ERROR_LOG__STATUS__SHIFT                                                                        0x10
#define SDMA3_ERROR_LOG__OVERRIDE_MASK                                                                        0x0000FFFFL
#define SDMA3_ERROR_LOG__STATUS_MASK                                                                          0xFFFF0000L
//SDMA3_PUB_DUMMY_REG0
#define SDMA3_PUB_DUMMY_REG0__VALUE__SHIFT                                                                    0x0
#define SDMA3_PUB_DUMMY_REG0__VALUE_MASK                                                                      0xFFFFFFFFL
//SDMA3_PUB_DUMMY_REG1
#define SDMA3_PUB_DUMMY_REG1__VALUE__SHIFT                                                                    0x0
#define SDMA3_PUB_DUMMY_REG1__VALUE_MASK                                                                      0xFFFFFFFFL
//SDMA3_PUB_DUMMY_REG2
#define SDMA3_PUB_DUMMY_REG2__VALUE__SHIFT                                                                    0x0
#define SDMA3_PUB_DUMMY_REG2__VALUE_MASK                                                                      0xFFFFFFFFL
//SDMA3_PUB_DUMMY_REG3
#define SDMA3_PUB_DUMMY_REG3__VALUE__SHIFT                                                                    0x0
#define SDMA3_PUB_DUMMY_REG3__VALUE_MASK                                                                      0xFFFFFFFFL
//SDMA3_F32_COUNTER
#define SDMA3_F32_COUNTER__VALUE__SHIFT                                                                       0x0
#define SDMA3_F32_COUNTER__VALUE_MASK                                                                         0xFFFFFFFFL
//SDMA3_CRD_CNTL
#define SDMA3_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT                                                                0x7
#define SDMA3_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT                                                                0xd
#define SDMA3_CRD_CNTL__CH_WRREQ_CREDIT__SHIFT                                                                0x13
#define SDMA3_CRD_CNTL__CH_RDREQ_CREDIT__SHIFT                                                                0x19
#define SDMA3_CRD_CNTL__MC_WRREQ_CREDIT_MASK                                                                  0x00001F80L
#define SDMA3_CRD_CNTL__MC_RDREQ_CREDIT_MASK                                                                  0x0007E000L
#define SDMA3_CRD_CNTL__CH_WRREQ_CREDIT_MASK                                                                  0x01F80000L
#define SDMA3_CRD_CNTL__CH_RDREQ_CREDIT_MASK                                                                  0x7E000000L
//SDMA3_AQL_STATUS
#define SDMA3_AQL_STATUS__COMPLETE_SIGNAL_EMPTY__SHIFT                                                        0x0
#define SDMA3_AQL_STATUS__INVALID_CMD_EMPTY__SHIFT                                                            0x1
#define SDMA3_AQL_STATUS__COMPLETE_SIGNAL_EMPTY_MASK                                                          0x00000001L
#define SDMA3_AQL_STATUS__INVALID_CMD_EMPTY_MASK                                                              0x00000002L
//SDMA3_EA_DBIT_ADDR_DATA
#define SDMA3_EA_DBIT_ADDR_DATA__VALUE__SHIFT                                                                 0x0
#define SDMA3_EA_DBIT_ADDR_DATA__VALUE_MASK                                                                   0xFFFFFFFFL
//SDMA3_EA_DBIT_ADDR_INDEX
#define SDMA3_EA_DBIT_ADDR_INDEX__VALUE__SHIFT                                                                0x0
#define SDMA3_EA_DBIT_ADDR_INDEX__VALUE_MASK                                                                  0x00000007L
//SDMA3_TLBI_GCR_CNTL
#define SDMA3_TLBI_GCR_CNTL__TLBI_CMD_DW__SHIFT                                                               0x0
#define SDMA3_TLBI_GCR_CNTL__GCR_CMD_DW__SHIFT                                                                0x4
#define SDMA3_TLBI_GCR_CNTL__GCR_CLKEN_CYCLE__SHIFT                                                           0x8
#define SDMA3_TLBI_GCR_CNTL__TLBI_CREDIT__SHIFT                                                               0x10
#define SDMA3_TLBI_GCR_CNTL__GCR_CREDIT__SHIFT                                                                0x18
#define SDMA3_TLBI_GCR_CNTL__TLBI_CMD_DW_MASK                                                                 0x0000000FL
#define SDMA3_TLBI_GCR_CNTL__GCR_CMD_DW_MASK                                                                  0x000000F0L
#define SDMA3_TLBI_GCR_CNTL__GCR_CLKEN_CYCLE_MASK                                                             0x00000F00L
#define SDMA3_TLBI_GCR_CNTL__TLBI_CREDIT_MASK                                                                 0x00FF0000L
#define SDMA3_TLBI_GCR_CNTL__GCR_CREDIT_MASK                                                                  0xFF000000L
//SDMA3_TILING_CONFIG
#define SDMA3_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT                                                      0x4
#define SDMA3_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK                                                        0x00000070L
//SDMA3_INT_STATUS
#define SDMA3_INT_STATUS__DATA__SHIFT                                                                         0x0
#define SDMA3_INT_STATUS__DATA_MASK                                                                           0xFFFFFFFFL
//SDMA3_HOLE_ADDR_LO
#define SDMA3_HOLE_ADDR_LO__VALUE__SHIFT                                                                      0x0
#define SDMA3_HOLE_ADDR_LO__VALUE_MASK                                                                        0xFFFFFFFFL
//SDMA3_HOLE_ADDR_HI
#define SDMA3_HOLE_ADDR_HI__VALUE__SHIFT                                                                      0x0
#define SDMA3_HOLE_ADDR_HI__VALUE_MASK                                                                        0xFFFFFFFFL
//SDMA3_CLOCK_GATING_REG
#define SDMA3_CLOCK_GATING_REG__DYN_CLK_GATE_STATUS__SHIFT                                                    0x0
#define SDMA3_CLOCK_GATING_REG__PTR_CLK_GATE_STATUS__SHIFT                                                    0x1
#define SDMA3_CLOCK_GATING_REG__CE_CLK_GATE_STATUS__SHIFT                                                     0x2
#define SDMA3_CLOCK_GATING_REG__CE_BC_CLK_GATE_STATUS__SHIFT                                                  0x3
#define SDMA3_CLOCK_GATING_REG__CE_NBC_CLK_GATE_STATUS__SHIFT                                                 0x4
#define SDMA3_CLOCK_GATING_REG__REG_CLK_GATE_STATUS__SHIFT                                                    0x5
#define SDMA3_CLOCK_GATING_REG__DYN_CLK_GATE_STATUS_MASK                                                      0x00000001L
#define SDMA3_CLOCK_GATING_REG__PTR_CLK_GATE_STATUS_MASK                                                      0x00000002L
#define SDMA3_CLOCK_GATING_REG__CE_CLK_GATE_STATUS_MASK                                                       0x00000004L
#define SDMA3_CLOCK_GATING_REG__CE_BC_CLK_GATE_STATUS_MASK                                                    0x00000008L
#define SDMA3_CLOCK_GATING_REG__CE_NBC_CLK_GATE_STATUS_MASK                                                   0x00000010L
#define SDMA3_CLOCK_GATING_REG__REG_CLK_GATE_STATUS_MASK                                                      0x00000020L
//SDMA3_STATUS4_REG
#define SDMA3_STATUS4_REG__IDLE__SHIFT                                                                        0x0
#define SDMA3_STATUS4_REG__IH_OUTSTANDING__SHIFT                                                              0x2
#define SDMA3_STATUS4_REG__SEM_OUTSTANDING__SHIFT                                                             0x3
#define SDMA3_STATUS4_REG__CH_RD_OUTSTANDING__SHIFT                                                           0x4
#define SDMA3_STATUS4_REG__CH_WR_OUTSTANDING__SHIFT                                                           0x5
#define SDMA3_STATUS4_REG__GCR_OUTSTANDING__SHIFT                                                             0x6
#define SDMA3_STATUS4_REG__TLBI_OUTSTANDING__SHIFT                                                            0x7
#define SDMA3_STATUS4_REG__UTCL2_RD_OUTSTANDING__SHIFT                                                        0x8
#define SDMA3_STATUS4_REG__UTCL2_WR_OUTSTANDING__SHIFT                                                        0x9
#define SDMA3_STATUS4_REG__REG_POLLING__SHIFT                                                                 0xa
#define SDMA3_STATUS4_REG__MEM_POLLING__SHIFT                                                                 0xb
#define SDMA3_STATUS4_REG__UTCL2_RD_XNACK__SHIFT                                                              0xc
#define SDMA3_STATUS4_REG__UTCL2_WR_XNACK__SHIFT                                                              0xe
#define SDMA3_STATUS4_REG__ACTIVE_QUEUE_ID__SHIFT                                                             0x10
#define SDMA3_STATUS4_REG__SRIOV_WATING_RLCV_CMD__SHIFT                                                       0x14
#define SDMA3_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD__SHIFT                                                    0x15
#define SDMA3_STATUS4_REG__IDLE_MASK                                                                          0x00000001L
#define SDMA3_STATUS4_REG__IH_OUTSTANDING_MASK                                                                0x00000004L
#define SDMA3_STATUS4_REG__SEM_OUTSTANDING_MASK                                                               0x00000008L
#define SDMA3_STATUS4_REG__CH_RD_OUTSTANDING_MASK                                                             0x00000010L
#define SDMA3_STATUS4_REG__CH_WR_OUTSTANDING_MASK                                                             0x00000020L
#define SDMA3_STATUS4_REG__GCR_OUTSTANDING_MASK                                                               0x00000040L
#define SDMA3_STATUS4_REG__TLBI_OUTSTANDING_MASK                                                              0x00000080L
#define SDMA3_STATUS4_REG__UTCL2_RD_OUTSTANDING_MASK                                                          0x00000100L
#define SDMA3_STATUS4_REG__UTCL2_WR_OUTSTANDING_MASK                                                          0x00000200L
#define SDMA3_STATUS4_REG__REG_POLLING_MASK                                                                   0x00000400L
#define SDMA3_STATUS4_REG__MEM_POLLING_MASK                                                                   0x00000800L
#define SDMA3_STATUS4_REG__UTCL2_RD_XNACK_MASK                                                                0x00003000L
#define SDMA3_STATUS4_REG__UTCL2_WR_XNACK_MASK                                                                0x0000C000L
#define SDMA3_STATUS4_REG__ACTIVE_QUEUE_ID_MASK                                                               0x000F0000L
#define SDMA3_STATUS4_REG__SRIOV_WATING_RLCV_CMD_MASK                                                         0x00100000L
#define SDMA3_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD_MASK                                                      0x00200000L
//SDMA3_SCRATCH_RAM_DATA
#define SDMA3_SCRATCH_RAM_DATA__DATA__SHIFT                                                                   0x0
#define SDMA3_SCRATCH_RAM_DATA__DATA_MASK                                                                     0xFFFFFFFFL
//SDMA3_SCRATCH_RAM_ADDR
#define SDMA3_SCRATCH_RAM_ADDR__ADDR__SHIFT                                                                   0x0
#define SDMA3_SCRATCH_RAM_ADDR__ADDR_MASK                                                                     0x000003FFL
//SDMA3_TIMESTAMP_CNTL
#define SDMA3_TIMESTAMP_CNTL__CAPTURE__SHIFT                                                                  0x0
#define SDMA3_TIMESTAMP_CNTL__CAPTURE_MASK                                                                    0x00000001L
//SDMA3_STATUS5_REG
#define SDMA3_STATUS5_REG__GFX_RB_ENABLE_STATUS__SHIFT                                                        0x0
#define SDMA3_STATUS5_REG__PAGE_RB_ENABLE_STATUS__SHIFT                                                       0x1
#define SDMA3_STATUS5_REG__RLC0_RB_ENABLE_STATUS__SHIFT                                                       0x2
#define SDMA3_STATUS5_REG__RLC1_RB_ENABLE_STATUS__SHIFT                                                       0x3
#define SDMA3_STATUS5_REG__RLC2_RB_ENABLE_STATUS__SHIFT                                                       0x4
#define SDMA3_STATUS5_REG__RLC3_RB_ENABLE_STATUS__SHIFT                                                       0x5
#define SDMA3_STATUS5_REG__RLC4_RB_ENABLE_STATUS__SHIFT                                                       0x6
#define SDMA3_STATUS5_REG__RLC5_RB_ENABLE_STATUS__SHIFT                                                       0x7
#define SDMA3_STATUS5_REG__RLC6_RB_ENABLE_STATUS__SHIFT                                                       0x8
#define SDMA3_STATUS5_REG__RLC7_RB_ENABLE_STATUS__SHIFT                                                       0x9
#define SDMA3_STATUS5_REG__ACTIVE_QUEUE_ID__SHIFT                                                             0x10
#define SDMA3_STATUS5_REG__GFX_RB_ENABLE_STATUS_MASK                                                          0x00000001L
#define SDMA3_STATUS5_REG__PAGE_RB_ENABLE_STATUS_MASK                                                         0x00000002L
#define SDMA3_STATUS5_REG__RLC0_RB_ENABLE_STATUS_MASK                                                         0x00000004L
#define SDMA3_STATUS5_REG__RLC1_RB_ENABLE_STATUS_MASK                                                         0x00000008L
#define SDMA3_STATUS5_REG__RLC2_RB_ENABLE_STATUS_MASK                                                         0x00000010L
#define SDMA3_STATUS5_REG__RLC3_RB_ENABLE_STATUS_MASK                                                         0x00000020L
#define SDMA3_STATUS5_REG__RLC4_RB_ENABLE_STATUS_MASK                                                         0x00000040L
#define SDMA3_STATUS5_REG__RLC5_RB_ENABLE_STATUS_MASK                                                         0x00000080L
#define SDMA3_STATUS5_REG__RLC6_RB_ENABLE_STATUS_MASK                                                         0x00000100L
#define SDMA3_STATUS5_REG__RLC7_RB_ENABLE_STATUS_MASK                                                         0x00000200L
#define SDMA3_STATUS5_REG__ACTIVE_QUEUE_ID_MASK                                                               0x000F0000L
//SDMA3_QUEUE_RESET_REQ
#define SDMA3_QUEUE_RESET_REQ__GFX_QUEUE_RESET__SHIFT                                                         0x0
#define SDMA3_QUEUE_RESET_REQ__PAGE_QUEUE_RESET__SHIFT                                                        0x1
#define SDMA3_QUEUE_RESET_REQ__RLC0_QUEUE_RESET__SHIFT                                                        0x2
#define SDMA3_QUEUE_RESET_REQ__RLC1_QUEUE_RESET__SHIFT                                                        0x3
#define SDMA3_QUEUE_RESET_REQ__RLC2_QUEUE_RESET__SHIFT                                                        0x4
#define SDMA3_QUEUE_RESET_REQ__RLC3_QUEUE_RESET__SHIFT                                                        0x5
#define SDMA3_QUEUE_RESET_REQ__RLC4_QUEUE_RESET__SHIFT                                                        0x6
#define SDMA3_QUEUE_RESET_REQ__RLC5_QUEUE_RESET__SHIFT                                                        0x7
#define SDMA3_QUEUE_RESET_REQ__RLC6_QUEUE_RESET__SHIFT                                                        0x8
#define SDMA3_QUEUE_RESET_REQ__RLC7_QUEUE_RESET__SHIFT                                                        0x9
#define SDMA3_QUEUE_RESET_REQ__RESERVED__SHIFT                                                                0xa
#define SDMA3_QUEUE_RESET_REQ__GFX_QUEUE_RESET_MASK                                                           0x00000001L
#define SDMA3_QUEUE_RESET_REQ__PAGE_QUEUE_RESET_MASK                                                          0x00000002L
#define SDMA3_QUEUE_RESET_REQ__RLC0_QUEUE_RESET_MASK                                                          0x00000004L
#define SDMA3_QUEUE_RESET_REQ__RLC1_QUEUE_RESET_MASK                                                          0x00000008L
#define SDMA3_QUEUE_RESET_REQ__RLC2_QUEUE_RESET_MASK                                                          0x00000010L
#define SDMA3_QUEUE_RESET_REQ__RLC3_QUEUE_RESET_MASK                                                          0x00000020L
#define SDMA3_QUEUE_RESET_REQ__RLC4_QUEUE_RESET_MASK                                                          0x00000040L
#define SDMA3_QUEUE_RESET_REQ__RLC5_QUEUE_RESET_MASK                                                          0x00000080L
#define SDMA3_QUEUE_RESET_REQ__RLC6_QUEUE_RESET_MASK                                                          0x00000100L
#define SDMA3_QUEUE_RESET_REQ__RLC7_QUEUE_RESET_MASK                                                          0x00000200L
#define SDMA3_QUEUE_RESET_REQ__RESERVED_MASK                                                                  0xFFFFFC00L
//SDMA3_GFX_RB_CNTL
#define SDMA3_GFX_RB_CNTL__RB_ENABLE__SHIFT                                                                   0x0
#define SDMA3_GFX_RB_CNTL__RB_SIZE__SHIFT                                                                     0x1
#define SDMA3_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                              0x9
#define SDMA3_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                       0xc
#define SDMA3_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                  0xd
#define SDMA3_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                        0x10
#define SDMA3_GFX_RB_CNTL__RB_PRIV__SHIFT                                                                     0x17
#define SDMA3_GFX_RB_CNTL__RB_VMID__SHIFT                                                                     0x18
#define SDMA3_GFX_RB_CNTL__RPTR_WB_IDLE__SHIFT                                                                0x1f
#define SDMA3_GFX_RB_CNTL__RB_ENABLE_MASK                                                                     0x00000001L
#define SDMA3_GFX_RB_CNTL__RB_SIZE_MASK                                                                       0x0000003EL
#define SDMA3_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK                                                                0x00000200L
#define SDMA3_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                         0x00001000L
#define SDMA3_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                    0x00002000L
#define SDMA3_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                          0x001F0000L
#define SDMA3_GFX_RB_CNTL__RB_PRIV_MASK                                                                       0x00800000L
#define SDMA3_GFX_RB_CNTL__RB_VMID_MASK                                                                       0x0F000000L
#define SDMA3_GFX_RB_CNTL__RPTR_WB_IDLE_MASK                                                                  0x80000000L
//SDMA3_GFX_RB_BASE
#define SDMA3_GFX_RB_BASE__ADDR__SHIFT                                                                        0x0
#define SDMA3_GFX_RB_BASE__ADDR_MASK                                                                          0xFFFFFFFFL
//SDMA3_GFX_RB_BASE_HI
#define SDMA3_GFX_RB_BASE_HI__ADDR__SHIFT                                                                     0x0
#define SDMA3_GFX_RB_BASE_HI__ADDR_MASK                                                                       0x00FFFFFFL
//SDMA3_GFX_RB_RPTR
#define SDMA3_GFX_RB_RPTR__OFFSET__SHIFT                                                                      0x0
#define SDMA3_GFX_RB_RPTR__OFFSET_MASK                                                                        0xFFFFFFFFL
//SDMA3_GFX_RB_RPTR_HI
#define SDMA3_GFX_RB_RPTR_HI__OFFSET__SHIFT                                                                   0x0
#define SDMA3_GFX_RB_RPTR_HI__OFFSET_MASK                                                                     0xFFFFFFFFL
//SDMA3_GFX_RB_WPTR
#define SDMA3_GFX_RB_WPTR__OFFSET__SHIFT                                                                      0x0
#define SDMA3_GFX_RB_WPTR__OFFSET_MASK                                                                        0xFFFFFFFFL
//SDMA3_GFX_RB_WPTR_HI
#define SDMA3_GFX_RB_WPTR_HI__OFFSET__SHIFT                                                                   0x0
#define SDMA3_GFX_RB_WPTR_HI__OFFSET_MASK                                                                     0xFFFFFFFFL
//SDMA3_GFX_RB_WPTR_POLL_CNTL
#define SDMA3_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                            0x0
#define SDMA3_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                       0x1
#define SDMA3_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                   0x2
#define SDMA3_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                         0x4
#define SDMA3_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                   0x10
#define SDMA3_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                              0x00000001L
#define SDMA3_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                         0x00000002L
#define SDMA3_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                     0x00000004L
#define SDMA3_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                           0x0000FFF0L
#define SDMA3_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                     0xFFFF0000L
//SDMA3_GFX_RB_RPTR_ADDR_HI
#define SDMA3_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                                0x0
#define SDMA3_GFX_RB_RPTR_ADDR_HI__ADDR_MASK                                                                  0xFFFFFFFFL
//SDMA3_GFX_RB_RPTR_ADDR_LO
#define SDMA3_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                                0x2
#define SDMA3_GFX_RB_RPTR_ADDR_LO__ADDR_MASK                                                                  0xFFFFFFFCL
//SDMA3_GFX_IB_CNTL
#define SDMA3_GFX_IB_CNTL__IB_ENABLE__SHIFT                                                                   0x0
#define SDMA3_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                              0x4
#define SDMA3_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                            0x8
#define SDMA3_GFX_IB_CNTL__CMD_VMID__SHIFT                                                                    0x10
#define SDMA3_GFX_IB_CNTL__IB_ENABLE_MASK                                                                     0x00000001L
#define SDMA3_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK                                                                0x00000010L
#define SDMA3_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                              0x00000100L
#define SDMA3_GFX_IB_CNTL__CMD_VMID_MASK                                                                      0x000F0000L
//SDMA3_GFX_IB_RPTR
#define SDMA3_GFX_IB_RPTR__OFFSET__SHIFT                                                                      0x2
#define SDMA3_GFX_IB_RPTR__OFFSET_MASK                                                                        0x003FFFFCL
//SDMA3_GFX_IB_OFFSET
#define SDMA3_GFX_IB_OFFSET__OFFSET__SHIFT                                                                    0x2
#define SDMA3_GFX_IB_OFFSET__OFFSET_MASK                                                                      0x003FFFFCL
//SDMA3_GFX_IB_BASE_LO
#define SDMA3_GFX_IB_BASE_LO__ADDR__SHIFT                                                                     0x5
#define SDMA3_GFX_IB_BASE_LO__ADDR_MASK                                                                       0xFFFFFFE0L
//SDMA3_GFX_IB_BASE_HI
#define SDMA3_GFX_IB_BASE_HI__ADDR__SHIFT                                                                     0x0
#define SDMA3_GFX_IB_BASE_HI__ADDR_MASK                                                                       0xFFFFFFFFL
//SDMA3_GFX_IB_SIZE
#define SDMA3_GFX_IB_SIZE__SIZE__SHIFT                                                                        0x0
#define SDMA3_GFX_IB_SIZE__SIZE_MASK                                                                          0x000FFFFFL
//SDMA3_GFX_SKIP_CNTL
#define SDMA3_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT                                                                0x0
#define SDMA3_GFX_SKIP_CNTL__SKIP_COUNT_MASK                                                                  0x000FFFFFL
//SDMA3_GFX_CONTEXT_STATUS
#define SDMA3_GFX_CONTEXT_STATUS__SELECTED__SHIFT                                                             0x0
#define SDMA3_GFX_CONTEXT_STATUS__IDLE__SHIFT                                                                 0x2
#define SDMA3_GFX_CONTEXT_STATUS__EXPIRED__SHIFT                                                              0x3
#define SDMA3_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT                                                            0x4
#define SDMA3_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                           0x7
#define SDMA3_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                          0x8
#define SDMA3_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT                                                            0x9
#define SDMA3_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                      0xa
#define SDMA3_GFX_CONTEXT_STATUS__SELECTED_MASK                                                               0x00000001L
#define SDMA3_GFX_CONTEXT_STATUS__IDLE_MASK                                                                   0x00000004L
#define SDMA3_GFX_CONTEXT_STATUS__EXPIRED_MASK                                                                0x00000008L
#define SDMA3_GFX_CONTEXT_STATUS__EXCEPTION_MASK                                                              0x00000070L
#define SDMA3_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                             0x00000080L
#define SDMA3_GFX_CONTEXT_STATUS__CTXSW_READY_MASK                                                            0x00000100L
#define SDMA3_GFX_CONTEXT_STATUS__PREEMPTED_MASK                                                              0x00000200L
#define SDMA3_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                        0x00000400L
//SDMA3_GFX_DOORBELL
#define SDMA3_GFX_DOORBELL__ENABLE__SHIFT                                                                     0x1c
#define SDMA3_GFX_DOORBELL__CAPTURED__SHIFT                                                                   0x1e
#define SDMA3_GFX_DOORBELL__ENABLE_MASK                                                                       0x10000000L
#define SDMA3_GFX_DOORBELL__CAPTURED_MASK                                                                     0x40000000L
//SDMA3_GFX_CONTEXT_CNTL
#define SDMA3_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT                                                             0x10
#define SDMA3_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT                                                            0x18
#define SDMA3_GFX_CONTEXT_CNTL__RESUME_CTX_MASK                                                               0x00010000L
#define SDMA3_GFX_CONTEXT_CNTL__SESSION_SEL_MASK                                                              0x0F000000L
//SDMA3_GFX_STATUS
#define SDMA3_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                       0x0
#define SDMA3_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                          0x8
#define SDMA3_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                         0x000000FFL
#define SDMA3_GFX_STATUS__WPTR_UPDATE_PENDING_MASK                                                            0x00000100L
//SDMA3_GFX_DOORBELL_LOG
#define SDMA3_GFX_DOORBELL_LOG__BE_ERROR__SHIFT                                                               0x0
#define SDMA3_GFX_DOORBELL_LOG__DATA__SHIFT                                                                   0x2
#define SDMA3_GFX_DOORBELL_LOG__BE_ERROR_MASK                                                                 0x00000001L
#define SDMA3_GFX_DOORBELL_LOG__DATA_MASK                                                                     0xFFFFFFFCL
//SDMA3_GFX_WATERMARK
#define SDMA3_GFX_WATERMARK__RD_OUTSTANDING__SHIFT                                                            0x0
#define SDMA3_GFX_WATERMARK__WR_OUTSTANDING__SHIFT                                                            0x10
#define SDMA3_GFX_WATERMARK__RD_OUTSTANDING_MASK                                                              0x00000FFFL
#define SDMA3_GFX_WATERMARK__WR_OUTSTANDING_MASK                                                              0x03FF0000L
//SDMA3_GFX_DOORBELL_OFFSET
#define SDMA3_GFX_DOORBELL_OFFSET__OFFSET__SHIFT                                                              0x2
#define SDMA3_GFX_DOORBELL_OFFSET__OFFSET_MASK                                                                0x0FFFFFFCL
//SDMA3_GFX_CSA_ADDR_LO
#define SDMA3_GFX_CSA_ADDR_LO__ADDR__SHIFT                                                                    0x2
#define SDMA3_GFX_CSA_ADDR_LO__ADDR_MASK                                                                      0xFFFFFFFCL
//SDMA3_GFX_CSA_ADDR_HI
#define SDMA3_GFX_CSA_ADDR_HI__ADDR__SHIFT                                                                    0x0
#define SDMA3_GFX_CSA_ADDR_HI__ADDR_MASK                                                                      0xFFFFFFFFL
//SDMA3_GFX_IB_SUB_REMAIN
#define SDMA3_GFX_IB_SUB_REMAIN__SIZE__SHIFT                                                                  0x0
#define SDMA3_GFX_IB_SUB_REMAIN__SIZE_MASK                                                                    0x00003FFFL
//SDMA3_GFX_PREEMPT
#define SDMA3_GFX_PREEMPT__IB_PREEMPT__SHIFT                                                                  0x0
#define SDMA3_GFX_PREEMPT__IB_PREEMPT_MASK                                                                    0x00000001L
//SDMA3_GFX_DUMMY_REG
#define SDMA3_GFX_DUMMY_REG__DUMMY__SHIFT                                                                     0x0
#define SDMA3_GFX_DUMMY_REG__DUMMY_MASK                                                                       0xFFFFFFFFL
//SDMA3_GFX_RB_WPTR_POLL_ADDR_HI
#define SDMA3_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                           0x0
#define SDMA3_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                             0xFFFFFFFFL
//SDMA3_GFX_RB_WPTR_POLL_ADDR_LO
#define SDMA3_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                           0x2
#define SDMA3_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                             0xFFFFFFFCL
//SDMA3_GFX_RB_AQL_CNTL
#define SDMA3_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                              0x0
#define SDMA3_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                         0x1
#define SDMA3_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                             0x8
#define SDMA3_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                   0x10
#define SDMA3_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT                                             0x11
#define SDMA3_GFX_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT                                                          0x12
#define SDMA3_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK                                                                0x00000001L
#define SDMA3_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                           0x000000FEL
#define SDMA3_GFX_RB_AQL_CNTL__PACKET_STEP_MASK                                                               0x0000FF00L
#define SDMA3_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                     0x00010000L
#define SDMA3_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK                                               0x00020000L
#define SDMA3_GFX_RB_AQL_CNTL__OVERLAP_ENABLE_MASK                                                            0x00040000L
//SDMA3_GFX_MINOR_PTR_UPDATE
#define SDMA3_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                             0x0
#define SDMA3_GFX_MINOR_PTR_UPDATE__ENABLE_MASK                                                               0x00000001L
//SDMA3_GFX_MIDCMD_DATA0
#define SDMA3_GFX_MIDCMD_DATA0__DATA0__SHIFT                                                                  0x0
#define SDMA3_GFX_MIDCMD_DATA0__DATA0_MASK                                                                    0xFFFFFFFFL
//SDMA3_GFX_MIDCMD_DATA1
#define SDMA3_GFX_MIDCMD_DATA1__DATA1__SHIFT                                                                  0x0
#define SDMA3_GFX_MIDCMD_DATA1__DATA1_MASK                                                                    0xFFFFFFFFL
//SDMA3_GFX_MIDCMD_DATA2
#define SDMA3_GFX_MIDCMD_DATA2__DATA2__SHIFT                                                                  0x0
#define SDMA3_GFX_MIDCMD_DATA2__DATA2_MASK                                                                    0xFFFFFFFFL
//SDMA3_GFX_MIDCMD_DATA3
#define SDMA3_GFX_MIDCMD_DATA3__DATA3__SHIFT                                                                  0x0
#define SDMA3_GFX_MIDCMD_DATA3__DATA3_MASK                                                                    0xFFFFFFFFL
//SDMA3_GFX_MIDCMD_DATA4
#define SDMA3_GFX_MIDCMD_DATA4__DATA4__SHIFT                                                                  0x0
#define SDMA3_GFX_MIDCMD_DATA4__DATA4_MASK                                                                    0xFFFFFFFFL
//SDMA3_GFX_MIDCMD_DATA5
#define SDMA3_GFX_MIDCMD_DATA5__DATA5__SHIFT                                                                  0x0
#define SDMA3_GFX_MIDCMD_DATA5__DATA5_MASK                                                                    0xFFFFFFFFL
//SDMA3_GFX_MIDCMD_DATA6
#define SDMA3_GFX_MIDCMD_DATA6__DATA6__SHIFT                                                                  0x0
#define SDMA3_GFX_MIDCMD_DATA6__DATA6_MASK                                                                    0xFFFFFFFFL
//SDMA3_GFX_MIDCMD_DATA7
#define SDMA3_GFX_MIDCMD_DATA7__DATA7__SHIFT                                                                  0x0
#define SDMA3_GFX_MIDCMD_DATA7__DATA7_MASK                                                                    0xFFFFFFFFL
//SDMA3_GFX_MIDCMD_DATA8
#define SDMA3_GFX_MIDCMD_DATA8__DATA8__SHIFT                                                                  0x0
#define SDMA3_GFX_MIDCMD_DATA8__DATA8_MASK                                                                    0xFFFFFFFFL
//SDMA3_GFX_MIDCMD_DATA9
#define SDMA3_GFX_MIDCMD_DATA9__DATA9__SHIFT                                                                  0x0
#define SDMA3_GFX_MIDCMD_DATA9__DATA9_MASK                                                                    0xFFFFFFFFL
//SDMA3_GFX_MIDCMD_DATA10
#define SDMA3_GFX_MIDCMD_DATA10__DATA10__SHIFT                                                                0x0
#define SDMA3_GFX_MIDCMD_DATA10__DATA10_MASK                                                                  0xFFFFFFFFL
//SDMA3_GFX_MIDCMD_CNTL
#define SDMA3_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT                                                              0x0
#define SDMA3_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT                                                               0x1
#define SDMA3_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                             0x4
#define SDMA3_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                           0x8
#define SDMA3_GFX_MIDCMD_CNTL__DATA_VALID_MASK                                                                0x00000001L
#define SDMA3_GFX_MIDCMD_CNTL__COPY_MODE_MASK                                                                 0x00000002L
#define SDMA3_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK                                                               0x000000F0L
#define SDMA3_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                             0x00000100L
//SDMA3_PAGE_RB_CNTL
#define SDMA3_PAGE_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
#define SDMA3_PAGE_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
#define SDMA3_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
#define SDMA3_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
#define SDMA3_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
#define SDMA3_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
#define SDMA3_PAGE_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
#define SDMA3_PAGE_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
#define SDMA3_PAGE_RB_CNTL__RPTR_WB_IDLE__SHIFT                                                               0x1f
#define SDMA3_PAGE_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
#define SDMA3_PAGE_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
#define SDMA3_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
#define SDMA3_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
#define SDMA3_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
#define SDMA3_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
#define SDMA3_PAGE_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
#define SDMA3_PAGE_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
#define SDMA3_PAGE_RB_CNTL__RPTR_WB_IDLE_MASK                                                                 0x80000000L
//SDMA3_PAGE_RB_BASE
#define SDMA3_PAGE_RB_BASE__ADDR__SHIFT                                                                       0x0
#define SDMA3_PAGE_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
//SDMA3_PAGE_RB_BASE_HI
#define SDMA3_PAGE_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA3_PAGE_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
//SDMA3_PAGE_RB_RPTR
#define SDMA3_PAGE_RB_RPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA3_PAGE_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA3_PAGE_RB_RPTR_HI
#define SDMA3_PAGE_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA3_PAGE_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA3_PAGE_RB_WPTR
#define SDMA3_PAGE_RB_WPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA3_PAGE_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA3_PAGE_RB_WPTR_HI
#define SDMA3_PAGE_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA3_PAGE_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA3_PAGE_RB_WPTR_POLL_CNTL
#define SDMA3_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
#define SDMA3_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
#define SDMA3_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
#define SDMA3_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
#define SDMA3_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
#define SDMA3_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
#define SDMA3_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
#define SDMA3_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
#define SDMA3_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
#define SDMA3_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
//SDMA3_PAGE_RB_RPTR_ADDR_HI
#define SDMA3_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
#define SDMA3_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
//SDMA3_PAGE_RB_RPTR_ADDR_LO
#define SDMA3_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
#define SDMA3_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
//SDMA3_PAGE_IB_CNTL
#define SDMA3_PAGE_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
#define SDMA3_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
#define SDMA3_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
#define SDMA3_PAGE_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
#define SDMA3_PAGE_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
#define SDMA3_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
#define SDMA3_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
#define SDMA3_PAGE_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
//SDMA3_PAGE_IB_RPTR
#define SDMA3_PAGE_IB_RPTR__OFFSET__SHIFT                                                                     0x2
#define SDMA3_PAGE_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
//SDMA3_PAGE_IB_OFFSET
#define SDMA3_PAGE_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
#define SDMA3_PAGE_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
//SDMA3_PAGE_IB_BASE_LO
#define SDMA3_PAGE_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
#define SDMA3_PAGE_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
//SDMA3_PAGE_IB_BASE_HI
#define SDMA3_PAGE_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA3_PAGE_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
//SDMA3_PAGE_IB_SIZE
#define SDMA3_PAGE_IB_SIZE__SIZE__SHIFT                                                                       0x0
#define SDMA3_PAGE_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
//SDMA3_PAGE_SKIP_CNTL
#define SDMA3_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
#define SDMA3_PAGE_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
//SDMA3_PAGE_CONTEXT_STATUS
#define SDMA3_PAGE_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
#define SDMA3_PAGE_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
#define SDMA3_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
#define SDMA3_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
#define SDMA3_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
#define SDMA3_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
#define SDMA3_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
#define SDMA3_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
#define SDMA3_PAGE_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
#define SDMA3_PAGE_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
#define SDMA3_PAGE_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
#define SDMA3_PAGE_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
#define SDMA3_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
#define SDMA3_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
#define SDMA3_PAGE_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
#define SDMA3_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
//SDMA3_PAGE_DOORBELL
#define SDMA3_PAGE_DOORBELL__ENABLE__SHIFT                                                                    0x1c
#define SDMA3_PAGE_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
#define SDMA3_PAGE_DOORBELL__ENABLE_MASK                                                                      0x10000000L
#define SDMA3_PAGE_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
//SDMA3_PAGE_STATUS
#define SDMA3_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
#define SDMA3_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
#define SDMA3_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
#define SDMA3_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
//SDMA3_PAGE_DOORBELL_LOG
#define SDMA3_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
#define SDMA3_PAGE_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
#define SDMA3_PAGE_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
#define SDMA3_PAGE_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
//SDMA3_PAGE_WATERMARK
#define SDMA3_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
#define SDMA3_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
#define SDMA3_PAGE_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
#define SDMA3_PAGE_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
//SDMA3_PAGE_DOORBELL_OFFSET
#define SDMA3_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
#define SDMA3_PAGE_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
//SDMA3_PAGE_CSA_ADDR_LO
#define SDMA3_PAGE_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
#define SDMA3_PAGE_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
//SDMA3_PAGE_CSA_ADDR_HI
#define SDMA3_PAGE_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
#define SDMA3_PAGE_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
//SDMA3_PAGE_IB_SUB_REMAIN
#define SDMA3_PAGE_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
#define SDMA3_PAGE_IB_SUB_REMAIN__SIZE_MASK                                                                   0x00003FFFL
//SDMA3_PAGE_PREEMPT
#define SDMA3_PAGE_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
#define SDMA3_PAGE_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
//SDMA3_PAGE_DUMMY_REG
#define SDMA3_PAGE_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
#define SDMA3_PAGE_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
//SDMA3_PAGE_RB_WPTR_POLL_ADDR_HI
#define SDMA3_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
#define SDMA3_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
//SDMA3_PAGE_RB_WPTR_POLL_ADDR_LO
#define SDMA3_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
#define SDMA3_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
//SDMA3_PAGE_RB_AQL_CNTL
#define SDMA3_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
#define SDMA3_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
#define SDMA3_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
#define SDMA3_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                  0x10
#define SDMA3_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT                                            0x11
#define SDMA3_PAGE_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT                                                         0x12
#define SDMA3_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
#define SDMA3_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
#define SDMA3_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
#define SDMA3_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                    0x00010000L
#define SDMA3_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK                                              0x00020000L
#define SDMA3_PAGE_RB_AQL_CNTL__OVERLAP_ENABLE_MASK                                                           0x00040000L
//SDMA3_PAGE_MINOR_PTR_UPDATE
#define SDMA3_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
#define SDMA3_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
//SDMA3_PAGE_MIDCMD_DATA0
#define SDMA3_PAGE_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
#define SDMA3_PAGE_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
//SDMA3_PAGE_MIDCMD_DATA1
#define SDMA3_PAGE_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
#define SDMA3_PAGE_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
//SDMA3_PAGE_MIDCMD_DATA2
#define SDMA3_PAGE_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
#define SDMA3_PAGE_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
//SDMA3_PAGE_MIDCMD_DATA3
#define SDMA3_PAGE_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
#define SDMA3_PAGE_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
//SDMA3_PAGE_MIDCMD_DATA4
#define SDMA3_PAGE_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
#define SDMA3_PAGE_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
//SDMA3_PAGE_MIDCMD_DATA5
#define SDMA3_PAGE_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
#define SDMA3_PAGE_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
//SDMA3_PAGE_MIDCMD_DATA6
#define SDMA3_PAGE_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
#define SDMA3_PAGE_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
//SDMA3_PAGE_MIDCMD_DATA7
#define SDMA3_PAGE_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
#define SDMA3_PAGE_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
//SDMA3_PAGE_MIDCMD_DATA8
#define SDMA3_PAGE_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
#define SDMA3_PAGE_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
//SDMA3_PAGE_MIDCMD_DATA9
#define SDMA3_PAGE_MIDCMD_DATA9__DATA9__SHIFT                                                                 0x0
#define SDMA3_PAGE_MIDCMD_DATA9__DATA9_MASK                                                                   0xFFFFFFFFL
//SDMA3_PAGE_MIDCMD_DATA10
#define SDMA3_PAGE_MIDCMD_DATA10__DATA10__SHIFT                                                               0x0
#define SDMA3_PAGE_MIDCMD_DATA10__DATA10_MASK                                                                 0xFFFFFFFFL
//SDMA3_PAGE_MIDCMD_CNTL
#define SDMA3_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
#define SDMA3_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
#define SDMA3_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
#define SDMA3_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
#define SDMA3_PAGE_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
#define SDMA3_PAGE_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
#define SDMA3_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
#define SDMA3_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
//SDMA3_RLC0_RB_CNTL
#define SDMA3_RLC0_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
#define SDMA3_RLC0_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
#define SDMA3_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
#define SDMA3_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
#define SDMA3_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
#define SDMA3_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
#define SDMA3_RLC0_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
#define SDMA3_RLC0_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
#define SDMA3_RLC0_RB_CNTL__RPTR_WB_IDLE__SHIFT                                                               0x1f
#define SDMA3_RLC0_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
#define SDMA3_RLC0_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
#define SDMA3_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
#define SDMA3_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
#define SDMA3_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
#define SDMA3_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
#define SDMA3_RLC0_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
#define SDMA3_RLC0_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
#define SDMA3_RLC0_RB_CNTL__RPTR_WB_IDLE_MASK                                                                 0x80000000L
//SDMA3_RLC0_RB_BASE
#define SDMA3_RLC0_RB_BASE__ADDR__SHIFT                                                                       0x0
#define SDMA3_RLC0_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
//SDMA3_RLC0_RB_BASE_HI
#define SDMA3_RLC0_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA3_RLC0_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
//SDMA3_RLC0_RB_RPTR
#define SDMA3_RLC0_RB_RPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA3_RLC0_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA3_RLC0_RB_RPTR_HI
#define SDMA3_RLC0_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA3_RLC0_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA3_RLC0_RB_WPTR
#define SDMA3_RLC0_RB_WPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA3_RLC0_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA3_RLC0_RB_WPTR_HI
#define SDMA3_RLC0_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA3_RLC0_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA3_RLC0_RB_WPTR_POLL_CNTL
#define SDMA3_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
#define SDMA3_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
#define SDMA3_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
#define SDMA3_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
#define SDMA3_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
#define SDMA3_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
#define SDMA3_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
#define SDMA3_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
#define SDMA3_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
#define SDMA3_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
//SDMA3_RLC0_RB_RPTR_ADDR_HI
#define SDMA3_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
#define SDMA3_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
//SDMA3_RLC0_RB_RPTR_ADDR_LO
#define SDMA3_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
#define SDMA3_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
//SDMA3_RLC0_IB_CNTL
#define SDMA3_RLC0_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
#define SDMA3_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
#define SDMA3_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
#define SDMA3_RLC0_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
#define SDMA3_RLC0_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
#define SDMA3_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
#define SDMA3_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
#define SDMA3_RLC0_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
//SDMA3_RLC0_IB_RPTR
#define SDMA3_RLC0_IB_RPTR__OFFSET__SHIFT                                                                     0x2
#define SDMA3_RLC0_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
//SDMA3_RLC0_IB_OFFSET
#define SDMA3_RLC0_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
#define SDMA3_RLC0_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
//SDMA3_RLC0_IB_BASE_LO
#define SDMA3_RLC0_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
#define SDMA3_RLC0_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
//SDMA3_RLC0_IB_BASE_HI
#define SDMA3_RLC0_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA3_RLC0_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
//SDMA3_RLC0_IB_SIZE
#define SDMA3_RLC0_IB_SIZE__SIZE__SHIFT                                                                       0x0
#define SDMA3_RLC0_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
//SDMA3_RLC0_SKIP_CNTL
#define SDMA3_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
#define SDMA3_RLC0_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
//SDMA3_RLC0_CONTEXT_STATUS
#define SDMA3_RLC0_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
#define SDMA3_RLC0_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
#define SDMA3_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
#define SDMA3_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
#define SDMA3_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
#define SDMA3_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
#define SDMA3_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
#define SDMA3_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
#define SDMA3_RLC0_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
#define SDMA3_RLC0_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
#define SDMA3_RLC0_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
#define SDMA3_RLC0_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
#define SDMA3_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
#define SDMA3_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
#define SDMA3_RLC0_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
#define SDMA3_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
//SDMA3_RLC0_DOORBELL
#define SDMA3_RLC0_DOORBELL__ENABLE__SHIFT                                                                    0x1c
#define SDMA3_RLC0_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
#define SDMA3_RLC0_DOORBELL__ENABLE_MASK                                                                      0x10000000L
#define SDMA3_RLC0_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
//SDMA3_RLC0_STATUS
#define SDMA3_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
#define SDMA3_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
#define SDMA3_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
#define SDMA3_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
//SDMA3_RLC0_DOORBELL_LOG
#define SDMA3_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
#define SDMA3_RLC0_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
#define SDMA3_RLC0_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
#define SDMA3_RLC0_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
//SDMA3_RLC0_WATERMARK
#define SDMA3_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
#define SDMA3_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
#define SDMA3_RLC0_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
#define SDMA3_RLC0_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
//SDMA3_RLC0_DOORBELL_OFFSET
#define SDMA3_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
#define SDMA3_RLC0_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
//SDMA3_RLC0_CSA_ADDR_LO
#define SDMA3_RLC0_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
#define SDMA3_RLC0_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
//SDMA3_RLC0_CSA_ADDR_HI
#define SDMA3_RLC0_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
#define SDMA3_RLC0_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
//SDMA3_RLC0_IB_SUB_REMAIN
#define SDMA3_RLC0_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
#define SDMA3_RLC0_IB_SUB_REMAIN__SIZE_MASK                                                                   0x00003FFFL
//SDMA3_RLC0_PREEMPT
#define SDMA3_RLC0_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
#define SDMA3_RLC0_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
//SDMA3_RLC0_DUMMY_REG
#define SDMA3_RLC0_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
#define SDMA3_RLC0_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
//SDMA3_RLC0_RB_WPTR_POLL_ADDR_HI
#define SDMA3_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
#define SDMA3_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
//SDMA3_RLC0_RB_WPTR_POLL_ADDR_LO
#define SDMA3_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
#define SDMA3_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
//SDMA3_RLC0_RB_AQL_CNTL
#define SDMA3_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
#define SDMA3_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
#define SDMA3_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
#define SDMA3_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                  0x10
#define SDMA3_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT                                            0x11
#define SDMA3_RLC0_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT                                                         0x12
#define SDMA3_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
#define SDMA3_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
#define SDMA3_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
#define SDMA3_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                    0x00010000L
#define SDMA3_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK                                              0x00020000L
#define SDMA3_RLC0_RB_AQL_CNTL__OVERLAP_ENABLE_MASK                                                           0x00040000L
//SDMA3_RLC0_MINOR_PTR_UPDATE
#define SDMA3_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
#define SDMA3_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
//SDMA3_RLC0_MIDCMD_DATA0
#define SDMA3_RLC0_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
#define SDMA3_RLC0_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC0_MIDCMD_DATA1
#define SDMA3_RLC0_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
#define SDMA3_RLC0_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC0_MIDCMD_DATA2
#define SDMA3_RLC0_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
#define SDMA3_RLC0_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC0_MIDCMD_DATA3
#define SDMA3_RLC0_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
#define SDMA3_RLC0_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC0_MIDCMD_DATA4
#define SDMA3_RLC0_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
#define SDMA3_RLC0_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC0_MIDCMD_DATA5
#define SDMA3_RLC0_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
#define SDMA3_RLC0_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC0_MIDCMD_DATA6
#define SDMA3_RLC0_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
#define SDMA3_RLC0_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC0_MIDCMD_DATA7
#define SDMA3_RLC0_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
#define SDMA3_RLC0_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC0_MIDCMD_DATA8
#define SDMA3_RLC0_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
#define SDMA3_RLC0_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC0_MIDCMD_DATA9
#define SDMA3_RLC0_MIDCMD_DATA9__DATA9__SHIFT                                                                 0x0
#define SDMA3_RLC0_MIDCMD_DATA9__DATA9_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC0_MIDCMD_DATA10
#define SDMA3_RLC0_MIDCMD_DATA10__DATA10__SHIFT                                                               0x0
#define SDMA3_RLC0_MIDCMD_DATA10__DATA10_MASK                                                                 0xFFFFFFFFL
//SDMA3_RLC0_MIDCMD_CNTL
#define SDMA3_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
#define SDMA3_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
#define SDMA3_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
#define SDMA3_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
#define SDMA3_RLC0_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
#define SDMA3_RLC0_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
#define SDMA3_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
#define SDMA3_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
//SDMA3_RLC1_RB_CNTL
#define SDMA3_RLC1_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
#define SDMA3_RLC1_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
#define SDMA3_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
#define SDMA3_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
#define SDMA3_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
#define SDMA3_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
#define SDMA3_RLC1_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
#define SDMA3_RLC1_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
#define SDMA3_RLC1_RB_CNTL__RPTR_WB_IDLE__SHIFT                                                               0x1f
#define SDMA3_RLC1_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
#define SDMA3_RLC1_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
#define SDMA3_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
#define SDMA3_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
#define SDMA3_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
#define SDMA3_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
#define SDMA3_RLC1_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
#define SDMA3_RLC1_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
#define SDMA3_RLC1_RB_CNTL__RPTR_WB_IDLE_MASK                                                                 0x80000000L
//SDMA3_RLC1_RB_BASE
#define SDMA3_RLC1_RB_BASE__ADDR__SHIFT                                                                       0x0
#define SDMA3_RLC1_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
//SDMA3_RLC1_RB_BASE_HI
#define SDMA3_RLC1_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA3_RLC1_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
//SDMA3_RLC1_RB_RPTR
#define SDMA3_RLC1_RB_RPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA3_RLC1_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA3_RLC1_RB_RPTR_HI
#define SDMA3_RLC1_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA3_RLC1_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA3_RLC1_RB_WPTR
#define SDMA3_RLC1_RB_WPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA3_RLC1_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA3_RLC1_RB_WPTR_HI
#define SDMA3_RLC1_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA3_RLC1_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA3_RLC1_RB_WPTR_POLL_CNTL
#define SDMA3_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
#define SDMA3_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
#define SDMA3_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
#define SDMA3_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
#define SDMA3_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
#define SDMA3_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
#define SDMA3_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
#define SDMA3_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
#define SDMA3_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
#define SDMA3_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
//SDMA3_RLC1_RB_RPTR_ADDR_HI
#define SDMA3_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
#define SDMA3_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
//SDMA3_RLC1_RB_RPTR_ADDR_LO
#define SDMA3_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
#define SDMA3_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
//SDMA3_RLC1_IB_CNTL
#define SDMA3_RLC1_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
#define SDMA3_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
#define SDMA3_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
#define SDMA3_RLC1_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
#define SDMA3_RLC1_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
#define SDMA3_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
#define SDMA3_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
#define SDMA3_RLC1_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
//SDMA3_RLC1_IB_RPTR
#define SDMA3_RLC1_IB_RPTR__OFFSET__SHIFT                                                                     0x2
#define SDMA3_RLC1_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
//SDMA3_RLC1_IB_OFFSET
#define SDMA3_RLC1_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
#define SDMA3_RLC1_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
//SDMA3_RLC1_IB_BASE_LO
#define SDMA3_RLC1_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
#define SDMA3_RLC1_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
//SDMA3_RLC1_IB_BASE_HI
#define SDMA3_RLC1_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA3_RLC1_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
//SDMA3_RLC1_IB_SIZE
#define SDMA3_RLC1_IB_SIZE__SIZE__SHIFT                                                                       0x0
#define SDMA3_RLC1_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
//SDMA3_RLC1_SKIP_CNTL
#define SDMA3_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
#define SDMA3_RLC1_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
//SDMA3_RLC1_CONTEXT_STATUS
#define SDMA3_RLC1_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
#define SDMA3_RLC1_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
#define SDMA3_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
#define SDMA3_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
#define SDMA3_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
#define SDMA3_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
#define SDMA3_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
#define SDMA3_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
#define SDMA3_RLC1_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
#define SDMA3_RLC1_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
#define SDMA3_RLC1_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
#define SDMA3_RLC1_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
#define SDMA3_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
#define SDMA3_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
#define SDMA3_RLC1_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
#define SDMA3_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
//SDMA3_RLC1_DOORBELL
#define SDMA3_RLC1_DOORBELL__ENABLE__SHIFT                                                                    0x1c
#define SDMA3_RLC1_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
#define SDMA3_RLC1_DOORBELL__ENABLE_MASK                                                                      0x10000000L
#define SDMA3_RLC1_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
//SDMA3_RLC1_STATUS
#define SDMA3_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
#define SDMA3_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
#define SDMA3_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
#define SDMA3_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
//SDMA3_RLC1_DOORBELL_LOG
#define SDMA3_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
#define SDMA3_RLC1_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
#define SDMA3_RLC1_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
#define SDMA3_RLC1_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
//SDMA3_RLC1_WATERMARK
#define SDMA3_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
#define SDMA3_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
#define SDMA3_RLC1_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
#define SDMA3_RLC1_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
//SDMA3_RLC1_DOORBELL_OFFSET
#define SDMA3_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
#define SDMA3_RLC1_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
//SDMA3_RLC1_CSA_ADDR_LO
#define SDMA3_RLC1_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
#define SDMA3_RLC1_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
//SDMA3_RLC1_CSA_ADDR_HI
#define SDMA3_RLC1_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
#define SDMA3_RLC1_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
//SDMA3_RLC1_IB_SUB_REMAIN
#define SDMA3_RLC1_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
#define SDMA3_RLC1_IB_SUB_REMAIN__SIZE_MASK                                                                   0x00003FFFL
//SDMA3_RLC1_PREEMPT
#define SDMA3_RLC1_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
#define SDMA3_RLC1_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
//SDMA3_RLC1_DUMMY_REG
#define SDMA3_RLC1_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
#define SDMA3_RLC1_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
//SDMA3_RLC1_RB_WPTR_POLL_ADDR_HI
#define SDMA3_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
#define SDMA3_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
//SDMA3_RLC1_RB_WPTR_POLL_ADDR_LO
#define SDMA3_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
#define SDMA3_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
//SDMA3_RLC1_RB_AQL_CNTL
#define SDMA3_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
#define SDMA3_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
#define SDMA3_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
#define SDMA3_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                  0x10
#define SDMA3_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT                                            0x11
#define SDMA3_RLC1_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT                                                         0x12
#define SDMA3_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
#define SDMA3_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
#define SDMA3_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
#define SDMA3_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                    0x00010000L
#define SDMA3_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK                                              0x00020000L
#define SDMA3_RLC1_RB_AQL_CNTL__OVERLAP_ENABLE_MASK                                                           0x00040000L
//SDMA3_RLC1_MINOR_PTR_UPDATE
#define SDMA3_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
#define SDMA3_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
//SDMA3_RLC1_MIDCMD_DATA0
#define SDMA3_RLC1_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
#define SDMA3_RLC1_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC1_MIDCMD_DATA1
#define SDMA3_RLC1_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
#define SDMA3_RLC1_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC1_MIDCMD_DATA2
#define SDMA3_RLC1_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
#define SDMA3_RLC1_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC1_MIDCMD_DATA3
#define SDMA3_RLC1_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
#define SDMA3_RLC1_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC1_MIDCMD_DATA4
#define SDMA3_RLC1_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
#define SDMA3_RLC1_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC1_MIDCMD_DATA5
#define SDMA3_RLC1_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
#define SDMA3_RLC1_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC1_MIDCMD_DATA6
#define SDMA3_RLC1_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
#define SDMA3_RLC1_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC1_MIDCMD_DATA7
#define SDMA3_RLC1_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
#define SDMA3_RLC1_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC1_MIDCMD_DATA8
#define SDMA3_RLC1_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
#define SDMA3_RLC1_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC1_MIDCMD_DATA9
#define SDMA3_RLC1_MIDCMD_DATA9__DATA9__SHIFT                                                                 0x0
#define SDMA3_RLC1_MIDCMD_DATA9__DATA9_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC1_MIDCMD_DATA10
#define SDMA3_RLC1_MIDCMD_DATA10__DATA10__SHIFT                                                               0x0
#define SDMA3_RLC1_MIDCMD_DATA10__DATA10_MASK                                                                 0xFFFFFFFFL
//SDMA3_RLC1_MIDCMD_CNTL
#define SDMA3_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
#define SDMA3_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
#define SDMA3_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
#define SDMA3_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
#define SDMA3_RLC1_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
#define SDMA3_RLC1_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
#define SDMA3_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
#define SDMA3_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
//SDMA3_RLC2_RB_CNTL
#define SDMA3_RLC2_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
#define SDMA3_RLC2_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
#define SDMA3_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
#define SDMA3_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
#define SDMA3_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
#define SDMA3_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
#define SDMA3_RLC2_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
#define SDMA3_RLC2_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
#define SDMA3_RLC2_RB_CNTL__RPTR_WB_IDLE__SHIFT                                                               0x1f
#define SDMA3_RLC2_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
#define SDMA3_RLC2_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
#define SDMA3_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
#define SDMA3_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
#define SDMA3_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
#define SDMA3_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
#define SDMA3_RLC2_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
#define SDMA3_RLC2_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
#define SDMA3_RLC2_RB_CNTL__RPTR_WB_IDLE_MASK                                                                 0x80000000L
//SDMA3_RLC2_RB_BASE
#define SDMA3_RLC2_RB_BASE__ADDR__SHIFT                                                                       0x0
#define SDMA3_RLC2_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
//SDMA3_RLC2_RB_BASE_HI
#define SDMA3_RLC2_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA3_RLC2_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
//SDMA3_RLC2_RB_RPTR
#define SDMA3_RLC2_RB_RPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA3_RLC2_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA3_RLC2_RB_RPTR_HI
#define SDMA3_RLC2_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA3_RLC2_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA3_RLC2_RB_WPTR
#define SDMA3_RLC2_RB_WPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA3_RLC2_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA3_RLC2_RB_WPTR_HI
#define SDMA3_RLC2_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA3_RLC2_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA3_RLC2_RB_WPTR_POLL_CNTL
#define SDMA3_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
#define SDMA3_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
#define SDMA3_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
#define SDMA3_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
#define SDMA3_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
#define SDMA3_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
#define SDMA3_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
#define SDMA3_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
#define SDMA3_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
#define SDMA3_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
//SDMA3_RLC2_RB_RPTR_ADDR_HI
#define SDMA3_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
#define SDMA3_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
//SDMA3_RLC2_RB_RPTR_ADDR_LO
#define SDMA3_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
#define SDMA3_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
//SDMA3_RLC2_IB_CNTL
#define SDMA3_RLC2_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
#define SDMA3_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
#define SDMA3_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
#define SDMA3_RLC2_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
#define SDMA3_RLC2_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
#define SDMA3_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
#define SDMA3_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
#define SDMA3_RLC2_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
//SDMA3_RLC2_IB_RPTR
#define SDMA3_RLC2_IB_RPTR__OFFSET__SHIFT                                                                     0x2
#define SDMA3_RLC2_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
//SDMA3_RLC2_IB_OFFSET
#define SDMA3_RLC2_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
#define SDMA3_RLC2_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
//SDMA3_RLC2_IB_BASE_LO
#define SDMA3_RLC2_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
#define SDMA3_RLC2_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
//SDMA3_RLC2_IB_BASE_HI
#define SDMA3_RLC2_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA3_RLC2_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
//SDMA3_RLC2_IB_SIZE
#define SDMA3_RLC2_IB_SIZE__SIZE__SHIFT                                                                       0x0
#define SDMA3_RLC2_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
//SDMA3_RLC2_SKIP_CNTL
#define SDMA3_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
#define SDMA3_RLC2_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
//SDMA3_RLC2_CONTEXT_STATUS
#define SDMA3_RLC2_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
#define SDMA3_RLC2_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
#define SDMA3_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
#define SDMA3_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
#define SDMA3_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
#define SDMA3_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
#define SDMA3_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
#define SDMA3_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
#define SDMA3_RLC2_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
#define SDMA3_RLC2_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
#define SDMA3_RLC2_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
#define SDMA3_RLC2_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
#define SDMA3_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
#define SDMA3_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
#define SDMA3_RLC2_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
#define SDMA3_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
//SDMA3_RLC2_DOORBELL
#define SDMA3_RLC2_DOORBELL__ENABLE__SHIFT                                                                    0x1c
#define SDMA3_RLC2_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
#define SDMA3_RLC2_DOORBELL__ENABLE_MASK                                                                      0x10000000L
#define SDMA3_RLC2_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
//SDMA3_RLC2_STATUS
#define SDMA3_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
#define SDMA3_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
#define SDMA3_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
#define SDMA3_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
//SDMA3_RLC2_DOORBELL_LOG
#define SDMA3_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
#define SDMA3_RLC2_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
#define SDMA3_RLC2_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
#define SDMA3_RLC2_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
//SDMA3_RLC2_WATERMARK
#define SDMA3_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
#define SDMA3_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
#define SDMA3_RLC2_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
#define SDMA3_RLC2_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
//SDMA3_RLC2_DOORBELL_OFFSET
#define SDMA3_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
#define SDMA3_RLC2_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
//SDMA3_RLC2_CSA_ADDR_LO
#define SDMA3_RLC2_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
#define SDMA3_RLC2_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
//SDMA3_RLC2_CSA_ADDR_HI
#define SDMA3_RLC2_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
#define SDMA3_RLC2_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
//SDMA3_RLC2_IB_SUB_REMAIN
#define SDMA3_RLC2_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
#define SDMA3_RLC2_IB_SUB_REMAIN__SIZE_MASK                                                                   0x00003FFFL
//SDMA3_RLC2_PREEMPT
#define SDMA3_RLC2_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
#define SDMA3_RLC2_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
//SDMA3_RLC2_DUMMY_REG
#define SDMA3_RLC2_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
#define SDMA3_RLC2_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
//SDMA3_RLC2_RB_WPTR_POLL_ADDR_HI
#define SDMA3_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
#define SDMA3_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
//SDMA3_RLC2_RB_WPTR_POLL_ADDR_LO
#define SDMA3_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
#define SDMA3_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
//SDMA3_RLC2_RB_AQL_CNTL
#define SDMA3_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
#define SDMA3_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
#define SDMA3_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
#define SDMA3_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                  0x10
#define SDMA3_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT                                            0x11
#define SDMA3_RLC2_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT                                                         0x12
#define SDMA3_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
#define SDMA3_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
#define SDMA3_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
#define SDMA3_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                    0x00010000L
#define SDMA3_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK                                              0x00020000L
#define SDMA3_RLC2_RB_AQL_CNTL__OVERLAP_ENABLE_MASK                                                           0x00040000L
//SDMA3_RLC2_MINOR_PTR_UPDATE
#define SDMA3_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
#define SDMA3_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
//SDMA3_RLC2_MIDCMD_DATA0
#define SDMA3_RLC2_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
#define SDMA3_RLC2_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC2_MIDCMD_DATA1
#define SDMA3_RLC2_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
#define SDMA3_RLC2_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC2_MIDCMD_DATA2
#define SDMA3_RLC2_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
#define SDMA3_RLC2_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC2_MIDCMD_DATA3
#define SDMA3_RLC2_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
#define SDMA3_RLC2_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC2_MIDCMD_DATA4
#define SDMA3_RLC2_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
#define SDMA3_RLC2_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC2_MIDCMD_DATA5
#define SDMA3_RLC2_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
#define SDMA3_RLC2_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC2_MIDCMD_DATA6
#define SDMA3_RLC2_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
#define SDMA3_RLC2_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC2_MIDCMD_DATA7
#define SDMA3_RLC2_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
#define SDMA3_RLC2_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC2_MIDCMD_DATA8
#define SDMA3_RLC2_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
#define SDMA3_RLC2_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC2_MIDCMD_DATA9
#define SDMA3_RLC2_MIDCMD_DATA9__DATA9__SHIFT                                                                 0x0
#define SDMA3_RLC2_MIDCMD_DATA9__DATA9_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC2_MIDCMD_DATA10
#define SDMA3_RLC2_MIDCMD_DATA10__DATA10__SHIFT                                                               0x0
#define SDMA3_RLC2_MIDCMD_DATA10__DATA10_MASK                                                                 0xFFFFFFFFL
//SDMA3_RLC2_MIDCMD_CNTL
#define SDMA3_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
#define SDMA3_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
#define SDMA3_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
#define SDMA3_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
#define SDMA3_RLC2_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
#define SDMA3_RLC2_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
#define SDMA3_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
#define SDMA3_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
//SDMA3_RLC3_RB_CNTL
#define SDMA3_RLC3_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
#define SDMA3_RLC3_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
#define SDMA3_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
#define SDMA3_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
#define SDMA3_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
#define SDMA3_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
#define SDMA3_RLC3_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
#define SDMA3_RLC3_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
#define SDMA3_RLC3_RB_CNTL__RPTR_WB_IDLE__SHIFT                                                               0x1f
#define SDMA3_RLC3_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
#define SDMA3_RLC3_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
#define SDMA3_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
#define SDMA3_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
#define SDMA3_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
#define SDMA3_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
#define SDMA3_RLC3_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
#define SDMA3_RLC3_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
#define SDMA3_RLC3_RB_CNTL__RPTR_WB_IDLE_MASK                                                                 0x80000000L
//SDMA3_RLC3_RB_BASE
#define SDMA3_RLC3_RB_BASE__ADDR__SHIFT                                                                       0x0
#define SDMA3_RLC3_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
//SDMA3_RLC3_RB_BASE_HI
#define SDMA3_RLC3_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA3_RLC3_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
//SDMA3_RLC3_RB_RPTR
#define SDMA3_RLC3_RB_RPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA3_RLC3_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA3_RLC3_RB_RPTR_HI
#define SDMA3_RLC3_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA3_RLC3_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA3_RLC3_RB_WPTR
#define SDMA3_RLC3_RB_WPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA3_RLC3_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA3_RLC3_RB_WPTR_HI
#define SDMA3_RLC3_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA3_RLC3_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA3_RLC3_RB_WPTR_POLL_CNTL
#define SDMA3_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
#define SDMA3_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
#define SDMA3_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
#define SDMA3_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
#define SDMA3_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
#define SDMA3_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
#define SDMA3_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
#define SDMA3_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
#define SDMA3_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
#define SDMA3_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
//SDMA3_RLC3_RB_RPTR_ADDR_HI
#define SDMA3_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
#define SDMA3_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
//SDMA3_RLC3_RB_RPTR_ADDR_LO
#define SDMA3_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
#define SDMA3_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
//SDMA3_RLC3_IB_CNTL
#define SDMA3_RLC3_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
#define SDMA3_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
#define SDMA3_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
#define SDMA3_RLC3_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
#define SDMA3_RLC3_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
#define SDMA3_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
#define SDMA3_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
#define SDMA3_RLC3_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
//SDMA3_RLC3_IB_RPTR
#define SDMA3_RLC3_IB_RPTR__OFFSET__SHIFT                                                                     0x2
#define SDMA3_RLC3_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
//SDMA3_RLC3_IB_OFFSET
#define SDMA3_RLC3_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
#define SDMA3_RLC3_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
//SDMA3_RLC3_IB_BASE_LO
#define SDMA3_RLC3_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
#define SDMA3_RLC3_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
//SDMA3_RLC3_IB_BASE_HI
#define SDMA3_RLC3_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA3_RLC3_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
//SDMA3_RLC3_IB_SIZE
#define SDMA3_RLC3_IB_SIZE__SIZE__SHIFT                                                                       0x0
#define SDMA3_RLC3_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
//SDMA3_RLC3_SKIP_CNTL
#define SDMA3_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
#define SDMA3_RLC3_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
//SDMA3_RLC3_CONTEXT_STATUS
#define SDMA3_RLC3_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
#define SDMA3_RLC3_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
#define SDMA3_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
#define SDMA3_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
#define SDMA3_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
#define SDMA3_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
#define SDMA3_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
#define SDMA3_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
#define SDMA3_RLC3_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
#define SDMA3_RLC3_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
#define SDMA3_RLC3_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
#define SDMA3_RLC3_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
#define SDMA3_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
#define SDMA3_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
#define SDMA3_RLC3_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
#define SDMA3_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
//SDMA3_RLC3_DOORBELL
#define SDMA3_RLC3_DOORBELL__ENABLE__SHIFT                                                                    0x1c
#define SDMA3_RLC3_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
#define SDMA3_RLC3_DOORBELL__ENABLE_MASK                                                                      0x10000000L
#define SDMA3_RLC3_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
//SDMA3_RLC3_STATUS
#define SDMA3_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
#define SDMA3_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
#define SDMA3_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
#define SDMA3_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
//SDMA3_RLC3_DOORBELL_LOG
#define SDMA3_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
#define SDMA3_RLC3_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
#define SDMA3_RLC3_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
#define SDMA3_RLC3_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
//SDMA3_RLC3_WATERMARK
#define SDMA3_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
#define SDMA3_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
#define SDMA3_RLC3_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
#define SDMA3_RLC3_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
//SDMA3_RLC3_DOORBELL_OFFSET
#define SDMA3_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
#define SDMA3_RLC3_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
//SDMA3_RLC3_CSA_ADDR_LO
#define SDMA3_RLC3_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
#define SDMA3_RLC3_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
//SDMA3_RLC3_CSA_ADDR_HI
#define SDMA3_RLC3_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
#define SDMA3_RLC3_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
//SDMA3_RLC3_IB_SUB_REMAIN
#define SDMA3_RLC3_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
#define SDMA3_RLC3_IB_SUB_REMAIN__SIZE_MASK                                                                   0x00003FFFL
//SDMA3_RLC3_PREEMPT
#define SDMA3_RLC3_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
#define SDMA3_RLC3_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
//SDMA3_RLC3_DUMMY_REG
#define SDMA3_RLC3_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
#define SDMA3_RLC3_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
//SDMA3_RLC3_RB_WPTR_POLL_ADDR_HI
#define SDMA3_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
#define SDMA3_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
//SDMA3_RLC3_RB_WPTR_POLL_ADDR_LO
#define SDMA3_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
#define SDMA3_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
//SDMA3_RLC3_RB_AQL_CNTL
#define SDMA3_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
#define SDMA3_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
#define SDMA3_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
#define SDMA3_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                  0x10
#define SDMA3_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT                                            0x11
#define SDMA3_RLC3_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT                                                         0x12
#define SDMA3_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
#define SDMA3_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
#define SDMA3_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
#define SDMA3_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                    0x00010000L
#define SDMA3_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK                                              0x00020000L
#define SDMA3_RLC3_RB_AQL_CNTL__OVERLAP_ENABLE_MASK                                                           0x00040000L
//SDMA3_RLC3_MINOR_PTR_UPDATE
#define SDMA3_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
#define SDMA3_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
//SDMA3_RLC3_MIDCMD_DATA0
#define SDMA3_RLC3_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
#define SDMA3_RLC3_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC3_MIDCMD_DATA1
#define SDMA3_RLC3_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
#define SDMA3_RLC3_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC3_MIDCMD_DATA2
#define SDMA3_RLC3_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
#define SDMA3_RLC3_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC3_MIDCMD_DATA3
#define SDMA3_RLC3_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
#define SDMA3_RLC3_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC3_MIDCMD_DATA4
#define SDMA3_RLC3_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
#define SDMA3_RLC3_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC3_MIDCMD_DATA5
#define SDMA3_RLC3_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
#define SDMA3_RLC3_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC3_MIDCMD_DATA6
#define SDMA3_RLC3_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
#define SDMA3_RLC3_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC3_MIDCMD_DATA7
#define SDMA3_RLC3_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
#define SDMA3_RLC3_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC3_MIDCMD_DATA8
#define SDMA3_RLC3_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
#define SDMA3_RLC3_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC3_MIDCMD_DATA9
#define SDMA3_RLC3_MIDCMD_DATA9__DATA9__SHIFT                                                                 0x0
#define SDMA3_RLC3_MIDCMD_DATA9__DATA9_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC3_MIDCMD_DATA10
#define SDMA3_RLC3_MIDCMD_DATA10__DATA10__SHIFT                                                               0x0
#define SDMA3_RLC3_MIDCMD_DATA10__DATA10_MASK                                                                 0xFFFFFFFFL
//SDMA3_RLC3_MIDCMD_CNTL
#define SDMA3_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
#define SDMA3_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
#define SDMA3_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
#define SDMA3_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
#define SDMA3_RLC3_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
#define SDMA3_RLC3_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
#define SDMA3_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
#define SDMA3_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
//SDMA3_RLC4_RB_CNTL
#define SDMA3_RLC4_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
#define SDMA3_RLC4_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
#define SDMA3_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
#define SDMA3_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
#define SDMA3_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
#define SDMA3_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
#define SDMA3_RLC4_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
#define SDMA3_RLC4_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
#define SDMA3_RLC4_RB_CNTL__RPTR_WB_IDLE__SHIFT                                                               0x1f
#define SDMA3_RLC4_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
#define SDMA3_RLC4_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
#define SDMA3_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
#define SDMA3_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
#define SDMA3_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
#define SDMA3_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
#define SDMA3_RLC4_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
#define SDMA3_RLC4_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
#define SDMA3_RLC4_RB_CNTL__RPTR_WB_IDLE_MASK                                                                 0x80000000L
//SDMA3_RLC4_RB_BASE
#define SDMA3_RLC4_RB_BASE__ADDR__SHIFT                                                                       0x0
#define SDMA3_RLC4_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
//SDMA3_RLC4_RB_BASE_HI
#define SDMA3_RLC4_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA3_RLC4_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
//SDMA3_RLC4_RB_RPTR
#define SDMA3_RLC4_RB_RPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA3_RLC4_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA3_RLC4_RB_RPTR_HI
#define SDMA3_RLC4_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA3_RLC4_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA3_RLC4_RB_WPTR
#define SDMA3_RLC4_RB_WPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA3_RLC4_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA3_RLC4_RB_WPTR_HI
#define SDMA3_RLC4_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA3_RLC4_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA3_RLC4_RB_WPTR_POLL_CNTL
#define SDMA3_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
#define SDMA3_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
#define SDMA3_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
#define SDMA3_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
#define SDMA3_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
#define SDMA3_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
#define SDMA3_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
#define SDMA3_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
#define SDMA3_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
#define SDMA3_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
//SDMA3_RLC4_RB_RPTR_ADDR_HI
#define SDMA3_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
#define SDMA3_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
//SDMA3_RLC4_RB_RPTR_ADDR_LO
#define SDMA3_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
#define SDMA3_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
//SDMA3_RLC4_IB_CNTL
#define SDMA3_RLC4_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
#define SDMA3_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
#define SDMA3_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
#define SDMA3_RLC4_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
#define SDMA3_RLC4_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
#define SDMA3_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
#define SDMA3_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
#define SDMA3_RLC4_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
//SDMA3_RLC4_IB_RPTR
#define SDMA3_RLC4_IB_RPTR__OFFSET__SHIFT                                                                     0x2
#define SDMA3_RLC4_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
//SDMA3_RLC4_IB_OFFSET
#define SDMA3_RLC4_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
#define SDMA3_RLC4_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
//SDMA3_RLC4_IB_BASE_LO
#define SDMA3_RLC4_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
#define SDMA3_RLC4_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
//SDMA3_RLC4_IB_BASE_HI
#define SDMA3_RLC4_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA3_RLC4_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
//SDMA3_RLC4_IB_SIZE
#define SDMA3_RLC4_IB_SIZE__SIZE__SHIFT                                                                       0x0
#define SDMA3_RLC4_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
//SDMA3_RLC4_SKIP_CNTL
#define SDMA3_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
#define SDMA3_RLC4_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
//SDMA3_RLC4_CONTEXT_STATUS
#define SDMA3_RLC4_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
#define SDMA3_RLC4_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
#define SDMA3_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
#define SDMA3_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
#define SDMA3_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
#define SDMA3_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
#define SDMA3_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
#define SDMA3_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
#define SDMA3_RLC4_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
#define SDMA3_RLC4_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
#define SDMA3_RLC4_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
#define SDMA3_RLC4_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
#define SDMA3_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
#define SDMA3_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
#define SDMA3_RLC4_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
#define SDMA3_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
//SDMA3_RLC4_DOORBELL
#define SDMA3_RLC4_DOORBELL__ENABLE__SHIFT                                                                    0x1c
#define SDMA3_RLC4_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
#define SDMA3_RLC4_DOORBELL__ENABLE_MASK                                                                      0x10000000L
#define SDMA3_RLC4_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
//SDMA3_RLC4_STATUS
#define SDMA3_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
#define SDMA3_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
#define SDMA3_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
#define SDMA3_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
//SDMA3_RLC4_DOORBELL_LOG
#define SDMA3_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
#define SDMA3_RLC4_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
#define SDMA3_RLC4_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
#define SDMA3_RLC4_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
//SDMA3_RLC4_WATERMARK
#define SDMA3_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
#define SDMA3_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
#define SDMA3_RLC4_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
#define SDMA3_RLC4_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
//SDMA3_RLC4_DOORBELL_OFFSET
#define SDMA3_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
#define SDMA3_RLC4_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
//SDMA3_RLC4_CSA_ADDR_LO
#define SDMA3_RLC4_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
#define SDMA3_RLC4_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
//SDMA3_RLC4_CSA_ADDR_HI
#define SDMA3_RLC4_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
#define SDMA3_RLC4_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
//SDMA3_RLC4_IB_SUB_REMAIN
#define SDMA3_RLC4_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
#define SDMA3_RLC4_IB_SUB_REMAIN__SIZE_MASK                                                                   0x00003FFFL
//SDMA3_RLC4_PREEMPT
#define SDMA3_RLC4_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
#define SDMA3_RLC4_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
//SDMA3_RLC4_DUMMY_REG
#define SDMA3_RLC4_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
#define SDMA3_RLC4_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
//SDMA3_RLC4_RB_WPTR_POLL_ADDR_HI
#define SDMA3_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
#define SDMA3_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
//SDMA3_RLC4_RB_WPTR_POLL_ADDR_LO
#define SDMA3_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
#define SDMA3_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
//SDMA3_RLC4_RB_AQL_CNTL
#define SDMA3_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
#define SDMA3_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
#define SDMA3_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
#define SDMA3_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                  0x10
#define SDMA3_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT                                            0x11
#define SDMA3_RLC4_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT                                                         0x12
#define SDMA3_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
#define SDMA3_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
#define SDMA3_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
#define SDMA3_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                    0x00010000L
#define SDMA3_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK                                              0x00020000L
#define SDMA3_RLC4_RB_AQL_CNTL__OVERLAP_ENABLE_MASK                                                           0x00040000L
//SDMA3_RLC4_MINOR_PTR_UPDATE
#define SDMA3_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
#define SDMA3_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
//SDMA3_RLC4_MIDCMD_DATA0
#define SDMA3_RLC4_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
#define SDMA3_RLC4_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC4_MIDCMD_DATA1
#define SDMA3_RLC4_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
#define SDMA3_RLC4_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC4_MIDCMD_DATA2
#define SDMA3_RLC4_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
#define SDMA3_RLC4_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC4_MIDCMD_DATA3
#define SDMA3_RLC4_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
#define SDMA3_RLC4_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC4_MIDCMD_DATA4
#define SDMA3_RLC4_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
#define SDMA3_RLC4_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC4_MIDCMD_DATA5
#define SDMA3_RLC4_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
#define SDMA3_RLC4_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC4_MIDCMD_DATA6
#define SDMA3_RLC4_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
#define SDMA3_RLC4_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC4_MIDCMD_DATA7
#define SDMA3_RLC4_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
#define SDMA3_RLC4_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC4_MIDCMD_DATA8
#define SDMA3_RLC4_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
#define SDMA3_RLC4_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC4_MIDCMD_DATA9
#define SDMA3_RLC4_MIDCMD_DATA9__DATA9__SHIFT                                                                 0x0
#define SDMA3_RLC4_MIDCMD_DATA9__DATA9_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC4_MIDCMD_DATA10
#define SDMA3_RLC4_MIDCMD_DATA10__DATA10__SHIFT                                                               0x0
#define SDMA3_RLC4_MIDCMD_DATA10__DATA10_MASK                                                                 0xFFFFFFFFL
//SDMA3_RLC4_MIDCMD_CNTL
#define SDMA3_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
#define SDMA3_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
#define SDMA3_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
#define SDMA3_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
#define SDMA3_RLC4_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
#define SDMA3_RLC4_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
#define SDMA3_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
#define SDMA3_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
//SDMA3_RLC5_RB_CNTL
#define SDMA3_RLC5_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
#define SDMA3_RLC5_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
#define SDMA3_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
#define SDMA3_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
#define SDMA3_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
#define SDMA3_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
#define SDMA3_RLC5_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
#define SDMA3_RLC5_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
#define SDMA3_RLC5_RB_CNTL__RPTR_WB_IDLE__SHIFT                                                               0x1f
#define SDMA3_RLC5_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
#define SDMA3_RLC5_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
#define SDMA3_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
#define SDMA3_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
#define SDMA3_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
#define SDMA3_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
#define SDMA3_RLC5_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
#define SDMA3_RLC5_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
#define SDMA3_RLC5_RB_CNTL__RPTR_WB_IDLE_MASK                                                                 0x80000000L
//SDMA3_RLC5_RB_BASE
#define SDMA3_RLC5_RB_BASE__ADDR__SHIFT                                                                       0x0
#define SDMA3_RLC5_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
//SDMA3_RLC5_RB_BASE_HI
#define SDMA3_RLC5_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA3_RLC5_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
//SDMA3_RLC5_RB_RPTR
#define SDMA3_RLC5_RB_RPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA3_RLC5_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA3_RLC5_RB_RPTR_HI
#define SDMA3_RLC5_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA3_RLC5_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA3_RLC5_RB_WPTR
#define SDMA3_RLC5_RB_WPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA3_RLC5_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA3_RLC5_RB_WPTR_HI
#define SDMA3_RLC5_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA3_RLC5_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA3_RLC5_RB_WPTR_POLL_CNTL
#define SDMA3_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
#define SDMA3_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
#define SDMA3_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
#define SDMA3_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
#define SDMA3_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
#define SDMA3_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
#define SDMA3_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
#define SDMA3_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
#define SDMA3_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
#define SDMA3_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
//SDMA3_RLC5_RB_RPTR_ADDR_HI
#define SDMA3_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
#define SDMA3_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
//SDMA3_RLC5_RB_RPTR_ADDR_LO
#define SDMA3_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
#define SDMA3_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
//SDMA3_RLC5_IB_CNTL
#define SDMA3_RLC5_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
#define SDMA3_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
#define SDMA3_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
#define SDMA3_RLC5_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
#define SDMA3_RLC5_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
#define SDMA3_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
#define SDMA3_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
#define SDMA3_RLC5_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
//SDMA3_RLC5_IB_RPTR
#define SDMA3_RLC5_IB_RPTR__OFFSET__SHIFT                                                                     0x2
#define SDMA3_RLC5_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
//SDMA3_RLC5_IB_OFFSET
#define SDMA3_RLC5_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
#define SDMA3_RLC5_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
//SDMA3_RLC5_IB_BASE_LO
#define SDMA3_RLC5_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
#define SDMA3_RLC5_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
//SDMA3_RLC5_IB_BASE_HI
#define SDMA3_RLC5_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA3_RLC5_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
//SDMA3_RLC5_IB_SIZE
#define SDMA3_RLC5_IB_SIZE__SIZE__SHIFT                                                                       0x0
#define SDMA3_RLC5_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
//SDMA3_RLC5_SKIP_CNTL
#define SDMA3_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
#define SDMA3_RLC5_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
//SDMA3_RLC5_CONTEXT_STATUS
#define SDMA3_RLC5_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
#define SDMA3_RLC5_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
#define SDMA3_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
#define SDMA3_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
#define SDMA3_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
#define SDMA3_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
#define SDMA3_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
#define SDMA3_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
#define SDMA3_RLC5_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
#define SDMA3_RLC5_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
#define SDMA3_RLC5_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
#define SDMA3_RLC5_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
#define SDMA3_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
#define SDMA3_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
#define SDMA3_RLC5_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
#define SDMA3_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
//SDMA3_RLC5_DOORBELL
#define SDMA3_RLC5_DOORBELL__ENABLE__SHIFT                                                                    0x1c
#define SDMA3_RLC5_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
#define SDMA3_RLC5_DOORBELL__ENABLE_MASK                                                                      0x10000000L
#define SDMA3_RLC5_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
//SDMA3_RLC5_STATUS
#define SDMA3_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
#define SDMA3_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
#define SDMA3_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
#define SDMA3_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
//SDMA3_RLC5_DOORBELL_LOG
#define SDMA3_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
#define SDMA3_RLC5_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
#define SDMA3_RLC5_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
#define SDMA3_RLC5_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
//SDMA3_RLC5_WATERMARK
#define SDMA3_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
#define SDMA3_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
#define SDMA3_RLC5_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
#define SDMA3_RLC5_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
//SDMA3_RLC5_DOORBELL_OFFSET
#define SDMA3_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
#define SDMA3_RLC5_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
//SDMA3_RLC5_CSA_ADDR_LO
#define SDMA3_RLC5_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
#define SDMA3_RLC5_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
//SDMA3_RLC5_CSA_ADDR_HI
#define SDMA3_RLC5_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
#define SDMA3_RLC5_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
//SDMA3_RLC5_IB_SUB_REMAIN
#define SDMA3_RLC5_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
#define SDMA3_RLC5_IB_SUB_REMAIN__SIZE_MASK                                                                   0x00003FFFL
//SDMA3_RLC5_PREEMPT
#define SDMA3_RLC5_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
#define SDMA3_RLC5_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
//SDMA3_RLC5_DUMMY_REG
#define SDMA3_RLC5_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
#define SDMA3_RLC5_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
//SDMA3_RLC5_RB_WPTR_POLL_ADDR_HI
#define SDMA3_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
#define SDMA3_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
//SDMA3_RLC5_RB_WPTR_POLL_ADDR_LO
#define SDMA3_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
#define SDMA3_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
//SDMA3_RLC5_RB_AQL_CNTL
#define SDMA3_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
#define SDMA3_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
#define SDMA3_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
#define SDMA3_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                  0x10
#define SDMA3_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT                                            0x11
#define SDMA3_RLC5_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT                                                         0x12
#define SDMA3_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
#define SDMA3_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
#define SDMA3_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
#define SDMA3_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                    0x00010000L
#define SDMA3_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK                                              0x00020000L
#define SDMA3_RLC5_RB_AQL_CNTL__OVERLAP_ENABLE_MASK                                                           0x00040000L
//SDMA3_RLC5_MINOR_PTR_UPDATE
#define SDMA3_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
#define SDMA3_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
//SDMA3_RLC5_MIDCMD_DATA0
#define SDMA3_RLC5_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
#define SDMA3_RLC5_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC5_MIDCMD_DATA1
#define SDMA3_RLC5_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
#define SDMA3_RLC5_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC5_MIDCMD_DATA2
#define SDMA3_RLC5_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
#define SDMA3_RLC5_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC5_MIDCMD_DATA3
#define SDMA3_RLC5_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
#define SDMA3_RLC5_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC5_MIDCMD_DATA4
#define SDMA3_RLC5_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
#define SDMA3_RLC5_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC5_MIDCMD_DATA5
#define SDMA3_RLC5_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
#define SDMA3_RLC5_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC5_MIDCMD_DATA6
#define SDMA3_RLC5_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
#define SDMA3_RLC5_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC5_MIDCMD_DATA7
#define SDMA3_RLC5_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
#define SDMA3_RLC5_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC5_MIDCMD_DATA8
#define SDMA3_RLC5_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
#define SDMA3_RLC5_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC5_MIDCMD_DATA9
#define SDMA3_RLC5_MIDCMD_DATA9__DATA9__SHIFT                                                                 0x0
#define SDMA3_RLC5_MIDCMD_DATA9__DATA9_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC5_MIDCMD_DATA10
#define SDMA3_RLC5_MIDCMD_DATA10__DATA10__SHIFT                                                               0x0
#define SDMA3_RLC5_MIDCMD_DATA10__DATA10_MASK                                                                 0xFFFFFFFFL
//SDMA3_RLC5_MIDCMD_CNTL
#define SDMA3_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
#define SDMA3_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
#define SDMA3_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
#define SDMA3_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
#define SDMA3_RLC5_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
#define SDMA3_RLC5_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
#define SDMA3_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
#define SDMA3_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
//SDMA3_RLC6_RB_CNTL
#define SDMA3_RLC6_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
#define SDMA3_RLC6_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
#define SDMA3_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
#define SDMA3_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
#define SDMA3_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
#define SDMA3_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
#define SDMA3_RLC6_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
#define SDMA3_RLC6_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
#define SDMA3_RLC6_RB_CNTL__RPTR_WB_IDLE__SHIFT                                                               0x1f
#define SDMA3_RLC6_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
#define SDMA3_RLC6_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
#define SDMA3_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
#define SDMA3_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
#define SDMA3_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
#define SDMA3_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
#define SDMA3_RLC6_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
#define SDMA3_RLC6_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
#define SDMA3_RLC6_RB_CNTL__RPTR_WB_IDLE_MASK                                                                 0x80000000L
//SDMA3_RLC6_RB_BASE
#define SDMA3_RLC6_RB_BASE__ADDR__SHIFT                                                                       0x0
#define SDMA3_RLC6_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
//SDMA3_RLC6_RB_BASE_HI
#define SDMA3_RLC6_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA3_RLC6_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
//SDMA3_RLC6_RB_RPTR
#define SDMA3_RLC6_RB_RPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA3_RLC6_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA3_RLC6_RB_RPTR_HI
#define SDMA3_RLC6_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA3_RLC6_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA3_RLC6_RB_WPTR
#define SDMA3_RLC6_RB_WPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA3_RLC6_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA3_RLC6_RB_WPTR_HI
#define SDMA3_RLC6_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA3_RLC6_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA3_RLC6_RB_WPTR_POLL_CNTL
#define SDMA3_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
#define SDMA3_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
#define SDMA3_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
#define SDMA3_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
#define SDMA3_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
#define SDMA3_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
#define SDMA3_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
#define SDMA3_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
#define SDMA3_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
#define SDMA3_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
//SDMA3_RLC6_RB_RPTR_ADDR_HI
#define SDMA3_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
#define SDMA3_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
//SDMA3_RLC6_RB_RPTR_ADDR_LO
#define SDMA3_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
#define SDMA3_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
//SDMA3_RLC6_IB_CNTL
#define SDMA3_RLC6_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
#define SDMA3_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
#define SDMA3_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
#define SDMA3_RLC6_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
#define SDMA3_RLC6_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
#define SDMA3_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
#define SDMA3_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
#define SDMA3_RLC6_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
//SDMA3_RLC6_IB_RPTR
#define SDMA3_RLC6_IB_RPTR__OFFSET__SHIFT                                                                     0x2
#define SDMA3_RLC6_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
//SDMA3_RLC6_IB_OFFSET
#define SDMA3_RLC6_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
#define SDMA3_RLC6_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
//SDMA3_RLC6_IB_BASE_LO
#define SDMA3_RLC6_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
#define SDMA3_RLC6_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
//SDMA3_RLC6_IB_BASE_HI
#define SDMA3_RLC6_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA3_RLC6_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
//SDMA3_RLC6_IB_SIZE
#define SDMA3_RLC6_IB_SIZE__SIZE__SHIFT                                                                       0x0
#define SDMA3_RLC6_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
//SDMA3_RLC6_SKIP_CNTL
#define SDMA3_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
#define SDMA3_RLC6_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
//SDMA3_RLC6_CONTEXT_STATUS
#define SDMA3_RLC6_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
#define SDMA3_RLC6_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
#define SDMA3_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
#define SDMA3_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
#define SDMA3_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
#define SDMA3_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
#define SDMA3_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
#define SDMA3_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
#define SDMA3_RLC6_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
#define SDMA3_RLC6_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
#define SDMA3_RLC6_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
#define SDMA3_RLC6_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
#define SDMA3_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
#define SDMA3_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
#define SDMA3_RLC6_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
#define SDMA3_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
//SDMA3_RLC6_DOORBELL
#define SDMA3_RLC6_DOORBELL__ENABLE__SHIFT                                                                    0x1c
#define SDMA3_RLC6_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
#define SDMA3_RLC6_DOORBELL__ENABLE_MASK                                                                      0x10000000L
#define SDMA3_RLC6_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
//SDMA3_RLC6_STATUS
#define SDMA3_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
#define SDMA3_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
#define SDMA3_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
#define SDMA3_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
//SDMA3_RLC6_DOORBELL_LOG
#define SDMA3_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
#define SDMA3_RLC6_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
#define SDMA3_RLC6_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
#define SDMA3_RLC6_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
//SDMA3_RLC6_WATERMARK
#define SDMA3_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
#define SDMA3_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
#define SDMA3_RLC6_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
#define SDMA3_RLC6_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
//SDMA3_RLC6_DOORBELL_OFFSET
#define SDMA3_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
#define SDMA3_RLC6_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
//SDMA3_RLC6_CSA_ADDR_LO
#define SDMA3_RLC6_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
#define SDMA3_RLC6_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
//SDMA3_RLC6_CSA_ADDR_HI
#define SDMA3_RLC6_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
#define SDMA3_RLC6_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
//SDMA3_RLC6_IB_SUB_REMAIN
#define SDMA3_RLC6_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
#define SDMA3_RLC6_IB_SUB_REMAIN__SIZE_MASK                                                                   0x00003FFFL
//SDMA3_RLC6_PREEMPT
#define SDMA3_RLC6_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
#define SDMA3_RLC6_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
//SDMA3_RLC6_DUMMY_REG
#define SDMA3_RLC6_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
#define SDMA3_RLC6_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
//SDMA3_RLC6_RB_WPTR_POLL_ADDR_HI
#define SDMA3_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
#define SDMA3_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
//SDMA3_RLC6_RB_WPTR_POLL_ADDR_LO
#define SDMA3_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
#define SDMA3_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
//SDMA3_RLC6_RB_AQL_CNTL
#define SDMA3_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
#define SDMA3_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
#define SDMA3_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
#define SDMA3_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                  0x10
#define SDMA3_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT                                            0x11
#define SDMA3_RLC6_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT                                                         0x12
#define SDMA3_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
#define SDMA3_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
#define SDMA3_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
#define SDMA3_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                    0x00010000L
#define SDMA3_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK                                              0x00020000L
#define SDMA3_RLC6_RB_AQL_CNTL__OVERLAP_ENABLE_MASK                                                           0x00040000L
//SDMA3_RLC6_MINOR_PTR_UPDATE
#define SDMA3_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
#define SDMA3_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
//SDMA3_RLC6_MIDCMD_DATA0
#define SDMA3_RLC6_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
#define SDMA3_RLC6_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC6_MIDCMD_DATA1
#define SDMA3_RLC6_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
#define SDMA3_RLC6_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC6_MIDCMD_DATA2
#define SDMA3_RLC6_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
#define SDMA3_RLC6_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC6_MIDCMD_DATA3
#define SDMA3_RLC6_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
#define SDMA3_RLC6_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC6_MIDCMD_DATA4
#define SDMA3_RLC6_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
#define SDMA3_RLC6_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC6_MIDCMD_DATA5
#define SDMA3_RLC6_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
#define SDMA3_RLC6_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC6_MIDCMD_DATA6
#define SDMA3_RLC6_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
#define SDMA3_RLC6_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC6_MIDCMD_DATA7
#define SDMA3_RLC6_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
#define SDMA3_RLC6_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC6_MIDCMD_DATA8
#define SDMA3_RLC6_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
#define SDMA3_RLC6_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC6_MIDCMD_DATA9
#define SDMA3_RLC6_MIDCMD_DATA9__DATA9__SHIFT                                                                 0x0
#define SDMA3_RLC6_MIDCMD_DATA9__DATA9_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC6_MIDCMD_DATA10
#define SDMA3_RLC6_MIDCMD_DATA10__DATA10__SHIFT                                                               0x0
#define SDMA3_RLC6_MIDCMD_DATA10__DATA10_MASK                                                                 0xFFFFFFFFL
//SDMA3_RLC6_MIDCMD_CNTL
#define SDMA3_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
#define SDMA3_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
#define SDMA3_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
#define SDMA3_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
#define SDMA3_RLC6_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
#define SDMA3_RLC6_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
#define SDMA3_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
#define SDMA3_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
//SDMA3_RLC7_RB_CNTL
#define SDMA3_RLC7_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
#define SDMA3_RLC7_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
#define SDMA3_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
#define SDMA3_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
#define SDMA3_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
#define SDMA3_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
#define SDMA3_RLC7_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
#define SDMA3_RLC7_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
#define SDMA3_RLC7_RB_CNTL__RPTR_WB_IDLE__SHIFT                                                               0x1f
#define SDMA3_RLC7_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
#define SDMA3_RLC7_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
#define SDMA3_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
#define SDMA3_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
#define SDMA3_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
#define SDMA3_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
#define SDMA3_RLC7_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
#define SDMA3_RLC7_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
#define SDMA3_RLC7_RB_CNTL__RPTR_WB_IDLE_MASK                                                                 0x80000000L
//SDMA3_RLC7_RB_BASE
#define SDMA3_RLC7_RB_BASE__ADDR__SHIFT                                                                       0x0
#define SDMA3_RLC7_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
//SDMA3_RLC7_RB_BASE_HI
#define SDMA3_RLC7_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA3_RLC7_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
//SDMA3_RLC7_RB_RPTR
#define SDMA3_RLC7_RB_RPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA3_RLC7_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA3_RLC7_RB_RPTR_HI
#define SDMA3_RLC7_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA3_RLC7_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA3_RLC7_RB_WPTR
#define SDMA3_RLC7_RB_WPTR__OFFSET__SHIFT                                                                     0x0
#define SDMA3_RLC7_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
//SDMA3_RLC7_RB_WPTR_HI
#define SDMA3_RLC7_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
#define SDMA3_RLC7_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
//SDMA3_RLC7_RB_WPTR_POLL_CNTL
#define SDMA3_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
#define SDMA3_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
#define SDMA3_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
#define SDMA3_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
#define SDMA3_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
#define SDMA3_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
#define SDMA3_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
#define SDMA3_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
#define SDMA3_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
#define SDMA3_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
//SDMA3_RLC7_RB_RPTR_ADDR_HI
#define SDMA3_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
#define SDMA3_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
//SDMA3_RLC7_RB_RPTR_ADDR_LO
#define SDMA3_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
#define SDMA3_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
//SDMA3_RLC7_IB_CNTL
#define SDMA3_RLC7_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
#define SDMA3_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
#define SDMA3_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
#define SDMA3_RLC7_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
#define SDMA3_RLC7_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
#define SDMA3_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
#define SDMA3_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
#define SDMA3_RLC7_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
//SDMA3_RLC7_IB_RPTR
#define SDMA3_RLC7_IB_RPTR__OFFSET__SHIFT                                                                     0x2
#define SDMA3_RLC7_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
//SDMA3_RLC7_IB_OFFSET
#define SDMA3_RLC7_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
#define SDMA3_RLC7_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
//SDMA3_RLC7_IB_BASE_LO
#define SDMA3_RLC7_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
#define SDMA3_RLC7_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
//SDMA3_RLC7_IB_BASE_HI
#define SDMA3_RLC7_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
#define SDMA3_RLC7_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
//SDMA3_RLC7_IB_SIZE
#define SDMA3_RLC7_IB_SIZE__SIZE__SHIFT                                                                       0x0
#define SDMA3_RLC7_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
//SDMA3_RLC7_SKIP_CNTL
#define SDMA3_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
#define SDMA3_RLC7_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
//SDMA3_RLC7_CONTEXT_STATUS
#define SDMA3_RLC7_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
#define SDMA3_RLC7_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
#define SDMA3_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
#define SDMA3_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
#define SDMA3_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
#define SDMA3_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
#define SDMA3_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
#define SDMA3_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
#define SDMA3_RLC7_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
#define SDMA3_RLC7_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
#define SDMA3_RLC7_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
#define SDMA3_RLC7_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
#define SDMA3_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
#define SDMA3_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
#define SDMA3_RLC7_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
#define SDMA3_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
//SDMA3_RLC7_DOORBELL
#define SDMA3_RLC7_DOORBELL__ENABLE__SHIFT                                                                    0x1c
#define SDMA3_RLC7_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
#define SDMA3_RLC7_DOORBELL__ENABLE_MASK                                                                      0x10000000L
#define SDMA3_RLC7_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
//SDMA3_RLC7_STATUS
#define SDMA3_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
#define SDMA3_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
#define SDMA3_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
#define SDMA3_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
//SDMA3_RLC7_DOORBELL_LOG
#define SDMA3_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
#define SDMA3_RLC7_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
#define SDMA3_RLC7_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
#define SDMA3_RLC7_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
//SDMA3_RLC7_WATERMARK
#define SDMA3_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
#define SDMA3_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
#define SDMA3_RLC7_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
#define SDMA3_RLC7_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
//SDMA3_RLC7_DOORBELL_OFFSET
#define SDMA3_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
#define SDMA3_RLC7_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
//SDMA3_RLC7_CSA_ADDR_LO
#define SDMA3_RLC7_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
#define SDMA3_RLC7_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
//SDMA3_RLC7_CSA_ADDR_HI
#define SDMA3_RLC7_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
#define SDMA3_RLC7_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
//SDMA3_RLC7_IB_SUB_REMAIN
#define SDMA3_RLC7_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
#define SDMA3_RLC7_IB_SUB_REMAIN__SIZE_MASK                                                                   0x00003FFFL
//SDMA3_RLC7_PREEMPT
#define SDMA3_RLC7_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
#define SDMA3_RLC7_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
//SDMA3_RLC7_DUMMY_REG
#define SDMA3_RLC7_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
#define SDMA3_RLC7_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
//SDMA3_RLC7_RB_WPTR_POLL_ADDR_HI
#define SDMA3_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
#define SDMA3_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
//SDMA3_RLC7_RB_WPTR_POLL_ADDR_LO
#define SDMA3_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
#define SDMA3_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
//SDMA3_RLC7_RB_AQL_CNTL
#define SDMA3_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
#define SDMA3_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
#define SDMA3_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
#define SDMA3_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                  0x10
#define SDMA3_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT                                            0x11
#define SDMA3_RLC7_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT                                                         0x12
#define SDMA3_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
#define SDMA3_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
#define SDMA3_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
#define SDMA3_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                    0x00010000L
#define SDMA3_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK                                              0x00020000L
#define SDMA3_RLC7_RB_AQL_CNTL__OVERLAP_ENABLE_MASK                                                           0x00040000L
//SDMA3_RLC7_MINOR_PTR_UPDATE
#define SDMA3_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
#define SDMA3_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
//SDMA3_RLC7_MIDCMD_DATA0
#define SDMA3_RLC7_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
#define SDMA3_RLC7_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC7_MIDCMD_DATA1
#define SDMA3_RLC7_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
#define SDMA3_RLC7_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC7_MIDCMD_DATA2
#define SDMA3_RLC7_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
#define SDMA3_RLC7_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC7_MIDCMD_DATA3
#define SDMA3_RLC7_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
#define SDMA3_RLC7_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC7_MIDCMD_DATA4
#define SDMA3_RLC7_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
#define SDMA3_RLC7_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC7_MIDCMD_DATA5
#define SDMA3_RLC7_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
#define SDMA3_RLC7_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC7_MIDCMD_DATA6
#define SDMA3_RLC7_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
#define SDMA3_RLC7_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC7_MIDCMD_DATA7
#define SDMA3_RLC7_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
#define SDMA3_RLC7_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC7_MIDCMD_DATA8
#define SDMA3_RLC7_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
#define SDMA3_RLC7_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC7_MIDCMD_DATA9
#define SDMA3_RLC7_MIDCMD_DATA9__DATA9__SHIFT                                                                 0x0
#define SDMA3_RLC7_MIDCMD_DATA9__DATA9_MASK                                                                   0xFFFFFFFFL
//SDMA3_RLC7_MIDCMD_DATA10
#define SDMA3_RLC7_MIDCMD_DATA10__DATA10__SHIFT                                                               0x0
#define SDMA3_RLC7_MIDCMD_DATA10__DATA10_MASK                                                                 0xFFFFFFFFL
//SDMA3_RLC7_MIDCMD_CNTL
#define SDMA3_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
#define SDMA3_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
#define SDMA3_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
#define SDMA3_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
#define SDMA3_RLC7_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
#define SDMA3_RLC7_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
#define SDMA3_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
#define SDMA3_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L


// addressBlock: gccacind
//PCC_STALL_PATTERN_CTRL
#define PCC_STALL_PATTERN_CTRL__PCC_STEP_INTERVAL__SHIFT                                                      0x0
#define PCC_STALL_PATTERN_CTRL__PCC_BEGIN_STEP__SHIFT                                                         0xa
#define PCC_STALL_PATTERN_CTRL__PCC_END_STEP__SHIFT                                                           0xf
#define PCC_STALL_PATTERN_CTRL__PCC_THROTTLE_PATTERN_BIT_NUMS__SHIFT                                          0x14
#define PCC_STALL_PATTERN_CTRL__PCC_INST_THROT_INCR__SHIFT                                                    0x18
#define PCC_STALL_PATTERN_CTRL__PCC_INST_THROT_DECR__SHIFT                                                    0x19
#define PCC_STALL_PATTERN_CTRL__PCC_DITHER_MODE__SHIFT                                                        0x1a
#define PCC_STALL_PATTERN_CTRL__PCC_STEP_INTERVAL_MASK                                                        0x000003FFL
#define PCC_STALL_PATTERN_CTRL__PCC_BEGIN_STEP_MASK                                                           0x00007C00L
#define PCC_STALL_PATTERN_CTRL__PCC_END_STEP_MASK                                                             0x000F8000L
#define PCC_STALL_PATTERN_CTRL__PCC_THROTTLE_PATTERN_BIT_NUMS_MASK                                            0x00F00000L
#define PCC_STALL_PATTERN_CTRL__PCC_INST_THROT_INCR_MASK                                                      0x01000000L
#define PCC_STALL_PATTERN_CTRL__PCC_INST_THROT_DECR_MASK                                                      0x02000000L
#define PCC_STALL_PATTERN_CTRL__PCC_DITHER_MODE_MASK                                                          0x04000000L
//PWRBRK_STALL_PATTERN_CTRL
#define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT                                                0x0
#define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT                                                   0xa
#define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT                                                     0xf
#define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT                                    0x14
#define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL_MASK                                                  0x000003FFL
#define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP_MASK                                                     0x00007C00L
#define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP_MASK                                                       0x000F8000L
#define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS_MASK                                      0x00F00000L
//PCC_STALL_PATTERN_1_2
#define PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_1__SHIFT                                                     0x0
#define PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_2__SHIFT                                                     0x10
#define PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_1_MASK                                                       0x00007FFFL
#define PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_2_MASK                                                       0x7FFF0000L
//PCC_STALL_PATTERN_3_4
#define PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_3__SHIFT                                                     0x0
#define PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_4__SHIFT                                                     0x10
#define PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_3_MASK                                                       0x00007FFFL
#define PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_4_MASK                                                       0x7FFF0000L
//PCC_STALL_PATTERN_5_6
#define PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_5__SHIFT                                                     0x0
#define PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_6__SHIFT                                                     0x10
#define PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_5_MASK                                                       0x00007FFFL
#define PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_6_MASK                                                       0x7FFF0000L
//PCC_STALL_PATTERN_7
#define PCC_STALL_PATTERN_7__PCC_STALL_PATTERN_7__SHIFT                                                       0x0
#define PCC_STALL_PATTERN_7__PCC_STALL_PATTERN_7_MASK                                                         0x00007FFFL
//PWRBRK_STALL_PATTERN_1_2
#define PWRBRK_STALL_PATTERN_1_2__PWRBRK_STALL_PATTERN_1__SHIFT                                               0x0
#define PWRBRK_STALL_PATTERN_1_2__PWRBRK_STALL_PATTERN_2__SHIFT                                               0x10
#define PWRBRK_STALL_PATTERN_1_2__PWRBRK_STALL_PATTERN_1_MASK                                                 0x00007FFFL
#define PWRBRK_STALL_PATTERN_1_2__PWRBRK_STALL_PATTERN_2_MASK                                                 0x7FFF0000L
//PWRBRK_STALL_PATTERN_3_4
#define PWRBRK_STALL_PATTERN_3_4__PWRBRK_STALL_PATTERN_3__SHIFT                                               0x0
#define PWRBRK_STALL_PATTERN_3_4__PWRBRK_STALL_PATTERN_4__SHIFT                                               0x10
#define PWRBRK_STALL_PATTERN_3_4__PWRBRK_STALL_PATTERN_3_MASK                                                 0x00007FFFL
#define PWRBRK_STALL_PATTERN_3_4__PWRBRK_STALL_PATTERN_4_MASK                                                 0x7FFF0000L
//PWRBRK_STALL_PATTERN_5_6
#define PWRBRK_STALL_PATTERN_5_6__PWRBRK_STALL_PATTERN_5__SHIFT                                               0x0
#define PWRBRK_STALL_PATTERN_5_6__PWRBRK_STALL_PATTERN_6__SHIFT                                               0x10
#define PWRBRK_STALL_PATTERN_5_6__PWRBRK_STALL_PATTERN_5_MASK                                                 0x00007FFFL
#define PWRBRK_STALL_PATTERN_5_6__PWRBRK_STALL_PATTERN_6_MASK                                                 0x7FFF0000L
//PWRBRK_STALL_PATTERN_7
#define PWRBRK_STALL_PATTERN_7__PWRBRK_STALL_PATTERN_7__SHIFT                                                 0x0
#define PWRBRK_STALL_PATTERN_7__PWRBRK_STALL_PATTERN_7_MASK                                                   0x00007FFFL
//PCC_PWRBRK_HYSTERESIS_CTRL
#define PCC_PWRBRK_HYSTERESIS_CTRL__PCC_MAX_HYSTERESIS__SHIFT                                                 0x0
#define PCC_PWRBRK_HYSTERESIS_CTRL__PWRBRK_MAX_HYSTERESIS__SHIFT                                              0x8
#define PCC_PWRBRK_HYSTERESIS_CTRL__PCC_MAX_HYSTERESIS_MASK                                                   0x000000FFL
#define PCC_PWRBRK_HYSTERESIS_CTRL__PWRBRK_MAX_HYSTERESIS_MASK                                                0x0000FF00L
//EDC_STRETCH_PERF_COUNTER
#define EDC_STRETCH_PERF_COUNTER__STRETCH_PERF_COUNTER__SHIFT                                                 0x0
#define EDC_STRETCH_PERF_COUNTER__STRETCH_PERF_COUNTER_MASK                                                   0xFFFFFFFFL
//EDC_UNSTRETCH_PERF_COUNTER
#define EDC_UNSTRETCH_PERF_COUNTER__UNSTRETCH_PERF_COUNTER__SHIFT                                             0x0
#define EDC_UNSTRETCH_PERF_COUNTER__UNSTRETCH_PERF_COUNTER_MASK                                               0xFFFFFFFFL
//EDC_STRETCH_NUM_PERF_COUNTER
#define EDC_STRETCH_NUM_PERF_COUNTER__STRETCH_NUM_PERF_COUNTER__SHIFT                                         0x0
#define EDC_STRETCH_NUM_PERF_COUNTER__STRETCH_NUM_PERF_COUNTER_MASK                                           0xFFFFFFFFL
//GC_CAC_ID
#define GC_CAC_ID__CAC_BLOCK_ID__SHIFT                                                                        0x0
#define GC_CAC_ID__CAC_SIGNAL_ID__SHIFT                                                                       0x6
#define GC_CAC_ID__UNUSED_0__SHIFT                                                                            0xe
#define GC_CAC_ID__CAC_BLOCK_ID_MASK                                                                          0x0000003FL
#define GC_CAC_ID__CAC_SIGNAL_ID_MASK                                                                         0x00003FC0L
#define GC_CAC_ID__UNUSED_0_MASK                                                                              0xFFFFC000L
//GC_CAC_CNTL
#define GC_CAC_CNTL__CAC_FORCE_DISABLE__SHIFT                                                                 0x0
#define GC_CAC_CNTL__CAC_THRESHOLD__SHIFT                                                                     0x1
#define GC_CAC_CNTL__UNUSED_0__SHIFT                                                                          0x11
#define GC_CAC_CNTL__CAC_FORCE_DISABLE_MASK                                                                   0x00000001L
#define GC_CAC_CNTL__CAC_THRESHOLD_MASK                                                                       0x0001FFFEL
#define GC_CAC_CNTL__UNUSED_0_MASK                                                                            0xFFFE0000L
//GC_CAC_OVR_SEL
#define GC_CAC_OVR_SEL__CAC_OVR_SEL__SHIFT                                                                    0x0
#define GC_CAC_OVR_SEL__CAC_OVR_SEL_MASK                                                                      0xFFFFFFFFL
//GC_CAC_OVR_VAL
#define GC_CAC_OVR_VAL__CAC_OVR_VAL__SHIFT                                                                    0x0
#define GC_CAC_OVR_VAL__CAC_OVR_VAL_MASK                                                                      0xFFFFFFFFL
//GC_CAC_WEIGHT_BCI_0
#define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG0__SHIFT                                                           0x0
#define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG1__SHIFT                                                           0x10
#define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG0_MASK                                                             0x0000FFFFL
#define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG1_MASK                                                             0xFFFF0000L
//GC_CAC_WEIGHT_CB_0
#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG0__SHIFT                                                             0x0
#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG1__SHIFT                                                             0x10
#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG0_MASK                                                               0x0000FFFFL
#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG1_MASK                                                               0xFFFF0000L
//GC_CAC_WEIGHT_CB_1
#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG2__SHIFT                                                             0x0
#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG3__SHIFT                                                             0x10
#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG2_MASK                                                               0x0000FFFFL
#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG3_MASK                                                               0xFFFF0000L
//GC_CAC_WEIGHT_CB_2
#define GC_CAC_WEIGHT_CB_2__WEIGHT_CB_SIG4__SHIFT                                                             0x0
#define GC_CAC_WEIGHT_CB_2__WEIGHT_CB_SIG5__SHIFT                                                             0x10
#define GC_CAC_WEIGHT_CB_2__WEIGHT_CB_SIG4_MASK                                                               0x0000FFFFL
#define GC_CAC_WEIGHT_CB_2__WEIGHT_CB_SIG5_MASK                                                               0xFFFF0000L
//GC_CAC_WEIGHT_CB_3
#define GC_CAC_WEIGHT_CB_3__WEIGHT_CB_SIG6__SHIFT                                                             0x0
#define GC_CAC_WEIGHT_CB_3__WEIGHT_CB_SIG7__SHIFT                                                             0x10
#define GC_CAC_WEIGHT_CB_3__WEIGHT_CB_SIG6_MASK                                                               0x0000FFFFL
#define GC_CAC_WEIGHT_CB_3__WEIGHT_CB_SIG7_MASK                                                               0xFFFF0000L
//GC_CAC_WEIGHT_CB_4
#define GC_CAC_WEIGHT_CB_4__WEIGHT_CB_SIG8__SHIFT                                                             0x0
#define GC_CAC_WEIGHT_CB_4__WEIGHT_CB_SIG9__SHIFT                                                             0x10
#define GC_CAC_WEIGHT_CB_4__WEIGHT_CB_SIG8_MASK                                                               0x0000FFFFL
#define GC_CAC_WEIGHT_CB_4__WEIGHT_CB_SIG9_MASK                                                               0xFFFF0000L
//GC_CAC_WEIGHT_CP_0
#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG0__SHIFT                                                             0x0
#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG1__SHIFT                                                             0x10
#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG0_MASK                                                               0x0000FFFFL
#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG1_MASK                                                               0xFFFF0000L
//GC_CAC_WEIGHT_CP_1
#define GC_CAC_WEIGHT_CP_1__WEIGHT_CP_SIG2__SHIFT                                                             0x0
#define GC_CAC_WEIGHT_CP_1__UNUSED_0__SHIFT                                                                   0x10
#define GC_CAC_WEIGHT_CP_1__WEIGHT_CP_SIG2_MASK                                                               0x0000FFFFL
#define GC_CAC_WEIGHT_CP_1__UNUSED_0_MASK                                                                     0xFFFF0000L
//GC_CAC_WEIGHT_DB_0
#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG0__SHIFT                                                             0x0
#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG1__SHIFT                                                             0x10
#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG0_MASK                                                               0x0000FFFFL
#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG1_MASK                                                               0xFFFF0000L
//GC_CAC_WEIGHT_DB_1
#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG2__SHIFT                                                             0x0
#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG3__SHIFT                                                             0x10
#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG2_MASK                                                               0x0000FFFFL
#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG3_MASK                                                               0xFFFF0000L
//GC_CAC_WEIGHT_DB_2
#define GC_CAC_WEIGHT_DB_2__WEIGHT_DB_SIG4__SHIFT                                                             0x0
#define GC_CAC_WEIGHT_DB_2__WEIGHT_DB_SIG5__SHIFT                                                             0x10
#define GC_CAC_WEIGHT_DB_2__WEIGHT_DB_SIG4_MASK                                                               0x0000FFFFL
#define GC_CAC_WEIGHT_DB_2__WEIGHT_DB_SIG5_MASK                                                               0xFFFF0000L
//GC_CAC_WEIGHT_DB_3
#define GC_CAC_WEIGHT_DB_3__WEIGHT_DB_SIG6__SHIFT                                                             0x0
#define GC_CAC_WEIGHT_DB_3__WEIGHT_DB_SIG7__SHIFT                                                             0x10
#define GC_CAC_WEIGHT_DB_3__WEIGHT_DB_SIG6_MASK                                                               0x0000FFFFL
#define GC_CAC_WEIGHT_DB_3__WEIGHT_DB_SIG7_MASK                                                               0xFFFF0000L
//GC_CAC_WEIGHT_DB_4
#define GC_CAC_WEIGHT_DB_4__WEIGHT_DB_SIG8__SHIFT                                                             0x0
#define GC_CAC_WEIGHT_DB_4__WEIGHT_DB_SIG9__SHIFT                                                             0x10
#define GC_CAC_WEIGHT_DB_4__WEIGHT_DB_SIG8_MASK                                                               0x0000FFFFL
#define GC_CAC_WEIGHT_DB_4__WEIGHT_DB_SIG9_MASK                                                               0xFFFF0000L
//GC_CAC_WEIGHT_GDS_0
#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG0__SHIFT                                                           0x0
#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG1__SHIFT                                                           0x10
#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG0_MASK                                                             0x0000FFFFL
#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG1_MASK                                                             0xFFFF0000L
//GC_CAC_WEIGHT_GDS_1
#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG2__SHIFT                                                           0x0
#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG3__SHIFT                                                           0x10
#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG2_MASK                                                             0x0000FFFFL
#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG3_MASK                                                             0xFFFF0000L
//GC_CAC_WEIGHT_GDS_2
#define GC_CAC_WEIGHT_GDS_2__WEIGHT_GDS_SIG4__SHIFT                                                           0x0
#define GC_CAC_WEIGHT_GDS_2__WEIGHT_GDS_SIG4_MASK                                                             0x0000FFFFL
//GC_CAC_WEIGHT_LDS_0
#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG0__SHIFT                                                           0x0
#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG1__SHIFT                                                           0x10
#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG0_MASK                                                             0x0000FFFFL
#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG1_MASK                                                             0xFFFF0000L
//GC_CAC_WEIGHT_LDS_1
#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG2__SHIFT                                                           0x0
#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG3__SHIFT                                                           0x10
#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG2_MASK                                                             0x0000FFFFL
#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG3_MASK                                                             0xFFFF0000L
//GC_CAC_WEIGHT_LDS_2
#define GC_CAC_WEIGHT_LDS_2__WEIGHT_LDS_SIG4__SHIFT                                                           0x0
#define GC_CAC_WEIGHT_LDS_2__WEIGHT_LDS_SIG5__SHIFT                                                           0x10
#define GC_CAC_WEIGHT_LDS_2__WEIGHT_LDS_SIG4_MASK                                                             0x0000FFFFL
#define GC_CAC_WEIGHT_LDS_2__WEIGHT_LDS_SIG5_MASK                                                             0xFFFF0000L
//GC_CAC_WEIGHT_LDS_3
#define GC_CAC_WEIGHT_LDS_3__WEIGHT_LDS_SIG6__SHIFT                                                           0x0
#define GC_CAC_WEIGHT_LDS_3__WEIGHT_LDS_SIG7__SHIFT                                                           0x10
#define GC_CAC_WEIGHT_LDS_3__WEIGHT_LDS_SIG6_MASK                                                             0x0000FFFFL
#define GC_CAC_WEIGHT_LDS_3__WEIGHT_LDS_SIG7_MASK                                                             0xFFFF0000L
//GC_CAC_WEIGHT_LDS_4
#define GC_CAC_WEIGHT_LDS_4__WEIGHT_LDS_SIG8__SHIFT                                                           0x0
#define GC_CAC_WEIGHT_LDS_4__UNUSED_0__SHIFT                                                                  0x10
#define GC_CAC_WEIGHT_LDS_4__WEIGHT_LDS_SIG8_MASK                                                             0x0000FFFFL
#define GC_CAC_WEIGHT_LDS_4__UNUSED_0_MASK                                                                    0xFFFF0000L
//GC_CAC_WEIGHT_PA_0
#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG0__SHIFT                                                             0x0
#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG1__SHIFT                                                             0x10
#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG0_MASK                                                               0x0000FFFFL
#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG1_MASK                                                               0xFFFF0000L
//GC_CAC_WEIGHT_PA_1
#define GC_CAC_WEIGHT_PA_1__WEIGHT_PA_SIG2__SHIFT                                                             0x0
#define GC_CAC_WEIGHT_PA_1__WEIGHT_PA_SIG3__SHIFT                                                             0x10
#define GC_CAC_WEIGHT_PA_1__WEIGHT_PA_SIG2_MASK                                                               0x0000FFFFL
#define GC_CAC_WEIGHT_PA_1__WEIGHT_PA_SIG3_MASK                                                               0xFFFF0000L
//GC_CAC_WEIGHT_PA_2
#define GC_CAC_WEIGHT_PA_2__WEIGHT_PA_SIG4__SHIFT                                                             0x0
#define GC_CAC_WEIGHT_PA_2__WEIGHT_PA_SIG5__SHIFT                                                             0x10
#define GC_CAC_WEIGHT_PA_2__WEIGHT_PA_SIG4_MASK                                                               0x0000FFFFL
#define GC_CAC_WEIGHT_PA_2__WEIGHT_PA_SIG5_MASK                                                               0xFFFF0000L
//GC_CAC_WEIGHT_PA_3
#define GC_CAC_WEIGHT_PA_3__WEIGHT_PA_SIG6__SHIFT                                                             0x0
#define GC_CAC_WEIGHT_PA_3__WEIGHT_PA_SIG7__SHIFT                                                             0x10
#define GC_CAC_WEIGHT_PA_3__WEIGHT_PA_SIG6_MASK                                                               0x0000FFFFL
#define GC_CAC_WEIGHT_PA_3__WEIGHT_PA_SIG7_MASK                                                               0xFFFF0000L
//GC_CAC_WEIGHT_PC_0
#define GC_CAC_WEIGHT_PC_0__WEIGHT_PC_SIG0__SHIFT                                                             0x0
#define GC_CAC_WEIGHT_PC_0__UNUSED_0__SHIFT                                                                   0x10
#define GC_CAC_WEIGHT_PC_0__WEIGHT_PC_SIG0_MASK                                                               0x0000FFFFL
#define GC_CAC_WEIGHT_PC_0__UNUSED_0_MASK                                                                     0xFFFF0000L
//GC_CAC_WEIGHT_SC_0
#define GC_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG0__SHIFT                                                             0x0
#define GC_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG1__SHIFT                                                             0x10
#define GC_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG0_MASK                                                               0x0000FFFFL
#define GC_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG1_MASK                                                               0xFFFF0000L
//GC_CAC_WEIGHT_SC_1
#define GC_CAC_WEIGHT_SC_1__WEIGHT_SC_SIG2__SHIFT                                                             0x0
#define GC_CAC_WEIGHT_SC_1__WEIGHT_SC_SIG3__SHIFT                                                             0x10
#define GC_CAC_WEIGHT_SC_1__WEIGHT_SC_SIG2_MASK                                                               0x0000FFFFL
#define GC_CAC_WEIGHT_SC_1__WEIGHT_SC_SIG3_MASK                                                               0xFFFF0000L
//GC_CAC_WEIGHT_SC_2
#define GC_CAC_WEIGHT_SC_2__WEIGHT_SC_SIG4__SHIFT                                                             0x0
#define GC_CAC_WEIGHT_SC_2__WEIGHT_SC_SIG5__SHIFT                                                             0x10
#define GC_CAC_WEIGHT_SC_2__WEIGHT_SC_SIG4_MASK                                                               0x0000FFFFL
#define GC_CAC_WEIGHT_SC_2__WEIGHT_SC_SIG5_MASK                                                               0xFFFF0000L
//GC_CAC_WEIGHT_SC_3
#define GC_CAC_WEIGHT_SC_3__WEIGHT_SC_SIG6__SHIFT                                                             0x0
#define GC_CAC_WEIGHT_SC_3__WEIGHT_SC_SIG7__SHIFT                                                             0x10
#define GC_CAC_WEIGHT_SC_3__WEIGHT_SC_SIG6_MASK                                                               0x0000FFFFL
#define GC_CAC_WEIGHT_SC_3__WEIGHT_SC_SIG7_MASK                                                               0xFFFF0000L
//GC_CAC_WEIGHT_SPI_0
#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG0__SHIFT                                                           0x0
#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG1__SHIFT                                                           0x10
#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG0_MASK                                                             0x0000FFFFL
#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG1_MASK                                                             0xFFFF0000L
//GC_CAC_WEIGHT_SPI_1
#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG2__SHIFT                                                           0x0
#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG3__SHIFT                                                           0x10
#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG2_MASK                                                             0x0000FFFFL
#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG3_MASK                                                             0xFFFF0000L
//GC_CAC_WEIGHT_SPI_2
#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG4__SHIFT                                                           0x0
#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG5__SHIFT                                                           0x10
#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG4_MASK                                                             0x0000FFFFL
#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG5_MASK                                                             0xFFFF0000L
//GC_CAC_WEIGHT_SQ_0
#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG0__SHIFT                                                             0x0
#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG1__SHIFT                                                             0x10
#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG0_MASK                                                               0x0000FFFFL
#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG1_MASK                                                               0xFFFF0000L
//GC_CAC_WEIGHT_SQ_1
#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG2__SHIFT                                                             0x0
#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG3__SHIFT                                                             0x10
#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG2_MASK                                                               0x0000FFFFL
#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG3_MASK                                                               0xFFFF0000L
//GC_CAC_WEIGHT_SQ_2
#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG4__SHIFT                                                             0x0
#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG5__SHIFT                                                             0x10
#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG4_MASK                                                               0x0000FFFFL
#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG5_MASK                                                               0xFFFF0000L
//GC_CAC_WEIGHT_SQ_3
#define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG6__SHIFT                                                             0x0
#define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG7__SHIFT                                                             0x10
#define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG6_MASK                                                               0x0000FFFFL
#define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG7_MASK                                                               0xFFFF0000L
//GC_CAC_WEIGHT_SX_0
#define GC_CAC_WEIGHT_SX_0__WEIGHT_SX_SIG0__SHIFT                                                             0x0
#define GC_CAC_WEIGHT_SX_0__UNUSED_0__SHIFT                                                                   0x10
#define GC_CAC_WEIGHT_SX_0__WEIGHT_SX_SIG0_MASK                                                               0x0000FFFFL
#define GC_CAC_WEIGHT_SX_0__UNUSED_0_MASK                                                                     0xFFFF0000L
//GC_CAC_WEIGHT_SXRB_0
#define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG0__SHIFT                                                         0x0
#define GC_CAC_WEIGHT_SXRB_0__UNUSED_0__SHIFT                                                                 0x10
#define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG0_MASK                                                           0x0000FFFFL
#define GC_CAC_WEIGHT_SXRB_0__UNUSED_0_MASK                                                                   0xFFFF0000L
//GC_CAC_WEIGHT_TA_0
#define GC_CAC_WEIGHT_TA_0__WEIGHT_TA_SIG0__SHIFT                                                             0x0
#define GC_CAC_WEIGHT_TA_0__UNUSED_0__SHIFT                                                                   0x10
#define GC_CAC_WEIGHT_TA_0__WEIGHT_TA_SIG0_MASK                                                               0x0000FFFFL
#define GC_CAC_WEIGHT_TA_0__UNUSED_0_MASK                                                                     0xFFFF0000L
//GC_CAC_WEIGHT_TCP_0
#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG0__SHIFT                                                           0x0
#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG1__SHIFT                                                           0x10
#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG0_MASK                                                             0x0000FFFFL
#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG1_MASK                                                             0xFFFF0000L
//GC_CAC_WEIGHT_TCP_1
#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG2__SHIFT                                                           0x0
#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG3__SHIFT                                                           0x10
#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG2_MASK                                                             0x0000FFFFL
#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG3_MASK                                                             0xFFFF0000L
//GC_CAC_WEIGHT_TCP_2
#define GC_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG4__SHIFT                                                           0x0
#define GC_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG5__SHIFT                                                           0x10
#define GC_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG4_MASK                                                             0x0000FFFFL
#define GC_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG5_MASK                                                             0xFFFF0000L
//GC_CAC_WEIGHT_TCP_3
#define GC_CAC_WEIGHT_TCP_3__WEIGHT_TCP_SIG6__SHIFT                                                           0x0
#define GC_CAC_WEIGHT_TCP_3__WEIGHT_TCP_SIG7__SHIFT                                                           0x10
#define GC_CAC_WEIGHT_TCP_3__WEIGHT_TCP_SIG6_MASK                                                             0x0000FFFFL
#define GC_CAC_WEIGHT_TCP_3__WEIGHT_TCP_SIG7_MASK                                                             0xFFFF0000L
//GC_CAC_WEIGHT_TD_0
#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG0__SHIFT                                                             0x0
#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG1__SHIFT                                                             0x10
#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG0_MASK                                                               0x0000FFFFL
#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG1_MASK                                                               0xFFFF0000L
//GC_CAC_WEIGHT_TD_1
#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG2__SHIFT                                                             0x0
#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG3__SHIFT                                                             0x10
#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG2_MASK                                                               0x0000FFFFL
#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG3_MASK                                                               0xFFFF0000L
//GC_CAC_WEIGHT_TD_2
#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG4__SHIFT                                                             0x0
#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG5__SHIFT                                                             0x10
#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG4_MASK                                                               0x0000FFFFL
#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG5_MASK                                                               0xFFFF0000L
//GC_CAC_WEIGHT_TD_3
#define GC_CAC_WEIGHT_TD_3__WEIGHT_TD_SIG6__SHIFT                                                             0x0
#define GC_CAC_WEIGHT_TD_3__WEIGHT_TD_SIG7__SHIFT                                                             0x10
#define GC_CAC_WEIGHT_TD_3__WEIGHT_TD_SIG6_MASK                                                               0x0000FFFFL
#define GC_CAC_WEIGHT_TD_3__WEIGHT_TD_SIG7_MASK                                                               0xFFFF0000L
//GC_CAC_WEIGHT_TD_4
#define GC_CAC_WEIGHT_TD_4__WEIGHT_TD_SIG8__SHIFT                                                             0x0
#define GC_CAC_WEIGHT_TD_4__WEIGHT_TD_SIG9__SHIFT                                                             0x10
#define GC_CAC_WEIGHT_TD_4__WEIGHT_TD_SIG8_MASK                                                               0x0000FFFFL
#define GC_CAC_WEIGHT_TD_4__WEIGHT_TD_SIG9_MASK                                                               0xFFFF0000L
//GC_CAC_WEIGHT_TD_5
#define GC_CAC_WEIGHT_TD_5__WEIGHT_TD_SIG10__SHIFT                                                            0x0
#define GC_CAC_WEIGHT_TD_5__WEIGHT_TD_SIG10_MASK                                                              0x0000FFFFL
//GC_CAC_WEIGHT_RMI_0
#define GC_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG0__SHIFT                                                           0x0
#define GC_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG1__SHIFT                                                           0x10
#define GC_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG0_MASK                                                             0x0000FFFFL
#define GC_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG1_MASK                                                             0xFFFF0000L
//GC_CAC_WEIGHT_RMI_1
#define GC_CAC_WEIGHT_RMI_1__WEIGHT_RMI_SIG2__SHIFT                                                           0x0
#define GC_CAC_WEIGHT_RMI_1__WEIGHT_RMI_SIG3__SHIFT                                                           0x10
#define GC_CAC_WEIGHT_RMI_1__WEIGHT_RMI_SIG2_MASK                                                             0x0000FFFFL
#define GC_CAC_WEIGHT_RMI_1__WEIGHT_RMI_SIG3_MASK                                                             0xFFFF0000L
//GC_CAC_WEIGHT_EA_0
#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG0__SHIFT                                                             0x0
#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG1__SHIFT                                                             0x10
#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG0_MASK                                                               0x0000FFFFL
#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG1_MASK                                                               0xFFFF0000L
//GC_CAC_WEIGHT_EA_1
#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG2__SHIFT                                                             0x0
#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG3__SHIFT                                                             0x10
#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG2_MASK                                                               0x0000FFFFL
#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG3_MASK                                                               0xFFFF0000L
//GC_CAC_WEIGHT_EA_2
#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG4__SHIFT                                                             0x0
#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG5__SHIFT                                                             0x10
#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG4_MASK                                                               0x0000FFFFL
#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG5_MASK                                                               0xFFFF0000L
//GC_CAC_WEIGHT_UTCL2_ATCL2_0
#define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG0__SHIFT                                           0x0
#define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG1__SHIFT                                           0x10
#define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG0_MASK                                             0x0000FFFFL
#define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG1_MASK                                             0xFFFF0000L
//GC_CAC_WEIGHT_UTCL2_ATCL2_1
#define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG2__SHIFT                                           0x0
#define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG3__SHIFT                                           0x10
#define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG2_MASK                                             0x0000FFFFL
#define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG3_MASK                                             0xFFFF0000L
//GC_CAC_WEIGHT_UTCL2_ATCL2_2
#define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG4__SHIFT                                           0x0
#define GC_CAC_WEIGHT_UTCL2_ATCL2_2__UNUSED_0__SHIFT                                                          0x10
#define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG4_MASK                                             0x0000FFFFL
#define GC_CAC_WEIGHT_UTCL2_ATCL2_2__UNUSED_0_MASK                                                            0xFFFF0000L
//GC_CAC_WEIGHT_UTCL2_ROUTER_0
#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG0__SHIFT                                         0x0
#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG1__SHIFT                                         0x10
#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG0_MASK                                           0x0000FFFFL
#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG1_MASK                                           0xFFFF0000L
//GC_CAC_WEIGHT_UTCL2_ROUTER_1
#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG2__SHIFT                                         0x0
#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG3__SHIFT                                         0x10
#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG2_MASK                                           0x0000FFFFL
#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG3_MASK                                           0xFFFF0000L
//GC_CAC_WEIGHT_UTCL2_ROUTER_2
#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG4__SHIFT                                         0x0
#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG5__SHIFT                                         0x10
#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG4_MASK                                           0x0000FFFFL
#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG5_MASK                                           0xFFFF0000L
//GC_CAC_WEIGHT_UTCL2_ROUTER_3
#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG6__SHIFT                                         0x0
#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG7__SHIFT                                         0x10
#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG6_MASK                                           0x0000FFFFL
#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG7_MASK                                           0xFFFF0000L
//GC_CAC_WEIGHT_UTCL2_ROUTER_4
#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG8__SHIFT                                         0x0
#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG9__SHIFT                                         0x10
#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG8_MASK                                           0x0000FFFFL
#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG9_MASK                                           0xFFFF0000L
//GC_CAC_WEIGHT_UTCL2_VML2_0
#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG0__SHIFT                                             0x0
#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG1__SHIFT                                             0x10
#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG0_MASK                                               0x0000FFFFL
#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG1_MASK                                               0xFFFF0000L
//GC_CAC_WEIGHT_UTCL2_VML2_1
#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG2__SHIFT                                             0x0
#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG3__SHIFT                                             0x10
#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG2_MASK                                               0x0000FFFFL
#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG3_MASK                                               0xFFFF0000L
//GC_CAC_WEIGHT_UTCL2_VML2_2
#define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG4__SHIFT                                             0x0
#define GC_CAC_WEIGHT_UTCL2_VML2_2__UNUSED_0__SHIFT                                                           0x10
#define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG4_MASK                                               0x0000FFFFL
#define GC_CAC_WEIGHT_UTCL2_VML2_2__UNUSED_0_MASK                                                             0xFFFF0000L
//GC_CAC_WEIGHT_UTCL2_WALKER_0
#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG0__SHIFT                                         0x0
#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG1__SHIFT                                         0x10
#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG0_MASK                                           0x0000FFFFL
#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG1_MASK                                           0xFFFF0000L
//GC_CAC_WEIGHT_UTCL2_WALKER_1
#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG2__SHIFT                                         0x0
#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG3__SHIFT                                         0x10
#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG2_MASK                                           0x0000FFFFL
#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG3_MASK                                           0xFFFF0000L
//GC_CAC_WEIGHT_UTCL2_WALKER_2
#define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG4__SHIFT                                         0x0
#define GC_CAC_WEIGHT_UTCL2_WALKER_2__UNUSED_0__SHIFT                                                         0x10
#define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG4_MASK                                           0x0000FFFFL
#define GC_CAC_WEIGHT_UTCL2_WALKER_2__UNUSED_0_MASK                                                           0xFFFF0000L
//GC_CAC_WEIGHT_CU_0
#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0__SHIFT                                                             0x0
#define GC_CAC_WEIGHT_CU_0__UNUSED_0__SHIFT                                                                   0x10
#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0_MASK                                                               0x0000FFFFL
#define GC_CAC_WEIGHT_CU_0__UNUSED_0_MASK                                                                     0xFFFF0000L
//GC_CAC_WEIGHT_UTCL1_0
#define GC_CAC_WEIGHT_UTCL1_0__WEIGHT_UTCL1_SIG0__SHIFT                                                       0x0
#define GC_CAC_WEIGHT_UTCL1_0__WEIGHT_UTCL1_SIG0_MASK                                                         0x0000FFFFL
//GC_CAC_WEIGHT_GE_0
#define GC_CAC_WEIGHT_GE_0__WEIGHT_GE_SIG0__SHIFT                                                             0x0
#define GC_CAC_WEIGHT_GE_0__WEIGHT_GE_SIG1__SHIFT                                                             0x10
#define GC_CAC_WEIGHT_GE_0__WEIGHT_GE_SIG0_MASK                                                               0x0000FFFFL
#define GC_CAC_WEIGHT_GE_0__WEIGHT_GE_SIG1_MASK                                                               0xFFFF0000L
//GC_CAC_WEIGHT_GE_1
#define GC_CAC_WEIGHT_GE_1__WEIGHT_GE_SIG2__SHIFT                                                             0x0
#define GC_CAC_WEIGHT_GE_1__WEIGHT_GE_SIG3__SHIFT                                                             0x10
#define GC_CAC_WEIGHT_GE_1__WEIGHT_GE_SIG2_MASK                                                               0x0000FFFFL
#define GC_CAC_WEIGHT_GE_1__WEIGHT_GE_SIG3_MASK                                                               0xFFFF0000L
//GC_CAC_WEIGHT_GE_2
#define GC_CAC_WEIGHT_GE_2__WEIGHT_GE_SIG4__SHIFT                                                             0x0
#define GC_CAC_WEIGHT_GE_2__WEIGHT_GE_SIG5__SHIFT                                                             0x10
#define GC_CAC_WEIGHT_GE_2__WEIGHT_GE_SIG4_MASK                                                               0x0000FFFFL
#define GC_CAC_WEIGHT_GE_2__WEIGHT_GE_SIG5_MASK                                                               0xFFFF0000L
//GC_CAC_WEIGHT_GE_3
#define GC_CAC_WEIGHT_GE_3__WEIGHT_GE_SIG6__SHIFT                                                             0x0
#define GC_CAC_WEIGHT_GE_3__WEIGHT_GE_SIG7__SHIFT                                                             0x10
#define GC_CAC_WEIGHT_GE_3__WEIGHT_GE_SIG6_MASK                                                               0x0000FFFFL
#define GC_CAC_WEIGHT_GE_3__WEIGHT_GE_SIG7_MASK                                                               0xFFFF0000L
//GC_CAC_WEIGHT_GE_4
#define GC_CAC_WEIGHT_GE_4__WEIGHT_GE_SIG8__SHIFT                                                             0x0
#define GC_CAC_WEIGHT_GE_4__WEIGHT_GE_SIG9__SHIFT                                                             0x10
#define GC_CAC_WEIGHT_GE_4__WEIGHT_GE_SIG8_MASK                                                               0x0000FFFFL
#define GC_CAC_WEIGHT_GE_4__WEIGHT_GE_SIG9_MASK                                                               0xFFFF0000L
//GC_CAC_WEIGHT_GE_5
#define GC_CAC_WEIGHT_GE_5__WEIGHT_GE_SIG10__SHIFT                                                            0x0
#define GC_CAC_WEIGHT_GE_5__WEIGHT_GE_SIG11__SHIFT                                                            0x10
#define GC_CAC_WEIGHT_GE_5__WEIGHT_GE_SIG10_MASK                                                              0x0000FFFFL
#define GC_CAC_WEIGHT_GE_5__WEIGHT_GE_SIG11_MASK                                                              0xFFFF0000L
//GC_CAC_WEIGHT_GE_6
#define GC_CAC_WEIGHT_GE_6__WEIGHT_GE_SIG12__SHIFT                                                            0x0
#define GC_CAC_WEIGHT_GE_6__WEIGHT_GE_SIG13__SHIFT                                                            0x10
#define GC_CAC_WEIGHT_GE_6__WEIGHT_GE_SIG12_MASK                                                              0x0000FFFFL
#define GC_CAC_WEIGHT_GE_6__WEIGHT_GE_SIG13_MASK                                                              0xFFFF0000L
//GC_CAC_WEIGHT_GE_7
#define GC_CAC_WEIGHT_GE_7__WEIGHT_GE_SIG14__SHIFT                                                            0x0
#define GC_CAC_WEIGHT_GE_7__WEIGHT_GE_SIG15__SHIFT                                                            0x10
#define GC_CAC_WEIGHT_GE_7__WEIGHT_GE_SIG14_MASK                                                              0x0000FFFFL
#define GC_CAC_WEIGHT_GE_7__WEIGHT_GE_SIG15_MASK                                                              0xFFFF0000L
//GC_CAC_WEIGHT_GE_8
#define GC_CAC_WEIGHT_GE_8__WEIGHT_GE_SIG16__SHIFT                                                            0x0
#define GC_CAC_WEIGHT_GE_8__WEIGHT_GE_SIG17__SHIFT                                                            0x10
#define GC_CAC_WEIGHT_GE_8__WEIGHT_GE_SIG16_MASK                                                              0x0000FFFFL
#define GC_CAC_WEIGHT_GE_8__WEIGHT_GE_SIG17_MASK                                                              0xFFFF0000L
//GC_CAC_WEIGHT_GE_9
#define GC_CAC_WEIGHT_GE_9__WEIGHT_GE_SIG18__SHIFT                                                            0x0
#define GC_CAC_WEIGHT_GE_9__WEIGHT_GE_SIG19__SHIFT                                                            0x10
#define GC_CAC_WEIGHT_GE_9__WEIGHT_GE_SIG18_MASK                                                              0x0000FFFFL
#define GC_CAC_WEIGHT_GE_9__WEIGHT_GE_SIG19_MASK                                                              0xFFFF0000L
//GC_CAC_WEIGHT_GE_10
#define GC_CAC_WEIGHT_GE_10__WEIGHT_GE_SIG20__SHIFT                                                           0x0
#define GC_CAC_WEIGHT_GE_10__WEIGHT_GE_SIG20_MASK                                                             0x0000FFFFL
//GC_CAC_WEIGHT_PMM_0
#define GC_CAC_WEIGHT_PMM_0__WEIGHT_PMM_SIG0__SHIFT                                                           0x0
#define GC_CAC_WEIGHT_PMM_0__WEIGHT_PMM_SIG0_MASK                                                             0x0000FFFFL
//GC_CAC_WEIGHT_GL2C_0
#define GC_CAC_WEIGHT_GL2C_0__WEIGHT_GL2C_SIG0__SHIFT                                                         0x0
#define GC_CAC_WEIGHT_GL2C_0__WEIGHT_GL2C_SIG1__SHIFT                                                         0x10
#define GC_CAC_WEIGHT_GL2C_0__WEIGHT_GL2C_SIG0_MASK                                                           0x0000FFFFL
#define GC_CAC_WEIGHT_GL2C_0__WEIGHT_GL2C_SIG1_MASK                                                           0xFFFF0000L
//GC_CAC_WEIGHT_GL2C_1
#define GC_CAC_WEIGHT_GL2C_1__WEIGHT_GL2C_SIG2__SHIFT                                                         0x0
#define GC_CAC_WEIGHT_GL2C_1__WEIGHT_GL2C_SIG3__SHIFT                                                         0x10
#define GC_CAC_WEIGHT_GL2C_1__WEIGHT_GL2C_SIG2_MASK                                                           0x0000FFFFL
#define GC_CAC_WEIGHT_GL2C_1__WEIGHT_GL2C_SIG3_MASK                                                           0xFFFF0000L
//GC_CAC_WEIGHT_GL2C_2
#define GC_CAC_WEIGHT_GL2C_2__WEIGHT_GL2C_SIG4__SHIFT                                                         0x0
#define GC_CAC_WEIGHT_GL2C_2__WEIGHT_GL2C_SIG4_MASK                                                           0x0000FFFFL
//GC_CAC_WEIGHT_GUS_0
#define GC_CAC_WEIGHT_GUS_0__WEIGHT_GUS_SIG0__SHIFT                                                           0x0
#define GC_CAC_WEIGHT_GUS_0__WEIGHT_GUS_SIG1__SHIFT                                                           0x10
#define GC_CAC_WEIGHT_GUS_0__WEIGHT_GUS_SIG0_MASK                                                             0x0000FFFFL
#define GC_CAC_WEIGHT_GUS_0__WEIGHT_GUS_SIG1_MASK                                                             0xFFFF0000L
//GC_CAC_WEIGHT_GUS_1
#define GC_CAC_WEIGHT_GUS_1__WEIGHT_GUS_SIG2__SHIFT                                                           0x0
#define GC_CAC_WEIGHT_GUS_1__WEIGHT_GUS_SIG2_MASK                                                             0x0000FFFFL
//GC_CAC_WEIGHT_PH_0
#define GC_CAC_WEIGHT_PH_0__WEIGHT_PH_SIG0__SHIFT                                                             0x0
#define GC_CAC_WEIGHT_PH_0__WEIGHT_PH_SIG1__SHIFT                                                             0x10
#define GC_CAC_WEIGHT_PH_0__WEIGHT_PH_SIG0_MASK                                                               0x0000FFFFL
#define GC_CAC_WEIGHT_PH_0__WEIGHT_PH_SIG1_MASK                                                               0xFFFF0000L
//GC_CAC_WEIGHT_PH_1
#define GC_CAC_WEIGHT_PH_1__WEIGHT_PH_SIG2__SHIFT                                                             0x0
#define GC_CAC_WEIGHT_PH_1__WEIGHT_PH_SIG3__SHIFT                                                             0x10
#define GC_CAC_WEIGHT_PH_1__WEIGHT_PH_SIG2_MASK                                                               0x0000FFFFL
#define GC_CAC_WEIGHT_PH_1__WEIGHT_PH_SIG3_MASK                                                               0xFFFF0000L
//GC_CAC_WEIGHT_PH_2
#define GC_CAC_WEIGHT_PH_2__WEIGHT_PH_SIG4__SHIFT                                                             0x0
#define GC_CAC_WEIGHT_PH_2__WEIGHT_PH_SIG5__SHIFT                                                             0x10
#define GC_CAC_WEIGHT_PH_2__WEIGHT_PH_SIG4_MASK                                                               0x0000FFFFL
#define GC_CAC_WEIGHT_PH_2__WEIGHT_PH_SIG5_MASK                                                               0xFFFF0000L
//GC_CAC_WEIGHT_PH_3
#define GC_CAC_WEIGHT_PH_3__WEIGHT_PH_SIG6__SHIFT                                                             0x0
#define GC_CAC_WEIGHT_PH_3__WEIGHT_PH_SIG7__SHIFT                                                             0x10
#define GC_CAC_WEIGHT_PH_3__WEIGHT_PH_SIG6_MASK                                                               0x0000FFFFL
#define GC_CAC_WEIGHT_PH_3__WEIGHT_PH_SIG7_MASK                                                               0xFFFF0000L
//GC_CAC_WEIGHT_SDMA_0
#define GC_CAC_WEIGHT_SDMA_0__WEIGHT_SDMA_SIG0__SHIFT                                                         0x0
#define GC_CAC_WEIGHT_SDMA_0__WEIGHT_SDMA_SIG1__SHIFT                                                         0x10
#define GC_CAC_WEIGHT_SDMA_0__WEIGHT_SDMA_SIG0_MASK                                                           0x0000FFFFL
#define GC_CAC_WEIGHT_SDMA_0__WEIGHT_SDMA_SIG1_MASK                                                           0xFFFF0000L
//GC_CAC_WEIGHT_SDMA_1
#define GC_CAC_WEIGHT_SDMA_1__WEIGHT_SDMA_SIG2__SHIFT                                                         0x0
#define GC_CAC_WEIGHT_SDMA_1__WEIGHT_SDMA_SIG3__SHIFT                                                         0x10
#define GC_CAC_WEIGHT_SDMA_1__WEIGHT_SDMA_SIG2_MASK                                                           0x0000FFFFL
#define GC_CAC_WEIGHT_SDMA_1__WEIGHT_SDMA_SIG3_MASK                                                           0xFFFF0000L
//GC_CAC_WEIGHT_SDMA_2
#define GC_CAC_WEIGHT_SDMA_2__WEIGHT_SDMA_SIG4__SHIFT                                                         0x0
#define GC_CAC_WEIGHT_SDMA_2__WEIGHT_SDMA_SIG5__SHIFT                                                         0x10
#define GC_CAC_WEIGHT_SDMA_2__WEIGHT_SDMA_SIG4_MASK                                                           0x0000FFFFL
#define GC_CAC_WEIGHT_SDMA_2__WEIGHT_SDMA_SIG5_MASK                                                           0xFFFF0000L
//GC_CAC_WEIGHT_SDMA_3
#define GC_CAC_WEIGHT_SDMA_3__WEIGHT_SDMA_SIG6__SHIFT                                                         0x0
#define GC_CAC_WEIGHT_SDMA_3__WEIGHT_SDMA_SIG7__SHIFT                                                         0x10
#define GC_CAC_WEIGHT_SDMA_3__WEIGHT_SDMA_SIG6_MASK                                                           0x0000FFFFL
#define GC_CAC_WEIGHT_SDMA_3__WEIGHT_SDMA_SIG7_MASK                                                           0xFFFF0000L
//GC_CAC_WEIGHT_SDMA_4
#define GC_CAC_WEIGHT_SDMA_4__WEIGHT_SDMA_SIG8__SHIFT                                                         0x0
#define GC_CAC_WEIGHT_SDMA_4__WEIGHT_SDMA_SIG9__SHIFT                                                         0x10
#define GC_CAC_WEIGHT_SDMA_4__WEIGHT_SDMA_SIG8_MASK                                                           0x0000FFFFL
#define GC_CAC_WEIGHT_SDMA_4__WEIGHT_SDMA_SIG9_MASK                                                           0xFFFF0000L
//GC_CAC_WEIGHT_SDMA_5
#define GC_CAC_WEIGHT_SDMA_5__WEIGHT_SDMA_SIG10__SHIFT                                                        0x0
#define GC_CAC_WEIGHT_SDMA_5__WEIGHT_SDMA_SIG11__SHIFT                                                        0x10
#define GC_CAC_WEIGHT_SDMA_5__WEIGHT_SDMA_SIG10_MASK                                                          0x0000FFFFL
#define GC_CAC_WEIGHT_SDMA_5__WEIGHT_SDMA_SIG11_MASK                                                          0xFFFF0000L
//GC_CAC_WEIGHT_SP_0
#define GC_CAC_WEIGHT_SP_0__WEIGHT_SP_SIG0__SHIFT                                                             0x0
#define GC_CAC_WEIGHT_SP_0__WEIGHT_SP_SIG1__SHIFT                                                             0x10
#define GC_CAC_WEIGHT_SP_0__WEIGHT_SP_SIG0_MASK                                                               0x0000FFFFL
#define GC_CAC_WEIGHT_SP_0__WEIGHT_SP_SIG1_MASK                                                               0xFFFF0000L
//GC_CAC_WEIGHT_SP_1
#define GC_CAC_WEIGHT_SP_1__WEIGHT_SP_SIG2__SHIFT                                                             0x0
#define GC_CAC_WEIGHT_SP_1__WEIGHT_SP_SIG2_MASK                                                               0x0000FFFFL
//GC_CAC_WEIGHT_GL1C_0
#define GC_CAC_WEIGHT_GL1C_0__WEIGHT_GL1C_SIG0__SHIFT                                                         0x0
#define GC_CAC_WEIGHT_GL1C_0__WEIGHT_GL1C_SIG1__SHIFT                                                         0x10
#define GC_CAC_WEIGHT_GL1C_0__WEIGHT_GL1C_SIG0_MASK                                                           0x0000FFFFL
#define GC_CAC_WEIGHT_GL1C_0__WEIGHT_GL1C_SIG1_MASK                                                           0xFFFF0000L
//GC_CAC_WEIGHT_GL1C_1
#define GC_CAC_WEIGHT_GL1C_1__WEIGHT_GL1C_SIG2__SHIFT                                                         0x0
#define GC_CAC_WEIGHT_GL1C_1__WEIGHT_GL1C_SIG3__SHIFT                                                         0x10
#define GC_CAC_WEIGHT_GL1C_1__WEIGHT_GL1C_SIG2_MASK                                                           0x0000FFFFL
#define GC_CAC_WEIGHT_GL1C_1__WEIGHT_GL1C_SIG3_MASK                                                           0xFFFF0000L
//GC_CAC_WEIGHT_GL1C_2
#define GC_CAC_WEIGHT_GL1C_2__WEIGHT_GL1C_SIG4__SHIFT                                                         0x0
#define GC_CAC_WEIGHT_GL1C_2__WEIGHT_GL1C_SIG4_MASK                                                           0x0000FFFFL
//GC_CAC_WEIGHT_CHC_0
#define GC_CAC_WEIGHT_CHC_0__WEIGHT_CHC_SIG0__SHIFT                                                           0x0
#define GC_CAC_WEIGHT_CHC_0__WEIGHT_CHC_SIG1__SHIFT                                                           0x10
#define GC_CAC_WEIGHT_CHC_0__WEIGHT_CHC_SIG0_MASK                                                             0x0000FFFFL
#define GC_CAC_WEIGHT_CHC_0__WEIGHT_CHC_SIG1_MASK                                                             0xFFFF0000L
//GC_CAC_WEIGHT_CHC_1
#define GC_CAC_WEIGHT_CHC_1__WEIGHT_CHC_SIG2__SHIFT                                                           0x0
#define GC_CAC_WEIGHT_CHC_1__WEIGHT_CHC_SIG2_MASK                                                             0x0000FFFFL
//GC_CAC_WEIGHT_SQC_0
#define GC_CAC_WEIGHT_SQC_0__WEIGHT_SQC_SIG0__SHIFT                                                           0x0
#define GC_CAC_WEIGHT_SQC_0__WEIGHT_SQC_SIG1__SHIFT                                                           0x10
#define GC_CAC_WEIGHT_SQC_0__WEIGHT_SQC_SIG0_MASK                                                             0x0000FFFFL
#define GC_CAC_WEIGHT_SQC_0__WEIGHT_SQC_SIG1_MASK                                                             0xFFFF0000L
//GC_CAC_WEIGHT_SQC_1
#define GC_CAC_WEIGHT_SQC_1__WEIGHT_SQC_SIG2__SHIFT                                                           0x0
#define GC_CAC_WEIGHT_SQC_1__WEIGHT_SQC_SIG2_MASK                                                             0x0000FFFFL
//GC_CAC_WEIGHT_RLC_0
#define GC_CAC_WEIGHT_RLC_0__WEIGHT_RLC_SIG0__SHIFT                                                           0x0
#define GC_CAC_WEIGHT_RLC_0__WEIGHT_RLC_SIG0_MASK                                                             0x0000FFFFL
//GC_CAC_ACC_LDS0
#define GC_CAC_ACC_LDS0__ACCUMULATOR_31_0__SHIFT                                                              0x0
#define GC_CAC_ACC_LDS0__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
//GC_CAC_ACC_LDS1
#define GC_CAC_ACC_LDS1__ACCUMULATOR_31_0__SHIFT                                                              0x0
#define GC_CAC_ACC_LDS1__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
//GC_CAC_ACC_LDS2
#define GC_CAC_ACC_LDS2__ACCUMULATOR_31_0__SHIFT                                                              0x0
#define GC_CAC_ACC_LDS2__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
//GC_CAC_ACC_LDS3
#define GC_CAC_ACC_LDS3__ACCUMULATOR_31_0__SHIFT                                                              0x0
#define GC_CAC_ACC_LDS3__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
//GC_CAC_ACC_LDS4
#define GC_CAC_ACC_LDS4__ACCUMULATOR_31_0__SHIFT                                                              0x0
#define GC_CAC_ACC_LDS4__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
//GC_CAC_ACC_LDS5
#define GC_CAC_ACC_LDS5__ACCUMULATOR_31_0__SHIFT                                                              0x0
#define GC_CAC_ACC_LDS5__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
//GC_CAC_ACC_LDS6
#define GC_CAC_ACC_LDS6__ACCUMULATOR_31_0__SHIFT                                                              0x0
#define GC_CAC_ACC_LDS6__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
//GC_CAC_ACC_LDS7
#define GC_CAC_ACC_LDS7__ACCUMULATOR_31_0__SHIFT                                                              0x0
#define GC_CAC_ACC_LDS7__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
//GC_CAC_ACC_LDS8
#define GC_CAC_ACC_LDS8__ACCUMULATOR_31_0__SHIFT                                                              0x0
#define GC_CAC_ACC_LDS8__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
//GC_CAC_ACC_BCI0
#define GC_CAC_ACC_BCI0__ACCUMULATOR_31_0__SHIFT                                                              0x0
#define GC_CAC_ACC_BCI0__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
//GC_CAC_ACC_BCI1
#define GC_CAC_ACC_BCI1__ACCUMULATOR_31_0__SHIFT                                                              0x0
#define GC_CAC_ACC_BCI1__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
//GC_CAC_ACC_CB0
#define GC_CAC_ACC_CB0__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_CB0__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_CB1
#define GC_CAC_ACC_CB1__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_CB1__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_CB2
#define GC_CAC_ACC_CB2__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_CB2__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_CB3
#define GC_CAC_ACC_CB3__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_CB3__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_CB4
#define GC_CAC_ACC_CB4__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_CB4__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_CB5
#define GC_CAC_ACC_CB5__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_CB5__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_CB6
#define GC_CAC_ACC_CB6__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_CB6__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_CB7
#define GC_CAC_ACC_CB7__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_CB7__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_CB8
#define GC_CAC_ACC_CB8__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_CB8__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_CB9
#define GC_CAC_ACC_CB9__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_CB9__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_CP0
#define GC_CAC_ACC_CP0__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_CP0__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_CP1
#define GC_CAC_ACC_CP1__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_CP1__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_CP2
#define GC_CAC_ACC_CP2__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_CP2__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_DB0
#define GC_CAC_ACC_DB0__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_DB0__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_DB1
#define GC_CAC_ACC_DB1__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_DB1__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_DB2
#define GC_CAC_ACC_DB2__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_DB2__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_DB3
#define GC_CAC_ACC_DB3__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_DB3__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_DB4
#define GC_CAC_ACC_DB4__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_DB4__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_DB5
#define GC_CAC_ACC_DB5__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_DB5__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_DB6
#define GC_CAC_ACC_DB6__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_DB6__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_DB7
#define GC_CAC_ACC_DB7__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_DB7__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_DB8
#define GC_CAC_ACC_DB8__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_DB8__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_DB9
#define GC_CAC_ACC_DB9__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_DB9__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_GDS0
#define GC_CAC_ACC_GDS0__ACCUMULATOR_31_0__SHIFT                                                              0x0
#define GC_CAC_ACC_GDS0__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
//GC_CAC_ACC_GDS1
#define GC_CAC_ACC_GDS1__ACCUMULATOR_31_0__SHIFT                                                              0x0
#define GC_CAC_ACC_GDS1__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
//GC_CAC_ACC_GDS2
#define GC_CAC_ACC_GDS2__ACCUMULATOR_31_0__SHIFT                                                              0x0
#define GC_CAC_ACC_GDS2__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
//GC_CAC_ACC_GDS3
#define GC_CAC_ACC_GDS3__ACCUMULATOR_31_0__SHIFT                                                              0x0
#define GC_CAC_ACC_GDS3__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
//GC_CAC_ACC_GDS4
#define GC_CAC_ACC_GDS4__ACCUMULATOR_31_0__SHIFT                                                              0x0
#define GC_CAC_ACC_GDS4__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
//GC_CAC_ACC_GDS5
#define GC_CAC_ACC_GDS5__ACCUMULATOR_31_0__SHIFT                                                              0x0
#define GC_CAC_ACC_GDS5__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
//GC_CAC_ACC_GDS6
#define GC_CAC_ACC_GDS6__ACCUMULATOR_31_0__SHIFT                                                              0x0
#define GC_CAC_ACC_GDS6__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
//GC_CAC_ACC_PA0
#define GC_CAC_ACC_PA0__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_PA0__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_PA1
#define GC_CAC_ACC_PA1__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_PA1__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_PA2
#define GC_CAC_ACC_PA2__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_PA2__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_PA3
#define GC_CAC_ACC_PA3__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_PA3__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_PA4
#define GC_CAC_ACC_PA4__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_PA4__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_PA5
#define GC_CAC_ACC_PA5__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_PA5__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_PA6
#define GC_CAC_ACC_PA6__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_PA6__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_PA7
#define GC_CAC_ACC_PA7__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_PA7__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_PC0
#define GC_CAC_ACC_PC0__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_PC0__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_SC0
#define GC_CAC_ACC_SC0__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_SC0__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_SC1
#define GC_CAC_ACC_SC1__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_SC1__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_SC2
#define GC_CAC_ACC_SC2__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_SC2__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_SC3
#define GC_CAC_ACC_SC3__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_SC3__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_SC4
#define GC_CAC_ACC_SC4__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_SC4__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_SC5
#define GC_CAC_ACC_SC5__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_SC5__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_SC6
#define GC_CAC_ACC_SC6__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_SC6__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_SC7
#define GC_CAC_ACC_SC7__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_SC7__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_SPI0
#define GC_CAC_ACC_SPI0__ACCUMULATOR_31_0__SHIFT                                                              0x0
#define GC_CAC_ACC_SPI0__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
//GC_CAC_ACC_SPI1
#define GC_CAC_ACC_SPI1__ACCUMULATOR_31_0__SHIFT                                                              0x0
#define GC_CAC_ACC_SPI1__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
//GC_CAC_ACC_SPI2
#define GC_CAC_ACC_SPI2__ACCUMULATOR_31_0__SHIFT                                                              0x0
#define GC_CAC_ACC_SPI2__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
//GC_CAC_ACC_SPI3
#define GC_CAC_ACC_SPI3__ACCUMULATOR_31_0__SHIFT                                                              0x0
#define GC_CAC_ACC_SPI3__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
//GC_CAC_ACC_SPI4
#define GC_CAC_ACC_SPI4__ACCUMULATOR_31_0__SHIFT                                                              0x0
#define GC_CAC_ACC_SPI4__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
//GC_CAC_ACC_SPI5
#define GC_CAC_ACC_SPI5__ACCUMULATOR_31_0__SHIFT                                                              0x0
#define GC_CAC_ACC_SPI5__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
//GC_CAC_ACC_SQ0_LOWER
#define GC_CAC_ACC_SQ0_LOWER__ACCUMULATOR_31_0__SHIFT                                                         0x0
#define GC_CAC_ACC_SQ0_LOWER__ACCUMULATOR_31_0_MASK                                                           0xFFFFFFFFL
//GC_CAC_ACC_SQ0_UPPER
#define GC_CAC_ACC_SQ0_UPPER__ACCUMULATOR_39_32__SHIFT                                                        0x0
#define GC_CAC_ACC_SQ0_UPPER__UNUSED_0__SHIFT                                                                 0x8
#define GC_CAC_ACC_SQ0_UPPER__ACCUMULATOR_39_32_MASK                                                          0x000000FFL
#define GC_CAC_ACC_SQ0_UPPER__UNUSED_0_MASK                                                                   0xFFFFFF00L
//GC_CAC_ACC_SQ1_LOWER
#define GC_CAC_ACC_SQ1_LOWER__ACCUMULATOR_31_0__SHIFT                                                         0x0
#define GC_CAC_ACC_SQ1_LOWER__ACCUMULATOR_31_0_MASK                                                           0xFFFFFFFFL
//GC_CAC_ACC_SQ1_UPPER
#define GC_CAC_ACC_SQ1_UPPER__ACCUMULATOR_39_32__SHIFT                                                        0x0
#define GC_CAC_ACC_SQ1_UPPER__UNUSED_0__SHIFT                                                                 0x8
#define GC_CAC_ACC_SQ1_UPPER__ACCUMULATOR_39_32_MASK                                                          0x000000FFL
#define GC_CAC_ACC_SQ1_UPPER__UNUSED_0_MASK                                                                   0xFFFFFF00L
//GC_CAC_ACC_SQ2_LOWER
#define GC_CAC_ACC_SQ2_LOWER__ACCUMULATOR_31_0__SHIFT                                                         0x0
#define GC_CAC_ACC_SQ2_LOWER__ACCUMULATOR_31_0_MASK                                                           0xFFFFFFFFL
//GC_CAC_ACC_SQ2_UPPER
#define GC_CAC_ACC_SQ2_UPPER__ACCUMULATOR_39_32__SHIFT                                                        0x0
#define GC_CAC_ACC_SQ2_UPPER__UNUSED_0__SHIFT                                                                 0x8
#define GC_CAC_ACC_SQ2_UPPER__ACCUMULATOR_39_32_MASK                                                          0x000000FFL
#define GC_CAC_ACC_SQ2_UPPER__UNUSED_0_MASK                                                                   0xFFFFFF00L
//GC_CAC_ACC_SQ3_LOWER
#define GC_CAC_ACC_SQ3_LOWER__ACCUMULATOR_31_0__SHIFT                                                         0x0
#define GC_CAC_ACC_SQ3_LOWER__ACCUMULATOR_31_0_MASK                                                           0xFFFFFFFFL
//GC_CAC_ACC_SQ3_UPPER
#define GC_CAC_ACC_SQ3_UPPER__ACCUMULATOR_39_32__SHIFT                                                        0x0
#define GC_CAC_ACC_SQ3_UPPER__UNUSED_0__SHIFT                                                                 0x8
#define GC_CAC_ACC_SQ3_UPPER__ACCUMULATOR_39_32_MASK                                                          0x000000FFL
#define GC_CAC_ACC_SQ3_UPPER__UNUSED_0_MASK                                                                   0xFFFFFF00L
//GC_CAC_ACC_SQ4_LOWER
#define GC_CAC_ACC_SQ4_LOWER__ACCUMULATOR_31_0__SHIFT                                                         0x0
#define GC_CAC_ACC_SQ4_LOWER__ACCUMULATOR_31_0_MASK                                                           0xFFFFFFFFL
//GC_CAC_ACC_SQ4_UPPER
#define GC_CAC_ACC_SQ4_UPPER__ACCUMULATOR_39_32__SHIFT                                                        0x0
#define GC_CAC_ACC_SQ4_UPPER__UNUSED_0__SHIFT                                                                 0x8
#define GC_CAC_ACC_SQ4_UPPER__ACCUMULATOR_39_32_MASK                                                          0x000000FFL
#define GC_CAC_ACC_SQ4_UPPER__UNUSED_0_MASK                                                                   0xFFFFFF00L
//GC_CAC_ACC_SQ5_LOWER
#define GC_CAC_ACC_SQ5_LOWER__ACCUMULATOR_31_0__SHIFT                                                         0x0
#define GC_CAC_ACC_SQ5_LOWER__ACCUMULATOR_31_0_MASK                                                           0xFFFFFFFFL
//GC_CAC_ACC_SQ5_UPPER
#define GC_CAC_ACC_SQ5_UPPER__ACCUMULATOR_39_32__SHIFT                                                        0x0
#define GC_CAC_ACC_SQ5_UPPER__UNUSED_0__SHIFT                                                                 0x8
#define GC_CAC_ACC_SQ5_UPPER__ACCUMULATOR_39_32_MASK                                                          0x000000FFL
#define GC_CAC_ACC_SQ5_UPPER__UNUSED_0_MASK                                                                   0xFFFFFF00L
//GC_CAC_ACC_SQ6_LOWER
#define GC_CAC_ACC_SQ6_LOWER__ACCUMULATOR_31_0__SHIFT                                                         0x0
#define GC_CAC_ACC_SQ6_LOWER__ACCUMULATOR_31_0_MASK                                                           0xFFFFFFFFL
//GC_CAC_ACC_SQ6_UPPER
#define GC_CAC_ACC_SQ6_UPPER__ACCUMULATOR_39_32__SHIFT                                                        0x0
#define GC_CAC_ACC_SQ6_UPPER__UNUSED_0__SHIFT                                                                 0x8
#define GC_CAC_ACC_SQ6_UPPER__ACCUMULATOR_39_32_MASK                                                          0x000000FFL
#define GC_CAC_ACC_SQ6_UPPER__UNUSED_0_MASK                                                                   0xFFFFFF00L
//GC_CAC_ACC_SQ7_LOWER
#define GC_CAC_ACC_SQ7_LOWER__ACCUMULATOR_31_0__SHIFT                                                         0x0
#define GC_CAC_ACC_SQ7_LOWER__ACCUMULATOR_31_0_MASK                                                           0xFFFFFFFFL
//GC_CAC_ACC_SQ7_UPPER
#define GC_CAC_ACC_SQ7_UPPER__ACCUMULATOR_39_32__SHIFT                                                        0x0
#define GC_CAC_ACC_SQ7_UPPER__UNUSED_0__SHIFT                                                                 0x8
#define GC_CAC_ACC_SQ7_UPPER__ACCUMULATOR_39_32_MASK                                                          0x000000FFL
#define GC_CAC_ACC_SQ7_UPPER__UNUSED_0_MASK                                                                   0xFFFFFF00L
//GC_CAC_ACC_SQ8_LOWER
#define GC_CAC_ACC_SQ8_LOWER__ACCUMULATOR_31_0__SHIFT                                                         0x0
#define GC_CAC_ACC_SQ8_LOWER__ACCUMULATOR_31_0_MASK                                                           0xFFFFFFFFL
//GC_CAC_ACC_SQ8_UPPER
#define GC_CAC_ACC_SQ8_UPPER__ACCUMULATOR_39_32__SHIFT                                                        0x0
#define GC_CAC_ACC_SQ8_UPPER__UNUSED_0__SHIFT                                                                 0x8
#define GC_CAC_ACC_SQ8_UPPER__ACCUMULATOR_39_32_MASK                                                          0x000000FFL
#define GC_CAC_ACC_SQ8_UPPER__UNUSED_0_MASK                                                                   0xFFFFFF00L
//GC_CAC_ACC_SX0
#define GC_CAC_ACC_SX0__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_SX0__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_SXRB0
#define GC_CAC_ACC_SXRB0__ACCUMULATOR_31_0__SHIFT                                                             0x0
#define GC_CAC_ACC_SXRB0__ACCUMULATOR_31_0_MASK                                                               0xFFFFFFFFL
//GC_CAC_ACC_TA0
#define GC_CAC_ACC_TA0__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_TA0__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_TCP0
#define GC_CAC_ACC_TCP0__ACCUMULATOR_31_0__SHIFT                                                              0x0
#define GC_CAC_ACC_TCP0__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
//GC_CAC_ACC_TCP1
#define GC_CAC_ACC_TCP1__ACCUMULATOR_31_0__SHIFT                                                              0x0
#define GC_CAC_ACC_TCP1__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
//GC_CAC_ACC_TCP2
#define GC_CAC_ACC_TCP2__ACCUMULATOR_31_0__SHIFT                                                              0x0
#define GC_CAC_ACC_TCP2__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
//GC_CAC_ACC_TCP3
#define GC_CAC_ACC_TCP3__ACCUMULATOR_31_0__SHIFT                                                              0x0
#define GC_CAC_ACC_TCP3__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
//GC_CAC_ACC_TCP4
#define GC_CAC_ACC_TCP4__ACCUMULATOR_31_0__SHIFT                                                              0x0
#define GC_CAC_ACC_TCP4__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
//GC_CAC_ACC_TCP5
#define GC_CAC_ACC_TCP5__ACCUMULATOR_31_0__SHIFT                                                              0x0
#define GC_CAC_ACC_TCP5__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
//GC_CAC_ACC_TCP6
#define GC_CAC_ACC_TCP6__ACCUMULATOR_31_0__SHIFT                                                              0x0
#define GC_CAC_ACC_TCP6__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
//GC_CAC_ACC_TCP7
#define GC_CAC_ACC_TCP7__ACCUMULATOR_31_0__SHIFT                                                              0x0
#define GC_CAC_ACC_TCP7__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
//GC_CAC_ACC_TD0
#define GC_CAC_ACC_TD0__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_TD0__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_TD1
#define GC_CAC_ACC_TD1__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_TD1__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_TD2
#define GC_CAC_ACC_TD2__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_TD2__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_TD3
#define GC_CAC_ACC_TD3__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_TD3__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_TD4
#define GC_CAC_ACC_TD4__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_TD4__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_TD5
#define GC_CAC_ACC_TD5__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_TD5__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_TD6
#define GC_CAC_ACC_TD6__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_TD6__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_TD7
#define GC_CAC_ACC_TD7__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_TD7__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_TD8
#define GC_CAC_ACC_TD8__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_TD8__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_TD9
#define GC_CAC_ACC_TD9__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_TD9__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_TD10
#define GC_CAC_ACC_TD10__ACCUMULATOR_31_0__SHIFT                                                              0x0
#define GC_CAC_ACC_TD10__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
//GC_CAC_ACC_RMI0
#define GC_CAC_ACC_RMI0__ACCUMULATOR_31_0__SHIFT                                                              0x0
#define GC_CAC_ACC_RMI0__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
//GC_CAC_ACC_RMI1
#define GC_CAC_ACC_RMI1__ACCUMULATOR_31_0__SHIFT                                                              0x0
#define GC_CAC_ACC_RMI1__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
//GC_CAC_ACC_RMI2
#define GC_CAC_ACC_RMI2__ACCUMULATOR_31_0__SHIFT                                                              0x0
#define GC_CAC_ACC_RMI2__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
//GC_CAC_ACC_RMI3
#define GC_CAC_ACC_RMI3__ACCUMULATOR_31_0__SHIFT                                                              0x0
#define GC_CAC_ACC_RMI3__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
//GC_CAC_ACC_EA0
#define GC_CAC_ACC_EA0__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_EA0__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_EA1
#define GC_CAC_ACC_EA1__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_EA1__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_EA2
#define GC_CAC_ACC_EA2__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_EA2__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_EA3
#define GC_CAC_ACC_EA3__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_EA3__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_EA4
#define GC_CAC_ACC_EA4__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_EA4__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_EA5
#define GC_CAC_ACC_EA5__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_EA5__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_UTCL2_ATCL20
#define GC_CAC_ACC_UTCL2_ATCL20__ACCUMULATOR_31_0__SHIFT                                                      0x0
#define GC_CAC_ACC_UTCL2_ATCL20__ACCUMULATOR_31_0_MASK                                                        0xFFFFFFFFL
//GC_CAC_ACC_UTCL2_ATCL21
#define GC_CAC_ACC_UTCL2_ATCL21__ACCUMULATOR_31_0__SHIFT                                                      0x0
#define GC_CAC_ACC_UTCL2_ATCL21__ACCUMULATOR_31_0_MASK                                                        0xFFFFFFFFL
//GC_CAC_ACC_UTCL2_ATCL22
#define GC_CAC_ACC_UTCL2_ATCL22__ACCUMULATOR_31_0__SHIFT                                                      0x0
#define GC_CAC_ACC_UTCL2_ATCL22__ACCUMULATOR_31_0_MASK                                                        0xFFFFFFFFL
//GC_CAC_ACC_UTCL2_ATCL23
#define GC_CAC_ACC_UTCL2_ATCL23__ACCUMULATOR_31_0__SHIFT                                                      0x0
#define GC_CAC_ACC_UTCL2_ATCL23__ACCUMULATOR_31_0_MASK                                                        0xFFFFFFFFL
//GC_CAC_ACC_UTCL2_ATCL24
#define GC_CAC_ACC_UTCL2_ATCL24__ACCUMULATOR_31_0__SHIFT                                                      0x0
#define GC_CAC_ACC_UTCL2_ATCL24__ACCUMULATOR_31_0_MASK                                                        0xFFFFFFFFL
//GC_CAC_ACC_UTCL2_ROUTER0
#define GC_CAC_ACC_UTCL2_ROUTER0__ACCUMULATOR_31_0__SHIFT                                                     0x0
#define GC_CAC_ACC_UTCL2_ROUTER0__ACCUMULATOR_31_0_MASK                                                       0xFFFFFFFFL
//GC_CAC_ACC_UTCL2_ROUTER1
#define GC_CAC_ACC_UTCL2_ROUTER1__ACCUMULATOR_31_0__SHIFT                                                     0x0
#define GC_CAC_ACC_UTCL2_ROUTER1__ACCUMULATOR_31_0_MASK                                                       0xFFFFFFFFL
//GC_CAC_ACC_UTCL2_ROUTER2
#define GC_CAC_ACC_UTCL2_ROUTER2__ACCUMULATOR_31_0__SHIFT                                                     0x0
#define GC_CAC_ACC_UTCL2_ROUTER2__ACCUMULATOR_31_0_MASK                                                       0xFFFFFFFFL
//GC_CAC_ACC_UTCL2_ROUTER3
#define GC_CAC_ACC_UTCL2_ROUTER3__ACCUMULATOR_31_0__SHIFT                                                     0x0
#define GC_CAC_ACC_UTCL2_ROUTER3__ACCUMULATOR_31_0_MASK                                                       0xFFFFFFFFL
//GC_CAC_ACC_UTCL2_ROUTER4
#define GC_CAC_ACC_UTCL2_ROUTER4__ACCUMULATOR_31_0__SHIFT                                                     0x0
#define GC_CAC_ACC_UTCL2_ROUTER4__ACCUMULATOR_31_0_MASK                                                       0xFFFFFFFFL
//GC_CAC_ACC_UTCL2_ROUTER5
#define GC_CAC_ACC_UTCL2_ROUTER5__ACCUMULATOR_31_0__SHIFT                                                     0x0
#define GC_CAC_ACC_UTCL2_ROUTER5__ACCUMULATOR_31_0_MASK                                                       0xFFFFFFFFL
//GC_CAC_ACC_UTCL2_ROUTER6
#define GC_CAC_ACC_UTCL2_ROUTER6__ACCUMULATOR_31_0__SHIFT                                                     0x0
#define GC_CAC_ACC_UTCL2_ROUTER6__ACCUMULATOR_31_0_MASK                                                       0xFFFFFFFFL
//GC_CAC_ACC_UTCL2_ROUTER7
#define GC_CAC_ACC_UTCL2_ROUTER7__ACCUMULATOR_31_0__SHIFT                                                     0x0
#define GC_CAC_ACC_UTCL2_ROUTER7__ACCUMULATOR_31_0_MASK                                                       0xFFFFFFFFL
//GC_CAC_ACC_UTCL2_ROUTER8
#define GC_CAC_ACC_UTCL2_ROUTER8__ACCUMULATOR_31_0__SHIFT                                                     0x0
#define GC_CAC_ACC_UTCL2_ROUTER8__ACCUMULATOR_31_0_MASK                                                       0xFFFFFFFFL
//GC_CAC_ACC_UTCL2_ROUTER9
#define GC_CAC_ACC_UTCL2_ROUTER9__ACCUMULATOR_31_0__SHIFT                                                     0x0
#define GC_CAC_ACC_UTCL2_ROUTER9__ACCUMULATOR_31_0_MASK                                                       0xFFFFFFFFL
//GC_CAC_ACC_UTCL2_VML20
#define GC_CAC_ACC_UTCL2_VML20__ACCUMULATOR_31_0__SHIFT                                                       0x0
#define GC_CAC_ACC_UTCL2_VML20__ACCUMULATOR_31_0_MASK                                                         0xFFFFFFFFL
//GC_CAC_ACC_UTCL2_VML21
#define GC_CAC_ACC_UTCL2_VML21__ACCUMULATOR_31_0__SHIFT                                                       0x0
#define GC_CAC_ACC_UTCL2_VML21__ACCUMULATOR_31_0_MASK                                                         0xFFFFFFFFL
//GC_CAC_ACC_UTCL2_VML22
#define GC_CAC_ACC_UTCL2_VML22__ACCUMULATOR_31_0__SHIFT                                                       0x0
#define GC_CAC_ACC_UTCL2_VML22__ACCUMULATOR_31_0_MASK                                                         0xFFFFFFFFL
//GC_CAC_ACC_UTCL2_VML23
#define GC_CAC_ACC_UTCL2_VML23__ACCUMULATOR_31_0__SHIFT                                                       0x0
#define GC_CAC_ACC_UTCL2_VML23__ACCUMULATOR_31_0_MASK                                                         0xFFFFFFFFL
//GC_CAC_ACC_UTCL2_VML24
#define GC_CAC_ACC_UTCL2_VML24__ACCUMULATOR_31_0__SHIFT                                                       0x0
#define GC_CAC_ACC_UTCL2_VML24__ACCUMULATOR_31_0_MASK                                                         0xFFFFFFFFL
//GC_CAC_ACC_UTCL2_WALKER0
#define GC_CAC_ACC_UTCL2_WALKER0__ACCUMULATOR_31_0__SHIFT                                                     0x0
#define GC_CAC_ACC_UTCL2_WALKER0__ACCUMULATOR_31_0_MASK                                                       0xFFFFFFFFL
//GC_CAC_ACC_UTCL2_WALKER1
#define GC_CAC_ACC_UTCL2_WALKER1__ACCUMULATOR_31_0__SHIFT                                                     0x0
#define GC_CAC_ACC_UTCL2_WALKER1__ACCUMULATOR_31_0_MASK                                                       0xFFFFFFFFL
//GC_CAC_ACC_UTCL2_WALKER2
#define GC_CAC_ACC_UTCL2_WALKER2__ACCUMULATOR_31_0__SHIFT                                                     0x0
#define GC_CAC_ACC_UTCL2_WALKER2__ACCUMULATOR_31_0_MASK                                                       0xFFFFFFFFL
//GC_CAC_ACC_UTCL2_WALKER3
#define GC_CAC_ACC_UTCL2_WALKER3__ACCUMULATOR_31_0__SHIFT                                                     0x0
#define GC_CAC_ACC_UTCL2_WALKER3__ACCUMULATOR_31_0_MASK                                                       0xFFFFFFFFL
//GC_CAC_ACC_UTCL2_WALKER4
#define GC_CAC_ACC_UTCL2_WALKER4__ACCUMULATOR_31_0__SHIFT                                                     0x0
#define GC_CAC_ACC_UTCL2_WALKER4__ACCUMULATOR_31_0_MASK                                                       0xFFFFFFFFL
//GC_CAC_ACC_CU0
#define GC_CAC_ACC_CU0__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_CU0__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_UTCL10
#define GC_CAC_ACC_UTCL10__ACCUMULATOR_31_0__SHIFT                                                            0x0
#define GC_CAC_ACC_UTCL10__ACCUMULATOR_31_0_MASK                                                              0xFFFFFFFFL
//GC_CAC_ACC_CHC0
#define GC_CAC_ACC_CHC0__ACCUMULATOR_31_0__SHIFT                                                              0x0
#define GC_CAC_ACC_CHC0__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
//GC_CAC_ACC_CHC1
#define GC_CAC_ACC_CHC1__ACCUMULATOR_31_0__SHIFT                                                              0x0
#define GC_CAC_ACC_CHC1__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
//GC_CAC_ACC_CHC2
#define GC_CAC_ACC_CHC2__ACCUMULATOR_31_0__SHIFT                                                              0x0
#define GC_CAC_ACC_CHC2__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
//GC_CAC_ACC_GE0
#define GC_CAC_ACC_GE0__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_GE0__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_GE1
#define GC_CAC_ACC_GE1__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_GE1__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_GE2
#define GC_CAC_ACC_GE2__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_GE2__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_GE3
#define GC_CAC_ACC_GE3__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_GE3__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_GE4
#define GC_CAC_ACC_GE4__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_GE4__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_GE5
#define GC_CAC_ACC_GE5__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_GE5__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_GE6
#define GC_CAC_ACC_GE6__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_GE6__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_GE7
#define GC_CAC_ACC_GE7__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_GE7__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_GE8
#define GC_CAC_ACC_GE8__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_GE8__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_GE9
#define GC_CAC_ACC_GE9__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_GE9__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_GE10
#define GC_CAC_ACC_GE10__ACCUMULATOR_31_0__SHIFT                                                              0x0
#define GC_CAC_ACC_GE10__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
//GC_CAC_ACC_GE11
#define GC_CAC_ACC_GE11__ACCUMULATOR_31_0__SHIFT                                                              0x0
#define GC_CAC_ACC_GE11__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
//GC_CAC_ACC_GE12
#define GC_CAC_ACC_GE12__ACCUMULATOR_31_0__SHIFT                                                              0x0
#define GC_CAC_ACC_GE12__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
//GC_CAC_ACC_GE13
#define GC_CAC_ACC_GE13__ACCUMULATOR_31_0__SHIFT                                                              0x0
#define GC_CAC_ACC_GE13__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
//GC_CAC_ACC_GE14
#define GC_CAC_ACC_GE14__ACCUMULATOR_31_0__SHIFT                                                              0x0
#define GC_CAC_ACC_GE14__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
//GC_CAC_ACC_GE15
#define GC_CAC_ACC_GE15__ACCUMULATOR_31_0__SHIFT                                                              0x0
#define GC_CAC_ACC_GE15__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
//GC_CAC_ACC_GE16
#define GC_CAC_ACC_GE16__ACCUMULATOR_31_0__SHIFT                                                              0x0
#define GC_CAC_ACC_GE16__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
//GC_CAC_ACC_GE17
#define GC_CAC_ACC_GE17__ACCUMULATOR_31_0__SHIFT                                                              0x0
#define GC_CAC_ACC_GE17__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
//GC_CAC_ACC_GE18
#define GC_CAC_ACC_GE18__ACCUMULATOR_31_0__SHIFT                                                              0x0
#define GC_CAC_ACC_GE18__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
//GC_CAC_ACC_GE19
#define GC_CAC_ACC_GE19__ACCUMULATOR_31_0__SHIFT                                                              0x0
#define GC_CAC_ACC_GE19__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
//GC_CAC_ACC_GE20
#define GC_CAC_ACC_GE20__ACCUMULATOR_31_0__SHIFT                                                              0x0
#define GC_CAC_ACC_GE20__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
//GC_CAC_ACC_PMM0
#define GC_CAC_ACC_PMM0__ACCUMULATOR_31_0__SHIFT                                                              0x0
#define GC_CAC_ACC_PMM0__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
//GC_CAC_ACC_GL2C0
#define GC_CAC_ACC_GL2C0__ACCUMULATOR_31_0__SHIFT                                                             0x0
#define GC_CAC_ACC_GL2C0__ACCUMULATOR_31_0_MASK                                                               0xFFFFFFFFL
//GC_CAC_ACC_GL2C1
#define GC_CAC_ACC_GL2C1__ACCUMULATOR_31_0__SHIFT                                                             0x0
#define GC_CAC_ACC_GL2C1__ACCUMULATOR_31_0_MASK                                                               0xFFFFFFFFL
//GC_CAC_ACC_GL2C2
#define GC_CAC_ACC_GL2C2__ACCUMULATOR_31_0__SHIFT                                                             0x0
#define GC_CAC_ACC_GL2C2__ACCUMULATOR_31_0_MASK                                                               0xFFFFFFFFL
//GC_CAC_ACC_GL2C3
#define GC_CAC_ACC_GL2C3__ACCUMULATOR_31_0__SHIFT                                                             0x0
#define GC_CAC_ACC_GL2C3__ACCUMULATOR_31_0_MASK                                                               0xFFFFFFFFL
//GC_CAC_ACC_GL2C4
#define GC_CAC_ACC_GL2C4__ACCUMULATOR_31_0__SHIFT                                                             0x0
#define GC_CAC_ACC_GL2C4__ACCUMULATOR_31_0_MASK                                                               0xFFFFFFFFL
//GC_CAC_ACC_GUS0
#define GC_CAC_ACC_GUS0__ACCUMULATOR_31_0__SHIFT                                                              0x0
#define GC_CAC_ACC_GUS0__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
//GC_CAC_ACC_GUS1
#define GC_CAC_ACC_GUS1__ACCUMULATOR_31_0__SHIFT                                                              0x0
#define GC_CAC_ACC_GUS1__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
//GC_CAC_ACC_GUS2
#define GC_CAC_ACC_GUS2__ACCUMULATOR_31_0__SHIFT                                                              0x0
#define GC_CAC_ACC_GUS2__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
//GC_CAC_ACC_PH0
#define GC_CAC_ACC_PH0__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_PH0__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_PH1
#define GC_CAC_ACC_PH1__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_PH1__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_PH2
#define GC_CAC_ACC_PH2__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_PH2__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_PH3
#define GC_CAC_ACC_PH3__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_PH3__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_PH4
#define GC_CAC_ACC_PH4__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_PH4__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_PH5
#define GC_CAC_ACC_PH5__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_PH5__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_PH6
#define GC_CAC_ACC_PH6__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_PH6__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_PH7
#define GC_CAC_ACC_PH7__ACCUMULATOR_31_0__SHIFT                                                               0x0
#define GC_CAC_ACC_PH7__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
//GC_CAC_ACC_SDMA0
#define GC_CAC_ACC_SDMA0__ACCUMULATOR_31_0__SHIFT                                                             0x0
#define GC_CAC_ACC_SDMA0__ACCUMULATOR_31_0_MASK                                                               0xFFFFFFFFL
//GC_CAC_ACC_SDMA1
#define GC_CAC_ACC_SDMA1__ACCUMULATOR_31_0__SHIFT                                                             0x0
#define GC_CAC_ACC_SDMA1__ACCUMULATOR_31_0_MASK                                                               0xFFFFFFFFL
//GC_CAC_ACC_SDMA2
#define GC_CAC_ACC_SDMA2__ACCUMULATOR_31_0__SHIFT                                                             0x0
#define GC_CAC_ACC_SDMA2__ACCUMULATOR_31_0_MASK                                                               0xFFFFFFFFL
//GC_CAC_ACC_SDMA3
#define GC_CAC_ACC_SDMA3__ACCUMULATOR_31_0__SHIFT                                                             0x0
#define GC_CAC_ACC_SDMA3__ACCUMULATOR_31_0_MASK                                                               0xFFFFFFFFL
//GC_CAC_ACC_SDMA4
#define GC_CAC_ACC_SDMA4__ACCUMULATOR_31_0__SHIFT                                                             0x0
#define GC_CAC_ACC_SDMA4__ACCUMULATOR_31_0_MASK                                                               0xFFFFFFFFL
//GC_CAC_ACC_SDMA5
#define GC_CAC_ACC_SDMA5__ACCUMULATOR_31_0__SHIFT                                                             0x0
#define GC_CAC_ACC_SDMA5__ACCUMULATOR_31_0_MASK                                                               0xFFFFFFFFL
//GC_CAC_ACC_SDMA6
#define GC_CAC_ACC_SDMA6__ACCUMULATOR_31_0__SHIFT                                                             0x0
#define GC_CAC_ACC_SDMA6__ACCUMULATOR_31_0_MASK                                                               0xFFFFFFFFL
//GC_CAC_ACC_SDMA7
#define GC_CAC_ACC_SDMA7__ACCUMULATOR_31_0__SHIFT                                                             0x0
#define GC_CAC_ACC_SDMA7__ACCUMULATOR_31_0_MASK                                                               0xFFFFFFFFL
//GC_CAC_ACC_SDMA8
#define GC_CAC_ACC_SDMA8__ACCUMULATOR_31_0__SHIFT                                                             0x0
#define GC_CAC_ACC_SDMA8__ACCUMULATOR_31_0_MASK                                                               0xFFFFFFFFL
//GC_CAC_ACC_SDMA9
#define GC_CAC_ACC_SDMA9__ACCUMULATOR_31_0__SHIFT                                                             0x0
#define GC_CAC_ACC_SDMA9__ACCUMULATOR_31_0_MASK                                                               0xFFFFFFFFL
//GC_CAC_ACC_SDMA10
#define GC_CAC_ACC_SDMA10__ACCUMULATOR_31_0__SHIFT                                                            0x0
#define GC_CAC_ACC_SDMA10__ACCUMULATOR_31_0_MASK                                                              0xFFFFFFFFL
//GC_CAC_ACC_SDMA11
#define GC_CAC_ACC_SDMA11__ACCUMULATOR_31_0__SHIFT                                                            0x0
#define GC_CAC_ACC_SDMA11__ACCUMULATOR_31_0_MASK                                                              0xFFFFFFFFL
//GC_CAC_ACC_SP0_LOWER
#define GC_CAC_ACC_SP0_LOWER__ACCUMULATOR_31_0__SHIFT                                                         0x0
#define GC_CAC_ACC_SP0_LOWER__ACCUMULATOR_31_0_MASK                                                           0xFFFFFFFFL
//GC_CAC_ACC_SP0_UPPER
#define GC_CAC_ACC_SP0_UPPER__ACCUMULATOR_39_32__SHIFT                                                        0x0
#define GC_CAC_ACC_SP0_UPPER__UNUSED_0__SHIFT                                                                 0x8
#define GC_CAC_ACC_SP0_UPPER__ACCUMULATOR_39_32_MASK                                                          0x000000FFL
#define GC_CAC_ACC_SP0_UPPER__UNUSED_0_MASK                                                                   0xFFFFFF00L
//GC_CAC_ACC_SP1_LOWER
#define GC_CAC_ACC_SP1_LOWER__ACCUMULATOR_31_0__SHIFT                                                         0x0
#define GC_CAC_ACC_SP1_LOWER__ACCUMULATOR_31_0_MASK                                                           0xFFFFFFFFL
//GC_CAC_ACC_SP1_UPPER
#define GC_CAC_ACC_SP1_UPPER__ACCUMULATOR_39_32__SHIFT                                                        0x0
#define GC_CAC_ACC_SP1_UPPER__UNUSED_0__SHIFT                                                                 0x8
#define GC_CAC_ACC_SP1_UPPER__ACCUMULATOR_39_32_MASK                                                          0x000000FFL
#define GC_CAC_ACC_SP1_UPPER__UNUSED_0_MASK                                                                   0xFFFFFF00L
//GC_CAC_ACC_SP2_LOWER
#define GC_CAC_ACC_SP2_LOWER__ACCUMULATOR_31_0__SHIFT                                                         0x0
#define GC_CAC_ACC_SP2_LOWER__ACCUMULATOR_31_0_MASK                                                           0xFFFFFFFFL
//GC_CAC_ACC_SP2_UPPER
#define GC_CAC_ACC_SP2_UPPER__ACCUMULATOR_39_32__SHIFT                                                        0x0
#define GC_CAC_ACC_SP2_UPPER__UNUSED_0__SHIFT                                                                 0x8
#define GC_CAC_ACC_SP2_UPPER__ACCUMULATOR_39_32_MASK                                                          0x000000FFL
#define GC_CAC_ACC_SP2_UPPER__UNUSED_0_MASK                                                                   0xFFFFFF00L
//GC_CAC_ACC_GL1C0
#define GC_CAC_ACC_GL1C0__ACCUMULATOR_31_0__SHIFT                                                             0x0
#define GC_CAC_ACC_GL1C0__ACCUMULATOR_31_0_MASK                                                               0xFFFFFFFFL
//GC_CAC_ACC_GL1C1
#define GC_CAC_ACC_GL1C1__ACCUMULATOR_31_0__SHIFT                                                             0x0
#define GC_CAC_ACC_GL1C1__ACCUMULATOR_31_0_MASK                                                               0xFFFFFFFFL
//GC_CAC_ACC_GL1C2
#define GC_CAC_ACC_GL1C2__ACCUMULATOR_31_0__SHIFT                                                             0x0
#define GC_CAC_ACC_GL1C2__ACCUMULATOR_31_0_MASK                                                               0xFFFFFFFFL
//GC_CAC_ACC_GL1C3
#define GC_CAC_ACC_GL1C3__ACCUMULATOR_31_0__SHIFT                                                             0x0
#define GC_CAC_ACC_GL1C3__ACCUMULATOR_31_0_MASK                                                               0xFFFFFFFFL
//GC_CAC_ACC_GL1C4
#define GC_CAC_ACC_GL1C4__ACCUMULATOR_31_0__SHIFT                                                             0x0
#define GC_CAC_ACC_GL1C4__ACCUMULATOR_31_0_MASK                                                               0xFFFFFFFFL
//GC_CAC_ACC_SQC0
#define GC_CAC_ACC_SQC0__ACCUMULATOR_31_0__SHIFT                                                              0x0
#define GC_CAC_ACC_SQC0__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
//GC_CAC_ACC_SQC1
#define GC_CAC_ACC_SQC1__ACCUMULATOR_31_0__SHIFT                                                              0x0
#define GC_CAC_ACC_SQC1__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
//GC_CAC_ACC_SQC2
#define GC_CAC_ACC_SQC2__ACCUMULATOR_31_0__SHIFT                                                              0x0
#define GC_CAC_ACC_SQC2__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
//GC_CAC_ACC_RLC0
#define GC_CAC_ACC_RLC0__ACCUMULATOR_31_0__SHIFT                                                              0x0
#define GC_CAC_ACC_RLC0__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
//GC_CAC_OVRD_BCI
#define GC_CAC_OVRD_BCI__OVRRD_SELECT__SHIFT                                                                  0x0
#define GC_CAC_OVRD_BCI__OVRRD_VALUE__SHIFT                                                                   0x2
#define GC_CAC_OVRD_BCI__OVRRD_SELECT_MASK                                                                    0x00000003L
#define GC_CAC_OVRD_BCI__OVRRD_VALUE_MASK                                                                     0x0000000CL
//GC_CAC_OVRD_CB
#define GC_CAC_OVRD_CB__OVRRD_SELECT__SHIFT                                                                   0x0
#define GC_CAC_OVRD_CB__OVRRD_VALUE__SHIFT                                                                    0xa
#define GC_CAC_OVRD_CB__OVRRD_SELECT_MASK                                                                     0x000003FFL
#define GC_CAC_OVRD_CB__OVRRD_VALUE_MASK                                                                      0x000FFC00L
//GC_CAC_OVRD_CP
#define GC_CAC_OVRD_CP__OVRRD_SELECT__SHIFT                                                                   0x0
#define GC_CAC_OVRD_CP__OVRRD_VALUE__SHIFT                                                                    0x3
#define GC_CAC_OVRD_CP__OVRRD_SELECT_MASK                                                                     0x00000007L
#define GC_CAC_OVRD_CP__OVRRD_VALUE_MASK                                                                      0x00000038L
//GC_CAC_OVRD_DB
#define GC_CAC_OVRD_DB__OVRRD_SELECT__SHIFT                                                                   0x0
#define GC_CAC_OVRD_DB__OVRRD_VALUE__SHIFT                                                                    0xa
#define GC_CAC_OVRD_DB__OVRRD_SELECT_MASK                                                                     0x000003FFL
#define GC_CAC_OVRD_DB__OVRRD_VALUE_MASK                                                                      0x000FFC00L
//GC_CAC_OVRD_GDS
#define GC_CAC_OVRD_GDS__OVRRD_SELECT__SHIFT                                                                  0x0
#define GC_CAC_OVRD_GDS__OVRRD_VALUE__SHIFT                                                                   0x5
#define GC_CAC_OVRD_GDS__OVRRD_SELECT_MASK                                                                    0x0000001FL
#define GC_CAC_OVRD_GDS__OVRRD_VALUE_MASK                                                                     0x000003E0L
//GC_CAC_OVRD_LDS
#define GC_CAC_OVRD_LDS__OVRRD_SELECT__SHIFT                                                                  0x0
#define GC_CAC_OVRD_LDS__OVRRD_VALUE__SHIFT                                                                   0x9
#define GC_CAC_OVRD_LDS__OVRRD_SELECT_MASK                                                                    0x000001FFL
#define GC_CAC_OVRD_LDS__OVRRD_VALUE_MASK                                                                     0x0003FE00L
//GC_CAC_OVRD_PA
#define GC_CAC_OVRD_PA__OVRRD_SELECT__SHIFT                                                                   0x0
#define GC_CAC_OVRD_PA__OVRRD_VALUE__SHIFT                                                                    0x8
#define GC_CAC_OVRD_PA__OVRRD_SELECT_MASK                                                                     0x000000FFL
#define GC_CAC_OVRD_PA__OVRRD_VALUE_MASK                                                                      0x0000FF00L
//GC_CAC_OVRD_PC
#define GC_CAC_OVRD_PC__OVRRD_SELECT__SHIFT                                                                   0x0
#define GC_CAC_OVRD_PC__OVRRD_VALUE__SHIFT                                                                    0x1
#define GC_CAC_OVRD_PC__OVRRD_SELECT_MASK                                                                     0x00000001L
#define GC_CAC_OVRD_PC__OVRRD_VALUE_MASK                                                                      0x00000002L
//GC_CAC_OVRD_SC
#define GC_CAC_OVRD_SC__OVRRD_SELECT__SHIFT                                                                   0x0
#define GC_CAC_OVRD_SC__OVRRD_VALUE__SHIFT                                                                    0x8
#define GC_CAC_OVRD_SC__OVRRD_SELECT_MASK                                                                     0x000000FFL
#define GC_CAC_OVRD_SC__OVRRD_VALUE_MASK                                                                      0x0000FF00L
//GC_CAC_OVRD_SPI
#define GC_CAC_OVRD_SPI__OVRRD_SELECT__SHIFT                                                                  0x0
#define GC_CAC_OVRD_SPI__OVRRD_VALUE__SHIFT                                                                   0x6
#define GC_CAC_OVRD_SPI__OVRRD_SELECT_MASK                                                                    0x0000003FL
#define GC_CAC_OVRD_SPI__OVRRD_VALUE_MASK                                                                     0x00000FC0L
//GC_CAC_OVRD_CU
#define GC_CAC_OVRD_CU__OVRRD_SELECT__SHIFT                                                                   0x0
#define GC_CAC_OVRD_CU__OVRRD_VALUE__SHIFT                                                                    0x1
#define GC_CAC_OVRD_CU__OVRRD_SELECT_MASK                                                                     0x00000001L
#define GC_CAC_OVRD_CU__OVRRD_VALUE_MASK                                                                      0x00000002L
//GC_CAC_OVRD_SQ
#define GC_CAC_OVRD_SQ__OVRRD_SELECT__SHIFT                                                                   0x0
#define GC_CAC_OVRD_SQ__OVRRD_VALUE__SHIFT                                                                    0x8
#define GC_CAC_OVRD_SQ__OVRRD_SELECT_MASK                                                                     0x000000FFL
#define GC_CAC_OVRD_SQ__OVRRD_VALUE_MASK                                                                      0x0000FF00L
//GC_CAC_OVRD_SX
#define GC_CAC_OVRD_SX__OVRRD_SELECT__SHIFT                                                                   0x0
#define GC_CAC_OVRD_SX__OVRRD_VALUE__SHIFT                                                                    0x1
#define GC_CAC_OVRD_SX__OVRRD_SELECT_MASK                                                                     0x00000001L
#define GC_CAC_OVRD_SX__OVRRD_VALUE_MASK                                                                      0x00000002L
//GC_CAC_OVRD_SXRB
#define GC_CAC_OVRD_SXRB__OVRRD_SELECT__SHIFT                                                                 0x0
#define GC_CAC_OVRD_SXRB__OVRRD_VALUE__SHIFT                                                                  0x1
#define GC_CAC_OVRD_SXRB__OVRRD_SELECT_MASK                                                                   0x00000001L
#define GC_CAC_OVRD_SXRB__OVRRD_VALUE_MASK                                                                    0x00000002L
//GC_CAC_OVRD_TA
#define GC_CAC_OVRD_TA__OVRRD_SELECT__SHIFT                                                                   0x0
#define GC_CAC_OVRD_TA__OVRRD_VALUE__SHIFT                                                                    0x1
#define GC_CAC_OVRD_TA__OVRRD_SELECT_MASK                                                                     0x00000001L
#define GC_CAC_OVRD_TA__OVRRD_VALUE_MASK                                                                      0x00000002L
//GC_CAC_OVRD_TCP
#define GC_CAC_OVRD_TCP__OVRRD_SELECT__SHIFT                                                                  0x0
#define GC_CAC_OVRD_TCP__OVRRD_VALUE__SHIFT                                                                   0x8
#define GC_CAC_OVRD_TCP__OVRRD_SELECT_MASK                                                                    0x000000FFL
#define GC_CAC_OVRD_TCP__OVRRD_VALUE_MASK                                                                     0x0000FF00L
//GC_CAC_OVRD_TD
#define GC_CAC_OVRD_TD__OVRRD_SELECT__SHIFT                                                                   0x0
#define GC_CAC_OVRD_TD__OVRRD_VALUE__SHIFT                                                                    0xb
#define GC_CAC_OVRD_TD__OVRRD_SELECT_MASK                                                                     0x000007FFL
#define GC_CAC_OVRD_TD__OVRRD_VALUE_MASK                                                                      0x003FF800L
//GC_CAC_OVRD_RMI
#define GC_CAC_OVRD_RMI__OVRRD_SELECT__SHIFT                                                                  0x0
#define GC_CAC_OVRD_RMI__OVRRD_VALUE__SHIFT                                                                   0x4
#define GC_CAC_OVRD_RMI__OVRRD_SELECT_MASK                                                                    0x0000000FL
#define GC_CAC_OVRD_RMI__OVRRD_VALUE_MASK                                                                     0x000000F0L
//GC_CAC_OVRD_EA
#define GC_CAC_OVRD_EA__OVRRD_SELECT__SHIFT                                                                   0x0
#define GC_CAC_OVRD_EA__OVRRD_VALUE__SHIFT                                                                    0x6
#define GC_CAC_OVRD_EA__OVRRD_SELECT_MASK                                                                     0x0000003FL
#define GC_CAC_OVRD_EA__OVRRD_VALUE_MASK                                                                      0x00000FC0L
//GC_CAC_OVRD_UTCL2_ATCL2
#define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_SELECT__SHIFT                                                          0x0
#define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_VALUE__SHIFT                                                           0x5
#define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_SELECT_MASK                                                            0x0000001FL
#define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_VALUE_MASK                                                             0x000003E0L
//GC_CAC_OVRD_UTCL2_ROUTER
#define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_SELECT__SHIFT                                                         0x0
#define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_VALUE__SHIFT                                                          0xa
#define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_SELECT_MASK                                                           0x000003FFL
#define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_VALUE_MASK                                                            0x000FFC00L
//GC_CAC_OVRD_UTCL2_VML2
#define GC_CAC_OVRD_UTCL2_VML2__OVRRD_SELECT__SHIFT                                                           0x0
#define GC_CAC_OVRD_UTCL2_VML2__OVRRD_VALUE__SHIFT                                                            0x5
#define GC_CAC_OVRD_UTCL2_VML2__OVRRD_SELECT_MASK                                                             0x0000001FL
#define GC_CAC_OVRD_UTCL2_VML2__OVRRD_VALUE_MASK                                                              0x000003E0L
//GC_CAC_OVRD_UTCL2_WALKER
#define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_SELECT__SHIFT                                                         0x0
#define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_VALUE__SHIFT                                                          0x5
#define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_SELECT_MASK                                                           0x0000001FL
#define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_VALUE_MASK                                                            0x000003E0L
//GC_CAC_OVRD_SP
#define GC_CAC_OVRD_SP__OVRRD_SELECT__SHIFT                                                                   0x0
#define GC_CAC_OVRD_SP__OVRRD_VALUE__SHIFT                                                                    0x3
#define GC_CAC_OVRD_SP__OVRRD_SELECT_MASK                                                                     0x00000007L
#define GC_CAC_OVRD_SP__OVRRD_VALUE_MASK                                                                      0x00000038L
//GC_CAC_OVRD_UTCL1
#define GC_CAC_OVRD_UTCL1__OVRRD_SELECT__SHIFT                                                                0x0
#define GC_CAC_OVRD_UTCL1__OVRRD_VALUE__SHIFT                                                                 0x1
#define GC_CAC_OVRD_UTCL1__OVRRD_SELECT_MASK                                                                  0x00000001L
#define GC_CAC_OVRD_UTCL1__OVRRD_VALUE_MASK                                                                   0x00000002L
//GC_CAC_OVRD_CHC
#define GC_CAC_OVRD_CHC__OVRRD_SELECT__SHIFT                                                                  0x0
#define GC_CAC_OVRD_CHC__OVRRD_VALUE__SHIFT                                                                   0x3
#define GC_CAC_OVRD_CHC__OVRRD_SELECT_MASK                                                                    0x00000007L
#define GC_CAC_OVRD_CHC__OVRRD_VALUE_MASK                                                                     0x00000038L
//GC_CAC_OVRD_GE
#define GC_CAC_OVRD_GE__OVRRD_SELECT__SHIFT                                                                   0x0
#define GC_CAC_OVRD_GE__OVRRD_VALUE__SHIFT                                                                    0x10
#define GC_CAC_OVRD_GE__OVRRD_SELECT_MASK                                                                     0x0000FFFFL
#define GC_CAC_OVRD_GE__OVRRD_VALUE_MASK                                                                      0xFFFF0000L
//GC_CAC_OVRD_PMM
#define GC_CAC_OVRD_PMM__OVRRD_SELECT__SHIFT                                                                  0x0
#define GC_CAC_OVRD_PMM__OVRRD_VALUE__SHIFT                                                                   0x1
#define GC_CAC_OVRD_PMM__OVRRD_SELECT_MASK                                                                    0x00000001L
#define GC_CAC_OVRD_PMM__OVRRD_VALUE_MASK                                                                     0x00000002L
//GC_CAC_OVRD_GL2C
#define GC_CAC_OVRD_GL2C__OVRRD_SELECT__SHIFT                                                                 0x0
#define GC_CAC_OVRD_GL2C__OVRRD_VALUE__SHIFT                                                                  0x5
#define GC_CAC_OVRD_GL2C__OVRRD_SELECT_MASK                                                                   0x0000001FL
#define GC_CAC_OVRD_GL2C__OVRRD_VALUE_MASK                                                                    0x000003E0L
//GC_CAC_OVRD_GUS
#define GC_CAC_OVRD_GUS__OVRRD_SELECT__SHIFT                                                                  0x0
#define GC_CAC_OVRD_GUS__OVRRD_VALUE__SHIFT                                                                   0x3
#define GC_CAC_OVRD_GUS__OVRRD_SELECT_MASK                                                                    0x00000007L
#define GC_CAC_OVRD_GUS__OVRRD_VALUE_MASK                                                                     0x00000038L
//GC_CAC_OVRD_PH
#define GC_CAC_OVRD_PH__OVRRD_SELECT__SHIFT                                                                   0x0
#define GC_CAC_OVRD_PH__OVRRD_VALUE__SHIFT                                                                    0x8
#define GC_CAC_OVRD_PH__OVRRD_SELECT_MASK                                                                     0x000000FFL
#define GC_CAC_OVRD_PH__OVRRD_VALUE_MASK                                                                      0x0000FF00L
//GC_CAC_OVRD_SDMA
#define GC_CAC_OVRD_SDMA__OVRRD_SELECT__SHIFT                                                                 0x0
#define GC_CAC_OVRD_SDMA__OVRRD_VALUE__SHIFT                                                                  0xc
#define GC_CAC_OVRD_SDMA__OVRRD_SELECT_MASK                                                                   0x00000FFFL
#define GC_CAC_OVRD_SDMA__OVRRD_VALUE_MASK                                                                    0x00FFF000L
//GC_CAC_OVRD_GL1C
#define GC_CAC_OVRD_GL1C__OVRRD_SELECT__SHIFT                                                                 0x0
#define GC_CAC_OVRD_GL1C__OVRRD_VALUE__SHIFT                                                                  0x5
#define GC_CAC_OVRD_GL1C__OVRRD_SELECT_MASK                                                                   0x0000001FL
#define GC_CAC_OVRD_GL1C__OVRRD_VALUE_MASK                                                                    0x000003E0L
//GC_CAC_OVRD_SQC
#define GC_CAC_OVRD_SQC__OVRRD_SELECT__SHIFT                                                                  0x0
#define GC_CAC_OVRD_SQC__OVRRD_VALUE__SHIFT                                                                   0x3
#define GC_CAC_OVRD_SQC__OVRRD_SELECT_MASK                                                                    0x00000007L
#define GC_CAC_OVRD_SQC__OVRRD_VALUE_MASK                                                                     0x00000038L
//GC_CAC_OVRD_RLC
#define GC_CAC_OVRD_RLC__OVRRD_SELECT__SHIFT                                                                  0x0
#define GC_CAC_OVRD_RLC__OVRRD_VALUE__SHIFT                                                                   0x1
#define GC_CAC_OVRD_RLC__OVRRD_SELECT_MASK                                                                    0x00000001L
#define GC_CAC_OVRD_RLC__OVRRD_VALUE_MASK                                                                     0x00000002L
//GC_CAC_OVRD_GE_HI
#define GC_CAC_OVRD_GE_HI__OVRRD_SELECT__SHIFT                                                                0x0
#define GC_CAC_OVRD_GE_HI__OVRRD_VALUE__SHIFT                                                                 0x10
#define GC_CAC_OVRD_GE_HI__OVRRD_SELECT_MASK                                                                  0x0000FFFFL
#define GC_CAC_OVRD_GE_HI__OVRRD_VALUE_MASK                                                                   0xFFFF0000L
//RELEASE_TO_STALL_LUT_1_8
#define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_1__SHIFT                                                      0x0
#define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_2__SHIFT                                                      0x4
#define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_3__SHIFT                                                      0x8
#define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_4__SHIFT                                                      0xc
#define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_5__SHIFT                                                      0x10
#define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_6__SHIFT                                                      0x14
#define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_7__SHIFT                                                      0x18
#define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_8__SHIFT                                                      0x1c
#define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_1_MASK                                                        0x00000007L
#define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_2_MASK                                                        0x00000070L
#define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_3_MASK                                                        0x00000700L
#define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_4_MASK                                                        0x00007000L
#define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_5_MASK                                                        0x00070000L
#define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_6_MASK                                                        0x00700000L
#define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_7_MASK                                                        0x07000000L
#define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_8_MASK                                                        0x70000000L
//RELEASE_TO_STALL_LUT_9_16
#define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_9__SHIFT                                                     0x0
#define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_10__SHIFT                                                    0x4
#define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_11__SHIFT                                                    0x8
#define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_12__SHIFT                                                    0xc
#define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_13__SHIFT                                                    0x10
#define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_14__SHIFT                                                    0x14
#define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_15__SHIFT                                                    0x18
#define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_16__SHIFT                                                    0x1c
#define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_9_MASK                                                       0x00000007L
#define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_10_MASK                                                      0x00000070L
#define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_11_MASK                                                      0x00000700L
#define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_12_MASK                                                      0x00007000L
#define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_13_MASK                                                      0x00070000L
#define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_14_MASK                                                      0x00700000L
#define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_15_MASK                                                      0x07000000L
#define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_16_MASK                                                      0x70000000L
//RELEASE_TO_STALL_LUT_17_20
#define RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_17__SHIFT                                                   0x0
#define RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_18__SHIFT                                                   0x4
#define RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_19__SHIFT                                                   0x8
#define RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_20__SHIFT                                                   0xc
#define RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_17_MASK                                                     0x00000007L
#define RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_18_MASK                                                     0x00000070L
#define RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_19_MASK                                                     0x00000700L
#define RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_20_MASK                                                     0x00007000L
//STALL_TO_RELEASE_LUT_1_4
#define STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_1__SHIFT                                                      0x0
#define STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_2__SHIFT                                                      0x8
#define STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_3__SHIFT                                                      0x10
#define STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_4__SHIFT                                                      0x18
#define STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_1_MASK                                                        0x0000001FL
#define STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_2_MASK                                                        0x00001F00L
#define STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_3_MASK                                                        0x001F0000L
#define STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_4_MASK                                                        0x1F000000L
//STALL_TO_RELEASE_LUT_5_7
#define STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_5__SHIFT                                                      0x0
#define STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_6__SHIFT                                                      0x8
#define STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_7__SHIFT                                                      0x10
#define STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_5_MASK                                                        0x0000001FL
#define STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_6_MASK                                                        0x00001F00L
#define STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_7_MASK                                                        0x001F0000L
//STALL_TO_PWRBRK_LUT_1_4
#define STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_1__SHIFT                                                       0x0
#define STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_2__SHIFT                                                       0x8
#define STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_3__SHIFT                                                       0x10
#define STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_4__SHIFT                                                       0x18
#define STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_1_MASK                                                         0x00000007L
#define STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_2_MASK                                                         0x00000700L
#define STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_3_MASK                                                         0x00070000L
#define STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_4_MASK                                                         0x07000000L
//STALL_TO_PWRBRK_LUT_5_7
#define STALL_TO_PWRBRK_LUT_5_7__FIRST_PATTERN_5__SHIFT                                                       0x0
#define STALL_TO_PWRBRK_LUT_5_7__FIRST_PATTERN_6__SHIFT                                                       0x8
#define STALL_TO_PWRBRK_LUT_5_7__FIRST_PATTERN_7__SHIFT                                                       0x10
#define STALL_TO_PWRBRK_LUT_5_7__FIRST_PATTERN_5_MASK                                                         0x00000007L
#define STALL_TO_PWRBRK_LUT_5_7__FIRST_PATTERN_6_MASK                                                         0x00000700L
#define STALL_TO_PWRBRK_LUT_5_7__FIRST_PATTERN_7_MASK                                                         0x00070000L
//PWRBRK_STALL_TO_RELEASE_LUT_1_4
#define PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_1__SHIFT                                               0x0
#define PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_2__SHIFT                                               0x8
#define PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_3__SHIFT                                               0x10
#define PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_4__SHIFT                                               0x18
#define PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_1_MASK                                                 0x0000001FL
#define PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_2_MASK                                                 0x00001F00L
#define PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_3_MASK                                                 0x001F0000L
#define PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_4_MASK                                                 0x1F000000L
//PWRBRK_STALL_TO_RELEASE_LUT_5_7
#define PWRBRK_STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_5__SHIFT                                               0x0
#define PWRBRK_STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_6__SHIFT                                               0x8
#define PWRBRK_STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_7__SHIFT                                               0x10
#define PWRBRK_STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_5_MASK                                                 0x0000001FL
#define PWRBRK_STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_6_MASK                                                 0x00001F00L
#define PWRBRK_STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_7_MASK                                                 0x001F0000L
//PWRBRK_RELEASE_TO_STALL_LUT_1_8
#define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_1__SHIFT                                               0x0
#define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_2__SHIFT                                               0x4
#define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_3__SHIFT                                               0x8
#define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_4__SHIFT                                               0xc
#define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_5__SHIFT                                               0x10
#define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_6__SHIFT                                               0x14
#define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_7__SHIFT                                               0x18
#define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_8__SHIFT                                               0x1c
#define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_1_MASK                                                 0x00000007L
#define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_2_MASK                                                 0x00000070L
#define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_3_MASK                                                 0x00000700L
#define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_4_MASK                                                 0x00007000L
#define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_5_MASK                                                 0x00070000L
#define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_6_MASK                                                 0x00700000L
#define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_7_MASK                                                 0x07000000L
#define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_8_MASK                                                 0x70000000L
//PWRBRK_RELEASE_TO_STALL_LUT_9_16
#define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_9__SHIFT                                              0x0
#define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_10__SHIFT                                             0x4
#define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_11__SHIFT                                             0x8
#define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_12__SHIFT                                             0xc
#define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_13__SHIFT                                             0x10
#define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_14__SHIFT                                             0x14
#define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_15__SHIFT                                             0x18
#define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_16__SHIFT                                             0x1c
#define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_9_MASK                                                0x00000007L
#define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_10_MASK                                               0x00000070L
#define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_11_MASK                                               0x00000700L
#define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_12_MASK                                               0x00007000L
#define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_13_MASK                                               0x00070000L
#define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_14_MASK                                               0x00700000L
#define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_15_MASK                                               0x07000000L
#define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_16_MASK                                               0x70000000L
//PWRBRK_RELEASE_TO_STALL_LUT_17_20
#define PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_17__SHIFT                                            0x0
#define PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_18__SHIFT                                            0x4
#define PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_19__SHIFT                                            0x8
#define PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_20__SHIFT                                            0xc
#define PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_17_MASK                                              0x00000007L
#define PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_18_MASK                                              0x00000070L
#define PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_19_MASK                                              0x00000700L
#define PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_20_MASK                                              0x00007000L
//FIXED_PATTERN_PERF_COUNTER_1
#define FIXED_PATTERN_PERF_COUNTER_1__PERF_COUNTER__SHIFT                                                     0x0
#define FIXED_PATTERN_PERF_COUNTER_1__PERF_COUNTER_MASK                                                       0x0001FFFFL
//FIXED_PATTERN_PERF_COUNTER_2
#define FIXED_PATTERN_PERF_COUNTER_2__PERF_COUNTER__SHIFT                                                     0x0
#define FIXED_PATTERN_PERF_COUNTER_2__PERF_COUNTER_MASK                                                       0x0001FFFFL
//FIXED_PATTERN_PERF_COUNTER_3
#define FIXED_PATTERN_PERF_COUNTER_3__PERF_COUNTER__SHIFT                                                     0x0
#define FIXED_PATTERN_PERF_COUNTER_3__PERF_COUNTER_MASK                                                       0x0001FFFFL
//FIXED_PATTERN_PERF_COUNTER_4
#define FIXED_PATTERN_PERF_COUNTER_4__PERF_COUNTER__SHIFT                                                     0x0
#define FIXED_PATTERN_PERF_COUNTER_4__PERF_COUNTER_MASK                                                       0x0001FFFFL
//FIXED_PATTERN_PERF_COUNTER_5
#define FIXED_PATTERN_PERF_COUNTER_5__PERF_COUNTER__SHIFT                                                     0x0
#define FIXED_PATTERN_PERF_COUNTER_5__PERF_COUNTER_MASK                                                       0x0001FFFFL
//FIXED_PATTERN_PERF_COUNTER_6
#define FIXED_PATTERN_PERF_COUNTER_6__PERF_COUNTER__SHIFT                                                     0x0
#define FIXED_PATTERN_PERF_COUNTER_6__PERF_COUNTER_MASK                                                       0x0001FFFFL
//FIXED_PATTERN_PERF_COUNTER_7
#define FIXED_PATTERN_PERF_COUNTER_7__PERF_COUNTER__SHIFT                                                     0x0
#define FIXED_PATTERN_PERF_COUNTER_7__PERF_COUNTER_MASK                                                       0x0001FFFFL
//FIXED_PATTERN_PERF_COUNTER_8
#define FIXED_PATTERN_PERF_COUNTER_8__PERF_COUNTER__SHIFT                                                     0x0
#define FIXED_PATTERN_PERF_COUNTER_8__PERF_COUNTER_MASK                                                       0x0001FFFFL
//FIXED_PATTERN_PERF_COUNTER_9
#define FIXED_PATTERN_PERF_COUNTER_9__PERF_COUNTER__SHIFT                                                     0x0
#define FIXED_PATTERN_PERF_COUNTER_9__PERF_COUNTER_MASK                                                       0x0001FFFFL
//FIXED_PATTERN_PERF_COUNTER_10
#define FIXED_PATTERN_PERF_COUNTER_10__PERF_COUNTER__SHIFT                                                    0x0
#define FIXED_PATTERN_PERF_COUNTER_10__PERF_COUNTER_MASK                                                      0x0001FFFFL
//HW_LUT_UPDATE_STATUS
#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_1_DONE__SHIFT                                                      0x0
#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_1_ERROR__SHIFT                                                     0x1
#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_1_ERROR_STEP__SHIFT                                                0x2
#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_2_DONE__SHIFT                                                      0x5
#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_2_ERROR__SHIFT                                                     0x6
#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_2_ERROR_STEP__SHIFT                                                0x7
#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_3_DONE__SHIFT                                                      0xa
#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_3_ERROR__SHIFT                                                     0xb
#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_3_ERROR_STEP__SHIFT                                                0xc
#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_4_DONE__SHIFT                                                      0x11
#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_4_ERROR__SHIFT                                                     0x12
#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_4_ERROR_STEP__SHIFT                                                0x13
#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_5_DONE__SHIFT                                                      0x16
#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_5_ERROR__SHIFT                                                     0x17
#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_5_ERROR_STEP__SHIFT                                                0x18
#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_1_DONE_MASK                                                        0x00000001L
#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_1_ERROR_MASK                                                       0x00000002L
#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_1_ERROR_STEP_MASK                                                  0x0000001CL
#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_2_DONE_MASK                                                        0x00000020L
#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_2_ERROR_MASK                                                       0x00000040L
#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_2_ERROR_STEP_MASK                                                  0x00000380L
#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_3_DONE_MASK                                                        0x00000400L
#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_3_ERROR_MASK                                                       0x00000800L
#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_3_ERROR_STEP_MASK                                                  0x0001F000L
#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_4_DONE_MASK                                                        0x00020000L
#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_4_ERROR_MASK                                                       0x00040000L
#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_4_ERROR_STEP_MASK                                                  0x00380000L
#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_5_DONE_MASK                                                        0x00400000L
#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_5_ERROR_MASK                                                       0x00800000L
#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_5_ERROR_STEP_MASK                                                  0x1F000000L


// addressBlock: secacind
//SE_CAC_ID
#define SE_CAC_ID__CAC_BLOCK_ID__SHIFT                                                                        0x0
#define SE_CAC_ID__CAC_SIGNAL_ID__SHIFT                                                                       0x6
#define SE_CAC_ID__UNUSED_0__SHIFT                                                                            0xe
#define SE_CAC_ID__CAC_BLOCK_ID_MASK                                                                          0x0000003FL
#define SE_CAC_ID__CAC_SIGNAL_ID_MASK                                                                         0x00003FC0L
#define SE_CAC_ID__UNUSED_0_MASK                                                                              0xFFFFC000L
//SE_CAC_CNTL
#define SE_CAC_CNTL__CAC_FORCE_DISABLE__SHIFT                                                                 0x0
#define SE_CAC_CNTL__CAC_THRESHOLD__SHIFT                                                                     0x1
#define SE_CAC_CNTL__UNUSED_0__SHIFT                                                                          0x11
#define SE_CAC_CNTL__CAC_FORCE_DISABLE_MASK                                                                   0x00000001L
#define SE_CAC_CNTL__CAC_THRESHOLD_MASK                                                                       0x0001FFFEL
#define SE_CAC_CNTL__UNUSED_0_MASK                                                                            0xFFFE0000L
//SE_CAC_OVR_SEL
#define SE_CAC_OVR_SEL__CAC_OVR_SEL__SHIFT                                                                    0x0
#define SE_CAC_OVR_SEL__CAC_OVR_SEL_MASK                                                                      0xFFFFFFFFL
//SE_CAC_OVR_VAL
#define SE_CAC_OVR_VAL__CAC_OVR_VAL__SHIFT                                                                    0x0
#define SE_CAC_OVR_VAL__CAC_OVR_VAL_MASK                                                                      0xFFFFFFFFL


// addressBlock: spmglbind
//GLB_CPG_SAMPLEDELAY
#define GLB_CPG_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                               0x0
#define GLB_CPG_SAMPLEDELAY__RESERVED__SHIFT                                                                  0x6
#define GLB_CPG_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                 0x0000003FL
#define GLB_CPG_SAMPLEDELAY__RESERVED_MASK                                                                    0xFFFFFFC0L
//GLB_CPC_SAMPLEDELAY
#define GLB_CPC_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                               0x0
#define GLB_CPC_SAMPLEDELAY__RESERVED__SHIFT                                                                  0x6
#define GLB_CPC_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                 0x0000003FL
#define GLB_CPC_SAMPLEDELAY__RESERVED_MASK                                                                    0xFFFFFFC0L
//GLB_CPF_SAMPLEDELAY
#define GLB_CPF_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                               0x0
#define GLB_CPF_SAMPLEDELAY__RESERVED__SHIFT                                                                  0x6
#define GLB_CPF_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                 0x0000003FL
#define GLB_CPF_SAMPLEDELAY__RESERVED_MASK                                                                    0xFFFFFFC0L
//GLB_GDS_SAMPLEDELAY
#define GLB_GDS_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                               0x0
#define GLB_GDS_SAMPLEDELAY__RESERVED__SHIFT                                                                  0x6
#define GLB_GDS_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                 0x0000003FL
#define GLB_GDS_SAMPLEDELAY__RESERVED_MASK                                                                    0xFFFFFFC0L
//GLB_GCR_SAMPLEDELAY
#define GLB_GCR_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                               0x0
#define GLB_GCR_SAMPLEDELAY__RESERVED__SHIFT                                                                  0x6
#define GLB_GCR_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                 0x0000003FL
#define GLB_GCR_SAMPLEDELAY__RESERVED_MASK                                                                    0xFFFFFFC0L
//GLB_PH_SAMPLEDELAY
#define GLB_PH_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                                0x0
#define GLB_PH_SAMPLEDELAY__RESERVED__SHIFT                                                                   0x6
#define GLB_PH_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                  0x0000003FL
#define GLB_PH_SAMPLEDELAY__RESERVED_MASK                                                                     0xFFFFFFC0L
//GLB_GE1_SAMPLEDELAY
#define GLB_GE1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                               0x0
#define GLB_GE1_SAMPLEDELAY__RESERVED__SHIFT                                                                  0x6
#define GLB_GE1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                 0x0000003FL
#define GLB_GE1_SAMPLEDELAY__RESERVED_MASK                                                                    0xFFFFFFC0L
//GLB_GE2DIST_SAMPLEDELAY
#define GLB_GE2DIST_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                           0x0
#define GLB_GE2DIST_SAMPLEDELAY__RESERVED__SHIFT                                                              0x6
#define GLB_GE2DIST_SAMPLEDELAY__SAMPLEDELAY_MASK                                                             0x0000003FL
#define GLB_GE2DIST_SAMPLEDELAY__RESERVED_MASK                                                                0xFFFFFFC0L
//GLB_GUS_SAMPLEDELAY
#define GLB_GUS_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                               0x0
#define GLB_GUS_SAMPLEDELAY__RESERVED__SHIFT                                                                  0x6
#define GLB_GUS_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                 0x0000003FL
#define GLB_GUS_SAMPLEDELAY__RESERVED_MASK                                                                    0xFFFFFFC0L
//GLB_CHA_SAMPLEDELAY
#define GLB_CHA_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                               0x0
#define GLB_CHA_SAMPLEDELAY__RESERVED__SHIFT                                                                  0x6
#define GLB_CHA_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                 0x0000003FL
#define GLB_CHA_SAMPLEDELAY__RESERVED_MASK                                                                    0xFFFFFFC0L
//GLB_CHCG_SAMPLEDELAY
#define GLB_CHCG_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                              0x0
#define GLB_CHCG_SAMPLEDELAY__RESERVED__SHIFT                                                                 0x6
#define GLB_CHCG_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                0x0000003FL
#define GLB_CHCG_SAMPLEDELAY__RESERVED_MASK                                                                   0xFFFFFFC0L
//GLB_ATCL2_SAMPLEDELAY
#define GLB_ATCL2_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
#define GLB_ATCL2_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
#define GLB_ATCL2_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
#define GLB_ATCL2_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
//GLB_VML2_SAMPLEDELAY
#define GLB_VML2_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                              0x0
#define GLB_VML2_SAMPLEDELAY__RESERVED__SHIFT                                                                 0x6
#define GLB_VML2_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                0x0000003FL
#define GLB_VML2_SAMPLEDELAY__RESERVED_MASK                                                                   0xFFFFFFC0L
//GLB_SDMA0_SAMPLEDELAY
#define GLB_SDMA0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
#define GLB_SDMA0_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
#define GLB_SDMA0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
#define GLB_SDMA0_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
//GLB_SDMA1_SAMPLEDELAY
#define GLB_SDMA1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
#define GLB_SDMA1_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
#define GLB_SDMA1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
#define GLB_SDMA1_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
//GLB_SDMA2_SAMPLEDELAY
#define GLB_SDMA2_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
#define GLB_SDMA2_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
#define GLB_SDMA2_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
#define GLB_SDMA2_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
//GLB_SDMA3_SAMPLEDELAY
#define GLB_SDMA3_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
#define GLB_SDMA3_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
#define GLB_SDMA3_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
#define GLB_SDMA3_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
//GLB_GL2A0_SAMPLEDELAY
#define GLB_GL2A0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
#define GLB_GL2A0_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
#define GLB_GL2A0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
#define GLB_GL2A0_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
//GLB_GL2A1_SAMPLEDELAY
#define GLB_GL2A1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
#define GLB_GL2A1_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
#define GLB_GL2A1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
#define GLB_GL2A1_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
//GLB_GL2A2_SAMPLEDELAY
#define GLB_GL2A2_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
#define GLB_GL2A2_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
#define GLB_GL2A2_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
#define GLB_GL2A2_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
//GLB_GL2A3_SAMPLEDELAY
#define GLB_GL2A3_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
#define GLB_GL2A3_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
#define GLB_GL2A3_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
#define GLB_GL2A3_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
//GLB_GL2C0_SAMPLEDELAY
#define GLB_GL2C0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
#define GLB_GL2C0_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
#define GLB_GL2C0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
#define GLB_GL2C0_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
//GLB_GL2C1_SAMPLEDELAY
#define GLB_GL2C1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
#define GLB_GL2C1_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
#define GLB_GL2C1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
#define GLB_GL2C1_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
//GLB_GL2C2_SAMPLEDELAY
#define GLB_GL2C2_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
#define GLB_GL2C2_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
#define GLB_GL2C2_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
#define GLB_GL2C2_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
//GLB_GL2C3_SAMPLEDELAY
#define GLB_GL2C3_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
#define GLB_GL2C3_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
#define GLB_GL2C3_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
#define GLB_GL2C3_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
//GLB_GL2C4_SAMPLEDELAY
#define GLB_GL2C4_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
#define GLB_GL2C4_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
#define GLB_GL2C4_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
#define GLB_GL2C4_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
//GLB_GL2C5_SAMPLEDELAY
#define GLB_GL2C5_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
#define GLB_GL2C5_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
#define GLB_GL2C5_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
#define GLB_GL2C5_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
//GLB_GL2C6_SAMPLEDELAY
#define GLB_GL2C6_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
#define GLB_GL2C6_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
#define GLB_GL2C6_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
#define GLB_GL2C6_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
//GLB_GL2C7_SAMPLEDELAY
#define GLB_GL2C7_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
#define GLB_GL2C7_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
#define GLB_GL2C7_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
#define GLB_GL2C7_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
//GLB_GL2C8_SAMPLEDELAY
#define GLB_GL2C8_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
#define GLB_GL2C8_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
#define GLB_GL2C8_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
#define GLB_GL2C8_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
//GLB_GL2C9_SAMPLEDELAY
#define GLB_GL2C9_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
#define GLB_GL2C9_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
#define GLB_GL2C9_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
#define GLB_GL2C9_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
//GLB_GL2C10_SAMPLEDELAY
#define GLB_GL2C10_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                            0x0
#define GLB_GL2C10_SAMPLEDELAY__RESERVED__SHIFT                                                               0x6
#define GLB_GL2C10_SAMPLEDELAY__SAMPLEDELAY_MASK                                                              0x0000003FL
#define GLB_GL2C10_SAMPLEDELAY__RESERVED_MASK                                                                 0xFFFFFFC0L
//GLB_GL2C11_SAMPLEDELAY
#define GLB_GL2C11_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                            0x0
#define GLB_GL2C11_SAMPLEDELAY__RESERVED__SHIFT                                                               0x6
#define GLB_GL2C11_SAMPLEDELAY__SAMPLEDELAY_MASK                                                              0x0000003FL
#define GLB_GL2C11_SAMPLEDELAY__RESERVED_MASK                                                                 0xFFFFFFC0L
//GLB_GL2C12_SAMPLEDELAY
#define GLB_GL2C12_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                            0x0
#define GLB_GL2C12_SAMPLEDELAY__RESERVED__SHIFT                                                               0x6
#define GLB_GL2C12_SAMPLEDELAY__SAMPLEDELAY_MASK                                                              0x0000003FL
#define GLB_GL2C12_SAMPLEDELAY__RESERVED_MASK                                                                 0xFFFFFFC0L
//GLB_GL2C13_SAMPLEDELAY
#define GLB_GL2C13_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                            0x0
#define GLB_GL2C13_SAMPLEDELAY__RESERVED__SHIFT                                                               0x6
#define GLB_GL2C13_SAMPLEDELAY__SAMPLEDELAY_MASK                                                              0x0000003FL
#define GLB_GL2C13_SAMPLEDELAY__RESERVED_MASK                                                                 0xFFFFFFC0L
//GLB_GL2C14_SAMPLEDELAY
#define GLB_GL2C14_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                            0x0
#define GLB_GL2C14_SAMPLEDELAY__RESERVED__SHIFT                                                               0x6
#define GLB_GL2C14_SAMPLEDELAY__SAMPLEDELAY_MASK                                                              0x0000003FL
#define GLB_GL2C14_SAMPLEDELAY__RESERVED_MASK                                                                 0xFFFFFFC0L
//GLB_GL2C15_SAMPLEDELAY
#define GLB_GL2C15_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                            0x0
#define GLB_GL2C15_SAMPLEDELAY__RESERVED__SHIFT                                                               0x6
#define GLB_GL2C15_SAMPLEDELAY__SAMPLEDELAY_MASK                                                              0x0000003FL
#define GLB_GL2C15_SAMPLEDELAY__RESERVED_MASK                                                                 0xFFFFFFC0L
//GLB_EA0_SAMPLEDELAY
#define GLB_EA0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                               0x0
#define GLB_EA0_SAMPLEDELAY__RESERVED__SHIFT                                                                  0x6
#define GLB_EA0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                 0x0000003FL
#define GLB_EA0_SAMPLEDELAY__RESERVED_MASK                                                                    0xFFFFFFC0L
//GLB_EA1_SAMPLEDELAY
#define GLB_EA1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                               0x0
#define GLB_EA1_SAMPLEDELAY__RESERVED__SHIFT                                                                  0x6
#define GLB_EA1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                 0x0000003FL
#define GLB_EA1_SAMPLEDELAY__RESERVED_MASK                                                                    0xFFFFFFC0L
//GLB_EA2_SAMPLEDELAY
#define GLB_EA2_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                               0x0
#define GLB_EA2_SAMPLEDELAY__RESERVED__SHIFT                                                                  0x6
#define GLB_EA2_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                 0x0000003FL
#define GLB_EA2_SAMPLEDELAY__RESERVED_MASK                                                                    0xFFFFFFC0L
//GLB_EA3_SAMPLEDELAY
#define GLB_EA3_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                               0x0
#define GLB_EA3_SAMPLEDELAY__RESERVED__SHIFT                                                                  0x6
#define GLB_EA3_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                 0x0000003FL
#define GLB_EA3_SAMPLEDELAY__RESERVED_MASK                                                                    0xFFFFFFC0L
//GLB_EA4_SAMPLEDELAY
#define GLB_EA4_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                               0x0
#define GLB_EA4_SAMPLEDELAY__RESERVED__SHIFT                                                                  0x6
#define GLB_EA4_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                 0x0000003FL
#define GLB_EA4_SAMPLEDELAY__RESERVED_MASK                                                                    0xFFFFFFC0L
//GLB_EA5_SAMPLEDELAY
#define GLB_EA5_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                               0x0
#define GLB_EA5_SAMPLEDELAY__RESERVED__SHIFT                                                                  0x6
#define GLB_EA5_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                 0x0000003FL
#define GLB_EA5_SAMPLEDELAY__RESERVED_MASK                                                                    0xFFFFFFC0L
//GLB_EA6_SAMPLEDELAY
#define GLB_EA6_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                               0x0
#define GLB_EA6_SAMPLEDELAY__RESERVED__SHIFT                                                                  0x6
#define GLB_EA6_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                 0x0000003FL
#define GLB_EA6_SAMPLEDELAY__RESERVED_MASK                                                                    0xFFFFFFC0L
//GLB_EA7_SAMPLEDELAY
#define GLB_EA7_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                               0x0
#define GLB_EA7_SAMPLEDELAY__RESERVED__SHIFT                                                                  0x6
#define GLB_EA7_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                 0x0000003FL
#define GLB_EA7_SAMPLEDELAY__RESERVED_MASK                                                                    0xFFFFFFC0L
//GLB_EA8_SAMPLEDELAY
#define GLB_EA8_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                               0x0
#define GLB_EA8_SAMPLEDELAY__RESERVED__SHIFT                                                                  0x6
#define GLB_EA8_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                 0x0000003FL
#define GLB_EA8_SAMPLEDELAY__RESERVED_MASK                                                                    0xFFFFFFC0L
//GLB_EA9_SAMPLEDELAY
#define GLB_EA9_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                               0x0
#define GLB_EA9_SAMPLEDELAY__RESERVED__SHIFT                                                                  0x6
#define GLB_EA9_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                 0x0000003FL
#define GLB_EA9_SAMPLEDELAY__RESERVED_MASK                                                                    0xFFFFFFC0L
//GLB_EA10_SAMPLEDELAY
#define GLB_EA10_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                              0x0
#define GLB_EA10_SAMPLEDELAY__RESERVED__SHIFT                                                                 0x6
#define GLB_EA10_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                0x0000003FL
#define GLB_EA10_SAMPLEDELAY__RESERVED_MASK                                                                   0xFFFFFFC0L
//GLB_EA11_SAMPLEDELAY
#define GLB_EA11_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                              0x0
#define GLB_EA11_SAMPLEDELAY__RESERVED__SHIFT                                                                 0x6
#define GLB_EA11_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                0x0000003FL
#define GLB_EA11_SAMPLEDELAY__RESERVED_MASK                                                                   0xFFFFFFC0L
//GLB_EA12_SAMPLEDELAY
#define GLB_EA12_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                              0x0
#define GLB_EA12_SAMPLEDELAY__RESERVED__SHIFT                                                                 0x6
#define GLB_EA12_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                0x0000003FL
#define GLB_EA12_SAMPLEDELAY__RESERVED_MASK                                                                   0xFFFFFFC0L
//GLB_EA13_SAMPLEDELAY
#define GLB_EA13_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                              0x0
#define GLB_EA13_SAMPLEDELAY__RESERVED__SHIFT                                                                 0x6
#define GLB_EA13_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                0x0000003FL
#define GLB_EA13_SAMPLEDELAY__RESERVED_MASK                                                                   0xFFFFFFC0L
//GLB_EA14_SAMPLEDELAY
#define GLB_EA14_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                              0x0
#define GLB_EA14_SAMPLEDELAY__RESERVED__SHIFT                                                                 0x6
#define GLB_EA14_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                0x0000003FL
#define GLB_EA14_SAMPLEDELAY__RESERVED_MASK                                                                   0xFFFFFFC0L
//GLB_EA15_SAMPLEDELAY
#define GLB_EA15_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                              0x0
#define GLB_EA15_SAMPLEDELAY__RESERVED__SHIFT                                                                 0x6
#define GLB_EA15_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                0x0000003FL
#define GLB_EA15_SAMPLEDELAY__RESERVED_MASK                                                                   0xFFFFFFC0L
//GLB_CHC0_SAMPLEDELAY
#define GLB_CHC0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                              0x0
#define GLB_CHC0_SAMPLEDELAY__RESERVED__SHIFT                                                                 0x6
#define GLB_CHC0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                0x0000003FL
#define GLB_CHC0_SAMPLEDELAY__RESERVED_MASK                                                                   0xFFFFFFC0L
//GLB_CHC1_SAMPLEDELAY
#define GLB_CHC1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                              0x0
#define GLB_CHC1_SAMPLEDELAY__RESERVED__SHIFT                                                                 0x6
#define GLB_CHC1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                0x0000003FL
#define GLB_CHC1_SAMPLEDELAY__RESERVED_MASK                                                                   0xFFFFFFC0L
//GLB_CHC2_SAMPLEDELAY
#define GLB_CHC2_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                              0x0
#define GLB_CHC2_SAMPLEDELAY__RESERVED__SHIFT                                                                 0x6
#define GLB_CHC2_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                0x0000003FL
#define GLB_CHC2_SAMPLEDELAY__RESERVED_MASK                                                                   0xFFFFFFC0L
//GLB_CHC3_SAMPLEDELAY
#define GLB_CHC3_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                              0x0
#define GLB_CHC3_SAMPLEDELAY__RESERVED__SHIFT                                                                 0x6
#define GLB_CHC3_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                0x0000003FL
#define GLB_CHC3_SAMPLEDELAY__RESERVED_MASK                                                                   0xFFFFFFC0L
//GLB_GE2SE0_SAMPLEDELAY
#define GLB_GE2SE0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                            0x0
#define GLB_GE2SE0_SAMPLEDELAY__RESERVED__SHIFT                                                               0x6
#define GLB_GE2SE0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                              0x0000003FL
#define GLB_GE2SE0_SAMPLEDELAY__RESERVED_MASK                                                                 0xFFFFFFC0L
//GLB_GE2SE1_SAMPLEDELAY
#define GLB_GE2SE1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                            0x0
#define GLB_GE2SE1_SAMPLEDELAY__RESERVED__SHIFT                                                               0x6
#define GLB_GE2SE1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                              0x0000003FL
#define GLB_GE2SE1_SAMPLEDELAY__RESERVED_MASK                                                                 0xFFFFFFC0L
//GLB_GE2SE2_SAMPLEDELAY
#define GLB_GE2SE2_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                            0x0
#define GLB_GE2SE2_SAMPLEDELAY__RESERVED__SHIFT                                                               0x6
#define GLB_GE2SE2_SAMPLEDELAY__SAMPLEDELAY_MASK                                                              0x0000003FL
#define GLB_GE2SE2_SAMPLEDELAY__RESERVED_MASK                                                                 0xFFFFFFC0L
//GLB_GE2SE3_SAMPLEDELAY
#define GLB_GE2SE3_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                            0x0
#define GLB_GE2SE3_SAMPLEDELAY__RESERVED__SHIFT                                                               0x6
#define GLB_GE2SE3_SAMPLEDELAY__SAMPLEDELAY_MASK                                                              0x0000003FL
#define GLB_GE2SE3_SAMPLEDELAY__RESERVED_MASK                                                                 0xFFFFFFC0L


// addressBlock: spmind
//SE_SPI_SAMPLEDELAY
#define SE_SPI_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                                0x0
#define SE_SPI_SAMPLEDELAY__RESERVED__SHIFT                                                                   0x6
#define SE_SPI_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                  0x0000003FL
#define SE_SPI_SAMPLEDELAY__RESERVED_MASK                                                                     0xFFFFFFC0L
//SE_SQG_SAMPLEDELAY
#define SE_SQG_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                                0x0
#define SE_SQG_SAMPLEDELAY__RESERVED__SHIFT                                                                   0x6
#define SE_SQG_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                  0x0000003FL
#define SE_SQG_SAMPLEDELAY__RESERVED_MASK                                                                     0xFFFFFFC0L
//SE_CBR_SAMPLEDELAY
#define SE_CBR_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                                0x0
#define SE_CBR_SAMPLEDELAY__RESERVED__SHIFT                                                                   0x6
#define SE_CBR_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                  0x0000003FL
#define SE_CBR_SAMPLEDELAY__RESERVED_MASK                                                                     0xFFFFFFC0L
//SE_DBR_SAMPLEDELAY
#define SE_DBR_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                                0x0
#define SE_DBR_SAMPLEDELAY__RESERVED__SHIFT                                                                   0x6
#define SE_DBR_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                  0x0000003FL
#define SE_DBR_SAMPLEDELAY__RESERVED_MASK                                                                     0xFFFFFFC0L
//SE_PA_SAMPLEDELAY
#define SE_PA_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                                 0x0
#define SE_PA_SAMPLEDELAY__RESERVED__SHIFT                                                                    0x6
#define SE_PA_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                   0x0000003FL
#define SE_PA_SAMPLEDELAY__RESERVED_MASK                                                                      0xFFFFFFC0L
//SE_SA0SX_SAMPLEDELAY
#define SE_SA0SX_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                              0x0
#define SE_SA0SX_SAMPLEDELAY__RESERVED__SHIFT                                                                 0x6
#define SE_SA0SX_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                0x0000003FL
#define SE_SA0SX_SAMPLEDELAY__RESERVED_MASK                                                                   0xFFFFFFC0L
//SE_SA0GL1A_SAMPLEDELAY
#define SE_SA0GL1A_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                            0x0
#define SE_SA0GL1A_SAMPLEDELAY__RESERVED__SHIFT                                                               0x6
#define SE_SA0GL1A_SAMPLEDELAY__SAMPLEDELAY_MASK                                                              0x0000003FL
#define SE_SA0GL1A_SAMPLEDELAY__RESERVED_MASK                                                                 0xFFFFFFC0L
//SE_SA0GL1CG_SAMPLEDELAY
#define SE_SA0GL1CG_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                           0x0
#define SE_SA0GL1CG_SAMPLEDELAY__RESERVED__SHIFT                                                              0x6
#define SE_SA0GL1CG_SAMPLEDELAY__SAMPLEDELAY_MASK                                                             0x0000003FL
#define SE_SA0GL1CG_SAMPLEDELAY__RESERVED_MASK                                                                0xFFFFFFC0L
//SE_SA0CB0_SAMPLEDELAY
#define SE_SA0CB0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
#define SE_SA0CB0_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
#define SE_SA0CB0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
#define SE_SA0CB0_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
//SE_SA0CB1_SAMPLEDELAY
#define SE_SA0CB1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
#define SE_SA0CB1_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
#define SE_SA0CB1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
#define SE_SA0CB1_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
//SE_SA0DB0_SAMPLEDELAY
#define SE_SA0DB0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
#define SE_SA0DB0_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
#define SE_SA0DB0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
#define SE_SA0DB0_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
//SE_SA0DB1_SAMPLEDELAY
#define SE_SA0DB1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
#define SE_SA0DB1_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
#define SE_SA0DB1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
#define SE_SA0DB1_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
//SE_SA0SC0_SAMPLEDELAY
#define SE_SA0SC0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
#define SE_SA0SC0_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
#define SE_SA0SC0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
#define SE_SA0SC0_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
//SE_SA0SC1_SAMPLEDELAY
#define SE_SA0SC1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
#define SE_SA0SC1_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
#define SE_SA0SC1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
#define SE_SA0SC1_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
//SE_SA0RMI0_SAMPLEDELAY
#define SE_SA0RMI0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                            0x0
#define SE_SA0RMI0_SAMPLEDELAY__RESERVED__SHIFT                                                               0x6
#define SE_SA0RMI0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                              0x0000003FL
#define SE_SA0RMI0_SAMPLEDELAY__RESERVED_MASK                                                                 0xFFFFFFC0L
//SE_SA0RMI1_SAMPLEDELAY
#define SE_SA0RMI1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                            0x0
#define SE_SA0RMI1_SAMPLEDELAY__RESERVED__SHIFT                                                               0x6
#define SE_SA0RMI1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                              0x0000003FL
#define SE_SA0RMI1_SAMPLEDELAY__RESERVED_MASK                                                                 0xFFFFFFC0L
//SE_SA0GL1C0_SAMPLEDELAY
#define SE_SA0GL1C0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                           0x0
#define SE_SA0GL1C0_SAMPLEDELAY__RESERVED__SHIFT                                                              0x6
#define SE_SA0GL1C0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                             0x0000003FL
#define SE_SA0GL1C0_SAMPLEDELAY__RESERVED_MASK                                                                0xFFFFFFC0L
//SE_SA0GL1C1_SAMPLEDELAY
#define SE_SA0GL1C1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                           0x0
#define SE_SA0GL1C1_SAMPLEDELAY__RESERVED__SHIFT                                                              0x6
#define SE_SA0GL1C1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                             0x0000003FL
#define SE_SA0GL1C1_SAMPLEDELAY__RESERVED_MASK                                                                0xFFFFFFC0L
//SE_SA0GL1C2_SAMPLEDELAY
#define SE_SA0GL1C2_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                           0x0
#define SE_SA0GL1C2_SAMPLEDELAY__RESERVED__SHIFT                                                              0x6
#define SE_SA0GL1C2_SAMPLEDELAY__SAMPLEDELAY_MASK                                                             0x0000003FL
#define SE_SA0GL1C2_SAMPLEDELAY__RESERVED_MASK                                                                0xFFFFFFC0L
//SE_SA0GL1C3_SAMPLEDELAY
#define SE_SA0GL1C3_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                           0x0
#define SE_SA0GL1C3_SAMPLEDELAY__RESERVED__SHIFT                                                              0x6
#define SE_SA0GL1C3_SAMPLEDELAY__SAMPLEDELAY_MASK                                                             0x0000003FL
#define SE_SA0GL1C3_SAMPLEDELAY__RESERVED_MASK                                                                0xFFFFFFC0L
//SE_SA0WGP00TA0_SAMPLEDELAY
#define SE_SA0WGP00TA0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
#define SE_SA0WGP00TA0_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
#define SE_SA0WGP00TA0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
#define SE_SA0WGP00TA0_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
//SE_SA0WGP00TA1_SAMPLEDELAY
#define SE_SA0WGP00TA1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
#define SE_SA0WGP00TA1_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
#define SE_SA0WGP00TA1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
#define SE_SA0WGP00TA1_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
//SE_SA0WGP00TD0_SAMPLEDELAY
#define SE_SA0WGP00TD0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
#define SE_SA0WGP00TD0_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
#define SE_SA0WGP00TD0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
#define SE_SA0WGP00TD0_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
//SE_SA0WGP00TD1_SAMPLEDELAY
#define SE_SA0WGP00TD1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
#define SE_SA0WGP00TD1_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
#define SE_SA0WGP00TD1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
#define SE_SA0WGP00TD1_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
//SE_SA0WGP00TCP0_SAMPLEDELAY
#define SE_SA0WGP00TCP0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                       0x0
#define SE_SA0WGP00TCP0_SAMPLEDELAY__RESERVED__SHIFT                                                          0x6
#define SE_SA0WGP00TCP0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                         0x0000003FL
#define SE_SA0WGP00TCP0_SAMPLEDELAY__RESERVED_MASK                                                            0xFFFFFFC0L
//SE_SA0WGP00TCP1_SAMPLEDELAY
#define SE_SA0WGP00TCP1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                       0x0
#define SE_SA0WGP00TCP1_SAMPLEDELAY__RESERVED__SHIFT                                                          0x6
#define SE_SA0WGP00TCP1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                         0x0000003FL
#define SE_SA0WGP00TCP1_SAMPLEDELAY__RESERVED_MASK                                                            0xFFFFFFC0L
//SE_SA0WGP01TA0_SAMPLEDELAY
#define SE_SA0WGP01TA0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
#define SE_SA0WGP01TA0_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
#define SE_SA0WGP01TA0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
#define SE_SA0WGP01TA0_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
//SE_SA0WGP01TA1_SAMPLEDELAY
#define SE_SA0WGP01TA1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
#define SE_SA0WGP01TA1_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
#define SE_SA0WGP01TA1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
#define SE_SA0WGP01TA1_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
//SE_SA0WGP01TD0_SAMPLEDELAY
#define SE_SA0WGP01TD0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
#define SE_SA0WGP01TD0_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
#define SE_SA0WGP01TD0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
#define SE_SA0WGP01TD0_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
//SE_SA0WGP01TD1_SAMPLEDELAY
#define SE_SA0WGP01TD1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
#define SE_SA0WGP01TD1_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
#define SE_SA0WGP01TD1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
#define SE_SA0WGP01TD1_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
//SE_SA0WGP01TCP0_SAMPLEDELAY
#define SE_SA0WGP01TCP0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                       0x0
#define SE_SA0WGP01TCP0_SAMPLEDELAY__RESERVED__SHIFT                                                          0x6
#define SE_SA0WGP01TCP0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                         0x0000003FL
#define SE_SA0WGP01TCP0_SAMPLEDELAY__RESERVED_MASK                                                            0xFFFFFFC0L
//SE_SA0WGP01TCP1_SAMPLEDELAY
#define SE_SA0WGP01TCP1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                       0x0
#define SE_SA0WGP01TCP1_SAMPLEDELAY__RESERVED__SHIFT                                                          0x6
#define SE_SA0WGP01TCP1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                         0x0000003FL
#define SE_SA0WGP01TCP1_SAMPLEDELAY__RESERVED_MASK                                                            0xFFFFFFC0L
//SE_SA0WGP02TA0_SAMPLEDELAY
#define SE_SA0WGP02TA0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
#define SE_SA0WGP02TA0_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
#define SE_SA0WGP02TA0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
#define SE_SA0WGP02TA0_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
//SE_SA0WGP02TA1_SAMPLEDELAY
#define SE_SA0WGP02TA1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
#define SE_SA0WGP02TA1_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
#define SE_SA0WGP02TA1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
#define SE_SA0WGP02TA1_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
//SE_SA0WGP02TD0_SAMPLEDELAY
#define SE_SA0WGP02TD0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
#define SE_SA0WGP02TD0_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
#define SE_SA0WGP02TD0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
#define SE_SA0WGP02TD0_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
//SE_SA0WGP02TD1_SAMPLEDELAY
#define SE_SA0WGP02TD1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
#define SE_SA0WGP02TD1_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
#define SE_SA0WGP02TD1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
#define SE_SA0WGP02TD1_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
//SE_SA0WGP02TCP0_SAMPLEDELAY
#define SE_SA0WGP02TCP0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                       0x0
#define SE_SA0WGP02TCP0_SAMPLEDELAY__RESERVED__SHIFT                                                          0x6
#define SE_SA0WGP02TCP0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                         0x0000003FL
#define SE_SA0WGP02TCP0_SAMPLEDELAY__RESERVED_MASK                                                            0xFFFFFFC0L
//SE_SA0WGP02TCP1_SAMPLEDELAY
#define SE_SA0WGP02TCP1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                       0x0
#define SE_SA0WGP02TCP1_SAMPLEDELAY__RESERVED__SHIFT                                                          0x6
#define SE_SA0WGP02TCP1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                         0x0000003FL
#define SE_SA0WGP02TCP1_SAMPLEDELAY__RESERVED_MASK                                                            0xFFFFFFC0L
//SE_SA0WGP03TA0_SAMPLEDELAY
#define SE_SA0WGP03TA0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
#define SE_SA0WGP03TA0_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
#define SE_SA0WGP03TA0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
#define SE_SA0WGP03TA0_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
//SE_SA0WGP03TA1_SAMPLEDELAY
#define SE_SA0WGP03TA1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
#define SE_SA0WGP03TA1_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
#define SE_SA0WGP03TA1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
#define SE_SA0WGP03TA1_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
//SE_SA0WGP03TD0_SAMPLEDELAY
#define SE_SA0WGP03TD0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
#define SE_SA0WGP03TD0_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
#define SE_SA0WGP03TD0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
#define SE_SA0WGP03TD0_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
//SE_SA0WGP03TD1_SAMPLEDELAY
#define SE_SA0WGP03TD1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
#define SE_SA0WGP03TD1_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
#define SE_SA0WGP03TD1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
#define SE_SA0WGP03TD1_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
//SE_SA0WGP03TCP0_SAMPLEDELAY
#define SE_SA0WGP03TCP0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                       0x0
#define SE_SA0WGP03TCP0_SAMPLEDELAY__RESERVED__SHIFT                                                          0x6
#define SE_SA0WGP03TCP0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                         0x0000003FL
#define SE_SA0WGP03TCP0_SAMPLEDELAY__RESERVED_MASK                                                            0xFFFFFFC0L
//SE_SA0WGP03TCP1_SAMPLEDELAY
#define SE_SA0WGP03TCP1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                       0x0
#define SE_SA0WGP03TCP1_SAMPLEDELAY__RESERVED__SHIFT                                                          0x6
#define SE_SA0WGP03TCP1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                         0x0000003FL
#define SE_SA0WGP03TCP1_SAMPLEDELAY__RESERVED_MASK                                                            0xFFFFFFC0L
//SE_SA0WGP04TA0_SAMPLEDELAY
#define SE_SA0WGP04TA0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
#define SE_SA0WGP04TA0_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
#define SE_SA0WGP04TA0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
#define SE_SA0WGP04TA0_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
//SE_SA0WGP04TA1_SAMPLEDELAY
#define SE_SA0WGP04TA1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
#define SE_SA0WGP04TA1_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
#define SE_SA0WGP04TA1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
#define SE_SA0WGP04TA1_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
//SE_SA0WGP04TD0_SAMPLEDELAY
#define SE_SA0WGP04TD0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
#define SE_SA0WGP04TD0_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
#define SE_SA0WGP04TD0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
#define SE_SA0WGP04TD0_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
//SE_SA0WGP04TD1_SAMPLEDELAY
#define SE_SA0WGP04TD1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
#define SE_SA0WGP04TD1_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
#define SE_SA0WGP04TD1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
#define SE_SA0WGP04TD1_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
//SE_SA0WGP04TCP0_SAMPLEDELAY
#define SE_SA0WGP04TCP0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                       0x0
#define SE_SA0WGP04TCP0_SAMPLEDELAY__RESERVED__SHIFT                                                          0x6
#define SE_SA0WGP04TCP0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                         0x0000003FL
#define SE_SA0WGP04TCP0_SAMPLEDELAY__RESERVED_MASK                                                            0xFFFFFFC0L
//SE_SA0WGP04TCP1_SAMPLEDELAY
#define SE_SA0WGP04TCP1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                       0x0
#define SE_SA0WGP04TCP1_SAMPLEDELAY__RESERVED__SHIFT                                                          0x6
#define SE_SA0WGP04TCP1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                         0x0000003FL
#define SE_SA0WGP04TCP1_SAMPLEDELAY__RESERVED_MASK                                                            0xFFFFFFC0L
//SE_SA1SX_SAMPLEDELAY
#define SE_SA1SX_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                              0x0
#define SE_SA1SX_SAMPLEDELAY__RESERVED__SHIFT                                                                 0x6
#define SE_SA1SX_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                0x0000003FL
#define SE_SA1SX_SAMPLEDELAY__RESERVED_MASK                                                                   0xFFFFFFC0L
//SE_SA1GL1A_SAMPLEDELAY
#define SE_SA1GL1A_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                            0x0
#define SE_SA1GL1A_SAMPLEDELAY__RESERVED__SHIFT                                                               0x6
#define SE_SA1GL1A_SAMPLEDELAY__SAMPLEDELAY_MASK                                                              0x0000003FL
#define SE_SA1GL1A_SAMPLEDELAY__RESERVED_MASK                                                                 0xFFFFFFC0L
//SE_SA1GL1CG_SAMPLEDELAY
#define SE_SA1GL1CG_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                           0x0
#define SE_SA1GL1CG_SAMPLEDELAY__RESERVED__SHIFT                                                              0x6
#define SE_SA1GL1CG_SAMPLEDELAY__SAMPLEDELAY_MASK                                                             0x0000003FL
#define SE_SA1GL1CG_SAMPLEDELAY__RESERVED_MASK                                                                0xFFFFFFC0L
//SE_SA1CB0_SAMPLEDELAY
#define SE_SA1CB0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
#define SE_SA1CB0_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
#define SE_SA1CB0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
#define SE_SA1CB0_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
//SE_SA1CB1_SAMPLEDELAY
#define SE_SA1CB1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
#define SE_SA1CB1_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
#define SE_SA1CB1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
#define SE_SA1CB1_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
//SE_SA1DB0_SAMPLEDELAY
#define SE_SA1DB0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
#define SE_SA1DB0_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
#define SE_SA1DB0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
#define SE_SA1DB0_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
//SE_SA1DB1_SAMPLEDELAY
#define SE_SA1DB1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
#define SE_SA1DB1_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
#define SE_SA1DB1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
#define SE_SA1DB1_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
//SE_SA1SC0_SAMPLEDELAY
#define SE_SA1SC0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
#define SE_SA1SC0_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
#define SE_SA1SC0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
#define SE_SA1SC0_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
//SE_SA1SC1_SAMPLEDELAY
#define SE_SA1SC1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
#define SE_SA1SC1_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
#define SE_SA1SC1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
#define SE_SA1SC1_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
//SE_SA1RMI0_SAMPLEDELAY
#define SE_SA1RMI0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                            0x0
#define SE_SA1RMI0_SAMPLEDELAY__RESERVED__SHIFT                                                               0x6
#define SE_SA1RMI0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                              0x0000003FL
#define SE_SA1RMI0_SAMPLEDELAY__RESERVED_MASK                                                                 0xFFFFFFC0L
//SE_SA1RMI1_SAMPLEDELAY
#define SE_SA1RMI1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                            0x0
#define SE_SA1RMI1_SAMPLEDELAY__RESERVED__SHIFT                                                               0x6
#define SE_SA1RMI1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                              0x0000003FL
#define SE_SA1RMI1_SAMPLEDELAY__RESERVED_MASK                                                                 0xFFFFFFC0L
//SE_SA1GL1C0_SAMPLEDELAY
#define SE_SA1GL1C0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                           0x0
#define SE_SA1GL1C0_SAMPLEDELAY__RESERVED__SHIFT                                                              0x6
#define SE_SA1GL1C0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                             0x0000003FL
#define SE_SA1GL1C0_SAMPLEDELAY__RESERVED_MASK                                                                0xFFFFFFC0L
//SE_SA1GL1C1_SAMPLEDELAY
#define SE_SA1GL1C1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                           0x0
#define SE_SA1GL1C1_SAMPLEDELAY__RESERVED__SHIFT                                                              0x6
#define SE_SA1GL1C1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                             0x0000003FL
#define SE_SA1GL1C1_SAMPLEDELAY__RESERVED_MASK                                                                0xFFFFFFC0L
//SE_SA1GL1C2_SAMPLEDELAY
#define SE_SA1GL1C2_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                           0x0
#define SE_SA1GL1C2_SAMPLEDELAY__RESERVED__SHIFT                                                              0x6
#define SE_SA1GL1C2_SAMPLEDELAY__SAMPLEDELAY_MASK                                                             0x0000003FL
#define SE_SA1GL1C2_SAMPLEDELAY__RESERVED_MASK                                                                0xFFFFFFC0L
//SE_SA1GL1C3_SAMPLEDELAY
#define SE_SA1GL1C3_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                           0x0
#define SE_SA1GL1C3_SAMPLEDELAY__RESERVED__SHIFT                                                              0x6
#define SE_SA1GL1C3_SAMPLEDELAY__SAMPLEDELAY_MASK                                                             0x0000003FL
#define SE_SA1GL1C3_SAMPLEDELAY__RESERVED_MASK                                                                0xFFFFFFC0L
//SE_SA1WGP00TA0_SAMPLEDELAY
#define SE_SA1WGP00TA0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
#define SE_SA1WGP00TA0_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
#define SE_SA1WGP00TA0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
#define SE_SA1WGP00TA0_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
//SE_SA1WGP00TA1_SAMPLEDELAY
#define SE_SA1WGP00TA1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
#define SE_SA1WGP00TA1_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
#define SE_SA1WGP00TA1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
#define SE_SA1WGP00TA1_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
//SE_SA1WGP00TD0_SAMPLEDELAY
#define SE_SA1WGP00TD0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
#define SE_SA1WGP00TD0_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
#define SE_SA1WGP00TD0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
#define SE_SA1WGP00TD0_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
//SE_SA1WGP00TD1_SAMPLEDELAY
#define SE_SA1WGP00TD1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
#define SE_SA1WGP00TD1_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
#define SE_SA1WGP00TD1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
#define SE_SA1WGP00TD1_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
//SE_SA1WGP00TCP0_SAMPLEDELAY
#define SE_SA1WGP00TCP0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                       0x0
#define SE_SA1WGP00TCP0_SAMPLEDELAY__RESERVED__SHIFT                                                          0x6
#define SE_SA1WGP00TCP0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                         0x0000003FL
#define SE_SA1WGP00TCP0_SAMPLEDELAY__RESERVED_MASK                                                            0xFFFFFFC0L
//SE_SA1WGP00TCP1_SAMPLEDELAY
#define SE_SA1WGP00TCP1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                       0x0
#define SE_SA1WGP00TCP1_SAMPLEDELAY__RESERVED__SHIFT                                                          0x6
#define SE_SA1WGP00TCP1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                         0x0000003FL
#define SE_SA1WGP00TCP1_SAMPLEDELAY__RESERVED_MASK                                                            0xFFFFFFC0L
//SE_SA1WGP01TA0_SAMPLEDELAY
#define SE_SA1WGP01TA0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
#define SE_SA1WGP01TA0_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
#define SE_SA1WGP01TA0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
#define SE_SA1WGP01TA0_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
//SE_SA1WGP01TA1_SAMPLEDELAY
#define SE_SA1WGP01TA1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
#define SE_SA1WGP01TA1_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
#define SE_SA1WGP01TA1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
#define SE_SA1WGP01TA1_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
//SE_SA1WGP01TD0_SAMPLEDELAY
#define SE_SA1WGP01TD0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
#define SE_SA1WGP01TD0_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
#define SE_SA1WGP01TD0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
#define SE_SA1WGP01TD0_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
//SE_SA1WGP01TD1_SAMPLEDELAY
#define SE_SA1WGP01TD1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
#define SE_SA1WGP01TD1_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
#define SE_SA1WGP01TD1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
#define SE_SA1WGP01TD1_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
//SE_SA1WGP01TCP0_SAMPLEDELAY
#define SE_SA1WGP01TCP0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                       0x0
#define SE_SA1WGP01TCP0_SAMPLEDELAY__RESERVED__SHIFT                                                          0x6
#define SE_SA1WGP01TCP0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                         0x0000003FL
#define SE_SA1WGP01TCP0_SAMPLEDELAY__RESERVED_MASK                                                            0xFFFFFFC0L
//SE_SA1WGP01TCP1_SAMPLEDELAY
#define SE_SA1WGP01TCP1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                       0x0
#define SE_SA1WGP01TCP1_SAMPLEDELAY__RESERVED__SHIFT                                                          0x6
#define SE_SA1WGP01TCP1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                         0x0000003FL
#define SE_SA1WGP01TCP1_SAMPLEDELAY__RESERVED_MASK                                                            0xFFFFFFC0L
//SE_SA1WGP02TA0_SAMPLEDELAY
#define SE_SA1WGP02TA0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
#define SE_SA1WGP02TA0_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
#define SE_SA1WGP02TA0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
#define SE_SA1WGP02TA0_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
//SE_SA1WGP02TA1_SAMPLEDELAY
#define SE_SA1WGP02TA1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
#define SE_SA1WGP02TA1_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
#define SE_SA1WGP02TA1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
#define SE_SA1WGP02TA1_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
//SE_SA1WGP02TD0_SAMPLEDELAY
#define SE_SA1WGP02TD0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
#define SE_SA1WGP02TD0_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
#define SE_SA1WGP02TD0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
#define SE_SA1WGP02TD0_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
//SE_SA1WGP02TD1_SAMPLEDELAY
#define SE_SA1WGP02TD1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
#define SE_SA1WGP02TD1_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
#define SE_SA1WGP02TD1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
#define SE_SA1WGP02TD1_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
//SE_SA1WGP02TCP0_SAMPLEDELAY
#define SE_SA1WGP02TCP0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                       0x0
#define SE_SA1WGP02TCP0_SAMPLEDELAY__RESERVED__SHIFT                                                          0x6
#define SE_SA1WGP02TCP0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                         0x0000003FL
#define SE_SA1WGP02TCP0_SAMPLEDELAY__RESERVED_MASK                                                            0xFFFFFFC0L
//SE_SA1WGP02TCP1_SAMPLEDELAY
#define SE_SA1WGP02TCP1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                       0x0
#define SE_SA1WGP02TCP1_SAMPLEDELAY__RESERVED__SHIFT                                                          0x6
#define SE_SA1WGP02TCP1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                         0x0000003FL
#define SE_SA1WGP02TCP1_SAMPLEDELAY__RESERVED_MASK                                                            0xFFFFFFC0L
//SE_SA1WGP03TA0_SAMPLEDELAY
#define SE_SA1WGP03TA0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
#define SE_SA1WGP03TA0_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
#define SE_SA1WGP03TA0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
#define SE_SA1WGP03TA0_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
//SE_SA1WGP03TA1_SAMPLEDELAY
#define SE_SA1WGP03TA1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
#define SE_SA1WGP03TA1_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
#define SE_SA1WGP03TA1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
#define SE_SA1WGP03TA1_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
//SE_SA1WGP03TD0_SAMPLEDELAY
#define SE_SA1WGP03TD0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
#define SE_SA1WGP03TD0_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
#define SE_SA1WGP03TD0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
#define SE_SA1WGP03TD0_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
//SE_SA1WGP03TD1_SAMPLEDELAY
#define SE_SA1WGP03TD1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
#define SE_SA1WGP03TD1_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
#define SE_SA1WGP03TD1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
#define SE_SA1WGP03TD1_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
//SE_SA1WGP03TCP0_SAMPLEDELAY
#define SE_SA1WGP03TCP0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                       0x0
#define SE_SA1WGP03TCP0_SAMPLEDELAY__RESERVED__SHIFT                                                          0x6
#define SE_SA1WGP03TCP0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                         0x0000003FL
#define SE_SA1WGP03TCP0_SAMPLEDELAY__RESERVED_MASK                                                            0xFFFFFFC0L
//SE_SA1WGP03TCP1_SAMPLEDELAY
#define SE_SA1WGP03TCP1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                       0x0
#define SE_SA1WGP03TCP1_SAMPLEDELAY__RESERVED__SHIFT                                                          0x6
#define SE_SA1WGP03TCP1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                         0x0000003FL
#define SE_SA1WGP03TCP1_SAMPLEDELAY__RESERVED_MASK                                                            0xFFFFFFC0L
//SE_SA1WGP04TA0_SAMPLEDELAY
#define SE_SA1WGP04TA0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
#define SE_SA1WGP04TA0_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
#define SE_SA1WGP04TA0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
#define SE_SA1WGP04TA0_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
//SE_SA1WGP04TA1_SAMPLEDELAY
#define SE_SA1WGP04TA1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
#define SE_SA1WGP04TA1_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
#define SE_SA1WGP04TA1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
#define SE_SA1WGP04TA1_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
//SE_SA1WGP04TD0_SAMPLEDELAY
#define SE_SA1WGP04TD0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
#define SE_SA1WGP04TD0_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
#define SE_SA1WGP04TD0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
#define SE_SA1WGP04TD0_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
//SE_SA1WGP04TD1_SAMPLEDELAY
#define SE_SA1WGP04TD1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
#define SE_SA1WGP04TD1_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
#define SE_SA1WGP04TD1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
#define SE_SA1WGP04TD1_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
//SE_SA1WGP04TCP0_SAMPLEDELAY
#define SE_SA1WGP04TCP0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                       0x0
#define SE_SA1WGP04TCP0_SAMPLEDELAY__RESERVED__SHIFT                                                          0x6
#define SE_SA1WGP04TCP0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                         0x0000003FL
#define SE_SA1WGP04TCP0_SAMPLEDELAY__RESERVED_MASK                                                            0xFFFFFFC0L
//SE_SA1WGP04TCP1_SAMPLEDELAY
#define SE_SA1WGP04TCP1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                       0x0
#define SE_SA1WGP04TCP1_SAMPLEDELAY__RESERVED__SHIFT                                                          0x6
#define SE_SA1WGP04TCP1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                         0x0000003FL
#define SE_SA1WGP04TCP1_SAMPLEDELAY__RESERVED_MASK                                                            0xFFFFFFC0L




// addressBlock: grtavfsind
//RTAVFS_REG0
#define RTAVFS_REG0__RTAVFSCPO0_STARTCNT__SHIFT                                                               0x0
#define RTAVFS_REG0__RTAVFSCPO0_STOPCNT__SHIFT                                                                0x10
#define RTAVFS_REG0__RTAVFSCPO0_STARTCNT_MASK                                                                 0x0000FFFFL
#define RTAVFS_REG0__RTAVFSCPO0_STOPCNT_MASK                                                                  0xFFFF0000L
//RTAVFS_REG1
#define RTAVFS_REG1__RTAVFSCPO0_RIPPLECNT__SHIFT                                                              0x0
#define RTAVFS_REG1__RESERVED__SHIFT                                                                          0x10
#define RTAVFS_REG1__RTAVFSCPO0_RIPPLECNT_MASK                                                                0x0000FFFFL
#define RTAVFS_REG1__RESERVED_MASK                                                                            0xFFFF0000L
//RTAVFS_REG2
#define RTAVFS_REG2__RTAVFSCPO1_STARTCNT__SHIFT                                                               0x0
#define RTAVFS_REG2__RTAVFSCPO1_STOPCNT__SHIFT                                                                0x10
#define RTAVFS_REG2__RTAVFSCPO1_STARTCNT_MASK                                                                 0x0000FFFFL
#define RTAVFS_REG2__RTAVFSCPO1_STOPCNT_MASK                                                                  0xFFFF0000L
//RTAVFS_REG3
#define RTAVFS_REG3__RTAVFSCPO1_RIPPLECNT__SHIFT                                                              0x0
#define RTAVFS_REG3__RESERVED__SHIFT                                                                          0x10
#define RTAVFS_REG3__RTAVFSCPO1_RIPPLECNT_MASK                                                                0x0000FFFFL
#define RTAVFS_REG3__RESERVED_MASK                                                                            0xFFFF0000L
//RTAVFS_REG4
#define RTAVFS_REG4__RTAVFSCPO2_STARTCNT__SHIFT                                                               0x0
#define RTAVFS_REG4__RTAVFSCPO2_STOPCNT__SHIFT                                                                0x10
#define RTAVFS_REG4__RTAVFSCPO2_STARTCNT_MASK                                                                 0x0000FFFFL
#define RTAVFS_REG4__RTAVFSCPO2_STOPCNT_MASK                                                                  0xFFFF0000L
//RTAVFS_REG5
#define RTAVFS_REG5__RTAVFSCPO2_RIPPLECNT__SHIFT                                                              0x0
#define RTAVFS_REG5__RESERVED__SHIFT                                                                          0x10
#define RTAVFS_REG5__RTAVFSCPO2_RIPPLECNT_MASK                                                                0x0000FFFFL
#define RTAVFS_REG5__RESERVED_MASK                                                                            0xFFFF0000L
//RTAVFS_REG6
#define RTAVFS_REG6__RTAVFSCPO3_STARTCNT__SHIFT                                                               0x0
#define RTAVFS_REG6__RTAVFSCPO3_STOPCNT__SHIFT                                                                0x10
#define RTAVFS_REG6__RTAVFSCPO3_STARTCNT_MASK                                                                 0x0000FFFFL
#define RTAVFS_REG6__RTAVFSCPO3_STOPCNT_MASK                                                                  0xFFFF0000L
//RTAVFS_REG7
#define RTAVFS_REG7__RTAVFSCPO3_RIPPLECNT__SHIFT                                                              0x0
#define RTAVFS_REG7__RESERVED__SHIFT                                                                          0x10
#define RTAVFS_REG7__RTAVFSCPO3_RIPPLECNT_MASK                                                                0x0000FFFFL
#define RTAVFS_REG7__RESERVED_MASK                                                                            0xFFFF0000L
//RTAVFS_REG8
#define RTAVFS_REG8__RTAVFSCPO4_STARTCNT__SHIFT                                                               0x0
#define RTAVFS_REG8__RTAVFSCPO4_STOPCNT__SHIFT                                                                0x10
#define RTAVFS_REG8__RTAVFSCPO4_STARTCNT_MASK                                                                 0x0000FFFFL
#define RTAVFS_REG8__RTAVFSCPO4_STOPCNT_MASK                                                                  0xFFFF0000L
//RTAVFS_REG9
#define RTAVFS_REG9__RTAVFSCPO4_RIPPLECNT__SHIFT                                                              0x0
#define RTAVFS_REG9__RESERVED__SHIFT                                                                          0x10
#define RTAVFS_REG9__RTAVFSCPO4_RIPPLECNT_MASK                                                                0x0000FFFFL
#define RTAVFS_REG9__RESERVED_MASK                                                                            0xFFFF0000L
//RTAVFS_REG10
#define RTAVFS_REG10__RTAVFSCPO5_STARTCNT__SHIFT                                                              0x0
#define RTAVFS_REG10__RTAVFSCPO5_STOPCNT__SHIFT                                                               0x10
#define RTAVFS_REG10__RTAVFSCPO5_STARTCNT_MASK                                                                0x0000FFFFL
#define RTAVFS_REG10__RTAVFSCPO5_STOPCNT_MASK                                                                 0xFFFF0000L
//RTAVFS_REG11
#define RTAVFS_REG11__RTAVFSCPO5_RIPPLECNT__SHIFT                                                             0x0
#define RTAVFS_REG11__RESERVED__SHIFT                                                                         0x10
#define RTAVFS_REG11__RTAVFSCPO5_RIPPLECNT_MASK                                                               0x0000FFFFL
#define RTAVFS_REG11__RESERVED_MASK                                                                           0xFFFF0000L
//RTAVFS_REG12
#define RTAVFS_REG12__RTAVFSCPO6_STARTCNT__SHIFT                                                              0x0
#define RTAVFS_REG12__RTAVFSCPO6_STOPCNT__SHIFT                                                               0x10
#define RTAVFS_REG12__RTAVFSCPO6_STARTCNT_MASK                                                                0x0000FFFFL
#define RTAVFS_REG12__RTAVFSCPO6_STOPCNT_MASK                                                                 0xFFFF0000L
//RTAVFS_REG13
#define RTAVFS_REG13__RTAVFSCPO6_RIPPLECNT__SHIFT                                                             0x0
#define RTAVFS_REG13__RESERVED__SHIFT                                                                         0x10
#define RTAVFS_REG13__RTAVFSCPO6_RIPPLECNT_MASK                                                               0x0000FFFFL
#define RTAVFS_REG13__RESERVED_MASK                                                                           0xFFFF0000L
//RTAVFS_REG14
#define RTAVFS_REG14__RTAVFSCPO7_STARTCNT__SHIFT                                                              0x0
#define RTAVFS_REG14__RTAVFSCPO7_STOPCNT__SHIFT                                                               0x10
#define RTAVFS_REG14__RTAVFSCPO7_STARTCNT_MASK                                                                0x0000FFFFL
#define RTAVFS_REG14__RTAVFSCPO7_STOPCNT_MASK                                                                 0xFFFF0000L
//RTAVFS_REG15
#define RTAVFS_REG15__RTAVFSCPO7_RIPPLECNT__SHIFT                                                             0x0
#define RTAVFS_REG15__RESERVED__SHIFT                                                                         0x10
#define RTAVFS_REG15__RTAVFSCPO7_RIPPLECNT_MASK                                                               0x0000FFFFL
#define RTAVFS_REG15__RESERVED_MASK                                                                           0xFFFF0000L
//RTAVFS_REG16
#define RTAVFS_REG16__RTAVFSCPO8_STARTCNT__SHIFT                                                              0x0
#define RTAVFS_REG16__RTAVFSCPO8_STOPCNT__SHIFT                                                               0x10
#define RTAVFS_REG16__RTAVFSCPO8_STARTCNT_MASK                                                                0x0000FFFFL
#define RTAVFS_REG16__RTAVFSCPO8_STOPCNT_MASK                                                                 0xFFFF0000L
//RTAVFS_REG17
#define RTAVFS_REG17__RTAVFSCPO8_RIPPLECNT__SHIFT                                                             0x0
#define RTAVFS_REG17__RESERVED__SHIFT                                                                         0x10
#define RTAVFS_REG17__RTAVFSCPO8_RIPPLECNT_MASK                                                               0x0000FFFFL
#define RTAVFS_REG17__RESERVED_MASK                                                                           0xFFFF0000L
//RTAVFS_REG18
#define RTAVFS_REG18__RTAVFSCPO9_STARTCNT__SHIFT                                                              0x0
#define RTAVFS_REG18__RTAVFSCPO9_STOPCNT__SHIFT                                                               0x10
#define RTAVFS_REG18__RTAVFSCPO9_STARTCNT_MASK                                                                0x0000FFFFL
#define RTAVFS_REG18__RTAVFSCPO9_STOPCNT_MASK                                                                 0xFFFF0000L
//RTAVFS_REG19
#define RTAVFS_REG19__RTAVFSCPO9_RIPPLECNT__SHIFT                                                             0x0
#define RTAVFS_REG19__RESERVED__SHIFT                                                                         0x10
#define RTAVFS_REG19__RTAVFSCPO9_RIPPLECNT_MASK                                                               0x0000FFFFL
#define RTAVFS_REG19__RESERVED_MASK                                                                           0xFFFF0000L
//RTAVFS_REG20
#define RTAVFS_REG20__RTAVFSCPO10_STARTCNT__SHIFT                                                             0x0
#define RTAVFS_REG20__RTAVFSCPO10_STOPCNT__SHIFT                                                              0x10
#define RTAVFS_REG20__RTAVFSCPO10_STARTCNT_MASK                                                               0x0000FFFFL
#define RTAVFS_REG20__RTAVFSCPO10_STOPCNT_MASK                                                                0xFFFF0000L
//RTAVFS_REG21
#define RTAVFS_REG21__RTAVFSCPO10_RIPPLECNT__SHIFT                                                            0x0
#define RTAVFS_REG21__RESERVED__SHIFT                                                                         0x10
#define RTAVFS_REG21__RTAVFSCPO10_RIPPLECNT_MASK                                                              0x0000FFFFL
#define RTAVFS_REG21__RESERVED_MASK                                                                           0xFFFF0000L
//RTAVFS_REG22
#define RTAVFS_REG22__RTAVFSCPO11_STARTCNT__SHIFT                                                             0x0
#define RTAVFS_REG22__RTAVFSCPO11_STOPCNT__SHIFT                                                              0x10
#define RTAVFS_REG22__RTAVFSCPO11_STARTCNT_MASK                                                               0x0000FFFFL
#define RTAVFS_REG22__RTAVFSCPO11_STOPCNT_MASK                                                                0xFFFF0000L
//RTAVFS_REG23
#define RTAVFS_REG23__RTAVFSCPO11_RIPPLECNT__SHIFT                                                            0x0
#define RTAVFS_REG23__RESERVED__SHIFT                                                                         0x10
#define RTAVFS_REG23__RTAVFSCPO11_RIPPLECNT_MASK                                                              0x0000FFFFL
#define RTAVFS_REG23__RESERVED_MASK                                                                           0xFFFF0000L
//RTAVFS_REG24
#define RTAVFS_REG24__RTAVFSCPO12_STARTCNT__SHIFT                                                             0x0
#define RTAVFS_REG24__RTAVFSCPO12_STOPCNT__SHIFT                                                              0x10
#define RTAVFS_REG24__RTAVFSCPO12_STARTCNT_MASK                                                               0x0000FFFFL
#define RTAVFS_REG24__RTAVFSCPO12_STOPCNT_MASK                                                                0xFFFF0000L
//RTAVFS_REG25
#define RTAVFS_REG25__RTAVFSCPO12_RIPPLECNT__SHIFT                                                            0x0
#define RTAVFS_REG25__RESERVED__SHIFT                                                                         0x10
#define RTAVFS_REG25__RTAVFSCPO12_RIPPLECNT_MASK                                                              0x0000FFFFL
#define RTAVFS_REG25__RESERVED_MASK                                                                           0xFFFF0000L
//RTAVFS_REG26
#define RTAVFS_REG26__RTAVFSCPO13_STARTCNT__SHIFT                                                             0x0
#define RTAVFS_REG26__RTAVFSCPO13_STOPCNT__SHIFT                                                              0x10
#define RTAVFS_REG26__RTAVFSCPO13_STARTCNT_MASK                                                               0x0000FFFFL
#define RTAVFS_REG26__RTAVFSCPO13_STOPCNT_MASK                                                                0xFFFF0000L
//RTAVFS_REG27
#define RTAVFS_REG27__RTAVFSCPO13_RIPPLECNT__SHIFT                                                            0x0
#define RTAVFS_REG27__RESERVED__SHIFT                                                                         0x10
#define RTAVFS_REG27__RTAVFSCPO13_RIPPLECNT_MASK                                                              0x0000FFFFL
#define RTAVFS_REG27__RESERVED_MASK                                                                           0xFFFF0000L
//RTAVFS_REG28
#define RTAVFS_REG28__RTAVFSCPO14_STARTCNT__SHIFT                                                             0x0
#define RTAVFS_REG28__RTAVFSCPO14_STOPCNT__SHIFT                                                              0x10
#define RTAVFS_REG28__RTAVFSCPO14_STARTCNT_MASK                                                               0x0000FFFFL
#define RTAVFS_REG28__RTAVFSCPO14_STOPCNT_MASK                                                                0xFFFF0000L
//RTAVFS_REG29
#define RTAVFS_REG29__RTAVFSCPO14_RIPPLECNT__SHIFT                                                            0x0
#define RTAVFS_REG29__RESERVED__SHIFT                                                                         0x10
#define RTAVFS_REG29__RTAVFSCPO14_RIPPLECNT_MASK                                                              0x0000FFFFL
#define RTAVFS_REG29__RESERVED_MASK                                                                           0xFFFF0000L
//RTAVFS_REG30
#define RTAVFS_REG30__RTAVFSCPO15_STARTCNT__SHIFT                                                             0x0
#define RTAVFS_REG30__RTAVFSCPO15_STOPCNT__SHIFT                                                              0x10
#define RTAVFS_REG30__RTAVFSCPO15_STARTCNT_MASK                                                               0x0000FFFFL
#define RTAVFS_REG30__RTAVFSCPO15_STOPCNT_MASK                                                                0xFFFF0000L
//RTAVFS_REG31
#define RTAVFS_REG31__RTAVFSCPO15_RIPPLECNT__SHIFT                                                            0x0
#define RTAVFS_REG31__RESERVED__SHIFT                                                                         0x10
#define RTAVFS_REG31__RTAVFSCPO15_RIPPLECNT_MASK                                                              0x0000FFFFL
#define RTAVFS_REG31__RESERVED_MASK                                                                           0xFFFF0000L
//RTAVFS_REG32
#define RTAVFS_REG32__RTAVFSCPO16_STARTCNT__SHIFT                                                             0x0
#define RTAVFS_REG32__RTAVFSCPO16_STOPCNT__SHIFT                                                              0x10
#define RTAVFS_REG32__RTAVFSCPO16_STARTCNT_MASK                                                               0x0000FFFFL
#define RTAVFS_REG32__RTAVFSCPO16_STOPCNT_MASK                                                                0xFFFF0000L
//RTAVFS_REG33
#define RTAVFS_REG33__RTAVFSCPO16_RIPPLECNT__SHIFT                                                            0x0
#define RTAVFS_REG33__RESERVED__SHIFT                                                                         0x10
#define RTAVFS_REG33__RTAVFSCPO16_RIPPLECNT_MASK                                                              0x0000FFFFL
#define RTAVFS_REG33__RESERVED_MASK                                                                           0xFFFF0000L
//RTAVFS_REG34
#define RTAVFS_REG34__RTAVFSCPO17_STARTCNT__SHIFT                                                             0x0
#define RTAVFS_REG34__RTAVFSCPO17_STOPCNT__SHIFT                                                              0x10
#define RTAVFS_REG34__RTAVFSCPO17_STARTCNT_MASK                                                               0x0000FFFFL
#define RTAVFS_REG34__RTAVFSCPO17_STOPCNT_MASK                                                                0xFFFF0000L
//RTAVFS_REG35
#define RTAVFS_REG35__RTAVFSCPO17_RIPPLECNT__SHIFT                                                            0x0
#define RTAVFS_REG35__RESERVED__SHIFT                                                                         0x10
#define RTAVFS_REG35__RTAVFSCPO17_RIPPLECNT_MASK                                                              0x0000FFFFL
#define RTAVFS_REG35__RESERVED_MASK                                                                           0xFFFF0000L
//RTAVFS_REG36
#define RTAVFS_REG36__RTAVFSCPO18_STARTCNT__SHIFT                                                             0x0
#define RTAVFS_REG36__RTAVFSCPO18_STOPCNT__SHIFT                                                              0x10
#define RTAVFS_REG36__RTAVFSCPO18_STARTCNT_MASK                                                               0x0000FFFFL
#define RTAVFS_REG36__RTAVFSCPO18_STOPCNT_MASK                                                                0xFFFF0000L
//RTAVFS_REG37
#define RTAVFS_REG37__RTAVFSCPO18_RIPPLECNT__SHIFT                                                            0x0
#define RTAVFS_REG37__RESERVED__SHIFT                                                                         0x10
#define RTAVFS_REG37__RTAVFSCPO18_RIPPLECNT_MASK                                                              0x0000FFFFL
#define RTAVFS_REG37__RESERVED_MASK                                                                           0xFFFF0000L
//RTAVFS_REG38
#define RTAVFS_REG38__RTAVFSCPO19_STARTCNT__SHIFT                                                             0x0
#define RTAVFS_REG38__RTAVFSCPO19_STOPCNT__SHIFT                                                              0x10
#define RTAVFS_REG38__RTAVFSCPO19_STARTCNT_MASK                                                               0x0000FFFFL
#define RTAVFS_REG38__RTAVFSCPO19_STOPCNT_MASK                                                                0xFFFF0000L
//RTAVFS_REG39
#define RTAVFS_REG39__RTAVFSCPO19_RIPPLECNT__SHIFT                                                            0x0
#define RTAVFS_REG39__RESERVED__SHIFT                                                                         0x10
#define RTAVFS_REG39__RTAVFSCPO19_RIPPLECNT_MASK                                                              0x0000FFFFL
#define RTAVFS_REG39__RESERVED_MASK                                                                           0xFFFF0000L
//RTAVFS_REG40
#define RTAVFS_REG40__RTAVFSCPO20_STARTCNT__SHIFT                                                             0x0
#define RTAVFS_REG40__RTAVFSCPO20_STOPCNT__SHIFT                                                              0x10
#define RTAVFS_REG40__RTAVFSCPO20_STARTCNT_MASK                                                               0x0000FFFFL
#define RTAVFS_REG40__RTAVFSCPO20_STOPCNT_MASK                                                                0xFFFF0000L
//RTAVFS_REG41
#define RTAVFS_REG41__RTAVFSCPO20_RIPPLECNT__SHIFT                                                            0x0
#define RTAVFS_REG41__RESERVED__SHIFT                                                                         0x10
#define RTAVFS_REG41__RTAVFSCPO20_RIPPLECNT_MASK                                                              0x0000FFFFL
#define RTAVFS_REG41__RESERVED_MASK                                                                           0xFFFF0000L
//RTAVFS_REG42
#define RTAVFS_REG42__RTAVFSCPO21_STARTCNT__SHIFT                                                             0x0
#define RTAVFS_REG42__RTAVFSCPO21_STOPCNT__SHIFT                                                              0x10
#define RTAVFS_REG42__RTAVFSCPO21_STARTCNT_MASK                                                               0x0000FFFFL
#define RTAVFS_REG42__RTAVFSCPO21_STOPCNT_MASK                                                                0xFFFF0000L
//RTAVFS_REG43
#define RTAVFS_REG43__RTAVFSCPO21_RIPPLECNT__SHIFT                                                            0x0
#define RTAVFS_REG43__RESERVED__SHIFT                                                                         0x10
#define RTAVFS_REG43__RTAVFSCPO21_RIPPLECNT_MASK                                                              0x0000FFFFL
#define RTAVFS_REG43__RESERVED_MASK                                                                           0xFFFF0000L
//RTAVFS_REG44
#define RTAVFS_REG44__RTAVFSCPO22_STARTCNT__SHIFT                                                             0x0
#define RTAVFS_REG44__RTAVFSCPO22_STOPCNT__SHIFT                                                              0x10
#define RTAVFS_REG44__RTAVFSCPO22_STARTCNT_MASK                                                               0x0000FFFFL
#define RTAVFS_REG44__RTAVFSCPO22_STOPCNT_MASK                                                                0xFFFF0000L
//RTAVFS_REG45
#define RTAVFS_REG45__RTAVFSCPO22_RIPPLECNT__SHIFT                                                            0x0
#define RTAVFS_REG45__RESERVED__SHIFT                                                                         0x10
#define RTAVFS_REG45__RTAVFSCPO22_RIPPLECNT_MASK                                                              0x0000FFFFL
#define RTAVFS_REG45__RESERVED_MASK                                                                           0xFFFF0000L
//RTAVFS_REG46
#define RTAVFS_REG46__RTAVFSCPO23_STARTCNT__SHIFT                                                             0x0
#define RTAVFS_REG46__RTAVFSCPO23_STOPCNT__SHIFT                                                              0x10
#define RTAVFS_REG46__RTAVFSCPO23_STARTCNT_MASK                                                               0x0000FFFFL
#define RTAVFS_REG46__RTAVFSCPO23_STOPCNT_MASK                                                                0xFFFF0000L
//RTAVFS_REG47
#define RTAVFS_REG47__RTAVFSCPO23_RIPPLECNT__SHIFT                                                            0x0
#define RTAVFS_REG47__RESERVED__SHIFT                                                                         0x10
#define RTAVFS_REG47__RTAVFSCPO23_RIPPLECNT_MASK                                                              0x0000FFFFL
#define RTAVFS_REG47__RESERVED_MASK                                                                           0xFFFF0000L
//RTAVFS_REG48
#define RTAVFS_REG48__RTAVFSCPO24_STARTCNT__SHIFT                                                             0x0
#define RTAVFS_REG48__RTAVFSCPO24_STOPCNT__SHIFT                                                              0x10
#define RTAVFS_REG48__RTAVFSCPO24_STARTCNT_MASK                                                               0x0000FFFFL
#define RTAVFS_REG48__RTAVFSCPO24_STOPCNT_MASK                                                                0xFFFF0000L
//RTAVFS_REG49
#define RTAVFS_REG49__RTAVFSCPO24_RIPPLECNT__SHIFT                                                            0x0
#define RTAVFS_REG49__RESERVED__SHIFT                                                                         0x10
#define RTAVFS_REG49__RTAVFSCPO24_RIPPLECNT_MASK                                                              0x0000FFFFL
#define RTAVFS_REG49__RESERVED_MASK                                                                           0xFFFF0000L
//RTAVFS_REG50
#define RTAVFS_REG50__RTAVFSCPO25_STARTCNT__SHIFT                                                             0x0
#define RTAVFS_REG50__RTAVFSCPO25_STOPCNT__SHIFT                                                              0x10
#define RTAVFS_REG50__RTAVFSCPO25_STARTCNT_MASK                                                               0x0000FFFFL
#define RTAVFS_REG50__RTAVFSCPO25_STOPCNT_MASK                                                                0xFFFF0000L
//RTAVFS_REG51
#define RTAVFS_REG51__RTAVFSCPO25_RIPPLECNT__SHIFT                                                            0x0
#define RTAVFS_REG51__RESERVED__SHIFT                                                                         0x10
#define RTAVFS_REG51__RTAVFSCPO25_RIPPLECNT_MASK                                                              0x0000FFFFL
#define RTAVFS_REG51__RESERVED_MASK                                                                           0xFFFF0000L
//RTAVFS_REG52
#define RTAVFS_REG52__RTAVFSCPO26_STARTCNT__SHIFT                                                             0x0
#define RTAVFS_REG52__RTAVFSCPO26_STOPCNT__SHIFT                                                              0x10
#define RTAVFS_REG52__RTAVFSCPO26_STARTCNT_MASK                                                               0x0000FFFFL
#define RTAVFS_REG52__RTAVFSCPO26_STOPCNT_MASK                                                                0xFFFF0000L
//RTAVFS_REG53
#define RTAVFS_REG53__RTAVFSCPO26_RIPPLECNT__SHIFT                                                            0x0
#define RTAVFS_REG53__RESERVED__SHIFT                                                                         0x10
#define RTAVFS_REG53__RTAVFSCPO26_RIPPLECNT_MASK                                                              0x0000FFFFL
#define RTAVFS_REG53__RESERVED_MASK                                                                           0xFFFF0000L
//RTAVFS_REG54
#define RTAVFS_REG54__RTAVFSCPO27_STARTCNT__SHIFT                                                             0x0
#define RTAVFS_REG54__RTAVFSCPO27_STOPCNT__SHIFT                                                              0x10
#define RTAVFS_REG54__RTAVFSCPO27_STARTCNT_MASK                                                               0x0000FFFFL
#define RTAVFS_REG54__RTAVFSCPO27_STOPCNT_MASK                                                                0xFFFF0000L
//RTAVFS_REG55
#define RTAVFS_REG55__RTAVFSCPO27_RIPPLECNT__SHIFT                                                            0x0
#define RTAVFS_REG55__RESERVED__SHIFT                                                                         0x10
#define RTAVFS_REG55__RTAVFSCPO27_RIPPLECNT_MASK                                                              0x0000FFFFL
#define RTAVFS_REG55__RESERVED_MASK                                                                           0xFFFF0000L
//RTAVFS_REG56
#define RTAVFS_REG56__RTAVFSCPO28_STARTCNT__SHIFT                                                             0x0
#define RTAVFS_REG56__RTAVFSCPO28_STOPCNT__SHIFT                                                              0x10
#define RTAVFS_REG56__RTAVFSCPO28_STARTCNT_MASK                                                               0x0000FFFFL
#define RTAVFS_REG56__RTAVFSCPO28_STOPCNT_MASK                                                                0xFFFF0000L
//RTAVFS_REG57
#define RTAVFS_REG57__RTAVFSCPO28_RIPPLECNT__SHIFT                                                            0x0
#define RTAVFS_REG57__RESERVED__SHIFT                                                                         0x10
#define RTAVFS_REG57__RTAVFSCPO28_RIPPLECNT_MASK                                                              0x0000FFFFL
#define RTAVFS_REG57__RESERVED_MASK                                                                           0xFFFF0000L
//RTAVFS_REG58
#define RTAVFS_REG58__RTAVFSCPO29_STARTCNT__SHIFT                                                             0x0
#define RTAVFS_REG58__RTAVFSCPO29_STOPCNT__SHIFT                                                              0x10
#define RTAVFS_REG58__RTAVFSCPO29_STARTCNT_MASK                                                               0x0000FFFFL
#define RTAVFS_REG58__RTAVFSCPO29_STOPCNT_MASK                                                                0xFFFF0000L
//RTAVFS_REG59
#define RTAVFS_REG59__RTAVFSCPO29_RIPPLECNT__SHIFT                                                            0x0
#define RTAVFS_REG59__RESERVED__SHIFT                                                                         0x10
#define RTAVFS_REG59__RTAVFSCPO29_RIPPLECNT_MASK                                                              0x0000FFFFL
#define RTAVFS_REG59__RESERVED_MASK                                                                           0xFFFF0000L
//RTAVFS_REG60
#define RTAVFS_REG60__RTAVFSCPO30_STARTCNT__SHIFT                                                             0x0
#define RTAVFS_REG60__RTAVFSCPO30_STOPCNT__SHIFT                                                              0x10
#define RTAVFS_REG60__RTAVFSCPO30_STARTCNT_MASK                                                               0x0000FFFFL
#define RTAVFS_REG60__RTAVFSCPO30_STOPCNT_MASK                                                                0xFFFF0000L
//RTAVFS_REG61
#define RTAVFS_REG61__RTAVFSCPO30_RIPPLECNT__SHIFT                                                            0x0
#define RTAVFS_REG61__RESERVED__SHIFT                                                                         0x10
#define RTAVFS_REG61__RTAVFSCPO30_RIPPLECNT_MASK                                                              0x0000FFFFL
#define RTAVFS_REG61__RESERVED_MASK                                                                           0xFFFF0000L
//RTAVFS_REG62
#define RTAVFS_REG62__RTAVFSCPO31_STARTCNT__SHIFT                                                             0x0
#define RTAVFS_REG62__RTAVFSCPO31_STOPCNT__SHIFT                                                              0x10
#define RTAVFS_REG62__RTAVFSCPO31_STARTCNT_MASK                                                               0x0000FFFFL
#define RTAVFS_REG62__RTAVFSCPO31_STOPCNT_MASK                                                                0xFFFF0000L
//RTAVFS_REG63
#define RTAVFS_REG63__RTAVFSCPO31_RIPPLECNT__SHIFT                                                            0x0
#define RTAVFS_REG63__RESERVED__SHIFT                                                                         0x10
#define RTAVFS_REG63__RTAVFSCPO31_RIPPLECNT_MASK                                                              0x0000FFFFL
#define RTAVFS_REG63__RESERVED_MASK                                                                           0xFFFF0000L
//RTAVFS_REG64
#define RTAVFS_REG64__RTAVFSCPO32_STARTCNT__SHIFT                                                             0x0
#define RTAVFS_REG64__RTAVFSCPO32_STOPCNT__SHIFT                                                              0x10
#define RTAVFS_REG64__RTAVFSCPO32_STARTCNT_MASK                                                               0x0000FFFFL
#define RTAVFS_REG64__RTAVFSCPO32_STOPCNT_MASK                                                                0xFFFF0000L
//RTAVFS_REG65
#define RTAVFS_REG65__RTAVFSCPO32_RIPPLECNT__SHIFT                                                            0x0
#define RTAVFS_REG65__RESERVED__SHIFT                                                                         0x10
#define RTAVFS_REG65__RTAVFSCPO32_RIPPLECNT_MASK                                                              0x0000FFFFL
#define RTAVFS_REG65__RESERVED_MASK                                                                           0xFFFF0000L
//RTAVFS_REG66
#define RTAVFS_REG66__RTAVFSCPO33_STARTCNT__SHIFT                                                             0x0
#define RTAVFS_REG66__RTAVFSCPO33_STOPCNT__SHIFT                                                              0x10
#define RTAVFS_REG66__RTAVFSCPO33_STARTCNT_MASK                                                               0x0000FFFFL
#define RTAVFS_REG66__RTAVFSCPO33_STOPCNT_MASK                                                                0xFFFF0000L
//RTAVFS_REG67
#define RTAVFS_REG67__RTAVFSCPO33_RIPPLECNT__SHIFT                                                            0x0
#define RTAVFS_REG67__RESERVED__SHIFT                                                                         0x10
#define RTAVFS_REG67__RTAVFSCPO33_RIPPLECNT_MASK                                                              0x0000FFFFL
#define RTAVFS_REG67__RESERVED_MASK                                                                           0xFFFF0000L
//RTAVFS_REG68
#define RTAVFS_REG68__RTAVFSCPO34_STARTCNT__SHIFT                                                             0x0
#define RTAVFS_REG68__RTAVFSCPO34_STOPCNT__SHIFT                                                              0x10
#define RTAVFS_REG68__RTAVFSCPO34_STARTCNT_MASK                                                               0x0000FFFFL
#define RTAVFS_REG68__RTAVFSCPO34_STOPCNT_MASK                                                                0xFFFF0000L
//RTAVFS_REG69
#define RTAVFS_REG69__RTAVFSCPO34_RIPPLECNT__SHIFT                                                            0x0
#define RTAVFS_REG69__RESERVED__SHIFT                                                                         0x10
#define RTAVFS_REG69__RTAVFSCPO34_RIPPLECNT_MASK                                                              0x0000FFFFL
#define RTAVFS_REG69__RESERVED_MASK                                                                           0xFFFF0000L
//RTAVFS_REG70
#define RTAVFS_REG70__RTAVFSCPO35_STARTCNT__SHIFT                                                             0x0
#define RTAVFS_REG70__RTAVFSCPO35_STOPCNT__SHIFT                                                              0x10
#define RTAVFS_REG70__RTAVFSCPO35_STARTCNT_MASK                                                               0x0000FFFFL
#define RTAVFS_REG70__RTAVFSCPO35_STOPCNT_MASK                                                                0xFFFF0000L
//RTAVFS_REG71
#define RTAVFS_REG71__RTAVFSCPO35_RIPPLECNT__SHIFT                                                            0x0
#define RTAVFS_REG71__RESERVED__SHIFT                                                                         0x10
#define RTAVFS_REG71__RTAVFSCPO35_RIPPLECNT_MASK                                                              0x0000FFFFL
#define RTAVFS_REG71__RESERVED_MASK                                                                           0xFFFF0000L
//RTAVFS_REG72
#define RTAVFS_REG72__RTAVFSCPO36_STARTCNT__SHIFT                                                             0x0
#define RTAVFS_REG72__RTAVFSCPO36_STOPCNT__SHIFT                                                              0x10
#define RTAVFS_REG72__RTAVFSCPO36_STARTCNT_MASK                                                               0x0000FFFFL
#define RTAVFS_REG72__RTAVFSCPO36_STOPCNT_MASK                                                                0xFFFF0000L
//RTAVFS_REG73
#define RTAVFS_REG73__RTAVFSCPO36_RIPPLECNT__SHIFT                                                            0x0
#define RTAVFS_REG73__RESERVED__SHIFT                                                                         0x10
#define RTAVFS_REG73__RTAVFSCPO36_RIPPLECNT_MASK                                                              0x0000FFFFL
#define RTAVFS_REG73__RESERVED_MASK                                                                           0xFFFF0000L
//RTAVFS_REG74
#define RTAVFS_REG74__RTAVFSCPO37_STARTCNT__SHIFT                                                             0x0
#define RTAVFS_REG74__RTAVFSCPO37_STOPCNT__SHIFT                                                              0x10
#define RTAVFS_REG74__RTAVFSCPO37_STARTCNT_MASK                                                               0x0000FFFFL
#define RTAVFS_REG74__RTAVFSCPO37_STOPCNT_MASK                                                                0xFFFF0000L
//RTAVFS_REG75
#define RTAVFS_REG75__RTAVFSCPO37_RIPPLECNT__SHIFT                                                            0x0
#define RTAVFS_REG75__RESERVED__SHIFT                                                                         0x10
#define RTAVFS_REG75__RTAVFSCPO37_RIPPLECNT_MASK                                                              0x0000FFFFL
#define RTAVFS_REG75__RESERVED_MASK                                                                           0xFFFF0000L
//RTAVFS_REG76
#define RTAVFS_REG76__RTAVFSCPO38_STARTCNT__SHIFT                                                             0x0
#define RTAVFS_REG76__RTAVFSCPO38_STOPCNT__SHIFT                                                              0x10
#define RTAVFS_REG76__RTAVFSCPO38_STARTCNT_MASK                                                               0x0000FFFFL
#define RTAVFS_REG76__RTAVFSCPO38_STOPCNT_MASK                                                                0xFFFF0000L
//RTAVFS_REG77
#define RTAVFS_REG77__RTAVFSCPO38_RIPPLECNT__SHIFT                                                            0x0
#define RTAVFS_REG77__RESERVED__SHIFT                                                                         0x10
#define RTAVFS_REG77__RTAVFSCPO38_RIPPLECNT_MASK                                                              0x0000FFFFL
#define RTAVFS_REG77__RESERVED_MASK                                                                           0xFFFF0000L
//RTAVFS_REG78
#define RTAVFS_REG78__RTAVFSCPO39_STARTCNT__SHIFT                                                             0x0
#define RTAVFS_REG78__RTAVFSCPO39_STOPCNT__SHIFT                                                              0x10
#define RTAVFS_REG78__RTAVFSCPO39_STARTCNT_MASK                                                               0x0000FFFFL
#define RTAVFS_REG78__RTAVFSCPO39_STOPCNT_MASK                                                                0xFFFF0000L
//RTAVFS_REG79
#define RTAVFS_REG79__RTAVFSCPO39_RIPPLECNT__SHIFT                                                            0x0
#define RTAVFS_REG79__RESERVED__SHIFT                                                                         0x10
#define RTAVFS_REG79__RTAVFSCPO39_RIPPLECNT_MASK                                                              0x0000FFFFL
#define RTAVFS_REG79__RESERVED_MASK                                                                           0xFFFF0000L
//RTAVFS_REG80
#define RTAVFS_REG80__RTAVFSCPO40_STARTCNT__SHIFT                                                             0x0
#define RTAVFS_REG80__RTAVFSCPO40_STOPCNT__SHIFT                                                              0x10
#define RTAVFS_REG80__RTAVFSCPO40_STARTCNT_MASK                                                               0x0000FFFFL
#define RTAVFS_REG80__RTAVFSCPO40_STOPCNT_MASK                                                                0xFFFF0000L
//RTAVFS_REG81
#define RTAVFS_REG81__RTAVFSCPO40_RIPPLECNT__SHIFT                                                            0x0
#define RTAVFS_REG81__RESERVED__SHIFT                                                                         0x10
#define RTAVFS_REG81__RTAVFSCPO40_RIPPLECNT_MASK                                                              0x0000FFFFL
#define RTAVFS_REG81__RESERVED_MASK                                                                           0xFFFF0000L
//RTAVFS_REG82
#define RTAVFS_REG82__RTAVFSCPO41_STARTCNT__SHIFT                                                             0x0
#define RTAVFS_REG82__RTAVFSCPO41_STOPCNT__SHIFT                                                              0x10
#define RTAVFS_REG82__RTAVFSCPO41_STARTCNT_MASK                                                               0x0000FFFFL
#define RTAVFS_REG82__RTAVFSCPO41_STOPCNT_MASK                                                                0xFFFF0000L
//RTAVFS_REG83
#define RTAVFS_REG83__RTAVFSCPO41_RIPPLECNT__SHIFT                                                            0x0
#define RTAVFS_REG83__RESERVED__SHIFT                                                                         0x10
#define RTAVFS_REG83__RTAVFSCPO41_RIPPLECNT_MASK                                                              0x0000FFFFL
#define RTAVFS_REG83__RESERVED_MASK                                                                           0xFFFF0000L
//RTAVFS_REG84
#define RTAVFS_REG84__RTAVFSCPO42_STARTCNT__SHIFT                                                             0x0
#define RTAVFS_REG84__RTAVFSCPO42_STOPCNT__SHIFT                                                              0x10
#define RTAVFS_REG84__RTAVFSCPO42_STARTCNT_MASK                                                               0x0000FFFFL
#define RTAVFS_REG84__RTAVFSCPO42_STOPCNT_MASK                                                                0xFFFF0000L
//RTAVFS_REG85
#define RTAVFS_REG85__RTAVFSCPO42_RIPPLECNT__SHIFT                                                            0x0
#define RTAVFS_REG85__RESERVED__SHIFT                                                                         0x10
#define RTAVFS_REG85__RTAVFSCPO42_RIPPLECNT_MASK                                                              0x0000FFFFL
#define RTAVFS_REG85__RESERVED_MASK                                                                           0xFFFF0000L
//RTAVFS_REG86
#define RTAVFS_REG86__RTAVFSCPO43_STARTCNT__SHIFT                                                             0x0
#define RTAVFS_REG86__RTAVFSCPO43_STOPCNT__SHIFT                                                              0x10
#define RTAVFS_REG86__RTAVFSCPO43_STARTCNT_MASK                                                               0x0000FFFFL
#define RTAVFS_REG86__RTAVFSCPO43_STOPCNT_MASK                                                                0xFFFF0000L
//RTAVFS_REG87
#define RTAVFS_REG87__RTAVFSCPO43_RIPPLECNT__SHIFT                                                            0x0
#define RTAVFS_REG87__RESERVED__SHIFT                                                                         0x10
#define RTAVFS_REG87__RTAVFSCPO43_RIPPLECNT_MASK                                                              0x0000FFFFL
#define RTAVFS_REG87__RESERVED_MASK                                                                           0xFFFF0000L
//RTAVFS_REG88
#define RTAVFS_REG88__RTAVFSCPO44_STARTCNT__SHIFT                                                             0x0
#define RTAVFS_REG88__RTAVFSCPO44_STOPCNT__SHIFT                                                              0x10
#define RTAVFS_REG88__RTAVFSCPO44_STARTCNT_MASK                                                               0x0000FFFFL
#define RTAVFS_REG88__RTAVFSCPO44_STOPCNT_MASK                                                                0xFFFF0000L
//RTAVFS_REG89
#define RTAVFS_REG89__RTAVFSCPO44_RIPPLECNT__SHIFT                                                            0x0
#define RTAVFS_REG89__RESERVED__SHIFT                                                                         0x10
#define RTAVFS_REG89__RTAVFSCPO44_RIPPLECNT_MASK                                                              0x0000FFFFL
#define RTAVFS_REG89__RESERVED_MASK                                                                           0xFFFF0000L
//RTAVFS_REG90
#define RTAVFS_REG90__RTAVFSCPO45_STARTCNT__SHIFT                                                             0x0
#define RTAVFS_REG90__RTAVFSCPO45_STOPCNT__SHIFT                                                              0x10
#define RTAVFS_REG90__RTAVFSCPO45_STARTCNT_MASK                                                               0x0000FFFFL
#define RTAVFS_REG90__RTAVFSCPO45_STOPCNT_MASK                                                                0xFFFF0000L
//RTAVFS_REG91
#define RTAVFS_REG91__RTAVFSCPO45_RIPPLECNT__SHIFT                                                            0x0
#define RTAVFS_REG91__RESERVED__SHIFT                                                                         0x10
#define RTAVFS_REG91__RTAVFSCPO45_RIPPLECNT_MASK                                                              0x0000FFFFL
#define RTAVFS_REG91__RESERVED_MASK                                                                           0xFFFF0000L
//RTAVFS_REG92
#define RTAVFS_REG92__RTAVFSCPO46_STARTCNT__SHIFT                                                             0x0
#define RTAVFS_REG92__RTAVFSCPO46_STOPCNT__SHIFT                                                              0x10
#define RTAVFS_REG92__RTAVFSCPO46_STARTCNT_MASK                                                               0x0000FFFFL
#define RTAVFS_REG92__RTAVFSCPO46_STOPCNT_MASK                                                                0xFFFF0000L
//RTAVFS_REG93
#define RTAVFS_REG93__RTAVFSCPO46_RIPPLECNT__SHIFT                                                            0x0
#define RTAVFS_REG93__RESERVED__SHIFT                                                                         0x10
#define RTAVFS_REG93__RTAVFSCPO46_RIPPLECNT_MASK                                                              0x0000FFFFL
#define RTAVFS_REG93__RESERVED_MASK                                                                           0xFFFF0000L
//RTAVFS_REG94
#define RTAVFS_REG94__RTAVFSCPO47_STARTCNT__SHIFT                                                             0x0
#define RTAVFS_REG94__RTAVFSCPO47_STOPCNT__SHIFT                                                              0x10
#define RTAVFS_REG94__RTAVFSCPO47_STARTCNT_MASK                                                               0x0000FFFFL
#define RTAVFS_REG94__RTAVFSCPO47_STOPCNT_MASK                                                                0xFFFF0000L
//RTAVFS_REG95
#define RTAVFS_REG95__RTAVFSCPO47_RIPPLECNT__SHIFT                                                            0x0
#define RTAVFS_REG95__RESERVED__SHIFT                                                                         0x10
#define RTAVFS_REG95__RTAVFSCPO47_RIPPLECNT_MASK                                                              0x0000FFFFL
#define RTAVFS_REG95__RESERVED_MASK                                                                           0xFFFF0000L
//RTAVFS_REG96
#define RTAVFS_REG96__RTAVFSCPO48_STARTCNT__SHIFT                                                             0x0
#define RTAVFS_REG96__RTAVFSCPO48_STOPCNT__SHIFT                                                              0x10
#define RTAVFS_REG96__RTAVFSCPO48_STARTCNT_MASK                                                               0x0000FFFFL
#define RTAVFS_REG96__RTAVFSCPO48_STOPCNT_MASK                                                                0xFFFF0000L
//RTAVFS_REG97
#define RTAVFS_REG97__RTAVFSCPO48_RIPPLECNT__SHIFT                                                            0x0
#define RTAVFS_REG97__RESERVED__SHIFT                                                                         0x10
#define RTAVFS_REG97__RTAVFSCPO48_RIPPLECNT_MASK                                                              0x0000FFFFL
#define RTAVFS_REG97__RESERVED_MASK                                                                           0xFFFF0000L
//RTAVFS_REG98
#define RTAVFS_REG98__RTAVFSCPO49_STARTCNT__SHIFT                                                             0x0
#define RTAVFS_REG98__RTAVFSCPO49_STOPCNT__SHIFT                                                              0x10
#define RTAVFS_REG98__RTAVFSCPO49_STARTCNT_MASK                                                               0x0000FFFFL
#define RTAVFS_REG98__RTAVFSCPO49_STOPCNT_MASK                                                                0xFFFF0000L
//RTAVFS_REG99
#define RTAVFS_REG99__RTAVFSCPO49_RIPPLECNT__SHIFT                                                            0x0
#define RTAVFS_REG99__RESERVED__SHIFT                                                                         0x10
#define RTAVFS_REG99__RTAVFSCPO49_RIPPLECNT_MASK                                                              0x0000FFFFL
#define RTAVFS_REG99__RESERVED_MASK                                                                           0xFFFF0000L
//RTAVFS_REG100
#define RTAVFS_REG100__RTAVFSCPO50_STARTCNT__SHIFT                                                            0x0
#define RTAVFS_REG100__RTAVFSCPO50_STOPCNT__SHIFT                                                             0x10
#define RTAVFS_REG100__RTAVFSCPO50_STARTCNT_MASK                                                              0x0000FFFFL
#define RTAVFS_REG100__RTAVFSCPO50_STOPCNT_MASK                                                               0xFFFF0000L
//RTAVFS_REG101
#define RTAVFS_REG101__RTAVFSCPO50_RIPPLECNT__SHIFT                                                           0x0
#define RTAVFS_REG101__RESERVED__SHIFT                                                                        0x10
#define RTAVFS_REG101__RTAVFSCPO50_RIPPLECNT_MASK                                                             0x0000FFFFL
#define RTAVFS_REG101__RESERVED_MASK                                                                          0xFFFF0000L
//RTAVFS_REG102
#define RTAVFS_REG102__RTAVFSCPO51_STARTCNT__SHIFT                                                            0x0
#define RTAVFS_REG102__RTAVFSCPO51_STOPCNT__SHIFT                                                             0x10
#define RTAVFS_REG102__RTAVFSCPO51_STARTCNT_MASK                                                              0x0000FFFFL
#define RTAVFS_REG102__RTAVFSCPO51_STOPCNT_MASK                                                               0xFFFF0000L
//RTAVFS_REG103
#define RTAVFS_REG103__RTAVFSCPO51_RIPPLECNT__SHIFT                                                           0x0
#define RTAVFS_REG103__RESERVED__SHIFT                                                                        0x10
#define RTAVFS_REG103__RTAVFSCPO51_RIPPLECNT_MASK                                                             0x0000FFFFL
#define RTAVFS_REG103__RESERVED_MASK                                                                          0xFFFF0000L
//RTAVFS_REG104
#define RTAVFS_REG104__RTAVFSCPO52_STARTCNT__SHIFT                                                            0x0
#define RTAVFS_REG104__RTAVFSCPO52_STOPCNT__SHIFT                                                             0x10
#define RTAVFS_REG104__RTAVFSCPO52_STARTCNT_MASK                                                              0x0000FFFFL
#define RTAVFS_REG104__RTAVFSCPO52_STOPCNT_MASK                                                               0xFFFF0000L
//RTAVFS_REG105
#define RTAVFS_REG105__RTAVFSCPO52_RIPPLECNT__SHIFT                                                           0x0
#define RTAVFS_REG105__RESERVED__SHIFT                                                                        0x10
#define RTAVFS_REG105__RTAVFSCPO52_RIPPLECNT_MASK                                                             0x0000FFFFL
#define RTAVFS_REG105__RESERVED_MASK                                                                          0xFFFF0000L
//RTAVFS_REG106
#define RTAVFS_REG106__RTAVFSCPO53_STARTCNT__SHIFT                                                            0x0
#define RTAVFS_REG106__RTAVFSCPO53_STOPCNT__SHIFT                                                             0x10
#define RTAVFS_REG106__RTAVFSCPO53_STARTCNT_MASK                                                              0x0000FFFFL
#define RTAVFS_REG106__RTAVFSCPO53_STOPCNT_MASK                                                               0xFFFF0000L
//RTAVFS_REG107
#define RTAVFS_REG107__RTAVFSCPO53_RIPPLECNT__SHIFT                                                           0x0
#define RTAVFS_REG107__RESERVED__SHIFT                                                                        0x10
#define RTAVFS_REG107__RTAVFSCPO53_RIPPLECNT_MASK                                                             0x0000FFFFL
#define RTAVFS_REG107__RESERVED_MASK                                                                          0xFFFF0000L
//RTAVFS_REG108
#define RTAVFS_REG108__RTAVFSCPO54_STARTCNT__SHIFT                                                            0x0
#define RTAVFS_REG108__RTAVFSCPO54_STOPCNT__SHIFT                                                             0x10
#define RTAVFS_REG108__RTAVFSCPO54_STARTCNT_MASK                                                              0x0000FFFFL
#define RTAVFS_REG108__RTAVFSCPO54_STOPCNT_MASK                                                               0xFFFF0000L
//RTAVFS_REG109
#define RTAVFS_REG109__RTAVFSCPO54_RIPPLECNT__SHIFT                                                           0x0
#define RTAVFS_REG109__RESERVED__SHIFT                                                                        0x10
#define RTAVFS_REG109__RTAVFSCPO54_RIPPLECNT_MASK                                                             0x0000FFFFL
#define RTAVFS_REG109__RESERVED_MASK                                                                          0xFFFF0000L
//RTAVFS_REG110
#define RTAVFS_REG110__RTAVFSCPO55_STARTCNT__SHIFT                                                            0x0
#define RTAVFS_REG110__RTAVFSCPO55_STOPCNT__SHIFT                                                             0x10
#define RTAVFS_REG110__RTAVFSCPO55_STARTCNT_MASK                                                              0x0000FFFFL
#define RTAVFS_REG110__RTAVFSCPO55_STOPCNT_MASK                                                               0xFFFF0000L
//RTAVFS_REG111
#define RTAVFS_REG111__RTAVFSCPO55_RIPPLECNT__SHIFT                                                           0x0
#define RTAVFS_REG111__RESERVED__SHIFT                                                                        0x10
#define RTAVFS_REG111__RTAVFSCPO55_RIPPLECNT_MASK                                                             0x0000FFFFL
#define RTAVFS_REG111__RESERVED_MASK                                                                          0xFFFF0000L
//RTAVFS_REG112
#define RTAVFS_REG112__RTAVFSCPO56_STARTCNT__SHIFT                                                            0x0
#define RTAVFS_REG112__RTAVFSCPO56_STOPCNT__SHIFT                                                             0x10
#define RTAVFS_REG112__RTAVFSCPO56_STARTCNT_MASK                                                              0x0000FFFFL
#define RTAVFS_REG112__RTAVFSCPO56_STOPCNT_MASK                                                               0xFFFF0000L
//RTAVFS_REG113
#define RTAVFS_REG113__RTAVFSCPO56_RIPPLECNT__SHIFT                                                           0x0
#define RTAVFS_REG113__RESERVED__SHIFT                                                                        0x10
#define RTAVFS_REG113__RTAVFSCPO56_RIPPLECNT_MASK                                                             0x0000FFFFL
#define RTAVFS_REG113__RESERVED_MASK                                                                          0xFFFF0000L
//RTAVFS_REG114
#define RTAVFS_REG114__RTAVFSCPO57_STARTCNT__SHIFT                                                            0x0
#define RTAVFS_REG114__RTAVFSCPO57_STOPCNT__SHIFT                                                             0x10
#define RTAVFS_REG114__RTAVFSCPO57_STARTCNT_MASK                                                              0x0000FFFFL
#define RTAVFS_REG114__RTAVFSCPO57_STOPCNT_MASK                                                               0xFFFF0000L
//RTAVFS_REG115
#define RTAVFS_REG115__RTAVFSCPO57_RIPPLECNT__SHIFT                                                           0x0
#define RTAVFS_REG115__RESERVED__SHIFT                                                                        0x10
#define RTAVFS_REG115__RTAVFSCPO57_RIPPLECNT_MASK                                                             0x0000FFFFL
#define RTAVFS_REG115__RESERVED_MASK                                                                          0xFFFF0000L
//RTAVFS_REG116
#define RTAVFS_REG116__RTAVFSCPO58_STARTCNT__SHIFT                                                            0x0
#define RTAVFS_REG116__RTAVFSCPO58_STOPCNT__SHIFT                                                             0x10
#define RTAVFS_REG116__RTAVFSCPO58_STARTCNT_MASK                                                              0x0000FFFFL
#define RTAVFS_REG116__RTAVFSCPO58_STOPCNT_MASK                                                               0xFFFF0000L
//RTAVFS_REG117
#define RTAVFS_REG117__RTAVFSCPO58_RIPPLECNT__SHIFT                                                           0x0
#define RTAVFS_REG117__RESERVED__SHIFT                                                                        0x10
#define RTAVFS_REG117__RTAVFSCPO58_RIPPLECNT_MASK                                                             0x0000FFFFL
#define RTAVFS_REG117__RESERVED_MASK                                                                          0xFFFF0000L
//RTAVFS_REG118
#define RTAVFS_REG118__RTAVFSCPO59_STARTCNT__SHIFT                                                            0x0
#define RTAVFS_REG118__RTAVFSCPO59_STOPCNT__SHIFT                                                             0x10
#define RTAVFS_REG118__RTAVFSCPO59_STARTCNT_MASK                                                              0x0000FFFFL
#define RTAVFS_REG118__RTAVFSCPO59_STOPCNT_MASK                                                               0xFFFF0000L
//RTAVFS_REG119
#define RTAVFS_REG119__RTAVFSCPO59_RIPPLECNT__SHIFT                                                           0x0
#define RTAVFS_REG119__RESERVED__SHIFT                                                                        0x10
#define RTAVFS_REG119__RTAVFSCPO59_RIPPLECNT_MASK                                                             0x0000FFFFL
#define RTAVFS_REG119__RESERVED_MASK                                                                          0xFFFF0000L
//RTAVFS_REG120
#define RTAVFS_REG120__RTAVFSCPO60_STARTCNT__SHIFT                                                            0x0
#define RTAVFS_REG120__RTAVFSCPO60_STOPCNT__SHIFT                                                             0x10
#define RTAVFS_REG120__RTAVFSCPO60_STARTCNT_MASK                                                              0x0000FFFFL
#define RTAVFS_REG120__RTAVFSCPO60_STOPCNT_MASK                                                               0xFFFF0000L
//RTAVFS_REG121
#define RTAVFS_REG121__RTAVFSCPO60_RIPPLECNT__SHIFT                                                           0x0
#define RTAVFS_REG121__RESERVED__SHIFT                                                                        0x10
#define RTAVFS_REG121__RTAVFSCPO60_RIPPLECNT_MASK                                                             0x0000FFFFL
#define RTAVFS_REG121__RESERVED_MASK                                                                          0xFFFF0000L
//RTAVFS_REG122
#define RTAVFS_REG122__RTAVFSCPO61_STARTCNT__SHIFT                                                            0x0
#define RTAVFS_REG122__RTAVFSCPO61_STOPCNT__SHIFT                                                             0x10
#define RTAVFS_REG122__RTAVFSCPO61_STARTCNT_MASK                                                              0x0000FFFFL
#define RTAVFS_REG122__RTAVFSCPO61_STOPCNT_MASK                                                               0xFFFF0000L
//RTAVFS_REG123
#define RTAVFS_REG123__RTAVFSCPO61_RIPPLECNT__SHIFT                                                           0x0
#define RTAVFS_REG123__RESERVED__SHIFT                                                                        0x10
#define RTAVFS_REG123__RTAVFSCPO61_RIPPLECNT_MASK                                                             0x0000FFFFL
#define RTAVFS_REG123__RESERVED_MASK                                                                          0xFFFF0000L
//RTAVFS_REG124
#define RTAVFS_REG124__RTAVFSCPO62_STARTCNT__SHIFT                                                            0x0
#define RTAVFS_REG124__RTAVFSCPO62_STOPCNT__SHIFT                                                             0x10
#define RTAVFS_REG124__RTAVFSCPO62_STARTCNT_MASK                                                              0x0000FFFFL
#define RTAVFS_REG124__RTAVFSCPO62_STOPCNT_MASK                                                               0xFFFF0000L
//RTAVFS_REG125
#define RTAVFS_REG125__RTAVFSCPO62_RIPPLECNT__SHIFT                                                           0x0
#define RTAVFS_REG125__RESERVED__SHIFT                                                                        0x10
#define RTAVFS_REG125__RTAVFSCPO62_RIPPLECNT_MASK                                                             0x0000FFFFL
#define RTAVFS_REG125__RESERVED_MASK                                                                          0xFFFF0000L
//RTAVFS_REG126
#define RTAVFS_REG126__RTAVFSCPO63_STARTCNT__SHIFT                                                            0x0
#define RTAVFS_REG126__RTAVFSCPO63_STOPCNT__SHIFT                                                             0x10
#define RTAVFS_REG126__RTAVFSCPO63_STARTCNT_MASK                                                              0x0000FFFFL
#define RTAVFS_REG126__RTAVFSCPO63_STOPCNT_MASK                                                               0xFFFF0000L
//RTAVFS_REG127
#define RTAVFS_REG127__RTAVFSCPO63_RIPPLECNT__SHIFT                                                           0x0
#define RTAVFS_REG127__RESERVED__SHIFT                                                                        0x10
#define RTAVFS_REG127__RTAVFSCPO63_RIPPLECNT_MASK                                                             0x0000FFFFL
#define RTAVFS_REG127__RESERVED_MASK                                                                          0xFFFF0000L
//RTAVFS_REG128
#define RTAVFS_REG128__RTAVFSCPOEN0__SHIFT                                                                    0x0
#define RTAVFS_REG128__RTAVFSCPOEN0_MASK                                                                      0xFFFFFFFFL
//RTAVFS_REG129
#define RTAVFS_REG129__RTAVFSCPOEN1__SHIFT                                                                    0x0
#define RTAVFS_REG129__RTAVFSCPOEN1_MASK                                                                      0xFFFFFFFFL
//RTAVFS_REG130
#define RTAVFS_REG130__RTAVFSVRBLEEDCNTRL__SHIFT                                                              0x0
#define RTAVFS_REG130__RTAVFSVRENABLE__SHIFT                                                                  0x1
#define RTAVFS_REG130__RTAVFSVOLTCODEOVERRIDE__SHIFT                                                          0x2
#define RTAVFS_REG130__RTAVFSVOLTCODEOVERRIDESEL__SHIFT                                                       0xc
#define RTAVFS_REG130__RTAVFSLOWPWREN__SHIFT                                                                  0xd
#define RTAVFS_REG130__RESERVED__SHIFT                                                                        0xe
#define RTAVFS_REG130__RTAVFSVRBLEEDCNTRL_MASK                                                                0x00000001L
#define RTAVFS_REG130__RTAVFSVRENABLE_MASK                                                                    0x00000002L
#define RTAVFS_REG130__RTAVFSVOLTCODEOVERRIDE_MASK                                                            0x00000FFCL
#define RTAVFS_REG130__RTAVFSVOLTCODEOVERRIDESEL_MASK                                                         0x00001000L
#define RTAVFS_REG130__RTAVFSLOWPWREN_MASK                                                                    0x00002000L
#define RTAVFS_REG130__RESERVED_MASK                                                                          0xFFFFC000L
//RTAVFS_REG131
#define RTAVFS_REG131__RTAVFSTARGETFREQCNTOVERRIDE__SHIFT                                                     0x0
#define RTAVFS_REG131__RTAVFSTARGETFREQCNTOVERRIDESEL__SHIFT                                                  0x10
#define RTAVFS_REG131__RESERVED__SHIFT                                                                        0x11
#define RTAVFS_REG131__RTAVFSTARGETFREQCNTOVERRIDE_MASK                                                       0x0000FFFFL
#define RTAVFS_REG131__RTAVFSTARGETFREQCNTOVERRIDESEL_MASK                                                    0x00010000L
#define RTAVFS_REG131__RESERVED_MASK                                                                          0xFFFE0000L
//RTAVFS_REG132
#define RTAVFS_REG132__RTAVFSCURRENTFREQCNTOVERRIDE__SHIFT                                                    0x0
#define RTAVFS_REG132__RTAVFSCURRENTFREQCNTOVERRIDESEL__SHIFT                                                 0x10
#define RTAVFS_REG132__RESERVED__SHIFT                                                                        0x11
#define RTAVFS_REG132__RTAVFSCURRENTFREQCNTOVERRIDE_MASK                                                      0x0000FFFFL
#define RTAVFS_REG132__RTAVFSCURRENTFREQCNTOVERRIDESEL_MASK                                                   0x00010000L
#define RTAVFS_REG132__RESERVED_MASK                                                                          0xFFFE0000L
//RTAVFS_REG133
#define RTAVFS_REG133__RESERVED__SHIFT                                                                        0x16
#define RTAVFS_REG133__RESERVED_MASK                                                                          0xFFC00000L
//RTAVFS_REG134
#define RTAVFS_REG134__RTAVFSKP__SHIFT                                                                        0x0
#define RTAVFS_REG134__RTAVFSKI__SHIFT                                                                        0x4
#define RTAVFS_REG134__RTAVFSPIENABLEANTIWINDUP__SHIFT                                                        0x8
#define RTAVFS_REG134__RTAVFSPISHIFT__SHIFT                                                                   0x9
#define RTAVFS_REG134__RTAVFSPIERREN__SHIFT                                                                   0xd
#define RTAVFS_REG134__RTAVFSPISHIFTOUT__SHIFT                                                                0xe
#define RTAVFS_REG134__RTAVFSUSELUTKPKI__SHIFT                                                                0x12
#define RTAVFS_REG134__RESERVED__SHIFT                                                                        0x13
#define RTAVFS_REG134__RTAVFSKP_MASK                                                                          0x0000000FL
#define RTAVFS_REG134__RTAVFSKI_MASK                                                                          0x000000F0L
#define RTAVFS_REG134__RTAVFSPIENABLEANTIWINDUP_MASK                                                          0x00000100L
#define RTAVFS_REG134__RTAVFSPISHIFT_MASK                                                                     0x00001E00L
#define RTAVFS_REG134__RTAVFSPIERREN_MASK                                                                     0x00002000L
#define RTAVFS_REG134__RTAVFSPISHIFTOUT_MASK                                                                  0x0003C000L
#define RTAVFS_REG134__RTAVFSUSELUTKPKI_MASK                                                                  0x00040000L
#define RTAVFS_REG134__RESERVED_MASK                                                                          0xFFF80000L
//RTAVFS_REG135
#define RTAVFS_REG135__RTAVFSVOLTCODEPIMIN__SHIFT                                                             0x0
#define RTAVFS_REG135__RTAVFSVOLTCODEPIMAX__SHIFT                                                             0xa
#define RTAVFS_REG135__RTAVFSPIERRMASK__SHIFT                                                                 0x14
#define RTAVFS_REG135__RTAVFSFORCEDISABLEPI__SHIFT                                                            0x1b
#define RTAVFS_REG135__RESERVED__SHIFT                                                                        0x1c
#define RTAVFS_REG135__RTAVFSVOLTCODEPIMIN_MASK                                                               0x000003FFL
#define RTAVFS_REG135__RTAVFSVOLTCODEPIMAX_MASK                                                               0x000FFC00L
#define RTAVFS_REG135__RTAVFSPIERRMASK_MASK                                                                   0x07F00000L
#define RTAVFS_REG135__RTAVFSFORCEDISABLEPI_MASK                                                              0x08000000L
#define RTAVFS_REG135__RESERVED_MASK                                                                          0xF0000000L
//RTAVFS_REG136
#define RTAVFS_REG136__RTAVFSPILOOPNITERATIONS__SHIFT                                                         0x0
#define RTAVFS_REG136__RTAVFSPIERRTHRESHOLD__SHIFT                                                            0x10
#define RTAVFS_REG136__RTAVFSPILOOPNITERATIONS_MASK                                                           0x0000FFFFL
#define RTAVFS_REG136__RTAVFSPIERRTHRESHOLD_MASK                                                              0xFFFF0000L
//RTAVFS_REG137
#define RTAVFS_REG137__RTAVFSVOLTCODEFROMPI__SHIFT                                                            0x0
#define RTAVFS_REG137__RTAVFSVOLTCODEFROMBINARYSEARCH__SHIFT                                                  0xa
#define RTAVFS_REG137__RTAVFSVDDREGON__SHIFT                                                                  0x14
#define RTAVFS_REG137__RESERVED__SHIFT                                                                        0x15
#define RTAVFS_REG137__RTAVFSVOLTCODEFROMPI_MASK                                                              0x000003FFL
#define RTAVFS_REG137__RTAVFSVOLTCODEFROMBINARYSEARCH_MASK                                                    0x000FFC00L
#define RTAVFS_REG137__RTAVFSVDDREGON_MASK                                                                    0x00100000L
#define RTAVFS_REG137__RESERVED_MASK                                                                          0xFFE00000L
//RTAVFS_REG138
#define RTAVFS_REG138__RTAVFSAVFSENABLE__SHIFT                                                                0x0
#define RTAVFS_REG138__RTAVFSCPOTURNONDELAY__SHIFT                                                            0x1
#define RTAVFS_REG138__RTAVFSSELECTMINMAX__SHIFT                                                              0x5
#define RTAVFS_REG138__RTAVFSIGNORERLCREQ__SHIFT                                                              0x6
#define RTAVFS_REG138__RTAVFSRIPPLECOUNTEROUTSEL__SHIFT                                                       0x7
#define RTAVFS_REG138__RTAVFSRUNLOOP__SHIFT                                                                   0xc
#define RTAVFS_REG138__RESERVED__SHIFT                                                                        0xd
#define RTAVFS_REG138__RTAVFSAVFSENABLE_MASK                                                                  0x00000001L
#define RTAVFS_REG138__RTAVFSCPOTURNONDELAY_MASK                                                              0x0000001EL
#define RTAVFS_REG138__RTAVFSSELECTMINMAX_MASK                                                                0x00000020L
#define RTAVFS_REG138__RTAVFSIGNORERLCREQ_MASK                                                                0x00000040L
#define RTAVFS_REG138__RTAVFSRIPPLECOUNTEROUTSEL_MASK                                                         0x00000F80L
#define RTAVFS_REG138__RTAVFSRUNLOOP_MASK                                                                     0x00001000L
#define RTAVFS_REG138__RESERVED_MASK                                                                          0xFFFFE000L
//RTAVFS_REG139
#define RTAVFS_REG139__RTAVFSAVFSSCALEDCPOCOUNT__SHIFT                                                        0x0
#define RTAVFS_REG139__RTAVFSAVFSFINALMINCPOCOUNT__SHIFT                                                      0x10
#define RTAVFS_REG139__RTAVFSAVFSSCALEDCPOCOUNT_MASK                                                          0x0000FFFFL
#define RTAVFS_REG139__RTAVFSAVFSFINALMINCPOCOUNT_MASK                                                        0xFFFF0000L
//RTAVFS_REG140
#define RTAVFS_REG140__RTAVFSPSMRSTAVGVDD__SHIFT                                                              0x0
#define RTAVFS_REG140__RTAVFSPSMMEASMAXVDD__SHIFT                                                             0x1
#define RTAVFS_REG140__RTAVFSPSMCLKDIVVDD__SHIFT                                                              0x2
#define RTAVFS_REG140__RTAVFSPSMAVGDIVVDD__SHIFT                                                              0x4
#define RTAVFS_REG140__RTAVFSPSMOSCENVDD__SHIFT                                                               0xa
#define RTAVFS_REG140__RTAVFSPSMAVGENVDD__SHIFT                                                               0xb
#define RTAVFS_REG140__RTAVFSPSMRSTMINMAXVDD__SHIFT                                                           0xc
#define RTAVFS_REG140__RESERVED__SHIFT                                                                        0xd
#define RTAVFS_REG140__RTAVFSPSMRSTAVGVDD_MASK                                                                0x00000001L
#define RTAVFS_REG140__RTAVFSPSMMEASMAXVDD_MASK                                                               0x00000002L
#define RTAVFS_REG140__RTAVFSPSMCLKDIVVDD_MASK                                                                0x0000000CL
#define RTAVFS_REG140__RTAVFSPSMAVGDIVVDD_MASK                                                                0x000003F0L
#define RTAVFS_REG140__RTAVFSPSMOSCENVDD_MASK                                                                 0x00000400L
#define RTAVFS_REG140__RTAVFSPSMAVGENVDD_MASK                                                                 0x00000800L
#define RTAVFS_REG140__RTAVFSPSMRSTMINMAXVDD_MASK                                                             0x00001000L
#define RTAVFS_REG140__RESERVED_MASK                                                                          0xFFFFE000L
//RTAVFS_REG141
#define RTAVFS_REG141__RTAVFSMINMAXPSMVDD__SHIFT                                                              0x0
#define RTAVFS_REG141__RTAVFSAVGPSMVDD__SHIFT                                                                 0xe
#define RTAVFS_REG141__RESERVED__SHIFT                                                                        0x1c
#define RTAVFS_REG141__RTAVFSMINMAXPSMVDD_MASK                                                                0x00003FFFL
#define RTAVFS_REG141__RTAVFSAVGPSMVDD_MASK                                                                   0x0FFFC000L
#define RTAVFS_REG141__RESERVED_MASK                                                                          0xF0000000L
//RTAVFS_REG142
#define RTAVFS_REG142__RTAVFSPSMRSTAVGVREG__SHIFT                                                             0x0
#define RTAVFS_REG142__RTAVFSPSMMEASMAXVREG__SHIFT                                                            0x1
#define RTAVFS_REG142__RTAVFSPSMCLKDIVVREG__SHIFT                                                             0x2
#define RTAVFS_REG142__RTAVFSPSMAVGDIVVREG__SHIFT                                                             0x4
#define RTAVFS_REG142__RTAVFSPSMOSCENVREG__SHIFT                                                              0xa
#define RTAVFS_REG142__RTAVFSPSMAVGENVREG__SHIFT                                                              0xb
#define RTAVFS_REG142__RTAVFSPSMRSTMINMAXVREG__SHIFT                                                          0xc
#define RTAVFS_REG142__RESERVED__SHIFT                                                                        0xd
#define RTAVFS_REG142__RTAVFSPSMRSTAVGVREG_MASK                                                               0x00000001L
#define RTAVFS_REG142__RTAVFSPSMMEASMAXVREG_MASK                                                              0x00000002L
#define RTAVFS_REG142__RTAVFSPSMCLKDIVVREG_MASK                                                               0x0000000CL
#define RTAVFS_REG142__RTAVFSPSMAVGDIVVREG_MASK                                                               0x000003F0L
#define RTAVFS_REG142__RTAVFSPSMOSCENVREG_MASK                                                                0x00000400L
#define RTAVFS_REG142__RTAVFSPSMAVGENVREG_MASK                                                                0x00000800L
#define RTAVFS_REG142__RTAVFSPSMRSTMINMAXVREG_MASK                                                            0x00001000L
#define RTAVFS_REG142__RESERVED_MASK                                                                          0xFFFFE000L
//RTAVFS_REG143
#define RTAVFS_REG143__RTAVFSMINMAXPSMVREG__SHIFT                                                             0x0
#define RTAVFS_REG143__RTAVFSAVGPSMVREG__SHIFT                                                                0xe
#define RTAVFS_REG143__RESERVED__SHIFT                                                                        0x1c
#define RTAVFS_REG143__RTAVFSMINMAXPSMVREG_MASK                                                               0x00003FFFL
#define RTAVFS_REG143__RTAVFSAVGPSMVREG_MASK                                                                  0x0FFFC000L
#define RTAVFS_REG143__RESERVED_MASK                                                                          0xF0000000L
//RTAVFS_REG144
#define RTAVFS_REG144__RTAVFSTROSAMPLESIZE__SHIFT                                                             0x0
#define RTAVFS_REG144__RTAVFSTROSAMPLEDLY__SHIFT                                                              0xc
#define RTAVFS_REG144__RTAVFSTROCONTMODEEN__SHIFT                                                             0xe
#define RTAVFS_REG144__RTAVFSTROPWRSAVEEN__SHIFT                                                              0xf
#define RTAVFS_REG144__RTAVFSTROTMPAVEEN__SHIFT                                                               0x10
#define RTAVFS_REG144__RTAVFSTROTMPAVEDIV__SHIFT                                                              0x11
#define RTAVFS_REG144__RTAVFSTROCALIBDIS__SHIFT                                                               0x17
#define RTAVFS_REG144__RTAVFSTROOUTVALSEL__SHIFT                                                              0x18
#define RTAVFS_REG144__RTAVFSTROCMGAIN__SHIFT                                                                 0x1b
#define RTAVFS_REG144__RTAVFSTROCLKDIVSEL__SHIFT                                                              0x1d
#define RTAVFS_REG144__RTAVFSTROTRODIS__SHIFT                                                                 0x1f
#define RTAVFS_REG144__RTAVFSTROSAMPLESIZE_MASK                                                               0x00000FFFL
#define RTAVFS_REG144__RTAVFSTROSAMPLEDLY_MASK                                                                0x00003000L
#define RTAVFS_REG144__RTAVFSTROCONTMODEEN_MASK                                                               0x00004000L
#define RTAVFS_REG144__RTAVFSTROPWRSAVEEN_MASK                                                                0x00008000L
#define RTAVFS_REG144__RTAVFSTROTMPAVEEN_MASK                                                                 0x00010000L
#define RTAVFS_REG144__RTAVFSTROTMPAVEDIV_MASK                                                                0x007E0000L
#define RTAVFS_REG144__RTAVFSTROCALIBDIS_MASK                                                                 0x00800000L
#define RTAVFS_REG144__RTAVFSTROOUTVALSEL_MASK                                                                0x07000000L
#define RTAVFS_REG144__RTAVFSTROCMGAIN_MASK                                                                   0x18000000L
#define RTAVFS_REG144__RTAVFSTROCLKDIVSEL_MASK                                                                0x60000000L
#define RTAVFS_REG144__RTAVFSTROTRODIS_MASK                                                                   0x80000000L
//RTAVFS_REG145
#define RTAVFS_REG145__RTAVFSTROTEMPDATA__SHIFT                                                               0x0
#define RTAVFS_REG145__RTAVFSTROSSTATE__SHIFT                                                                 0x10
#define RTAVFS_REG145__RTAVFSTROCALIBDONE__SHIFT                                                              0x14
#define RTAVFS_REG145__RTAVFSTRORESERVED__SHIFT                                                               0x15
#define RTAVFS_REG145__RTAVFSTROTEMPDATA_MASK                                                                 0x0000FFFFL
#define RTAVFS_REG145__RTAVFSTROSSTATE_MASK                                                                   0x000F0000L
#define RTAVFS_REG145__RTAVFSTROCALIBDONE_MASK                                                                0x00100000L
#define RTAVFS_REG145__RTAVFSTRORESERVED_MASK                                                                 0xFFE00000L
//RTAVFS_REG146
#define RTAVFS_REG146__RTAVFSTROTMP_M__SHIFT                                                                  0x0
#define RTAVFS_REG146__RTAVFSTROTMP_C__SHIFT                                                                  0x10
#define RTAVFS_REG146__RTAVFSTROTMP_M_MASK                                                                    0x0000FFFFL
#define RTAVFS_REG146__RTAVFSTROTMP_C_MASK                                                                    0xFFFF0000L
//RTAVFS_REG147
#define RTAVFS_REG147__RTAVFSTROTMP_OFFSET__SHIFT                                                             0x0
#define RTAVFS_REG147__RTAVFSTROTMPSAMPSIZE__SHIFT                                                            0x5
#define RTAVFS_REG147__RTAVFSTROTMPREADSKIPSCALE__SHIFT                                                       0x11
#define RTAVFS_REG147__RTAVFSTROTMPSKIPSCALEFIX__SHIFT                                                        0x12
#define RTAVFS_REG147__RESERVED__SHIFT                                                                        0x13
#define RTAVFS_REG147__RTAVFSTROTMP_OFFSET_MASK                                                               0x0000001FL
#define RTAVFS_REG147__RTAVFSTROTMPSAMPSIZE_MASK                                                              0x0001FFE0L
#define RTAVFS_REG147__RTAVFSTROTMPREADSKIPSCALE_MASK                                                         0x00020000L
#define RTAVFS_REG147__RTAVFSTROTMPSKIPSCALEFIX_MASK                                                          0x00040000L
#define RTAVFS_REG147__RESERVED_MASK                                                                          0xFFF80000L
//RTAVFS_REG148
#define RTAVFS_REG148__RTAVFSTROTMPOUT__SHIFT                                                                 0x0
#define RTAVFS_REG148__RTAVFSTROTMPOUTVAL__SHIFT                                                              0xc
#define RTAVFS_REG148__RTAVFSTROCURTMP__SHIFT                                                                 0xd
#define RTAVFS_REG148__RESERVED__SHIFT                                                                        0x18
#define RTAVFS_REG148__RTAVFSTROTMPOUT_MASK                                                                   0x00000FFFL
#define RTAVFS_REG148__RTAVFSTROTMPOUTVAL_MASK                                                                0x00001000L
#define RTAVFS_REG148__RTAVFSTROCURTMP_MASK                                                                   0x00FFE000L
#define RTAVFS_REG148__RESERVED_MASK                                                                          0xFF000000L
//RTAVFS_REG149
#define RTAVFS_REG149__RTAVFSFSMSTARTUPCNT__SHIFT                                                             0x0
#define RTAVFS_REG149__RESERVED__SHIFT                                                                        0x10
#define RTAVFS_REG149__RTAVFSFSMSTARTUPCNT_MASK                                                               0x0000FFFFL
#define RTAVFS_REG149__RESERVED_MASK                                                                          0xFFFF0000L
//RTAVFS_REG150
#define RTAVFS_REG150__RTAVFSFSMIDLECNT__SHIFT                                                                0x0
#define RTAVFS_REG150__RESERVED__SHIFT                                                                        0x10
#define RTAVFS_REG150__RTAVFSFSMIDLECNT_MASK                                                                  0x0000FFFFL
#define RTAVFS_REG150__RESERVED_MASK                                                                          0xFFFF0000L
//RTAVFS_REG151
#define RTAVFS_REG151__RTAVFSFSMRESETCPORIPPLECOUNTERSCNT__SHIFT                                              0x0
#define RTAVFS_REG151__RESERVED__SHIFT                                                                        0x10
#define RTAVFS_REG151__RTAVFSFSMRESETCPORIPPLECOUNTERSCNT_MASK                                                0x0000FFFFL
#define RTAVFS_REG151__RESERVED_MASK                                                                          0xFFFF0000L
//RTAVFS_REG152
#define RTAVFS_REG152__RTAVFSFSMSTARTCPOSCNT__SHIFT                                                           0x0
#define RTAVFS_REG152__RESERVED__SHIFT                                                                        0x10
#define RTAVFS_REG152__RTAVFSFSMSTARTCPOSCNT_MASK                                                             0x0000FFFFL
#define RTAVFS_REG152__RESERVED_MASK                                                                          0xFFFF0000L
//RTAVFS_REG153
#define RTAVFS_REG153__RTAVFSFSMSTARTRIPPLECOUNTERSCNT__SHIFT                                                 0x0
#define RTAVFS_REG153__RESERVED__SHIFT                                                                        0x10
#define RTAVFS_REG153__RTAVFSFSMSTARTRIPPLECOUNTERSCNT_MASK                                                   0x0000FFFFL
#define RTAVFS_REG153__RESERVED_MASK                                                                          0xFFFF0000L
//RTAVFS_REG154
#define RTAVFS_REG154__RTAVFSFSMRIPPLECOUNTERSDONECNT__SHIFT                                                  0x0
#define RTAVFS_REG154__RESERVED__SHIFT                                                                        0x10
#define RTAVFS_REG154__RTAVFSFSMRIPPLECOUNTERSDONECNT_MASK                                                    0x0000FFFFL
#define RTAVFS_REG154__RESERVED_MASK                                                                          0xFFFF0000L
//RTAVFS_REG155
#define RTAVFS_REG155__RTAVFSFSMCPOFINALRESULTREADYCNT__SHIFT                                                 0x0
#define RTAVFS_REG155__RESERVED__SHIFT                                                                        0x10
#define RTAVFS_REG155__RTAVFSFSMCPOFINALRESULTREADYCNT_MASK                                                   0x0000FFFFL
#define RTAVFS_REG155__RESERVED_MASK                                                                          0xFFFF0000L
//RTAVFS_REG156
#define RTAVFS_REG156__RTAVFSFSMVOLTCODEREADYCNT__SHIFT                                                       0x0
#define RTAVFS_REG156__RESERVED__SHIFT                                                                        0x10
#define RTAVFS_REG156__RTAVFSFSMVOLTCODEREADYCNT_MASK                                                         0x0000FFFFL
#define RTAVFS_REG156__RESERVED_MASK                                                                          0xFFFF0000L
//RTAVFS_REG157
#define RTAVFS_REG157__RTAVFSFSMTARGETVOLTAGEREADYCNT__SHIFT                                                  0x0
#define RTAVFS_REG157__RESERVED__SHIFT                                                                        0x10
#define RTAVFS_REG157__RTAVFSFSMTARGETVOLTAGEREADYCNT_MASK                                                    0x0000FFFFL
#define RTAVFS_REG157__RESERVED_MASK                                                                          0xFFFF0000L
//RTAVFS_REG158
#define RTAVFS_REG158__RTAVFSFSMSTOPCPOSCNT__SHIFT                                                            0x0
#define RTAVFS_REG158__RESERVED__SHIFT                                                                        0x10
#define RTAVFS_REG158__RTAVFSFSMSTOPCPOSCNT_MASK                                                              0x0000FFFFL
#define RTAVFS_REG158__RESERVED_MASK                                                                          0xFFFF0000L
//RTAVFS_REG159
#define RTAVFS_REG159__RTAVFSFSMWAITFORACKCNT__SHIFT                                                          0x0
#define RTAVFS_REG159__RESERVED__SHIFT                                                                        0x10
#define RTAVFS_REG159__RTAVFSFSMWAITFORACKCNT_MASK                                                            0x0000FFFFL
#define RTAVFS_REG159__RESERVED_MASK                                                                          0xFFFF0000L
//RTAVFS_REG160
#define RTAVFS_REG160__RTAVFSCPOAVGDIV0__SHIFT                                                                0x0
#define RTAVFS_REG160__RTAVFSCPOAVGDIV1__SHIFT                                                                0x2
#define RTAVFS_REG160__RTAVFSCPOAVGDIV2__SHIFT                                                                0x4
#define RTAVFS_REG160__RTAVFSCPOAVGDIV3__SHIFT                                                                0x6
#define RTAVFS_REG160__RTAVFSCPOAVGDIV4__SHIFT                                                                0x8
#define RTAVFS_REG160__RTAVFSCPOAVGDIV5__SHIFT                                                                0xa
#define RTAVFS_REG160__RTAVFSCPOAVGDIV6__SHIFT                                                                0xc
#define RTAVFS_REG160__RTAVFSCPOAVGDIV7__SHIFT                                                                0xe
#define RTAVFS_REG160__RTAVFSCPOAVGDIVFINAL__SHIFT                                                            0x10
#define RTAVFS_REG160__RESERVED__SHIFT                                                                        0x12
#define RTAVFS_REG160__RTAVFSCPOAVGDIV0_MASK                                                                  0x00000003L
#define RTAVFS_REG160__RTAVFSCPOAVGDIV1_MASK                                                                  0x0000000CL
#define RTAVFS_REG160__RTAVFSCPOAVGDIV2_MASK                                                                  0x00000030L
#define RTAVFS_REG160__RTAVFSCPOAVGDIV3_MASK                                                                  0x000000C0L
#define RTAVFS_REG160__RTAVFSCPOAVGDIV4_MASK                                                                  0x00000300L
#define RTAVFS_REG160__RTAVFSCPOAVGDIV5_MASK                                                                  0x00000C00L
#define RTAVFS_REG160__RTAVFSCPOAVGDIV6_MASK                                                                  0x00003000L
#define RTAVFS_REG160__RTAVFSCPOAVGDIV7_MASK                                                                  0x0000C000L
#define RTAVFS_REG160__RTAVFSCPOAVGDIVFINAL_MASK                                                              0x00030000L
#define RTAVFS_REG160__RESERVED_MASK                                                                          0xFFFC0000L
//RTAVFS_REG161
#define RTAVFS_REG161__RTAVFSKP0__SHIFT                                                                       0x0
#define RTAVFS_REG161__RTAVFSKP1__SHIFT                                                                       0x4
#define RTAVFS_REG161__RTAVFSKP2__SHIFT                                                                       0x8
#define RTAVFS_REG161__RTAVFSKP3__SHIFT                                                                       0xc
#define RTAVFS_REG161__RTAVFSKI0__SHIFT                                                                       0x10
#define RTAVFS_REG161__RTAVFSKI1__SHIFT                                                                       0x14
#define RTAVFS_REG161__RTAVFSKI2__SHIFT                                                                       0x18
#define RTAVFS_REG161__RTAVFSKI3__SHIFT                                                                       0x1c
#define RTAVFS_REG161__RTAVFSKP0_MASK                                                                         0x0000000FL
#define RTAVFS_REG161__RTAVFSKP1_MASK                                                                         0x000000F0L
#define RTAVFS_REG161__RTAVFSKP2_MASK                                                                         0x00000F00L
#define RTAVFS_REG161__RTAVFSKP3_MASK                                                                         0x0000F000L
#define RTAVFS_REG161__RTAVFSKI0_MASK                                                                         0x000F0000L
#define RTAVFS_REG161__RTAVFSKI1_MASK                                                                         0x00F00000L
#define RTAVFS_REG161__RTAVFSKI2_MASK                                                                         0x0F000000L
#define RTAVFS_REG161__RTAVFSKI3_MASK                                                                         0xF0000000L
//RTAVFS_REG162
#define RTAVFS_REG162__RTAVFSV1__SHIFT                                                                        0x0
#define RTAVFS_REG162__RTAVFSV2__SHIFT                                                                        0xa
#define RTAVFS_REG162__RTAVFSV3__SHIFT                                                                        0x14
#define RTAVFS_REG162__RTAVFSUSEBINARYSEARCH__SHIFT                                                           0x1e
#define RTAVFS_REG162__RTAVFSVOLTCODEHWCAL__SHIFT                                                             0x1f
#define RTAVFS_REG162__RTAVFSV1_MASK                                                                          0x000003FFL
#define RTAVFS_REG162__RTAVFSV2_MASK                                                                          0x000FFC00L
#define RTAVFS_REG162__RTAVFSV3_MASK                                                                          0x3FF00000L
#define RTAVFS_REG162__RTAVFSUSEBINARYSEARCH_MASK                                                             0x40000000L
#define RTAVFS_REG162__RTAVFSVOLTCODEHWCAL_MASK                                                               0x80000000L
//RTAVFS_REG163
#define RTAVFS_REG163__RTAVFSFSMSTATE__SHIFT                                                                  0x0
#define RTAVFS_REG163__RESERVED__SHIFT                                                                        0x10
#define RTAVFS_REG163__RTAVFSFSMSTATE_MASK                                                                    0x0000FFFFL
#define RTAVFS_REG163__RESERVED_MASK                                                                          0xFFFF0000L
//RTAVFS_REG164
#define RTAVFS_REG164__RTAVFSGB_V1__SHIFT                                                                     0x0
#define RTAVFS_REG164__RTAVFSGB_V1V2__SHIFT                                                                   0x8
#define RTAVFS_REG164__RTAVFSGB_V2V3__SHIFT                                                                   0x10
#define RTAVFS_REG164__RTAVFSGB_V3__SHIFT                                                                     0x18
#define RTAVFS_REG164__RTAVFSGB_V1_MASK                                                                       0x000000FFL
#define RTAVFS_REG164__RTAVFSGB_V1V2_MASK                                                                     0x0000FF00L
#define RTAVFS_REG164__RTAVFSGB_V2V3_MASK                                                                     0x00FF0000L
#define RTAVFS_REG164__RTAVFSGB_V3_MASK                                                                       0xFF000000L
//RTAVFS_REG165
#define RTAVFS_REG165__RTAVFSRIPPLECNTREAD__SHIFT                                                             0x0
#define RTAVFS_REG165__RTAVFSRIPPLECNTREAD_MASK                                                               0xFFFFFFFFL


// addressBlock: spiind
//SA_WGP_BLK_ID
#define SA_WGP_BLK_ID__BLK_ID__SHIFT                                                                          0x0
#define SA_WGP_BLK_ID__WGP_SIDE__SHIFT                                                                        0x4
#define SA_WGP_BLK_ID__SA_ID__SHIFT                                                                           0x5
#define SA_WGP_BLK_ID__BLK_ID_MASK                                                                            0x0000000FL
#define SA_WGP_BLK_ID__WGP_SIDE_MASK                                                                          0x00000010L
#define SA_WGP_BLK_ID__SA_ID_MASK                                                                             0x00000020L


// addressBlock: sqind
//SQ_DEBUG_STS_GLOBAL
#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0_MASK 0x000000ffL
#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0__SHIFT 0x00000000
#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1_MASK 0x0000ff00L
#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1__SHIFT 0x00000008
#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_COMPUTE_MASK 0xff0000L
#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_COMPUTE__SHIFT 0x00000010
#define SQ_DEBUG_STS_GLOBAL__BUSY_MASK 0x00000001L
#define SQ_DEBUG_STS_GLOBAL__BUSY__SHIFT 0x00000000
#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY_MASK 0x00000002L
#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY__SHIFT 0x00000001
#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA0_MASK 0x0000fff0L
#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA0__SHIFT 0x00000004
#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA1_MASK 0x0fff0000L
#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA1__SHIFT 0x00000010

//SQ_DEBUG_STS_LOCAL
#define SQ_DEBUG_STS_LOCAL__BUSY_MASK                                                                         0x00000001L
#define SQ_DEBUG_STS_LOCAL__BUSY__SHIFT                                                                       0x00000000
#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL_MASK                                                                   0x000003f0L
#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL__SHIFT                                                                 0x00000004
#define SQ_DEBUG_STS_LOCAL__SQ_BUSY_MASK                                                                      0x00001000L
#define SQ_DEBUG_STS_LOCAL__SQ_BUSY__SHIFT                                                                    0x0000000C
#define SQ_DEBUG_STS_LOCAL__IS_BUSY_MASK                                                                      0x00002000L
#define SQ_DEBUG_STS_LOCAL__IS_BUSY__SHIFT                                                                    0x0000000D
#define SQ_DEBUG_STS_LOCAL__IB_BUSY_MASK                                                                      0x00004000L
#define SQ_DEBUG_STS_LOCAL__IB_BUSY__SHIFT                                                                    0x0000000E
#define SQ_DEBUG_STS_LOCAL__ARB_BUSY_MASK                                                                     0x00008000L
#define SQ_DEBUG_STS_LOCAL__ARB_BUSY__SHIFT                                                                   0x0000000F
#define SQ_DEBUG_STS_LOCAL__EXP_BUSY_MASK                                                                     0x00010000L
#define SQ_DEBUG_STS_LOCAL__EXP_BUSY__SHIFT                                                                   0x00000010
#define SQ_DEBUG_STS_LOCAL__BRMSG_BUSY_MASK                                                                   0x00020000L
#define SQ_DEBUG_STS_LOCAL__BRMSG_BUSY__SHIFT                                                                 0x00000011
#define SQ_DEBUG_STS_LOCAL__VM_BUSY_MASK                                                                      0x00040000L
#define SQ_DEBUG_STS_LOCAL__VM_BUSY__SHIFT                                                                    0x00000018
//SQ_WAVE_ACTIVE
#define SQ_WAVE_ACTIVE__WAVE_SLOT__SHIFT                                                                      0x0
#define SQ_WAVE_ACTIVE__WAVE_SLOT_MASK                                                                        0x000FFFFFL
//SQ_WAVE_VALID_AND_IDLE
#define SQ_WAVE_VALID_AND_IDLE__WAVE_SLOT__SHIFT                                                              0x0
#define SQ_WAVE_VALID_AND_IDLE__WAVE_SLOT_MASK                                                                0x000FFFFFL
//SQ_WAVE_MODE
#define SQ_WAVE_MODE__FP_ROUND__SHIFT                                                                         0x0
#define SQ_WAVE_MODE__FP_DENORM__SHIFT                                                                        0x4
#define SQ_WAVE_MODE__DX10_CLAMP__SHIFT                                                                       0x8
#define SQ_WAVE_MODE__IEEE__SHIFT                                                                             0x9
#define SQ_WAVE_MODE__LOD_CLAMPED__SHIFT                                                                      0xa
#define SQ_WAVE_MODE__EXCP_EN__SHIFT                                                                          0xc
#define SQ_WAVE_MODE__FP16_OVFL__SHIFT                                                                        0x17
#define SQ_WAVE_MODE__DISABLE_PERF__SHIFT                                                                     0x1b
#define SQ_WAVE_MODE__FP_ROUND_MASK                                                                           0x0000000FL
#define SQ_WAVE_MODE__FP_DENORM_MASK                                                                          0x000000F0L
#define SQ_WAVE_MODE__DX10_CLAMP_MASK                                                                         0x00000100L
#define SQ_WAVE_MODE__IEEE_MASK                                                                               0x00000200L
#define SQ_WAVE_MODE__LOD_CLAMPED_MASK                                                                        0x00000400L
#define SQ_WAVE_MODE__EXCP_EN_MASK                                                                            0x001FF000L
#define SQ_WAVE_MODE__FP16_OVFL_MASK                                                                          0x00800000L
#define SQ_WAVE_MODE__DISABLE_PERF_MASK                                                                       0x08000000L
//SQ_WAVE_STATUS
#define SQ_WAVE_STATUS__SCC__SHIFT                                                                            0x0
#define SQ_WAVE_STATUS__SPI_PRIO__SHIFT                                                                       0x1
#define SQ_WAVE_STATUS__USER_PRIO__SHIFT                                                                      0x3
#define SQ_WAVE_STATUS__PRIV__SHIFT                                                                           0x5
#define SQ_WAVE_STATUS__TRAP_EN__SHIFT                                                                        0x6
#define SQ_WAVE_STATUS__TTRACE_EN__SHIFT                                                                      0x7
#define SQ_WAVE_STATUS__EXPORT_RDY__SHIFT                                                                     0x8
#define SQ_WAVE_STATUS__EXECZ__SHIFT                                                                          0x9
#define SQ_WAVE_STATUS__VCCZ__SHIFT                                                                           0xa
#define SQ_WAVE_STATUS__IN_TG__SHIFT                                                                          0xb
#define SQ_WAVE_STATUS__IN_BARRIER__SHIFT                                                                     0xc
#define SQ_WAVE_STATUS__HALT__SHIFT                                                                           0xd
#define SQ_WAVE_STATUS__TRAP__SHIFT                                                                           0xe
#define SQ_WAVE_STATUS__TTRACE_SIMD_EN__SHIFT                                                                 0xf
#define SQ_WAVE_STATUS__VALID__SHIFT                                                                          0x10
#define SQ_WAVE_STATUS__ECC_ERR__SHIFT                                                                        0x11
#define SQ_WAVE_STATUS__SKIP_EXPORT__SHIFT                                                                    0x12
#define SQ_WAVE_STATUS__PERF_EN__SHIFT                                                                        0x13
#define SQ_WAVE_STATUS__FATAL_HALT__SHIFT                                                                     0x17
#define SQ_WAVE_STATUS__MUST_EXPORT__SHIFT                                                                    0x1b
#define SQ_WAVE_STATUS__SCC_MASK                                                                              0x00000001L
#define SQ_WAVE_STATUS__SPI_PRIO_MASK                                                                         0x00000006L
#define SQ_WAVE_STATUS__USER_PRIO_MASK                                                                        0x00000018L
#define SQ_WAVE_STATUS__PRIV_MASK                                                                             0x00000020L
#define SQ_WAVE_STATUS__TRAP_EN_MASK                                                                          0x00000040L
#define SQ_WAVE_STATUS__TTRACE_EN_MASK                                                                        0x00000080L
#define SQ_WAVE_STATUS__EXPORT_RDY_MASK                                                                       0x00000100L
#define SQ_WAVE_STATUS__EXECZ_MASK                                                                            0x00000200L
#define SQ_WAVE_STATUS__VCCZ_MASK                                                                             0x00000400L
#define SQ_WAVE_STATUS__IN_TG_MASK                                                                            0x00000800L
#define SQ_WAVE_STATUS__IN_BARRIER_MASK                                                                       0x00001000L
#define SQ_WAVE_STATUS__HALT_MASK                                                                             0x00002000L
#define SQ_WAVE_STATUS__TRAP_MASK                                                                             0x00004000L
#define SQ_WAVE_STATUS__TTRACE_SIMD_EN_MASK                                                                   0x00008000L
#define SQ_WAVE_STATUS__VALID_MASK                                                                            0x00010000L
#define SQ_WAVE_STATUS__ECC_ERR_MASK                                                                          0x00020000L
#define SQ_WAVE_STATUS__SKIP_EXPORT_MASK                                                                      0x00040000L
#define SQ_WAVE_STATUS__PERF_EN_MASK                                                                          0x00080000L
#define SQ_WAVE_STATUS__FATAL_HALT_MASK                                                                       0x00800000L
#define SQ_WAVE_STATUS__MUST_EXPORT_MASK                                                                      0x08000000L
//SQ_WAVE_TRAPSTS
#define SQ_WAVE_TRAPSTS__EXCP__SHIFT                                                                          0x0
#define SQ_WAVE_TRAPSTS__SAVECTX__SHIFT                                                                       0xa
#define SQ_WAVE_TRAPSTS__ILLEGAL_INST__SHIFT                                                                  0xb
#define SQ_WAVE_TRAPSTS__EXCP_HI__SHIFT                                                                       0xc
#define SQ_WAVE_TRAPSTS__BUFFER_OOB__SHIFT                                                                    0xf
#define SQ_WAVE_TRAPSTS__EXCP_CYCLE__SHIFT                                                                    0x10
#define SQ_WAVE_TRAPSTS__EXCP_GROUP_MASK__SHIFT                                                               0x14
#define SQ_WAVE_TRAPSTS__EXCP_WAVE64HI__SHIFT                                                                 0x18
#define SQ_WAVE_TRAPSTS__UTC_ERROR__SHIFT                                                                     0x1c
#define SQ_WAVE_TRAPSTS__DP_RATE__SHIFT                                                                       0x1d
#define SQ_WAVE_TRAPSTS__EXCP_MASK                                                                            0x000001FFL
#define SQ_WAVE_TRAPSTS__SAVECTX_MASK                                                                         0x00000400L
#define SQ_WAVE_TRAPSTS__ILLEGAL_INST_MASK                                                                    0x00000800L
#define SQ_WAVE_TRAPSTS__EXCP_HI_MASK                                                                         0x00007000L
#define SQ_WAVE_TRAPSTS__BUFFER_OOB_MASK                                                                      0x00008000L
#define SQ_WAVE_TRAPSTS__EXCP_CYCLE_MASK                                                                      0x000F0000L
#define SQ_WAVE_TRAPSTS__EXCP_GROUP_MASK_MASK                                                                 0x00F00000L
#define SQ_WAVE_TRAPSTS__EXCP_WAVE64HI_MASK                                                                   0x01000000L
#define SQ_WAVE_TRAPSTS__UTC_ERROR_MASK                                                                       0x10000000L
#define SQ_WAVE_TRAPSTS__DP_RATE_MASK                                                                         0xE0000000L
//SQ_WAVE_HW_ID_LEGACY
#define SQ_WAVE_HW_ID_LEGACY__WAVE_ID__SHIFT                                                                  0x0
#define SQ_WAVE_HW_ID_LEGACY__SIMD_ID__SHIFT                                                                  0x4
#define SQ_WAVE_HW_ID_LEGACY__PIPE_ID__SHIFT                                                                  0x6
#define SQ_WAVE_HW_ID_LEGACY__CU_ID__SHIFT                                                                    0x8
#define SQ_WAVE_HW_ID_LEGACY__SH_ID__SHIFT                                                                    0xc
#define SQ_WAVE_HW_ID_LEGACY__SE_ID__SHIFT                                                                    0xd
#define SQ_WAVE_HW_ID_LEGACY__WAVE_ID_MSB__SHIFT                                                              0xf
#define SQ_WAVE_HW_ID_LEGACY__TG_ID__SHIFT                                                                    0x10
#define SQ_WAVE_HW_ID_LEGACY__VM_ID__SHIFT                                                                    0x14
#define SQ_WAVE_HW_ID_LEGACY__QUEUE_ID__SHIFT                                                                 0x18
#define SQ_WAVE_HW_ID_LEGACY__STATE_ID__SHIFT                                                                 0x1b
#define SQ_WAVE_HW_ID_LEGACY__ME_ID__SHIFT                                                                    0x1e
#define SQ_WAVE_HW_ID_LEGACY__WAVE_ID_MASK                                                                    0x0000000FL
#define SQ_WAVE_HW_ID_LEGACY__SIMD_ID_MASK                                                                    0x00000030L
#define SQ_WAVE_HW_ID_LEGACY__PIPE_ID_MASK                                                                    0x000000C0L
#define SQ_WAVE_HW_ID_LEGACY__CU_ID_MASK                                                                      0x00000F00L
#define SQ_WAVE_HW_ID_LEGACY__SH_ID_MASK                                                                      0x00001000L
#define SQ_WAVE_HW_ID_LEGACY__SE_ID_MASK                                                                      0x00006000L
#define SQ_WAVE_HW_ID_LEGACY__WAVE_ID_MSB_MASK                                                                0x00008000L
#define SQ_WAVE_HW_ID_LEGACY__TG_ID_MASK                                                                      0x000F0000L
#define SQ_WAVE_HW_ID_LEGACY__VM_ID_MASK                                                                      0x00F00000L
#define SQ_WAVE_HW_ID_LEGACY__QUEUE_ID_MASK                                                                   0x07000000L
#define SQ_WAVE_HW_ID_LEGACY__STATE_ID_MASK                                                                   0x38000000L
#define SQ_WAVE_HW_ID_LEGACY__ME_ID_MASK                                                                      0xC0000000L
//SQ_WAVE_GPR_ALLOC
#define SQ_WAVE_GPR_ALLOC__VGPR_BASE__SHIFT                                                                   0x0
#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE__SHIFT                                                                   0x8
#define SQ_WAVE_GPR_ALLOC__SGPR_BASE__SHIFT                                                                   0x10
#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE__SHIFT                                                                   0x18
#define SQ_WAVE_GPR_ALLOC__VGPR_BASE_MASK                                                                     0x000000FFL
#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE_MASK                                                                     0x0000FF00L
#define SQ_WAVE_GPR_ALLOC__SGPR_BASE_MASK                                                                     0x00FF0000L
#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE_MASK                                                                     0x0F000000L
//SQ_WAVE_LDS_ALLOC
#define SQ_WAVE_LDS_ALLOC__LDS_BASE__SHIFT                                                                    0x0
#define SQ_WAVE_LDS_ALLOC__LDS_SIZE__SHIFT                                                                    0xc
#define SQ_WAVE_LDS_ALLOC__VGPR_SHARED_SIZE__SHIFT                                                            0x18
#define SQ_WAVE_LDS_ALLOC__LDS_BASE_MASK                                                                      0x000001FFL
#define SQ_WAVE_LDS_ALLOC__LDS_SIZE_MASK                                                                      0x001FF000L
#define SQ_WAVE_LDS_ALLOC__VGPR_SHARED_SIZE_MASK                                                              0x0F000000L
//SQ_WAVE_IB_STS
#define SQ_WAVE_IB_STS__VM_CNT__SHIFT                                                                         0x0
#define SQ_WAVE_IB_STS__EXP_CNT__SHIFT                                                                        0x4
#define SQ_WAVE_IB_STS__LGKM_CNT_BIT4__SHIFT                                                                  0x7
#define SQ_WAVE_IB_STS__LGKM_CNT__SHIFT                                                                       0x8
#define SQ_WAVE_IB_STS__VALU_CNT__SHIFT                                                                       0xc
#define SQ_WAVE_IB_STS__VM_CNT_HI__SHIFT                                                                      0x16
#define SQ_WAVE_IB_STS__LGKM_CNT_BIT5__SHIFT                                                                  0x18
#define SQ_WAVE_IB_STS__VS_CNT__SHIFT                                                                         0x1a
#define SQ_WAVE_IB_STS__VM_CNT_MASK                                                                           0x0000000FL
#define SQ_WAVE_IB_STS__EXP_CNT_MASK                                                                          0x00000070L
#define SQ_WAVE_IB_STS__LGKM_CNT_BIT4_MASK                                                                    0x00000080L
#define SQ_WAVE_IB_STS__LGKM_CNT_MASK                                                                         0x00000F00L
#define SQ_WAVE_IB_STS__VALU_CNT_MASK                                                                         0x00007000L
#define SQ_WAVE_IB_STS__VM_CNT_HI_MASK                                                                        0x00C00000L
#define SQ_WAVE_IB_STS__LGKM_CNT_BIT5_MASK                                                                    0x01000000L
#define SQ_WAVE_IB_STS__VS_CNT_MASK                                                                           0xFC000000L
//SQ_WAVE_PC_LO
#define SQ_WAVE_PC_LO__PC_LO__SHIFT                                                                           0x0
#define SQ_WAVE_PC_LO__PC_LO_MASK                                                                             0xFFFFFFFFL
//SQ_WAVE_PC_HI
#define SQ_WAVE_PC_HI__PC_HI__SHIFT                                                                           0x0
#define SQ_WAVE_PC_HI__PC_HI_MASK                                                                             0x0000FFFFL
//SQ_WAVE_INST_DW0
#define SQ_WAVE_INST_DW0__INST_DW0__SHIFT                                                                     0x0
#define SQ_WAVE_INST_DW0__INST_DW0_MASK                                                                       0xFFFFFFFFL
//SQ_WAVE_IB_DBG1
#define SQ_WAVE_IB_DBG1__WAVE_IDLE__SHIFT                                                                     0x18
#define SQ_WAVE_IB_DBG1__MISC_CNT__SHIFT                                                                      0x19
#define SQ_WAVE_IB_DBG1__WAVE_IDLE_MASK                                                                       0x01000000L
#define SQ_WAVE_IB_DBG1__MISC_CNT_MASK                                                                        0xFE000000L
//SQ_WAVE_FLUSH_IB
#define SQ_WAVE_FLUSH_IB__UNUSED__SHIFT                                                                       0x0
#define SQ_WAVE_FLUSH_IB__UNUSED_MASK                                                                         0xFFFFFFFFL
//SQ_WAVE_FLAT_SCRATCH_LO
#define SQ_WAVE_FLAT_SCRATCH_LO__DATA__SHIFT                                                                  0x0
#define SQ_WAVE_FLAT_SCRATCH_LO__DATA_MASK                                                                    0xFFFFFFFFL
//SQ_WAVE_FLAT_SCRATCH_HI
#define SQ_WAVE_FLAT_SCRATCH_HI__DATA__SHIFT                                                                  0x0
#define SQ_WAVE_FLAT_SCRATCH_HI__DATA_MASK                                                                    0xFFFFFFFFL
//SQ_WAVE_HW_ID1
#define SQ_WAVE_HW_ID1__WAVE_ID__SHIFT                                                                        0x0
#define SQ_WAVE_HW_ID1__SIMD_ID__SHIFT                                                                        0x8
#define SQ_WAVE_HW_ID1__WGP_ID__SHIFT                                                                         0xa
#define SQ_WAVE_HW_ID1__SA_ID__SHIFT                                                                          0x10
#define SQ_WAVE_HW_ID1__SE_ID__SHIFT                                                                          0x12
#define SQ_WAVE_HW_ID1__WAVE_ID_MASK                                                                          0x0000001FL
#define SQ_WAVE_HW_ID1__SIMD_ID_MASK                                                                          0x00000300L
#define SQ_WAVE_HW_ID1__WGP_ID_MASK                                                                           0x00003C00L
#define SQ_WAVE_HW_ID1__SA_ID_MASK                                                                            0x00010000L
#define SQ_WAVE_HW_ID1__SE_ID_MASK                                                                            0x000C0000L
//SQ_WAVE_HW_ID2
#define SQ_WAVE_HW_ID2__QUEUE_ID__SHIFT                                                                       0x0
#define SQ_WAVE_HW_ID2__PIPE_ID__SHIFT                                                                        0x4
#define SQ_WAVE_HW_ID2__ME_ID__SHIFT                                                                          0x8
#define SQ_WAVE_HW_ID2__STATE_ID__SHIFT                                                                       0xc
#define SQ_WAVE_HW_ID2__WG_ID__SHIFT                                                                          0x10
#define SQ_WAVE_HW_ID2__VM_ID__SHIFT                                                                          0x18
#define SQ_WAVE_HW_ID2__QUEUE_ID_MASK                                                                         0x0000000FL
#define SQ_WAVE_HW_ID2__PIPE_ID_MASK                                                                          0x00000030L
#define SQ_WAVE_HW_ID2__ME_ID_MASK                                                                            0x00000300L
#define SQ_WAVE_HW_ID2__STATE_ID_MASK                                                                         0x00007000L
#define SQ_WAVE_HW_ID2__WG_ID_MASK                                                                            0x001F0000L
#define SQ_WAVE_HW_ID2__VM_ID_MASK                                                                            0x0F000000L
//SQ_WAVE_POPS_PACKER
#define SQ_WAVE_POPS_PACKER__POPS_EN__SHIFT                                                                   0x0
#define SQ_WAVE_POPS_PACKER__POPS_PACKER_ID__SHIFT                                                            0x1
#define SQ_WAVE_POPS_PACKER__POPS_EN_MASK                                                                     0x00000001L
#define SQ_WAVE_POPS_PACKER__POPS_PACKER_ID_MASK                                                              0x00000006L
//SQ_WAVE_SCHED_MODE
#define SQ_WAVE_SCHED_MODE__DEP_MODE__SHIFT                                                                   0x0
#define SQ_WAVE_SCHED_MODE__DEP_MODE_MASK                                                                     0x00000003L
//SQ_WAVE_VGPR_OFFSET
#define SQ_WAVE_VGPR_OFFSET__SRC0__SHIFT                                                                      0x0
#define SQ_WAVE_VGPR_OFFSET__SRC1__SHIFT                                                                      0x6
#define SQ_WAVE_VGPR_OFFSET__SRC2__SHIFT                                                                      0xc
#define SQ_WAVE_VGPR_OFFSET__DST__SHIFT                                                                       0x12
#define SQ_WAVE_VGPR_OFFSET__SRC0_MASK                                                                        0x0000003FL
#define SQ_WAVE_VGPR_OFFSET__SRC1_MASK                                                                        0x00000FC0L
#define SQ_WAVE_VGPR_OFFSET__SRC2_MASK                                                                        0x0003F000L
#define SQ_WAVE_VGPR_OFFSET__DST_MASK                                                                         0x00FC0000L
//SQ_WAVE_IB_STS2
#define SQ_WAVE_IB_STS2__INST_PREFETCH__SHIFT                                                                 0x0
#define SQ_WAVE_IB_STS2__RESOURCE_OVERRIDE__SHIFT                                                             0x7
#define SQ_WAVE_IB_STS2__MEM_ORDER__SHIFT                                                                     0x8
#define SQ_WAVE_IB_STS2__FWD_PROGRESS__SHIFT                                                                  0xa
#define SQ_WAVE_IB_STS2__WAVE64__SHIFT                                                                        0xb
#define SQ_WAVE_IB_STS2__INST_PREFETCH_MASK                                                                   0x00000003L
#define SQ_WAVE_IB_STS2__RESOURCE_OVERRIDE_MASK                                                               0x00000080L
#define SQ_WAVE_IB_STS2__MEM_ORDER_MASK                                                                       0x00000300L
#define SQ_WAVE_IB_STS2__FWD_PROGRESS_MASK                                                                    0x00000400L
#define SQ_WAVE_IB_STS2__WAVE64_MASK                                                                          0x00000800L
//SQ_WAVE_SHADER_CYCLES
#define SQ_WAVE_SHADER_CYCLES__CYCLES__SHIFT                                                                  0x0
#define SQ_WAVE_SHADER_CYCLES__CYCLES_MASK                                                                    0x000FFFFFL
//SQ_WAVE_TTMP0
#define SQ_WAVE_TTMP0__DATA__SHIFT                                                                            0x0
#define SQ_WAVE_TTMP0__DATA_MASK                                                                              0xFFFFFFFFL
//SQ_WAVE_TTMP1
#define SQ_WAVE_TTMP1__DATA__SHIFT                                                                            0x0
#define SQ_WAVE_TTMP1__DATA_MASK                                                                              0xFFFFFFFFL
//SQ_WAVE_TTMP2
#define SQ_WAVE_TTMP2__DATA__SHIFT                                                                            0x0
#define SQ_WAVE_TTMP2__DATA_MASK                                                                              0xFFFFFFFFL
//SQ_WAVE_TTMP3
#define SQ_WAVE_TTMP3__DATA__SHIFT                                                                            0x0
#define SQ_WAVE_TTMP3__DATA_MASK                                                                              0xFFFFFFFFL
//SQ_WAVE_TTMP4
#define SQ_WAVE_TTMP4__DATA__SHIFT                                                                            0x0
#define SQ_WAVE_TTMP4__DATA_MASK                                                                              0xFFFFFFFFL
//SQ_WAVE_TTMP5
#define SQ_WAVE_TTMP5__DATA__SHIFT                                                                            0x0
#define SQ_WAVE_TTMP5__DATA_MASK                                                                              0xFFFFFFFFL
//SQ_WAVE_TTMP6
#define SQ_WAVE_TTMP6__DATA__SHIFT                                                                            0x0
#define SQ_WAVE_TTMP6__DATA_MASK                                                                              0xFFFFFFFFL
//SQ_WAVE_TTMP7
#define SQ_WAVE_TTMP7__DATA__SHIFT                                                                            0x0
#define SQ_WAVE_TTMP7__DATA_MASK                                                                              0xFFFFFFFFL
//SQ_WAVE_TTMP8
#define SQ_WAVE_TTMP8__DATA__SHIFT                                                                            0x0
#define SQ_WAVE_TTMP8__DATA_MASK                                                                              0xFFFFFFFFL
//SQ_WAVE_TTMP9
#define SQ_WAVE_TTMP9__DATA__SHIFT                                                                            0x0
#define SQ_WAVE_TTMP9__DATA_MASK                                                                              0xFFFFFFFFL
//SQ_WAVE_TTMP10
#define SQ_WAVE_TTMP10__DATA__SHIFT                                                                           0x0
#define SQ_WAVE_TTMP10__DATA_MASK                                                                             0xFFFFFFFFL
//SQ_WAVE_TTMP11
#define SQ_WAVE_TTMP11__DATA__SHIFT                                                                           0x0
#define SQ_WAVE_TTMP11__DATA_MASK                                                                             0xFFFFFFFFL
//SQ_WAVE_TTMP12
#define SQ_WAVE_TTMP12__DATA__SHIFT                                                                           0x0
#define SQ_WAVE_TTMP12__DATA_MASK                                                                             0xFFFFFFFFL
//SQ_WAVE_TTMP13
#define SQ_WAVE_TTMP13__DATA__SHIFT                                                                           0x0
#define SQ_WAVE_TTMP13__DATA_MASK                                                                             0xFFFFFFFFL
//SQ_WAVE_TTMP14
#define SQ_WAVE_TTMP14__DATA__SHIFT                                                                           0x0
#define SQ_WAVE_TTMP14__DATA_MASK                                                                             0xFFFFFFFFL
//SQ_WAVE_TTMP15
#define SQ_WAVE_TTMP15__DATA__SHIFT                                                                           0x0
#define SQ_WAVE_TTMP15__DATA_MASK                                                                             0xFFFFFFFFL
//SQ_WAVE_M0
#define SQ_WAVE_M0__M0__SHIFT                                                                                 0x0
#define SQ_WAVE_M0__M0_MASK                                                                                   0xFFFFFFFFL
//SQ_WAVE_EXEC_LO
#define SQ_WAVE_EXEC_LO__EXEC_LO__SHIFT                                                                       0x0
#define SQ_WAVE_EXEC_LO__EXEC_LO_MASK                                                                         0xFFFFFFFFL
//SQ_WAVE_EXEC_HI
#define SQ_WAVE_EXEC_HI__EXEC_HI__SHIFT                                                                       0x0
#define SQ_WAVE_EXEC_HI__EXEC_HI_MASK                                                                         0xFFFFFFFFL
//SQ_INTERRUPT_WORD_AUTO
#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE__SHIFT                                                           0x0
#define SQ_INTERRUPT_WORD_AUTO__WLT__SHIFT                                                                    0x1
#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_BUF0_FULL__SHIFT                                                 0x2
#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_BUF1_FULL__SHIFT                                                 0x3
#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_UTC_ERROR__SHIFT                                                 0x8
#define SQ_INTERRUPT_WORD_AUTO__SE_ID__SHIFT                                                                  0x24
#define SQ_INTERRUPT_WORD_AUTO__ENCODING__SHIFT                                                               0x26
#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_MASK                                                             0x0000000001L
#define SQ_INTERRUPT_WORD_AUTO__WLT_MASK                                                                      0x0000000002L
#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_BUF0_FULL_MASK                                                   0x0000000004L
#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_BUF1_FULL_MASK                                                   0x0000000008L
#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_UTC_ERROR_MASK                                                   0x0000000100L
#define SQ_INTERRUPT_WORD_AUTO__SE_ID_MASK                                                                    0x3000000000L
#define SQ_INTERRUPT_WORD_AUTO__ENCODING_MASK                                                                 0xC000000000L
//SQ_INTERRUPT_WORD_ERROR
#define SQ_INTERRUPT_WORD_ERROR__ERR_DETAIL__SHIFT                                                            0x0
#define SQ_INTERRUPT_WORD_ERROR__ERR_TYPE__SHIFT                                                              0x13
#define SQ_INTERRUPT_WORD_ERROR__SA_ID__SHIFT                                                                 0x17
#define SQ_INTERRUPT_WORD_ERROR__PRIV__SHIFT                                                                  0x18
#define SQ_INTERRUPT_WORD_ERROR__WAVE_ID__SHIFT                                                               0x19
#define SQ_INTERRUPT_WORD_ERROR__SIMD_ID__SHIFT                                                               0x1e
#define SQ_INTERRUPT_WORD_ERROR__WGP_ID__SHIFT                                                                0x20
#define SQ_INTERRUPT_WORD_ERROR__SE_ID__SHIFT                                                                 0x24
#define SQ_INTERRUPT_WORD_ERROR__ENCODING__SHIFT                                                              0x26
#define SQ_INTERRUPT_WORD_ERROR__ERR_DETAIL_MASK                                                              0x000007FFFFL
#define SQ_INTERRUPT_WORD_ERROR__ERR_TYPE_MASK                                                                0x0000780000L
#define SQ_INTERRUPT_WORD_ERROR__SA_ID_MASK                                                                   0x0000800000L
#define SQ_INTERRUPT_WORD_ERROR__PRIV_MASK                                                                    0x0001000000L
#define SQ_INTERRUPT_WORD_ERROR__WAVE_ID_MASK                                                                 0x003E000000L
#define SQ_INTERRUPT_WORD_ERROR__SIMD_ID_MASK                                                                 0x00C0000000L
#define SQ_INTERRUPT_WORD_ERROR__WGP_ID_MASK                                                                  0x0F00000000L
#define SQ_INTERRUPT_WORD_ERROR__SE_ID_MASK                                                                   0x3000000000L
#define SQ_INTERRUPT_WORD_ERROR__ENCODING_MASK                                                                0xC000000000L
//SQ_INTERRUPT_WORD_WAVE
#define SQ_INTERRUPT_WORD_WAVE__DATA__SHIFT                                                                   0x0
#define SQ_INTERRUPT_WORD_WAVE__SA_ID__SHIFT                                                                  0x17
#define SQ_INTERRUPT_WORD_WAVE__PRIV__SHIFT                                                                   0x18
#define SQ_INTERRUPT_WORD_WAVE__WAVE_ID__SHIFT                                                                0x19
#define SQ_INTERRUPT_WORD_WAVE__SIMD_ID__SHIFT                                                                0x1e
#define SQ_INTERRUPT_WORD_WAVE__WGP_ID__SHIFT                                                                 0x20
#define SQ_INTERRUPT_WORD_WAVE__SE_ID__SHIFT                                                                  0x24
#define SQ_INTERRUPT_WORD_WAVE__ENCODING__SHIFT                                                               0x26
#define SQ_INTERRUPT_WORD_WAVE__DATA_MASK                                                                     0x00007FFFFFL
#define SQ_INTERRUPT_WORD_WAVE__SA_ID_MASK                                                                    0x0000800000L
#define SQ_INTERRUPT_WORD_WAVE__PRIV_MASK                                                                     0x0001000000L
#define SQ_INTERRUPT_WORD_WAVE__WAVE_ID_MASK                                                                  0x003E000000L
#define SQ_INTERRUPT_WORD_WAVE__SIMD_ID_MASK                                                                  0x00C0000000L
#define SQ_INTERRUPT_WORD_WAVE__WGP_ID_MASK                                                                   0x0F00000000L
#define SQ_INTERRUPT_WORD_WAVE__SE_ID_MASK                                                                    0x3000000000L
#define SQ_INTERRUPT_WORD_WAVE__ENCODING_MASK                                                                 0xC000000000L


// addressBlock: didtind
//DIDT_SQ_CTRL0
#define DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT                                                                    0x0
#define DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT                                                                    0x1
#define DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT                                                                   0x3
#define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT                                                            0x4
#define DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN__SHIFT                                                              0x5
#define DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT                                                             0x6
#define DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT                                                      0x7
#define DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT                                                         0x8
#define DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN__SHIFT                                                                0x18
#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN__SHIFT                                                             0x19
#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT                                                  0x1a
#define DIDT_SQ_CTRL0__DIDT_RLC_FORCE_STALL_EN__SHIFT                                                         0x1b
#define DIDT_SQ_CTRL0__DIDT_RLC_STALL_LEVEL_SEL__SHIFT                                                        0x1c
#define DIDT_SQ_CTRL0__DIDT_THROTTLE_MODE__SHIFT                                                              0x1d
#define DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK                                                                      0x00000001L
#define DIDT_SQ_CTRL0__PHASE_OFFSET_MASK                                                                      0x00000006L
#define DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK                                                                     0x00000008L
#define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK                                                              0x00000010L
#define DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN_MASK                                                                0x00000020L
#define DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN_MASK                                                               0x00000040L
#define DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK                                                        0x00000080L
#define DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK                                                           0x00FFFF00L
#define DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN_MASK                                                                  0x01000000L
#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN_MASK                                                               0x02000000L
#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK                                                    0x04000000L
#define DIDT_SQ_CTRL0__DIDT_RLC_FORCE_STALL_EN_MASK                                                           0x08000000L
#define DIDT_SQ_CTRL0__DIDT_RLC_STALL_LEVEL_SEL_MASK                                                          0x10000000L
#define DIDT_SQ_CTRL0__DIDT_THROTTLE_MODE_MASK                                                                0x20000000L
//DIDT_SQ_CTRL1
#define DIDT_SQ_CTRL1__MIN_POWER__SHIFT                                                                       0x0
#define DIDT_SQ_CTRL1__MAX_POWER__SHIFT                                                                       0x10
#define DIDT_SQ_CTRL1__MIN_POWER_MASK                                                                         0x0000FFFFL
#define DIDT_SQ_CTRL1__MAX_POWER_MASK                                                                         0xFFFF0000L
//DIDT_SQ_CTRL2
#define DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT                                                                 0x0
#define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT                                                        0x10
#define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT                                                        0x1b
#define DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK                                                                   0x00003FFFL
#define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK                                                          0x03FF0000L
#define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK                                                          0x78000000L
//DIDT_SQ_CTRL_OCP
#define DIDT_SQ_CTRL_OCP__OCP_MAX_POWER__SHIFT                                                                0x0
#define DIDT_SQ_CTRL_OCP__OCP_MAX_POWER_MASK                                                                  0x0000FFFFL
//DIDT_SQ_STALL_CTRL
#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT                                                        0x0
#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT                                                        0x6
#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT                                                 0xc
#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT                                                 0x12
#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK                                                          0x0000003FL
#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK                                                          0x00000FC0L
#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK                                                   0x0003F000L
#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK                                                   0x00FC0000L
//DIDT_SQ_TUNING_CTRL
#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT                                                        0x0
#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT                                                        0xe
#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK                                                          0x00003FFFL
#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK                                                          0x0FFFC000L
//DIDT_SQ_STALL_AUTO_RELEASE_CTRL
#define DIDT_SQ_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT                                  0x0
#define DIDT_SQ_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK                                    0x00FFFFFFL
//DIDT_SQ_CTRL3
#define DIDT_SQ_CTRL3__GC_DIDT_ENABLE__SHIFT                                                                  0x0
#define DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT                                                         0x1
#define DIDT_SQ_CTRL3__THROTTLE_POLICY__SHIFT                                                                 0x2
#define DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT                                                    0x4
#define DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT                                                         0x9
#define DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT                                                     0xe
#define DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT                                                           0x16
#define DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT                                                           0x17
#define DIDT_SQ_CTRL3__QUALIFY_STALL_EN__SHIFT                                                                0x18
#define DIDT_SQ_CTRL3__DIDT_STALL_SEL__SHIFT                                                                  0x19
#define DIDT_SQ_CTRL3__DIDT_FORCE_STALL__SHIFT                                                                0x1b
#define DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN__SHIFT                                                             0x1c
#define DIDT_SQ_CTRL3__GC_DIDT_ENABLE_MASK                                                                    0x00000001L
#define DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK                                                           0x00000002L
#define DIDT_SQ_CTRL3__THROTTLE_POLICY_MASK                                                                   0x0000000CL
#define DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK                                                      0x000001F0L
#define DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK                                                           0x00003E00L
#define DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK                                                       0x003FC000L
#define DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK                                                             0x00400000L
#define DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK                                                             0x00800000L
#define DIDT_SQ_CTRL3__QUALIFY_STALL_EN_MASK                                                                  0x01000000L
#define DIDT_SQ_CTRL3__DIDT_STALL_SEL_MASK                                                                    0x06000000L
#define DIDT_SQ_CTRL3__DIDT_FORCE_STALL_MASK                                                                  0x08000000L
#define DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN_MASK                                                               0x10000000L
//DIDT_SQ_STALL_PATTERN_1_2
#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT                                                0x0
#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT                                                0x10
#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK                                                  0x00007FFFL
#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK                                                  0x7FFF0000L
//DIDT_SQ_STALL_PATTERN_3_4
#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT                                                0x0
#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT                                                0x10
#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK                                                  0x00007FFFL
#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK                                                  0x7FFF0000L
//DIDT_SQ_STALL_PATTERN_5_6
#define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT                                                0x0
#define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT                                                0x10
#define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK                                                  0x00007FFFL
#define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK                                                  0x7FFF0000L
//DIDT_SQ_STALL_PATTERN_7
#define DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT                                                  0x0
#define DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK                                                    0x00007FFFL
//DIDT_SQ_MPD_SCALE_FACTOR
#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1__SHIFT                                               0x0
#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2__SHIFT                                               0x4
#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3__SHIFT                                               0x8
#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4__SHIFT                                               0xc
#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0__SHIFT                                                     0x10
#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1__SHIFT                                                     0x14
#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2__SHIFT                                                     0x18
#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3__SHIFT                                                     0x1c
#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1_MASK                                                 0x0000000FL
#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2_MASK                                                 0x000000F0L
#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3_MASK                                                 0x00000F00L
#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4_MASK                                                 0x0000F000L
#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0_MASK                                                       0x000F0000L
#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1_MASK                                                       0x00F00000L
#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2_MASK                                                       0x0F000000L
#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3_MASK                                                       0xF0000000L
//DIDT_SQ_STALL_RELEASE_CNTL0
#define DIDT_SQ_STALL_RELEASE_CNTL0__DIDT_STALL_RELEASE_CNTL_EN__SHIFT                                        0x0
#define DIDT_SQ_STALL_RELEASE_CNTL0__DIDT_STALL_CNTL_SEL__SHIFT                                               0x1
#define DIDT_SQ_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_HI__SHIFT                                             0x2
#define DIDT_SQ_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_LO__SHIFT                                             0xd
#define DIDT_SQ_STALL_RELEASE_CNTL0__DIDT_STALL_RELEASE_CNTL_EN_MASK                                          0x00000001L
#define DIDT_SQ_STALL_RELEASE_CNTL0__DIDT_STALL_CNTL_SEL_MASK                                                 0x00000002L
#define DIDT_SQ_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_HI_MASK                                               0x00001FFCL
#define DIDT_SQ_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_LO_MASK                                               0x00FFE000L
//DIDT_SQ_STALL_RELEASE_CNTL1
#define DIDT_SQ_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI__SHIFT                                      0x0
#define DIDT_SQ_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI__SHIFT                                      0x5
#define DIDT_SQ_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO__SHIFT                                      0xa
#define DIDT_SQ_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO__SHIFT                                      0xf
#define DIDT_SQ_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI_MASK                                        0x0000001FL
#define DIDT_SQ_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI_MASK                                        0x000003E0L
#define DIDT_SQ_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO_MASK                                        0x00007C00L
#define DIDT_SQ_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO_MASK                                        0x000F8000L
//DIDT_SQ_STALL_RELEASE_CNTL_STATUS
#define DIDT_SQ_STALL_RELEASE_CNTL_STATUS__DIDT_STALL_RELEASE_CNTL_FSM_STATE__SHIFT                           0x0
#define DIDT_SQ_STALL_RELEASE_CNTL_STATUS__DIDT_STALL_RELEASE_CNTL_FSM_STATE_MASK                             0x00000003L
//DIDT_SQ_WEIGHT0_3
#define DIDT_SQ_WEIGHT0_3__WEIGHT0__SHIFT                                                                     0x0
#define DIDT_SQ_WEIGHT0_3__WEIGHT1__SHIFT                                                                     0x8
#define DIDT_SQ_WEIGHT0_3__WEIGHT2__SHIFT                                                                     0x10
#define DIDT_SQ_WEIGHT0_3__WEIGHT3__SHIFT                                                                     0x18
#define DIDT_SQ_WEIGHT0_3__WEIGHT0_MASK                                                                       0x000000FFL
#define DIDT_SQ_WEIGHT0_3__WEIGHT1_MASK                                                                       0x0000FF00L
#define DIDT_SQ_WEIGHT0_3__WEIGHT2_MASK                                                                       0x00FF0000L
#define DIDT_SQ_WEIGHT0_3__WEIGHT3_MASK                                                                       0xFF000000L
//DIDT_SQ_WEIGHT4_7
#define DIDT_SQ_WEIGHT4_7__WEIGHT4__SHIFT                                                                     0x0
#define DIDT_SQ_WEIGHT4_7__WEIGHT5__SHIFT                                                                     0x8
#define DIDT_SQ_WEIGHT4_7__WEIGHT6__SHIFT                                                                     0x10
#define DIDT_SQ_WEIGHT4_7__WEIGHT7__SHIFT                                                                     0x18
#define DIDT_SQ_WEIGHT4_7__WEIGHT4_MASK                                                                       0x000000FFL
#define DIDT_SQ_WEIGHT4_7__WEIGHT5_MASK                                                                       0x0000FF00L
#define DIDT_SQ_WEIGHT4_7__WEIGHT6_MASK                                                                       0x00FF0000L
#define DIDT_SQ_WEIGHT4_7__WEIGHT7_MASK                                                                       0xFF000000L
//DIDT_SQ_WEIGHT8_11
#define DIDT_SQ_WEIGHT8_11__WEIGHT8__SHIFT                                                                    0x0
#define DIDT_SQ_WEIGHT8_11__WEIGHT9__SHIFT                                                                    0x8
#define DIDT_SQ_WEIGHT8_11__WEIGHT10__SHIFT                                                                   0x10
#define DIDT_SQ_WEIGHT8_11__WEIGHT11__SHIFT                                                                   0x18
#define DIDT_SQ_WEIGHT8_11__WEIGHT8_MASK                                                                      0x000000FFL
#define DIDT_SQ_WEIGHT8_11__WEIGHT9_MASK                                                                      0x0000FF00L
#define DIDT_SQ_WEIGHT8_11__WEIGHT10_MASK                                                                     0x00FF0000L
#define DIDT_SQ_WEIGHT8_11__WEIGHT11_MASK                                                                     0xFF000000L
//DIDT_SQ_EDC_CTRL
#define DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT                                                                       0x0
#define DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT                                                                   0x1
#define DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT                                                          0x2
#define DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT                                                              0x3
#define DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT                                                  0x4
#define DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT                                                   0x9
#define DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT                                                     0x11
#define DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT                                                                    0x12
#define DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT                                                          0x13
#define DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT                                                         0x15
#define DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT                                                         0x16
#define DIDT_SQ_EDC_CTRL__EDC_LEVEL_MODE_SEL__SHIFT                                                           0x17
#define DIDT_SQ_EDC_CTRL__EDC_LEVEL_COMB_ADAPT_MODE_EN__SHIFT                                                 0x18
#define DIDT_SQ_EDC_CTRL__EDC_EN_MASK                                                                         0x00000001L
#define DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK                                                                     0x00000002L
#define DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK                                                            0x00000004L
#define DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK                                                                0x00000008L
#define DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK                                                    0x000001F0L
#define DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK                                                     0x0001FE00L
#define DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK                                                       0x00020000L
#define DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK                                                                      0x00040000L
#define DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK                                                            0x00180000L
#define DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK                                                           0x00200000L
#define DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK                                                           0x00400000L
#define DIDT_SQ_EDC_CTRL__EDC_LEVEL_MODE_SEL_MASK                                                             0x00800000L
#define DIDT_SQ_EDC_CTRL__EDC_LEVEL_COMB_ADAPT_MODE_EN_MASK                                                   0x01000000L
//DIDT_SQ_EDC_THRESHOLD
#define DIDT_SQ_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT                                                           0x0
#define DIDT_SQ_EDC_THRESHOLD__EDC_THRESHOLD_MASK                                                             0xFFFFFFFFL
//DIDT_SQ_EDC_STALL_PATTERN_1_2
#define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT                                             0x0
#define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT                                             0x10
#define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK                                               0x00007FFFL
#define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK                                               0x7FFF0000L
//DIDT_SQ_EDC_STALL_PATTERN_3_4
#define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT                                             0x0
#define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT                                             0x10
#define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK                                               0x00007FFFL
#define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK                                               0x7FFF0000L
//DIDT_SQ_EDC_STALL_PATTERN_5_6
#define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT                                             0x0
#define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT                                             0x10
#define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK                                               0x00007FFFL
#define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK                                               0x7FFF0000L
//DIDT_SQ_EDC_STALL_PATTERN_7
#define DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT                                               0x0
#define DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK                                                 0x00007FFFL
//DIDT_SQ_EDC_TIMER_PERIOD
#define DIDT_SQ_EDC_TIMER_PERIOD__EDC_TIMER_PERIOD__SHIFT                                                     0x0
#define DIDT_SQ_EDC_TIMER_PERIOD__EDC_TIMER_PERIOD_MASK                                                       0x00003FFFL
//DIDT_SQ_THROTTLE_CTRL
#define DIDT_SQ_THROTTLE_CTRL__GC_EDC_STALL_EN__SHIFT                                                         0x0
#define DIDT_SQ_THROTTLE_CTRL__PCC_STALL_EN__SHIFT                                                            0x1
#define DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT                                                         0x2
#define DIDT_SQ_THROTTLE_CTRL__GC_EDC_ONLY_MODE__SHIFT                                                        0x3
#define DIDT_SQ_THROTTLE_CTRL__GC_EDC_STALL_EN_MASK                                                           0x00000001L
#define DIDT_SQ_THROTTLE_CTRL__PCC_STALL_EN_MASK                                                              0x00000002L
#define DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN_MASK                                                           0x00000004L
#define DIDT_SQ_THROTTLE_CTRL__GC_EDC_ONLY_MODE_MASK                                                          0x00000008L
//DIDT_SQ_EDC_STALL_DELAY_1
#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0__SHIFT                                                 0x0
#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1__SHIFT                                                 0x6
#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2__SHIFT                                                 0xc
#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3__SHIFT                                                 0x12
#define DIDT_SQ_EDC_STALL_DELAY_1__UNUSED__SHIFT                                                              0x18
#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0_MASK                                                   0x0000003FL
#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1_MASK                                                   0x00000FC0L
#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2_MASK                                                   0x0003F000L
#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3_MASK                                                   0x00FC0000L
#define DIDT_SQ_EDC_STALL_DELAY_1__UNUSED_MASK                                                                0xFF000000L
//DIDT_SQ_EDC_STALL_DELAY_2
#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4__SHIFT                                                 0x0
#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ5__SHIFT                                                 0x6
#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ6__SHIFT                                                 0xc
#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ7__SHIFT                                                 0x12
#define DIDT_SQ_EDC_STALL_DELAY_2__UNUSED__SHIFT                                                              0x18
#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4_MASK                                                   0x0000003FL
#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ5_MASK                                                   0x00000FC0L
#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ6_MASK                                                   0x0003F000L
#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ7_MASK                                                   0x00FC0000L
#define DIDT_SQ_EDC_STALL_DELAY_2__UNUSED_MASK                                                                0xFF000000L
//DIDT_SQ_EDC_STALL_DELAY_3
#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ8__SHIFT                                                 0x0
#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ9__SHIFT                                                 0x6
#define DIDT_SQ_EDC_STALL_DELAY_3__UNUSED__SHIFT                                                              0xc
#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ8_MASK                                                   0x0000003FL
#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ9_MASK                                                   0x00000FC0L
#define DIDT_SQ_EDC_STALL_DELAY_3__UNUSED_MASK                                                                0xFFFFF000L
//DIDT_SQ_EDC_STATUS
#define DIDT_SQ_EDC_STATUS__EDC_FSM_STATE__SHIFT                                                              0x0
#define DIDT_SQ_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT                                                         0x1
#define DIDT_SQ_EDC_STATUS__EDC_FSM_STATE_MASK                                                                0x00000001L
#define DIDT_SQ_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK                                                           0x0000000EL
//DIDT_SQ_EDC_OVERFLOW
#define DIDT_SQ_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT                                         0x0
#define DIDT_SQ_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT                                      0x1
#define DIDT_SQ_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK                                           0x00000001L
#define DIDT_SQ_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK                                        0x0001FFFEL
//DIDT_SQ_EDC_ROLLING_POWER_DELTA
#define DIDT_SQ_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT                                       0x0
#define DIDT_SQ_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK                                         0xFFFFFFFFL
//DIDT_SQ_EDC_PCC_PERF_COUNTER
#define DIDT_SQ_EDC_PCC_PERF_COUNTER__EDC_PCC_PERF_COUNTER__SHIFT                                             0x0
#define DIDT_SQ_EDC_PCC_PERF_COUNTER__EDC_PCC_PERF_COUNTER_MASK                                               0xFFFFFFFFL
//DIDT_DB_CTRL0
#define DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT                                                                    0x0
#define DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT                                                                    0x1
#define DIDT_DB_CTRL0__DIDT_CTRL_RST__SHIFT                                                                   0x3
#define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT                                                            0x4
#define DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN__SHIFT                                                              0x5
#define DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT                                                             0x6
#define DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT                                                      0x7
#define DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT                                                         0x8
#define DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN__SHIFT                                                                0x18
#define DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN__SHIFT                                                             0x19
#define DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT                                                  0x1a
#define DIDT_DB_CTRL0__DIDT_RLC_FORCE_STALL_EN__SHIFT                                                         0x1b
#define DIDT_DB_CTRL0__DIDT_RLC_STALL_LEVEL_SEL__SHIFT                                                        0x1c
#define DIDT_DB_CTRL0__DIDT_THROTTLE_MODE__SHIFT                                                              0x1d
#define DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK                                                                      0x00000001L
#define DIDT_DB_CTRL0__PHASE_OFFSET_MASK                                                                      0x00000006L
#define DIDT_DB_CTRL0__DIDT_CTRL_RST_MASK                                                                     0x00000008L
#define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK                                                              0x00000010L
#define DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN_MASK                                                                0x00000020L
#define DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN_MASK                                                               0x00000040L
#define DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK                                                        0x00000080L
#define DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK                                                           0x00FFFF00L
#define DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN_MASK                                                                  0x01000000L
#define DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN_MASK                                                               0x02000000L
#define DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK                                                    0x04000000L
#define DIDT_DB_CTRL0__DIDT_RLC_FORCE_STALL_EN_MASK                                                           0x08000000L
#define DIDT_DB_CTRL0__DIDT_RLC_STALL_LEVEL_SEL_MASK                                                          0x10000000L
#define DIDT_DB_CTRL0__DIDT_THROTTLE_MODE_MASK                                                                0x20000000L
//DIDT_DB_CTRL1
#define DIDT_DB_CTRL1__MIN_POWER__SHIFT                                                                       0x0
#define DIDT_DB_CTRL1__MAX_POWER__SHIFT                                                                       0x10
#define DIDT_DB_CTRL1__MIN_POWER_MASK                                                                         0x0000FFFFL
#define DIDT_DB_CTRL1__MAX_POWER_MASK                                                                         0xFFFF0000L
//DIDT_DB_CTRL2
#define DIDT_DB_CTRL2__MAX_POWER_DELTA__SHIFT                                                                 0x0
#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT                                                        0x10
#define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT                                                        0x1b
#define DIDT_DB_CTRL2__MAX_POWER_DELTA_MASK                                                                   0x00003FFFL
#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK                                                          0x03FF0000L
#define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK                                                          0x78000000L
//DIDT_DB_CTRL_OCP
#define DIDT_DB_CTRL_OCP__OCP_MAX_POWER__SHIFT                                                                0x0
#define DIDT_DB_CTRL_OCP__OCP_MAX_POWER_MASK                                                                  0x0000FFFFL
//DIDT_DB_STALL_CTRL
#define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT                                                        0x0
#define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT                                                        0x6
#define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT                                                 0xc
#define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT                                                 0x12
#define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK                                                          0x0000003FL
#define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK                                                          0x00000FC0L
#define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK                                                   0x0003F000L
#define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK                                                   0x00FC0000L
//DIDT_DB_TUNING_CTRL
#define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT                                                        0x0
#define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT                                                        0xe
#define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK                                                          0x00003FFFL
#define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK                                                          0x0FFFC000L
//DIDT_DB_STALL_AUTO_RELEASE_CTRL
#define DIDT_DB_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT                                  0x0
#define DIDT_DB_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK                                    0x00FFFFFFL
//DIDT_DB_CTRL3
#define DIDT_DB_CTRL3__GC_DIDT_ENABLE__SHIFT                                                                  0x0
#define DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT                                                         0x1
#define DIDT_DB_CTRL3__THROTTLE_POLICY__SHIFT                                                                 0x2
#define DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT                                                    0x4
#define DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT                                                         0x9
#define DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT                                                     0xe
#define DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT                                                           0x16
#define DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT                                                           0x17
#define DIDT_DB_CTRL3__QUALIFY_STALL_EN__SHIFT                                                                0x18
#define DIDT_DB_CTRL3__DIDT_STALL_SEL__SHIFT                                                                  0x19
#define DIDT_DB_CTRL3__DIDT_FORCE_STALL__SHIFT                                                                0x1b
#define DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN__SHIFT                                                             0x1c
#define DIDT_DB_CTRL3__GC_DIDT_ENABLE_MASK                                                                    0x00000001L
#define DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK                                                           0x00000002L
#define DIDT_DB_CTRL3__THROTTLE_POLICY_MASK                                                                   0x0000000CL
#define DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK                                                      0x000001F0L
#define DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK                                                           0x00003E00L
#define DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK                                                       0x003FC000L
#define DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK                                                             0x00400000L
#define DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK                                                             0x00800000L
#define DIDT_DB_CTRL3__QUALIFY_STALL_EN_MASK                                                                  0x01000000L
#define DIDT_DB_CTRL3__DIDT_STALL_SEL_MASK                                                                    0x06000000L
#define DIDT_DB_CTRL3__DIDT_FORCE_STALL_MASK                                                                  0x08000000L
#define DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN_MASK                                                               0x10000000L
//DIDT_DB_STALL_PATTERN_1_2
#define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT                                                0x0
#define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT                                                0x10
#define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK                                                  0x00007FFFL
#define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK                                                  0x7FFF0000L
//DIDT_DB_STALL_PATTERN_3_4
#define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT                                                0x0
#define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT                                                0x10
#define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK                                                  0x00007FFFL
#define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK                                                  0x7FFF0000L
//DIDT_DB_STALL_PATTERN_5_6
#define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT                                                0x0
#define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT                                                0x10
#define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK                                                  0x00007FFFL
#define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK                                                  0x7FFF0000L
//DIDT_DB_STALL_PATTERN_7
#define DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT                                                  0x0
#define DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK                                                    0x00007FFFL
//DIDT_DB_MPD_SCALE_FACTOR
#define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1__SHIFT                                               0x0
#define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2__SHIFT                                               0x4
#define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3__SHIFT                                               0x8
#define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4__SHIFT                                               0xc
#define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0__SHIFT                                                     0x10
#define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1__SHIFT                                                     0x14
#define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2__SHIFT                                                     0x18
#define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3__SHIFT                                                     0x1c
#define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1_MASK                                                 0x0000000FL
#define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2_MASK                                                 0x000000F0L
#define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3_MASK                                                 0x00000F00L
#define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4_MASK                                                 0x0000F000L
#define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0_MASK                                                       0x000F0000L
#define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1_MASK                                                       0x00F00000L
#define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2_MASK                                                       0x0F000000L
#define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3_MASK                                                       0xF0000000L
//DIDT_DB_STALL_RELEASE_CNTL0
#define DIDT_DB_STALL_RELEASE_CNTL0__DIDT_STALL_RELEASE_CNTL_EN__SHIFT                                        0x0
#define DIDT_DB_STALL_RELEASE_CNTL0__DIDT_STALL_CNTL_SEL__SHIFT                                               0x1
#define DIDT_DB_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_HI__SHIFT                                             0x2
#define DIDT_DB_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_LO__SHIFT                                             0xd
#define DIDT_DB_STALL_RELEASE_CNTL0__DIDT_STALL_RELEASE_CNTL_EN_MASK                                          0x00000001L
#define DIDT_DB_STALL_RELEASE_CNTL0__DIDT_STALL_CNTL_SEL_MASK                                                 0x00000002L
#define DIDT_DB_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_HI_MASK                                               0x00001FFCL
#define DIDT_DB_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_LO_MASK                                               0x00FFE000L
//DIDT_DB_STALL_RELEASE_CNTL1
#define DIDT_DB_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI__SHIFT                                      0x0
#define DIDT_DB_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI__SHIFT                                      0x5
#define DIDT_DB_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO__SHIFT                                      0xa
#define DIDT_DB_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO__SHIFT                                      0xf
#define DIDT_DB_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI_MASK                                        0x0000001FL
#define DIDT_DB_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI_MASK                                        0x000003E0L
#define DIDT_DB_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO_MASK                                        0x00007C00L
#define DIDT_DB_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO_MASK                                        0x000F8000L
//DIDT_DB_STALL_RELEASE_CNTL_STATUS
#define DIDT_DB_STALL_RELEASE_CNTL_STATUS__DIDT_STALL_RELEASE_CNTL_FSM_STATE__SHIFT                           0x0
#define DIDT_DB_STALL_RELEASE_CNTL_STATUS__DIDT_STALL_RELEASE_CNTL_FSM_STATE_MASK                             0x00000003L
//DIDT_DB_WEIGHT0_3
#define DIDT_DB_WEIGHT0_3__WEIGHT0__SHIFT                                                                     0x0
#define DIDT_DB_WEIGHT0_3__WEIGHT1__SHIFT                                                                     0x8
#define DIDT_DB_WEIGHT0_3__WEIGHT2__SHIFT                                                                     0x10
#define DIDT_DB_WEIGHT0_3__WEIGHT3__SHIFT                                                                     0x18
#define DIDT_DB_WEIGHT0_3__WEIGHT0_MASK                                                                       0x000000FFL
#define DIDT_DB_WEIGHT0_3__WEIGHT1_MASK                                                                       0x0000FF00L
#define DIDT_DB_WEIGHT0_3__WEIGHT2_MASK                                                                       0x00FF0000L
#define DIDT_DB_WEIGHT0_3__WEIGHT3_MASK                                                                       0xFF000000L
//DIDT_DB_WEIGHT4_7
#define DIDT_DB_WEIGHT4_7__WEIGHT4__SHIFT                                                                     0x0
#define DIDT_DB_WEIGHT4_7__WEIGHT5__SHIFT                                                                     0x8
#define DIDT_DB_WEIGHT4_7__WEIGHT6__SHIFT                                                                     0x10
#define DIDT_DB_WEIGHT4_7__WEIGHT7__SHIFT                                                                     0x18
#define DIDT_DB_WEIGHT4_7__WEIGHT4_MASK                                                                       0x000000FFL
#define DIDT_DB_WEIGHT4_7__WEIGHT5_MASK                                                                       0x0000FF00L
#define DIDT_DB_WEIGHT4_7__WEIGHT6_MASK                                                                       0x00FF0000L
#define DIDT_DB_WEIGHT4_7__WEIGHT7_MASK                                                                       0xFF000000L
//DIDT_DB_WEIGHT8_11
#define DIDT_DB_WEIGHT8_11__WEIGHT8__SHIFT                                                                    0x0
#define DIDT_DB_WEIGHT8_11__WEIGHT9__SHIFT                                                                    0x8
#define DIDT_DB_WEIGHT8_11__WEIGHT10__SHIFT                                                                   0x10
#define DIDT_DB_WEIGHT8_11__WEIGHT11__SHIFT                                                                   0x18
#define DIDT_DB_WEIGHT8_11__WEIGHT8_MASK                                                                      0x000000FFL
#define DIDT_DB_WEIGHT8_11__WEIGHT9_MASK                                                                      0x0000FF00L
#define DIDT_DB_WEIGHT8_11__WEIGHT10_MASK                                                                     0x00FF0000L
#define DIDT_DB_WEIGHT8_11__WEIGHT11_MASK                                                                     0xFF000000L
//DIDT_DB_EDC_CTRL
#define DIDT_DB_EDC_CTRL__EDC_EN__SHIFT                                                                       0x0
#define DIDT_DB_EDC_CTRL__EDC_SW_RST__SHIFT                                                                   0x1
#define DIDT_DB_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT                                                          0x2
#define DIDT_DB_EDC_CTRL__EDC_FORCE_STALL__SHIFT                                                              0x3
#define DIDT_DB_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT                                                  0x4
#define DIDT_DB_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT                                                   0x9
#define DIDT_DB_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT                                                     0x11
#define DIDT_DB_EDC_CTRL__GC_EDC_EN__SHIFT                                                                    0x12
#define DIDT_DB_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT                                                          0x13
#define DIDT_DB_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT                                                         0x15
#define DIDT_DB_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT                                                         0x16
#define DIDT_DB_EDC_CTRL__EDC_LEVEL_MODE_SEL__SHIFT                                                           0x17
#define DIDT_DB_EDC_CTRL__EDC_LEVEL_COMB_ADAPT_MODE_EN__SHIFT                                                 0x18
#define DIDT_DB_EDC_CTRL__EDC_EN_MASK                                                                         0x00000001L
#define DIDT_DB_EDC_CTRL__EDC_SW_RST_MASK                                                                     0x00000002L
#define DIDT_DB_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK                                                            0x00000004L
#define DIDT_DB_EDC_CTRL__EDC_FORCE_STALL_MASK                                                                0x00000008L
#define DIDT_DB_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK                                                    0x000001F0L
#define DIDT_DB_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK                                                     0x0001FE00L
#define DIDT_DB_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK                                                       0x00020000L
#define DIDT_DB_EDC_CTRL__GC_EDC_EN_MASK                                                                      0x00040000L
#define DIDT_DB_EDC_CTRL__GC_EDC_STALL_POLICY_MASK                                                            0x00180000L
#define DIDT_DB_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK                                                           0x00200000L
#define DIDT_DB_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK                                                           0x00400000L
#define DIDT_DB_EDC_CTRL__EDC_LEVEL_MODE_SEL_MASK                                                             0x00800000L
#define DIDT_DB_EDC_CTRL__EDC_LEVEL_COMB_ADAPT_MODE_EN_MASK                                                   0x01000000L
//DIDT_DB_EDC_THRESHOLD
#define DIDT_DB_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT                                                           0x0
#define DIDT_DB_EDC_THRESHOLD__EDC_THRESHOLD_MASK                                                             0xFFFFFFFFL
//DIDT_DB_EDC_STALL_PATTERN_1_2
#define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT                                             0x0
#define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT                                             0x10
#define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK                                               0x00007FFFL
#define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK                                               0x7FFF0000L
//DIDT_DB_EDC_STALL_PATTERN_3_4
#define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT                                             0x0
#define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT                                             0x10
#define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK                                               0x00007FFFL
#define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK                                               0x7FFF0000L
//DIDT_DB_EDC_STALL_PATTERN_5_6
#define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT                                             0x0
#define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT                                             0x10
#define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK                                               0x00007FFFL
#define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK                                               0x7FFF0000L
//DIDT_DB_EDC_STALL_PATTERN_7
#define DIDT_DB_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT                                               0x0
#define DIDT_DB_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK                                                 0x00007FFFL
//DIDT_DB_EDC_TIMER_PERIOD
#define DIDT_DB_EDC_TIMER_PERIOD__EDC_TIMER_PERIOD__SHIFT                                                     0x0
#define DIDT_DB_EDC_TIMER_PERIOD__EDC_TIMER_PERIOD_MASK                                                       0x00003FFFL
//DIDT_DB_THROTTLE_CTRL
#define DIDT_DB_THROTTLE_CTRL__GC_EDC_STALL_EN__SHIFT                                                         0x0
#define DIDT_DB_THROTTLE_CTRL__PCC_STALL_EN__SHIFT                                                            0x1
#define DIDT_DB_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT                                                         0x2
#define DIDT_DB_THROTTLE_CTRL__GC_EDC_ONLY_MODE__SHIFT                                                        0x3
#define DIDT_DB_THROTTLE_CTRL__GC_EDC_STALL_EN_MASK                                                           0x00000001L
#define DIDT_DB_THROTTLE_CTRL__PCC_STALL_EN_MASK                                                              0x00000002L
#define DIDT_DB_THROTTLE_CTRL__PWRBRK_STALL_EN_MASK                                                           0x00000004L
#define DIDT_DB_THROTTLE_CTRL__GC_EDC_ONLY_MODE_MASK                                                          0x00000008L
//DIDT_DB_EDC_STALL_DELAY_1
#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB0__SHIFT                                                 0x0
#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB1__SHIFT                                                 0x4
#define DIDT_DB_EDC_STALL_DELAY_1__UNUSED__SHIFT                                                              0x8
#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB0_MASK                                                   0x0000000FL
#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB1_MASK                                                   0x000000F0L
#define DIDT_DB_EDC_STALL_DELAY_1__UNUSED_MASK                                                                0xFFFFFF00L
//DIDT_DB_EDC_STATUS
#define DIDT_DB_EDC_STATUS__EDC_FSM_STATE__SHIFT                                                              0x0
#define DIDT_DB_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT                                                         0x1
#define DIDT_DB_EDC_STATUS__EDC_FSM_STATE_MASK                                                                0x00000001L
#define DIDT_DB_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK                                                           0x0000000EL
//DIDT_DB_EDC_OVERFLOW
#define DIDT_DB_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT                                         0x0
#define DIDT_DB_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT                                      0x1
#define DIDT_DB_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK                                           0x00000001L
#define DIDT_DB_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK                                        0x0001FFFEL
//DIDT_DB_EDC_ROLLING_POWER_DELTA
#define DIDT_DB_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT                                       0x0
#define DIDT_DB_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK                                         0xFFFFFFFFL
//DIDT_DB_EDC_PCC_PERF_COUNTER
#define DIDT_DB_EDC_PCC_PERF_COUNTER__EDC_PCC_PERF_COUNTER__SHIFT                                             0x0
#define DIDT_DB_EDC_PCC_PERF_COUNTER__EDC_PCC_PERF_COUNTER_MASK                                               0xFFFFFFFFL
//DIDT_TD_CTRL0
#define DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT                                                                    0x0
#define DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT                                                                    0x1
#define DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT                                                                   0x3
#define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT                                                            0x4
#define DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN__SHIFT                                                              0x5
#define DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT                                                             0x6
#define DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT                                                      0x7
#define DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT                                                         0x8
#define DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN__SHIFT                                                                0x18
#define DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN__SHIFT                                                             0x19
#define DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT                                                  0x1a
#define DIDT_TD_CTRL0__DIDT_RLC_FORCE_STALL_EN__SHIFT                                                         0x1b
#define DIDT_TD_CTRL0__DIDT_RLC_STALL_LEVEL_SEL__SHIFT                                                        0x1c
#define DIDT_TD_CTRL0__DIDT_THROTTLE_MODE__SHIFT                                                              0x1d
#define DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK                                                                      0x00000001L
#define DIDT_TD_CTRL0__PHASE_OFFSET_MASK                                                                      0x00000006L
#define DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK                                                                     0x00000008L
#define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK                                                              0x00000010L
#define DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN_MASK                                                                0x00000020L
#define DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN_MASK                                                               0x00000040L
#define DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK                                                        0x00000080L
#define DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK                                                           0x00FFFF00L
#define DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN_MASK                                                                  0x01000000L
#define DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN_MASK                                                               0x02000000L
#define DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK                                                    0x04000000L
#define DIDT_TD_CTRL0__DIDT_RLC_FORCE_STALL_EN_MASK                                                           0x08000000L
#define DIDT_TD_CTRL0__DIDT_RLC_STALL_LEVEL_SEL_MASK                                                          0x10000000L
#define DIDT_TD_CTRL0__DIDT_THROTTLE_MODE_MASK                                                                0x20000000L
//DIDT_TD_CTRL1
#define DIDT_TD_CTRL1__MIN_POWER__SHIFT                                                                       0x0
#define DIDT_TD_CTRL1__MAX_POWER__SHIFT                                                                       0x10
#define DIDT_TD_CTRL1__MIN_POWER_MASK                                                                         0x0000FFFFL
#define DIDT_TD_CTRL1__MAX_POWER_MASK                                                                         0xFFFF0000L
//DIDT_TD_CTRL2
#define DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT                                                                 0x0
#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT                                                        0x10
#define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT                                                        0x1b
#define DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK                                                                   0x00003FFFL
#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK                                                          0x03FF0000L
#define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK                                                          0x78000000L
//DIDT_TD_CTRL_OCP
#define DIDT_TD_CTRL_OCP__OCP_MAX_POWER__SHIFT                                                                0x0
#define DIDT_TD_CTRL_OCP__OCP_MAX_POWER_MASK                                                                  0x0000FFFFL
//DIDT_TD_STALL_CTRL
#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT                                                        0x0
#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT                                                        0x6
#define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT                                                 0xc
#define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT                                                 0x12
#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK                                                          0x0000003FL
#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK                                                          0x00000FC0L
#define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK                                                   0x0003F000L
#define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK                                                   0x00FC0000L
//DIDT_TD_TUNING_CTRL
#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT                                                        0x0
#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT                                                        0xe
#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK                                                          0x00003FFFL
#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK                                                          0x0FFFC000L
//DIDT_TD_STALL_AUTO_RELEASE_CTRL
#define DIDT_TD_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT                                  0x0
#define DIDT_TD_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK                                    0x00FFFFFFL
//DIDT_TD_CTRL3
#define DIDT_TD_CTRL3__GC_DIDT_ENABLE__SHIFT                                                                  0x0
#define DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT                                                         0x1
#define DIDT_TD_CTRL3__THROTTLE_POLICY__SHIFT                                                                 0x2
#define DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT                                                    0x4
#define DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT                                                         0x9
#define DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT                                                     0xe
#define DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT                                                           0x16
#define DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT                                                           0x17
#define DIDT_TD_CTRL3__QUALIFY_STALL_EN__SHIFT                                                                0x18
#define DIDT_TD_CTRL3__DIDT_STALL_SEL__SHIFT                                                                  0x19
#define DIDT_TD_CTRL3__DIDT_FORCE_STALL__SHIFT                                                                0x1b
#define DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN__SHIFT                                                             0x1c
#define DIDT_TD_CTRL3__GC_DIDT_ENABLE_MASK                                                                    0x00000001L
#define DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK                                                           0x00000002L
#define DIDT_TD_CTRL3__THROTTLE_POLICY_MASK                                                                   0x0000000CL
#define DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK                                                      0x000001F0L
#define DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK                                                           0x00003E00L
#define DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK                                                       0x003FC000L
#define DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK                                                             0x00400000L
#define DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK                                                             0x00800000L
#define DIDT_TD_CTRL3__QUALIFY_STALL_EN_MASK                                                                  0x01000000L
#define DIDT_TD_CTRL3__DIDT_STALL_SEL_MASK                                                                    0x06000000L
#define DIDT_TD_CTRL3__DIDT_FORCE_STALL_MASK                                                                  0x08000000L
#define DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN_MASK                                                               0x10000000L
//DIDT_TD_STALL_PATTERN_1_2
#define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT                                                0x0
#define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT                                                0x10
#define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK                                                  0x00007FFFL
#define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK                                                  0x7FFF0000L
//DIDT_TD_STALL_PATTERN_3_4
#define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT                                                0x0
#define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT                                                0x10
#define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK                                                  0x00007FFFL
#define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK                                                  0x7FFF0000L
//DIDT_TD_STALL_PATTERN_5_6
#define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT                                                0x0
#define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT                                                0x10
#define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK                                                  0x00007FFFL
#define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK                                                  0x7FFF0000L
//DIDT_TD_STALL_PATTERN_7
#define DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT                                                  0x0
#define DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK                                                    0x00007FFFL
//DIDT_TD_MPD_SCALE_FACTOR
#define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1__SHIFT                                               0x0
#define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2__SHIFT                                               0x4
#define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3__SHIFT                                               0x8
#define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4__SHIFT                                               0xc
#define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0__SHIFT                                                     0x10
#define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1__SHIFT                                                     0x14
#define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2__SHIFT                                                     0x18
#define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3__SHIFT                                                     0x1c
#define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1_MASK                                                 0x0000000FL
#define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2_MASK                                                 0x000000F0L
#define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3_MASK                                                 0x00000F00L
#define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4_MASK                                                 0x0000F000L
#define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0_MASK                                                       0x000F0000L
#define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1_MASK                                                       0x00F00000L
#define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2_MASK                                                       0x0F000000L
#define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3_MASK                                                       0xF0000000L
//DIDT_TD_STALL_RELEASE_CNTL0
#define DIDT_TD_STALL_RELEASE_CNTL0__DIDT_STALL_RELEASE_CNTL_EN__SHIFT                                        0x0
#define DIDT_TD_STALL_RELEASE_CNTL0__DIDT_STALL_CNTL_SEL__SHIFT                                               0x1
#define DIDT_TD_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_HI__SHIFT                                             0x2
#define DIDT_TD_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_LO__SHIFT                                             0xd
#define DIDT_TD_STALL_RELEASE_CNTL0__DIDT_STALL_RELEASE_CNTL_EN_MASK                                          0x00000001L
#define DIDT_TD_STALL_RELEASE_CNTL0__DIDT_STALL_CNTL_SEL_MASK                                                 0x00000002L
#define DIDT_TD_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_HI_MASK                                               0x00001FFCL
#define DIDT_TD_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_LO_MASK                                               0x00FFE000L
//DIDT_TD_STALL_RELEASE_CNTL1
#define DIDT_TD_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI__SHIFT                                      0x0
#define DIDT_TD_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI__SHIFT                                      0x5
#define DIDT_TD_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO__SHIFT                                      0xa
#define DIDT_TD_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO__SHIFT                                      0xf
#define DIDT_TD_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI_MASK                                        0x0000001FL
#define DIDT_TD_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI_MASK                                        0x000003E0L
#define DIDT_TD_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO_MASK                                        0x00007C00L
#define DIDT_TD_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO_MASK                                        0x000F8000L
//DIDT_TD_STALL_RELEASE_CNTL_STATUS
#define DIDT_TD_STALL_RELEASE_CNTL_STATUS__DIDT_STALL_RELEASE_CNTL_FSM_STATE__SHIFT                           0x0
#define DIDT_TD_STALL_RELEASE_CNTL_STATUS__DIDT_STALL_RELEASE_CNTL_FSM_STATE_MASK                             0x00000003L
//DIDT_TD_WEIGHT0_3
#define DIDT_TD_WEIGHT0_3__WEIGHT0__SHIFT                                                                     0x0
#define DIDT_TD_WEIGHT0_3__WEIGHT1__SHIFT                                                                     0x8
#define DIDT_TD_WEIGHT0_3__WEIGHT2__SHIFT                                                                     0x10
#define DIDT_TD_WEIGHT0_3__WEIGHT3__SHIFT                                                                     0x18
#define DIDT_TD_WEIGHT0_3__WEIGHT0_MASK                                                                       0x000000FFL
#define DIDT_TD_WEIGHT0_3__WEIGHT1_MASK                                                                       0x0000FF00L
#define DIDT_TD_WEIGHT0_3__WEIGHT2_MASK                                                                       0x00FF0000L
#define DIDT_TD_WEIGHT0_3__WEIGHT3_MASK                                                                       0xFF000000L
//DIDT_TD_WEIGHT4_7
#define DIDT_TD_WEIGHT4_7__WEIGHT4__SHIFT                                                                     0x0
#define DIDT_TD_WEIGHT4_7__WEIGHT5__SHIFT                                                                     0x8
#define DIDT_TD_WEIGHT4_7__WEIGHT6__SHIFT                                                                     0x10
#define DIDT_TD_WEIGHT4_7__WEIGHT7__SHIFT                                                                     0x18
#define DIDT_TD_WEIGHT4_7__WEIGHT4_MASK                                                                       0x000000FFL
#define DIDT_TD_WEIGHT4_7__WEIGHT5_MASK                                                                       0x0000FF00L
#define DIDT_TD_WEIGHT4_7__WEIGHT6_MASK                                                                       0x00FF0000L
#define DIDT_TD_WEIGHT4_7__WEIGHT7_MASK                                                                       0xFF000000L
//DIDT_TD_WEIGHT8_11
#define DIDT_TD_WEIGHT8_11__WEIGHT8__SHIFT                                                                    0x0
#define DIDT_TD_WEIGHT8_11__WEIGHT9__SHIFT                                                                    0x8
#define DIDT_TD_WEIGHT8_11__WEIGHT10__SHIFT                                                                   0x10
#define DIDT_TD_WEIGHT8_11__WEIGHT11__SHIFT                                                                   0x18
#define DIDT_TD_WEIGHT8_11__WEIGHT8_MASK                                                                      0x000000FFL
#define DIDT_TD_WEIGHT8_11__WEIGHT9_MASK                                                                      0x0000FF00L
#define DIDT_TD_WEIGHT8_11__WEIGHT10_MASK                                                                     0x00FF0000L
#define DIDT_TD_WEIGHT8_11__WEIGHT11_MASK                                                                     0xFF000000L
//DIDT_TD_EDC_CTRL
#define DIDT_TD_EDC_CTRL__EDC_EN__SHIFT                                                                       0x0
#define DIDT_TD_EDC_CTRL__EDC_SW_RST__SHIFT                                                                   0x1
#define DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT                                                          0x2
#define DIDT_TD_EDC_CTRL__EDC_FORCE_STALL__SHIFT                                                              0x3
#define DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT                                                  0x4
#define DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT                                                   0x9
#define DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT                                                     0x11
#define DIDT_TD_EDC_CTRL__GC_EDC_EN__SHIFT                                                                    0x12
#define DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT                                                          0x13
#define DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT                                                         0x15
#define DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT                                                         0x16
#define DIDT_TD_EDC_CTRL__EDC_LEVEL_MODE_SEL__SHIFT                                                           0x17
#define DIDT_TD_EDC_CTRL__EDC_LEVEL_COMB_ADAPT_MODE_EN__SHIFT                                                 0x18
#define DIDT_TD_EDC_CTRL__EDC_EN_MASK                                                                         0x00000001L
#define DIDT_TD_EDC_CTRL__EDC_SW_RST_MASK                                                                     0x00000002L
#define DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK                                                            0x00000004L
#define DIDT_TD_EDC_CTRL__EDC_FORCE_STALL_MASK                                                                0x00000008L
#define DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK                                                    0x000001F0L
#define DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK                                                     0x0001FE00L
#define DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK                                                       0x00020000L
#define DIDT_TD_EDC_CTRL__GC_EDC_EN_MASK                                                                      0x00040000L
#define DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY_MASK                                                            0x00180000L
#define DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK                                                           0x00200000L
#define DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK                                                           0x00400000L
#define DIDT_TD_EDC_CTRL__EDC_LEVEL_MODE_SEL_MASK                                                             0x00800000L
#define DIDT_TD_EDC_CTRL__EDC_LEVEL_COMB_ADAPT_MODE_EN_MASK                                                   0x01000000L
//DIDT_TD_EDC_THRESHOLD
#define DIDT_TD_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT                                                           0x0
#define DIDT_TD_EDC_THRESHOLD__EDC_THRESHOLD_MASK                                                             0xFFFFFFFFL
//DIDT_TD_EDC_STALL_PATTERN_1_2
#define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT                                             0x0
#define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT                                             0x10
#define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK                                               0x00007FFFL
#define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK                                               0x7FFF0000L
//DIDT_TD_EDC_STALL_PATTERN_3_4
#define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT                                             0x0
#define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT                                             0x10
#define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK                                               0x00007FFFL
#define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK                                               0x7FFF0000L
//DIDT_TD_EDC_STALL_PATTERN_5_6
#define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT                                             0x0
#define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT                                             0x10
#define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK                                               0x00007FFFL
#define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK                                               0x7FFF0000L
//DIDT_TD_EDC_STALL_PATTERN_7
#define DIDT_TD_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT                                               0x0
#define DIDT_TD_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK                                                 0x00007FFFL
//DIDT_TD_EDC_TIMER_PERIOD
#define DIDT_TD_EDC_TIMER_PERIOD__EDC_TIMER_PERIOD__SHIFT                                                     0x0
#define DIDT_TD_EDC_TIMER_PERIOD__EDC_TIMER_PERIOD_MASK                                                       0x00003FFFL
//DIDT_TD_THROTTLE_CTRL
#define DIDT_TD_THROTTLE_CTRL__GC_EDC_STALL_EN__SHIFT                                                         0x0
#define DIDT_TD_THROTTLE_CTRL__PCC_STALL_EN__SHIFT                                                            0x1
#define DIDT_TD_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT                                                         0x2
#define DIDT_TD_THROTTLE_CTRL__GC_EDC_ONLY_MODE__SHIFT                                                        0x3
#define DIDT_TD_THROTTLE_CTRL__GC_EDC_STALL_EN_MASK                                                           0x00000001L
#define DIDT_TD_THROTTLE_CTRL__PCC_STALL_EN_MASK                                                              0x00000002L
#define DIDT_TD_THROTTLE_CTRL__PWRBRK_STALL_EN_MASK                                                           0x00000004L
#define DIDT_TD_THROTTLE_CTRL__GC_EDC_ONLY_MODE_MASK                                                          0x00000008L
//DIDT_TD_EDC_STALL_DELAY_1
#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD0__SHIFT                                                 0x0
#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD1__SHIFT                                                 0x6
#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD2__SHIFT                                                 0xc
#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD3__SHIFT                                                 0x12
#define DIDT_TD_EDC_STALL_DELAY_1__UNUSED__SHIFT                                                              0x18
#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD0_MASK                                                   0x0000003FL
#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD1_MASK                                                   0x00000FC0L
#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD2_MASK                                                   0x0003F000L
#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD3_MASK                                                   0x00FC0000L
#define DIDT_TD_EDC_STALL_DELAY_1__UNUSED_MASK                                                                0xFF000000L
//DIDT_TD_EDC_STALL_DELAY_2
#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD4__SHIFT                                                 0x0
#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD5__SHIFT                                                 0x6
#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD6__SHIFT                                                 0xc
#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD7__SHIFT                                                 0x12
#define DIDT_TD_EDC_STALL_DELAY_2__UNUSED__SHIFT                                                              0x18
#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD4_MASK                                                   0x0000003FL
#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD5_MASK                                                   0x00000FC0L
#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD6_MASK                                                   0x0003F000L
#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD7_MASK                                                   0x00FC0000L
#define DIDT_TD_EDC_STALL_DELAY_2__UNUSED_MASK                                                                0xFF000000L
//DIDT_TD_EDC_STALL_DELAY_3
#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD8__SHIFT                                                 0x0
#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD9__SHIFT                                                 0x6
#define DIDT_TD_EDC_STALL_DELAY_3__UNUSED__SHIFT                                                              0xc
#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD8_MASK                                                   0x0000003FL
#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD9_MASK                                                   0x00000FC0L
#define DIDT_TD_EDC_STALL_DELAY_3__UNUSED_MASK                                                                0xFFFFF000L
//DIDT_TD_EDC_STATUS
#define DIDT_TD_EDC_STATUS__EDC_FSM_STATE__SHIFT                                                              0x0
#define DIDT_TD_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT                                                         0x1
#define DIDT_TD_EDC_STATUS__EDC_FSM_STATE_MASK                                                                0x00000001L
#define DIDT_TD_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK                                                           0x0000000EL
//DIDT_TD_EDC_OVERFLOW
#define DIDT_TD_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT                                         0x0
#define DIDT_TD_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT                                      0x1
#define DIDT_TD_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK                                           0x00000001L
#define DIDT_TD_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK                                        0x0001FFFEL
//DIDT_TD_EDC_ROLLING_POWER_DELTA
#define DIDT_TD_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT                                       0x0
#define DIDT_TD_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK                                         0xFFFFFFFFL
//DIDT_TD_EDC_PCC_PERF_COUNTER
#define DIDT_TD_EDC_PCC_PERF_COUNTER__EDC_PCC_PERF_COUNTER__SHIFT                                             0x0
#define DIDT_TD_EDC_PCC_PERF_COUNTER__EDC_PCC_PERF_COUNTER_MASK                                               0xFFFFFFFFL
//DIDT_TCP_CTRL0
#define DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT                                                                   0x0
#define DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT                                                                   0x1
#define DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT                                                                  0x3
#define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT                                                           0x4
#define DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN__SHIFT                                                             0x5
#define DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT                                                            0x6
#define DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT                                                     0x7
#define DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT                                                        0x8
#define DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN__SHIFT                                                               0x18
#define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN__SHIFT                                                            0x19
#define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT                                                 0x1a
#define DIDT_TCP_CTRL0__DIDT_RLC_FORCE_STALL_EN__SHIFT                                                        0x1b
#define DIDT_TCP_CTRL0__DIDT_RLC_STALL_LEVEL_SEL__SHIFT                                                       0x1c
#define DIDT_TCP_CTRL0__DIDT_THROTTLE_MODE__SHIFT                                                             0x1d
#define DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK                                                                     0x00000001L
#define DIDT_TCP_CTRL0__PHASE_OFFSET_MASK                                                                     0x00000006L
#define DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK                                                                    0x00000008L
#define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK                                                             0x00000010L
#define DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN_MASK                                                               0x00000020L
#define DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN_MASK                                                              0x00000040L
#define DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK                                                       0x00000080L
#define DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK                                                          0x00FFFF00L
#define DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN_MASK                                                                 0x01000000L
#define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN_MASK                                                              0x02000000L
#define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK                                                   0x04000000L
#define DIDT_TCP_CTRL0__DIDT_RLC_FORCE_STALL_EN_MASK                                                          0x08000000L
#define DIDT_TCP_CTRL0__DIDT_RLC_STALL_LEVEL_SEL_MASK                                                         0x10000000L
#define DIDT_TCP_CTRL0__DIDT_THROTTLE_MODE_MASK                                                               0x20000000L
//DIDT_TCP_CTRL1
#define DIDT_TCP_CTRL1__MIN_POWER__SHIFT                                                                      0x0
#define DIDT_TCP_CTRL1__MAX_POWER__SHIFT                                                                      0x10
#define DIDT_TCP_CTRL1__MIN_POWER_MASK                                                                        0x0000FFFFL
#define DIDT_TCP_CTRL1__MAX_POWER_MASK                                                                        0xFFFF0000L
//DIDT_TCP_CTRL2
#define DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT                                                                0x0
#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT                                                       0x10
#define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT                                                       0x1b
#define DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK                                                                  0x00003FFFL
#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK                                                         0x03FF0000L
#define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK                                                         0x78000000L
//DIDT_TCP_CTRL_OCP
#define DIDT_TCP_CTRL_OCP__OCP_MAX_POWER__SHIFT                                                               0x0
#define DIDT_TCP_CTRL_OCP__OCP_MAX_POWER_MASK                                                                 0x0000FFFFL
//DIDT_TCP_STALL_CTRL
#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT                                                       0x0
#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT                                                       0x6
#define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT                                                0xc
#define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT                                                0x12
#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK                                                         0x0000003FL
#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK                                                         0x00000FC0L
#define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK                                                  0x0003F000L
#define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK                                                  0x00FC0000L
//DIDT_TCP_TUNING_CTRL
#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT                                                       0x0
#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT                                                       0xe
#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK                                                         0x00003FFFL
#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK                                                         0x0FFFC000L
//DIDT_TCP_STALL_AUTO_RELEASE_CTRL
#define DIDT_TCP_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT                                 0x0
#define DIDT_TCP_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK                                   0x00FFFFFFL
//DIDT_TCP_CTRL3
#define DIDT_TCP_CTRL3__GC_DIDT_ENABLE__SHIFT                                                                 0x0
#define DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT                                                        0x1
#define DIDT_TCP_CTRL3__THROTTLE_POLICY__SHIFT                                                                0x2
#define DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT                                                   0x4
#define DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT                                                        0x9
#define DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT                                                    0xe
#define DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT                                                          0x16
#define DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT                                                          0x17
#define DIDT_TCP_CTRL3__QUALIFY_STALL_EN__SHIFT                                                               0x18
#define DIDT_TCP_CTRL3__DIDT_STALL_SEL__SHIFT                                                                 0x19
#define DIDT_TCP_CTRL3__DIDT_FORCE_STALL__SHIFT                                                               0x1b
#define DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN__SHIFT                                                            0x1c
#define DIDT_TCP_CTRL3__GC_DIDT_ENABLE_MASK                                                                   0x00000001L
#define DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK                                                          0x00000002L
#define DIDT_TCP_CTRL3__THROTTLE_POLICY_MASK                                                                  0x0000000CL
#define DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK                                                     0x000001F0L
#define DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK                                                          0x00003E00L
#define DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK                                                      0x003FC000L
#define DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK                                                            0x00400000L
#define DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK                                                            0x00800000L
#define DIDT_TCP_CTRL3__QUALIFY_STALL_EN_MASK                                                                 0x01000000L
#define DIDT_TCP_CTRL3__DIDT_STALL_SEL_MASK                                                                   0x06000000L
#define DIDT_TCP_CTRL3__DIDT_FORCE_STALL_MASK                                                                 0x08000000L
#define DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN_MASK                                                              0x10000000L
//DIDT_TCP_STALL_PATTERN_1_2
#define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT                                               0x0
#define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT                                               0x10
#define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK                                                 0x00007FFFL
#define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK                                                 0x7FFF0000L
//DIDT_TCP_STALL_PATTERN_3_4
#define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT                                               0x0
#define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT                                               0x10
#define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK                                                 0x00007FFFL
#define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK                                                 0x7FFF0000L
//DIDT_TCP_STALL_PATTERN_5_6
#define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT                                               0x0
#define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT                                               0x10
#define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK                                                 0x00007FFFL
#define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK                                                 0x7FFF0000L
//DIDT_TCP_STALL_PATTERN_7
#define DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT                                                 0x0
#define DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK                                                   0x00007FFFL
//DIDT_TCP_MPD_SCALE_FACTOR
#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1__SHIFT                                              0x0
#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2__SHIFT                                              0x4
#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3__SHIFT                                              0x8
#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4__SHIFT                                              0xc
#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0__SHIFT                                                    0x10
#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1__SHIFT                                                    0x14
#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2__SHIFT                                                    0x18
#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3__SHIFT                                                    0x1c
#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1_MASK                                                0x0000000FL
#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2_MASK                                                0x000000F0L
#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3_MASK                                                0x00000F00L
#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4_MASK                                                0x0000F000L
#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0_MASK                                                      0x000F0000L
#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1_MASK                                                      0x00F00000L
#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2_MASK                                                      0x0F000000L
#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3_MASK                                                      0xF0000000L
//DIDT_TCP_STALL_RELEASE_CNTL0
#define DIDT_TCP_STALL_RELEASE_CNTL0__DIDT_STALL_RELEASE_CNTL_EN__SHIFT                                       0x0
#define DIDT_TCP_STALL_RELEASE_CNTL0__DIDT_STALL_CNTL_SEL__SHIFT                                              0x1
#define DIDT_TCP_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_HI__SHIFT                                            0x2
#define DIDT_TCP_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_LO__SHIFT                                            0xd
#define DIDT_TCP_STALL_RELEASE_CNTL0__DIDT_STALL_RELEASE_CNTL_EN_MASK                                         0x00000001L
#define DIDT_TCP_STALL_RELEASE_CNTL0__DIDT_STALL_CNTL_SEL_MASK                                                0x00000002L
#define DIDT_TCP_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_HI_MASK                                              0x00001FFCL
#define DIDT_TCP_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_LO_MASK                                              0x00FFE000L
//DIDT_TCP_STALL_RELEASE_CNTL1
#define DIDT_TCP_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI__SHIFT                                     0x0
#define DIDT_TCP_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI__SHIFT                                     0x5
#define DIDT_TCP_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO__SHIFT                                     0xa
#define DIDT_TCP_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO__SHIFT                                     0xf
#define DIDT_TCP_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI_MASK                                       0x0000001FL
#define DIDT_TCP_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI_MASK                                       0x000003E0L
#define DIDT_TCP_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO_MASK                                       0x00007C00L
#define DIDT_TCP_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO_MASK                                       0x000F8000L
//DIDT_TCP_STALL_RELEASE_CNTL_STATUS
#define DIDT_TCP_STALL_RELEASE_CNTL_STATUS__DIDT_STALL_RELEASE_CNTL_FSM_STATE__SHIFT                          0x0
#define DIDT_TCP_STALL_RELEASE_CNTL_STATUS__DIDT_STALL_RELEASE_CNTL_FSM_STATE_MASK                            0x00000003L
//DIDT_TCP_WEIGHT0_3
#define DIDT_TCP_WEIGHT0_3__WEIGHT0__SHIFT                                                                    0x0
#define DIDT_TCP_WEIGHT0_3__WEIGHT1__SHIFT                                                                    0x8
#define DIDT_TCP_WEIGHT0_3__WEIGHT2__SHIFT                                                                    0x10
#define DIDT_TCP_WEIGHT0_3__WEIGHT3__SHIFT                                                                    0x18
#define DIDT_TCP_WEIGHT0_3__WEIGHT0_MASK                                                                      0x000000FFL
#define DIDT_TCP_WEIGHT0_3__WEIGHT1_MASK                                                                      0x0000FF00L
#define DIDT_TCP_WEIGHT0_3__WEIGHT2_MASK                                                                      0x00FF0000L
#define DIDT_TCP_WEIGHT0_3__WEIGHT3_MASK                                                                      0xFF000000L
//DIDT_TCP_WEIGHT4_7
#define DIDT_TCP_WEIGHT4_7__WEIGHT4__SHIFT                                                                    0x0
#define DIDT_TCP_WEIGHT4_7__WEIGHT5__SHIFT                                                                    0x8
#define DIDT_TCP_WEIGHT4_7__WEIGHT6__SHIFT                                                                    0x10
#define DIDT_TCP_WEIGHT4_7__WEIGHT7__SHIFT                                                                    0x18
#define DIDT_TCP_WEIGHT4_7__WEIGHT4_MASK                                                                      0x000000FFL
#define DIDT_TCP_WEIGHT4_7__WEIGHT5_MASK                                                                      0x0000FF00L
#define DIDT_TCP_WEIGHT4_7__WEIGHT6_MASK                                                                      0x00FF0000L
#define DIDT_TCP_WEIGHT4_7__WEIGHT7_MASK                                                                      0xFF000000L
//DIDT_TCP_WEIGHT8_11
#define DIDT_TCP_WEIGHT8_11__WEIGHT8__SHIFT                                                                   0x0
#define DIDT_TCP_WEIGHT8_11__WEIGHT9__SHIFT                                                                   0x8
#define DIDT_TCP_WEIGHT8_11__WEIGHT10__SHIFT                                                                  0x10
#define DIDT_TCP_WEIGHT8_11__WEIGHT11__SHIFT                                                                  0x18
#define DIDT_TCP_WEIGHT8_11__WEIGHT8_MASK                                                                     0x000000FFL
#define DIDT_TCP_WEIGHT8_11__WEIGHT9_MASK                                                                     0x0000FF00L
#define DIDT_TCP_WEIGHT8_11__WEIGHT10_MASK                                                                    0x00FF0000L
#define DIDT_TCP_WEIGHT8_11__WEIGHT11_MASK                                                                    0xFF000000L
//DIDT_TCP_EDC_CTRL
#define DIDT_TCP_EDC_CTRL__EDC_EN__SHIFT                                                                      0x0
#define DIDT_TCP_EDC_CTRL__EDC_SW_RST__SHIFT                                                                  0x1
#define DIDT_TCP_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT                                                         0x2
#define DIDT_TCP_EDC_CTRL__EDC_FORCE_STALL__SHIFT                                                             0x3
#define DIDT_TCP_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT                                                 0x4
#define DIDT_TCP_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT                                                  0x9
#define DIDT_TCP_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT                                                    0x11
#define DIDT_TCP_EDC_CTRL__GC_EDC_EN__SHIFT                                                                   0x12
#define DIDT_TCP_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT                                                         0x13
#define DIDT_TCP_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT                                                        0x15
#define DIDT_TCP_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT                                                        0x16
#define DIDT_TCP_EDC_CTRL__EDC_LEVEL_MODE_SEL__SHIFT                                                          0x17
#define DIDT_TCP_EDC_CTRL__EDC_LEVEL_COMB_ADAPT_MODE_EN__SHIFT                                                0x18
#define DIDT_TCP_EDC_CTRL__EDC_EN_MASK                                                                        0x00000001L
#define DIDT_TCP_EDC_CTRL__EDC_SW_RST_MASK                                                                    0x00000002L
#define DIDT_TCP_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK                                                           0x00000004L
#define DIDT_TCP_EDC_CTRL__EDC_FORCE_STALL_MASK                                                               0x00000008L
#define DIDT_TCP_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK                                                   0x000001F0L
#define DIDT_TCP_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK                                                    0x0001FE00L
#define DIDT_TCP_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK                                                      0x00020000L
#define DIDT_TCP_EDC_CTRL__GC_EDC_EN_MASK                                                                     0x00040000L
#define DIDT_TCP_EDC_CTRL__GC_EDC_STALL_POLICY_MASK                                                           0x00180000L
#define DIDT_TCP_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK                                                          0x00200000L
#define DIDT_TCP_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK                                                          0x00400000L
#define DIDT_TCP_EDC_CTRL__EDC_LEVEL_MODE_SEL_MASK                                                            0x00800000L
#define DIDT_TCP_EDC_CTRL__EDC_LEVEL_COMB_ADAPT_MODE_EN_MASK                                                  0x01000000L
//DIDT_TCP_EDC_THRESHOLD
#define DIDT_TCP_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT                                                          0x0
#define DIDT_TCP_EDC_THRESHOLD__EDC_THRESHOLD_MASK                                                            0xFFFFFFFFL
//DIDT_TCP_EDC_STALL_PATTERN_1_2
#define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT                                            0x0
#define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT                                            0x10
#define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK                                              0x00007FFFL
#define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK                                              0x7FFF0000L
//DIDT_TCP_EDC_STALL_PATTERN_3_4
#define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT                                            0x0
#define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT                                            0x10
#define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK                                              0x00007FFFL
#define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK                                              0x7FFF0000L
//DIDT_TCP_EDC_STALL_PATTERN_5_6
#define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT                                            0x0
#define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT                                            0x10
#define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK                                              0x00007FFFL
#define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK                                              0x7FFF0000L
//DIDT_TCP_EDC_STALL_PATTERN_7
#define DIDT_TCP_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT                                              0x0
#define DIDT_TCP_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK                                                0x00007FFFL
//DIDT_TCP_EDC_TIMER_PERIOD
#define DIDT_TCP_EDC_TIMER_PERIOD__EDC_TIMER_PERIOD__SHIFT                                                    0x0
#define DIDT_TCP_EDC_TIMER_PERIOD__EDC_TIMER_PERIOD_MASK                                                      0x00003FFFL
//DIDT_TCP_THROTTLE_CTRL
#define DIDT_TCP_THROTTLE_CTRL__GC_EDC_STALL_EN__SHIFT                                                        0x0
#define DIDT_TCP_THROTTLE_CTRL__PCC_STALL_EN__SHIFT                                                           0x1
#define DIDT_TCP_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT                                                        0x2
#define DIDT_TCP_THROTTLE_CTRL__GC_EDC_ONLY_MODE__SHIFT                                                       0x3
#define DIDT_TCP_THROTTLE_CTRL__GC_EDC_STALL_EN_MASK                                                          0x00000001L
#define DIDT_TCP_THROTTLE_CTRL__PCC_STALL_EN_MASK                                                             0x00000002L
#define DIDT_TCP_THROTTLE_CTRL__PWRBRK_STALL_EN_MASK                                                          0x00000004L
#define DIDT_TCP_THROTTLE_CTRL__GC_EDC_ONLY_MODE_MASK                                                         0x00000008L
//DIDT_TCP_EDC_STALL_DELAY_1
#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP0__SHIFT                                               0x0
#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP1__SHIFT                                               0x6
#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP2__SHIFT                                               0xc
#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP3__SHIFT                                               0x12
#define DIDT_TCP_EDC_STALL_DELAY_1__UNUSED__SHIFT                                                             0x18
#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP0_MASK                                                 0x0000003FL
#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP1_MASK                                                 0x00000FC0L
#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP2_MASK                                                 0x0003F000L
#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP3_MASK                                                 0x00FC0000L
#define DIDT_TCP_EDC_STALL_DELAY_1__UNUSED_MASK                                                               0xFF000000L
//DIDT_TCP_EDC_STALL_DELAY_2
#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP4__SHIFT                                               0x0
#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP5__SHIFT                                               0x6
#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP6__SHIFT                                               0xc
#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP7__SHIFT                                               0x12
#define DIDT_TCP_EDC_STALL_DELAY_2__UNUSED__SHIFT                                                             0x18
#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP4_MASK                                                 0x0000003FL
#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP5_MASK                                                 0x00000FC0L
#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP6_MASK                                                 0x0003F000L
#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP7_MASK                                                 0x00FC0000L
#define DIDT_TCP_EDC_STALL_DELAY_2__UNUSED_MASK                                                               0xFF000000L
//DIDT_TCP_EDC_STALL_DELAY_3
#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP8__SHIFT                                               0x0
#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP9__SHIFT                                               0x6
#define DIDT_TCP_EDC_STALL_DELAY_3__UNUSED__SHIFT                                                             0xc
#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP8_MASK                                                 0x0000003FL
#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP9_MASK                                                 0x00000FC0L
#define DIDT_TCP_EDC_STALL_DELAY_3__UNUSED_MASK                                                               0xFFFFF000L
//DIDT_TCP_EDC_STATUS
#define DIDT_TCP_EDC_STATUS__EDC_FSM_STATE__SHIFT                                                             0x0
#define DIDT_TCP_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT                                                        0x1
#define DIDT_TCP_EDC_STATUS__EDC_FSM_STATE_MASK                                                               0x00000001L
#define DIDT_TCP_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK                                                          0x0000000EL
//DIDT_TCP_EDC_OVERFLOW
#define DIDT_TCP_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT                                        0x0
#define DIDT_TCP_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT                                     0x1
#define DIDT_TCP_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK                                          0x00000001L
#define DIDT_TCP_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK                                       0x0001FFFEL
//DIDT_TCP_EDC_ROLLING_POWER_DELTA
#define DIDT_TCP_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT                                      0x0
#define DIDT_TCP_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK                                        0xFFFFFFFFL
//DIDT_TCP_EDC_PCC_PERF_COUNTER
#define DIDT_TCP_EDC_PCC_PERF_COUNTER__EDC_PCC_PERF_COUNTER__SHIFT                                            0x0
#define DIDT_TCP_EDC_PCC_PERF_COUNTER__EDC_PCC_PERF_COUNTER_MASK                                              0xFFFFFFFFL
//DIDT_SQ_STALL_EVENT_COUNTER
#define DIDT_SQ_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT                                          0x0
#define DIDT_SQ_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK                                            0xFFFFFFFFL
//DIDT_DB_STALL_EVENT_COUNTER
#define DIDT_DB_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT                                          0x0
#define DIDT_DB_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK                                            0xFFFFFFFFL
//DIDT_TD_STALL_EVENT_COUNTER
#define DIDT_TD_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT                                          0x0
#define DIDT_TD_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK                                            0xFFFFFFFFL
//DIDT_TCP_STALL_EVENT_COUNTER
#define DIDT_TCP_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT                                         0x0
#define DIDT_TCP_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK                                           0xFFFFFFFFL


#endif