drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_3_0_3_offset.h

   1 #ifndef _dpcs_3_0_3_OFFSET_HEADER
   2 #define _dpcs_3_0_3_OFFSET_HEADER
   3
   4
   5
   6 // addressBlock: dpcssys_dpcs0_dpcstx0_dispdec
   7 // base address: 0x0
   8 #define mmDPCSTX0_DPCSTX_TX_CLOCK_CNTL                                                                 0x2928
   9 #define mmDPCSTX0_DPCSTX_TX_CLOCK_CNTL_BASE_IDX                                                        2
  10 #define mmDPCSTX0_DPCSTX_TX_CNTL                                                                       0x2929
  11 #define mmDPCSTX0_DPCSTX_TX_CNTL_BASE_IDX                                                              2
  12 #define mmDPCSTX0_DPCSTX_CBUS_CNTL                                                                     0x292a
  13 #define mmDPCSTX0_DPCSTX_CBUS_CNTL_BASE_IDX                                                            2
  14 #define mmDPCSTX0_DPCSTX_INTERRUPT_CNTL                                                                0x292b
  15 #define mmDPCSTX0_DPCSTX_INTERRUPT_CNTL_BASE_IDX                                                       2
  16 #define mmDPCSTX0_DPCSTX_PLL_UPDATE_ADDR                                                               0x292c
  17 #define mmDPCSTX0_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX                                                      2
  18 #define mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA                                                               0x292d
  19 #define mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                      2
  20
  21
  22 // addressBlock: dpcssys_dpcs0_rdpcstx0_dispdec
  23 // base address: 0x0
  24 #define mmRDPCSTX0_RDPCSTX_CNTL                                                                        0x2930
  25 #define mmRDPCSTX0_RDPCSTX_CNTL_BASE_IDX                                                               2
  26 #define mmRDPCSTX0_RDPCSTX_CLOCK_CNTL                                                                  0x2931
  27 #define mmRDPCSTX0_RDPCSTX_CLOCK_CNTL_BASE_IDX                                                         2
  28 #define mmRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL                                                           0x2932
  29 #define mmRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX                                                  2
  30 #define mmRDPCSTX0_RDPCSTX_PLL_UPDATE_DATA                                                             0x2933
  31 #define mmRDPCSTX0_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                    2
  32 #define mmRDPCSTX0_RDPCS_TX_CR_ADDR                                                                    0x2934
  33 #define mmRDPCSTX0_RDPCS_TX_CR_ADDR_BASE_IDX                                                           2
  34 #define mmRDPCSTX0_RDPCS_TX_CR_DATA                                                                    0x2935
  35 #define mmRDPCSTX0_RDPCS_TX_CR_DATA_BASE_IDX                                                           2
  36 #define mmRDPCSTX0_RDPCS_TX_SRAM_CNTL                                                                  0x2936
  37 #define mmRDPCSTX0_RDPCS_TX_SRAM_CNTL_BASE_IDX                                                         2
  38 #define mmRDPCSTX0_RDPCSTX_SCRATCH                                                                     0x2937
  39 #define mmRDPCSTX0_RDPCSTX_SCRATCH_BASE_IDX                                                            2
  40 #define mmRDPCSTX0_RDPCSTX_SPARE                                                                       0x2938
  41 #define mmRDPCSTX0_RDPCSTX_SPARE_BASE_IDX                                                              2
  42 #define mmRDPCSTX0_RDPCSTX_CNTL2                                                                       0x2939
  43 #define mmRDPCSTX0_RDPCSTX_CNTL2_BASE_IDX                                                              2
  44 #define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG                                                    0x293c
  45 #define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX                                           2
  46 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL0                                                                   0x2940
  47 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL0_BASE_IDX                                                          2
  48 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL1                                                                   0x2941
  49 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL1_BASE_IDX                                                          2
  50 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL2                                                                   0x2942
  51 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL2_BASE_IDX                                                          2
  52 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL3                                                                   0x2943
  53 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL3_BASE_IDX                                                          2
  54 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL4                                                                   0x2944
  55 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL4_BASE_IDX                                                          2
  56 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL5                                                                   0x2945
  57 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL5_BASE_IDX                                                          2
  58 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL6                                                                   0x2946
  59 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL6_BASE_IDX                                                          2
  60 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL7                                                                   0x2947
  61 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL7_BASE_IDX                                                          2
  62 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL8                                                                   0x2948
  63 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL8_BASE_IDX                                                          2
  64 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL9                                                                   0x2949
  65 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL9_BASE_IDX                                                          2
  66 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL10                                                                  0x294a
  67 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL10_BASE_IDX                                                         2
  68 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL11                                                                  0x294b
  69 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL11_BASE_IDX                                                         2
  70 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL12                                                                  0x294c
  71 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL12_BASE_IDX                                                         2
  72 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL13                                                                  0x294d
  73 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL13_BASE_IDX                                                         2
  74 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL14                                                                  0x294e
  75 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL14_BASE_IDX                                                         2
  76 #define mmRDPCSTX0_RDPCSTX_PHY_FUSE0                                                                   0x294f
  77 #define mmRDPCSTX0_RDPCSTX_PHY_FUSE0_BASE_IDX                                                          2
  78 #define mmRDPCSTX0_RDPCSTX_PHY_FUSE1                                                                   0x2950
  79 #define mmRDPCSTX0_RDPCSTX_PHY_FUSE1_BASE_IDX                                                          2
  80 #define mmRDPCSTX0_RDPCSTX_PHY_FUSE2                                                                   0x2951
  81 #define mmRDPCSTX0_RDPCSTX_PHY_FUSE2_BASE_IDX                                                          2
  82 #define mmRDPCSTX0_RDPCSTX_PHY_FUSE3                                                                   0x2952
  83 #define mmRDPCSTX0_RDPCSTX_PHY_FUSE3_BASE_IDX                                                          2
  84 #define mmRDPCSTX0_RDPCSTX_PHY_RX_LD_VAL                                                               0x2953
  85 #define mmRDPCSTX0_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX                                                      2
  86 #define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3                                                        0x2954
  87 #define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX                                               2
  88 #define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6                                                        0x2955
  89 #define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX                                               2
  90 #define mmRDPCSTX0_RDPCSTX_DPALT_CONTROL_REG                                                           0x2956
  91 #define mmRDPCSTX0_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX                                                  2
  92
  93
  94 // addressBlock: dpcssys_dpcssys_cr0_dispdec
  95 // base address: 0x0
  96 #define mmDPCSSYS_CR0_DPCSSYS_CR_ADDR                                                                  0x2934
  97 #define mmDPCSSYS_CR0_DPCSSYS_CR_ADDR_BASE_IDX                                                         2
  98 #define mmDPCSSYS_CR0_DPCSSYS_CR_DATA                                                                  0x2935
  99 #define mmDPCSSYS_CR0_DPCSSYS_CR_DATA_BASE_IDX                                                         2
 100
 101
 102 // addressBlock: dpcssys_dpcs0_dpcstx1_dispdec
 103 // base address: 0x360
 104 #define mmDPCSTX1_DPCSTX_TX_CLOCK_CNTL                                                                 0x2a00
 105 #define mmDPCSTX1_DPCSTX_TX_CLOCK_CNTL_BASE_IDX                                                        2
 106 #define mmDPCSTX1_DPCSTX_TX_CNTL                                                                       0x2a01
 107 #define mmDPCSTX1_DPCSTX_TX_CNTL_BASE_IDX                                                              2
 108 #define mmDPCSTX1_DPCSTX_CBUS_CNTL                                                                     0x2a02
 109 #define mmDPCSTX1_DPCSTX_CBUS_CNTL_BASE_IDX                                                            2
 110 #define mmDPCSTX1_DPCSTX_INTERRUPT_CNTL                                                                0x2a03
 111 #define mmDPCSTX1_DPCSTX_INTERRUPT_CNTL_BASE_IDX                                                       2
 112 #define mmDPCSTX1_DPCSTX_PLL_UPDATE_ADDR                                                               0x2a04
 113 #define mmDPCSTX1_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX                                                      2
 114 #define mmDPCSTX1_DPCSTX_PLL_UPDATE_DATA                                                               0x2a05
 115 #define mmDPCSTX1_DPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                      2
 116
 117
 118 // addressBlock: dpcssys_dpcs0_rdpcstx1_dispdec
 119 // base address: 0x360
 120 #define mmRDPCSTX1_RDPCSTX_CNTL                                                                        0x2a08
 121 #define mmRDPCSTX1_RDPCSTX_CNTL_BASE_IDX                                                               2
 122 #define mmRDPCSTX1_RDPCSTX_CLOCK_CNTL                                                                  0x2a09
 123 #define mmRDPCSTX1_RDPCSTX_CLOCK_CNTL_BASE_IDX                                                         2
 124 #define mmRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL                                                           0x2a0a
 125 #define mmRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX                                                  2
 126 #define mmRDPCSTX1_RDPCSTX_PLL_UPDATE_DATA                                                             0x2a0b
 127 #define mmRDPCSTX1_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                    2
 128 #define mmRDPCSTX1_RDPCS_TX_CR_ADDR                                                                    0x2a0c
 129 #define mmRDPCSTX1_RDPCS_TX_CR_ADDR_BASE_IDX                                                           2
 130 #define mmRDPCSTX1_RDPCS_TX_CR_DATA                                                                    0x2a0d
 131 #define mmRDPCSTX1_RDPCS_TX_CR_DATA_BASE_IDX                                                           2
 132 #define mmRDPCSTX1_RDPCS_TX_SRAM_CNTL                                                                  0x2a0e
 133 #define mmRDPCSTX1_RDPCS_TX_SRAM_CNTL_BASE_IDX                                                         2
 134 #define mmRDPCSTX1_RDPCSTX_SCRATCH                                                                     0x2a0f
 135 #define mmRDPCSTX1_RDPCSTX_SCRATCH_BASE_IDX                                                            2
 136 #define mmRDPCSTX1_RDPCSTX_SPARE                                                                       0x2a10
 137 #define mmRDPCSTX1_RDPCSTX_SPARE_BASE_IDX                                                              2
 138 #define mmRDPCSTX1_RDPCSTX_CNTL2                                                                       0x2a11
 139 #define mmRDPCSTX1_RDPCSTX_CNTL2_BASE_IDX                                                              2
 140 #define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG                                                    0x2a14
 141 #define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX                                           2
 142 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL0                                                                   0x2a18
 143 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL0_BASE_IDX                                                          2
 144 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL1                                                                   0x2a19
 145 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL1_BASE_IDX                                                          2
 146 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL2                                                                   0x2a1a
 147 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL2_BASE_IDX                                                          2
 148 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL3                                                                   0x2a1b
 149 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL3_BASE_IDX                                                          2
 150 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL4                                                                   0x2a1c
 151 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL4_BASE_IDX                                                          2
 152 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL5                                                                   0x2a1d
 153 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL5_BASE_IDX                                                          2
 154 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL6                                                                   0x2a1e
 155 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL6_BASE_IDX                                                          2
 156 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL7                                                                   0x2a1f
 157 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL7_BASE_IDX                                                          2
 158 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL8                                                                   0x2a20
 159 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL8_BASE_IDX                                                          2
 160 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL9                                                                   0x2a21
 161 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL9_BASE_IDX                                                          2
 162 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL10                                                                  0x2a22
 163 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL10_BASE_IDX                                                         2
 164 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL11                                                                  0x2a23
 165 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL11_BASE_IDX                                                         2
 166 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL12                                                                  0x2a24
 167 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL12_BASE_IDX                                                         2
 168 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL13                                                                  0x2a25
 169 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL13_BASE_IDX                                                         2
 170 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL14                                                                  0x2a26
 171 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL14_BASE_IDX                                                         2
 172 #define mmRDPCSTX1_RDPCSTX_PHY_FUSE0                                                                   0x2a27
 173 #define mmRDPCSTX1_RDPCSTX_PHY_FUSE0_BASE_IDX                                                          2
 174 #define mmRDPCSTX1_RDPCSTX_PHY_FUSE1                                                                   0x2a28
 175 #define mmRDPCSTX1_RDPCSTX_PHY_FUSE1_BASE_IDX                                                          2
 176 #define mmRDPCSTX1_RDPCSTX_PHY_FUSE2                                                                   0x2a29
 177 #define mmRDPCSTX1_RDPCSTX_PHY_FUSE2_BASE_IDX                                                          2
 178 #define mmRDPCSTX1_RDPCSTX_PHY_FUSE3                                                                   0x2a2a
 179 #define mmRDPCSTX1_RDPCSTX_PHY_FUSE3_BASE_IDX                                                          2
 180 #define mmRDPCSTX1_RDPCSTX_PHY_RX_LD_VAL                                                               0x2a2b
 181 #define mmRDPCSTX1_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX                                                      2
 182 #define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3                                                        0x2a2c
 183 #define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX                                               2
 184 #define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6                                                        0x2a2d
 185 #define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX                                               2
 186 #define mmRDPCSTX1_RDPCSTX_DPALT_CONTROL_REG                                                           0x2a2e
 187 #define mmRDPCSTX1_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX                                                  2
 188
 189
 190 // addressBlock: dpcssys_dpcssys_cr1_dispdec
 191 // base address: 0x360
 192 #define mmDPCSSYS_CR1_DPCSSYS_CR_ADDR                                                                  0x2a0c
 193 #define mmDPCSSYS_CR1_DPCSSYS_CR_ADDR_BASE_IDX                                                         2
 194 #define mmDPCSSYS_CR1_DPCSSYS_CR_DATA                                                                  0x2a0d
 195 #define mmDPCSSYS_CR1_DPCSSYS_CR_DATA_BASE_IDX                                                         2
 196
 197 #endif