drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "mod_info_packet.h"
  27 #include "core_types.h"
  28 #include "dc_types.h"
  29 #include "mod_shared.h"
  30 #include "mod_freesync.h"
  31 #include "dc.h"
  32
  33 enum vsc_packet_revision {
  34         vsc_packet_undefined = 0,
  35         //01h = VSC SDP supports only 3D stereo.
  36         vsc_packet_rev1 = 1,
  37         //02h = 3D stereo + PSR.
  38         vsc_packet_rev2 = 2,
  39         //03h = 3D stereo + PSR2.
  40         vsc_packet_rev3 = 3,
  41         //04h = 3D stereo + PSR/PSR2 + Y-coordinate.
  42         vsc_packet_rev4 = 4,
  43         //05h = 3D stereo + PSR/PSR2 + Y-coordinate + Pixel Encoding/Colorimetry Format
  44         vsc_packet_rev5 = 5,
  45 };
  46
  47 #define HDMI_INFOFRAME_TYPE_VENDOR 0x81
  48 #define HF_VSIF_VERSION 1
  49
  50 // VTEM Byte Offset
  51 #define VTEM_PB0                0
  52 #define VTEM_PB1                1
  53 #define VTEM_PB2                2
  54 #define VTEM_PB3                3
  55 #define VTEM_PB4                4
  56 #define VTEM_PB5                5
  57 #define VTEM_PB6                6
  58
  59 #define VTEM_MD0                7
  60 #define VTEM_MD1                8
  61 #define VTEM_MD2                9
  62 #define VTEM_MD3                10
  63
  64
  65 // VTEM Byte Masks
  66 //PB0
  67 #define MASK_VTEM_PB0__RESERVED0  0x01
  68 #define MASK_VTEM_PB0__SYNC       0x02
  69 #define MASK_VTEM_PB0__VFR        0x04
  70 #define MASK_VTEM_PB0__AFR        0x08
  71 #define MASK_VTEM_PB0__DS_TYPE    0x30
  72         //0: Periodic pseudo-static EM Data Set
  73         //1: Periodic dynamic EM Data Set
  74         //2: Unique EM Data Set
  75         //3: Reserved
  76 #define MASK_VTEM_PB0__END        0x40
  77 #define MASK_VTEM_PB0__NEW        0x80
  78
  79 //PB1
  80 #define MASK_VTEM_PB1__RESERVED1 0xFF
  81
  82 //PB2
  83 #define MASK_VTEM_PB2__ORGANIZATION_ID 0xFF
  84         //0: This is a Vendor Specific EM Data Set
  85         //1: This EM Data Set is defined by This Specification (HDMI 2.1 r102.clean)
  86         //2: This EM Data Set is defined by CTA-861-G
  87         //3: This EM Data Set is defined by VESA
  88 //PB3
  89 #define MASK_VTEM_PB3__DATA_SET_TAG_MSB    0xFF
  90 //PB4
  91 #define MASK_VTEM_PB4__DATA_SET_TAG_LSB    0xFF
  92 //PB5
  93 #define MASK_VTEM_PB5__DATA_SET_LENGTH_MSB 0xFF
  94 //PB6
  95 #define MASK_VTEM_PB6__DATA_SET_LENGTH_LSB 0xFF
  96
  97
  98
  99 //PB7-27 (20 bytes):
 100 //PB7 = MD0
 101 #define MASK_VTEM_MD0__VRR_EN         0x01
 102 #define MASK_VTEM_MD0__M_CONST        0x02
 103 #define MASK_VTEM_MD0__RESERVED2      0x0C
 104 #define MASK_VTEM_MD0__FVA_FACTOR_M1  0xF0
 105
 106 //MD1
 107 #define MASK_VTEM_MD1__BASE_VFRONT    0xFF
 108
 109 //MD2
 110 #define MASK_VTEM_MD2__BASE_REFRESH_RATE_98  0x03
 111 #define MASK_VTEM_MD2__RB                    0x04
 112 #define MASK_VTEM_MD2__RESERVED3             0xF8
 113
 114 //MD3
 115 #define MASK_VTEM_MD3__BASE_REFRESH_RATE_07  0xFF
 116
 117 enum ColorimetryRGBDP {
 118         ColorimetryRGB_DP_sRGB               = 0,
 119         ColorimetryRGB_DP_AdobeRGB           = 3,
 120         ColorimetryRGB_DP_P3                 = 4,
 121         ColorimetryRGB_DP_CustomColorProfile = 5,
 122         ColorimetryRGB_DP_ITU_R_BT2020RGB    = 6,
 123 };
 124 enum ColorimetryYCCDP {
 125         ColorimetryYCC_DP_ITU601        = 0,
 126         ColorimetryYCC_DP_ITU709        = 1,
 127         ColorimetryYCC_DP_AdobeYCC      = 5,
 128         ColorimetryYCC_DP_ITU2020YCC    = 6,
 129         ColorimetryYCC_DP_ITU2020YCbCr  = 7,
 130 };
 131
 132 void mod_build_vsc_infopacket(const struct dc_stream_state *stream,
 133                 struct dc_info_packet *info_packet,
 134                 bool *use_vsc_sdp_for_colorimetry)
 135 {
 136         unsigned int vsc_packet_revision = vsc_packet_undefined;
 137         unsigned int i;
 138         unsigned int pixelEncoding = 0;
 139         unsigned int colorimetryFormat = 0;
 140         bool stereo3dSupport = false;
 141
 142         /* Initialize first, later if infopacket is valid determine if VSC SDP
 143          * should be used to signal colorimetry format and pixel encoding.
 144          */
 145         *use_vsc_sdp_for_colorimetry = false;
 146
 147         if (stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE && stream->view_format != VIEW_3D_FORMAT_NONE) {
 148                 vsc_packet_revision = vsc_packet_rev1;
 149                 stereo3dSupport = true;
 150         }
 151
 152         /*VSC packet set to 2 when DP revision >= 1.2*/
 153         if (stream->psr_version != 0)
 154                 vsc_packet_revision = vsc_packet_rev2;
 155
 156         /* Update to revision 5 for extended colorimetry support for DPCD 1.4+ */
 157         if (stream->link->dpcd_caps.dpcd_rev.raw >= 0x14 &&
 158                         stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED)
 159                 vsc_packet_revision = vsc_packet_rev5;
 160
 161         /* VSC packet not needed based on the features
 162          * supported by this DP display
 163          */
 164         if (vsc_packet_revision == vsc_packet_undefined)
 165                 return;
 166
 167         if (vsc_packet_revision == vsc_packet_rev2) {
 168                 /* Secondary-data Packet ID = 0*/
 169                 info_packet->hb0 = 0x00;
 170                 /* 07h - Packet Type Value indicating Video
 171                  * Stream Configuration packet
 172                  */
 173                 info_packet->hb1 = 0x07;
 174                 /* 02h = VSC SDP supporting 3D stereo and PSR
 175                  * (applies to eDP v1.3 or higher).
 176                  */
 177                 info_packet->hb2 = 0x02;
 178                 /* 08h = VSC packet supporting 3D stereo + PSR
 179                  * (HB2 = 02h).
 180                  */
 181                 info_packet->hb3 = 0x08;
 182
 183                 for (i = 0; i < 28; i++)
 184                         info_packet->sb[i] = 0;
 185
 186                 info_packet->valid = true;
 187         }
 188
 189         if (vsc_packet_revision == vsc_packet_rev1) {
 190
 191                 info_packet->hb0 = 0x00;        // Secondary-data Packet ID = 0
 192                 info_packet->hb1 = 0x07;        // 07h = Packet Type Value indicating Video Stream Configuration packet
 193                 info_packet->hb2 = 0x01;        // 01h = Revision number. VSC SDP supporting 3D stereo only
 194                 info_packet->hb3 = 0x01;        // 01h = VSC SDP supporting 3D stereo only (HB2 = 01h).
 195
 196                 info_packet->valid = true;
 197         }
 198
 199         if (stereo3dSupport) {
 200                 /* ==============================================================================================================|
 201                  * A. STEREO 3D
 202                  * ==============================================================================================================|
 203                  * VSC Payload (1 byte) From DP1.2 spec
 204                  *
 205                  * Bits 3:0 (Stereo Interface Method Code)  |  Bits 7:4 (Stereo Interface Method Specific Parameter)
 206                  * -----------------------------------------------------------------------------------------------------
 207                  * 0 = Non Stereo Video                     |  Must be set to 0x0
 208                  * -----------------------------------------------------------------------------------------------------
 209                  * 1 = Frame/Field Sequential               |  0x0: L + R view indication based on MISC1 bit 2:1
 210                  *                                          |  0x1: Right when Stereo Signal = 1
 211                  *                                          |  0x2: Left when Stereo Signal = 1
 212                  *                                          |  (others reserved)
 213                  * -----------------------------------------------------------------------------------------------------
 214                  * 2 = Stacked Frame                        |  0x0: Left view is on top and right view on bottom
 215                  *                                          |  (others reserved)
 216                  * -----------------------------------------------------------------------------------------------------
 217                  * 3 = Pixel Interleaved                    |  0x0: horiz interleaved, right view pixels on even lines
 218                  *                                          |  0x1: horiz interleaved, right view pixels on odd lines
 219                  *                                          |  0x2: checker board, start with left view pixel
 220                  *                                          |  0x3: vertical interleaved, start with left view pixels
 221                  *                                          |  0x4: vertical interleaved, start with right view pixels
 222                  *                                          |  (others reserved)
 223                  * -----------------------------------------------------------------------------------------------------
 224                  * 4 = Side-by-side                         |  0x0: left half represents left eye view
 225                  *                                          |  0x1: left half represents right eye view
 226                  */
 227                 switch (stream->timing.timing_3d_format) {
 228                 case TIMING_3D_FORMAT_HW_FRAME_PACKING:
 229                 case TIMING_3D_FORMAT_SW_FRAME_PACKING:
 230                 case TIMING_3D_FORMAT_TOP_AND_BOTTOM:
 231                 case TIMING_3D_FORMAT_TB_SW_PACKED:
 232                         info_packet->sb[0] = 0x02; // Stacked Frame, Left view is on top and right view on bottom.
 233                         break;
 234                 case TIMING_3D_FORMAT_DP_HDMI_INBAND_FA:
 235                 case TIMING_3D_FORMAT_INBAND_FA:
 236                         info_packet->sb[0] = 0x01; // Frame/Field Sequential, L + R view indication based on MISC1 bit 2:1
 237                         break;
 238                 case TIMING_3D_FORMAT_SIDE_BY_SIDE:
 239                 case TIMING_3D_FORMAT_SBS_SW_PACKED:
 240                         info_packet->sb[0] = 0x04; // Side-by-side
 241                         break;
 242                 default:
 243                         info_packet->sb[0] = 0x00; // No Stereo Video, Shall be cleared to 0x0.
 244                         break;
 245                 }
 246
 247         }
 248
 249         /* 05h = VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/Colorimetry Format indication.
 250          *   Added in DP1.3, a DP Source device is allowed to indicate the pixel encoding/colorimetry
 251          *   format to the DP Sink device with VSC SDP only when the DP Sink device supports it
 252          *   (i.e., VSC_SDP_EXTENSION_FOR_COLORIMETRY_SUPPORTED bit in the DPRX_FEATURE_ENUMERATION_LIST
 253          *   register (DPCD Address 02210h, bit 3) is set to 1).
 254          *   (Requires VSC_SDP_EXTENSION_FOR_COLORIMETRY_SUPPORTED bit set to 1 in DPCD 02210h. This
 255          *   DPCD register is exposed in the new Extended Receiver Capability field for DPCD Rev. 1.4
 256          *   (and higher). When MISC1. bit 6. is Set to 1, a Source device uses a VSC SDP to indicate
 257          *   the Pixel Encoding/Colorimetry Format and that a Sink device must ignore MISC1, bit 7, and
 258          *   MISC0, bits 7:1 (MISC1, bit 7. and MISC0, bits 7:1 become "don't care").)
 259          */
 260         if (vsc_packet_revision == vsc_packet_rev5) {
 261                 /* Secondary-data Packet ID = 0 */
 262                 info_packet->hb0 = 0x00;
 263                 /* 07h - Packet Type Value indicating Video Stream Configuration packet */
 264                 info_packet->hb1 = 0x07;
 265                 /* 05h = VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/Colorimetry Format indication. */
 266                 info_packet->hb2 = 0x05;
 267                 /* 13h = VSC SDP supporting 3D stereo, + PSR2, + Pixel Encoding/Colorimetry Format indication (HB2 = 05h). */
 268                 info_packet->hb3 = 0x13;
 269
 270                 info_packet->valid = true;
 271
 272                 /* If we are using VSC SDP revision 05h, use this to signal for
 273                  * colorimetry format and pixel encoding. HW should later be
 274                  * programmed to set MSA MISC1 bit 6 to indicate ignore
 275                  * colorimetry format and pixel encoding in the MSA.
 276                  */
 277                 *use_vsc_sdp_for_colorimetry = true;
 278
 279                 /* Set VSC SDP fields for pixel encoding and colorimetry format from DP 1.3 specs
 280                  * Data Bytes DB 18~16
 281                  * Bits 3:0 (Colorimetry Format)        |  Bits 7:4 (Pixel Encoding)
 282                  * ----------------------------------------------------------------------------------------------------
 283                  * 0x0 = sRGB                           |  0 = RGB
 284                  * 0x1 = RGB Wide Gamut Fixed Point
 285                  * 0x2 = RGB Wide Gamut Floating Point
 286                  * 0x3 = AdobeRGB
 287                  * 0x4 = DCI-P3
 288                  * 0x5 = CustomColorProfile
 289                  * (others reserved)
 290                  * ----------------------------------------------------------------------------------------------------
 291                  * 0x0 = ITU-R BT.601                   |  1 = YCbCr444
 292                  * 0x1 = ITU-R BT.709
 293                  * 0x2 = xvYCC601
 294                  * 0x3 = xvYCC709
 295                  * 0x4 = sYCC601
 296                  * 0x5 = AdobeYCC601
 297                  * 0x6 = ITU-R BT.2020 Y'cC'bcC'rc
 298                  * 0x7 = ITU-R BT.2020 Y'C'bC'r
 299                  * (others reserved)
 300                  * ----------------------------------------------------------------------------------------------------
 301                  * 0x0 = ITU-R BT.601                   |  2 = YCbCr422
 302                  * 0x1 = ITU-R BT.709
 303                  * 0x2 = xvYCC601
 304                  * 0x3 = xvYCC709
 305                  * 0x4 = sYCC601
 306                  * 0x5 = AdobeYCC601
 307                  * 0x6 = ITU-R BT.2020 Y'cC'bcC'rc
 308                  * 0x7 = ITU-R BT.2020 Y'C'bC'r
 309                  * (others reserved)
 310                  * ----------------------------------------------------------------------------------------------------
 311                  * 0x0 = ITU-R BT.601                   |  3 = YCbCr420
 312                  * 0x1 = ITU-R BT.709
 313                  * 0x2 = xvYCC601
 314                  * 0x3 = xvYCC709
 315                  * 0x4 = sYCC601
 316                  * 0x5 = AdobeYCC601
 317                  * 0x6 = ITU-R BT.2020 Y'cC'bcC'rc
 318                  * 0x7 = ITU-R BT.2020 Y'C'bC'r
 319                  * (others reserved)
 320                  * ----------------------------------------------------------------------------------------------------
 321                  * 0x0 =DICOM Part14 Grayscale          |  4 = Yonly
 322                  * Display Function
 323                  * (others reserved)
 324                  */
 325
 326                 /* Set Pixel Encoding */
 327                 switch (stream->timing.pixel_encoding) {
 328                 case PIXEL_ENCODING_RGB:
 329                         pixelEncoding = 0x0;  /* RGB = 0h */
 330                         break;
 331                 case PIXEL_ENCODING_YCBCR444:
 332                         pixelEncoding = 0x1;  /* YCbCr444 = 1h */
 333                         break;
 334                 case PIXEL_ENCODING_YCBCR422:
 335                         pixelEncoding = 0x2;  /* YCbCr422 = 2h */
 336                         break;
 337                 case PIXEL_ENCODING_YCBCR420:
 338                         pixelEncoding = 0x3;  /* YCbCr420 = 3h */
 339                         break;
 340                 default:
 341                         pixelEncoding = 0x0;  /* default RGB = 0h */
 342                         break;
 343                 }
 344
 345                 /* Set Colorimetry format based on pixel encoding */
 346                 switch (stream->timing.pixel_encoding) {
 347                 case PIXEL_ENCODING_RGB:
 348                         if ((stream->output_color_space == COLOR_SPACE_SRGB) ||
 349                                         (stream->output_color_space == COLOR_SPACE_SRGB_LIMITED))
 350                                 colorimetryFormat = ColorimetryRGB_DP_sRGB;
 351                         else if (stream->output_color_space == COLOR_SPACE_ADOBERGB)
 352                                 colorimetryFormat = ColorimetryRGB_DP_AdobeRGB;
 353                         else if ((stream->output_color_space == COLOR_SPACE_2020_RGB_FULLRANGE) ||
 354                                         (stream->output_color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE))
 355                                 colorimetryFormat = ColorimetryRGB_DP_ITU_R_BT2020RGB;
 356                         break;
 357
 358                 case PIXEL_ENCODING_YCBCR444:
 359                 case PIXEL_ENCODING_YCBCR422:
 360                 case PIXEL_ENCODING_YCBCR420:
 361                         /* Note: xvYCC probably not supported correctly here on DP since colorspace translation
 362                          * loses distinction between BT601 vs xvYCC601 in translation
 363                          */
 364                         if (stream->output_color_space == COLOR_SPACE_YCBCR601)
 365                                 colorimetryFormat = ColorimetryYCC_DP_ITU601;
 366                         else if (stream->output_color_space == COLOR_SPACE_YCBCR709)
 367                                 colorimetryFormat = ColorimetryYCC_DP_ITU709;
 368                         else if (stream->output_color_space == COLOR_SPACE_ADOBERGB)
 369                                 colorimetryFormat = ColorimetryYCC_DP_AdobeYCC;
 370                         else if (stream->output_color_space == COLOR_SPACE_2020_YCBCR)
 371                                 colorimetryFormat = ColorimetryYCC_DP_ITU2020YCbCr;
 372                         break;
 373
 374                 default:
 375                         colorimetryFormat = ColorimetryRGB_DP_sRGB;
 376                         break;
 377                 }
 378
 379                 info_packet->sb[16] = (pixelEncoding << 4) | colorimetryFormat;
 380
 381                 /* Set color depth */
 382                 switch (stream->timing.display_color_depth) {
 383                 case COLOR_DEPTH_666:
 384                         /* NOTE: This is actually not valid for YCbCr pixel encoding to have 6 bpc
 385                          *       as of DP1.4 spec, but value of 0 probably reserved here for potential future use.
 386                          */
 387                         info_packet->sb[17] = 0;
 388                         break;
 389                 case COLOR_DEPTH_888:
 390                         info_packet->sb[17] = 1;
 391                         break;
 392                 case COLOR_DEPTH_101010:
 393                         info_packet->sb[17] = 2;
 394                         break;
 395                 case COLOR_DEPTH_121212:
 396                         info_packet->sb[17] = 3;
 397                         break;
 398                 /*case COLOR_DEPTH_141414: -- NO SUCH FORMAT IN DP SPEC */
 399                 case COLOR_DEPTH_161616:
 400                         info_packet->sb[17] = 4;
 401                         break;
 402                 default:
 403                         info_packet->sb[17] = 0;
 404                         break;
 405                 }
 406
 407                 /* all YCbCr are always limited range */
 408                 if ((stream->output_color_space == COLOR_SPACE_SRGB_LIMITED) ||
 409                                 (stream->output_color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE) ||
 410                                 (pixelEncoding != 0x0)) {
 411                         info_packet->sb[17] |= 0x80; /* DB17 bit 7 set to 1 for CEA timing. */
 412                 }
 413
 414                 /* Content Type (Bits 2:0)
 415                  *  0 = Not defined.
 416                  *  1 = Graphics.
 417                  *  2 = Photo.
 418                  *  3 = Video.
 419                  *  4 = Game.
 420                  */
 421                 info_packet->sb[18] = 0;
 422         }
 423 }
 424
 425 /**
 426  *****************************************************************************
 427  *  Function: mod_build_hf_vsif_infopacket
 428  *
 429  *  @brief
 430  *     Prepare HDMI Vendor Specific info frame.
 431  *     Follows HDMI Spec to build up Vendor Specific info frame
 432  *
 433  *  @param [in] stream: contains data we may need to construct VSIF (i.e. timing_3d_format, etc.)
 434  *  @param [out] info_packet:   output structure where to store VSIF
 435  *****************************************************************************
 436  */
 437 void mod_build_hf_vsif_infopacket(const struct dc_stream_state *stream,
 438                 struct dc_info_packet *info_packet, int ALLMEnabled, int ALLMValue)
 439 {
 440                 unsigned int length = 5;
 441                 bool hdmi_vic_mode = false;
 442                 uint8_t checksum = 0;
 443                 uint32_t i = 0;
 444                 enum dc_timing_3d_format format;
 445                 bool bALLM = (bool)ALLMEnabled;
 446                 bool bALLMVal = (bool)ALLMValue;
 447
 448                 info_packet->valid = false;
 449                 format = stream->timing.timing_3d_format;
 450                 if (stream->view_format == VIEW_3D_FORMAT_NONE)
 451                         format = TIMING_3D_FORMAT_NONE;
 452
 453                 if (stream->timing.hdmi_vic != 0
 454                                 && stream->timing.h_total >= 3840
 455                                 && stream->timing.v_total >= 2160
 456                                 && format == TIMING_3D_FORMAT_NONE)
 457                         hdmi_vic_mode = true;
 458
 459                 if ((format == TIMING_3D_FORMAT_NONE) && !hdmi_vic_mode && !bALLM)
 460                         return;
 461
 462                 info_packet->sb[1] = 0x03;
 463                 info_packet->sb[2] = 0x0C;
 464                 info_packet->sb[3] = 0x00;
 465
 466                 if (bALLM) {
 467                         info_packet->sb[1] = 0xD8;
 468                         info_packet->sb[2] = 0x5D;
 469                         info_packet->sb[3] = 0xC4;
 470                         info_packet->sb[4] = HF_VSIF_VERSION;
 471                 }
 472
 473                 if (format != TIMING_3D_FORMAT_NONE)
 474                         info_packet->sb[4] = (2 << 5);
 475
 476                 else if (hdmi_vic_mode)
 477                         info_packet->sb[4] = (1 << 5);
 478
 479                 switch (format) {
 480                 case TIMING_3D_FORMAT_HW_FRAME_PACKING:
 481                 case TIMING_3D_FORMAT_SW_FRAME_PACKING:
 482                         info_packet->sb[5] = (0x0 << 4);
 483                         break;
 484
 485                 case TIMING_3D_FORMAT_SIDE_BY_SIDE:
 486                 case TIMING_3D_FORMAT_SBS_SW_PACKED:
 487                         info_packet->sb[5] = (0x8 << 4);
 488                         length = 6;
 489                         break;
 490
 491                 case TIMING_3D_FORMAT_TOP_AND_BOTTOM:
 492                 case TIMING_3D_FORMAT_TB_SW_PACKED:
 493                         info_packet->sb[5] = (0x6 << 4);
 494                         break;
 495
 496                 default:
 497                         break;
 498                 }
 499
 500                 if (hdmi_vic_mode)
 501                         info_packet->sb[5] = stream->timing.hdmi_vic;
 502
 503                 info_packet->hb0 = HDMI_INFOFRAME_TYPE_VENDOR;
 504                 info_packet->hb1 = 0x01;
 505                 info_packet->hb2 = (uint8_t) (length);
 506
 507                 if (bALLM)
 508                         info_packet->sb[5] = (info_packet->sb[5] & ~0x02) | (bALLMVal << 1);
 509
 510                 checksum += info_packet->hb0;
 511                 checksum += info_packet->hb1;
 512                 checksum += info_packet->hb2;
 513
 514                 for (i = 1; i <= length; i++)
 515                         checksum += info_packet->sb[i];
 516
 517                 info_packet->sb[0] = (uint8_t) (0x100 - checksum);
 518
 519                 info_packet->valid = true;
 520 }
 521