2 * Copyright 2019 Advanced Micro Devices, Inc.
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
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14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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29 #include "dmub_types.h"
30 #include "dmub_cmd_dal.h"
31 #include "dmub_cmd_vbios.h"
32 #include "atomfirmware.h"
34 #define DMUB_RB_CMD_SIZE 64
35 #define DMUB_RB_MAX_ENTRY 128
36 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY)
37 #define REG_SET_MASK 0xFFFF
41 * Command IDs should be treated as stable ABI.
42 * Do not reuse or modify IDs.
47 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1,
48 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2,
49 DMUB_CMD__REG_SEQ_BURST_WRITE = 3,
50 DMUB_CMD__REG_REG_WAIT = 4,
51 DMUB_CMD__PLAT_54186_WA = 5,
54 DMUB_CMD__VBIOS = 128,
59 struct dmub_cmd_header {
60 unsigned int type : 8;
61 unsigned int sub_type : 8;
62 unsigned int reserved0 : 8;
63 unsigned int payload_bytes : 6; /* up to 60 bytes */
64 unsigned int reserved1 : 2;
70 * 60 payload bytes can hold up to 5 sets of read modify writes,
73 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence)
75 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case
76 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write
78 struct dmub_cmd_read_modify_write_sequence {
81 uint32_t modify_value;
84 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5
85 struct dmub_rb_cmd_read_modify_write {
86 struct dmub_cmd_header header; // type = DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE
87 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX];
91 * Update a register with specified masks and values sequeunce
93 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword
95 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence)
99 * 1. auto-increment register where additional read would update pointer and produce wrong result
100 * 2. toggle a bit without read in the middle
103 struct dmub_cmd_reg_field_update_sequence {
104 uint32_t modify_mask; // 0xffff'ffff to skip initial read
105 uint32_t modify_value;
108 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7
110 struct dmub_rb_cmd_reg_field_update_sequence {
111 struct dmub_cmd_header header;
113 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX];
120 * support use case such as writing out LUTs.
122 * 60 payload bytes can hold up to 14 values to write to given address
124 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence)
126 #define DMUB_BURST_WRITE_VALUES__MAX 14
127 struct dmub_rb_cmd_burst_write {
128 struct dmub_cmd_header header; // type = DMUB_CMD__REG_SEQ_BURST_WRITE
130 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX];
134 struct dmub_rb_cmd_common {
135 struct dmub_cmd_header header;
136 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)];
139 struct dmub_cmd_reg_wait_data {
142 uint32_t condition_field_value;
143 uint32_t time_out_us;
146 struct dmub_rb_cmd_reg_wait {
147 struct dmub_cmd_header header;
148 struct dmub_cmd_reg_wait_data reg_wait;
151 #ifndef PHYSICAL_ADDRESS_LOC
152 #define PHYSICAL_ADDRESS_LOC union large_integer
155 struct dmub_cmd_PLAT_54186_wa {
156 uint32_t DCSURF_SURFACE_CONTROL;
157 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH;
158 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS;
159 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C;
160 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C;
162 uint8_t hubp_inst : 4;
163 uint8_t tmz_surface : 1;
164 uint8_t immediate :1;
166 uint8_t grph_stereo : 1;
167 uint32_t reserved : 21;
169 uint32_t reserved[9];
172 struct dmub_rb_cmd_PLAT_54186_wa {
173 struct dmub_cmd_header header;
174 struct dmub_cmd_PLAT_54186_wa flip;
177 struct dmub_cmd_digx_encoder_control_data {
178 union dig_encoder_control_parameters_v1_5 dig;
181 struct dmub_rb_cmd_digx_encoder_control {
182 struct dmub_cmd_header header;
183 struct dmub_cmd_digx_encoder_control_data encoder_control;
186 struct dmub_cmd_set_pixel_clock_data {
187 struct set_pixel_clock_parameter_v1_7 clk;
190 struct dmub_rb_cmd_set_pixel_clock {
191 struct dmub_cmd_header header;
192 struct dmub_cmd_set_pixel_clock_data pixel_clock;
195 struct dmub_cmd_enable_disp_power_gating_data {
196 struct enable_disp_power_gating_parameters_v2_1 pwr;
199 struct dmub_rb_cmd_enable_disp_power_gating {
200 struct dmub_cmd_header header;
201 struct dmub_cmd_enable_disp_power_gating_data power_gating;
204 struct dmub_cmd_dig1_transmitter_control_data {
205 struct dig_transmitter_control_parameters_v1_6 dig;
208 struct dmub_rb_cmd_dig1_transmitter_control {
209 struct dmub_cmd_header header;
210 struct dmub_cmd_dig1_transmitter_control_data transmitter_control;
213 struct dmub_rb_cmd_dpphy_init {
214 struct dmub_cmd_header header;
215 uint8_t reserved[60];
218 struct dmub_cmd_psr_copy_settings_data {
228 uint8_t smu_optimizations_en;
230 uint8_t frame_cap_ind;
231 struct dmub_psr_debug_flags debug;
234 struct dmub_rb_cmd_psr_copy_settings {
235 struct dmub_cmd_header header;
236 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data;
239 struct dmub_cmd_psr_set_level_data {
243 struct dmub_rb_cmd_psr_set_level {
244 struct dmub_cmd_header header;
245 struct dmub_cmd_psr_set_level_data psr_set_level_data;
248 struct dmub_rb_cmd_psr_enable {
249 struct dmub_cmd_header header;
252 struct dmub_cmd_psr_set_version_data {
253 enum psr_version version; // PSR version 1 or 2
256 struct dmub_rb_cmd_psr_set_version {
257 struct dmub_cmd_header header;
258 struct dmub_cmd_psr_set_version_data psr_set_version_data;
261 struct dmub_cmd_abm_set_pipe_data {
262 uint32_t ramping_boundary;
265 uint32_t set_pipe_option;
268 struct dmub_rb_cmd_abm_set_pipe {
269 struct dmub_cmd_header header;
270 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data;
273 struct dmub_cmd_abm_set_backlight_data {
277 struct dmub_rb_cmd_abm_set_backlight {
278 struct dmub_cmd_header header;
279 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data;
282 struct dmub_cmd_abm_set_level_data {
286 struct dmub_rb_cmd_abm_set_level {
287 struct dmub_cmd_header header;
288 struct dmub_cmd_abm_set_level_data abm_set_level_data;
291 struct dmub_cmd_abm_set_ambient_level_data {
292 uint32_t ambient_lux;
295 struct dmub_rb_cmd_abm_set_ambient_level {
296 struct dmub_cmd_header header;
297 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data;
300 struct dmub_cmd_abm_set_pwm_frac_data {
301 uint32_t fractional_pwm;
304 struct dmub_rb_cmd_abm_set_pwm_frac {
305 struct dmub_cmd_header header;
306 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data;
309 struct dmub_cmd_abm_init_config_data {
314 struct dmub_rb_cmd_abm_init_config {
315 struct dmub_cmd_header header;
316 struct dmub_cmd_abm_init_config_data abm_init_config_data;
320 struct dmub_rb_cmd_read_modify_write read_modify_write;
321 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq;
322 struct dmub_rb_cmd_burst_write burst_write;
323 struct dmub_rb_cmd_reg_wait reg_wait;
324 struct dmub_rb_cmd_common cmd_common;
325 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control;
326 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock;
327 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating;
328 struct dmub_rb_cmd_dpphy_init dpphy_init;
329 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control;
330 struct dmub_rb_cmd_psr_set_version psr_set_version;
331 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings;
332 struct dmub_rb_cmd_psr_enable psr_enable;
333 struct dmub_rb_cmd_psr_set_level psr_set_level;
334 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa;
335 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe;
336 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight;
337 struct dmub_rb_cmd_abm_set_level abm_set_level;
338 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level;
339 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac;
340 struct dmub_rb_cmd_abm_init_config abm_init_config;
345 #endif /* _DMUB_CMD_H_ */