2 * Copyright 2019 Advanced Micro Devices, Inc.
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
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15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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29 #include "dmub_types.h"
30 #include "dmub_cmd_dal.h"
31 #include "dmub_cmd_vbios.h"
32 #include "atomfirmware.h"
34 #define DMUB_RB_CMD_SIZE 64
35 #define DMUB_RB_MAX_ENTRY 128
36 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY)
37 #define REG_SET_MASK 0xFFFF
40 * Command IDs should be treated as stable ABI.
41 * Do not reuse or modify IDs.
46 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1,
47 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2,
48 DMUB_CMD__REG_SEQ_BURST_WRITE = 3,
49 DMUB_CMD__REG_REG_WAIT = 4,
51 DMUB_CMD__VBIOS = 128,
56 struct dmub_cmd_header {
57 unsigned int type : 8;
58 unsigned int sub_type : 8;
59 unsigned int reserved0 : 8;
60 unsigned int payload_bytes : 6; /* up to 60 bytes */
61 unsigned int reserved1 : 2;
67 * 60 payload bytes can hold up to 5 sets of read modify writes,
70 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence)
72 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case
73 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write
75 struct dmub_cmd_read_modify_write_sequence {
78 uint32_t modify_value;
81 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5
82 struct dmub_rb_cmd_read_modify_write {
83 struct dmub_cmd_header header; // type = DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE
84 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX];
88 * Update a register with specified masks and values sequeunce
90 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword
92 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence)
96 * 1. auto-increment register where additional read would update pointer and produce wrong result
97 * 2. toggle a bit without read in the middle
100 struct dmub_cmd_reg_field_update_sequence {
101 uint32_t modify_mask; // 0xffff'ffff to skip initial read
102 uint32_t modify_value;
105 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7
107 struct dmub_rb_cmd_reg_field_update_sequence {
108 struct dmub_cmd_header header;
110 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX];
117 * support use case such as writing out LUTs.
119 * 60 payload bytes can hold up to 14 values to write to given address
121 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence)
123 #define DMUB_BURST_WRITE_VALUES__MAX 14
124 struct dmub_rb_cmd_burst_write {
125 struct dmub_cmd_header header; // type = DMUB_CMD__REG_SEQ_BURST_WRITE
127 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX];
131 struct dmub_rb_cmd_common {
132 struct dmub_cmd_header header;
133 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)];
136 struct dmub_cmd_reg_wait_data {
139 uint32_t condition_field_value;
140 uint32_t time_out_us;
143 struct dmub_rb_cmd_reg_wait {
144 struct dmub_cmd_header header;
145 struct dmub_cmd_reg_wait_data reg_wait;
148 struct dmub_cmd_digx_encoder_control_data {
149 union dig_encoder_control_parameters_v1_5 dig;
152 struct dmub_rb_cmd_digx_encoder_control {
153 struct dmub_cmd_header header;
154 struct dmub_cmd_digx_encoder_control_data encoder_control;
157 struct dmub_cmd_set_pixel_clock_data {
158 struct set_pixel_clock_parameter_v1_7 clk;
161 struct dmub_rb_cmd_set_pixel_clock {
162 struct dmub_cmd_header header;
163 struct dmub_cmd_set_pixel_clock_data pixel_clock;
166 struct dmub_cmd_enable_disp_power_gating_data {
167 struct enable_disp_power_gating_parameters_v2_1 pwr;
170 struct dmub_rb_cmd_enable_disp_power_gating {
171 struct dmub_cmd_header header;
172 struct dmub_cmd_enable_disp_power_gating_data power_gating;
175 struct dmub_cmd_dig1_transmitter_control_data {
176 struct dig_transmitter_control_parameters_v1_6 dig;
179 struct dmub_rb_cmd_dig1_transmitter_control {
180 struct dmub_cmd_header header;
181 struct dmub_cmd_dig1_transmitter_control_data transmitter_control;
184 struct dmub_rb_cmd_dpphy_init {
185 struct dmub_cmd_header header;
186 uint8_t reserved[60];
189 struct dmub_cmd_psr_copy_settings_data {
195 struct dmub_rb_cmd_psr_copy_settings {
196 struct dmub_cmd_header header;
197 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data;
200 struct dmub_cmd_psr_set_level_data {
204 struct dmub_rb_cmd_psr_set_level {
205 struct dmub_cmd_header header;
206 struct dmub_cmd_psr_set_level_data psr_set_level_data;
209 struct dmub_rb_cmd_psr_disable {
210 struct dmub_cmd_header header;
213 struct dmub_rb_cmd_psr_enable {
214 struct dmub_cmd_header header;
217 struct dmub_cmd_psr_notify_vblank_data {
218 uint32_t vblank_int; // Which vblank interrupt was triggered
221 struct dmub_rb_cmd_notify_vblank {
222 struct dmub_cmd_header header;
223 struct dmub_cmd_psr_notify_vblank_data psr_notify_vblank_data;
226 struct dmub_cmd_psr_notify_static_state_data {
227 uint32_t ss_int; // Which static screen interrupt was triggered
228 uint32_t ss_enter; // Enter (1) or exit (0) static screen
231 struct dmub_rb_cmd_psr_notify_static_state {
232 struct dmub_cmd_header header;
233 struct dmub_cmd_psr_notify_static_state_data psr_notify_static_state_data;
237 struct dmub_rb_cmd_read_modify_write read_modify_write;
238 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq;
239 struct dmub_rb_cmd_burst_write burst_write;
240 struct dmub_rb_cmd_reg_wait reg_wait;
241 struct dmub_rb_cmd_common cmd_common;
242 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control;
243 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock;
244 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating;
245 struct dmub_rb_cmd_dpphy_init dpphy_init;
246 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control;
247 struct dmub_rb_cmd_psr_enable psr_enable;
248 struct dmub_rb_cmd_psr_disable psr_disable;
249 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings;
250 struct dmub_rb_cmd_psr_set_level psr_set_level;
255 #endif /* _DMUB_CMD_H_ */