2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
29 #if defined(_TEST_HARNESS) || defined(FPGA_USB4)
30 #include "dmub_fw_types.h"
31 #include "include_legacy/atomfirmware.h"
33 #if defined(_TEST_HARNESS)
38 #include <asm/byteorder.h>
39 #include <linux/types.h>
40 #include <linux/string.h>
41 #include <linux/delay.h>
44 #include "atomfirmware.h"
46 #endif // defined(_TEST_HARNESS) || defined(FPGA_USB4)
48 /* Firmware versioning. */
49 #ifdef DMUB_EXPOSE_VERSION
50 #define DMUB_FW_VERSION_GIT_HASH 0x7383caadc
51 #define DMUB_FW_VERSION_MAJOR 0
52 #define DMUB_FW_VERSION_MINOR 0
53 #define DMUB_FW_VERSION_REVISION 79
54 #define DMUB_FW_VERSION_TEST 0
55 #define DMUB_FW_VERSION_VBIOS 0
56 #define DMUB_FW_VERSION_HOTFIX 0
57 #define DMUB_FW_VERSION_UCODE (((DMUB_FW_VERSION_MAJOR & 0xFF) << 24) | \
58 ((DMUB_FW_VERSION_MINOR & 0xFF) << 16) | \
59 ((DMUB_FW_VERSION_REVISION & 0xFF) << 8) | \
60 ((DMUB_FW_VERSION_TEST & 0x1) << 7) | \
61 ((DMUB_FW_VERSION_VBIOS & 0x1) << 6) | \
62 (DMUB_FW_VERSION_HOTFIX & 0x3F))
66 //<DMUB_TYPES>==================================================================
67 /* Basic type definitions. */
69 #define __forceinline inline
72 * Flag from driver to indicate that ABM should be disabled gradually
73 * by slowly reversing all backlight programming and pixel compensation.
75 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0
78 * Flag from driver to indicate that ABM should be disabled immediately
79 * and undo all backlight programming and pixel compensation.
81 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255
84 * Flag from driver to indicate that ABM should be disabled immediately
85 * and keep the current backlight programming and pixel compensation.
87 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254
90 * Flag from driver to set the current ABM pipe index or ABM operating level.
92 #define SET_ABM_PIPE_NORMAL 1
95 * Number of ambient light levels in ABM algorithm.
97 #define NUM_AMBI_LEVEL 5
100 * Number of operating/aggression levels in ABM algorithm.
102 #define NUM_AGGR_LEVEL 4
105 * Number of segments in the gamma curve.
107 #define NUM_POWER_FN_SEGS 8
110 * Number of segments in the backlight curve.
112 #define NUM_BL_CURVE_SEGS 16
114 /* Maximum number of streams on any ASIC. */
115 #define DMUB_MAX_STREAMS 6
117 /* Maximum number of planes on any ASIC. */
118 #define DMUB_MAX_PLANES 6
120 /* Trace buffer offset for entry */
121 #define TRACE_BUFFER_ENTRY_OFFSET 16
125 * PSR control version legacy
127 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0
129 * PSR control version with multi edp support
131 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1
135 * ABM control version legacy
137 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0
140 * ABM control version with multi edp support
142 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1
145 * Physical framebuffer address location, 64-bit.
147 #ifndef PHYSICAL_ADDRESS_LOC
148 #define PHYSICAL_ADDRESS_LOC union large_integer
152 * OS/FW agnostic memcpy
155 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes))
159 * OS/FW agnostic memset
162 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes))
165 #if defined(__cplusplus)
170 * OS/FW agnostic udelay
173 #define dmub_udelay(microseconds) udelay(microseconds)
177 * Number of nanoseconds per DMUB tick.
178 * DMCUB_TIMER_CURRENT increments in DMUB ticks, which are 10ns by default.
179 * If DMCUB_TIMER_WINDOW is non-zero this will no longer be true.
181 #define NS_PER_DMUB_TICK 10
184 * union dmub_addr - DMUB physical/virtual 64-bit address.
188 uint32_t low_part; /**< Lower 32 bits */
189 uint32_t high_part; /**< Upper 32 bits */
190 } u; /*<< Low/high bit access */
191 uint64_t quad_part; /*<< 64 bit address */
195 * Flags that can be set by driver to change some PSR behaviour.
197 union dmub_psr_debug_flags {
203 * Enable visual confirm in FW.
205 uint32_t visual_confirm : 1;
207 * Use HW Lock Mgr object to do HW locking in FW.
209 uint32_t use_hw_lock_mgr : 1;
215 uint32_t log_line_nums : 1;
219 * Union for debug flags.
225 * DMUB feature capabilities.
226 * After DMUB init, driver will query FW capabilities prior to enabling certain features.
228 struct dmub_feature_caps {
230 * Max PSR version supported by FW.
236 #if defined(__cplusplus)
240 //==============================================================================
241 //</DMUB_TYPES>=================================================================
242 //==============================================================================
243 //< DMUB_META>==================================================================
244 //==============================================================================
245 #pragma pack(push, 1)
247 /* Magic value for identifying dmub_fw_meta_info */
248 #define DMUB_FW_META_MAGIC 0x444D5542
250 /* Offset from the end of the file to the dmub_fw_meta_info */
251 #define DMUB_FW_META_OFFSET 0x24
254 * struct dmub_fw_meta_info - metadata associated with fw binary
256 * NOTE: This should be considered a stable API. Fields should
257 * not be repurposed or reordered. New fields should be
258 * added instead to extend the structure.
260 * @magic_value: magic value identifying DMUB firmware meta info
261 * @fw_region_size: size of the firmware state region
262 * @trace_buffer_size: size of the tracebuffer region
263 * @fw_version: the firmware version information
264 * @dal_fw: 1 if the firmware is DAL
266 struct dmub_fw_meta_info {
267 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */
268 uint32_t fw_region_size; /**< size of the firmware state region */
269 uint32_t trace_buffer_size; /**< size of the tracebuffer region */
270 uint32_t fw_version; /**< the firmware version information */
271 uint8_t dal_fw; /**< 1 if the firmware is DAL */
272 uint8_t reserved[3]; /**< padding bits */
276 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes
279 struct dmub_fw_meta_info info; /**< metadata info */
280 uint8_t reserved[64]; /**< padding bits */
285 //==============================================================================
286 //< DMUB Trace Buffer>================================================================
287 //==============================================================================
289 * dmub_trace_code_t - firmware trace code, 32-bits
291 typedef uint32_t dmub_trace_code_t;
294 * struct dmcub_trace_buf_entry - Firmware trace entry
296 struct dmcub_trace_buf_entry {
297 dmub_trace_code_t trace_code; /**< trace code for the event */
298 uint32_t tick_count; /**< the tick count at time of trace */
299 uint32_t param0; /**< trace defined parameter 0 */
300 uint32_t param1; /**< trace defined parameter 1 */
303 //==============================================================================
304 //< DMUB_STATUS>================================================================
305 //==============================================================================
308 * DMCUB scratch registers can be used to determine firmware status.
309 * Current scratch register usage is as follows:
311 * SCRATCH0: FW Boot Status register
312 * SCRATCH5: LVTMA Status Register
313 * SCRATCH15: FW Boot Options register
317 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0.
319 union dmub_fw_boot_status {
321 uint32_t dal_fw : 1; /**< 1 if DAL FW */
322 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */
323 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */
324 uint32_t restore_required : 1; /**< 1 if driver should call restore */
325 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */
326 uint32_t reserved : 1;
327 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */
329 } bits; /**< status bits */
330 uint32_t all; /**< 32-bit access to status bits */
334 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0.
336 enum dmub_fw_boot_status_bit {
337 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */
338 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */
339 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */
340 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */
341 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */
342 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/
345 /* Register bit definition for SCRATCH5 */
346 union dmub_lvtma_status {
350 uint32_t reserved : 30;
355 enum dmub_lvtma_status_bit {
356 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0),
357 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1),
361 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14
363 union dmub_fw_boot_options {
365 uint32_t pemu_env : 1; /**< 1 if PEMU */
366 uint32_t fpga_env : 1; /**< 1 if FPGA */
367 uint32_t optimized_init : 1; /**< 1 if optimized init */
368 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */
369 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */
370 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */
371 uint32_t z10_disable: 1; /**< 1 to disable z10 */
372 uint32_t reserved2: 1; /**< reserved for an unreleased feature */
373 uint32_t reserved_unreleased1: 1; /**< reserved for an unreleased feature */
374 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */
375 uint32_t reserved : 23; /**< reserved */
376 } bits; /**< boot bits */
377 uint32_t all; /**< 32-bit access to bits */
380 enum dmub_fw_boot_options_bit {
381 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */
382 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */
383 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */
386 //==============================================================================
387 //</DMUB_STATUS>================================================================
388 //==============================================================================
389 //< DMUB_VBIOS>=================================================================
390 //==============================================================================
393 * enum dmub_cmd_vbios_type - VBIOS commands.
395 * Command IDs should be treated as stable ABI.
396 * Do not reuse or modify IDs.
398 enum dmub_cmd_vbios_type {
400 * Configures the DIG encoder.
402 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0,
406 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1,
408 * Sets the pixel clock/symbol clock.
410 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2,
412 * Enables or disables power gating.
414 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3,
415 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15,
418 //==============================================================================
419 //</DMUB_VBIOS>=================================================================
420 //==============================================================================
421 //< DMUB_GPINT>=================================================================
422 //==============================================================================
425 * The shifts and masks below may alternatively be used to format and read
426 * the command register bits.
429 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF
430 #define DMUB_GPINT_DATA_PARAM_SHIFT 0
432 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF
433 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16
435 #define DMUB_GPINT_DATA_STATUS_MASK 0xF
436 #define DMUB_GPINT_DATA_STATUS_SHIFT 28
443 * Return response for DMUB_GPINT__STOP_FW command.
445 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD
448 * union dmub_gpint_data_register - Format for sending a command via the GPINT.
450 union dmub_gpint_data_register {
452 uint32_t param : 16; /**< 16-bit parameter */
453 uint32_t command_code : 12; /**< GPINT command */
454 uint32_t status : 4; /**< Command status bit */
455 } bits; /**< GPINT bit access */
456 uint32_t all; /**< GPINT 32-bit access */
460 * enum dmub_gpint_command - GPINT command to DMCUB FW
462 * Command IDs should be treated as stable ABI.
463 * Do not reuse or modify IDs.
465 enum dmub_gpint_command {
467 * Invalid command, ignored.
469 DMUB_GPINT__INVALID_COMMAND = 0,
471 * DESC: Queries the firmware version.
472 * RETURN: Firmware version.
474 DMUB_GPINT__GET_FW_VERSION = 1,
476 * DESC: Halts the firmware.
477 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted
479 DMUB_GPINT__STOP_FW = 2,
481 * DESC: Get PSR state from FW.
482 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value.
484 DMUB_GPINT__GET_PSR_STATE = 7,
486 * DESC: Notifies DMCUB of the currently active streams.
487 * ARGS: Stream mask, 1 bit per active stream index.
489 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8,
491 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value.
492 * ARGS: We can measure residency from various points. The argument will specify the residency mode.
493 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY.
494 * RETURN: PSR residency in milli-percent.
496 DMUB_GPINT__PSR_RESIDENCY = 9,
499 * DESC: Notifies DMCUB detection is done so detection required can be cleared.
501 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12,
505 * INBOX0 generic command definition
507 union dmub_inbox0_cmd_common {
509 uint32_t command_code: 8; /**< INBOX0 command code */
510 uint32_t param: 24; /**< 24-bit parameter */
516 * INBOX0 hw_lock command definition
518 union dmub_inbox0_cmd_lock_hw {
520 uint32_t command_code: 8;
522 /* NOTE: Must be have enough bits to match: enum hw_lock_client */
523 uint32_t hw_lock_client: 1;
525 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */
526 uint32_t otg_inst: 3;
527 uint32_t opp_inst: 3;
528 uint32_t dig_inst: 3;
530 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */
531 uint32_t lock_pipe: 1;
532 uint32_t lock_cursor: 1;
533 uint32_t lock_dig: 1;
534 uint32_t triple_buffer_lock: 1;
536 uint32_t lock: 1; /**< Lock */
537 uint32_t should_release: 1; /**< Release */
538 uint32_t reserved: 8; /**< Reserved for extending more clients, HW, etc. */
543 union dmub_inbox0_data_register {
544 union dmub_inbox0_cmd_common inbox0_cmd_common;
545 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw;
548 enum dmub_inbox0_command {
550 * DESC: Invalid command, ignored.
552 DMUB_INBOX0_CMD__INVALID_COMMAND = 0,
554 * DESC: Notification to acquire/release HW lock
557 DMUB_INBOX0_CMD__HW_LOCK = 1,
559 //==============================================================================
560 //</DMUB_GPINT>=================================================================
561 //==============================================================================
562 //< DMUB_CMD>===================================================================
563 //==============================================================================
566 * Size in bytes of each DMUB command.
568 #define DMUB_RB_CMD_SIZE 64
571 * Maximum number of items in the DMUB ringbuffer.
573 #define DMUB_RB_MAX_ENTRY 128
576 * Ringbuffer size in bytes.
578 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY)
581 * REG_SET mask for reg offload.
583 #define REG_SET_MASK 0xFFFF
586 * enum dmub_cmd_type - DMUB inbox command.
588 * Command IDs should be treated as stable ABI.
589 * Do not reuse or modify IDs.
597 * Read modify write register sequence offload.
599 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1,
601 * Field update register sequence offload.
603 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2,
605 * Burst write sequence offload.
607 DMUB_CMD__REG_SEQ_BURST_WRITE = 3,
609 * Reg wait sequence offload.
611 DMUB_CMD__REG_REG_WAIT = 4,
613 * Workaround to avoid HUBP underflow during NV12 playback.
615 DMUB_CMD__PLAT_54186_WA = 5,
617 * Command type used to query FW feature caps.
619 DMUB_CMD__QUERY_FEATURE_CAPS = 6,
621 * Command type used for all PSR commands.
625 * Command type used for all MALL commands.
629 * Command type used for all ABM commands.
633 * Command type used for HW locking in FW.
635 DMUB_CMD__HW_LOCK = 69,
637 * Command type used to access DP AUX.
639 DMUB_CMD__DP_AUX_ACCESS = 70,
641 * Command type used for OUTBOX1 notification enable
643 DMUB_CMD__OUTBOX1_ENABLE = 71,
645 * Command type used for all idle optimization commands.
647 DMUB_CMD__IDLE_OPT = 72,
649 * Command type used for all clock manager commands.
651 DMUB_CMD__CLK_MGR = 73,
653 * Command type used for all panel control commands.
655 DMUB_CMD__PANEL_CNTL = 74,
657 * Command type used for EDID CEA parsing
659 DMUB_CMD__EDID_CEA = 79,
661 * Command type used for all VBIOS interface commands.
663 DMUB_CMD__VBIOS = 128,
667 * enum dmub_out_cmd_type - DMUB outbox commands.
669 enum dmub_out_cmd_type {
671 * Invalid outbox command, ignored.
673 DMUB_OUT_CMD__NULL = 0,
675 * Command type used for DP AUX Reply data notification
677 DMUB_OUT_CMD__DP_AUX_REPLY = 1,
680 #pragma pack(push, 1)
683 * struct dmub_cmd_header - Common command header fields.
685 struct dmub_cmd_header {
686 unsigned int type : 8; /**< command type */
687 unsigned int sub_type : 8; /**< command sub type */
688 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */
689 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */
690 unsigned int reserved0 : 6; /**< reserved bits */
691 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */
692 unsigned int reserved1 : 2; /**< reserved bits */
696 * struct dmub_cmd_read_modify_write_sequence - Read modify write
698 * 60 payload bytes can hold up to 5 sets of read modify writes,
699 * each take 3 dwords.
701 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence)
703 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case
704 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write
706 struct dmub_cmd_read_modify_write_sequence {
707 uint32_t addr; /**< register address */
708 uint32_t modify_mask; /**< modify mask */
709 uint32_t modify_value; /**< modify value */
713 * Maximum number of ops in read modify write sequence.
715 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5
718 * struct dmub_cmd_read_modify_write_sequence - Read modify write command.
720 struct dmub_rb_cmd_read_modify_write {
721 struct dmub_cmd_header header; /**< command header */
723 * Read modify write sequence.
725 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX];
729 * Update a register with specified masks and values sequeunce
731 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword
733 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence)
737 * 1. auto-increment register where additional read would update pointer and produce wrong result
738 * 2. toggle a bit without read in the middle
741 struct dmub_cmd_reg_field_update_sequence {
742 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */
743 uint32_t modify_value; /**< value to update with */
747 * Maximum number of ops in field update sequence.
749 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7
752 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command.
754 struct dmub_rb_cmd_reg_field_update_sequence {
755 struct dmub_cmd_header header; /**< command header */
756 uint32_t addr; /**< register address */
758 * Field update sequence.
760 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX];
765 * Maximum number of burst write values.
767 #define DMUB_BURST_WRITE_VALUES__MAX 14
770 * struct dmub_rb_cmd_burst_write - Burst write
772 * support use case such as writing out LUTs.
774 * 60 payload bytes can hold up to 14 values to write to given address
776 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence)
778 struct dmub_rb_cmd_burst_write {
779 struct dmub_cmd_header header; /**< command header */
780 uint32_t addr; /**< register start address */
782 * Burst write register values.
784 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX];
788 * struct dmub_rb_cmd_common - Common command header
790 struct dmub_rb_cmd_common {
791 struct dmub_cmd_header header; /**< command header */
793 * Padding to RB_CMD_SIZE
795 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)];
799 * struct dmub_cmd_reg_wait_data - Register wait data
801 struct dmub_cmd_reg_wait_data {
802 uint32_t addr; /**< Register address */
803 uint32_t mask; /**< Mask for register bits */
804 uint32_t condition_field_value; /**< Value to wait for */
805 uint32_t time_out_us; /**< Time out for reg wait in microseconds */
809 * struct dmub_rb_cmd_reg_wait - Register wait command
811 struct dmub_rb_cmd_reg_wait {
812 struct dmub_cmd_header header; /**< Command header */
813 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */
817 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround
819 * Reprograms surface parameters to avoid underflow.
821 struct dmub_cmd_PLAT_54186_wa {
822 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */
823 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */
824 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */
825 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */
826 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */
828 uint8_t hubp_inst : 4; /**< HUBP instance */
829 uint8_t tmz_surface : 1; /**< TMZ enable or disable */
830 uint8_t immediate :1; /**< Immediate flip */
831 uint8_t vmid : 4; /**< VMID */
832 uint8_t grph_stereo : 1; /**< 1 if stereo */
833 uint32_t reserved : 21; /**< Reserved */
834 } flip_params; /**< Pageflip parameters */
835 uint32_t reserved[9]; /**< Reserved bits */
839 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command
841 struct dmub_rb_cmd_PLAT_54186_wa {
842 struct dmub_cmd_header header; /**< Command header */
843 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */
847 * struct dmub_rb_cmd_mall - MALL command data.
849 struct dmub_rb_cmd_mall {
850 struct dmub_cmd_header header; /**< Common command header */
851 union dmub_addr cursor_copy_src; /**< Cursor copy address */
852 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */
853 uint32_t tmr_delay; /**< Timer delay */
854 uint32_t tmr_scale; /**< Timer scale */
855 uint16_t cursor_width; /**< Cursor width in pixels */
856 uint16_t cursor_pitch; /**< Cursor pitch in pixels */
857 uint16_t cursor_height; /**< Cursor height in pixels */
858 uint8_t cursor_bpp; /**< Cursor bits per pixel */
859 uint8_t debug_bits; /**< Debug bits */
861 uint8_t reserved1; /**< Reserved bits */
862 uint8_t reserved2; /**< Reserved bits */
866 * enum dmub_cmd_idle_opt_type - Idle optimization command type.
868 enum dmub_cmd_idle_opt_type {
870 * DCN hardware restore.
872 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0,
877 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1
881 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data.
883 struct dmub_rb_cmd_idle_opt_dcn_restore {
884 struct dmub_cmd_header header; /**< header */
888 * struct dmub_clocks - Clock update notification.
891 uint32_t dispclk_khz; /**< dispclk kHz */
892 uint32_t dppclk_khz; /**< dppclk kHz */
893 uint32_t dcfclk_khz; /**< dcfclk kHz */
894 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */
898 * enum dmub_cmd_clk_mgr_type - Clock manager commands.
900 enum dmub_cmd_clk_mgr_type {
902 * Notify DMCUB of clock update.
904 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0,
908 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification.
910 struct dmub_rb_cmd_clk_mgr_notify_clocks {
911 struct dmub_cmd_header header; /**< header */
912 struct dmub_clocks clocks; /**< clock data */
916 * struct dmub_cmd_digx_encoder_control_data - Encoder control data.
918 struct dmub_cmd_digx_encoder_control_data {
919 union dig_encoder_control_parameters_v1_5 dig; /**< payload */
923 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command.
925 struct dmub_rb_cmd_digx_encoder_control {
926 struct dmub_cmd_header header; /**< header */
927 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */
931 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data.
933 struct dmub_cmd_set_pixel_clock_data {
934 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */
938 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command.
940 struct dmub_rb_cmd_set_pixel_clock {
941 struct dmub_cmd_header header; /**< header */
942 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */
946 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating.
948 struct dmub_cmd_enable_disp_power_gating_data {
949 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */
953 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command.
955 struct dmub_rb_cmd_enable_disp_power_gating {
956 struct dmub_cmd_header header; /**< header */
957 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */
961 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control.
963 struct dmub_dig_transmitter_control_data_v1_7 {
964 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */
965 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */
967 uint8_t digmode; /**< enum atom_encode_mode_def */
968 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */
970 uint8_t lanenum; /**< Number of lanes */
972 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */
974 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */
975 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */
976 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */
977 uint8_t reserved0; /**< For future use */
978 uint8_t reserved1; /**< For future use */
979 uint8_t reserved2[3]; /**< For future use */
980 uint32_t reserved3[11]; /**< For future use */
984 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data.
986 union dmub_cmd_dig1_transmitter_control_data {
987 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */
988 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */
992 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command.
994 struct dmub_rb_cmd_dig1_transmitter_control {
995 struct dmub_cmd_header header; /**< header */
996 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */
1000 * struct dmub_rb_cmd_dpphy_init - DPPHY init.
1002 struct dmub_rb_cmd_dpphy_init {
1003 struct dmub_cmd_header header; /**< header */
1004 uint8_t reserved[60]; /**< reserved bits */
1008 * enum dp_aux_request_action - DP AUX request command listing.
1010 * 4 AUX request command bits are shifted to high nibble.
1012 enum dp_aux_request_action {
1013 /** I2C-over-AUX write request */
1014 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00,
1015 /** I2C-over-AUX read request */
1016 DP_AUX_REQ_ACTION_I2C_READ = 0x10,
1017 /** I2C-over-AUX write status request */
1018 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20,
1019 /** I2C-over-AUX write request with MOT=1 */
1020 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40,
1021 /** I2C-over-AUX read request with MOT=1 */
1022 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50,
1023 /** I2C-over-AUX write status request with MOT=1 */
1024 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60,
1025 /** Native AUX write request */
1026 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80,
1027 /** Native AUX read request */
1028 DP_AUX_REQ_ACTION_DPCD_READ = 0x90
1032 * enum aux_return_code_type - DP AUX process return code listing.
1034 enum aux_return_code_type {
1035 /** AUX process succeeded */
1036 AUX_RET_SUCCESS = 0,
1037 /** AUX process failed with unknown reason */
1038 AUX_RET_ERROR_UNKNOWN,
1039 /** AUX process completed with invalid reply */
1040 AUX_RET_ERROR_INVALID_REPLY,
1041 /** AUX process timed out */
1042 AUX_RET_ERROR_TIMEOUT,
1043 /** HPD was low during AUX process */
1044 AUX_RET_ERROR_HPD_DISCON,
1045 /** Failed to acquire AUX engine */
1046 AUX_RET_ERROR_ENGINE_ACQUIRE,
1047 /** AUX request not supported */
1048 AUX_RET_ERROR_INVALID_OPERATION,
1049 /** AUX process not available */
1050 AUX_RET_ERROR_PROTOCOL_ERROR,
1054 * enum aux_channel_type - DP AUX channel type listing.
1056 enum aux_channel_type {
1057 /** AUX thru Legacy DP AUX */
1058 AUX_CHANNEL_LEGACY_DDC,
1059 /** AUX thru DPIA DP tunneling */
1064 * struct aux_transaction_parameters - DP AUX request transaction data
1066 struct aux_transaction_parameters {
1067 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */
1068 uint8_t action; /**< enum dp_aux_request_action */
1069 uint8_t length; /**< DP AUX request data length */
1070 uint8_t reserved; /**< For future use */
1071 uint32_t address; /**< DP AUX address */
1072 uint8_t data[16]; /**< DP AUX write data */
1076 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command.
1078 struct dmub_cmd_dp_aux_control_data {
1079 uint8_t instance; /**< AUX instance or DPIA instance */
1080 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */
1081 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */
1082 uint8_t reserved0; /**< For future use */
1083 uint16_t timeout; /**< timeout time in us */
1084 uint16_t reserved1; /**< For future use */
1085 enum aux_channel_type type; /**< enum aux_channel_type */
1086 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */
1090 * Definition of a DMUB_CMD__DP_AUX_ACCESS command.
1092 struct dmub_rb_cmd_dp_aux_access {
1096 struct dmub_cmd_header header;
1098 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command.
1100 struct dmub_cmd_dp_aux_control_data aux_control;
1104 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command.
1106 struct dmub_rb_cmd_outbox1_enable {
1110 struct dmub_cmd_header header;
1112 * enable: 0x0 -> disable outbox1 notification (default value)
1113 * 0x1 -> enable outbox1 notification
1118 /* DP AUX Reply command - OutBox Cmd */
1120 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
1122 struct aux_reply_data {
1128 * Aux reply data length (max: 16 bytes)
1142 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
1144 struct aux_reply_control_data {
1146 * Reserved for future use
1154 * Aux transaction result: definition in enum aux_return_code_type
1164 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command.
1166 struct dmub_rb_cmd_dp_aux_reply {
1170 struct dmub_cmd_header header;
1172 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
1174 struct aux_reply_control_data control;
1176 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
1178 struct aux_reply_data reply_data;
1181 /* DP HPD Notify command - OutBox Cmd */
1191 * DP HPD short pulse
1199 enum dp_hpd_status {
1205 * DP_HPD status high
1211 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command.
1213 struct dp_hpd_data {
1223 * HPD status: only for type: DP_HPD to indicate status
1233 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command.
1235 struct dmub_rb_cmd_dp_hpd_notify {
1239 struct dmub_cmd_header header;
1241 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command.
1243 struct dp_hpd_data hpd_data;
1247 * Command IDs should be treated as stable ABI.
1248 * Do not reuse or modify IDs.
1252 * PSR command sub-types.
1254 enum dmub_cmd_psr_type {
1256 * Set PSR version support.
1258 DMUB_CMD__PSR_SET_VERSION = 0,
1260 * Copy driver-calculated parameters to PSR state.
1262 DMUB_CMD__PSR_COPY_SETTINGS = 1,
1266 DMUB_CMD__PSR_ENABLE = 2,
1271 DMUB_CMD__PSR_DISABLE = 3,
1275 * PSR level is a 16-bit value dicated by driver that
1276 * will enable/disable different functionality.
1278 DMUB_CMD__PSR_SET_LEVEL = 4,
1281 * Forces PSR enabled until an explicit PSR disable call.
1283 DMUB_CMD__PSR_FORCE_STATIC = 5,
1295 * PSR not supported.
1297 PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF,
1301 * enum dmub_cmd_mall_type - MALL commands
1303 enum dmub_cmd_mall_type {
1305 * Allows display refresh from MALL.
1307 DMUB_CMD__MALL_ACTION_ALLOW = 0,
1309 * Disallows display refresh from MALL.
1311 DMUB_CMD__MALL_ACTION_DISALLOW = 1,
1313 * Cursor copy for MALL.
1315 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2,
1317 * Controls DF requests.
1319 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3,
1324 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command.
1326 struct dmub_cmd_psr_copy_settings_data {
1328 * Flags that can be set by driver to change some PSR behaviour.
1330 union dmub_psr_debug_flags debug;
1332 * 16-bit value dicated by driver that will enable/disable different functionality.
1341 * Not used in dmub fw,
1342 * dmub fw will get active opp by reading odm registers.
1347 * Not used in dmub fw,
1348 * dmub fw will get active opp by reading odm registers.
1356 * DIG FE HW instance.
1360 * DIG BE HW instance.
1364 * DP PHY HW instance.
1372 * Determines if SMU optimzations are enabled/disabled.
1374 uint8_t smu_optimizations_en;
1379 uint8_t frame_delay;
1381 * If RFB setup time is greater than the total VBLANK time,
1382 * it is not possible for the sink to capture the video frame
1383 * in the same frame the SDP is sent. In this case,
1384 * the frame capture indication bit should be set and an extra
1385 * static frame should be transmitted to the sink.
1387 uint8_t frame_cap_ind;
1389 * Explicit padding to 4 byte boundary.
1393 * Multi-display optimizations are implemented on certain ASICs.
1395 uint8_t multi_disp_optimizations_en;
1397 * The last possible line SDP may be transmitted without violating
1398 * the RFB setup time or entering the active video frame.
1400 uint16_t init_sdp_deadline;
1402 * Explicit padding to 4 byte boundary.
1406 * Length of each horizontal line in us.
1408 uint32_t line_time_in_us;
1410 * FEC enable status in driver
1412 uint8_t fec_enable_status;
1414 * FEC re-enable delay when PSR exit.
1415 * unit is 100us, range form 0~255(0xFF).
1417 uint8_t fec_enable_delay_in100us;
1419 * PSR control version.
1421 uint8_t cmd_version;
1424 * Panel isntance to identify which psr_state to use
1425 * Currently the support is only for 0 or 1
1429 * Explicit padding to 4 byte boundary.
1435 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command.
1437 struct dmub_rb_cmd_psr_copy_settings {
1441 struct dmub_cmd_header header;
1443 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command.
1445 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data;
1449 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command.
1451 struct dmub_cmd_psr_set_level_data {
1453 * 16-bit value dicated by driver that will enable/disable different functionality.
1457 * PSR control version.
1459 uint8_t cmd_version;
1462 * Panel isntance to identify which psr_state to use
1463 * Currently the support is only for 0 or 1
1469 * Definition of a DMUB_CMD__PSR_SET_LEVEL command.
1471 struct dmub_rb_cmd_psr_set_level {
1475 struct dmub_cmd_header header;
1477 * Definition of a DMUB_CMD__PSR_SET_LEVEL command.
1479 struct dmub_cmd_psr_set_level_data psr_set_level_data;
1482 struct dmub_rb_cmd_psr_enable_data {
1484 * PSR control version.
1486 uint8_t cmd_version;
1489 * Panel isntance to identify which psr_state to use
1490 * Currently the support is only for 0 or 1
1494 * Explicit padding to 4 byte boundary.
1500 * Definition of a DMUB_CMD__PSR_ENABLE command.
1501 * PSR enable/disable is controlled using the sub_type.
1503 struct dmub_rb_cmd_psr_enable {
1507 struct dmub_cmd_header header;
1509 struct dmub_rb_cmd_psr_enable_data data;
1513 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command.
1515 struct dmub_cmd_psr_set_version_data {
1517 * PSR version that FW should implement.
1519 enum psr_version version;
1521 * PSR control version.
1523 uint8_t cmd_version;
1526 * Panel isntance to identify which psr_state to use
1527 * Currently the support is only for 0 or 1
1531 * Explicit padding to 4 byte boundary.
1537 * Definition of a DMUB_CMD__PSR_SET_VERSION command.
1539 struct dmub_rb_cmd_psr_set_version {
1543 struct dmub_cmd_header header;
1545 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command.
1547 struct dmub_cmd_psr_set_version_data psr_set_version_data;
1550 struct dmub_cmd_psr_force_static_data {
1552 * PSR control version.
1554 uint8_t cmd_version;
1557 * Panel isntance to identify which psr_state to use
1558 * Currently the support is only for 0 or 1
1562 * Explicit padding to 4 byte boundary.
1568 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command.
1570 struct dmub_rb_cmd_psr_force_static {
1574 struct dmub_cmd_header header;
1576 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command.
1578 struct dmub_cmd_psr_force_static_data psr_force_static_data;
1582 * Set of HW components that can be locked.
1584 * Note: If updating with more HW components, fields
1585 * in dmub_inbox0_cmd_lock_hw must be updated to match.
1587 union dmub_hw_lock_flags {
1589 * Set of HW components that can be locked.
1593 * Lock/unlock OTG master update lock.
1595 uint8_t lock_pipe : 1;
1597 * Lock/unlock cursor.
1599 uint8_t lock_cursor : 1;
1601 * Lock/unlock global update lock.
1603 uint8_t lock_dig : 1;
1605 * Triple buffer lock requires additional hw programming to usual OTG master lock.
1607 uint8_t triple_buffer_lock : 1;
1611 * Union for HW Lock flags.
1617 * Instances of HW to be locked.
1619 * Note: If updating with more HW components, fields
1620 * in dmub_inbox0_cmd_lock_hw must be updated to match.
1622 struct dmub_hw_lock_inst_flags {
1624 * OTG HW instance for OTG master update lock.
1628 * OPP instance for cursor lock.
1632 * OTG HW instance for global update lock.
1633 * TODO: Remove, and re-use otg_inst.
1637 * Explicit pad to 4 byte boundary.
1643 * Clients that can acquire the HW Lock Manager.
1645 * Note: If updating with more clients, fields in
1646 * dmub_inbox0_cmd_lock_hw must be updated to match.
1648 enum hw_lock_client {
1650 * Driver is the client of HW Lock Manager.
1652 HW_LOCK_CLIENT_DRIVER = 0,
1656 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF,
1660 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command.
1662 struct dmub_cmd_lock_hw_data {
1664 * Specifies the client accessing HW Lock Manager.
1666 enum hw_lock_client client;
1668 * HW instances to be locked.
1670 struct dmub_hw_lock_inst_flags inst_flags;
1672 * Which components to be locked.
1674 union dmub_hw_lock_flags hw_locks;
1676 * Specifies lock/unlock.
1680 * HW can be unlocked separately from releasing the HW Lock Mgr.
1681 * This flag is set if the client wishes to release the object.
1683 uint8_t should_release;
1685 * Explicit padding to 4 byte boundary.
1691 * Definition of a DMUB_CMD__HW_LOCK command.
1692 * Command is used by driver and FW.
1694 struct dmub_rb_cmd_lock_hw {
1698 struct dmub_cmd_header header;
1700 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command.
1702 struct dmub_cmd_lock_hw_data lock_hw_data;
1706 * ABM command sub-types.
1708 enum dmub_cmd_abm_type {
1710 * Initialize parameters for ABM algorithm.
1711 * Data is passed through an indirect buffer.
1713 DMUB_CMD__ABM_INIT_CONFIG = 0,
1715 * Set OTG and panel HW instance.
1717 DMUB_CMD__ABM_SET_PIPE = 1,
1719 * Set user requested backklight level.
1721 DMUB_CMD__ABM_SET_BACKLIGHT = 2,
1723 * Set ABM operating/aggression level.
1725 DMUB_CMD__ABM_SET_LEVEL = 3,
1727 * Set ambient light level.
1729 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4,
1731 * Enable/disable fractional duty cycle for backlight PWM.
1733 DMUB_CMD__ABM_SET_PWM_FRAC = 5,
1737 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer.
1739 * - Padded explicitly to 32-bit boundary.
1740 * - Must ensure this structure matches the one on driver-side,
1741 * otherwise it won't be aligned.
1743 struct abm_config_table {
1745 * Gamma curve thresholds, used for crgb conversion.
1747 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B
1749 * Gamma curve offsets, used for crgb conversion.
1751 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B
1753 * Gamma curve slopes, used for crgb conversion.
1755 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B
1757 * Custom backlight curve thresholds.
1759 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B
1761 * Custom backlight curve offsets.
1763 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B
1765 * Ambient light thresholds.
1767 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B
1769 * Minimum programmable backlight.
1771 uint16_t min_abm_backlight; // 122B
1773 * Minimum reduction values.
1775 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B
1777 * Maximum reduction values.
1779 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B
1781 * Bright positive gain.
1783 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B
1785 * Dark negative gain.
1787 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B
1791 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B
1795 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B
1799 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B
1803 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B
1807 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B
1811 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B
1813 * Explicit padding to 4 byte boundary.
1815 uint8_t pad3[3]; // 229B
1817 * Backlight ramp reduction.
1819 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B
1821 * Backlight ramp start.
1823 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B
1827 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command.
1829 struct dmub_cmd_abm_set_pipe_data {
1836 * Panel Control HW instance.
1841 * Controls how ABM will interpret a set pipe or set level command.
1843 uint8_t set_pipe_option;
1849 uint8_t ramping_boundary;
1853 * Definition of a DMUB_CMD__ABM_SET_PIPE command.
1855 struct dmub_rb_cmd_abm_set_pipe {
1859 struct dmub_cmd_header header;
1862 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command.
1864 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data;
1868 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command.
1870 struct dmub_cmd_abm_set_backlight_data {
1872 * Number of frames to ramp to backlight user level.
1874 uint32_t frame_ramp;
1877 * Requested backlight level from user.
1879 uint32_t backlight_user_level;
1882 * ABM control version.
1887 * Panel Control HW instance mask.
1888 * Bit 0 is Panel Control HW instance 0.
1889 * Bit 1 is Panel Control HW instance 1.
1894 * Explicit padding to 4 byte boundary.
1900 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command.
1902 struct dmub_rb_cmd_abm_set_backlight {
1906 struct dmub_cmd_header header;
1909 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command.
1911 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data;
1915 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command.
1917 struct dmub_cmd_abm_set_level_data {
1919 * Set current ABM operating/aggression level.
1924 * ABM control version.
1929 * Panel Control HW instance mask.
1930 * Bit 0 is Panel Control HW instance 0.
1931 * Bit 1 is Panel Control HW instance 1.
1936 * Explicit padding to 4 byte boundary.
1942 * Definition of a DMUB_CMD__ABM_SET_LEVEL command.
1944 struct dmub_rb_cmd_abm_set_level {
1948 struct dmub_cmd_header header;
1951 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command.
1953 struct dmub_cmd_abm_set_level_data abm_set_level_data;
1957 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
1959 struct dmub_cmd_abm_set_ambient_level_data {
1961 * Ambient light sensor reading from OS.
1963 uint32_t ambient_lux;
1966 * ABM control version.
1971 * Panel Control HW instance mask.
1972 * Bit 0 is Panel Control HW instance 0.
1973 * Bit 1 is Panel Control HW instance 1.
1978 * Explicit padding to 4 byte boundary.
1984 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
1986 struct dmub_rb_cmd_abm_set_ambient_level {
1990 struct dmub_cmd_header header;
1993 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
1995 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data;
1999 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command.
2001 struct dmub_cmd_abm_set_pwm_frac_data {
2003 * Enable/disable fractional duty cycle for backlight PWM.
2004 * TODO: Convert to uint8_t.
2006 uint32_t fractional_pwm;
2009 * ABM control version.
2014 * Panel Control HW instance mask.
2015 * Bit 0 is Panel Control HW instance 0.
2016 * Bit 1 is Panel Control HW instance 1.
2021 * Explicit padding to 4 byte boundary.
2027 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command.
2029 struct dmub_rb_cmd_abm_set_pwm_frac {
2033 struct dmub_cmd_header header;
2036 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command.
2038 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data;
2042 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command.
2044 struct dmub_cmd_abm_init_config_data {
2046 * Location of indirect buffer used to pass init data to ABM.
2048 union dmub_addr src;
2051 * Indirect buffer length.
2057 * ABM control version.
2062 * Panel Control HW instance mask.
2063 * Bit 0 is Panel Control HW instance 0.
2064 * Bit 1 is Panel Control HW instance 1.
2069 * Explicit padding to 4 byte boundary.
2075 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command.
2077 struct dmub_rb_cmd_abm_init_config {
2081 struct dmub_cmd_header header;
2084 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command.
2086 struct dmub_cmd_abm_init_config_data abm_init_config_data;
2090 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command.
2092 struct dmub_cmd_query_feature_caps_data {
2094 * DMUB feature capabilities.
2095 * After DMUB init, driver will query FW capabilities prior to enabling certain features.
2097 struct dmub_feature_caps feature_caps;
2101 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command.
2103 struct dmub_rb_cmd_query_feature_caps {
2107 struct dmub_cmd_header header;
2109 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command.
2111 struct dmub_cmd_query_feature_caps_data query_feature_caps_data;
2114 struct dmub_optc_state {
2115 uint32_t v_total_max;
2116 uint32_t v_total_min;
2117 uint32_t v_total_mid;
2118 uint32_t v_total_mid_frame_num;
2120 uint32_t enable_manual_trigger;
2121 uint32_t clear_force_vsync;
2124 struct dmub_rb_cmd_drr_update {
2125 struct dmub_cmd_header header;
2126 struct dmub_optc_state dmub_optc_state_req;
2130 * enum dmub_cmd_panel_cntl_type - Panel control command.
2132 enum dmub_cmd_panel_cntl_type {
2134 * Initializes embedded panel hardware blocks.
2136 DMUB_CMD__PANEL_CNTL_HW_INIT = 0,
2138 * Queries backlight info for the embedded panel.
2140 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1,
2144 * struct dmub_cmd_panel_cntl_data - Panel control data.
2146 struct dmub_cmd_panel_cntl_data {
2147 uint32_t inst; /**< panel instance */
2148 uint32_t current_backlight; /* in/out */
2149 uint32_t bl_pwm_cntl; /* in/out */
2150 uint32_t bl_pwm_period_cntl; /* in/out */
2151 uint32_t bl_pwm_ref_div1; /* in/out */
2152 uint8_t is_backlight_on : 1; /* in/out */
2153 uint8_t is_powered_on : 1; /* in/out */
2157 * struct dmub_rb_cmd_panel_cntl - Panel control command.
2159 struct dmub_rb_cmd_panel_cntl {
2160 struct dmub_cmd_header header; /**< header */
2161 struct dmub_cmd_panel_cntl_data data; /**< payload */
2165 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
2167 struct dmub_cmd_lvtma_control_data {
2168 uint8_t uc_pwr_action; /**< LVTMA_ACTION */
2169 uint8_t reserved_0[3]; /**< For future use */
2170 uint8_t panel_inst; /**< LVTMA control instance */
2171 uint8_t reserved_1[3]; /**< For future use */
2175 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
2177 struct dmub_rb_cmd_lvtma_control {
2181 struct dmub_cmd_header header;
2183 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
2185 struct dmub_cmd_lvtma_control_data data;
2189 * Maximum number of bytes a chunk sent to DMUB for parsing
2191 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8
2194 * Represent a chunk of CEA blocks sent to DMUB for parsing
2196 struct dmub_cmd_send_edid_cea {
2197 uint16_t offset; /**< offset into the CEA block */
2198 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */
2199 uint16_t total_length; /**< total length of the CEA block */
2200 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */
2201 uint8_t pad[3]; /**< padding and for future expansion */
2205 * Result of VSDB parsing from CEA block
2207 struct dmub_cmd_edid_cea_amd_vsdb {
2208 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */
2209 uint8_t freesync_supported; /**< 1 if Freesync is supported */
2210 uint16_t amd_vsdb_version; /**< AMD VSDB version */
2211 uint16_t min_frame_rate; /**< Maximum frame rate */
2212 uint16_t max_frame_rate; /**< Minimum frame rate */
2216 * Result of sending a CEA chunk
2218 struct dmub_cmd_edid_cea_ack {
2219 uint16_t offset; /**< offset of the chunk into the CEA block */
2220 uint8_t success; /**< 1 if this sending of chunk succeeded */
2221 uint8_t pad; /**< padding and for future expansion */
2225 * Specify whether the result is an ACK/NACK or the parsing has finished
2227 enum dmub_cmd_edid_cea_reply_type {
2228 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */
2229 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */
2233 * Definition of a DMUB_CMD__EDID_CEA command.
2235 struct dmub_rb_cmd_edid_cea {
2236 struct dmub_cmd_header header; /**< Command header */
2237 union dmub_cmd_edid_cea_data {
2238 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */
2239 struct dmub_cmd_edid_cea_output { /**< output with results */
2240 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */
2242 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb;
2243 struct dmub_cmd_edid_cea_ack ack;
2245 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */
2246 } data; /**< Command data */
2251 * union dmub_rb_cmd - DMUB inbox command.
2254 struct dmub_rb_cmd_lock_hw lock_hw;
2256 * Elements shared with all commands.
2258 struct dmub_rb_cmd_common cmd_common;
2260 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command.
2262 struct dmub_rb_cmd_read_modify_write read_modify_write;
2264 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command.
2266 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq;
2268 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command.
2270 struct dmub_rb_cmd_burst_write burst_write;
2272 * Definition of a DMUB_CMD__REG_REG_WAIT command.
2274 struct dmub_rb_cmd_reg_wait reg_wait;
2276 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command.
2278 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control;
2280 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command.
2282 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock;
2284 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command.
2286 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating;
2288 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command.
2290 struct dmub_rb_cmd_dpphy_init dpphy_init;
2292 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command.
2294 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control;
2296 * Definition of a DMUB_CMD__PSR_SET_VERSION command.
2298 struct dmub_rb_cmd_psr_set_version psr_set_version;
2300 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command.
2302 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings;
2304 * Definition of a DMUB_CMD__PSR_ENABLE command.
2306 struct dmub_rb_cmd_psr_enable psr_enable;
2308 * Definition of a DMUB_CMD__PSR_SET_LEVEL command.
2310 struct dmub_rb_cmd_psr_set_level psr_set_level;
2312 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command.
2314 struct dmub_rb_cmd_psr_force_static psr_force_static;
2316 * Definition of a DMUB_CMD__PLAT_54186_WA command.
2318 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa;
2320 * Definition of a DMUB_CMD__MALL command.
2322 struct dmub_rb_cmd_mall mall;
2324 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command.
2326 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore;
2329 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command.
2331 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks;
2334 * Definition of DMUB_CMD__PANEL_CNTL commands.
2336 struct dmub_rb_cmd_panel_cntl panel_cntl;
2338 * Definition of a DMUB_CMD__ABM_SET_PIPE command.
2340 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe;
2343 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command.
2345 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight;
2348 * Definition of a DMUB_CMD__ABM_SET_LEVEL command.
2350 struct dmub_rb_cmd_abm_set_level abm_set_level;
2353 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
2355 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level;
2358 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command.
2360 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac;
2363 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command.
2365 struct dmub_rb_cmd_abm_init_config abm_init_config;
2368 * Definition of a DMUB_CMD__DP_AUX_ACCESS command.
2370 struct dmub_rb_cmd_dp_aux_access dp_aux_access;
2373 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command.
2375 struct dmub_rb_cmd_outbox1_enable outbox1_enable;
2378 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command.
2380 struct dmub_rb_cmd_query_feature_caps query_feature_caps;
2381 struct dmub_rb_cmd_drr_update drr_update;
2383 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
2385 struct dmub_rb_cmd_lvtma_control lvtma_control;
2387 * Definition of a DMUB_CMD__EDID_CEA command.
2389 struct dmub_rb_cmd_edid_cea edid_cea;
2393 * union dmub_rb_out_cmd - Outbox command
2395 union dmub_rb_out_cmd {
2397 * Parameters common to every command.
2399 struct dmub_rb_cmd_common cmd_common;
2401 * AUX reply command.
2403 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply;
2405 * HPD notify command.
2407 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify;
2412 //==============================================================================
2413 //</DMUB_CMD>===================================================================
2414 //==============================================================================
2415 //< DMUB_RB>====================================================================
2416 //==============================================================================
2418 #if defined(__cplusplus)
2423 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer
2425 struct dmub_rb_init_params {
2426 void *ctx; /**< Caller provided context pointer */
2427 void *base_address; /**< CPU base address for ring's data */
2428 uint32_t capacity; /**< Ringbuffer capacity in bytes */
2429 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */
2430 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */
2434 * struct dmub_rb - Inbox or outbox DMUB ringbuffer
2437 void *base_address; /**< CPU address for the ring's data */
2438 uint32_t rptr; /**< Read pointer for consumer in bytes */
2439 uint32_t wrpt; /**< Write pointer for producer in bytes */
2440 uint32_t capacity; /**< Ringbuffer capacity in bytes */
2442 void *ctx; /**< Caller provided context pointer */
2443 void *dmub; /**< Pointer to the DMUB interface */
2447 * @brief Checks if the ringbuffer is empty.
2449 * @param rb DMUB Ringbuffer
2450 * @return true if empty
2451 * @return false otherwise
2453 static inline bool dmub_rb_empty(struct dmub_rb *rb)
2455 return (rb->wrpt == rb->rptr);
2459 * @brief Checks if the ringbuffer is full
2461 * @param rb DMUB Ringbuffer
2462 * @return true if full
2463 * @return false otherwise
2465 static inline bool dmub_rb_full(struct dmub_rb *rb)
2467 uint32_t data_count;
2469 if (rb->wrpt >= rb->rptr)
2470 data_count = rb->wrpt - rb->rptr;
2472 data_count = rb->capacity - (rb->rptr - rb->wrpt);
2474 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE));
2478 * @brief Pushes a command into the ringbuffer
2480 * @param rb DMUB ringbuffer
2481 * @param cmd The command to push
2482 * @return true if the ringbuffer was not full
2483 * @return false otherwise
2485 static inline bool dmub_rb_push_front(struct dmub_rb *rb,
2486 const union dmub_rb_cmd *cmd)
2488 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt;
2489 const uint8_t *src = (const uint8_t *)cmd;
2491 if (dmub_rb_full(rb))
2495 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE);
2497 rb->wrpt += DMUB_RB_CMD_SIZE;
2499 if (rb->wrpt >= rb->capacity)
2500 rb->wrpt %= rb->capacity;
2506 * @brief Pushes a command into the DMUB outbox ringbuffer
2508 * @param rb DMUB outbox ringbuffer
2509 * @param cmd Outbox command
2510 * @return true if not full
2511 * @return false otherwise
2513 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb,
2514 const union dmub_rb_out_cmd *cmd)
2516 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt;
2517 const uint8_t *src = (const uint8_t *)cmd;
2519 if (dmub_rb_full(rb))
2522 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE);
2524 rb->wrpt += DMUB_RB_CMD_SIZE;
2526 if (rb->wrpt >= rb->capacity)
2527 rb->wrpt %= rb->capacity;
2533 * @brief Returns the next unprocessed command in the ringbuffer.
2535 * @param rb DMUB ringbuffer
2536 * @param cmd The command to return
2537 * @return true if not empty
2538 * @return false otherwise
2540 static inline bool dmub_rb_front(struct dmub_rb *rb,
2541 union dmub_rb_cmd **cmd)
2543 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr;
2545 if (dmub_rb_empty(rb))
2548 *cmd = (union dmub_rb_cmd *)rb_cmd;
2554 * @brief Determines the next ringbuffer offset.
2556 * @param rb DMUB inbox ringbuffer
2557 * @param num_cmds Number of commands
2558 * @param next_rptr The next offset in the ringbuffer
2560 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb,
2562 uint32_t *next_rptr)
2564 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds;
2566 if (*next_rptr >= rb->capacity)
2567 *next_rptr %= rb->capacity;
2571 * @brief Returns a pointer to a command in the inbox.
2573 * @param rb DMUB inbox ringbuffer
2574 * @param cmd The inbox command to return
2575 * @param rptr The ringbuffer offset
2576 * @return true if not empty
2577 * @return false otherwise
2579 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb,
2580 union dmub_rb_cmd **cmd,
2583 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr;
2585 if (dmub_rb_empty(rb))
2588 *cmd = (union dmub_rb_cmd *)rb_cmd;
2594 * @brief Returns the next unprocessed command in the outbox.
2596 * @param rb DMUB outbox ringbuffer
2597 * @param cmd The outbox command to return
2598 * @return true if not empty
2599 * @return false otherwise
2601 static inline bool dmub_rb_out_front(struct dmub_rb *rb,
2602 union dmub_rb_out_cmd *cmd)
2604 const uint8_t *src = (const uint8_t *)(rb->base_address) + rb->rptr;
2605 uint8_t *dst = (uint8_t *)cmd;
2607 if (dmub_rb_empty(rb))
2611 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE);
2617 * @brief Removes the front entry in the ringbuffer.
2619 * @param rb DMUB ringbuffer
2620 * @return true if the command was removed
2621 * @return false if there were no commands
2623 static inline bool dmub_rb_pop_front(struct dmub_rb *rb)
2625 if (dmub_rb_empty(rb))
2628 rb->rptr += DMUB_RB_CMD_SIZE;
2630 if (rb->rptr >= rb->capacity)
2631 rb->rptr %= rb->capacity;
2637 * @brief Flushes commands in the ringbuffer to framebuffer memory.
2639 * Avoids a race condition where DMCUB accesses memory while
2640 * there are still writes in flight to framebuffer.
2642 * @param rb DMUB ringbuffer
2644 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb)
2646 uint8_t buf[DMUB_RB_CMD_SIZE];
2647 uint32_t rptr = rb->rptr;
2648 uint32_t wptr = rb->wrpt;
2650 while (rptr != wptr) {
2651 const uint8_t *data = (const uint8_t *)rb->base_address + rptr;
2653 dmub_memcpy(buf, data, DMUB_RB_CMD_SIZE);
2655 rptr += DMUB_RB_CMD_SIZE;
2656 if (rptr >= rb->capacity)
2657 rptr %= rb->capacity;
2662 * @brief Initializes a DMCUB ringbuffer
2664 * @param rb DMUB ringbuffer
2665 * @param init_params initial configuration for the ringbuffer
2667 static inline void dmub_rb_init(struct dmub_rb *rb,
2668 struct dmub_rb_init_params *init_params)
2670 rb->base_address = init_params->base_address;
2671 rb->capacity = init_params->capacity;
2672 rb->rptr = init_params->read_ptr;
2673 rb->wrpt = init_params->write_ptr;
2677 * @brief Copies output data from in/out commands into the given command.
2679 * @param rb DMUB ringbuffer
2680 * @param cmd Command to copy data into
2682 static inline void dmub_rb_get_return_data(struct dmub_rb *rb,
2683 union dmub_rb_cmd *cmd)
2685 // Copy rb entry back into command
2686 uint8_t *rd_ptr = (rb->rptr == 0) ?
2687 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE :
2688 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE;
2690 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE);
2693 #if defined(__cplusplus)
2697 //==============================================================================
2698 //</DMUB_RB>====================================================================
2699 //==============================================================================
2701 #endif /* _DMUB_CMD_H_ */