2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
29 #if defined(_TEST_HARNESS) || defined(FPGA_USB4)
30 #include "dmub_fw_types.h"
31 #include "include_legacy/atomfirmware.h"
33 #if defined(_TEST_HARNESS)
38 #include <asm/byteorder.h>
39 #include <linux/types.h>
40 #include <linux/string.h>
41 #include <linux/delay.h>
44 #include "atomfirmware.h"
46 #endif // defined(_TEST_HARNESS) || defined(FPGA_USB4)
48 /* Firmware versioning. */
49 #ifdef DMUB_EXPOSE_VERSION
50 #define DMUB_FW_VERSION_GIT_HASH 0xeb3203315
51 #define DMUB_FW_VERSION_MAJOR 0
52 #define DMUB_FW_VERSION_MINOR 0
53 #define DMUB_FW_VERSION_REVISION 68
54 #define DMUB_FW_VERSION_TEST 0
55 #define DMUB_FW_VERSION_VBIOS 0
56 #define DMUB_FW_VERSION_HOTFIX 0
57 #define DMUB_FW_VERSION_UCODE (((DMUB_FW_VERSION_MAJOR & 0xFF) << 24) | \
58 ((DMUB_FW_VERSION_MINOR & 0xFF) << 16) | \
59 ((DMUB_FW_VERSION_REVISION & 0xFF) << 8) | \
60 ((DMUB_FW_VERSION_TEST & 0x1) << 7) | \
61 ((DMUB_FW_VERSION_VBIOS & 0x1) << 6) | \
62 (DMUB_FW_VERSION_HOTFIX & 0x3F))
66 //<DMUB_TYPES>==================================================================
67 /* Basic type definitions. */
69 #define __forceinline inline
72 * Flag from driver to indicate that ABM should be disabled gradually
73 * by slowly reversing all backlight programming and pixel compensation.
75 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0
78 * Flag from driver to indicate that ABM should be disabled immediately
79 * and undo all backlight programming and pixel compensation.
81 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255
84 * Flag from driver to indicate that ABM should be disabled immediately
85 * and keep the current backlight programming and pixel compensation.
87 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254
90 * Flag from driver to set the current ABM pipe index or ABM operating level.
92 #define SET_ABM_PIPE_NORMAL 1
95 * Number of ambient light levels in ABM algorithm.
97 #define NUM_AMBI_LEVEL 5
100 * Number of operating/aggression levels in ABM algorithm.
102 #define NUM_AGGR_LEVEL 4
105 * Number of segments in the gamma curve.
107 #define NUM_POWER_FN_SEGS 8
110 * Number of segments in the backlight curve.
112 #define NUM_BL_CURVE_SEGS 16
114 /* Maximum number of streams on any ASIC. */
115 #define DMUB_MAX_STREAMS 6
117 /* Maximum number of planes on any ASIC. */
118 #define DMUB_MAX_PLANES 6
120 /* Trace buffer offset for entry */
121 #define TRACE_BUFFER_ENTRY_OFFSET 16
125 * PSR control version legacy
127 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0
129 * PSR control version with multi edp support
131 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1
135 * ABM control version legacy
137 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0
140 * ABM control version with multi edp support
142 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1
145 * Physical framebuffer address location, 64-bit.
147 #ifndef PHYSICAL_ADDRESS_LOC
148 #define PHYSICAL_ADDRESS_LOC union large_integer
152 * OS/FW agnostic memcpy
155 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes))
159 * OS/FW agnostic memset
162 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes))
165 #if defined(__cplusplus)
170 * OS/FW agnostic udelay
173 #define dmub_udelay(microseconds) udelay(microseconds)
177 * Number of nanoseconds per DMUB tick.
178 * DMCUB_TIMER_CURRENT increments in DMUB ticks, which are 10ns by default.
179 * If DMCUB_TIMER_WINDOW is non-zero this will no longer be true.
181 #define NS_PER_DMUB_TICK 10
184 * union dmub_addr - DMUB physical/virtual 64-bit address.
188 uint32_t low_part; /**< Lower 32 bits */
189 uint32_t high_part; /**< Upper 32 bits */
190 } u; /*<< Low/high bit access */
191 uint64_t quad_part; /*<< 64 bit address */
195 * Flags that can be set by driver to change some PSR behaviour.
197 union dmub_psr_debug_flags {
203 * Enable visual confirm in FW.
205 uint32_t visual_confirm : 1;
207 * Use HW Lock Mgr object to do HW locking in FW.
209 uint32_t use_hw_lock_mgr : 1;
215 uint32_t log_line_nums : 1;
219 * Union for debug flags.
225 * DMUB feature capabilities.
226 * After DMUB init, driver will query FW capabilities prior to enabling certain features.
228 struct dmub_feature_caps {
230 * Max PSR version supported by FW.
236 #if defined(__cplusplus)
240 //==============================================================================
241 //</DMUB_TYPES>=================================================================
242 //==============================================================================
243 //< DMUB_META>==================================================================
244 //==============================================================================
245 #pragma pack(push, 1)
247 /* Magic value for identifying dmub_fw_meta_info */
248 #define DMUB_FW_META_MAGIC 0x444D5542
250 /* Offset from the end of the file to the dmub_fw_meta_info */
251 #define DMUB_FW_META_OFFSET 0x24
254 * struct dmub_fw_meta_info - metadata associated with fw binary
256 * NOTE: This should be considered a stable API. Fields should
257 * not be repurposed or reordered. New fields should be
258 * added instead to extend the structure.
260 * @magic_value: magic value identifying DMUB firmware meta info
261 * @fw_region_size: size of the firmware state region
262 * @trace_buffer_size: size of the tracebuffer region
263 * @fw_version: the firmware version information
264 * @dal_fw: 1 if the firmware is DAL
266 struct dmub_fw_meta_info {
267 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */
268 uint32_t fw_region_size; /**< size of the firmware state region */
269 uint32_t trace_buffer_size; /**< size of the tracebuffer region */
270 uint32_t fw_version; /**< the firmware version information */
271 uint8_t dal_fw; /**< 1 if the firmware is DAL */
272 uint8_t reserved[3]; /**< padding bits */
276 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes
279 struct dmub_fw_meta_info info; /**< metadata info */
280 uint8_t reserved[64]; /**< padding bits */
285 //==============================================================================
286 //< DMUB Trace Buffer>================================================================
287 //==============================================================================
289 * dmub_trace_code_t - firmware trace code, 32-bits
291 typedef uint32_t dmub_trace_code_t;
294 * struct dmcub_trace_buf_entry - Firmware trace entry
296 struct dmcub_trace_buf_entry {
297 dmub_trace_code_t trace_code; /**< trace code for the event */
298 uint32_t tick_count; /**< the tick count at time of trace */
299 uint32_t param0; /**< trace defined parameter 0 */
300 uint32_t param1; /**< trace defined parameter 1 */
303 //==============================================================================
304 //< DMUB_STATUS>================================================================
305 //==============================================================================
308 * DMCUB scratch registers can be used to determine firmware status.
309 * Current scratch register usage is as follows:
311 * SCRATCH0: FW Boot Status register
312 * SCRATCH15: FW Boot Options register
316 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0.
318 union dmub_fw_boot_status {
320 uint32_t dal_fw : 1; /**< 1 if DAL FW */
321 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */
322 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */
323 uint32_t restore_required : 1; /**< 1 if driver should call restore */
324 } bits; /**< status bits */
325 uint32_t all; /**< 32-bit access to status bits */
329 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0.
331 enum dmub_fw_boot_status_bit {
332 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */
333 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */
334 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */
335 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */
339 * union dmub_fw_boot_options - Boot option definitions for SCRATCH15
341 union dmub_fw_boot_options {
343 uint32_t pemu_env : 1; /**< 1 if PEMU */
344 uint32_t fpga_env : 1; /**< 1 if FPGA */
345 uint32_t optimized_init : 1; /**< 1 if optimized init */
346 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */
347 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */
348 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */
349 #ifdef CONFIG_DRM_AMD_DC_DCN3_1
350 uint32_t z10_disable: 1; /**< 1 to disable z10 */
352 uint32_t reserved_unreleased: 1; /**< reserved for an unreleased feature */
354 uint32_t reserved : 25; /**< reserved */
355 } bits; /**< boot bits */
356 uint32_t all; /**< 32-bit access to bits */
359 enum dmub_fw_boot_options_bit {
360 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */
361 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */
362 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */
365 //==============================================================================
366 //</DMUB_STATUS>================================================================
367 //==============================================================================
368 //< DMUB_VBIOS>=================================================================
369 //==============================================================================
372 * enum dmub_cmd_vbios_type - VBIOS commands.
374 * Command IDs should be treated as stable ABI.
375 * Do not reuse or modify IDs.
377 enum dmub_cmd_vbios_type {
379 * Configures the DIG encoder.
381 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0,
385 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1,
387 * Sets the pixel clock/symbol clock.
389 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2,
391 * Enables or disables power gating.
393 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3,
394 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15,
397 //==============================================================================
398 //</DMUB_VBIOS>=================================================================
399 //==============================================================================
400 //< DMUB_GPINT>=================================================================
401 //==============================================================================
404 * The shifts and masks below may alternatively be used to format and read
405 * the command register bits.
408 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF
409 #define DMUB_GPINT_DATA_PARAM_SHIFT 0
411 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF
412 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16
414 #define DMUB_GPINT_DATA_STATUS_MASK 0xF
415 #define DMUB_GPINT_DATA_STATUS_SHIFT 28
422 * Return response for DMUB_GPINT__STOP_FW command.
424 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD
427 * union dmub_gpint_data_register - Format for sending a command via the GPINT.
429 union dmub_gpint_data_register {
431 uint32_t param : 16; /**< 16-bit parameter */
432 uint32_t command_code : 12; /**< GPINT command */
433 uint32_t status : 4; /**< Command status bit */
434 } bits; /**< GPINT bit access */
435 uint32_t all; /**< GPINT 32-bit access */
439 * enum dmub_gpint_command - GPINT command to DMCUB FW
441 * Command IDs should be treated as stable ABI.
442 * Do not reuse or modify IDs.
444 enum dmub_gpint_command {
446 * Invalid command, ignored.
448 DMUB_GPINT__INVALID_COMMAND = 0,
450 * DESC: Queries the firmware version.
451 * RETURN: Firmware version.
453 DMUB_GPINT__GET_FW_VERSION = 1,
455 * DESC: Halts the firmware.
456 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted
458 DMUB_GPINT__STOP_FW = 2,
460 * DESC: Get PSR state from FW.
461 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value.
463 DMUB_GPINT__GET_PSR_STATE = 7,
465 * DESC: Notifies DMCUB of the currently active streams.
466 * ARGS: Stream mask, 1 bit per active stream index.
468 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8,
470 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value.
471 * ARGS: We can measure residency from various points. The argument will specify the residency mode.
472 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY.
473 * RETURN: PSR residency in milli-percent.
475 DMUB_GPINT__PSR_RESIDENCY = 9,
479 * INBOX0 generic command definition
481 union dmub_inbox0_cmd_common {
483 uint32_t command_code: 8; /**< INBOX0 command code */
484 uint32_t param: 24; /**< 24-bit parameter */
490 * INBOX0 hw_lock command definition
492 union dmub_inbox0_cmd_lock_hw {
494 uint32_t command_code: 8;
496 /* NOTE: Must be have enough bits to match: enum hw_lock_client */
497 uint32_t hw_lock_client: 1;
499 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */
500 uint32_t otg_inst: 3;
501 uint32_t opp_inst: 3;
502 uint32_t dig_inst: 3;
504 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */
505 uint32_t lock_pipe: 1;
506 uint32_t lock_cursor: 1;
507 uint32_t lock_dig: 1;
508 uint32_t triple_buffer_lock: 1;
510 uint32_t lock: 1; /**< Lock */
511 uint32_t should_release: 1; /**< Release */
512 uint32_t reserved: 8; /**< Reserved for extending more clients, HW, etc. */
517 union dmub_inbox0_data_register {
518 union dmub_inbox0_cmd_common inbox0_cmd_common;
519 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw;
522 enum dmub_inbox0_command {
524 * DESC: Invalid command, ignored.
526 DMUB_INBOX0_CMD__INVALID_COMMAND = 0,
528 * DESC: Notification to acquire/release HW lock
531 DMUB_INBOX0_CMD__HW_LOCK = 1,
533 //==============================================================================
534 //</DMUB_GPINT>=================================================================
535 //==============================================================================
536 //< DMUB_CMD>===================================================================
537 //==============================================================================
540 * Size in bytes of each DMUB command.
542 #define DMUB_RB_CMD_SIZE 64
545 * Maximum number of items in the DMUB ringbuffer.
547 #define DMUB_RB_MAX_ENTRY 128
550 * Ringbuffer size in bytes.
552 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY)
555 * REG_SET mask for reg offload.
557 #define REG_SET_MASK 0xFFFF
560 * enum dmub_cmd_type - DMUB inbox command.
562 * Command IDs should be treated as stable ABI.
563 * Do not reuse or modify IDs.
571 * Read modify write register sequence offload.
573 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1,
575 * Field update register sequence offload.
577 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2,
579 * Burst write sequence offload.
581 DMUB_CMD__REG_SEQ_BURST_WRITE = 3,
583 * Reg wait sequence offload.
585 DMUB_CMD__REG_REG_WAIT = 4,
587 * Workaround to avoid HUBP underflow during NV12 playback.
589 DMUB_CMD__PLAT_54186_WA = 5,
591 * Command type used to query FW feature caps.
593 DMUB_CMD__QUERY_FEATURE_CAPS = 6,
595 * Command type used for all PSR commands.
599 * Command type used for all MALL commands.
603 * Command type used for all ABM commands.
607 * Command type used for HW locking in FW.
609 DMUB_CMD__HW_LOCK = 69,
611 * Command type used to access DP AUX.
613 DMUB_CMD__DP_AUX_ACCESS = 70,
615 * Command type used for OUTBOX1 notification enable
617 DMUB_CMD__OUTBOX1_ENABLE = 71,
618 #ifdef CONFIG_DRM_AMD_DC_DCN3_1
620 * Command type used for all idle optimization commands.
622 DMUB_CMD__IDLE_OPT = 72,
624 * Command type used for all clock manager commands.
626 DMUB_CMD__CLK_MGR = 73,
628 * Command type used for all panel control commands.
630 DMUB_CMD__PANEL_CNTL = 74,
633 * Command type used for all VBIOS interface commands.
635 DMUB_CMD__VBIOS = 128,
639 * enum dmub_out_cmd_type - DMUB outbox commands.
641 enum dmub_out_cmd_type {
643 * Invalid outbox command, ignored.
645 DMUB_OUT_CMD__NULL = 0,
647 * Command type used for DP AUX Reply data notification
649 DMUB_OUT_CMD__DP_AUX_REPLY = 1,
652 #pragma pack(push, 1)
655 * struct dmub_cmd_header - Common command header fields.
657 struct dmub_cmd_header {
658 unsigned int type : 8; /**< command type */
659 unsigned int sub_type : 8; /**< command sub type */
660 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */
661 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */
662 unsigned int reserved0 : 6; /**< reserved bits */
663 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */
664 unsigned int reserved1 : 2; /**< reserved bits */
668 * struct dmub_cmd_read_modify_write_sequence - Read modify write
670 * 60 payload bytes can hold up to 5 sets of read modify writes,
671 * each take 3 dwords.
673 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence)
675 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case
676 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write
678 struct dmub_cmd_read_modify_write_sequence {
679 uint32_t addr; /**< register address */
680 uint32_t modify_mask; /**< modify mask */
681 uint32_t modify_value; /**< modify value */
685 * Maximum number of ops in read modify write sequence.
687 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5
690 * struct dmub_cmd_read_modify_write_sequence - Read modify write command.
692 struct dmub_rb_cmd_read_modify_write {
693 struct dmub_cmd_header header; /**< command header */
695 * Read modify write sequence.
697 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX];
701 * Update a register with specified masks and values sequeunce
703 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword
705 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence)
709 * 1. auto-increment register where additional read would update pointer and produce wrong result
710 * 2. toggle a bit without read in the middle
713 struct dmub_cmd_reg_field_update_sequence {
714 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */
715 uint32_t modify_value; /**< value to update with */
719 * Maximum number of ops in field update sequence.
721 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7
724 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command.
726 struct dmub_rb_cmd_reg_field_update_sequence {
727 struct dmub_cmd_header header; /**< command header */
728 uint32_t addr; /**< register address */
730 * Field update sequence.
732 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX];
737 * Maximum number of burst write values.
739 #define DMUB_BURST_WRITE_VALUES__MAX 14
742 * struct dmub_rb_cmd_burst_write - Burst write
744 * support use case such as writing out LUTs.
746 * 60 payload bytes can hold up to 14 values to write to given address
748 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence)
750 struct dmub_rb_cmd_burst_write {
751 struct dmub_cmd_header header; /**< command header */
752 uint32_t addr; /**< register start address */
754 * Burst write register values.
756 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX];
760 * struct dmub_rb_cmd_common - Common command header
762 struct dmub_rb_cmd_common {
763 struct dmub_cmd_header header; /**< command header */
765 * Padding to RB_CMD_SIZE
767 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)];
771 * struct dmub_cmd_reg_wait_data - Register wait data
773 struct dmub_cmd_reg_wait_data {
774 uint32_t addr; /**< Register address */
775 uint32_t mask; /**< Mask for register bits */
776 uint32_t condition_field_value; /**< Value to wait for */
777 uint32_t time_out_us; /**< Time out for reg wait in microseconds */
781 * struct dmub_rb_cmd_reg_wait - Register wait command
783 struct dmub_rb_cmd_reg_wait {
784 struct dmub_cmd_header header; /**< Command header */
785 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */
789 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround
791 * Reprograms surface parameters to avoid underflow.
793 struct dmub_cmd_PLAT_54186_wa {
794 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */
795 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */
796 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */
797 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */
798 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */
800 uint8_t hubp_inst : 4; /**< HUBP instance */
801 uint8_t tmz_surface : 1; /**< TMZ enable or disable */
802 uint8_t immediate :1; /**< Immediate flip */
803 uint8_t vmid : 4; /**< VMID */
804 uint8_t grph_stereo : 1; /**< 1 if stereo */
805 uint32_t reserved : 21; /**< Reserved */
806 } flip_params; /**< Pageflip parameters */
807 uint32_t reserved[9]; /**< Reserved bits */
811 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command
813 struct dmub_rb_cmd_PLAT_54186_wa {
814 struct dmub_cmd_header header; /**< Command header */
815 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */
819 * struct dmub_rb_cmd_mall - MALL command data.
821 struct dmub_rb_cmd_mall {
822 struct dmub_cmd_header header; /**< Common command header */
823 union dmub_addr cursor_copy_src; /**< Cursor copy address */
824 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */
825 uint32_t tmr_delay; /**< Timer delay */
826 uint32_t tmr_scale; /**< Timer scale */
827 uint16_t cursor_width; /**< Cursor width in pixels */
828 uint16_t cursor_pitch; /**< Cursor pitch in pixels */
829 uint16_t cursor_height; /**< Cursor height in pixels */
830 uint8_t cursor_bpp; /**< Cursor bits per pixel */
831 uint8_t debug_bits; /**< Debug bits */
833 uint8_t reserved1; /**< Reserved bits */
834 uint8_t reserved2; /**< Reserved bits */
837 #ifdef CONFIG_DRM_AMD_DC_DCN3_1
840 * enum dmub_cmd_idle_opt_type - Idle optimization command type.
842 enum dmub_cmd_idle_opt_type {
844 * DCN hardware restore.
846 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0,
850 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data.
852 struct dmub_rb_cmd_idle_opt_dcn_restore {
853 struct dmub_cmd_header header; /**< header */
857 * struct dmub_clocks - Clock update notification.
860 uint32_t dispclk_khz; /**< dispclk kHz */
861 uint32_t dppclk_khz; /**< dppclk kHz */
862 uint32_t dcfclk_khz; /**< dcfclk kHz */
863 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */
867 * enum dmub_cmd_clk_mgr_type - Clock manager commands.
869 enum dmub_cmd_clk_mgr_type {
871 * Notify DMCUB of clock update.
873 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0,
877 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification.
879 struct dmub_rb_cmd_clk_mgr_notify_clocks {
880 struct dmub_cmd_header header; /**< header */
881 struct dmub_clocks clocks; /**< clock data */
885 * struct dmub_cmd_digx_encoder_control_data - Encoder control data.
887 struct dmub_cmd_digx_encoder_control_data {
888 union dig_encoder_control_parameters_v1_5 dig; /**< payload */
892 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command.
894 struct dmub_rb_cmd_digx_encoder_control {
895 struct dmub_cmd_header header; /**< header */
896 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */
900 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data.
902 struct dmub_cmd_set_pixel_clock_data {
903 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */
907 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command.
909 struct dmub_rb_cmd_set_pixel_clock {
910 struct dmub_cmd_header header; /**< header */
911 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */
915 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating.
917 struct dmub_cmd_enable_disp_power_gating_data {
918 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */
922 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command.
924 struct dmub_rb_cmd_enable_disp_power_gating {
925 struct dmub_cmd_header header; /**< header */
926 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */
930 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control.
932 struct dmub_dig_transmitter_control_data_v1_7 {
933 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */
934 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */
936 uint8_t digmode; /**< enum atom_encode_mode_def */
937 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */
939 uint8_t lanenum; /**< Number of lanes */
941 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */
943 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */
944 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */
945 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */
946 uint8_t reserved0; /**< For future use */
947 uint8_t reserved1; /**< For future use */
948 uint8_t reserved2[3]; /**< For future use */
949 uint32_t reserved3[11]; /**< For future use */
953 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data.
955 union dmub_cmd_dig1_transmitter_control_data {
956 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */
957 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */
961 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command.
963 struct dmub_rb_cmd_dig1_transmitter_control {
964 struct dmub_cmd_header header; /**< header */
965 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */
969 * struct dmub_rb_cmd_dpphy_init - DPPHY init.
971 struct dmub_rb_cmd_dpphy_init {
972 struct dmub_cmd_header header; /**< header */
973 uint8_t reserved[60]; /**< reserved bits */
977 * enum dp_aux_request_action - DP AUX request command listing.
979 * 4 AUX request command bits are shifted to high nibble.
981 enum dp_aux_request_action {
982 /** I2C-over-AUX write request */
983 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00,
984 /** I2C-over-AUX read request */
985 DP_AUX_REQ_ACTION_I2C_READ = 0x10,
986 /** I2C-over-AUX write status request */
987 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20,
988 /** I2C-over-AUX write request with MOT=1 */
989 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40,
990 /** I2C-over-AUX read request with MOT=1 */
991 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50,
992 /** I2C-over-AUX write status request with MOT=1 */
993 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60,
994 /** Native AUX write request */
995 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80,
996 /** Native AUX read request */
997 DP_AUX_REQ_ACTION_DPCD_READ = 0x90
1001 * enum aux_return_code_type - DP AUX process return code listing.
1003 enum aux_return_code_type {
1004 /** AUX process succeeded */
1005 AUX_RET_SUCCESS = 0,
1006 /** AUX process failed with unknown reason */
1007 AUX_RET_ERROR_UNKNOWN,
1008 /** AUX process completed with invalid reply */
1009 AUX_RET_ERROR_INVALID_REPLY,
1010 /** AUX process timed out */
1011 AUX_RET_ERROR_TIMEOUT,
1012 /** HPD was low during AUX process */
1013 AUX_RET_ERROR_HPD_DISCON,
1014 /** Failed to acquire AUX engine */
1015 AUX_RET_ERROR_ENGINE_ACQUIRE,
1016 /** AUX request not supported */
1017 AUX_RET_ERROR_INVALID_OPERATION,
1018 /** AUX process not available */
1019 AUX_RET_ERROR_PROTOCOL_ERROR,
1023 * enum aux_channel_type - DP AUX channel type listing.
1025 enum aux_channel_type {
1026 /** AUX thru Legacy DP AUX */
1027 AUX_CHANNEL_LEGACY_DDC,
1028 /** AUX thru DPIA DP tunneling */
1033 * struct aux_transaction_parameters - DP AUX request transaction data
1035 struct aux_transaction_parameters {
1036 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */
1037 uint8_t action; /**< enum dp_aux_request_action */
1038 uint8_t length; /**< DP AUX request data length */
1039 uint8_t reserved; /**< For future use */
1040 uint32_t address; /**< DP AUX address */
1041 uint8_t data[16]; /**< DP AUX write data */
1045 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command.
1047 struct dmub_cmd_dp_aux_control_data {
1048 uint8_t instance; /**< AUX instance or DPIA instance */
1049 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */
1050 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */
1051 uint8_t reserved0; /**< For future use */
1052 uint16_t timeout; /**< timeout time in us */
1053 uint16_t reserved1; /**< For future use */
1054 enum aux_channel_type type; /**< enum aux_channel_type */
1055 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */
1059 * Definition of a DMUB_CMD__DP_AUX_ACCESS command.
1061 struct dmub_rb_cmd_dp_aux_access {
1065 struct dmub_cmd_header header;
1067 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command.
1069 struct dmub_cmd_dp_aux_control_data aux_control;
1073 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command.
1075 struct dmub_rb_cmd_outbox1_enable {
1079 struct dmub_cmd_header header;
1081 * enable: 0x0 -> disable outbox1 notification (default value)
1082 * 0x1 -> enable outbox1 notification
1087 /* DP AUX Reply command - OutBox Cmd */
1089 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
1091 struct aux_reply_data {
1097 * Aux reply data length (max: 16 bytes)
1111 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
1113 struct aux_reply_control_data {
1115 * Reserved for future use
1123 * Aux transaction result: definition in enum aux_return_code_type
1133 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command.
1135 struct dmub_rb_cmd_dp_aux_reply {
1139 struct dmub_cmd_header header;
1141 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
1143 struct aux_reply_control_data control;
1145 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
1147 struct aux_reply_data reply_data;
1150 /* DP HPD Notify command - OutBox Cmd */
1160 * DP HPD short pulse
1168 enum dp_hpd_status {
1174 * DP_HPD status high
1180 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command.
1182 struct dp_hpd_data {
1192 * HPD status: only for type: DP_HPD to indicate status
1202 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command.
1204 struct dmub_rb_cmd_dp_hpd_notify {
1208 struct dmub_cmd_header header;
1210 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command.
1212 struct dp_hpd_data hpd_data;
1216 * Command IDs should be treated as stable ABI.
1217 * Do not reuse or modify IDs.
1221 * PSR command sub-types.
1223 enum dmub_cmd_psr_type {
1225 * Set PSR version support.
1227 DMUB_CMD__PSR_SET_VERSION = 0,
1229 * Copy driver-calculated parameters to PSR state.
1231 DMUB_CMD__PSR_COPY_SETTINGS = 1,
1235 DMUB_CMD__PSR_ENABLE = 2,
1240 DMUB_CMD__PSR_DISABLE = 3,
1244 * PSR level is a 16-bit value dicated by driver that
1245 * will enable/disable different functionality.
1247 DMUB_CMD__PSR_SET_LEVEL = 4,
1250 * Forces PSR enabled until an explicit PSR disable call.
1252 DMUB_CMD__PSR_FORCE_STATIC = 5,
1264 * PSR not supported.
1266 PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF,
1270 * enum dmub_cmd_mall_type - MALL commands
1272 enum dmub_cmd_mall_type {
1274 * Allows display refresh from MALL.
1276 DMUB_CMD__MALL_ACTION_ALLOW = 0,
1278 * Disallows display refresh from MALL.
1280 DMUB_CMD__MALL_ACTION_DISALLOW = 1,
1282 * Cursor copy for MALL.
1284 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2,
1286 * Controls DF requests.
1288 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3,
1293 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command.
1295 struct dmub_cmd_psr_copy_settings_data {
1297 * Flags that can be set by driver to change some PSR behaviour.
1299 union dmub_psr_debug_flags debug;
1301 * 16-bit value dicated by driver that will enable/disable different functionality.
1310 * Not used in dmub fw,
1311 * dmub fw will get active opp by reading odm registers.
1316 * Not used in dmub fw,
1317 * dmub fw will get active opp by reading odm registers.
1325 * DIG FE HW instance.
1329 * DIG BE HW instance.
1333 * DP PHY HW instance.
1341 * Determines if SMU optimzations are enabled/disabled.
1343 uint8_t smu_optimizations_en;
1348 uint8_t frame_delay;
1350 * If RFB setup time is greater than the total VBLANK time,
1351 * it is not possible for the sink to capture the video frame
1352 * in the same frame the SDP is sent. In this case,
1353 * the frame capture indication bit should be set and an extra
1354 * static frame should be transmitted to the sink.
1356 uint8_t frame_cap_ind;
1358 * Explicit padding to 4 byte boundary.
1362 * Multi-display optimizations are implemented on certain ASICs.
1364 uint8_t multi_disp_optimizations_en;
1366 * The last possible line SDP may be transmitted without violating
1367 * the RFB setup time or entering the active video frame.
1369 uint16_t init_sdp_deadline;
1371 * Explicit padding to 4 byte boundary.
1375 * Length of each horizontal line in us.
1377 uint32_t line_time_in_us;
1379 * FEC enable status in driver
1381 uint8_t fec_enable_status;
1383 * FEC re-enable delay when PSR exit.
1384 * unit is 100us, range form 0~255(0xFF).
1386 uint8_t fec_enable_delay_in100us;
1388 * PSR control version.
1390 uint8_t cmd_version;
1393 * Panel isntance to identify which psr_state to use
1394 * Currently the support is only for 0 or 1
1400 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command.
1402 struct dmub_rb_cmd_psr_copy_settings {
1406 struct dmub_cmd_header header;
1408 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command.
1410 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data;
1414 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command.
1416 struct dmub_cmd_psr_set_level_data {
1418 * 16-bit value dicated by driver that will enable/disable different functionality.
1422 * PSR control version.
1424 uint8_t cmd_version;
1427 * Panel isntance to identify which psr_state to use
1428 * Currently the support is only for 0 or 1
1434 * Definition of a DMUB_CMD__PSR_SET_LEVEL command.
1436 struct dmub_rb_cmd_psr_set_level {
1440 struct dmub_cmd_header header;
1442 * Definition of a DMUB_CMD__PSR_SET_LEVEL command.
1444 struct dmub_cmd_psr_set_level_data psr_set_level_data;
1447 struct dmub_rb_cmd_psr_enable_data {
1449 * PSR control version.
1451 uint8_t cmd_version;
1454 * Panel isntance to identify which psr_state to use
1455 * Currently the support is only for 0 or 1
1459 * Explicit padding to 4 byte boundary.
1465 * Definition of a DMUB_CMD__PSR_ENABLE command.
1466 * PSR enable/disable is controlled using the sub_type.
1468 struct dmub_rb_cmd_psr_enable {
1472 struct dmub_cmd_header header;
1474 struct dmub_rb_cmd_psr_enable_data data;
1478 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command.
1480 struct dmub_cmd_psr_set_version_data {
1482 * PSR version that FW should implement.
1484 enum psr_version version;
1486 * PSR control version.
1488 uint8_t cmd_version;
1491 * Panel isntance to identify which psr_state to use
1492 * Currently the support is only for 0 or 1
1496 * Explicit padding to 4 byte boundary.
1502 * Definition of a DMUB_CMD__PSR_SET_VERSION command.
1504 struct dmub_rb_cmd_psr_set_version {
1508 struct dmub_cmd_header header;
1510 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command.
1512 struct dmub_cmd_psr_set_version_data psr_set_version_data;
1515 struct dmub_cmd_psr_force_static_data {
1517 * PSR control version.
1519 uint8_t cmd_version;
1522 * Panel isntance to identify which psr_state to use
1523 * Currently the support is only for 0 or 1
1527 * Explicit padding to 4 byte boundary.
1533 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command.
1535 struct dmub_rb_cmd_psr_force_static {
1539 struct dmub_cmd_header header;
1541 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command.
1543 struct dmub_cmd_psr_force_static_data psr_force_static_data;
1547 * Set of HW components that can be locked.
1549 * Note: If updating with more HW components, fields
1550 * in dmub_inbox0_cmd_lock_hw must be updated to match.
1552 union dmub_hw_lock_flags {
1554 * Set of HW components that can be locked.
1558 * Lock/unlock OTG master update lock.
1560 uint8_t lock_pipe : 1;
1562 * Lock/unlock cursor.
1564 uint8_t lock_cursor : 1;
1566 * Lock/unlock global update lock.
1568 uint8_t lock_dig : 1;
1570 * Triple buffer lock requires additional hw programming to usual OTG master lock.
1572 uint8_t triple_buffer_lock : 1;
1576 * Union for HW Lock flags.
1582 * Instances of HW to be locked.
1584 * Note: If updating with more HW components, fields
1585 * in dmub_inbox0_cmd_lock_hw must be updated to match.
1587 struct dmub_hw_lock_inst_flags {
1589 * OTG HW instance for OTG master update lock.
1593 * OPP instance for cursor lock.
1597 * OTG HW instance for global update lock.
1598 * TODO: Remove, and re-use otg_inst.
1602 * Explicit pad to 4 byte boundary.
1608 * Clients that can acquire the HW Lock Manager.
1610 * Note: If updating with more clients, fields in
1611 * dmub_inbox0_cmd_lock_hw must be updated to match.
1613 enum hw_lock_client {
1615 * Driver is the client of HW Lock Manager.
1617 HW_LOCK_CLIENT_DRIVER = 0,
1621 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF,
1625 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command.
1627 struct dmub_cmd_lock_hw_data {
1629 * Specifies the client accessing HW Lock Manager.
1631 enum hw_lock_client client;
1633 * HW instances to be locked.
1635 struct dmub_hw_lock_inst_flags inst_flags;
1637 * Which components to be locked.
1639 union dmub_hw_lock_flags hw_locks;
1641 * Specifies lock/unlock.
1645 * HW can be unlocked separately from releasing the HW Lock Mgr.
1646 * This flag is set if the client wishes to release the object.
1648 uint8_t should_release;
1650 * Explicit padding to 4 byte boundary.
1656 * Definition of a DMUB_CMD__HW_LOCK command.
1657 * Command is used by driver and FW.
1659 struct dmub_rb_cmd_lock_hw {
1663 struct dmub_cmd_header header;
1665 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command.
1667 struct dmub_cmd_lock_hw_data lock_hw_data;
1671 * ABM command sub-types.
1673 enum dmub_cmd_abm_type {
1675 * Initialize parameters for ABM algorithm.
1676 * Data is passed through an indirect buffer.
1678 DMUB_CMD__ABM_INIT_CONFIG = 0,
1680 * Set OTG and panel HW instance.
1682 DMUB_CMD__ABM_SET_PIPE = 1,
1684 * Set user requested backklight level.
1686 DMUB_CMD__ABM_SET_BACKLIGHT = 2,
1688 * Set ABM operating/aggression level.
1690 DMUB_CMD__ABM_SET_LEVEL = 3,
1692 * Set ambient light level.
1694 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4,
1696 * Enable/disable fractional duty cycle for backlight PWM.
1698 DMUB_CMD__ABM_SET_PWM_FRAC = 5,
1702 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer.
1704 * - Padded explicitly to 32-bit boundary.
1705 * - Must ensure this structure matches the one on driver-side,
1706 * otherwise it won't be aligned.
1708 struct abm_config_table {
1710 * Gamma curve thresholds, used for crgb conversion.
1712 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B
1714 * Gamma curve offsets, used for crgb conversion.
1716 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B
1718 * Gamma curve slopes, used for crgb conversion.
1720 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B
1722 * Custom backlight curve thresholds.
1724 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B
1726 * Custom backlight curve offsets.
1728 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B
1730 * Ambient light thresholds.
1732 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B
1734 * Minimum programmable backlight.
1736 uint16_t min_abm_backlight; // 122B
1738 * Minimum reduction values.
1740 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B
1742 * Maximum reduction values.
1744 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B
1746 * Bright positive gain.
1748 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B
1750 * Dark negative gain.
1752 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B
1756 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B
1760 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B
1764 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B
1768 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B
1772 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B
1776 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B
1778 * Explicit padding to 4 byte boundary.
1780 uint8_t pad3[3]; // 229B
1782 * Backlight ramp reduction.
1784 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B
1786 * Backlight ramp start.
1788 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B
1792 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command.
1794 struct dmub_cmd_abm_set_pipe_data {
1801 * Panel Control HW instance.
1806 * Controls how ABM will interpret a set pipe or set level command.
1808 uint8_t set_pipe_option;
1814 uint8_t ramping_boundary;
1818 * Definition of a DMUB_CMD__ABM_SET_PIPE command.
1820 struct dmub_rb_cmd_abm_set_pipe {
1824 struct dmub_cmd_header header;
1827 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command.
1829 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data;
1833 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command.
1835 struct dmub_cmd_abm_set_backlight_data {
1837 * Number of frames to ramp to backlight user level.
1839 uint32_t frame_ramp;
1842 * Requested backlight level from user.
1844 uint32_t backlight_user_level;
1847 * ABM control version.
1852 * Panel Control HW instance mask.
1853 * Bit 0 is Panel Control HW instance 0.
1854 * Bit 1 is Panel Control HW instance 1.
1859 * Explicit padding to 4 byte boundary.
1865 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command.
1867 struct dmub_rb_cmd_abm_set_backlight {
1871 struct dmub_cmd_header header;
1874 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command.
1876 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data;
1880 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command.
1882 struct dmub_cmd_abm_set_level_data {
1884 * Set current ABM operating/aggression level.
1889 * ABM control version.
1894 * Panel Control HW instance mask.
1895 * Bit 0 is Panel Control HW instance 0.
1896 * Bit 1 is Panel Control HW instance 1.
1901 * Explicit padding to 4 byte boundary.
1907 * Definition of a DMUB_CMD__ABM_SET_LEVEL command.
1909 struct dmub_rb_cmd_abm_set_level {
1913 struct dmub_cmd_header header;
1916 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command.
1918 struct dmub_cmd_abm_set_level_data abm_set_level_data;
1922 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
1924 struct dmub_cmd_abm_set_ambient_level_data {
1926 * Ambient light sensor reading from OS.
1928 uint32_t ambient_lux;
1931 * ABM control version.
1936 * Panel Control HW instance mask.
1937 * Bit 0 is Panel Control HW instance 0.
1938 * Bit 1 is Panel Control HW instance 1.
1943 * Explicit padding to 4 byte boundary.
1949 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
1951 struct dmub_rb_cmd_abm_set_ambient_level {
1955 struct dmub_cmd_header header;
1958 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
1960 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data;
1964 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command.
1966 struct dmub_cmd_abm_set_pwm_frac_data {
1968 * Enable/disable fractional duty cycle for backlight PWM.
1969 * TODO: Convert to uint8_t.
1971 uint32_t fractional_pwm;
1974 * ABM control version.
1979 * Panel Control HW instance mask.
1980 * Bit 0 is Panel Control HW instance 0.
1981 * Bit 1 is Panel Control HW instance 1.
1986 * Explicit padding to 4 byte boundary.
1992 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command.
1994 struct dmub_rb_cmd_abm_set_pwm_frac {
1998 struct dmub_cmd_header header;
2001 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command.
2003 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data;
2007 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command.
2009 struct dmub_cmd_abm_init_config_data {
2011 * Location of indirect buffer used to pass init data to ABM.
2013 union dmub_addr src;
2016 * Indirect buffer length.
2022 * ABM control version.
2027 * Panel Control HW instance mask.
2028 * Bit 0 is Panel Control HW instance 0.
2029 * Bit 1 is Panel Control HW instance 1.
2034 * Explicit padding to 4 byte boundary.
2040 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command.
2042 struct dmub_rb_cmd_abm_init_config {
2046 struct dmub_cmd_header header;
2049 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command.
2051 struct dmub_cmd_abm_init_config_data abm_init_config_data;
2055 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command.
2057 struct dmub_cmd_query_feature_caps_data {
2059 * DMUB feature capabilities.
2060 * After DMUB init, driver will query FW capabilities prior to enabling certain features.
2062 struct dmub_feature_caps feature_caps;
2066 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command.
2068 struct dmub_rb_cmd_query_feature_caps {
2072 struct dmub_cmd_header header;
2074 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command.
2076 struct dmub_cmd_query_feature_caps_data query_feature_caps_data;
2079 struct dmub_optc_state {
2080 uint32_t v_total_max;
2081 uint32_t v_total_min;
2082 uint32_t v_total_mid;
2083 uint32_t v_total_mid_frame_num;
2085 uint32_t enable_manual_trigger;
2086 uint32_t clear_force_vsync;
2089 struct dmub_rb_cmd_drr_update {
2090 struct dmub_cmd_header header;
2091 struct dmub_optc_state dmub_optc_state_req;
2094 #ifdef CONFIG_DRM_AMD_DC_DCN3_1
2096 * enum dmub_cmd_panel_cntl_type - Panel control command.
2098 enum dmub_cmd_panel_cntl_type {
2100 * Initializes embedded panel hardware blocks.
2102 DMUB_CMD__PANEL_CNTL_HW_INIT = 0,
2104 * Queries backlight info for the embedded panel.
2106 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1,
2110 * struct dmub_cmd_panel_cntl_data - Panel control data.
2112 struct dmub_cmd_panel_cntl_data {
2113 uint32_t inst; /**< panel instance */
2114 uint32_t current_backlight; /* in/out */
2115 uint32_t bl_pwm_cntl; /* in/out */
2116 uint32_t bl_pwm_period_cntl; /* in/out */
2117 uint32_t bl_pwm_ref_div1; /* in/out */
2118 uint8_t is_backlight_on : 1; /* in/out */
2119 uint8_t is_powered_on : 1; /* in/out */
2123 * struct dmub_rb_cmd_panel_cntl - Panel control command.
2125 struct dmub_rb_cmd_panel_cntl {
2126 struct dmub_cmd_header header; /**< header */
2127 struct dmub_cmd_panel_cntl_data data; /**< payload */
2132 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
2134 struct dmub_cmd_lvtma_control_data {
2135 uint8_t uc_pwr_action; /**< LVTMA_ACTION */
2136 uint8_t reserved_0[3]; /**< For future use */
2137 uint8_t panel_inst; /**< LVTMA control instance */
2138 uint8_t reserved_1[3]; /**< For future use */
2142 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
2144 struct dmub_rb_cmd_lvtma_control {
2148 struct dmub_cmd_header header;
2150 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
2152 struct dmub_cmd_lvtma_control_data data;
2156 * union dmub_rb_cmd - DMUB inbox command.
2159 struct dmub_rb_cmd_lock_hw lock_hw;
2161 * Elements shared with all commands.
2163 struct dmub_rb_cmd_common cmd_common;
2165 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command.
2167 struct dmub_rb_cmd_read_modify_write read_modify_write;
2169 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command.
2171 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq;
2173 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command.
2175 struct dmub_rb_cmd_burst_write burst_write;
2177 * Definition of a DMUB_CMD__REG_REG_WAIT command.
2179 struct dmub_rb_cmd_reg_wait reg_wait;
2181 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command.
2183 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control;
2185 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command.
2187 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock;
2189 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command.
2191 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating;
2193 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command.
2195 struct dmub_rb_cmd_dpphy_init dpphy_init;
2197 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command.
2199 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control;
2201 * Definition of a DMUB_CMD__PSR_SET_VERSION command.
2203 struct dmub_rb_cmd_psr_set_version psr_set_version;
2205 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command.
2207 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings;
2209 * Definition of a DMUB_CMD__PSR_ENABLE command.
2211 struct dmub_rb_cmd_psr_enable psr_enable;
2213 * Definition of a DMUB_CMD__PSR_SET_LEVEL command.
2215 struct dmub_rb_cmd_psr_set_level psr_set_level;
2217 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command.
2219 struct dmub_rb_cmd_psr_force_static psr_force_static;
2221 * Definition of a DMUB_CMD__PLAT_54186_WA command.
2223 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa;
2225 * Definition of a DMUB_CMD__MALL command.
2227 struct dmub_rb_cmd_mall mall;
2228 #ifdef CONFIG_DRM_AMD_DC_DCN3_1
2230 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command.
2232 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore;
2235 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command.
2237 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks;
2240 * Definition of DMUB_CMD__PANEL_CNTL commands.
2242 struct dmub_rb_cmd_panel_cntl panel_cntl;
2245 * Definition of a DMUB_CMD__ABM_SET_PIPE command.
2247 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe;
2250 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command.
2252 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight;
2255 * Definition of a DMUB_CMD__ABM_SET_LEVEL command.
2257 struct dmub_rb_cmd_abm_set_level abm_set_level;
2260 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
2262 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level;
2265 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command.
2267 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac;
2270 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command.
2272 struct dmub_rb_cmd_abm_init_config abm_init_config;
2275 * Definition of a DMUB_CMD__DP_AUX_ACCESS command.
2277 struct dmub_rb_cmd_dp_aux_access dp_aux_access;
2280 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command.
2282 struct dmub_rb_cmd_outbox1_enable outbox1_enable;
2285 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command.
2287 struct dmub_rb_cmd_query_feature_caps query_feature_caps;
2288 struct dmub_rb_cmd_drr_update drr_update;
2290 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
2292 struct dmub_rb_cmd_lvtma_control lvtma_control;
2296 * union dmub_rb_out_cmd - Outbox command
2298 union dmub_rb_out_cmd {
2300 * Parameters common to every command.
2302 struct dmub_rb_cmd_common cmd_common;
2304 * AUX reply command.
2306 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply;
2308 * HPD notify command.
2310 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify;
2315 //==============================================================================
2316 //</DMUB_CMD>===================================================================
2317 //==============================================================================
2318 //< DMUB_RB>====================================================================
2319 //==============================================================================
2321 #if defined(__cplusplus)
2326 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer
2328 struct dmub_rb_init_params {
2329 void *ctx; /**< Caller provided context pointer */
2330 void *base_address; /**< CPU base address for ring's data */
2331 uint32_t capacity; /**< Ringbuffer capacity in bytes */
2332 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */
2333 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */
2337 * struct dmub_rb - Inbox or outbox DMUB ringbuffer
2340 void *base_address; /**< CPU address for the ring's data */
2341 uint32_t rptr; /**< Read pointer for consumer in bytes */
2342 uint32_t wrpt; /**< Write pointer for producer in bytes */
2343 uint32_t capacity; /**< Ringbuffer capacity in bytes */
2345 void *ctx; /**< Caller provided context pointer */
2346 void *dmub; /**< Pointer to the DMUB interface */
2350 * @brief Checks if the ringbuffer is empty.
2352 * @param rb DMUB Ringbuffer
2353 * @return true if empty
2354 * @return false otherwise
2356 static inline bool dmub_rb_empty(struct dmub_rb *rb)
2358 return (rb->wrpt == rb->rptr);
2362 * @brief Checks if the ringbuffer is full
2364 * @param rb DMUB Ringbuffer
2365 * @return true if full
2366 * @return false otherwise
2368 static inline bool dmub_rb_full(struct dmub_rb *rb)
2370 uint32_t data_count;
2372 if (rb->wrpt >= rb->rptr)
2373 data_count = rb->wrpt - rb->rptr;
2375 data_count = rb->capacity - (rb->rptr - rb->wrpt);
2377 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE));
2381 * @brief Pushes a command into the ringbuffer
2383 * @param rb DMUB ringbuffer
2384 * @param cmd The command to push
2385 * @return true if the ringbuffer was not full
2386 * @return false otherwise
2388 static inline bool dmub_rb_push_front(struct dmub_rb *rb,
2389 const union dmub_rb_cmd *cmd)
2391 uint64_t volatile *dst = (uint64_t volatile *)(rb->base_address) + rb->wrpt / sizeof(uint64_t);
2392 const uint64_t *src = (const uint64_t *)cmd;
2395 if (dmub_rb_full(rb))
2399 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++)
2402 rb->wrpt += DMUB_RB_CMD_SIZE;
2404 if (rb->wrpt >= rb->capacity)
2405 rb->wrpt %= rb->capacity;
2411 * @brief Pushes a command into the DMUB outbox ringbuffer
2413 * @param rb DMUB outbox ringbuffer
2414 * @param cmd Outbox command
2415 * @return true if not full
2416 * @return false otherwise
2418 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb,
2419 const union dmub_rb_out_cmd *cmd)
2421 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt;
2422 const uint8_t *src = (uint8_t *)cmd;
2424 if (dmub_rb_full(rb))
2427 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE);
2429 rb->wrpt += DMUB_RB_CMD_SIZE;
2431 if (rb->wrpt >= rb->capacity)
2432 rb->wrpt %= rb->capacity;
2438 * @brief Returns the next unprocessed command in the ringbuffer.
2440 * @param rb DMUB ringbuffer
2441 * @param cmd The command to return
2442 * @return true if not empty
2443 * @return false otherwise
2445 static inline bool dmub_rb_front(struct dmub_rb *rb,
2446 union dmub_rb_cmd **cmd)
2448 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr;
2450 if (dmub_rb_empty(rb))
2453 *cmd = (union dmub_rb_cmd *)rb_cmd;
2459 * @brief Determines the next ringbuffer offset.
2461 * @param rb DMUB inbox ringbuffer
2462 * @param num_cmds Number of commands
2463 * @param next_rptr The next offset in the ringbuffer
2465 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb,
2467 uint32_t *next_rptr)
2469 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds;
2471 if (*next_rptr >= rb->capacity)
2472 *next_rptr %= rb->capacity;
2476 * @brief Returns a pointer to a command in the inbox.
2478 * @param rb DMUB inbox ringbuffer
2479 * @param cmd The inbox command to return
2480 * @param rptr The ringbuffer offset
2481 * @return true if not empty
2482 * @return false otherwise
2484 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb,
2485 union dmub_rb_cmd **cmd,
2488 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr;
2490 if (dmub_rb_empty(rb))
2493 *cmd = (union dmub_rb_cmd *)rb_cmd;
2499 * @brief Returns the next unprocessed command in the outbox.
2501 * @param rb DMUB outbox ringbuffer
2502 * @param cmd The outbox command to return
2503 * @return true if not empty
2504 * @return false otherwise
2506 static inline bool dmub_rb_out_front(struct dmub_rb *rb,
2507 union dmub_rb_out_cmd *cmd)
2509 const uint64_t volatile *src = (const uint64_t volatile *)(rb->base_address) + rb->rptr / sizeof(uint64_t);
2510 uint64_t *dst = (uint64_t *)cmd;
2513 if (dmub_rb_empty(rb))
2517 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++)
2524 * @brief Removes the front entry in the ringbuffer.
2526 * @param rb DMUB ringbuffer
2527 * @return true if the command was removed
2528 * @return false if there were no commands
2530 static inline bool dmub_rb_pop_front(struct dmub_rb *rb)
2532 if (dmub_rb_empty(rb))
2535 rb->rptr += DMUB_RB_CMD_SIZE;
2537 if (rb->rptr >= rb->capacity)
2538 rb->rptr %= rb->capacity;
2544 * @brief Flushes commands in the ringbuffer to framebuffer memory.
2546 * Avoids a race condition where DMCUB accesses memory while
2547 * there are still writes in flight to framebuffer.
2549 * @param rb DMUB ringbuffer
2551 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb)
2553 uint32_t rptr = rb->rptr;
2554 uint32_t wptr = rb->wrpt;
2556 while (rptr != wptr) {
2557 uint64_t volatile *data = (uint64_t volatile *)rb->base_address + rptr / sizeof(uint64_t);
2560 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++)
2563 rptr += DMUB_RB_CMD_SIZE;
2564 if (rptr >= rb->capacity)
2565 rptr %= rb->capacity;
2570 * @brief Initializes a DMCUB ringbuffer
2572 * @param rb DMUB ringbuffer
2573 * @param init_params initial configuration for the ringbuffer
2575 static inline void dmub_rb_init(struct dmub_rb *rb,
2576 struct dmub_rb_init_params *init_params)
2578 rb->base_address = init_params->base_address;
2579 rb->capacity = init_params->capacity;
2580 rb->rptr = init_params->read_ptr;
2581 rb->wrpt = init_params->write_ptr;
2585 * @brief Copies output data from in/out commands into the given command.
2587 * @param rb DMUB ringbuffer
2588 * @param cmd Command to copy data into
2590 static inline void dmub_rb_get_return_data(struct dmub_rb *rb,
2591 union dmub_rb_cmd *cmd)
2593 // Copy rb entry back into command
2594 uint8_t *rd_ptr = (rb->rptr == 0) ?
2595 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE :
2596 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE;
2598 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE);
2601 #if defined(__cplusplus)
2605 //==============================================================================
2606 //</DMUB_RB>====================================================================
2607 //==============================================================================
2609 #endif /* _DMUB_CMD_H_ */