drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

   1 /*
   2  * Copyright 2021 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services.h"
  27 #include "irq_service_dcn303.h"
  28 #include "../dce110/irq_service_dce110.h"
  29
  30 #include "sienna_cichlid_ip_offset.h"
  31 #include "dcn/dcn_3_0_3_offset.h"
  32 #include "dcn/dcn_3_0_3_sh_mask.h"
  33
  34 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
  35
  36 static enum dc_irq_source to_dal_irq_source_dcn303(struct irq_service *irq_service,
  37                                                    uint32_t src_id,
  38                                                    uint32_t ext_id)
  39 {
  40         switch (src_id) {
  41         case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
  42                 return DC_IRQ_SOURCE_VBLANK1;
  43         case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
  44                 return DC_IRQ_SOURCE_VBLANK2;
  45         case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
  46                 return DC_IRQ_SOURCE_PFLIP1;
  47         case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
  48                 return DC_IRQ_SOURCE_PFLIP2;
  49         case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
  50                 return DC_IRQ_SOURCE_VUPDATE1;
  51         case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
  52                 return DC_IRQ_SOURCE_VUPDATE2;
  53
  54         case DCN_1_0__SRCID__DC_HPD1_INT:
  55                 /* generic src_id for all HPD and HPDRX interrupts */
  56                 switch (ext_id) {
  57                 case DCN_1_0__CTXID__DC_HPD1_INT:
  58                         return DC_IRQ_SOURCE_HPD1;
  59                 case DCN_1_0__CTXID__DC_HPD2_INT:
  60                         return DC_IRQ_SOURCE_HPD2;
  61                 case DCN_1_0__CTXID__DC_HPD1_RX_INT:
  62                         return DC_IRQ_SOURCE_HPD1RX;
  63                 case DCN_1_0__CTXID__DC_HPD2_RX_INT:
  64                         return DC_IRQ_SOURCE_HPD2RX;
  65                 default:
  66                         return DC_IRQ_SOURCE_INVALID;
  67                 }
  68                 break;
  69
  70         default:
  71                 return DC_IRQ_SOURCE_INVALID;
  72         }
  73 }
  74
  75 static bool hpd_ack(struct irq_service *irq_service, const struct irq_source_info *info)
  76 {
  77         uint32_t addr = info->status_reg;
  78         uint32_t value = dm_read_reg(irq_service->ctx, addr);
  79         uint32_t current_status = get_reg_field_value(value, HPD0_DC_HPD_INT_STATUS, DC_HPD_SENSE_DELAYED);
  80
  81         dal_irq_service_ack_generic(irq_service, info);
  82
  83         value = dm_read_reg(irq_service->ctx, info->enable_reg);
  84
  85         set_reg_field_value(value, current_status ? 0 : 1, HPD0_DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY);
  86
  87         dm_write_reg(irq_service->ctx, info->enable_reg, value);
  88
  89         return true;
  90 }
  91
  92 static const struct irq_source_info_funcs hpd_irq_info_funcs = {
  93                 .set = NULL,
  94                 .ack = hpd_ack
  95 };
  96
  97 static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
  98                 .set = NULL,
  99                 .ack = NULL
 100 };
 101
 102 static const struct irq_source_info_funcs pflip_irq_info_funcs = {
 103                 .set = NULL,
 104                 .ack = NULL
 105 };
 106
 107 static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
 108         .set = NULL,
 109         .ack = NULL
 110 };
 111
 112 static const struct irq_source_info_funcs vblank_irq_info_funcs = {
 113                 .set = NULL,
 114                 .ack = NULL
 115 };
 116
 117 #undef BASE_INNER
 118 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
 119
 120 /* compile time expand base address. */
 121 #define BASE(seg) BASE_INNER(seg)
 122
 123 #define SRI(reg_name, block, id)\
 124                 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 125                 mm ## block ## id ## _ ## reg_name
 126
 127
 128 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
 129                 .enable_reg = SRI(reg1, block, reg_num),\
 130                 .enable_mask = block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
 131                 .enable_value = {\
 132                                 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
 133                                 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
 134                 },\
 135                 .ack_reg = SRI(reg2, block, reg_num),\
 136                 .ack_mask = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
 137                 .ack_value = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
 138
 139
 140
 141 #define hpd_int_entry(reg_num)\
 142                 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
 143                                 IRQ_REG_ENTRY(HPD, reg_num,\
 144                                                 DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
 145                                                 DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
 146                                                 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
 147                                                 .funcs = &hpd_irq_info_funcs\
 148 }
 149
 150 #define hpd_rx_int_entry(reg_num)\
 151                 [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
 152                                 IRQ_REG_ENTRY(HPD, reg_num,\
 153                                                 DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
 154                                                 DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
 155                                                 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
 156                                                 .funcs = &hpd_rx_irq_info_funcs\
 157 }
 158 #define pflip_int_entry(reg_num)\
 159                 [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
 160                                 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
 161                                                 DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\
 162                                                 DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\
 163                                                 .funcs = &pflip_irq_info_funcs\
 164 }
 165
 166 /* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic
 167  * of DCE's DC_IRQ_SOURCE_VUPDATEx.
 168  */
 169 #define vupdate_no_lock_int_entry(reg_num)\
 170         [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
 171                 IRQ_REG_ENTRY(OTG, reg_num,\
 172                         OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\
 173                         OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\
 174                 .funcs = &vupdate_no_lock_irq_info_funcs\
 175         }
 176
 177 #define vblank_int_entry(reg_num)\
 178         [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
 179                 IRQ_REG_ENTRY(OTG, reg_num,\
 180                         OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
 181                         OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
 182                 .funcs = &vblank_irq_info_funcs\
 183         }
 184
 185 #define dummy_irq_entry() { .funcs = &dummy_irq_info_funcs }
 186
 187 #define i2c_int_entry(reg_num) \
 188                 [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
 189
 190 #define dp_sink_int_entry(reg_num) \
 191                 [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
 192
 193 #define gpio_pad_int_entry(reg_num) \
 194                 [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
 195
 196 #define dc_underflow_int_entry(reg_num) \
 197                 [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
 198
 199 static const struct irq_source_info_funcs dummy_irq_info_funcs = {
 200                 .set = dal_irq_service_dummy_set,
 201                 .ack = dal_irq_service_dummy_ack
 202 };
 203
 204 static const struct irq_source_info irq_source_info_dcn303[DAL_IRQ_SOURCES_NUMBER] = {
 205                 [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
 206                 hpd_int_entry(0),
 207                 hpd_int_entry(1),
 208                 hpd_rx_int_entry(0),
 209                 hpd_rx_int_entry(1),
 210                 i2c_int_entry(1),
 211                 i2c_int_entry(2),
 212                 dp_sink_int_entry(1),
 213                 dp_sink_int_entry(2),
 214                 [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
 215                 pflip_int_entry(0),
 216                 pflip_int_entry(1),
 217                 [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
 218                 gpio_pad_int_entry(0),
 219                 gpio_pad_int_entry(1),
 220                 gpio_pad_int_entry(2),
 221                 gpio_pad_int_entry(3),
 222                 gpio_pad_int_entry(4),
 223                 gpio_pad_int_entry(5),
 224                 gpio_pad_int_entry(6),
 225                 gpio_pad_int_entry(7),
 226                 gpio_pad_int_entry(8),
 227                 gpio_pad_int_entry(9),
 228                 gpio_pad_int_entry(10),
 229                 gpio_pad_int_entry(11),
 230                 gpio_pad_int_entry(12),
 231                 gpio_pad_int_entry(13),
 232                 gpio_pad_int_entry(14),
 233                 gpio_pad_int_entry(15),
 234                 gpio_pad_int_entry(16),
 235                 gpio_pad_int_entry(17),
 236                 gpio_pad_int_entry(18),
 237                 gpio_pad_int_entry(19),
 238                 gpio_pad_int_entry(20),
 239                 gpio_pad_int_entry(21),
 240                 gpio_pad_int_entry(22),
 241                 gpio_pad_int_entry(23),
 242                 gpio_pad_int_entry(24),
 243                 gpio_pad_int_entry(25),
 244                 gpio_pad_int_entry(26),
 245                 gpio_pad_int_entry(27),
 246                 gpio_pad_int_entry(28),
 247                 gpio_pad_int_entry(29),
 248                 gpio_pad_int_entry(30),
 249                 dc_underflow_int_entry(1),
 250                 dc_underflow_int_entry(2),
 251                 [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
 252                 [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
 253                 vupdate_no_lock_int_entry(0),
 254                 vupdate_no_lock_int_entry(1),
 255                 vblank_int_entry(0),
 256                 vblank_int_entry(1),
 257 };
 258
 259 static const struct irq_service_funcs irq_service_funcs_dcn303 = {
 260                 .to_dal_irq_source = to_dal_irq_source_dcn303
 261 };
 262
 263 static void dcn303_irq_construct(struct irq_service *irq_service, struct irq_service_init_data *init_data)
 264 {
 265         dal_irq_service_construct(irq_service, init_data);
 266
 267         irq_service->info = irq_source_info_dcn303;
 268         irq_service->funcs = &irq_service_funcs_dcn303;
 269 }
 270
 271 struct irq_service *dal_irq_service_dcn303_create(struct irq_service_init_data *init_data)
 272 {
 273         struct irq_service *irq_service = kzalloc(sizeof(*irq_service), GFP_KERNEL);
 274
 275         if (!irq_service)
 276                 return NULL;
 277
 278         dcn303_irq_construct(irq_service, init_data);
 279         return irq_service;
 280 }