2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #ifndef __DC_HW_SEQUENCER_PRIVATE_H__
27 #define __DC_HW_SEQUENCER_PRIVATE_H__
31 enum pipe_gating_control {
32 PIPE_GATING_CONTROL_DISABLE = 0,
33 PIPE_GATING_CONTROL_ENABLE,
34 PIPE_GATING_CONTROL_INIT
38 bool blnd_crtc_trigger;
40 bool false_optc_underflow;
43 bool disallow_self_refresh_during_multi_plane_transition;
44 bool dp_hpo_and_otg_sequence;
45 bool wait_hubpret_read_start_during_mpo_transition;
48 struct hwseq_wa_state {
49 bool DEGVIDCN10_253_applied;
50 bool disallow_self_refresh_during_multi_plane_transition_applied;
51 unsigned int disallow_self_refresh_during_multi_plane_transition_applied_on_frame;
56 struct dc_stream_status;
57 struct dc_writeback_info;
58 struct dchub_init_data;
59 struct dc_static_screen_params;
61 struct resource_context;
62 struct stream_resource;
63 struct dc_phy_addr_space_config;
64 struct dc_virtual_addr_space_config;
68 struct timing_generator;
70 struct output_pixel_processor;
72 struct hwseq_private_funcs {
74 void (*disable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
75 void (*enable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
76 void (*init_pipes)(struct dc *dc, struct dc_state *context);
77 void (*reset_hw_ctx_wrap)(struct dc *dc, struct dc_state *context);
78 void (*update_plane_addr)(const struct dc *dc,
79 struct pipe_ctx *pipe_ctx);
80 void (*plane_atomic_disconnect)(struct dc *dc,
81 struct pipe_ctx *pipe_ctx);
82 void (*update_mpcc)(struct dc *dc, struct pipe_ctx *pipe_ctx);
83 bool (*set_input_transfer_func)(struct dc *dc,
84 struct pipe_ctx *pipe_ctx,
85 const struct dc_plane_state *plane_state);
86 bool (*set_output_transfer_func)(struct dc *dc,
87 struct pipe_ctx *pipe_ctx,
88 const struct dc_stream_state *stream);
89 void (*power_down)(struct dc *dc);
90 void (*enable_display_pipe_clock_gating)(struct dc_context *ctx,
92 bool (*enable_display_power_gating)(struct dc *dc,
93 uint8_t controller_id,
95 enum pipe_gating_control power_gating);
96 void (*blank_pixel_data)(struct dc *dc,
97 struct pipe_ctx *pipe_ctx,
99 enum dc_status (*enable_stream_timing)(
100 struct pipe_ctx *pipe_ctx,
101 struct dc_state *context,
103 void (*edp_backlight_control)(struct dc_link *link,
105 void (*setup_vupdate_interrupt)(struct dc *dc,
106 struct pipe_ctx *pipe_ctx);
107 bool (*did_underflow_occur)(struct dc *dc, struct pipe_ctx *pipe_ctx);
108 void (*init_blank)(struct dc *dc, struct timing_generator *tg);
109 void (*disable_vga)(struct dce_hwseq *hws);
110 void (*bios_golden_init)(struct dc *dc);
111 void (*plane_atomic_power_down)(struct dc *dc,
114 void (*plane_atomic_disable)(struct dc *dc, struct pipe_ctx *pipe_ctx);
115 void (*enable_power_gating_plane)(struct dce_hwseq *hws,
117 void (*dpp_pg_control)(struct dce_hwseq *hws,
118 unsigned int dpp_inst,
120 void (*hubp_pg_control)(struct dce_hwseq *hws,
121 unsigned int hubp_inst,
123 void (*dsc_pg_control)(struct dce_hwseq *hws,
124 unsigned int dsc_inst,
126 void (*update_odm)(struct dc *dc, struct dc_state *context,
127 struct pipe_ctx *pipe_ctx);
128 void (*program_all_writeback_pipes_in_tree)(struct dc *dc,
129 const struct dc_stream_state *stream,
130 struct dc_state *context);
131 bool (*s0i3_golden_init_wa)(struct dc *dc);
132 void (*set_hdr_multiplier)(struct pipe_ctx *pipe_ctx);
133 void (*verify_allow_pstate_change_high)(struct dc *dc);
134 void (*program_pipe)(struct dc *dc,
135 struct pipe_ctx *pipe_ctx,
136 struct dc_state *context);
137 bool (*wait_for_blank_complete)(struct output_pixel_processor *opp);
138 void (*dccg_init)(struct dce_hwseq *hws);
139 bool (*set_blend_lut)(struct pipe_ctx *pipe_ctx,
140 const struct dc_plane_state *plane_state);
141 bool (*set_shaper_3dlut)(struct pipe_ctx *pipe_ctx,
142 const struct dc_plane_state *plane_state);
143 void (*PLAT_58856_wa)(struct dc_state *context,
144 struct pipe_ctx *pipe_ctx);
145 void (*setup_hpo_hw_control)(const struct dce_hwseq *hws, bool enable);
149 struct dc_context *ctx;
150 const struct dce_hwseq_registers *regs;
151 const struct dce_hwseq_shift *shifts;
152 const struct dce_hwseq_mask *masks;
153 struct dce_hwseq_wa wa;
154 struct hwseq_wa_state wa_state;
155 struct hwseq_private_funcs funcs;
157 PHYSICAL_ADDRESS_LOC fb_base;
158 PHYSICAL_ADDRESS_LOC fb_top;
159 PHYSICAL_ADDRESS_LOC fb_offset;
160 PHYSICAL_ADDRESS_LOC uma_top;
163 #endif /* __DC_HW_SEQUENCER_PRIVATE_H__ */