2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #ifndef __DC_HW_SEQUENCER_H__
27 #define __DC_HW_SEQUENCER_H__
29 #include "clock_source.h"
30 #include "inc/hw/timing_generator.h"
31 #include "inc/hw/opp.h"
32 #include "inc/hw/link_encoder.h"
33 #include "core_status.h"
42 struct dc_stream_status;
43 struct dc_writeback_info;
44 struct dchub_init_data;
45 struct dc_static_screen_params;
47 struct dc_phy_addr_space_config;
48 struct dc_virtual_addr_space_config;
52 struct hw_sequencer_funcs {
53 #ifdef CONFIG_DRM_AMD_DC_DCN3_0
54 void (*hardware_release)(struct dc *dc);
56 /* Embedded Display Related */
57 void (*edp_power_control)(struct dc_link *link, bool enable);
58 void (*edp_wait_for_hpd_ready)(struct dc_link *link, bool power_up);
60 /* Pipe Programming Related */
61 void (*init_hw)(struct dc *dc);
62 void (*power_down_on_boot)(struct dc *dc);
63 void (*enable_accelerated_mode)(struct dc *dc,
64 struct dc_state *context);
65 enum dc_status (*apply_ctx_to_hw)(struct dc *dc,
66 struct dc_state *context);
67 void (*disable_plane)(struct dc *dc, struct pipe_ctx *pipe_ctx);
68 void (*apply_ctx_for_surface)(struct dc *dc,
69 const struct dc_stream_state *stream,
70 int num_planes, struct dc_state *context);
71 void (*program_front_end_for_ctx)(struct dc *dc,
72 struct dc_state *context);
73 void (*disconnect_pipes)(struct dc *dc,
74 struct dc_state *context);
75 void (*wait_for_pending_cleared)(struct dc *dc,
76 struct dc_state *context);
77 void (*post_unlock_program_front_end)(struct dc *dc,
78 struct dc_state *context);
79 void (*update_plane_addr)(const struct dc *dc,
80 struct pipe_ctx *pipe_ctx);
81 void (*update_dchub)(struct dce_hwseq *hws,
82 struct dchub_init_data *dh_data);
83 void (*wait_for_mpcc_disconnect)(struct dc *dc,
84 struct resource_pool *res_pool,
85 struct pipe_ctx *pipe_ctx);
86 void (*edp_backlight_control)(
89 void (*program_triplebuffer)(const struct dc *dc,
90 struct pipe_ctx *pipe_ctx, bool enableTripleBuffer);
91 void (*update_pending_status)(struct pipe_ctx *pipe_ctx);
92 void (*power_down)(struct dc *dc);
94 /* Pipe Lock Related */
95 void (*pipe_control_lock)(struct dc *dc,
96 struct pipe_ctx *pipe, bool lock);
97 void (*interdependent_update_lock)(struct dc *dc,
98 struct dc_state *context, bool lock);
99 void (*set_flip_control_gsl)(struct pipe_ctx *pipe_ctx,
100 bool flip_immediate);
101 void (*cursor_lock)(struct dc *dc, struct pipe_ctx *pipe, bool lock);
104 void (*get_position)(struct pipe_ctx **pipe_ctx, int num_pipes,
105 struct crtc_position *position);
106 int (*get_vupdate_offset_from_vsync)(struct pipe_ctx *pipe_ctx);
107 void (*calc_vupdate_position)(
109 struct pipe_ctx *pipe_ctx,
110 uint32_t *start_line,
112 void (*enable_per_frame_crtc_position_reset)(struct dc *dc,
113 int group_size, struct pipe_ctx *grouped_pipes[]);
114 void (*enable_timing_synchronization)(struct dc *dc,
115 int group_index, int group_size,
116 struct pipe_ctx *grouped_pipes[]);
117 void (*setup_periodic_interrupt)(struct dc *dc,
118 struct pipe_ctx *pipe_ctx,
119 enum vline_select vline);
120 void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes,
121 unsigned int vmin, unsigned int vmax,
122 unsigned int vmid, unsigned int vmid_frame_number);
123 void (*set_static_screen_control)(struct pipe_ctx **pipe_ctx,
125 const struct dc_static_screen_params *events);
127 bool (*optimize_timing_for_fsft)(struct dc *dc,
128 struct dc_crtc_timing *timing,
129 unsigned int max_input_rate_in_khz);
133 void (*enable_stream)(struct pipe_ctx *pipe_ctx);
134 void (*disable_stream)(struct pipe_ctx *pipe_ctx);
135 void (*blank_stream)(struct pipe_ctx *pipe_ctx);
136 void (*unblank_stream)(struct pipe_ctx *pipe_ctx,
137 struct dc_link_settings *link_settings);
139 /* Bandwidth Related */
140 void (*prepare_bandwidth)(struct dc *dc, struct dc_state *context);
141 bool (*update_bandwidth)(struct dc *dc, struct dc_state *context);
142 void (*optimize_bandwidth)(struct dc *dc, struct dc_state *context);
144 /* Infopacket Related */
145 void (*set_avmute)(struct pipe_ctx *pipe_ctx, bool enable);
146 void (*send_immediate_sdp_message)(
147 struct pipe_ctx *pipe_ctx,
148 const uint8_t *custom_sdp_message,
149 unsigned int sdp_message_size);
150 void (*update_info_frame)(struct pipe_ctx *pipe_ctx);
151 void (*set_dmdata_attributes)(struct pipe_ctx *pipe);
152 void (*program_dmdata_engine)(struct pipe_ctx *pipe_ctx);
153 bool (*dmdata_status_done)(struct pipe_ctx *pipe_ctx);
156 void (*set_cursor_position)(struct pipe_ctx *pipe);
157 void (*set_cursor_attribute)(struct pipe_ctx *pipe);
158 void (*set_cursor_sdr_white_level)(struct pipe_ctx *pipe);
161 void (*program_gamut_remap)(struct pipe_ctx *pipe_ctx);
162 void (*program_output_csc)(struct dc *dc, struct pipe_ctx *pipe_ctx,
163 enum dc_color_space colorspace,
164 uint16_t *matrix, int opp_id);
167 int (*init_sys_ctx)(struct dce_hwseq *hws,
169 struct dc_phy_addr_space_config *pa_config);
170 void (*init_vm_ctx)(struct dce_hwseq *hws,
172 struct dc_virtual_addr_space_config *va_config,
175 /* Writeback Related */
176 void (*update_writeback)(struct dc *dc,
177 struct dc_writeback_info *wb_info,
178 struct dc_state *context);
179 void (*enable_writeback)(struct dc *dc,
180 struct dc_writeback_info *wb_info,
181 struct dc_state *context);
182 void (*disable_writeback)(struct dc *dc,
183 unsigned int dwb_pipe_inst);
185 bool (*mmhubbub_warmup)(struct dc *dc,
186 unsigned int num_dwb,
187 struct dc_writeback_info *wb_info);
190 enum dc_status (*set_clock)(struct dc *dc,
191 enum dc_clock_type clock_type,
192 uint32_t clk_khz, uint32_t stepping);
193 void (*get_clock)(struct dc *dc, enum dc_clock_type clock_type,
194 struct dc_clock_config *clock_cfg);
195 void (*optimize_pwr_state)(const struct dc *dc,
196 struct dc_state *context);
197 void (*exit_optimized_pwr_state)(const struct dc *dc,
198 struct dc_state *context);
201 void (*enable_audio_stream)(struct pipe_ctx *pipe_ctx);
202 void (*disable_audio_stream)(struct pipe_ctx *pipe_ctx);
204 /* Stereo 3D Related */
205 void (*setup_stereo)(struct pipe_ctx *pipe_ctx, struct dc *dc);
207 /* HW State Logging Related */
208 void (*log_hw_state)(struct dc *dc, struct dc_log_buffer_ctx *log_ctx);
209 void (*get_hw_state)(struct dc *dc, char *pBuf,
210 unsigned int bufSize, unsigned int mask);
211 void (*clear_status_bits)(struct dc *dc, unsigned int mask);
213 bool (*set_backlight_level)(struct pipe_ctx *pipe_ctx,
214 uint32_t backlight_pwm_u16_16,
215 uint32_t frame_ramp);
217 void (*set_abm_immediate_disable)(struct pipe_ctx *pipe_ctx);
219 void (*set_pipe)(struct pipe_ctx *pipe_ctx);
221 #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
222 /* Idle Optimization Related */
223 bool (*apply_idle_power_optimizations)(struct dc *dc, bool enable);
226 bool (*is_abm_supported)(struct dc *dc,
227 struct dc_state *context, struct dc_stream_state *stream);
230 void color_space_to_black_color(
232 enum dc_color_space colorspace,
233 struct tg_color *black_color);
235 bool hwss_wait_for_blank_complete(
236 struct timing_generator *tg);
238 const uint16_t *find_color_matrix(
239 enum dc_color_space color_space,
240 uint32_t *array_size);
242 #endif /* __DC_HW_SEQUENCER_H__ */