2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #ifndef _CORE_TYPES_H_
27 #define _CORE_TYPES_H_
30 #include "dce_calcs.h"
31 #include "dcn_calcs.h"
32 #include "ddc_service_types.h"
33 #include "dc_bios_types.h"
34 #include "mem_input.h"
39 #include "panel_cntl.h"
41 #define MAX_CLOCK_SOURCES 7
42 #define MAX_SVP_PHANTOM_STREAMS 2
43 #define MAX_SVP_PHANTOM_PLANES 2
45 void enable_surface_flip_reporting(struct dc_plane_state *plane_state,
46 uint32_t controller_id);
48 #include "grph_object_id.h"
49 #include "link_encoder.h"
50 #include "stream_encoder.h"
51 #include "clock_source.h"
53 #include "dm_pp_smu.h"
54 #ifdef CONFIG_DRM_AMD_DC_HDCP
55 #include "dm_cp_psp.h"
57 #include "link_hwss.h"
59 /********** DAL Core*********************/
60 #include "transform.h"
65 struct resource_context;
68 struct resource_funcs {
69 void (*destroy)(struct resource_pool **pool);
70 void (*link_init)(struct dc_link *link);
71 struct panel_cntl*(*panel_cntl_create)(
72 const struct panel_cntl_init_data *panel_cntl_init_data);
73 struct link_encoder *(*link_enc_create)(
74 struct dc_context *ctx,
75 const struct encoder_init_data *init);
76 /* Create a minimal link encoder object with no dc_link object
77 * associated with it. */
78 struct link_encoder *(*link_enc_create_minimal)(struct dc_context *ctx, enum engine_id eng_id);
80 bool (*validate_bandwidth)(
82 struct dc_state *context,
84 void (*calculate_wm_and_dlg)(
85 struct dc *dc, struct dc_state *context,
86 display_e2e_pipe_params_st *pipes,
89 void (*update_soc_for_wm_a)(
90 struct dc *dc, struct dc_state *context);
93 * @populate_dml_pipes - Populate pipe data struct
96 * Total of pipes available in the specific ASIC.
98 int (*populate_dml_pipes)(
100 struct dc_state *context,
101 display_e2e_pipe_params_st *pipes,
105 * Algorithm for assigning available link encoders to links.
107 * Update link_enc_assignments table and link_enc_avail list accordingly in
108 * struct resource_context.
110 void (*link_encs_assign)(
112 struct dc_state *state,
113 struct dc_stream_state *streams[],
114 uint8_t stream_count);
116 * Unassign a link encoder from a stream.
118 * Update link_enc_assignments table and link_enc_avail list accordingly in
119 * struct resource_context.
121 void (*link_enc_unassign)(
122 struct dc_state *state,
123 struct dc_stream_state *stream);
125 enum dc_status (*validate_global)(
127 struct dc_state *context);
130 * Acquires a free pipe for the head pipe.
131 * The head pipe is first pipe in the current context that matches the stream
132 * and does not have a top pipe or prev_odm_pipe.
134 struct pipe_ctx *(*acquire_idle_pipe_for_layer)(
135 struct dc_state *context,
136 const struct resource_pool *pool,
137 struct dc_stream_state *stream);
140 * Acquires a free pipe for the head pipe with some additional checks for odm.
141 * The head pipe is passed in as an argument unlike acquire_idle_pipe_for_layer
142 * where it is read from the context. So this allows us look for different
143 * idle_pipe if the head_pipes are different ( ex. in odm 2:1 when we have
144 * a left and right pipe ).
146 * It also checks the old context to see if:
148 * 1. a pipe has already been allocated for the head pipe. If so, it will
149 * try to select that pipe as the idle pipe if it is available in the current
151 * 2. if the head_pipe is on the left, it will check if the right pipe has
152 * a pipe already allocated. If so, it will not use that pipe if it is
153 * selected as the idle pipe.
155 struct pipe_ctx *(*acquire_idle_pipe_for_head_pipe_in_layer)(
156 struct dc_state *context,
157 const struct resource_pool *pool,
158 struct dc_stream_state *stream,
159 struct pipe_ctx *head_pipe);
161 enum dc_status (*validate_plane)(const struct dc_plane_state *plane_state, struct dc_caps *caps);
163 enum dc_status (*add_stream_to_ctx)(
165 struct dc_state *new_ctx,
166 struct dc_stream_state *dc_stream);
168 enum dc_status (*remove_stream_from_ctx)(
170 struct dc_state *new_ctx,
171 struct dc_stream_state *stream);
172 enum dc_status (*patch_unknown_plane_state)(
173 struct dc_plane_state *plane_state);
175 struct stream_encoder *(*find_first_free_match_stream_enc_for_link)(
176 struct resource_context *res_ctx,
177 const struct resource_pool *pool,
178 struct dc_stream_state *stream);
179 void (*populate_dml_writeback_from_context)(
181 struct resource_context *res_ctx,
182 display_e2e_pipe_params_st *pipes);
184 void (*set_mcif_arb_params)(
186 struct dc_state *context,
187 display_e2e_pipe_params_st *pipes,
189 void (*update_bw_bounding_box)(
191 struct clk_bw_params *bw_params);
192 bool (*acquire_post_bldn_3dlut)(
193 struct resource_context *res_ctx,
194 const struct resource_pool *pool,
196 struct dc_3dlut **lut,
197 struct dc_transfer_func **shaper);
199 bool (*release_post_bldn_3dlut)(
200 struct resource_context *res_ctx,
201 const struct resource_pool *pool,
202 struct dc_3dlut **lut,
203 struct dc_transfer_func **shaper);
205 enum dc_status (*add_dsc_to_stream_resource)(
206 struct dc *dc, struct dc_state *state,
207 struct dc_stream_state *stream);
209 void (*add_phantom_pipes)(
211 struct dc_state *context,
212 display_e2e_pipe_params_st *pipes,
213 unsigned int pipe_cnt,
216 bool (*remove_phantom_pipes)(struct dc *dc, struct dc_state *context, bool fast_update);
217 void (*retain_phantom_pipes)(struct dc *dc, struct dc_state *context);
218 void (*get_panel_config_defaults)(struct dc_panel_config *panel_config);
219 void (*save_mall_state)(struct dc *dc, struct dc_state *context, struct mall_temp_config *temp_config);
220 void (*restore_mall_state)(struct dc *dc, struct dc_state *context, struct mall_temp_config *temp_config);
223 struct audio_support{
225 bool hdmi_audio_on_dongle;
226 bool hdmi_audio_native;
229 #define NO_UNDERLAY_PIPE -1
231 struct resource_pool {
232 struct mem_input *mis[MAX_PIPES];
233 struct hubp *hubps[MAX_PIPES];
234 struct input_pixel_processor *ipps[MAX_PIPES];
235 struct transform *transforms[MAX_PIPES];
236 struct dpp *dpps[MAX_PIPES];
237 struct output_pixel_processor *opps[MAX_PIPES];
238 struct timing_generator *timing_generators[MAX_PIPES];
239 struct stream_encoder *stream_enc[MAX_PIPES * 2];
240 struct hubbub *hubbub;
242 struct pp_smu_funcs *pp_smu;
243 struct dce_aux *engines[MAX_PIPES];
244 struct dce_i2c_hw *hw_i2cs[MAX_PIPES];
245 struct dce_i2c_sw *sw_i2cs[MAX_PIPES];
246 bool i2c_hw_buffer_in_use;
248 struct dwbc *dwbc[MAX_DWB_PIPES];
249 struct mcif_wb *mcif_wb[MAX_DWB_PIPES];
251 unsigned int gsl_0:1;
252 unsigned int gsl_1:1;
253 unsigned int gsl_2:1;
256 struct display_stream_compressor *dscs[MAX_PIPES];
258 unsigned int pipe_count;
259 unsigned int underlay_pipe_index;
260 unsigned int stream_enc_count;
262 /* An array for accessing the link encoder objects that have been created.
263 * Index in array corresponds to engine ID - viz. 0: ENGINE_ID_DIGA
265 struct link_encoder *link_encoders[MAX_DIG_LINK_ENCODERS];
266 /* Number of DIG link encoder objects created - i.e. number of valid
267 * entries in link_encoders array.
269 unsigned int dig_link_enc_count;
270 /* Number of USB4 DPIA (DisplayPort Input Adapter) link objects created.*/
271 unsigned int usb4_dpia_count;
273 unsigned int hpo_dp_stream_enc_count;
274 struct hpo_dp_stream_encoder *hpo_dp_stream_enc[MAX_HPO_DP2_ENCODERS];
275 unsigned int hpo_dp_link_enc_count;
276 struct hpo_dp_link_encoder *hpo_dp_link_enc[MAX_HPO_DP2_LINK_ENCODERS];
277 struct dc_3dlut *mpc_lut[MAX_PIPES];
278 struct dc_transfer_func *mpc_shaper[MAX_PIPES];
281 unsigned int xtalin_clock_inKhz;
282 unsigned int dccg_ref_clock_inKhz;
283 unsigned int dchub_ref_clock_inKhz;
285 unsigned int timing_generator_count;
286 unsigned int mpcc_count;
288 unsigned int writeback_pipe_count;
290 * reserved clock source for DP
292 struct clock_source *dp_clock_source;
294 struct clock_source *clock_sources[MAX_CLOCK_SOURCES];
295 unsigned int clk_src_count;
297 struct audio *audios[MAX_AUDIOS];
298 unsigned int audio_count;
299 struct audio_support audio_support;
302 struct irq_service *irqs;
306 struct dmub_psr *psr;
308 struct abm *multiple_abms[MAX_PIPES];
310 const struct resource_funcs *funcs;
311 const struct resource_caps *res_cap;
313 struct ddc_service *oem_device;
316 struct dcn_fe_bandwidth {
321 struct stream_resource {
322 struct output_pixel_processor *opp;
323 struct display_stream_compressor *dsc;
324 struct timing_generator *tg;
325 struct stream_encoder *stream_enc;
326 struct hpo_dp_stream_encoder *hpo_dp_stream_enc;
329 struct pixel_clk_params pix_clk_params;
330 struct encoder_info_frame encoder_info_frame;
333 /* There are only (num_pipes+1)/2 groups. 0 means unassigned,
334 * otherwise it's using group number 'gsl_group-1'
339 struct plane_resource {
340 struct scaler_data scl_data;
342 struct mem_input *mi;
343 struct input_pixel_processor *ipp;
344 struct transform *xfm;
348 struct dcn_fe_bandwidth bw;
351 #define LINK_RES_HPO_DP_REC_MAP__MASK 0xFFFF
352 #define LINK_RES_HPO_DP_REC_MAP__SHIFT 0
354 /* all mappable hardware resources used to enable a link */
355 struct link_resource {
356 struct hpo_dp_link_encoder *hpo_dp_link_enc;
360 struct dc_link_settings dp_link_settings;
362 union pipe_update_flags {
365 uint32_t disable : 1;
367 uint32_t global_sync : 1;
368 uint32_t opp_changed : 1;
369 uint32_t tg_changed : 1;
372 uint32_t hubp_interdependent : 1;
373 uint32_t hubp_rq_dlg_ttu : 1;
374 uint32_t gamut_remap : 1;
376 uint32_t viewport : 1;
377 uint32_t plane_changed : 1;
378 uint32_t det_size : 1;
384 struct dc_plane_state *plane_state;
385 struct dc_stream_state *stream;
387 struct plane_resource plane_res;
390 * @stream_res: Reference to DCN resource components such OPP and DSC.
392 struct stream_resource stream_res;
393 struct link_resource link_res;
395 struct clock_source *clock_source;
397 struct pll_settings pll_settings;
402 * link config records software decision for what link config should be
403 * enabled given current link capability and stream during hw resource
404 * mapping. This is to decouple the dependency on link capability during
405 * dc commit or update.
407 struct link_config link_config;
410 uint8_t pipe_idx_syncd;
412 struct pipe_ctx *top_pipe;
413 struct pipe_ctx *bottom_pipe;
414 struct pipe_ctx *next_odm_pipe;
415 struct pipe_ctx *prev_odm_pipe;
417 struct _vcs_dpi_display_dlg_regs_st dlg_regs;
418 struct _vcs_dpi_display_ttu_regs_st ttu_regs;
419 struct _vcs_dpi_display_rq_regs_st rq_regs;
420 struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param;
421 struct _vcs_dpi_display_rq_params_st dml_rq_param;
422 struct _vcs_dpi_display_dlg_sys_params_st dml_dlg_sys_param;
423 struct _vcs_dpi_display_e2e_pipe_params_st dml_input;
424 int det_buffer_size_kb;
426 unsigned int surface_size_in_mall_bytes;
429 struct mcif_wb *mcif_wb;
430 union pipe_update_flags update_flags;
433 /* Data used for dynamic link encoder assignment.
434 * Tracks current and future assignments; available link encoders;
435 * and mode of operation (whether to use current or future assignments).
437 struct link_enc_cfg_context {
438 enum link_enc_cfg_mode mode;
439 struct link_enc_assignment link_enc_assignments[MAX_PIPES];
440 enum engine_id link_enc_avail[MAX_DIG_LINK_ENCODERS];
441 struct link_enc_assignment transient_assignments[MAX_PIPES];
444 struct resource_context {
445 struct pipe_ctx pipe_ctx[MAX_PIPES];
446 bool is_stream_enc_acquired[MAX_PIPES * 2];
447 bool is_audio_acquired[MAX_PIPES];
448 uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES];
449 uint8_t dp_clock_source_ref_count;
450 bool is_dsc_acquired[MAX_PIPES];
451 struct link_enc_cfg_context link_enc_cfg_ctx;
452 bool is_hpo_dp_stream_enc_acquired[MAX_HPO_DP2_ENCODERS];
453 unsigned int hpo_dp_link_enc_to_link_idx[MAX_HPO_DP2_LINK_ENCODERS];
454 int hpo_dp_link_enc_ref_cnts[MAX_HPO_DP2_LINK_ENCODERS];
455 bool is_mpc_3dlut_acquired[MAX_PIPES];
458 struct dce_bw_output {
459 bool cpuc_state_change_enable;
460 bool cpup_state_change_enable;
461 bool stutter_mode_enable;
462 bool nbp_state_change_enable;
463 bool all_displays_in_sync;
464 struct dce_watermarks urgent_wm_ns[MAX_PIPES];
465 struct dce_watermarks stutter_exit_wm_ns[MAX_PIPES];
466 struct dce_watermarks stutter_entry_wm_ns[MAX_PIPES];
467 struct dce_watermarks nbp_state_change_wm_ns[MAX_PIPES];
469 int sclk_deep_sleep_khz;
472 int blackout_recovery_time_us;
475 struct dcn_bw_writeback {
476 struct mcif_arb_params mcif_wb_arb[MAX_DWB_PIPES];
479 struct dcn_bw_output {
480 struct dc_clocks clk;
481 struct dcn_watermark_set watermarks;
482 struct dcn_bw_writeback bw_writeback;
484 unsigned int mall_ss_size_bytes;
485 unsigned int mall_ss_psr_active_size_bytes;
486 unsigned int mall_subvp_size_bytes;
487 unsigned int legacy_svp_drr_stream_index;
488 bool legacy_svp_drr_stream_index_valid;
492 struct dcn_bw_output dcn;
493 struct dce_bw_output dce;
498 struct display_mode_lib dml;
502 * struct dc_state - The full description of a state requested by users
506 * @streams: Stream state properties
508 struct dc_stream_state *streams[MAX_PIPES];
511 * @stream_status: Planes status on a given stream
513 struct dc_stream_status stream_status[MAX_PIPES];
516 * @stream_count: Total of streams in use
518 uint8_t stream_count;
522 * @res_ctx: Persistent state of resources
524 struct resource_context res_ctx;
527 * @pp_display_cfg: PowerPlay clocks and settings
528 * Note: this is a big struct, do *not* put on stack!
530 struct dm_pp_display_configuration pp_display_cfg;
533 * @dcn_bw_vars: non-stack memory to support bandwidth calculations
534 * Note: this is a big struct, do *not* put on stack!
536 struct dcn_bw_internal_vars dcn_bw_vars;
538 struct clk_mgr *clk_mgr;
541 * @bw_ctx: The output from bandwidth and watermark calculations and the DML
543 * Each context must have its own instance of VBA, and in order to
544 * initialize and obtain IP and SOC, the base DML instance from DC is
545 * initially copied into every context.
547 struct bw_context bw_ctx;
550 * @refcount: refcount reference
552 * Notice that dc_state is used around the code to capture the current
553 * context, so we need to pass it everywhere. That's why we want to use
554 * kref in this struct.
556 struct kref refcount;
559 unsigned int stutter_period_us;
563 struct dc_bounding_box_max_clk {
570 #endif /* _CORE_TYPES_H_ */