drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services.h"
  27 #include "dc.h"
  28 #include "dc_bios_types.h"
  29 #include "core_types.h"
  30 #include "core_status.h"
  31 #include "resource.h"
  32 #include "dm_helpers.h"
  33 #include "dce110_hwseq.h"
  34 #include "dce110/dce110_timing_generator.h"
  35 #include "dce/dce_hwseq.h"
  36 #include "gpio_service_interface.h"
  37
  38 #include "dce110/dce110_compressor.h"
  39
  40 #include "bios/bios_parser_helper.h"
  41 #include "timing_generator.h"
  42 #include "mem_input.h"
  43 #include "opp.h"
  44 #include "ipp.h"
  45 #include "transform.h"
  46 #include "stream_encoder.h"
  47 #include "link_encoder.h"
  48 #include "link_enc_cfg.h"
  49 #include "link_hwss.h"
  50 #include "link.h"
  51 #include "dccg.h"
  52 #include "clock_source.h"
  53 #include "clk_mgr.h"
  54 #include "abm.h"
  55 #include "audio.h"
  56 #include "reg_helper.h"
  57 #include "panel_cntl.h"
  58 #include "dpcd_defs.h"
  59 /* include DCE11 register header files */
  60 #include "dce/dce_11_0_d.h"
  61 #include "dce/dce_11_0_sh_mask.h"
  62 #include "custom_float.h"
  63
  64 #include "atomfirmware.h"
  65
  66 #include "dcn10/dcn10_hwseq.h"
  67
  68 #include "dce110_hwseq.h"
  69
  70 #define GAMMA_HW_POINTS_NUM 256
  71
  72 /*
  73  * All values are in milliseconds;
  74  * For eDP, after power-up/power/down,
  75  * 300/500 msec max. delay from LCDVCC to black video generation
  76  */
  77 #define PANEL_POWER_UP_TIMEOUT 300
  78 #define PANEL_POWER_DOWN_TIMEOUT 500
  79 #define HPD_CHECK_INTERVAL 10
  80 #define OLED_POST_T7_DELAY 100
  81 #define OLED_PRE_T11_DELAY 150
  82
  83 #define CTX \
  84         hws->ctx
  85
  86 #define DC_LOGGER \
  87         ctx->logger
  88 #define DC_LOGGER_INIT() \
  89         struct dc_context *ctx = dc->ctx
  90
  91 #define REG(reg)\
  92         hws->regs->reg
  93
  94 #undef FN
  95 #define FN(reg_name, field_name) \
  96         hws->shifts->field_name, hws->masks->field_name
  97
  98 struct dce110_hw_seq_reg_offsets {
  99         uint32_t crtc;
 100 };
 101
 102 static const struct dce110_hw_seq_reg_offsets reg_offsets[] = {
 103 {
 104         .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
 105 },
 106 {
 107         .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
 108 },
 109 {
 110         .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
 111 },
 112 {
 113         .crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL),
 114 }
 115 };
 116
 117 #define HW_REG_BLND(reg, id)\
 118         (reg + reg_offsets[id].blnd)
 119
 120 #define HW_REG_CRTC(reg, id)\
 121         (reg + reg_offsets[id].crtc)
 122
 123 #define MAX_WATERMARK 0xFFFF
 124 #define SAFE_NBP_MARK 0x7FFF
 125
 126 /*******************************************************************************
 127  * Private definitions
 128  ******************************************************************************/
 129 /***************************PIPE_CONTROL***********************************/
 130 static void dce110_init_pte(struct dc_context *ctx)
 131 {
 132         uint32_t addr;
 133         uint32_t value = 0;
 134         uint32_t chunk_int = 0;
 135         uint32_t chunk_mul = 0;
 136
 137         addr = mmUNP_DVMM_PTE_CONTROL;
 138         value = dm_read_reg(ctx, addr);
 139
 140         set_reg_field_value(
 141                 value,
 142                 0,
 143                 DVMM_PTE_CONTROL,
 144                 DVMM_USE_SINGLE_PTE);
 145
 146         set_reg_field_value(
 147                 value,
 148                 1,
 149                 DVMM_PTE_CONTROL,
 150                 DVMM_PTE_BUFFER_MODE0);
 151
 152         set_reg_field_value(
 153                 value,
 154                 1,
 155                 DVMM_PTE_CONTROL,
 156                 DVMM_PTE_BUFFER_MODE1);
 157
 158         dm_write_reg(ctx, addr, value);
 159
 160         addr = mmDVMM_PTE_REQ;
 161         value = dm_read_reg(ctx, addr);
 162
 163         chunk_int = get_reg_field_value(
 164                 value,
 165                 DVMM_PTE_REQ,
 166                 HFLIP_PTEREQ_PER_CHUNK_INT);
 167
 168         chunk_mul = get_reg_field_value(
 169                 value,
 170                 DVMM_PTE_REQ,
 171                 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
 172
 173         if (chunk_int != 0x4 || chunk_mul != 0x4) {
 174
 175                 set_reg_field_value(
 176                         value,
 177                         255,
 178                         DVMM_PTE_REQ,
 179                         MAX_PTEREQ_TO_ISSUE);
 180
 181                 set_reg_field_value(
 182                         value,
 183                         4,
 184                         DVMM_PTE_REQ,
 185                         HFLIP_PTEREQ_PER_CHUNK_INT);
 186
 187                 set_reg_field_value(
 188                         value,
 189                         4,
 190                         DVMM_PTE_REQ,
 191                         HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
 192
 193                 dm_write_reg(ctx, addr, value);
 194         }
 195 }
 196 /**************************************************************************/
 197
 198 static void enable_display_pipe_clock_gating(
 199         struct dc_context *ctx,
 200         bool clock_gating)
 201 {
 202         /*TODO*/
 203 }
 204
 205 static bool dce110_enable_display_power_gating(
 206         struct dc *dc,
 207         uint8_t controller_id,
 208         struct dc_bios *dcb,
 209         enum pipe_gating_control power_gating)
 210 {
 211         enum bp_result bp_result = BP_RESULT_OK;
 212         enum bp_pipe_control_action cntl;
 213         struct dc_context *ctx = dc->ctx;
 214         unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
 215
 216         if (power_gating == PIPE_GATING_CONTROL_INIT)
 217                 cntl = ASIC_PIPE_INIT;
 218         else if (power_gating == PIPE_GATING_CONTROL_ENABLE)
 219                 cntl = ASIC_PIPE_ENABLE;
 220         else
 221                 cntl = ASIC_PIPE_DISABLE;
 222
 223         if (controller_id == underlay_idx)
 224                 controller_id = CONTROLLER_ID_UNDERLAY0 - 1;
 225
 226         if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0) {
 227
 228                 bp_result = dcb->funcs->enable_disp_power_gating(
 229                                                 dcb, controller_id + 1, cntl);
 230
 231                 /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2
 232                  * by default when command table is called
 233                  *
 234                  * Bios parser accepts controller_id = 6 as indicative of
 235                  * underlay pipe in dce110. But we do not support more
 236                  * than 3.
 237                  */
 238                 if (controller_id < CONTROLLER_ID_MAX - 1)
 239                         dm_write_reg(ctx,
 240                                 HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id),
 241                                 0);
 242         }
 243
 244         if (power_gating != PIPE_GATING_CONTROL_ENABLE)
 245                 dce110_init_pte(ctx);
 246
 247         if (bp_result == BP_RESULT_OK)
 248                 return true;
 249         else
 250                 return false;
 251 }
 252
 253 static void build_prescale_params(struct ipp_prescale_params *prescale_params,
 254                 const struct dc_plane_state *plane_state)
 255 {
 256         prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED;
 257
 258         switch (plane_state->format) {
 259         case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
 260                 prescale_params->scale = 0x2082;
 261                 break;
 262         case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
 263         case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
 264                 prescale_params->scale = 0x2020;
 265                 break;
 266         case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
 267         case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
 268                 prescale_params->scale = 0x2008;
 269                 break;
 270         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
 271         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
 272         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
 273                 prescale_params->scale = 0x2000;
 274                 break;
 275         default:
 276                 ASSERT(false);
 277                 break;
 278         }
 279 }
 280
 281 static bool
 282 dce110_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
 283                                const struct dc_plane_state *plane_state)
 284 {
 285         struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
 286         const struct dc_transfer_func *tf = NULL;
 287         struct ipp_prescale_params prescale_params = { 0 };
 288         bool result = true;
 289
 290         if (ipp == NULL)
 291                 return false;
 292
 293         if (plane_state->in_transfer_func)
 294                 tf = plane_state->in_transfer_func;
 295
 296         build_prescale_params(&prescale_params, plane_state);
 297         ipp->funcs->ipp_program_prescale(ipp, &prescale_params);
 298
 299         if (plane_state->gamma_correction &&
 300                         !plane_state->gamma_correction->is_identity &&
 301                         dce_use_lut(plane_state->format))
 302                 ipp->funcs->ipp_program_input_lut(ipp, plane_state->gamma_correction);
 303
 304         if (tf == NULL) {
 305                 /* Default case if no input transfer function specified */
 306                 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB);
 307         } else if (tf->type == TF_TYPE_PREDEFINED) {
 308                 switch (tf->tf) {
 309                 case TRANSFER_FUNCTION_SRGB:
 310                         ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB);
 311                         break;
 312                 case TRANSFER_FUNCTION_BT709:
 313                         ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_xvYCC);
 314                         break;
 315                 case TRANSFER_FUNCTION_LINEAR:
 316                         ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
 317                         break;
 318                 case TRANSFER_FUNCTION_PQ:
 319                 default:
 320                         result = false;
 321                         break;
 322                 }
 323         } else if (tf->type == TF_TYPE_BYPASS) {
 324                 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
 325         } else {
 326                 /*TF_TYPE_DISTRIBUTED_POINTS - Not supported in DCE 11*/
 327                 result = false;
 328         }
 329
 330         return result;
 331 }
 332
 333 static bool convert_to_custom_float(struct pwl_result_data *rgb_resulted,
 334                                     struct curve_points *arr_points,
 335                                     uint32_t hw_points_num)
 336 {
 337         struct custom_float_format fmt;
 338
 339         struct pwl_result_data *rgb = rgb_resulted;
 340
 341         uint32_t i = 0;
 342
 343         fmt.exponenta_bits = 6;
 344         fmt.mantissa_bits = 12;
 345         fmt.sign = true;
 346
 347         if (!convert_to_custom_float_format(arr_points[0].x, &fmt,
 348                                             &arr_points[0].custom_float_x)) {
 349                 BREAK_TO_DEBUGGER();
 350                 return false;
 351         }
 352
 353         if (!convert_to_custom_float_format(arr_points[0].offset, &fmt,
 354                                             &arr_points[0].custom_float_offset)) {
 355                 BREAK_TO_DEBUGGER();
 356                 return false;
 357         }
 358
 359         if (!convert_to_custom_float_format(arr_points[0].slope, &fmt,
 360                                             &arr_points[0].custom_float_slope)) {
 361                 BREAK_TO_DEBUGGER();
 362                 return false;
 363         }
 364
 365         fmt.mantissa_bits = 10;
 366         fmt.sign = false;
 367
 368         if (!convert_to_custom_float_format(arr_points[1].x, &fmt,
 369                                             &arr_points[1].custom_float_x)) {
 370                 BREAK_TO_DEBUGGER();
 371                 return false;
 372         }
 373
 374         if (!convert_to_custom_float_format(arr_points[1].y, &fmt,
 375                                             &arr_points[1].custom_float_y)) {
 376                 BREAK_TO_DEBUGGER();
 377                 return false;
 378         }
 379
 380         if (!convert_to_custom_float_format(arr_points[1].slope, &fmt,
 381                                             &arr_points[1].custom_float_slope)) {
 382                 BREAK_TO_DEBUGGER();
 383                 return false;
 384         }
 385
 386         fmt.mantissa_bits = 12;
 387         fmt.sign = true;
 388
 389         while (i != hw_points_num) {
 390                 if (!convert_to_custom_float_format(rgb->red, &fmt,
 391                                                     &rgb->red_reg)) {
 392                         BREAK_TO_DEBUGGER();
 393                         return false;
 394                 }
 395
 396                 if (!convert_to_custom_float_format(rgb->green, &fmt,
 397                                                     &rgb->green_reg)) {
 398                         BREAK_TO_DEBUGGER();
 399                         return false;
 400                 }
 401
 402                 if (!convert_to_custom_float_format(rgb->blue, &fmt,
 403                                                     &rgb->blue_reg)) {
 404                         BREAK_TO_DEBUGGER();
 405                         return false;
 406                 }
 407
 408                 if (!convert_to_custom_float_format(rgb->delta_red, &fmt,
 409                                                     &rgb->delta_red_reg)) {
 410                         BREAK_TO_DEBUGGER();
 411                         return false;
 412                 }
 413
 414                 if (!convert_to_custom_float_format(rgb->delta_green, &fmt,
 415                                                     &rgb->delta_green_reg)) {
 416                         BREAK_TO_DEBUGGER();
 417                         return false;
 418                 }
 419
 420                 if (!convert_to_custom_float_format(rgb->delta_blue, &fmt,
 421                                                     &rgb->delta_blue_reg)) {
 422                         BREAK_TO_DEBUGGER();
 423                         return false;
 424                 }
 425
 426                 ++rgb;
 427                 ++i;
 428         }
 429
 430         return true;
 431 }
 432
 433 #define MAX_LOW_POINT      25
 434 #define NUMBER_REGIONS     16
 435 #define NUMBER_SW_SEGMENTS 16
 436
 437 static bool
 438 dce110_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf,
 439                                       struct pwl_params *regamma_params)
 440 {
 441         struct curve_points *arr_points;
 442         struct pwl_result_data *rgb_resulted;
 443         struct pwl_result_data *rgb;
 444         struct pwl_result_data *rgb_plus_1;
 445         struct fixed31_32 y_r;
 446         struct fixed31_32 y_g;
 447         struct fixed31_32 y_b;
 448         struct fixed31_32 y1_min;
 449         struct fixed31_32 y3_max;
 450
 451         int32_t region_start, region_end;
 452         uint32_t i, j, k, seg_distr[NUMBER_REGIONS], increment, start_index, hw_points;
 453
 454         if (output_tf == NULL || regamma_params == NULL || output_tf->type == TF_TYPE_BYPASS)
 455                 return false;
 456
 457         arr_points = regamma_params->arr_points;
 458         rgb_resulted = regamma_params->rgb_resulted;
 459         hw_points = 0;
 460
 461         memset(regamma_params, 0, sizeof(struct pwl_params));
 462
 463         if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
 464                 /* 16 segments
 465                  * segments are from 2^-11 to 2^5
 466                  */
 467                 region_start = -11;
 468                 region_end = region_start + NUMBER_REGIONS;
 469
 470                 for (i = 0; i < NUMBER_REGIONS; i++)
 471                         seg_distr[i] = 4;
 472
 473         } else {
 474                 /* 10 segments
 475                  * segment is from 2^-10 to 2^1
 476                  * We include an extra segment for range [2^0, 2^1). This is to
 477                  * ensure that colors with normalized values of 1 don't miss the
 478                  * LUT.
 479                  */
 480                 region_start = -10;
 481                 region_end = 1;
 482
 483                 seg_distr[0] = 4;
 484                 seg_distr[1] = 4;
 485                 seg_distr[2] = 4;
 486                 seg_distr[3] = 4;
 487                 seg_distr[4] = 4;
 488                 seg_distr[5] = 4;
 489                 seg_distr[6] = 4;
 490                 seg_distr[7] = 4;
 491                 seg_distr[8] = 4;
 492                 seg_distr[9] = 4;
 493                 seg_distr[10] = 0;
 494                 seg_distr[11] = -1;
 495                 seg_distr[12] = -1;
 496                 seg_distr[13] = -1;
 497                 seg_distr[14] = -1;
 498                 seg_distr[15] = -1;
 499         }
 500
 501         for (k = 0; k < 16; k++) {
 502                 if (seg_distr[k] != -1)
 503                         hw_points += (1 << seg_distr[k]);
 504         }
 505
 506         j = 0;
 507         for (k = 0; k < (region_end - region_start); k++) {
 508                 increment = NUMBER_SW_SEGMENTS / (1 << seg_distr[k]);
 509                 start_index = (region_start + k + MAX_LOW_POINT) *
 510                                 NUMBER_SW_SEGMENTS;
 511                 for (i = start_index; i < start_index + NUMBER_SW_SEGMENTS;
 512                                 i += increment) {
 513                         if (j == hw_points - 1)
 514                                 break;
 515                         rgb_resulted[j].red = output_tf->tf_pts.red[i];
 516                         rgb_resulted[j].green = output_tf->tf_pts.green[i];
 517                         rgb_resulted[j].blue = output_tf->tf_pts.blue[i];
 518                         j++;
 519                 }
 520         }
 521
 522         /* last point */
 523         start_index = (region_end + MAX_LOW_POINT) * NUMBER_SW_SEGMENTS;
 524         rgb_resulted[hw_points - 1].red = output_tf->tf_pts.red[start_index];
 525         rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index];
 526         rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index];
 527
 528         arr_points[0].x = dc_fixpt_pow(dc_fixpt_from_int(2),
 529                                              dc_fixpt_from_int(region_start));
 530         arr_points[1].x = dc_fixpt_pow(dc_fixpt_from_int(2),
 531                                              dc_fixpt_from_int(region_end));
 532
 533         y_r = rgb_resulted[0].red;
 534         y_g = rgb_resulted[0].green;
 535         y_b = rgb_resulted[0].blue;
 536
 537         y1_min = dc_fixpt_min(y_r, dc_fixpt_min(y_g, y_b));
 538
 539         arr_points[0].y = y1_min;
 540         arr_points[0].slope = dc_fixpt_div(arr_points[0].y,
 541                                                  arr_points[0].x);
 542
 543         y_r = rgb_resulted[hw_points - 1].red;
 544         y_g = rgb_resulted[hw_points - 1].green;
 545         y_b = rgb_resulted[hw_points - 1].blue;
 546
 547         /* see comment above, m_arrPoints[1].y should be the Y value for the
 548          * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1)
 549          */
 550         y3_max = dc_fixpt_max(y_r, dc_fixpt_max(y_g, y_b));
 551
 552         arr_points[1].y = y3_max;
 553
 554         arr_points[1].slope = dc_fixpt_zero;
 555
 556         if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
 557                 /* for PQ, we want to have a straight line from last HW X point,
 558                  * and the slope to be such that we hit 1.0 at 10000 nits.
 559                  */
 560                 const struct fixed31_32 end_value = dc_fixpt_from_int(125);
 561
 562                 arr_points[1].slope = dc_fixpt_div(
 563                                 dc_fixpt_sub(dc_fixpt_one, arr_points[1].y),
 564                                 dc_fixpt_sub(end_value, arr_points[1].x));
 565         }
 566
 567         regamma_params->hw_points_num = hw_points;
 568
 569         k = 0;
 570         for (i = 1; i < 16; i++) {
 571                 if (seg_distr[k] != -1) {
 572                         regamma_params->arr_curve_points[k].segments_num = seg_distr[k];
 573                         regamma_params->arr_curve_points[i].offset =
 574                                         regamma_params->arr_curve_points[k].offset + (1 << seg_distr[k]);
 575                 }
 576                 k++;
 577         }
 578
 579         if (seg_distr[k] != -1)
 580                 regamma_params->arr_curve_points[k].segments_num = seg_distr[k];
 581
 582         rgb = rgb_resulted;
 583         rgb_plus_1 = rgb_resulted + 1;
 584
 585         i = 1;
 586
 587         while (i != hw_points + 1) {
 588                 if (dc_fixpt_lt(rgb_plus_1->red, rgb->red))
 589                         rgb_plus_1->red = rgb->red;
 590                 if (dc_fixpt_lt(rgb_plus_1->green, rgb->green))
 591                         rgb_plus_1->green = rgb->green;
 592                 if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue))
 593                         rgb_plus_1->blue = rgb->blue;
 594
 595                 rgb->delta_red = dc_fixpt_sub(rgb_plus_1->red, rgb->red);
 596                 rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green);
 597                 rgb->delta_blue = dc_fixpt_sub(rgb_plus_1->blue, rgb->blue);
 598
 599                 ++rgb_plus_1;
 600                 ++rgb;
 601                 ++i;
 602         }
 603
 604         convert_to_custom_float(rgb_resulted, arr_points, hw_points);
 605
 606         return true;
 607 }
 608
 609 static bool
 610 dce110_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
 611                                 const struct dc_stream_state *stream)
 612 {
 613         struct transform *xfm = pipe_ctx->plane_res.xfm;
 614
 615         xfm->funcs->opp_power_on_regamma_lut(xfm, true);
 616         xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
 617
 618         if (stream->out_transfer_func &&
 619             stream->out_transfer_func->type == TF_TYPE_PREDEFINED &&
 620             stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB) {
 621                 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB);
 622         } else if (dce110_translate_regamma_to_hw_format(stream->out_transfer_func,
 623                                                          &xfm->regamma_params)) {
 624                 xfm->funcs->opp_program_regamma_pwl(xfm, &xfm->regamma_params);
 625                 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_USER);
 626         } else {
 627                 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_BYPASS);
 628         }
 629
 630         xfm->funcs->opp_power_on_regamma_lut(xfm, false);
 631
 632         return true;
 633 }
 634
 635 void dce110_update_info_frame(struct pipe_ctx *pipe_ctx)
 636 {
 637         bool is_hdmi_tmds;
 638         bool is_dp;
 639
 640         ASSERT(pipe_ctx->stream);
 641
 642         if (pipe_ctx->stream_res.stream_enc == NULL)
 643                 return;  /* this is not root pipe */
 644
 645         is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal);
 646         is_dp = dc_is_dp_signal(pipe_ctx->stream->signal);
 647
 648         if (!is_hdmi_tmds && !is_dp)
 649                 return;
 650
 651         if (is_hdmi_tmds)
 652                 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(
 653                         pipe_ctx->stream_res.stream_enc,
 654                         &pipe_ctx->stream_res.encoder_info_frame);
 655         else {
 656                 if (pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num)
 657                         pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num(
 658                                 pipe_ctx->stream_res.stream_enc,
 659                                 &pipe_ctx->stream_res.encoder_info_frame);
 660
 661                 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(
 662                         pipe_ctx->stream_res.stream_enc,
 663                         &pipe_ctx->stream_res.encoder_info_frame);
 664         }
 665 }
 666
 667 void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
 668 {
 669         enum dc_lane_count lane_count =
 670                 pipe_ctx->stream->link->cur_link_settings.lane_count;
 671         struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
 672         struct dc_link *link = pipe_ctx->stream->link;
 673         const struct dc *dc = link->dc;
 674         const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
 675         uint32_t active_total_with_borders;
 676         uint32_t early_control = 0;
 677         struct timing_generator *tg = pipe_ctx->stream_res.tg;
 678
 679         link_hwss->setup_stream_encoder(pipe_ctx);
 680
 681         dc->hwss.update_info_frame(pipe_ctx);
 682
 683         /* enable early control to avoid corruption on DP monitor*/
 684         active_total_with_borders =
 685                         timing->h_addressable
 686                                 + timing->h_border_left
 687                                 + timing->h_border_right;
 688
 689         if (lane_count != 0)
 690                 early_control = active_total_with_borders % lane_count;
 691
 692         if (early_control == 0)
 693                 early_control = lane_count;
 694
 695         tg->funcs->set_early_control(tg, early_control);
 696 }
 697
 698 static enum bp_result link_transmitter_control(
 699                 struct dc_bios *bios,
 700         struct bp_transmitter_control *cntl)
 701 {
 702         enum bp_result result;
 703
 704         result = bios->funcs->transmitter_control(bios, cntl);
 705
 706         return result;
 707 }
 708
 709 /*
 710  * @brief
 711  * eDP only.
 712  */
 713 void dce110_edp_wait_for_hpd_ready(
 714                 struct dc_link *link,
 715                 bool power_up)
 716 {
 717         struct dc_context *ctx = link->ctx;
 718         struct graphics_object_id connector = link->link_enc->connector;
 719         struct gpio *hpd;
 720         bool edp_hpd_high = false;
 721         uint32_t time_elapsed = 0;
 722         uint32_t timeout = power_up ?
 723                 PANEL_POWER_UP_TIMEOUT : PANEL_POWER_DOWN_TIMEOUT;
 724
 725         if (dal_graphics_object_id_get_connector_id(connector)
 726                         != CONNECTOR_ID_EDP) {
 727                 BREAK_TO_DEBUGGER();
 728                 return;
 729         }
 730
 731         if (!power_up)
 732                 /*
 733                  * From KV, we will not HPD low after turning off VCC -
 734                  * instead, we will check the SW timer in power_up().
 735                  */
 736                 return;
 737
 738         /*
 739          * When we power on/off the eDP panel,
 740          * we need to wait until SENSE bit is high/low.
 741          */
 742
 743         /* obtain HPD */
 744         /* TODO what to do with this? */
 745         hpd = ctx->dc->link_srv->get_hpd_gpio(ctx->dc_bios, connector, ctx->gpio_service);
 746
 747         if (!hpd) {
 748                 BREAK_TO_DEBUGGER();
 749                 return;
 750         }
 751
 752         if (link != NULL) {
 753                 if (link->panel_config.pps.extra_t3_ms > 0) {
 754                         int extra_t3_in_ms = link->panel_config.pps.extra_t3_ms;
 755
 756                         msleep(extra_t3_in_ms);
 757                 }
 758         }
 759
 760         dal_gpio_open(hpd, GPIO_MODE_INTERRUPT);
 761
 762         /* wait until timeout or panel detected */
 763
 764         do {
 765                 uint32_t detected = 0;
 766
 767                 dal_gpio_get_value(hpd, &detected);
 768
 769                 if (!(detected ^ power_up)) {
 770                         edp_hpd_high = true;
 771                         break;
 772                 }
 773
 774                 msleep(HPD_CHECK_INTERVAL);
 775
 776                 time_elapsed += HPD_CHECK_INTERVAL;
 777         } while (time_elapsed < timeout);
 778
 779         dal_gpio_close(hpd);
 780
 781         dal_gpio_destroy_irq(&hpd);
 782
 783         /* ensure that the panel is detected */
 784         if (!edp_hpd_high)
 785                 DC_LOG_DC("%s: wait timed out!\n", __func__);
 786 }
 787
 788 void dce110_edp_power_control(
 789                 struct dc_link *link,
 790                 bool power_up)
 791 {
 792         struct dc_context *ctx = link->ctx;
 793         struct bp_transmitter_control cntl = { 0 };
 794         enum bp_result bp_result;
 795         uint8_t panel_instance;
 796
 797
 798         if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
 799                         != CONNECTOR_ID_EDP) {
 800                 BREAK_TO_DEBUGGER();
 801                 return;
 802         }
 803
 804         if (!link->panel_cntl)
 805                 return;
 806         if (power_up !=
 807                 link->panel_cntl->funcs->is_panel_powered_on(link->panel_cntl)) {
 808
 809                 unsigned long long current_ts = dm_get_timestamp(ctx);
 810                 unsigned long long time_since_edp_poweroff_ms =
 811                                 div64_u64(dm_get_elapse_time_in_ns(
 812                                                 ctx,
 813                                                 current_ts,
 814                                                 ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link)), 1000000);
 815                 unsigned long long time_since_edp_poweron_ms =
 816                                 div64_u64(dm_get_elapse_time_in_ns(
 817                                                 ctx,
 818                                                 current_ts,
 819                                                 ctx->dc->link_srv->dp_trace_get_edp_poweron_timestamp(link)), 1000000);
 820                 DC_LOG_HW_RESUME_S3(
 821                                 "%s: transition: power_up=%d current_ts=%llu edp_poweroff=%llu edp_poweron=%llu time_since_edp_poweroff_ms=%llu time_since_edp_poweron_ms=%llu",
 822                                 __func__,
 823                                 power_up,
 824                                 current_ts,
 825                                 ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link),
 826                                 ctx->dc->link_srv->dp_trace_get_edp_poweron_timestamp(link),
 827                                 time_since_edp_poweroff_ms,
 828                                 time_since_edp_poweron_ms);
 829
 830                 /* Send VBIOS command to prompt eDP panel power */
 831                 if (power_up) {
 832                         /* edp requires a min of 500ms from LCDVDD off to on */
 833                         unsigned long long remaining_min_edp_poweroff_time_ms = 500;
 834
 835                         /* add time defined by a patch, if any (usually patch extra_t12_ms is 0) */
 836                         if (link->local_sink != NULL)
 837                                 remaining_min_edp_poweroff_time_ms +=
 838                                         link->panel_config.pps.extra_t12_ms;
 839
 840                         /* Adjust remaining_min_edp_poweroff_time_ms if this is not the first time. */
 841                         if (ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link) != 0) {
 842                                 if (time_since_edp_poweroff_ms < remaining_min_edp_poweroff_time_ms)
 843                                         remaining_min_edp_poweroff_time_ms =
 844                                                 remaining_min_edp_poweroff_time_ms - time_since_edp_poweroff_ms;
 845                                 else
 846                                         remaining_min_edp_poweroff_time_ms = 0;
 847                         }
 848
 849                         if (remaining_min_edp_poweroff_time_ms) {
 850                                 DC_LOG_HW_RESUME_S3(
 851                                                 "%s: remaining_min_edp_poweroff_time_ms=%llu: begin wait.\n",
 852                                                 __func__, remaining_min_edp_poweroff_time_ms);
 853                                 msleep(remaining_min_edp_poweroff_time_ms);
 854                                 DC_LOG_HW_RESUME_S3(
 855                                                 "%s: remaining_min_edp_poweroff_time_ms=%llu: end wait.\n",
 856                                                 __func__, remaining_min_edp_poweroff_time_ms);
 857                                 dm_output_to_console("%s: wait %lld ms to power on eDP.\n",
 858                                                 __func__, remaining_min_edp_poweroff_time_ms);
 859                         } else {
 860                                 DC_LOG_HW_RESUME_S3(
 861                                                 "%s: remaining_min_edp_poweroff_time_ms=%llu: no wait required.\n",
 862                                                 __func__, remaining_min_edp_poweroff_time_ms);
 863                         }
 864                 }
 865
 866                 DC_LOG_HW_RESUME_S3(
 867                                 "%s: BEGIN: Panel Power action: %s\n",
 868                                 __func__, (power_up ? "On":"Off"));
 869
 870                 cntl.action = power_up ?
 871                         TRANSMITTER_CONTROL_POWER_ON :
 872                         TRANSMITTER_CONTROL_POWER_OFF;
 873                 cntl.transmitter = link->link_enc->transmitter;
 874                 cntl.connector_obj_id = link->link_enc->connector;
 875                 cntl.coherent = false;
 876                 cntl.lanes_number = LANE_COUNT_FOUR;
 877                 cntl.hpd_sel = link->link_enc->hpd_source;
 878                 panel_instance = link->panel_cntl->inst;
 879
 880                 if (ctx->dc->ctx->dmub_srv &&
 881                                 ctx->dc->debug.dmub_command_table) {
 882
 883                         if (cntl.action == TRANSMITTER_CONTROL_POWER_ON) {
 884                                 bp_result = ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,
 885                                                 LVTMA_CONTROL_POWER_ON,
 886                                                 panel_instance, link->link_powered_externally);
 887                         } else {
 888                                 bp_result = ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,
 889                                                 LVTMA_CONTROL_POWER_OFF,
 890                                                 panel_instance, link->link_powered_externally);
 891                         }
 892                 }
 893
 894                 bp_result = link_transmitter_control(ctx->dc_bios, &cntl);
 895
 896                 DC_LOG_HW_RESUME_S3(
 897                                 "%s: END: Panel Power action: %s bp_result=%u\n",
 898                                 __func__, (power_up ? "On":"Off"),
 899                                 bp_result);
 900
 901                 ctx->dc->link_srv->dp_trace_set_edp_power_timestamp(link, power_up);
 902
 903                 DC_LOG_HW_RESUME_S3(
 904                                 "%s: updated values: edp_poweroff=%llu edp_poweron=%llu\n",
 905                                 __func__,
 906                                 ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link),
 907                                 ctx->dc->link_srv->dp_trace_get_edp_poweron_timestamp(link));
 908
 909                 if (bp_result != BP_RESULT_OK)
 910                         DC_LOG_ERROR(
 911                                         "%s: Panel Power bp_result: %d\n",
 912                                         __func__, bp_result);
 913         } else {
 914                 DC_LOG_HW_RESUME_S3(
 915                                 "%s: Skipping Panel Power action: %s\n",
 916                                 __func__, (power_up ? "On":"Off"));
 917         }
 918 }
 919
 920 void dce110_edp_wait_for_T12(
 921                 struct dc_link *link)
 922 {
 923         struct dc_context *ctx = link->ctx;
 924
 925         if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
 926                         != CONNECTOR_ID_EDP) {
 927                 BREAK_TO_DEBUGGER();
 928                 return;
 929         }
 930
 931         if (!link->panel_cntl)
 932                 return;
 933
 934         if (!link->panel_cntl->funcs->is_panel_powered_on(link->panel_cntl) &&
 935                         ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link) != 0) {
 936                 unsigned int t12_duration = 500; // Default T12 as per spec
 937                 unsigned long long current_ts = dm_get_timestamp(ctx);
 938                 unsigned long long time_since_edp_poweroff_ms =
 939                                 div64_u64(dm_get_elapse_time_in_ns(
 940                                                 ctx,
 941                                                 current_ts,
 942                                                 ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link)), 1000000);
 943
 944                 t12_duration += link->panel_config.pps.extra_t12_ms; // Add extra T12
 945
 946                 if (time_since_edp_poweroff_ms < t12_duration)
 947                         msleep(t12_duration - time_since_edp_poweroff_ms);
 948         }
 949 }
 950 /*todo: cloned in stream enc, fix*/
 951 /*
 952  * @brief
 953  * eDP only. Control the backlight of the eDP panel
 954  */
 955 void dce110_edp_backlight_control(
 956                 struct dc_link *link,
 957                 bool enable)
 958 {
 959         struct dc_context *ctx = link->ctx;
 960         struct bp_transmitter_control cntl = { 0 };
 961         uint8_t panel_instance;
 962         unsigned int pre_T11_delay = OLED_PRE_T11_DELAY;
 963         unsigned int post_T7_delay = OLED_POST_T7_DELAY;
 964
 965         if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
 966                 != CONNECTOR_ID_EDP) {
 967                 BREAK_TO_DEBUGGER();
 968                 return;
 969         }
 970
 971         if (link->panel_cntl && !(link->dpcd_sink_ext_caps.bits.oled ||
 972                 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 ||
 973                 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1)) {
 974                 bool is_backlight_on = link->panel_cntl->funcs->is_panel_backlight_on(link->panel_cntl);
 975
 976                 if ((enable && is_backlight_on) || (!enable && !is_backlight_on)) {
 977                         DC_LOG_HW_RESUME_S3(
 978                                 "%s: panel already powered up/off. Do nothing.\n",
 979                                 __func__);
 980                         return;
 981                 }
 982         }
 983
 984         /* Send VBIOS command to control eDP panel backlight */
 985
 986         DC_LOG_HW_RESUME_S3(
 987                         "%s: backlight action: %s\n",
 988                         __func__, (enable ? "On":"Off"));
 989
 990         cntl.action = enable ?
 991                 TRANSMITTER_CONTROL_BACKLIGHT_ON :
 992                 TRANSMITTER_CONTROL_BACKLIGHT_OFF;
 993
 994         /*cntl.engine_id = ctx->engine;*/
 995         cntl.transmitter = link->link_enc->transmitter;
 996         cntl.connector_obj_id = link->link_enc->connector;
 997         /*todo: unhardcode*/
 998         cntl.lanes_number = LANE_COUNT_FOUR;
 999         cntl.hpd_sel = link->link_enc->hpd_source;
1000         cntl.signal = SIGNAL_TYPE_EDP;
1001
1002         /* For eDP, the following delays might need to be considered
1003          * after link training completed:
1004          * idle period - min. accounts for required BS-Idle pattern,
1005          * max. allows for source frame synchronization);
1006          * 50 msec max. delay from valid video data from source
1007          * to video on dislpay or backlight enable.
1008          *
1009          * Disable the delay for now.
1010          * Enable it in the future if necessary.
1011          */
1012         /* dc_service_sleep_in_milliseconds(50); */
1013                 /*edp 1.2*/
1014         panel_instance = link->panel_cntl->inst;
1015
1016         if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON) {
1017                 if (!link->dc->config.edp_no_power_sequencing)
1018                 /*
1019                  * Sometimes, DP receiver chip power-controlled externally by an
1020                  * Embedded Controller could be treated and used as eDP,
1021                  * if it drives mobile display. In this case,
1022                  * we shouldn't be doing power-sequencing, hence we can skip
1023                  * waiting for T7-ready.
1024                  */
1025                         ctx->dc->link_srv->edp_receiver_ready_T7(link);
1026                 else
1027                         DC_LOG_DC("edp_receiver_ready_T7 skipped\n");
1028         }
1029
1030         /* Setting link_powered_externally will bypass delays in the backlight
1031          * as they are not required if the link is being powered by a different
1032          * source.
1033          */
1034         if (ctx->dc->ctx->dmub_srv &&
1035                         ctx->dc->debug.dmub_command_table) {
1036                 if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON)
1037                         ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,
1038                                         LVTMA_CONTROL_LCD_BLON,
1039                                         panel_instance, link->link_powered_externally);
1040                 else
1041                         ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,
1042                                         LVTMA_CONTROL_LCD_BLOFF,
1043                                         panel_instance, link->link_powered_externally);
1044         }
1045
1046         link_transmitter_control(ctx->dc_bios, &cntl);
1047
1048         if (enable && link->dpcd_sink_ext_caps.bits.oled &&
1049             !link->dc->config.edp_no_power_sequencing) {
1050                 post_T7_delay += link->panel_config.pps.extra_post_t7_ms;
1051                 msleep(post_T7_delay);
1052         }
1053
1054         if (link->dpcd_sink_ext_caps.bits.oled ||
1055                 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 ||
1056                 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1)
1057                 ctx->dc->link_srv->edp_backlight_enable_aux(link, enable);
1058
1059         /*edp 1.2*/
1060         if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_OFF) {
1061                 if (!link->dc->config.edp_no_power_sequencing)
1062                 /*
1063                  * Sometimes, DP receiver chip power-controlled externally by an
1064                  * Embedded Controller could be treated and used as eDP,
1065                  * if it drives mobile display. In this case,
1066                  * we shouldn't be doing power-sequencing, hence we can skip
1067                  * waiting for T9-ready.
1068                  */
1069                         ctx->dc->link_srv->edp_add_delay_for_T9(link);
1070                 else
1071                         DC_LOG_DC("edp_receiver_ready_T9 skipped\n");
1072         }
1073
1074         if (!enable && link->dpcd_sink_ext_caps.bits.oled) {
1075                 pre_T11_delay += link->panel_config.pps.extra_pre_t11_ms;
1076                 msleep(pre_T11_delay);
1077         }
1078 }
1079
1080 void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx)
1081 {
1082         /* notify audio driver for audio modes of monitor */
1083         struct dc *dc;
1084         struct clk_mgr *clk_mgr;
1085         unsigned int i, num_audio = 1;
1086         const struct link_hwss *link_hwss;
1087
1088         if (!pipe_ctx->stream)
1089                 return;
1090
1091         dc = pipe_ctx->stream->ctx->dc;
1092         clk_mgr = dc->clk_mgr;
1093         link_hwss = get_link_hwss(pipe_ctx->stream->link, &pipe_ctx->link_res);
1094
1095         if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == true)
1096                 return;
1097
1098         if (pipe_ctx->stream_res.audio) {
1099                 for (i = 0; i < MAX_PIPES; i++) {
1100                         /*current_state not updated yet*/
1101                         if (dc->current_state->res_ctx.pipe_ctx[i].stream_res.audio != NULL)
1102                                 num_audio++;
1103                 }
1104
1105                 pipe_ctx->stream_res.audio->funcs->az_enable(pipe_ctx->stream_res.audio);
1106
1107                 if (num_audio >= 1 && clk_mgr->funcs->enable_pme_wa)
1108                         /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/
1109                         clk_mgr->funcs->enable_pme_wa(clk_mgr);
1110
1111                 link_hwss->enable_audio_packet(pipe_ctx);
1112
1113                 if (pipe_ctx->stream_res.audio)
1114                         pipe_ctx->stream_res.audio->enabled = true;
1115         }
1116 }
1117
1118 void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx)
1119 {
1120         struct dc *dc;
1121         struct clk_mgr *clk_mgr;
1122         const struct link_hwss *link_hwss;
1123
1124         if (!pipe_ctx || !pipe_ctx->stream)
1125                 return;
1126
1127         dc = pipe_ctx->stream->ctx->dc;
1128         clk_mgr = dc->clk_mgr;
1129         link_hwss = get_link_hwss(pipe_ctx->stream->link, &pipe_ctx->link_res);
1130
1131         if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == false)
1132                 return;
1133
1134         link_hwss->disable_audio_packet(pipe_ctx);
1135
1136         if (pipe_ctx->stream_res.audio) {
1137                 pipe_ctx->stream_res.audio->enabled = false;
1138
1139                 if (clk_mgr->funcs->enable_pme_wa)
1140                         /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/
1141                         clk_mgr->funcs->enable_pme_wa(clk_mgr);
1142
1143                 /* TODO: notify audio driver for if audio modes list changed
1144                  * add audio mode list change flag */
1145                 /* dal_audio_disable_azalia_audio_jack_presence(stream->audio,
1146                  * stream->stream_engine_id);
1147                  */
1148         }
1149 }
1150
1151 void dce110_disable_stream(struct pipe_ctx *pipe_ctx)
1152 {
1153         struct dc_stream_state *stream = pipe_ctx->stream;
1154         struct dc_link *link = stream->link;
1155         struct dc *dc = pipe_ctx->stream->ctx->dc;
1156         const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
1157         struct dccg *dccg = dc->res_pool->dccg;
1158         struct timing_generator *tg = pipe_ctx->stream_res.tg;
1159         struct dtbclk_dto_params dto_params = {0};
1160         int dp_hpo_inst;
1161         struct link_encoder *link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link);
1162         struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;
1163
1164         if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal)) {
1165                 pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets(
1166                         pipe_ctx->stream_res.stream_enc);
1167                 pipe_ctx->stream_res.stream_enc->funcs->hdmi_reset_stream_attribute(
1168                         pipe_ctx->stream_res.stream_enc);
1169         }
1170
1171         if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
1172                 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->stop_dp_info_packets(
1173                                         pipe_ctx->stream_res.hpo_dp_stream_enc);
1174         } else if (dc_is_dp_signal(pipe_ctx->stream->signal))
1175                 pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets(
1176                         pipe_ctx->stream_res.stream_enc);
1177
1178         dc->hwss.disable_audio_stream(pipe_ctx);
1179
1180         link_hwss->reset_stream_encoder(pipe_ctx);
1181
1182         if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx) && dccg) {
1183                 dto_params.otg_inst = tg->inst;
1184                 dto_params.timing = &pipe_ctx->stream->timing;
1185                 dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst;
1186
1187                 dccg->funcs->set_dtbclk_dto(dccg, &dto_params);
1188                 dccg->funcs->disable_symclk32_se(dccg, dp_hpo_inst);
1189                 dccg->funcs->set_dpstreamclk(dccg, REFCLK, tg->inst, dp_hpo_inst);
1190         } else if (dccg && dccg->funcs->disable_symclk_se) {
1191                 dccg->funcs->disable_symclk_se(dccg, stream_enc->stream_enc_inst,
1192                                                link_enc->transmitter - TRANSMITTER_UNIPHY_A);
1193         }
1194
1195         if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
1196                 /* TODO: This looks like a bug to me as we are disabling HPO IO when
1197                  * we are just disabling a single HPO stream. Shouldn't we disable HPO
1198                  * HW control only when HPOs for all streams are disabled?
1199                  */
1200                 if (pipe_ctx->stream->ctx->dc->hwseq->funcs.setup_hpo_hw_control)
1201                         pipe_ctx->stream->ctx->dc->hwseq->funcs.setup_hpo_hw_control(
1202                                         pipe_ctx->stream->ctx->dc->hwseq, false);
1203         }
1204 }
1205
1206 void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
1207                 struct dc_link_settings *link_settings)
1208 {
1209         struct encoder_unblank_param params = { { 0 } };
1210         struct dc_stream_state *stream = pipe_ctx->stream;
1211         struct dc_link *link = stream->link;
1212         struct dce_hwseq *hws = link->dc->hwseq;
1213
1214         /* only 3 items below are used by unblank */
1215         params.timing = pipe_ctx->stream->timing;
1216         params.link_settings.link_rate = link_settings->link_rate;
1217
1218         if (dc_is_dp_signal(pipe_ctx->stream->signal))
1219                 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, &params);
1220
1221         if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1222                 hws->funcs.edp_backlight_control(link, true);
1223         }
1224 }
1225
1226 void dce110_blank_stream(struct pipe_ctx *pipe_ctx)
1227 {
1228         struct dc_stream_state *stream = pipe_ctx->stream;
1229         struct dc_link *link = stream->link;
1230         struct dce_hwseq *hws = link->dc->hwseq;
1231
1232         if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1233                 if (!link->skip_implict_edp_power_control)
1234                         hws->funcs.edp_backlight_control(link, false);
1235                 link->dc->hwss.set_abm_immediate_disable(pipe_ctx);
1236         }
1237
1238         if (link->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
1239                 /* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */
1240                 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_blank(
1241                                 pipe_ctx->stream_res.hpo_dp_stream_enc);
1242         } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
1243                 pipe_ctx->stream_res.stream_enc->funcs->dp_blank(link, pipe_ctx->stream_res.stream_enc);
1244
1245                 if (!dc_is_embedded_signal(pipe_ctx->stream->signal)) {
1246                         /*
1247                          * After output is idle pattern some sinks need time to recognize the stream
1248                          * has changed or they enter protection state and hang.
1249                          */
1250                         msleep(60);
1251                 } else if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) {
1252                         if (!link->dc->config.edp_no_power_sequencing) {
1253                                 /*
1254                                  * Sometimes, DP receiver chip power-controlled externally by an
1255                                  * Embedded Controller could be treated and used as eDP,
1256                                  * if it drives mobile display. In this case,
1257                                  * we shouldn't be doing power-sequencing, hence we can skip
1258                                  * waiting for T9-ready.
1259                                  */
1260                                 link->dc->link_srv->edp_receiver_ready_T9(link);
1261                         }
1262                 }
1263         }
1264
1265 }
1266
1267
1268 void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
1269 {
1270         if (pipe_ctx != NULL && pipe_ctx->stream_res.stream_enc != NULL)
1271                 pipe_ctx->stream_res.stream_enc->funcs->set_avmute(pipe_ctx->stream_res.stream_enc, enable);
1272 }
1273
1274 static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id)
1275 {
1276         switch (crtc_id) {
1277         case CONTROLLER_ID_D0:
1278                 return DTO_SOURCE_ID0;
1279         case CONTROLLER_ID_D1:
1280                 return DTO_SOURCE_ID1;
1281         case CONTROLLER_ID_D2:
1282                 return DTO_SOURCE_ID2;
1283         case CONTROLLER_ID_D3:
1284                 return DTO_SOURCE_ID3;
1285         case CONTROLLER_ID_D4:
1286                 return DTO_SOURCE_ID4;
1287         case CONTROLLER_ID_D5:
1288                 return DTO_SOURCE_ID5;
1289         default:
1290                 return DTO_SOURCE_UNKNOWN;
1291         }
1292 }
1293
1294 static void build_audio_output(
1295         struct dc_state *state,
1296         const struct pipe_ctx *pipe_ctx,
1297         struct audio_output *audio_output)
1298 {
1299         const struct dc_stream_state *stream = pipe_ctx->stream;
1300         audio_output->engine_id = pipe_ctx->stream_res.stream_enc->id;
1301
1302         audio_output->signal = pipe_ctx->stream->signal;
1303
1304         /* audio_crtc_info  */
1305
1306         audio_output->crtc_info.h_total =
1307                 stream->timing.h_total;
1308
1309         /*
1310          * Audio packets are sent during actual CRTC blank physical signal, we
1311          * need to specify actual active signal portion
1312          */
1313         audio_output->crtc_info.h_active =
1314                         stream->timing.h_addressable
1315                         + stream->timing.h_border_left
1316                         + stream->timing.h_border_right;
1317
1318         audio_output->crtc_info.v_active =
1319                         stream->timing.v_addressable
1320                         + stream->timing.v_border_top
1321                         + stream->timing.v_border_bottom;
1322
1323         audio_output->crtc_info.pixel_repetition = 1;
1324
1325         audio_output->crtc_info.interlaced =
1326                         stream->timing.flags.INTERLACE;
1327
1328         audio_output->crtc_info.refresh_rate =
1329                 (stream->timing.pix_clk_100hz*100)/
1330                 (stream->timing.h_total*stream->timing.v_total);
1331
1332         audio_output->crtc_info.color_depth =
1333                 stream->timing.display_color_depth;
1334
1335         audio_output->crtc_info.requested_pixel_clock_100Hz =
1336                         pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz;
1337
1338         audio_output->crtc_info.calculated_pixel_clock_100Hz =
1339                         pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz;
1340
1341 /*for HDMI, audio ACR is with deep color ratio factor*/
1342         if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) &&
1343                 audio_output->crtc_info.requested_pixel_clock_100Hz ==
1344                                 (stream->timing.pix_clk_100hz)) {
1345                 if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
1346                         audio_output->crtc_info.requested_pixel_clock_100Hz =
1347                                         audio_output->crtc_info.requested_pixel_clock_100Hz/2;
1348                         audio_output->crtc_info.calculated_pixel_clock_100Hz =
1349                                         pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz/2;
1350
1351                 }
1352         }
1353
1354         if (state->clk_mgr &&
1355                 (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||
1356                         pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)) {
1357                 audio_output->pll_info.dp_dto_source_clock_in_khz =
1358                                 state->clk_mgr->funcs->get_dp_ref_clk_frequency(
1359                                                 state->clk_mgr);
1360         }
1361
1362         audio_output->pll_info.feed_back_divider =
1363                         pipe_ctx->pll_settings.feedback_divider;
1364
1365         audio_output->pll_info.dto_source =
1366                 translate_to_dto_source(
1367                         pipe_ctx->stream_res.tg->inst + 1);
1368
1369         /* TODO hard code to enable for now. Need get from stream */
1370         audio_output->pll_info.ss_enabled = true;
1371
1372         audio_output->pll_info.ss_percentage =
1373                         pipe_ctx->pll_settings.ss_percentage;
1374 }
1375
1376 static void program_scaler(const struct dc *dc,
1377                 const struct pipe_ctx *pipe_ctx)
1378 {
1379         struct tg_color color = {0};
1380
1381         /* TOFPGA */
1382         if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL)
1383                 return;
1384
1385         if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE)
1386                 get_surface_visual_confirm_color(pipe_ctx, &color);
1387         else
1388                 color_space_to_black_color(dc,
1389                                 pipe_ctx->stream->output_color_space,
1390                                 &color);
1391
1392         pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth(
1393                 pipe_ctx->plane_res.xfm,
1394                 pipe_ctx->plane_res.scl_data.lb_params.depth,
1395                 &pipe_ctx->stream->bit_depth_params);
1396
1397         if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color) {
1398                 /*
1399                  * The way 420 is packed, 2 channels carry Y component, 1 channel
1400                  * alternate between Cb and Cr, so both channels need the pixel
1401                  * value for Y
1402                  */
1403                 if (pipe_ctx->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
1404                         color.color_r_cr = color.color_g_y;
1405
1406                 pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color(
1407                                 pipe_ctx->stream_res.tg,
1408                                 &color);
1409         }
1410
1411         pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm,
1412                 &pipe_ctx->plane_res.scl_data);
1413 }
1414
1415 static enum dc_status dce110_enable_stream_timing(
1416                 struct pipe_ctx *pipe_ctx,
1417                 struct dc_state *context,
1418                 struct dc *dc)
1419 {
1420         struct dc_stream_state *stream = pipe_ctx->stream;
1421         struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx.
1422                         pipe_ctx[pipe_ctx->pipe_idx];
1423         struct tg_color black_color = {0};
1424
1425         if (!pipe_ctx_old->stream) {
1426
1427                 /* program blank color */
1428                 color_space_to_black_color(dc,
1429                                 stream->output_color_space, &black_color);
1430                 pipe_ctx->stream_res.tg->funcs->set_blank_color(
1431                                 pipe_ctx->stream_res.tg,
1432                                 &black_color);
1433
1434                 /*
1435                  * Must blank CRTC after disabling power gating and before any
1436                  * programming, otherwise CRTC will be hung in bad state
1437                  */
1438                 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);
1439
1440                 if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
1441                                 pipe_ctx->clock_source,
1442                                 &pipe_ctx->stream_res.pix_clk_params,
1443                                 dc->link_srv->dp_get_encoding_format(&pipe_ctx->link_config.dp_link_settings),
1444                                 &pipe_ctx->pll_settings)) {
1445                         BREAK_TO_DEBUGGER();
1446                         return DC_ERROR_UNEXPECTED;
1447                 }
1448
1449                 if (dc_is_hdmi_tmds_signal(stream->signal)) {
1450                         stream->link->phy_state.symclk_ref_cnts.otg = 1;
1451                         if (stream->link->phy_state.symclk_state == SYMCLK_OFF_TX_OFF)
1452                                 stream->link->phy_state.symclk_state = SYMCLK_ON_TX_OFF;
1453                         else
1454                                 stream->link->phy_state.symclk_state = SYMCLK_ON_TX_ON;
1455                 }
1456
1457                 pipe_ctx->stream_res.tg->funcs->program_timing(
1458                                 pipe_ctx->stream_res.tg,
1459                                 &stream->timing,
1460                                 0,
1461                                 0,
1462                                 0,
1463                                 0,
1464                                 pipe_ctx->stream->signal,
1465                                 true);
1466         }
1467
1468         if (!pipe_ctx_old->stream) {
1469                 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(
1470                                 pipe_ctx->stream_res.tg)) {
1471                         BREAK_TO_DEBUGGER();
1472                         return DC_ERROR_UNEXPECTED;
1473                 }
1474         }
1475
1476         return DC_OK;
1477 }
1478
1479 static enum dc_status apply_single_controller_ctx_to_hw(
1480                 struct pipe_ctx *pipe_ctx,
1481                 struct dc_state *context,
1482                 struct dc *dc)
1483 {
1484         struct dc_stream_state *stream = pipe_ctx->stream;
1485         struct dc_link *link = stream->link;
1486         struct drr_params params = {0};
1487         unsigned int event_triggers = 0;
1488         struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
1489         struct dce_hwseq *hws = dc->hwseq;
1490         const struct link_hwss *link_hwss = get_link_hwss(
1491                         link, &pipe_ctx->link_res);
1492
1493
1494         if (hws->funcs.disable_stream_gating) {
1495                 hws->funcs.disable_stream_gating(dc, pipe_ctx);
1496         }
1497
1498         if (pipe_ctx->stream_res.audio != NULL) {
1499                 struct audio_output audio_output;
1500
1501                 build_audio_output(context, pipe_ctx, &audio_output);
1502
1503                 link_hwss->setup_audio_output(pipe_ctx, &audio_output,
1504                                 pipe_ctx->stream_res.audio->inst);
1505
1506                 pipe_ctx->stream_res.audio->funcs->az_configure(
1507                                 pipe_ctx->stream_res.audio,
1508                                 pipe_ctx->stream->signal,
1509                                 &audio_output.crtc_info,
1510                                 &pipe_ctx->stream->audio_info);
1511         }
1512
1513         /* make sure no pipes syncd to the pipe being enabled */
1514         if (!pipe_ctx->stream->apply_seamless_boot_optimization && dc->config.use_pipe_ctx_sync_logic)
1515                 check_syncd_pipes_for_disabled_master_pipe(dc, context, pipe_ctx->pipe_idx);
1516
1517         pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
1518                 pipe_ctx->stream_res.opp,
1519                 &stream->bit_depth_params,
1520                 &stream->clamping);
1521
1522         pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
1523                         pipe_ctx->stream_res.opp,
1524                         COLOR_SPACE_YCBCR601,
1525                         stream->timing.display_color_depth,
1526                         stream->signal);
1527
1528         while (odm_pipe) {
1529                 odm_pipe->stream_res.opp->funcs->opp_set_dyn_expansion(
1530                                 odm_pipe->stream_res.opp,
1531                                 COLOR_SPACE_YCBCR601,
1532                                 stream->timing.display_color_depth,
1533                                 stream->signal);
1534
1535                 odm_pipe->stream_res.opp->funcs->opp_program_fmt(
1536                                 odm_pipe->stream_res.opp,
1537                                 &stream->bit_depth_params,
1538                                 &stream->clamping);
1539                 odm_pipe = odm_pipe->next_odm_pipe;
1540         }
1541
1542         /* DCN3.1 FPGA Workaround
1543          * Need to enable HPO DP Stream Encoder before setting OTG master enable.
1544          * To do so, move calling function enable_stream_timing to only be done AFTER calling
1545          * function core_link_enable_stream
1546          */
1547         if (!(hws->wa.dp_hpo_and_otg_sequence && dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)))
1548                 /*  */
1549                 /* Do not touch stream timing on seamless boot optimization. */
1550                 if (!pipe_ctx->stream->apply_seamless_boot_optimization)
1551                         hws->funcs.enable_stream_timing(pipe_ctx, context, dc);
1552
1553         if (hws->funcs.setup_vupdate_interrupt)
1554                 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
1555
1556         params.vertical_total_min = stream->adjust.v_total_min;
1557         params.vertical_total_max = stream->adjust.v_total_max;
1558         if (pipe_ctx->stream_res.tg->funcs->set_drr)
1559                 pipe_ctx->stream_res.tg->funcs->set_drr(
1560                         pipe_ctx->stream_res.tg, &params);
1561
1562         // DRR should set trigger event to monitor surface update event
1563         if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0)
1564                 event_triggers = 0x80;
1565         /* Event triggers and num frames initialized for DRR, but can be
1566          * later updated for PSR use. Note DRR trigger events are generated
1567          * regardless of whether num frames met.
1568          */
1569         if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control)
1570                 pipe_ctx->stream_res.tg->funcs->set_static_screen_control(
1571                                 pipe_ctx->stream_res.tg, event_triggers, 2);
1572
1573         if (!dc_is_virtual_signal(pipe_ctx->stream->signal))
1574                 pipe_ctx->stream_res.stream_enc->funcs->dig_connect_to_otg(
1575                         pipe_ctx->stream_res.stream_enc,
1576                         pipe_ctx->stream_res.tg->inst);
1577
1578         if (dc_is_dp_signal(pipe_ctx->stream->signal))
1579                 dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_CONNECT_DIG_FE_OTG);
1580
1581         if (!stream->dpms_off)
1582                 dc->link_srv->set_dpms_on(context, pipe_ctx);
1583
1584         /* DCN3.1 FPGA Workaround
1585          * Need to enable HPO DP Stream Encoder before setting OTG master enable.
1586          * To do so, move calling function enable_stream_timing to only be done AFTER calling
1587          * function core_link_enable_stream
1588          */
1589         if (hws->wa.dp_hpo_and_otg_sequence && dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
1590                 if (!pipe_ctx->stream->apply_seamless_boot_optimization)
1591                         hws->funcs.enable_stream_timing(pipe_ctx, context, dc);
1592         }
1593
1594         pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != NULL;
1595
1596         /* Phantom and main stream share the same link (because the stream
1597          * is constructed with the same sink). Make sure not to override
1598          * and link programming on the main.
1599          */
1600         if (pipe_ctx->stream->mall_stream_config.type != SUBVP_PHANTOM) {
1601                 pipe_ctx->stream->link->psr_settings.psr_feature_enabled = false;
1602                 pipe_ctx->stream->link->replay_settings.replay_feature_enabled = false;
1603         }
1604         return DC_OK;
1605 }
1606
1607 /******************************************************************************/
1608
1609 static void power_down_encoders(struct dc *dc)
1610 {
1611         int i;
1612
1613         for (i = 0; i < dc->link_count; i++) {
1614                 enum signal_type signal = dc->links[i]->connector_signal;
1615
1616                 dc->link_srv->blank_dp_stream(dc->links[i], false);
1617
1618                 if (signal != SIGNAL_TYPE_EDP)
1619                         signal = SIGNAL_TYPE_NONE;
1620
1621                 if (dc->links[i]->ep_type == DISPLAY_ENDPOINT_PHY)
1622                         dc->links[i]->link_enc->funcs->disable_output(
1623                                         dc->links[i]->link_enc, signal);
1624
1625                 dc->links[i]->link_status.link_active = false;
1626                 memset(&dc->links[i]->cur_link_settings, 0,
1627                                 sizeof(dc->links[i]->cur_link_settings));
1628         }
1629 }
1630
1631 static void power_down_controllers(struct dc *dc)
1632 {
1633         int i;
1634
1635         for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
1636                 dc->res_pool->timing_generators[i]->funcs->disable_crtc(
1637                                 dc->res_pool->timing_generators[i]);
1638         }
1639 }
1640
1641 static void power_down_clock_sources(struct dc *dc)
1642 {
1643         int i;
1644
1645         if (dc->res_pool->dp_clock_source->funcs->cs_power_down(
1646                 dc->res_pool->dp_clock_source) == false)
1647                 dm_error("Failed to power down pll! (dp clk src)\n");
1648
1649         for (i = 0; i < dc->res_pool->clk_src_count; i++) {
1650                 if (dc->res_pool->clock_sources[i]->funcs->cs_power_down(
1651                                 dc->res_pool->clock_sources[i]) == false)
1652                         dm_error("Failed to power down pll! (clk src index=%d)\n", i);
1653         }
1654 }
1655
1656 static void power_down_all_hw_blocks(struct dc *dc)
1657 {
1658         power_down_encoders(dc);
1659
1660         power_down_controllers(dc);
1661
1662         power_down_clock_sources(dc);
1663
1664         if (dc->fbc_compressor)
1665                 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
1666 }
1667
1668 static void disable_vga_and_power_gate_all_controllers(
1669                 struct dc *dc)
1670 {
1671         int i;
1672         struct timing_generator *tg;
1673         struct dc_context *ctx = dc->ctx;
1674
1675         for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
1676                 tg = dc->res_pool->timing_generators[i];
1677
1678                 if (tg->funcs->disable_vga)
1679                         tg->funcs->disable_vga(tg);
1680         }
1681         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1682                 /* Enable CLOCK gating for each pipe BEFORE controller
1683                  * powergating. */
1684                 enable_display_pipe_clock_gating(ctx,
1685                                 true);
1686
1687                 dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i;
1688                 dc->hwss.disable_plane(dc,
1689                         &dc->current_state->res_ctx.pipe_ctx[i]);
1690         }
1691 }
1692
1693
1694 static void get_edp_streams(struct dc_state *context,
1695                 struct dc_stream_state **edp_streams,
1696                 int *edp_stream_num)
1697 {
1698         int i;
1699
1700         *edp_stream_num = 0;
1701         for (i = 0; i < context->stream_count; i++) {
1702                 if (context->streams[i]->signal == SIGNAL_TYPE_EDP) {
1703                         edp_streams[*edp_stream_num] = context->streams[i];
1704                         if (++(*edp_stream_num) == MAX_NUM_EDP)
1705                                 return;
1706                 }
1707         }
1708 }
1709
1710 static void get_edp_links_with_sink(
1711                 struct dc *dc,
1712                 struct dc_link **edp_links_with_sink,
1713                 int *edp_with_sink_num)
1714 {
1715         int i;
1716
1717         /* check if there is an eDP panel not in use */
1718         *edp_with_sink_num = 0;
1719         for (i = 0; i < dc->link_count; i++) {
1720                 if (dc->links[i]->local_sink &&
1721                         dc->links[i]->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1722                         edp_links_with_sink[*edp_with_sink_num] = dc->links[i];
1723                         if (++(*edp_with_sink_num) == MAX_NUM_EDP)
1724                                 return;
1725                 }
1726         }
1727 }
1728
1729 /*
1730  * When ASIC goes from VBIOS/VGA mode to driver/accelerated mode we need:
1731  *  1. Power down all DC HW blocks
1732  *  2. Disable VGA engine on all controllers
1733  *  3. Enable power gating for controller
1734  *  4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS)
1735  */
1736 void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context)
1737 {
1738         struct dc_link *edp_links_with_sink[MAX_NUM_EDP];
1739         struct dc_link *edp_links[MAX_NUM_EDP];
1740         struct dc_stream_state *edp_streams[MAX_NUM_EDP];
1741         struct dc_link *edp_link_with_sink = NULL;
1742         struct dc_link *edp_link = NULL;
1743         struct dce_hwseq *hws = dc->hwseq;
1744         int edp_with_sink_num;
1745         int edp_num;
1746         int edp_stream_num;
1747         int i;
1748         bool can_apply_edp_fast_boot = false;
1749         bool can_apply_seamless_boot = false;
1750         bool keep_edp_vdd_on = false;
1751         DC_LOGGER_INIT();
1752
1753
1754         get_edp_links_with_sink(dc, edp_links_with_sink, &edp_with_sink_num);
1755         dc_get_edp_links(dc, edp_links, &edp_num);
1756
1757         if (hws->funcs.init_pipes)
1758                 hws->funcs.init_pipes(dc, context);
1759
1760         get_edp_streams(context, edp_streams, &edp_stream_num);
1761
1762         // Check fastboot support, disable on DCE8 because of blank screens
1763         if (edp_num && edp_stream_num && dc->ctx->dce_version != DCE_VERSION_8_0 &&
1764                     dc->ctx->dce_version != DCE_VERSION_8_1 &&
1765                     dc->ctx->dce_version != DCE_VERSION_8_3) {
1766                 for (i = 0; i < edp_num; i++) {
1767                         edp_link = edp_links[i];
1768                         if (edp_link != edp_streams[0]->link)
1769                                 continue;
1770                         // enable fastboot if backend is enabled on eDP
1771                         if (edp_link->link_enc->funcs->is_dig_enabled &&
1772                             edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) &&
1773                             edp_link->link_status.link_active) {
1774                                 struct dc_stream_state *edp_stream = edp_streams[0];
1775
1776                                 can_apply_edp_fast_boot = dc_validate_boot_timing(dc,
1777                                         edp_stream->sink, &edp_stream->timing);
1778                                 edp_stream->apply_edp_fast_boot_optimization = can_apply_edp_fast_boot;
1779                                 if (can_apply_edp_fast_boot)
1780                                         DC_LOG_EVENT_LINK_TRAINING("eDP fast boot disabled to optimize link rate\n");
1781
1782                                 break;
1783                         }
1784                 }
1785                 // We are trying to enable eDP, don't power down VDD
1786                 if (can_apply_edp_fast_boot)
1787                         keep_edp_vdd_on = true;
1788         }
1789
1790         // Check seamless boot support
1791         for (i = 0; i < context->stream_count; i++) {
1792                 if (context->streams[i]->apply_seamless_boot_optimization) {
1793                         can_apply_seamless_boot = true;
1794                         break;
1795                 }
1796         }
1797
1798         /* eDP should not have stream in resume from S4 and so even with VBios post
1799          * it should get turned off
1800          */
1801         if (edp_with_sink_num)
1802                 edp_link_with_sink = edp_links_with_sink[0];
1803
1804         if (!can_apply_edp_fast_boot && !can_apply_seamless_boot) {
1805                 if (edp_link_with_sink && !keep_edp_vdd_on) {
1806                         /*turn off backlight before DP_blank and encoder powered down*/
1807                         hws->funcs.edp_backlight_control(edp_link_with_sink, false);
1808                 }
1809                 /*resume from S3, no vbios posting, no need to power down again*/
1810                 clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr);
1811
1812                 power_down_all_hw_blocks(dc);
1813                 disable_vga_and_power_gate_all_controllers(dc);
1814                 if (edp_link_with_sink && !keep_edp_vdd_on)
1815                         dc->hwss.edp_power_control(edp_link_with_sink, false);
1816                 clk_mgr_optimize_pwr_state(dc, dc->clk_mgr);
1817         }
1818         bios_set_scratch_acc_mode_change(dc->ctx->dc_bios, 1);
1819 }
1820
1821 static uint32_t compute_pstate_blackout_duration(
1822         struct bw_fixed blackout_duration,
1823         const struct dc_stream_state *stream)
1824 {
1825         uint32_t total_dest_line_time_ns;
1826         uint32_t pstate_blackout_duration_ns;
1827
1828         pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24;
1829
1830         total_dest_line_time_ns = 1000000UL *
1831                 (stream->timing.h_total * 10) /
1832                 stream->timing.pix_clk_100hz +
1833                 pstate_blackout_duration_ns;
1834
1835         return total_dest_line_time_ns;
1836 }
1837
1838 static void dce110_set_displaymarks(
1839         const struct dc *dc,
1840         struct dc_state *context)
1841 {
1842         uint8_t i, num_pipes;
1843         unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
1844
1845         for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) {
1846                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1847                 uint32_t total_dest_line_time_ns;
1848
1849                 if (pipe_ctx->stream == NULL)
1850                         continue;
1851
1852                 total_dest_line_time_ns = compute_pstate_blackout_duration(
1853                         dc->bw_vbios->blackout_duration, pipe_ctx->stream);
1854                 pipe_ctx->plane_res.mi->funcs->mem_input_program_display_marks(
1855                         pipe_ctx->plane_res.mi,
1856                         context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes],
1857                         context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes],
1858                         context->bw_ctx.bw.dce.stutter_entry_wm_ns[num_pipes],
1859                         context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes],
1860                         total_dest_line_time_ns);
1861                 if (i == underlay_idx) {
1862                         num_pipes++;
1863                         pipe_ctx->plane_res.mi->funcs->mem_input_program_chroma_display_marks(
1864                                 pipe_ctx->plane_res.mi,
1865                                 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes],
1866                                 context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes],
1867                                 context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes],
1868                                 total_dest_line_time_ns);
1869                 }
1870                 num_pipes++;
1871         }
1872 }
1873
1874 void dce110_set_safe_displaymarks(
1875                 struct resource_context *res_ctx,
1876                 const struct resource_pool *pool)
1877 {
1878         int i;
1879         int underlay_idx = pool->underlay_pipe_index;
1880         struct dce_watermarks max_marks = {
1881                 MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK };
1882         struct dce_watermarks nbp_marks = {
1883                 SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK };
1884         struct dce_watermarks min_marks = { 0, 0, 0, 0};
1885
1886         for (i = 0; i < MAX_PIPES; i++) {
1887                 if (res_ctx->pipe_ctx[i].stream == NULL || res_ctx->pipe_ctx[i].plane_res.mi == NULL)
1888                         continue;
1889
1890                 res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_display_marks(
1891                                 res_ctx->pipe_ctx[i].plane_res.mi,
1892                                 nbp_marks,
1893                                 max_marks,
1894                                 min_marks,
1895                                 max_marks,
1896                                 MAX_WATERMARK);
1897
1898                 if (i == underlay_idx)
1899                         res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_chroma_display_marks(
1900                                 res_ctx->pipe_ctx[i].plane_res.mi,
1901                                 nbp_marks,
1902                                 max_marks,
1903                                 max_marks,
1904                                 MAX_WATERMARK);
1905
1906         }
1907 }
1908
1909 /*******************************************************************************
1910  * Public functions
1911  ******************************************************************************/
1912
1913 static void set_drr(struct pipe_ctx **pipe_ctx,
1914                 int num_pipes, struct dc_crtc_timing_adjust adjust)
1915 {
1916         int i = 0;
1917         struct drr_params params = {0};
1918         // DRR should set trigger event to monitor surface update event
1919         unsigned int event_triggers = 0x80;
1920         // Note DRR trigger events are generated regardless of whether num frames met.
1921         unsigned int num_frames = 2;
1922
1923         params.vertical_total_max = adjust.v_total_max;
1924         params.vertical_total_min = adjust.v_total_min;
1925
1926         /* TODO: If multiple pipes are to be supported, you need
1927          * some GSL stuff. Static screen triggers may be programmed differently
1928          * as well.
1929          */
1930         for (i = 0; i < num_pipes; i++) {
1931                 pipe_ctx[i]->stream_res.tg->funcs->set_drr(
1932                         pipe_ctx[i]->stream_res.tg, &params);
1933
1934                 if (adjust.v_total_max != 0 && adjust.v_total_min != 0)
1935                         pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control(
1936                                         pipe_ctx[i]->stream_res.tg,
1937                                         event_triggers, num_frames);
1938         }
1939 }
1940
1941 static void get_position(struct pipe_ctx **pipe_ctx,
1942                 int num_pipes,
1943                 struct crtc_position *position)
1944 {
1945         int i = 0;
1946
1947         /* TODO: handle pipes > 1
1948          */
1949         for (i = 0; i < num_pipes; i++)
1950                 pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);
1951 }
1952
1953 static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
1954                 int num_pipes, const struct dc_static_screen_params *params)
1955 {
1956         unsigned int i;
1957         unsigned int triggers = 0;
1958
1959         if (params->triggers.overlay_update)
1960                 triggers |= 0x100;
1961         if (params->triggers.surface_update)
1962                 triggers |= 0x80;
1963         if (params->triggers.cursor_update)
1964                 triggers |= 0x2;
1965         if (params->triggers.force_trigger)
1966                 triggers |= 0x1;
1967
1968         if (num_pipes) {
1969                 struct dc *dc = pipe_ctx[0]->stream->ctx->dc;
1970
1971                 if (dc->fbc_compressor)
1972                         triggers |= 0x84;
1973         }
1974
1975         for (i = 0; i < num_pipes; i++)
1976                 pipe_ctx[i]->stream_res.tg->funcs->
1977                         set_static_screen_control(pipe_ctx[i]->stream_res.tg,
1978                                         triggers, params->num_frames);
1979 }
1980
1981 /*
1982  *  Check if FBC can be enabled
1983  */
1984 static bool should_enable_fbc(struct dc *dc,
1985                 struct dc_state *context,
1986                 uint32_t *pipe_idx)
1987 {
1988         uint32_t i;
1989         struct pipe_ctx *pipe_ctx = NULL;
1990         struct resource_context *res_ctx = &context->res_ctx;
1991         unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
1992
1993
1994         ASSERT(dc->fbc_compressor);
1995
1996         /* FBC memory should be allocated */
1997         if (!dc->ctx->fbc_gpu_addr)
1998                 return false;
1999
2000         /* Only supports single display */
2001         if (context->stream_count != 1)
2002                 return false;
2003
2004         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2005                 if (res_ctx->pipe_ctx[i].stream) {
2006
2007                         pipe_ctx = &res_ctx->pipe_ctx[i];
2008
2009                         /* fbc not applicable on underlay pipe */
2010                         if (pipe_ctx->pipe_idx != underlay_idx) {
2011                                 *pipe_idx = i;
2012                                 break;
2013                         }
2014                 }
2015         }
2016
2017         if (i == dc->res_pool->pipe_count)
2018                 return false;
2019
2020         if (!pipe_ctx->stream->link)
2021                 return false;
2022
2023         /* Only supports eDP */
2024         if (pipe_ctx->stream->link->connector_signal != SIGNAL_TYPE_EDP)
2025                 return false;
2026
2027         /* PSR should not be enabled */
2028         if (pipe_ctx->stream->link->psr_settings.psr_feature_enabled)
2029                 return false;
2030
2031         /* Replay should not be enabled */
2032         if (pipe_ctx->stream->link->replay_settings.replay_feature_enabled)
2033                 return false;
2034
2035         /* Nothing to compress */
2036         if (!pipe_ctx->plane_state)
2037                 return false;
2038
2039         /* Only for non-linear tiling */
2040         if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL)
2041                 return false;
2042
2043         return true;
2044 }
2045
2046 /*
2047  *  Enable FBC
2048  */
2049 static void enable_fbc(
2050                 struct dc *dc,
2051                 struct dc_state *context)
2052 {
2053         uint32_t pipe_idx = 0;
2054
2055         if (should_enable_fbc(dc, context, &pipe_idx)) {
2056                 /* Program GRPH COMPRESSED ADDRESS and PITCH */
2057                 struct compr_addr_and_pitch_params params = {0, 0, 0};
2058                 struct compressor *compr = dc->fbc_compressor;
2059                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
2060
2061                 params.source_view_width = pipe_ctx->stream->timing.h_addressable;
2062                 params.source_view_height = pipe_ctx->stream->timing.v_addressable;
2063                 params.inst = pipe_ctx->stream_res.tg->inst;
2064                 compr->compr_surface_address.quad_part = dc->ctx->fbc_gpu_addr;
2065
2066                 compr->funcs->surface_address_and_pitch(compr, &params);
2067                 compr->funcs->set_fbc_invalidation_triggers(compr, 1);
2068
2069                 compr->funcs->enable_fbc(compr, &params);
2070         }
2071 }
2072
2073 static void dce110_reset_hw_ctx_wrap(
2074                 struct dc *dc,
2075                 struct dc_state *context)
2076 {
2077         int i;
2078
2079         /* Reset old context */
2080         /* look up the targets that have been removed since last commit */
2081         for (i = 0; i < MAX_PIPES; i++) {
2082                 struct pipe_ctx *pipe_ctx_old =
2083                         &dc->current_state->res_ctx.pipe_ctx[i];
2084                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2085
2086                 /* Note: We need to disable output if clock sources change,
2087                  * since bios does optimization and doesn't apply if changing
2088                  * PHY when not already disabled.
2089                  */
2090
2091                 /* Skip underlay pipe since it will be handled in commit surface*/
2092                 if (!pipe_ctx_old->stream || pipe_ctx_old->top_pipe)
2093                         continue;
2094
2095                 if (!pipe_ctx->stream ||
2096                                 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
2097                         struct clock_source *old_clk = pipe_ctx_old->clock_source;
2098
2099                         /* Disable if new stream is null. O/w, if stream is
2100                          * disabled already, no need to disable again.
2101                          */
2102                         if (!pipe_ctx->stream || !pipe_ctx->stream->dpms_off) {
2103                                 dc->link_srv->set_dpms_off(pipe_ctx_old);
2104
2105                                 /* free acquired resources*/
2106                                 if (pipe_ctx_old->stream_res.audio) {
2107                                         /*disable az_endpoint*/
2108                                         pipe_ctx_old->stream_res.audio->funcs->
2109                                                         az_disable(pipe_ctx_old->stream_res.audio);
2110
2111                                         /*free audio*/
2112                                         if (dc->caps.dynamic_audio == true) {
2113                                                 /*we have to dynamic arbitrate the audio endpoints*/
2114                                                 /*we free the resource, need reset is_audio_acquired*/
2115                                                 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,
2116                                                                 pipe_ctx_old->stream_res.audio, false);
2117                                                 pipe_ctx_old->stream_res.audio = NULL;
2118                                         }
2119                                 }
2120                         }
2121
2122                         pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true);
2123                         if (!hwss_wait_for_blank_complete(pipe_ctx_old->stream_res.tg)) {
2124                                 dm_error("DC: failed to blank crtc!\n");
2125                                 BREAK_TO_DEBUGGER();
2126                         }
2127                         pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg);
2128                         pipe_ctx_old->stream->link->phy_state.symclk_ref_cnts.otg = 0;
2129                         pipe_ctx_old->plane_res.mi->funcs->free_mem_input(
2130                                         pipe_ctx_old->plane_res.mi, dc->current_state->stream_count);
2131
2132                         if (old_clk && 0 == resource_get_clock_source_reference(&context->res_ctx,
2133                                                                                 dc->res_pool,
2134                                                                                 old_clk))
2135                                 old_clk->funcs->cs_power_down(old_clk);
2136
2137                         dc->hwss.disable_plane(dc, pipe_ctx_old);
2138
2139                         pipe_ctx_old->stream = NULL;
2140                 }
2141         }
2142 }
2143
2144 static void dce110_setup_audio_dto(
2145                 struct dc *dc,
2146                 struct dc_state *context)
2147 {
2148         int i;
2149
2150         /* program audio wall clock. use HDMI as clock source if HDMI
2151          * audio active. Otherwise, use DP as clock source
2152          * first, loop to find any HDMI audio, if not, loop find DP audio
2153          */
2154         /* Setup audio rate clock source */
2155         /* Issue:
2156         * Audio lag happened on DP monitor when unplug a HDMI monitor
2157         *
2158         * Cause:
2159         * In case of DP and HDMI connected or HDMI only, DCCG_AUDIO_DTO_SEL
2160         * is set to either dto0 or dto1, audio should work fine.
2161         * In case of DP connected only, DCCG_AUDIO_DTO_SEL should be dto1,
2162         * set to dto0 will cause audio lag.
2163         *
2164         * Solution:
2165         * Not optimized audio wall dto setup. When mode set, iterate pipe_ctx,
2166         * find first available pipe with audio, setup audio wall DTO per topology
2167         * instead of per pipe.
2168         */
2169         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2170                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2171
2172                 if (pipe_ctx->stream == NULL)
2173                         continue;
2174
2175                 if (pipe_ctx->top_pipe)
2176                         continue;
2177                 if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A)
2178                         continue;
2179                 if (pipe_ctx->stream_res.audio != NULL) {
2180                         struct audio_output audio_output;
2181
2182                         build_audio_output(context, pipe_ctx, &audio_output);
2183
2184                         if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->set_audio_dtbclk_dto) {
2185                                 struct dtbclk_dto_params dto_params = {0};
2186
2187                                 dc->res_pool->dccg->funcs->set_audio_dtbclk_dto(
2188                                         dc->res_pool->dccg, &dto_params);
2189
2190                                 pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
2191                                                 pipe_ctx->stream_res.audio,
2192                                                 pipe_ctx->stream->signal,
2193                                                 &audio_output.crtc_info,
2194                                                 &audio_output.pll_info);
2195                         } else
2196                                 pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
2197                                         pipe_ctx->stream_res.audio,
2198                                         pipe_ctx->stream->signal,
2199                                         &audio_output.crtc_info,
2200                                         &audio_output.pll_info);
2201                         break;
2202                 }
2203         }
2204
2205         /* no HDMI audio is found, try DP audio */
2206         if (i == dc->res_pool->pipe_count) {
2207                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2208                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2209
2210                         if (pipe_ctx->stream == NULL)
2211                                 continue;
2212
2213                         if (pipe_ctx->top_pipe)
2214                                 continue;
2215
2216                         if (!dc_is_dp_signal(pipe_ctx->stream->signal))
2217                                 continue;
2218
2219                         if (pipe_ctx->stream_res.audio != NULL) {
2220                                 struct audio_output audio_output;
2221
2222                                 build_audio_output(context, pipe_ctx, &audio_output);
2223
2224                                 pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
2225                                         pipe_ctx->stream_res.audio,
2226                                         pipe_ctx->stream->signal,
2227                                         &audio_output.crtc_info,
2228                                         &audio_output.pll_info);
2229                                 break;
2230                         }
2231                 }
2232         }
2233 }
2234
2235 enum dc_status dce110_apply_ctx_to_hw(
2236                 struct dc *dc,
2237                 struct dc_state *context)
2238 {
2239         struct dce_hwseq *hws = dc->hwseq;
2240         struct dc_bios *dcb = dc->ctx->dc_bios;
2241         enum dc_status status;
2242         int i;
2243
2244         /* reset syncd pipes from disabled pipes */
2245         if (dc->config.use_pipe_ctx_sync_logic)
2246                 reset_syncd_pipes_from_disabled_pipes(dc, context);
2247
2248         /* Reset old context */
2249         /* look up the targets that have been removed since last commit */
2250         hws->funcs.reset_hw_ctx_wrap(dc, context);
2251
2252         /* Skip applying if no targets */
2253         if (context->stream_count <= 0)
2254                 return DC_OK;
2255
2256         /* Apply new context */
2257         dcb->funcs->set_scratch_critical_state(dcb, true);
2258
2259         /* below is for real asic only */
2260         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2261                 struct pipe_ctx *pipe_ctx_old =
2262                                         &dc->current_state->res_ctx.pipe_ctx[i];
2263                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2264
2265                 if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe)
2266                         continue;
2267
2268                 if (pipe_ctx->stream == pipe_ctx_old->stream) {
2269                         if (pipe_ctx_old->clock_source != pipe_ctx->clock_source)
2270                                 dce_crtc_switch_to_clk_src(dc->hwseq,
2271                                                 pipe_ctx->clock_source, i);
2272                         continue;
2273                 }
2274
2275                 hws->funcs.enable_display_power_gating(
2276                                 dc, i, dc->ctx->dc_bios,
2277                                 PIPE_GATING_CONTROL_DISABLE);
2278         }
2279
2280         if (dc->fbc_compressor)
2281                 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
2282
2283         dce110_setup_audio_dto(dc, context);
2284
2285         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2286                 struct pipe_ctx *pipe_ctx_old =
2287                                         &dc->current_state->res_ctx.pipe_ctx[i];
2288                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2289
2290                 if (pipe_ctx->stream == NULL)
2291                         continue;
2292
2293                 if (pipe_ctx->stream == pipe_ctx_old->stream &&
2294                         pipe_ctx->stream->link->link_state_valid) {
2295                         continue;
2296                 }
2297
2298                 if (pipe_ctx_old->stream && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx))
2299                         continue;
2300
2301                 if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe)
2302                         continue;
2303
2304                 status = apply_single_controller_ctx_to_hw(
2305                                 pipe_ctx,
2306                                 context,
2307                                 dc);
2308
2309                 if (DC_OK != status)
2310                         return status;
2311
2312 #ifdef CONFIG_DRM_AMD_DC_FP
2313                 if (hws->funcs.resync_fifo_dccg_dio)
2314                         hws->funcs.resync_fifo_dccg_dio(hws, dc, context);
2315 #endif
2316         }
2317
2318         if (dc->fbc_compressor)
2319                 enable_fbc(dc, dc->current_state);
2320
2321         dcb->funcs->set_scratch_critical_state(dcb, false);
2322
2323         return DC_OK;
2324 }
2325
2326 /*******************************************************************************
2327  * Front End programming
2328  ******************************************************************************/
2329 static void set_default_colors(struct pipe_ctx *pipe_ctx)
2330 {
2331         struct default_adjustment default_adjust = { 0 };
2332
2333         default_adjust.force_hw_default = false;
2334         default_adjust.in_color_space = pipe_ctx->plane_state->color_space;
2335         default_adjust.out_color_space = pipe_ctx->stream->output_color_space;
2336         default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW;
2337         default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format;
2338
2339         /* display color depth */
2340         default_adjust.color_depth =
2341                 pipe_ctx->stream->timing.display_color_depth;
2342
2343         /* Lb color depth */
2344         default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth;
2345
2346         pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default(
2347                                         pipe_ctx->plane_res.xfm, &default_adjust);
2348 }
2349
2350
2351 /*******************************************************************************
2352  * In order to turn on/off specific surface we will program
2353  * Blender + CRTC
2354  *
2355  * In case that we have two surfaces and they have a different visibility
2356  * we can't turn off the CRTC since it will turn off the entire display
2357  *
2358  * |----------------------------------------------- |
2359  * |bottom pipe|curr pipe  |              |         |
2360  * |Surface    |Surface    | Blender      |  CRCT   |
2361  * |visibility |visibility | Configuration|         |
2362  * |------------------------------------------------|
2363  * |   off     |    off    | CURRENT_PIPE | blank   |
2364  * |   off     |    on     | CURRENT_PIPE | unblank |
2365  * |   on      |    off    | OTHER_PIPE   | unblank |
2366  * |   on      |    on     | BLENDING     | unblank |
2367  * -------------------------------------------------|
2368  *
2369  ******************************************************************************/
2370 static void program_surface_visibility(const struct dc *dc,
2371                 struct pipe_ctx *pipe_ctx)
2372 {
2373         enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE;
2374         bool blank_target = false;
2375
2376         if (pipe_ctx->bottom_pipe) {
2377
2378                 /* For now we are supporting only two pipes */
2379                 ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL);
2380
2381                 if (pipe_ctx->bottom_pipe->plane_state->visible) {
2382                         if (pipe_ctx->plane_state->visible)
2383                                 blender_mode = BLND_MODE_BLENDING;
2384                         else
2385                                 blender_mode = BLND_MODE_OTHER_PIPE;
2386
2387                 } else if (!pipe_ctx->plane_state->visible)
2388                         blank_target = true;
2389
2390         } else if (!pipe_ctx->plane_state->visible)
2391                 blank_target = true;
2392
2393         dce_set_blender_mode(dc->hwseq, pipe_ctx->stream_res.tg->inst, blender_mode);
2394         pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target);
2395
2396 }
2397
2398 static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
2399 {
2400         int i = 0;
2401         struct xfm_grph_csc_adjustment adjust;
2402         memset(&adjust, 0, sizeof(adjust));
2403         adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
2404
2405
2406         if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
2407                 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2408
2409                 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
2410                         adjust.temperature_matrix[i] =
2411                                 pipe_ctx->stream->gamut_remap_matrix.matrix[i];
2412         }
2413
2414         pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
2415 }
2416 static void update_plane_addr(const struct dc *dc,
2417                 struct pipe_ctx *pipe_ctx)
2418 {
2419         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2420
2421         if (plane_state == NULL)
2422                 return;
2423
2424         pipe_ctx->plane_res.mi->funcs->mem_input_program_surface_flip_and_addr(
2425                         pipe_ctx->plane_res.mi,
2426                         &plane_state->address,
2427                         plane_state->flip_immediate);
2428
2429         plane_state->status.requested_address = plane_state->address;
2430 }
2431
2432 static void dce110_update_pending_status(struct pipe_ctx *pipe_ctx)
2433 {
2434         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2435
2436         if (plane_state == NULL)
2437                 return;
2438
2439         plane_state->status.is_flip_pending =
2440                         pipe_ctx->plane_res.mi->funcs->mem_input_is_flip_pending(
2441                                         pipe_ctx->plane_res.mi);
2442
2443         if (plane_state->status.is_flip_pending && !plane_state->visible)
2444                 pipe_ctx->plane_res.mi->current_address = pipe_ctx->plane_res.mi->request_address;
2445
2446         plane_state->status.current_address = pipe_ctx->plane_res.mi->current_address;
2447         if (pipe_ctx->plane_res.mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
2448                         pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye) {
2449                 plane_state->status.is_right_eye =\
2450                                 !pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);
2451         }
2452 }
2453
2454 void dce110_power_down(struct dc *dc)
2455 {
2456         power_down_all_hw_blocks(dc);
2457         disable_vga_and_power_gate_all_controllers(dc);
2458 }
2459
2460 static bool wait_for_reset_trigger_to_occur(
2461         struct dc_context *dc_ctx,
2462         struct timing_generator *tg)
2463 {
2464         struct dc_context *ctx = dc_ctx;
2465         bool rc = false;
2466
2467         /* To avoid endless loop we wait at most
2468          * frames_to_wait_on_triggered_reset frames for the reset to occur. */
2469         const uint32_t frames_to_wait_on_triggered_reset = 10;
2470         uint32_t i;
2471
2472         for (i = 0; i < frames_to_wait_on_triggered_reset; i++) {
2473
2474                 if (!tg->funcs->is_counter_moving(tg)) {
2475                         DC_ERROR("TG counter is not moving!\n");
2476                         break;
2477                 }
2478
2479                 if (tg->funcs->did_triggered_reset_occur(tg)) {
2480                         rc = true;
2481                         /* usually occurs at i=1 */
2482                         DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n",
2483                                         i);
2484                         break;
2485                 }
2486
2487                 /* Wait for one frame. */
2488                 tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE);
2489                 tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
2490         }
2491
2492         if (false == rc)
2493                 DC_ERROR("GSL: Timeout on reset trigger!\n");
2494
2495         return rc;
2496 }
2497
2498 /* Enable timing synchronization for a group of Timing Generators. */
2499 static void dce110_enable_timing_synchronization(
2500                 struct dc *dc,
2501                 int group_index,
2502                 int group_size,
2503                 struct pipe_ctx *grouped_pipes[])
2504 {
2505         struct dc_context *dc_ctx = dc->ctx;
2506         struct dcp_gsl_params gsl_params = { 0 };
2507         int i;
2508         DC_LOGGER_INIT();
2509
2510         DC_SYNC_INFO("GSL: Setting-up...\n");
2511
2512         /* Designate a single TG in the group as a master.
2513          * Since HW doesn't care which one, we always assign
2514          * the 1st one in the group. */
2515         gsl_params.gsl_group = 0;
2516         gsl_params.gsl_master = grouped_pipes[0]->stream_res.tg->inst;
2517
2518         for (i = 0; i < group_size; i++)
2519                 grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock(
2520                                         grouped_pipes[i]->stream_res.tg, &gsl_params);
2521
2522         /* Reset slave controllers on master VSync */
2523         DC_SYNC_INFO("GSL: enabling trigger-reset\n");
2524
2525         for (i = 1 /* skip the master */; i < group_size; i++)
2526                 grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger(
2527                                 grouped_pipes[i]->stream_res.tg,
2528                                 gsl_params.gsl_group);
2529
2530         for (i = 1 /* skip the master */; i < group_size; i++) {
2531                 DC_SYNC_INFO("GSL: waiting for reset to occur.\n");
2532                 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
2533                 grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(
2534                                 grouped_pipes[i]->stream_res.tg);
2535         }
2536
2537         /* GSL Vblank synchronization is a one time sync mechanism, assumption
2538          * is that the sync'ed displays will not drift out of sync over time*/
2539         DC_SYNC_INFO("GSL: Restoring register states.\n");
2540         for (i = 0; i < group_size; i++)
2541                 grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg);
2542
2543         DC_SYNC_INFO("GSL: Set-up complete.\n");
2544 }
2545
2546 static void dce110_enable_per_frame_crtc_position_reset(
2547                 struct dc *dc,
2548                 int group_size,
2549                 struct pipe_ctx *grouped_pipes[])
2550 {
2551         struct dc_context *dc_ctx = dc->ctx;
2552         struct dcp_gsl_params gsl_params = { 0 };
2553         int i;
2554         DC_LOGGER_INIT();
2555
2556         gsl_params.gsl_group = 0;
2557         gsl_params.gsl_master = 0;
2558
2559         for (i = 0; i < group_size; i++)
2560                 grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock(
2561                                         grouped_pipes[i]->stream_res.tg, &gsl_params);
2562
2563         DC_SYNC_INFO("GSL: enabling trigger-reset\n");
2564
2565         for (i = 1; i < group_size; i++)
2566                 grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset(
2567                                 grouped_pipes[i]->stream_res.tg,
2568                                 gsl_params.gsl_master,
2569                                 &grouped_pipes[i]->stream->triggered_crtc_reset);
2570
2571         DC_SYNC_INFO("GSL: waiting for reset to occur.\n");
2572         for (i = 1; i < group_size; i++)
2573                 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
2574
2575         for (i = 0; i < group_size; i++)
2576                 grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg);
2577
2578 }
2579
2580 static void init_pipes(struct dc *dc, struct dc_state *context)
2581 {
2582         // Do nothing
2583 }
2584
2585 static void init_hw(struct dc *dc)
2586 {
2587         int i;
2588         struct dc_bios *bp;
2589         struct transform *xfm;
2590         struct abm *abm;
2591         struct dmcu *dmcu;
2592         struct dce_hwseq *hws = dc->hwseq;
2593         uint32_t backlight = MAX_BACKLIGHT_LEVEL;
2594
2595         bp = dc->ctx->dc_bios;
2596         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2597                 xfm = dc->res_pool->transforms[i];
2598                 xfm->funcs->transform_reset(xfm);
2599
2600                 hws->funcs.enable_display_power_gating(
2601                                 dc, i, bp,
2602                                 PIPE_GATING_CONTROL_INIT);
2603                 hws->funcs.enable_display_power_gating(
2604                                 dc, i, bp,
2605                                 PIPE_GATING_CONTROL_DISABLE);
2606                 hws->funcs.enable_display_pipe_clock_gating(
2607                         dc->ctx,
2608                         true);
2609         }
2610
2611         dce_clock_gating_power_up(dc->hwseq, false);
2612         /***************************************/
2613
2614         for (i = 0; i < dc->link_count; i++) {
2615                 /****************************************/
2616                 /* Power up AND update implementation according to the
2617                  * required signal (which may be different from the
2618                  * default signal on connector). */
2619                 struct dc_link *link = dc->links[i];
2620
2621                 link->link_enc->funcs->hw_init(link->link_enc);
2622         }
2623
2624         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2625                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2626
2627                 tg->funcs->disable_vga(tg);
2628
2629                 /* Blank controller using driver code instead of
2630                  * command table. */
2631                 tg->funcs->set_blank(tg, true);
2632                 hwss_wait_for_blank_complete(tg);
2633         }
2634
2635         for (i = 0; i < dc->res_pool->audio_count; i++) {
2636                 struct audio *audio = dc->res_pool->audios[i];
2637                 audio->funcs->hw_init(audio);
2638         }
2639
2640         for (i = 0; i < dc->link_count; i++) {
2641                 struct dc_link *link = dc->links[i];
2642
2643                 if (link->panel_cntl)
2644                         backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl);
2645         }
2646
2647         abm = dc->res_pool->abm;
2648         if (abm != NULL)
2649                 abm->funcs->abm_init(abm, backlight);
2650
2651         dmcu = dc->res_pool->dmcu;
2652         if (dmcu != NULL && abm != NULL)
2653                 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
2654
2655         if (dc->fbc_compressor)
2656                 dc->fbc_compressor->funcs->power_up_fbc(dc->fbc_compressor);
2657
2658 }
2659
2660
2661 void dce110_prepare_bandwidth(
2662                 struct dc *dc,
2663                 struct dc_state *context)
2664 {
2665         struct clk_mgr *dccg = dc->clk_mgr;
2666
2667         dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool);
2668         if (dccg)
2669                 dccg->funcs->update_clocks(
2670                                 dccg,
2671                                 context,
2672                                 false);
2673 }
2674
2675 void dce110_optimize_bandwidth(
2676                 struct dc *dc,
2677                 struct dc_state *context)
2678 {
2679         struct clk_mgr *dccg = dc->clk_mgr;
2680
2681         dce110_set_displaymarks(dc, context);
2682
2683         if (dccg)
2684                 dccg->funcs->update_clocks(
2685                                 dccg,
2686                                 context,
2687                                 true);
2688 }
2689
2690 static void dce110_program_front_end_for_pipe(
2691                 struct dc *dc, struct pipe_ctx *pipe_ctx)
2692 {
2693         struct mem_input *mi = pipe_ctx->plane_res.mi;
2694         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2695         struct xfm_grph_csc_adjustment adjust;
2696         struct out_csc_color_matrix tbl_entry;
2697         unsigned int i;
2698         struct dce_hwseq *hws = dc->hwseq;
2699
2700         memset(&tbl_entry, 0, sizeof(tbl_entry));
2701
2702         memset(&adjust, 0, sizeof(adjust));
2703         adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
2704
2705         dce_enable_fe_clock(dc->hwseq, mi->inst, true);
2706
2707         set_default_colors(pipe_ctx);
2708         if (pipe_ctx->stream->csc_color_matrix.enable_adjustment
2709                         == true) {
2710                 tbl_entry.color_space =
2711                         pipe_ctx->stream->output_color_space;
2712
2713                 for (i = 0; i < 12; i++)
2714                         tbl_entry.regval[i] =
2715                         pipe_ctx->stream->csc_color_matrix.matrix[i];
2716
2717                 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment
2718                                 (pipe_ctx->plane_res.xfm, &tbl_entry);
2719         }
2720
2721         if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
2722                 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2723
2724                 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
2725                         adjust.temperature_matrix[i] =
2726                                 pipe_ctx->stream->gamut_remap_matrix.matrix[i];
2727         }
2728
2729         pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
2730
2731         pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != NULL;
2732
2733         program_scaler(dc, pipe_ctx);
2734
2735         mi->funcs->mem_input_program_surface_config(
2736                         mi,
2737                         plane_state->format,
2738                         &plane_state->tiling_info,
2739                         &plane_state->plane_size,
2740                         plane_state->rotation,
2741                         NULL,
2742                         false);
2743         if (mi->funcs->set_blank)
2744                 mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible);
2745
2746         if (dc->config.gpu_vm_support)
2747                 mi->funcs->mem_input_program_pte_vm(
2748                                 pipe_ctx->plane_res.mi,
2749                                 plane_state->format,
2750                                 &plane_state->tiling_info,
2751                                 plane_state->rotation);
2752
2753         /* Moved programming gamma from dc to hwss */
2754         if (pipe_ctx->plane_state->update_flags.bits.full_update ||
2755                         pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
2756                         pipe_ctx->plane_state->update_flags.bits.gamma_change)
2757                 hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);
2758
2759         if (pipe_ctx->plane_state->update_flags.bits.full_update)
2760                 hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);
2761
2762         DC_LOG_SURFACE(
2763                         "Pipe:%d %p: addr hi:0x%x, "
2764                         "addr low:0x%x, "
2765                         "src: %d, %d, %d,"
2766                         " %d; dst: %d, %d, %d, %d;"
2767                         "clip: %d, %d, %d, %d\n",
2768                         pipe_ctx->pipe_idx,
2769                         (void *) pipe_ctx->plane_state,
2770                         pipe_ctx->plane_state->address.grph.addr.high_part,
2771                         pipe_ctx->plane_state->address.grph.addr.low_part,
2772                         pipe_ctx->plane_state->src_rect.x,
2773                         pipe_ctx->plane_state->src_rect.y,
2774                         pipe_ctx->plane_state->src_rect.width,
2775                         pipe_ctx->plane_state->src_rect.height,
2776                         pipe_ctx->plane_state->dst_rect.x,
2777                         pipe_ctx->plane_state->dst_rect.y,
2778                         pipe_ctx->plane_state->dst_rect.width,
2779                         pipe_ctx->plane_state->dst_rect.height,
2780                         pipe_ctx->plane_state->clip_rect.x,
2781                         pipe_ctx->plane_state->clip_rect.y,
2782                         pipe_ctx->plane_state->clip_rect.width,
2783                         pipe_ctx->plane_state->clip_rect.height);
2784
2785         DC_LOG_SURFACE(
2786                         "Pipe %d: width, height, x, y\n"
2787                         "viewport:%d, %d, %d, %d\n"
2788                         "recout:  %d, %d, %d, %d\n",
2789                         pipe_ctx->pipe_idx,
2790                         pipe_ctx->plane_res.scl_data.viewport.width,
2791                         pipe_ctx->plane_res.scl_data.viewport.height,
2792                         pipe_ctx->plane_res.scl_data.viewport.x,
2793                         pipe_ctx->plane_res.scl_data.viewport.y,
2794                         pipe_ctx->plane_res.scl_data.recout.width,
2795                         pipe_ctx->plane_res.scl_data.recout.height,
2796                         pipe_ctx->plane_res.scl_data.recout.x,
2797                         pipe_ctx->plane_res.scl_data.recout.y);
2798 }
2799
2800 static void dce110_apply_ctx_for_surface(
2801                 struct dc *dc,
2802                 const struct dc_stream_state *stream,
2803                 int num_planes,
2804                 struct dc_state *context)
2805 {
2806         int i;
2807
2808         if (num_planes == 0)
2809                 return;
2810
2811         if (dc->fbc_compressor)
2812                 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
2813
2814         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2815                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2816
2817                 if (pipe_ctx->stream != stream)
2818                         continue;
2819
2820                 /* Need to allocate mem before program front end for Fiji */
2821                 pipe_ctx->plane_res.mi->funcs->allocate_mem_input(
2822                                 pipe_ctx->plane_res.mi,
2823                                 pipe_ctx->stream->timing.h_total,
2824                                 pipe_ctx->stream->timing.v_total,
2825                                 pipe_ctx->stream->timing.pix_clk_100hz / 10,
2826                                 context->stream_count);
2827
2828                 dce110_program_front_end_for_pipe(dc, pipe_ctx);
2829
2830                 dc->hwss.update_plane_addr(dc, pipe_ctx);
2831
2832                 program_surface_visibility(dc, pipe_ctx);
2833
2834         }
2835
2836         if (dc->fbc_compressor)
2837                 enable_fbc(dc, context);
2838 }
2839
2840 static void dce110_post_unlock_program_front_end(
2841                 struct dc *dc,
2842                 struct dc_state *context)
2843 {
2844 }
2845
2846 static void dce110_power_down_fe(struct dc *dc, struct pipe_ctx *pipe_ctx)
2847 {
2848         struct dce_hwseq *hws = dc->hwseq;
2849         int fe_idx = pipe_ctx->plane_res.mi ?
2850                 pipe_ctx->plane_res.mi->inst : pipe_ctx->pipe_idx;
2851
2852         /* Do not power down fe when stream is active on dce*/
2853         if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream)
2854                 return;
2855
2856         hws->funcs.enable_display_power_gating(
2857                 dc, fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE);
2858
2859         dc->res_pool->transforms[fe_idx]->funcs->transform_reset(
2860                                 dc->res_pool->transforms[fe_idx]);
2861 }
2862
2863 static void dce110_wait_for_mpcc_disconnect(
2864                 struct dc *dc,
2865                 struct resource_pool *res_pool,
2866                 struct pipe_ctx *pipe_ctx)
2867 {
2868         /* do nothing*/
2869 }
2870
2871 static void program_output_csc(struct dc *dc,
2872                 struct pipe_ctx *pipe_ctx,
2873                 enum dc_color_space colorspace,
2874                 uint16_t *matrix,
2875                 int opp_id)
2876 {
2877         int i;
2878         struct out_csc_color_matrix tbl_entry;
2879
2880         if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
2881                 enum dc_color_space color_space = pipe_ctx->stream->output_color_space;
2882
2883                 for (i = 0; i < 12; i++)
2884                         tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i];
2885
2886                 tbl_entry.color_space = color_space;
2887
2888                 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment(
2889                                 pipe_ctx->plane_res.xfm, &tbl_entry);
2890         }
2891 }
2892
2893 static void dce110_set_cursor_position(struct pipe_ctx *pipe_ctx)
2894 {
2895         struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position;
2896         struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
2897         struct mem_input *mi = pipe_ctx->plane_res.mi;
2898         struct dc_cursor_mi_param param = {
2899                 .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10,
2900                 .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.xtalin_clock_inKhz,
2901                 .viewport = pipe_ctx->plane_res.scl_data.viewport,
2902                 .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz,
2903                 .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert,
2904                 .rotation = pipe_ctx->plane_state->rotation,
2905                 .mirror = pipe_ctx->plane_state->horizontal_mirror
2906         };
2907
2908         /**
2909          * If the cursor's source viewport is clipped then we need to
2910          * translate the cursor to appear in the correct position on
2911          * the screen.
2912          *
2913          * This translation isn't affected by scaling so it needs to be
2914          * done *after* we adjust the position for the scale factor.
2915          *
2916          * This is only done by opt-in for now since there are still
2917          * some usecases like tiled display that might enable the
2918          * cursor on both streams while expecting dc to clip it.
2919          */
2920         if (pos_cpy.translate_by_source) {
2921                 pos_cpy.x += pipe_ctx->plane_state->src_rect.x;
2922                 pos_cpy.y += pipe_ctx->plane_state->src_rect.y;
2923         }
2924
2925         if (pipe_ctx->plane_state->address.type
2926                         == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
2927                 pos_cpy.enable = false;
2928
2929         if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)
2930                 pos_cpy.enable = false;
2931
2932         if (ipp->funcs->ipp_cursor_set_position)
2933                 ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, &param);
2934         if (mi->funcs->set_cursor_position)
2935                 mi->funcs->set_cursor_position(mi, &pos_cpy, &param);
2936 }
2937
2938 static void dce110_set_cursor_attribute(struct pipe_ctx *pipe_ctx)
2939 {
2940         struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes;
2941
2942         if (pipe_ctx->plane_res.ipp &&
2943             pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes)
2944                 pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes(
2945                                 pipe_ctx->plane_res.ipp, attributes);
2946
2947         if (pipe_ctx->plane_res.mi &&
2948             pipe_ctx->plane_res.mi->funcs->set_cursor_attributes)
2949                 pipe_ctx->plane_res.mi->funcs->set_cursor_attributes(
2950                                 pipe_ctx->plane_res.mi, attributes);
2951
2952         if (pipe_ctx->plane_res.xfm &&
2953             pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes)
2954                 pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes(
2955                                 pipe_ctx->plane_res.xfm, attributes);
2956 }
2957
2958 bool dce110_set_backlight_level(struct pipe_ctx *pipe_ctx,
2959                 uint32_t backlight_pwm_u16_16,
2960                 uint32_t frame_ramp)
2961 {
2962         struct dc_link *link = pipe_ctx->stream->link;
2963         struct dc  *dc = link->ctx->dc;
2964         struct abm *abm = pipe_ctx->stream_res.abm;
2965         struct panel_cntl *panel_cntl = link->panel_cntl;
2966         struct dmcu *dmcu = dc->res_pool->dmcu;
2967         bool fw_set_brightness = true;
2968         /* DMCU -1 for all controller id values,
2969          * therefore +1 here
2970          */
2971         uint32_t controller_id = pipe_ctx->stream_res.tg->inst + 1;
2972
2973         if (abm == NULL || panel_cntl == NULL || (abm->funcs->set_backlight_level_pwm == NULL))
2974                 return false;
2975
2976         if (dmcu)
2977                 fw_set_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);
2978
2979         if (!fw_set_brightness && panel_cntl->funcs->driver_set_backlight)
2980                 panel_cntl->funcs->driver_set_backlight(panel_cntl, backlight_pwm_u16_16);
2981         else
2982                 abm->funcs->set_backlight_level_pwm(
2983                                 abm,
2984                                 backlight_pwm_u16_16,
2985                                 frame_ramp,
2986                                 controller_id,
2987                                 link->panel_cntl->inst);
2988
2989         return true;
2990 }
2991
2992 void dce110_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx)
2993 {
2994         struct abm *abm = pipe_ctx->stream_res.abm;
2995         struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl;
2996
2997         if (abm)
2998                 abm->funcs->set_abm_immediate_disable(abm,
2999                                 pipe_ctx->stream->link->panel_cntl->inst);
3000
3001         if (panel_cntl)
3002                 panel_cntl->funcs->store_backlight_level(panel_cntl);
3003 }
3004
3005 void dce110_set_pipe(struct pipe_ctx *pipe_ctx)
3006 {
3007         struct abm *abm = pipe_ctx->stream_res.abm;
3008         struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl;
3009         uint32_t otg_inst = pipe_ctx->stream_res.tg->inst + 1;
3010
3011         if (abm && panel_cntl)
3012                 abm->funcs->set_pipe(abm, otg_inst, panel_cntl->inst);
3013 }
3014
3015 void dce110_enable_lvds_link_output(struct dc_link *link,
3016                 const struct link_resource *link_res,
3017                 enum clock_source_id clock_source,
3018                 uint32_t pixel_clock)
3019 {
3020         link->link_enc->funcs->enable_lvds_output(
3021                         link->link_enc,
3022                         clock_source,
3023                         pixel_clock);
3024         link->phy_state.symclk_state = SYMCLK_ON_TX_ON;
3025 }
3026
3027 void dce110_enable_tmds_link_output(struct dc_link *link,
3028                 const struct link_resource *link_res,
3029                 enum signal_type signal,
3030                 enum clock_source_id clock_source,
3031                 enum dc_color_depth color_depth,
3032                 uint32_t pixel_clock)
3033 {
3034         link->link_enc->funcs->enable_tmds_output(
3035                         link->link_enc,
3036                         clock_source,
3037                         color_depth,
3038                         signal,
3039                         pixel_clock);
3040         link->phy_state.symclk_state = SYMCLK_ON_TX_ON;
3041 }
3042
3043 void dce110_enable_dp_link_output(
3044                 struct dc_link *link,
3045                 const struct link_resource *link_res,
3046                 enum signal_type signal,
3047                 enum clock_source_id clock_source,
3048                 const struct dc_link_settings *link_settings)
3049 {
3050         struct dc  *dc = link->ctx->dc;
3051         struct dmcu *dmcu = dc->res_pool->dmcu;
3052         struct pipe_ctx *pipes =
3053                         link->dc->current_state->res_ctx.pipe_ctx;
3054         struct clock_source *dp_cs =
3055                         link->dc->res_pool->dp_clock_source;
3056         const struct link_hwss *link_hwss = get_link_hwss(link, link_res);
3057         unsigned int i;
3058
3059         /*
3060          * Add the logic to extract BOTH power up and power down sequences
3061          * from enable/disable link output and only call edp panel control
3062          * in enable_link_dp and disable_link_dp once.
3063          */
3064         if (link->connector_signal == SIGNAL_TYPE_EDP) {
3065                 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
3066         }
3067
3068         /* If the current pixel clock source is not DTO(happens after
3069          * switching from HDMI passive dongle to DP on the same connector),
3070          * switch the pixel clock source to DTO.
3071          */
3072
3073         for (i = 0; i < MAX_PIPES; i++) {
3074                 if (pipes[i].stream != NULL &&
3075                                 pipes[i].stream->link == link) {
3076                         if (pipes[i].clock_source != NULL &&
3077                                         pipes[i].clock_source->id != CLOCK_SOURCE_ID_DP_DTO) {
3078                                 pipes[i].clock_source = dp_cs;
3079                                 pipes[i].stream_res.pix_clk_params.requested_pix_clk_100hz =
3080                                                 pipes[i].stream->timing.pix_clk_100hz;
3081                                 pipes[i].clock_source->funcs->program_pix_clk(
3082                                                 pipes[i].clock_source,
3083                                                 &pipes[i].stream_res.pix_clk_params,
3084                                                 dc->link_srv->dp_get_encoding_format(link_settings),
3085                                                 &pipes[i].pll_settings);
3086                         }
3087                 }
3088         }
3089
3090         if (dc->link_srv->dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING) {
3091                 if (dc->clk_mgr->funcs->notify_link_rate_change)
3092                         dc->clk_mgr->funcs->notify_link_rate_change(dc->clk_mgr, link);
3093         }
3094
3095         if (dmcu != NULL && dmcu->funcs->lock_phy)
3096                 dmcu->funcs->lock_phy(dmcu);
3097
3098         if (link_hwss->ext.enable_dp_link_output)
3099                 link_hwss->ext.enable_dp_link_output(link, link_res, signal,
3100                                 clock_source, link_settings);
3101
3102         link->phy_state.symclk_state = SYMCLK_ON_TX_ON;
3103
3104         if (dmcu != NULL && dmcu->funcs->unlock_phy)
3105                 dmcu->funcs->unlock_phy(dmcu);
3106
3107         dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_ENABLE_LINK_PHY);
3108 }
3109
3110 void dce110_disable_link_output(struct dc_link *link,
3111                 const struct link_resource *link_res,
3112                 enum signal_type signal)
3113 {
3114         struct dc *dc = link->ctx->dc;
3115         const struct link_hwss *link_hwss = get_link_hwss(link, link_res);
3116         struct dmcu *dmcu = dc->res_pool->dmcu;
3117
3118         if (signal == SIGNAL_TYPE_EDP &&
3119                         link->dc->hwss.edp_backlight_control)
3120                 link->dc->hwss.edp_backlight_control(link, false);
3121         else if (dmcu != NULL && dmcu->funcs->lock_phy)
3122                 dmcu->funcs->lock_phy(dmcu);
3123
3124         link_hwss->disable_link_output(link, link_res, signal);
3125         link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF;
3126         /*
3127          * Add the logic to extract BOTH power up and power down sequences
3128          * from enable/disable link output and only call edp panel control
3129          * in enable_link_dp and disable_link_dp once.
3130          */
3131         if (dmcu != NULL && dmcu->funcs->lock_phy)
3132                 dmcu->funcs->unlock_phy(dmcu);
3133         dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY);
3134 }
3135
3136 static const struct hw_sequencer_funcs dce110_funcs = {
3137         .program_gamut_remap = program_gamut_remap,
3138         .program_output_csc = program_output_csc,
3139         .init_hw = init_hw,
3140         .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
3141         .apply_ctx_for_surface = dce110_apply_ctx_for_surface,
3142         .post_unlock_program_front_end = dce110_post_unlock_program_front_end,
3143         .update_plane_addr = update_plane_addr,
3144         .update_pending_status = dce110_update_pending_status,
3145         .enable_accelerated_mode = dce110_enable_accelerated_mode,
3146         .enable_timing_synchronization = dce110_enable_timing_synchronization,
3147         .enable_per_frame_crtc_position_reset = dce110_enable_per_frame_crtc_position_reset,
3148         .update_info_frame = dce110_update_info_frame,
3149         .enable_stream = dce110_enable_stream,
3150         .disable_stream = dce110_disable_stream,
3151         .unblank_stream = dce110_unblank_stream,
3152         .blank_stream = dce110_blank_stream,
3153         .enable_audio_stream = dce110_enable_audio_stream,
3154         .disable_audio_stream = dce110_disable_audio_stream,
3155         .disable_plane = dce110_power_down_fe,
3156         .pipe_control_lock = dce_pipe_control_lock,
3157         .interdependent_update_lock = NULL,
3158         .cursor_lock = dce_pipe_control_lock,
3159         .prepare_bandwidth = dce110_prepare_bandwidth,
3160         .optimize_bandwidth = dce110_optimize_bandwidth,
3161         .set_drr = set_drr,
3162         .get_position = get_position,
3163         .set_static_screen_control = set_static_screen_control,
3164         .setup_stereo = NULL,
3165         .set_avmute = dce110_set_avmute,
3166         .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect,
3167         .edp_backlight_control = dce110_edp_backlight_control,
3168         .edp_power_control = dce110_edp_power_control,
3169         .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
3170         .set_cursor_position = dce110_set_cursor_position,
3171         .set_cursor_attribute = dce110_set_cursor_attribute,
3172         .set_backlight_level = dce110_set_backlight_level,
3173         .set_abm_immediate_disable = dce110_set_abm_immediate_disable,
3174         .set_pipe = dce110_set_pipe,
3175         .enable_lvds_link_output = dce110_enable_lvds_link_output,
3176         .enable_tmds_link_output = dce110_enable_tmds_link_output,
3177         .enable_dp_link_output = dce110_enable_dp_link_output,
3178         .disable_link_output = dce110_disable_link_output,
3179 };
3180
3181 static const struct hwseq_private_funcs dce110_private_funcs = {
3182         .init_pipes = init_pipes,
3183         .update_plane_addr = update_plane_addr,
3184         .set_input_transfer_func = dce110_set_input_transfer_func,
3185         .set_output_transfer_func = dce110_set_output_transfer_func,
3186         .power_down = dce110_power_down,
3187         .enable_display_pipe_clock_gating = enable_display_pipe_clock_gating,
3188         .enable_display_power_gating = dce110_enable_display_power_gating,
3189         .reset_hw_ctx_wrap = dce110_reset_hw_ctx_wrap,
3190         .enable_stream_timing = dce110_enable_stream_timing,
3191         .disable_stream_gating = NULL,
3192         .enable_stream_gating = NULL,
3193         .edp_backlight_control = dce110_edp_backlight_control,
3194 };
3195
3196 void dce110_hw_sequencer_construct(struct dc *dc)
3197 {
3198         dc->hwss = dce110_funcs;
3199         dc->hwseq->funcs = dce110_private_funcs;
3200 }
3201