2 * Copyright 2018 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
27 * Pre-requisites: headers required by header of this unit
29 #include "hw_translate_dcn20.h"
31 #include "dm_services.h"
32 #include "include/gpio_types.h"
33 #include "../hw_translate.h"
35 #include "dcn/dcn_1_0_offset.h"
36 #include "dcn/dcn_1_0_sh_mask.h"
37 #include "soc15_hw_ip.h"
38 #include "vega10_ip_offset.h"
42 /* begin *********************
43 * macros to expend register list macro defined in HW object header file */
50 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
52 #define BASE(seg) BASE_INNER(seg)
55 #define REG(reg_name)\
56 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
57 #define SF_HPD(reg_name, field_name, post_fix)\
58 .field_name = reg_name ## __ ## field_name ## post_fix
61 /* macros to expend register list macro defined in HW object header file
62 * end *********************/
65 static bool offset_to_id(
73 case REG(DC_GPIO_GENERIC_A):
74 *id = GPIO_ID_GENERIC;
76 case DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK:
79 case DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK:
82 case DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK:
85 case DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK:
88 case DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK:
91 case DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK:
94 case DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK:
98 ASSERT_CRITICAL(false);
103 case REG(DC_GPIO_HPD_A):
106 case DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK:
109 case DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK:
112 case DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK:
115 case DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK:
118 case DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK:
121 case DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK:
125 ASSERT_CRITICAL(false);
129 /* REG(DC_GPIO_GENLK_MASK */
130 case REG(DC_GPIO_GENLK_A):
133 case DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK:
134 *en = GPIO_GSL_GENLOCK_CLOCK;
136 case DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK:
137 *en = GPIO_GSL_GENLOCK_VSYNC;
139 case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK:
140 *en = GPIO_GSL_SWAPLOCK_A;
142 case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK:
143 *en = GPIO_GSL_SWAPLOCK_B;
146 ASSERT_CRITICAL(false);
151 /* we don't care about the GPIO_ID for DDC
152 * in DdcHandle it will use GPIO_ID_DDC_DATA/GPIO_ID_DDC_CLOCK
153 * directly in the create method */
154 case REG(DC_GPIO_DDC1_A):
155 *en = GPIO_DDC_LINE_DDC1;
157 case REG(DC_GPIO_DDC2_A):
158 *en = GPIO_DDC_LINE_DDC2;
160 case REG(DC_GPIO_DDC3_A):
161 *en = GPIO_DDC_LINE_DDC3;
163 case REG(DC_GPIO_DDC4_A):
164 *en = GPIO_DDC_LINE_DDC4;
166 case REG(DC_GPIO_DDC5_A):
167 *en = GPIO_DDC_LINE_DDC5;
169 case REG(DC_GPIO_DDC6_A):
170 *en = GPIO_DDC_LINE_DDC6;
172 case REG(DC_GPIO_DDCVGA_A):
173 *en = GPIO_DDC_LINE_DDC_VGA;
176 // case REG(DC_GPIO_I2CPAD_A): not exit
177 // case REG(DC_GPIO_PWRSEQ_A):
178 // case REG(DC_GPIO_PAD_STRENGTH_1):
179 // case REG(DC_GPIO_PAD_STRENGTH_2):
180 // case REG(DC_GPIO_DEBUG):
183 // case REG(DC_GPIO_SYNCA_A): not exist
184 ASSERT_CRITICAL(false);
189 static bool id_to_offset(
192 struct gpio_pin_info *info)
197 case GPIO_ID_DDC_DATA:
198 info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK;
200 case GPIO_DDC_LINE_DDC1:
201 info->offset = REG(DC_GPIO_DDC1_A);
203 case GPIO_DDC_LINE_DDC2:
204 info->offset = REG(DC_GPIO_DDC2_A);
206 case GPIO_DDC_LINE_DDC3:
207 info->offset = REG(DC_GPIO_DDC3_A);
209 case GPIO_DDC_LINE_DDC4:
210 info->offset = REG(DC_GPIO_DDC4_A);
212 case GPIO_DDC_LINE_DDC5:
213 info->offset = REG(DC_GPIO_DDC5_A);
215 case GPIO_DDC_LINE_DDC6:
216 info->offset = REG(DC_GPIO_DDC6_A);
218 case GPIO_DDC_LINE_DDC_VGA:
219 info->offset = REG(DC_GPIO_DDCVGA_A);
221 case GPIO_DDC_LINE_I2C_PAD:
223 ASSERT_CRITICAL(false);
227 case GPIO_ID_DDC_CLOCK:
228 info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK;
230 case GPIO_DDC_LINE_DDC1:
231 info->offset = REG(DC_GPIO_DDC1_A);
233 case GPIO_DDC_LINE_DDC2:
234 info->offset = REG(DC_GPIO_DDC2_A);
236 case GPIO_DDC_LINE_DDC3:
237 info->offset = REG(DC_GPIO_DDC3_A);
239 case GPIO_DDC_LINE_DDC4:
240 info->offset = REG(DC_GPIO_DDC4_A);
242 case GPIO_DDC_LINE_DDC5:
243 info->offset = REG(DC_GPIO_DDC5_A);
245 case GPIO_DDC_LINE_DDC6:
246 info->offset = REG(DC_GPIO_DDC6_A);
248 case GPIO_DDC_LINE_DDC_VGA:
249 info->offset = REG(DC_GPIO_DDCVGA_A);
251 case GPIO_DDC_LINE_I2C_PAD:
253 ASSERT_CRITICAL(false);
257 case GPIO_ID_GENERIC:
258 info->offset = REG(DC_GPIO_GENERIC_A);
261 info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK;
264 info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK;
267 info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK;
270 info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK;
273 info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK;
276 info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK;
279 info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK;
282 ASSERT_CRITICAL(false);
287 info->offset = REG(DC_GPIO_HPD_A);
290 info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK;
293 info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK;
296 info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK;
299 info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK;
302 info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK;
305 info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK;
308 ASSERT_CRITICAL(false);
314 case GPIO_GSL_GENLOCK_CLOCK:
316 ASSERT_CRITICAL(false);
319 case GPIO_GSL_GENLOCK_VSYNC:
321 ASSERT_CRITICAL(false);
324 case GPIO_GSL_SWAPLOCK_A:
326 ASSERT_CRITICAL(false);
329 case GPIO_GSL_SWAPLOCK_B:
331 ASSERT_CRITICAL(false);
336 ASSERT_CRITICAL(false);
341 case GPIO_ID_VIP_PAD:
343 ASSERT_CRITICAL(false);
348 info->offset_y = info->offset + 2;
349 info->offset_en = info->offset + 1;
350 info->offset_mask = info->offset - 1;
352 info->mask_y = info->mask;
353 info->mask_en = info->mask;
354 info->mask_mask = info->mask;
361 static const struct hw_translate_funcs funcs = {
362 .offset_to_id = offset_to_id,
363 .id_to_offset = id_to_offset,
367 * dal_hw_translate_dcn10_init
370 * Initialize Hw translate function pointers.
373 * struct hw_translate *tr - [out] struct of function pointers
376 void dal_hw_translate_dcn20_init(struct hw_translate *tr)