2 * Copyright 2013-15 Advanced Micro Devices, Inc.
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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25 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
26 #include "dm_services.h"
27 #include "include/gpio_types.h"
28 #include "../hw_factory.h"
31 #include "../hw_gpio.h"
32 #include "../hw_ddc.h"
33 #include "../hw_hpd.h"
34 #include "../hw_generic.h"
36 #include "hw_factory_dcn20.h"
39 #include "dcn/dcn_2_0_0_offset.h"
40 #include "dcn/dcn_2_0_0_sh_mask.h"
41 #include "navi10_ip_offset.h"
44 #include "reg_helper.h"
45 #include "../hpd_regs.h"
46 /* begin *********************
47 * macros to expend register list macro defined in HW object header file */
54 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
56 #define BASE(seg) BASE_INNER(seg)
60 #define REG(reg_name)\
61 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
63 #define SF_HPD(reg_name, field_name, post_fix)\
64 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
66 #define REGI(reg_name, block, id)\
67 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
68 mm ## block ## id ## _ ## reg_name
70 #define SF(reg_name, field_name, post_fix)\
71 .field_name = reg_name ## __ ## field_name ## post_fix
73 /* macros to expend register list macro defined in HW object header file
74 * end *********************/
78 #define hpd_regs(id) \
83 static const struct hpd_registers hpd_regs[] = {
92 static const struct hpd_sh_mask hpd_shift = {
93 HPD_MASK_SH_LIST(__SHIFT)
96 static const struct hpd_sh_mask hpd_mask = {
97 HPD_MASK_SH_LIST(_MASK)
100 #include "../ddc_regs.h"
103 #define SF_DDC(reg_name, field_name, post_fix)\
104 .field_name = reg_name ## __ ## field_name ## post_fix
106 static const struct ddc_registers ddc_data_regs_dcn[] = {
107 ddc_data_regs_dcn2(1),
108 ddc_data_regs_dcn2(2),
109 ddc_data_regs_dcn2(3),
110 ddc_data_regs_dcn2(4),
111 ddc_data_regs_dcn2(5),
112 ddc_data_regs_dcn2(6),
114 DDC_GPIO_VGA_REG_LIST(DATA),
117 .dc_gpio_aux_ctrl_5 = 0
121 static const struct ddc_registers ddc_clk_regs_dcn[] = {
122 ddc_clk_regs_dcn2(1),
123 ddc_clk_regs_dcn2(2),
124 ddc_clk_regs_dcn2(3),
125 ddc_clk_regs_dcn2(4),
126 ddc_clk_regs_dcn2(5),
127 ddc_clk_regs_dcn2(6),
129 DDC_GPIO_VGA_REG_LIST(CLK),
132 .dc_gpio_aux_ctrl_5 = 0
136 static const struct ddc_sh_mask ddc_shift[] = {
137 DDC_MASK_SH_LIST_DCN2(__SHIFT, 1),
138 DDC_MASK_SH_LIST_DCN2(__SHIFT, 2),
139 DDC_MASK_SH_LIST_DCN2(__SHIFT, 3),
140 DDC_MASK_SH_LIST_DCN2(__SHIFT, 4),
141 DDC_MASK_SH_LIST_DCN2(__SHIFT, 5),
142 DDC_MASK_SH_LIST_DCN2(__SHIFT, 6)
145 static const struct ddc_sh_mask ddc_mask[] = {
146 DDC_MASK_SH_LIST_DCN2(_MASK, 1),
147 DDC_MASK_SH_LIST_DCN2(_MASK, 2),
148 DDC_MASK_SH_LIST_DCN2(_MASK, 3),
149 DDC_MASK_SH_LIST_DCN2(_MASK, 4),
150 DDC_MASK_SH_LIST_DCN2(_MASK, 5),
151 DDC_MASK_SH_LIST_DCN2(_MASK, 6)
154 #include "../generic_regs.h"
157 #define SF_GENERIC(reg_name, field_name, post_fix)\
158 .field_name = reg_name ## __ ## field_name ## post_fix
160 #define generic_regs(id) \
162 GENERIC_REG_LIST(id)\
165 static const struct generic_registers generic_regs[] = {
170 static const struct generic_sh_mask generic_shift[] = {
171 GENERIC_MASK_SH_LIST(__SHIFT, A),
172 GENERIC_MASK_SH_LIST(__SHIFT, B),
175 static const struct generic_sh_mask generic_mask[] = {
176 GENERIC_MASK_SH_LIST(_MASK, A),
177 GENERIC_MASK_SH_LIST(_MASK, B),
180 static void define_ddc_registers(
181 struct hw_gpio_pin *pin,
184 struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin);
187 case GPIO_ID_DDC_DATA:
188 ddc->regs = &ddc_data_regs_dcn[en];
189 ddc->base.regs = &ddc_data_regs_dcn[en].gpio;
191 case GPIO_ID_DDC_CLOCK:
192 ddc->regs = &ddc_clk_regs_dcn[en];
193 ddc->base.regs = &ddc_clk_regs_dcn[en].gpio;
196 ASSERT_CRITICAL(false);
200 ddc->shifts = &ddc_shift[en];
201 ddc->masks = &ddc_mask[en];
205 static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en)
207 struct hw_hpd *hpd = HW_HPD_FROM_BASE(pin);
209 hpd->regs = &hpd_regs[en];
210 hpd->shifts = &hpd_shift;
211 hpd->masks = &hpd_mask;
212 hpd->base.regs = &hpd_regs[en].gpio;
215 static void define_generic_registers(struct hw_gpio_pin *pin, uint32_t en)
217 struct hw_generic *generic = HW_GENERIC_FROM_BASE(pin);
219 generic->regs = &generic_regs[en];
220 generic->shifts = &generic_shift[en];
221 generic->masks = &generic_mask[en];
222 generic->base.regs = &generic_regs[en].gpio;
226 static const struct hw_factory_funcs funcs = {
227 .init_ddc_data = dal_hw_ddc_init,
228 .init_generic = dal_hw_generic_init,
229 .init_hpd = dal_hw_hpd_init,
230 .get_ddc_pin = dal_hw_ddc_get_pin,
231 .get_hpd_pin = dal_hw_hpd_get_pin,
232 .get_generic_pin = dal_hw_generic_get_pin,
233 .define_hpd_registers = define_hpd_registers,
234 .define_ddc_registers = define_ddc_registers,
235 .define_generic_registers = define_generic_registers,
238 * dal_hw_factory_dcn10_init
241 * Initialize HW factory function pointers and pin info
244 * struct hw_factory *factory - [out] struct of function pointers
246 void dal_hw_factory_dcn20_init(struct hw_factory *factory)
248 /*TODO check ASIC CAPs*/
249 factory->number_of_pins[GPIO_ID_DDC_DATA] = 8;
250 factory->number_of_pins[GPIO_ID_DDC_CLOCK] = 8;
251 factory->number_of_pins[GPIO_ID_GENERIC] = 4;
252 factory->number_of_pins[GPIO_ID_HPD] = 6;
253 factory->number_of_pins[GPIO_ID_GPIO_PAD] = 28;
254 factory->number_of_pins[GPIO_ID_VIP_PAD] = 0;
255 factory->number_of_pins[GPIO_ID_SYNC] = 0;
256 factory->number_of_pins[GPIO_ID_GSL] = 0;/*add this*/
258 factory->funcs = &funcs;