interconnect: qcom: icc-rpm: Fix peak rate calculation
[linux-2.6-microblaze.git] / drivers / gpu / drm / amd / display / dc / dml2 / dml2_wrapper.h
1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Copyright 2023 Advanced Micro Devices, Inc.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  *
23  * Authors: AMD
24  *
25  */
26
27 #ifndef _DML2_WRAPPER_H_
28 #define _DML2_WRAPPER_H_
29
30 #include "os_types.h"
31
32 #define DML2_MAX_NUM_DPM_LVL 30
33
34 struct dml2_context;
35 struct display_mode_lib_st;
36 struct dc;
37 struct pipe_ctx;
38 struct dc_plane_state;
39 struct dc_sink;
40 struct dc_stream_state;
41 struct resource_context;
42 struct display_stream_compressor;
43
44 // Configuration of the MALL on the SoC
45 struct dml2_soc_mall_info {
46         // Cache line size of 0 means MALL is not enabled/present
47         unsigned int cache_line_size_bytes;
48         unsigned int cache_num_ways;
49         unsigned int max_cab_allocation_bytes;
50
51         unsigned int mblk_width_pixels;
52         unsigned int mblk_size_bytes;
53         unsigned int mblk_height_4bpe_pixels;
54         unsigned int mblk_height_8bpe_pixels;
55 };
56
57 // Output of DML2 for clock requirements
58 struct dml2_dcn_clocks {
59         unsigned int dispclk_khz;
60         unsigned int dcfclk_khz;
61         unsigned int fclk_khz;
62         unsigned int uclk_mts;
63         unsigned int phyclk_khz;
64         unsigned int socclk_khz;
65         unsigned int ref_dtbclk_khz;
66         bool p_state_supported;
67         unsigned int cab_num_ways_required;
68         unsigned int dcfclk_khz_ds;
69 };
70
71 struct dml2_dc_callbacks {
72         struct dc *dc;
73         bool (*build_scaling_params)(struct pipe_ctx *pipe_ctx);
74         bool (*can_support_mclk_switch_using_fw_based_vblank_stretch)(struct dc *dc, struct dc_state *context);
75         bool (*acquire_secondary_pipe_for_mpc_odm)(const struct dc *dc, struct dc_state *state, struct pipe_ctx *pri_pipe, struct pipe_ctx *sec_pipe, bool odm);
76         bool (*update_pipes_for_stream_with_slice_count)(
77                         struct dc_state *new_ctx,
78                         const struct dc_state *cur_ctx,
79                         const struct resource_pool *pool,
80                         const struct dc_stream_state *stream,
81                         int new_slice_count);
82         bool (*update_pipes_for_plane_with_slice_count)(
83                         struct dc_state *new_ctx,
84                         const struct dc_state *cur_ctx,
85                         const struct resource_pool *pool,
86                         const struct dc_plane_state *plane,
87                         int slice_count);
88         int (*get_odm_slice_index)(const struct pipe_ctx *opp_head);
89         int (*get_mpc_slice_index)(const struct pipe_ctx *dpp_pipe);
90         struct pipe_ctx *(*get_opp_head)(const struct pipe_ctx *pipe_ctx);
91 };
92
93 struct dml2_dc_svp_callbacks {
94         struct dc *dc;
95         bool (*build_scaling_params)(struct pipe_ctx *pipe_ctx);
96         struct dc_stream_state* (*create_stream_for_sink)(struct dc_sink *dc_sink_data);
97         struct dc_plane_state* (*create_plane)(struct dc *dc);
98         enum dc_status (*add_stream_to_ctx)(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream);
99         bool (*add_plane_to_context)(const struct dc *dc, struct dc_stream_state *stream, struct dc_plane_state *plane_state, struct dc_state *context);
100         bool (*remove_plane_from_context)(const struct dc *dc, struct dc_stream_state *stream, struct dc_plane_state *plane_state, struct dc_state *context);
101         enum dc_status (*remove_stream_from_ctx)(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *stream);
102         void (*plane_state_release)(struct dc_plane_state *plane_state);
103         void (*stream_release)(struct dc_stream_state *stream);
104         void (*release_dsc)(struct resource_context *res_ctx, const struct resource_pool *pool, struct display_stream_compressor **dsc);
105 };
106
107 struct dml2_clks_table_entry {
108         unsigned int dcfclk_mhz;
109         unsigned int fclk_mhz;
110         unsigned int memclk_mhz;
111         unsigned int socclk_mhz;
112         unsigned int dtbclk_mhz;
113         unsigned int dispclk_mhz;
114         unsigned int dppclk_mhz;
115 };
116
117 struct dml2_clks_num_entries {
118         unsigned int num_dcfclk_levels;
119         unsigned int num_fclk_levels;
120         unsigned int num_memclk_levels;
121         unsigned int num_socclk_levels;
122         unsigned int num_dtbclk_levels;
123         unsigned int num_dispclk_levels;
124         unsigned int num_dppclk_levels;
125 };
126
127 struct dml2_clks_limit_table {
128         struct dml2_clks_table_entry clk_entries[DML2_MAX_NUM_DPM_LVL];
129         struct dml2_clks_num_entries num_entries_per_clk;
130         unsigned int num_states;
131 };
132
133 // Various overrides, per ASIC or per SKU specific, or for debugging purpose when/if available
134 struct dml2_soc_bbox_overrides {
135         double xtalclk_mhz;
136         double dchub_refclk_mhz;
137         double dprefclk_mhz;
138         double disp_pll_vco_speed_mhz;
139         double urgent_latency_us;
140         double sr_exit_latency_us;
141         double sr_enter_plus_exit_latency_us;
142         double dram_clock_change_latency_us;
143         double fclk_change_latency_us;
144         unsigned int dram_num_chan;
145         unsigned int dram_chanel_width_bytes;
146         struct dml2_clks_limit_table clks_table;
147 };
148
149 struct dml2_configuration_options {
150         int dcn_pipe_count;
151         bool use_native_pstate_optimization;
152         bool enable_windowed_mpo_odm;
153         bool use_native_soc_bb_construction;
154         bool skip_hw_state_mapping;
155         bool optimize_odm_4to1;
156         bool minimize_dispclk_using_odm;
157         bool override_det_buffer_size_kbytes;
158         struct dml2_dc_callbacks callbacks;
159         struct {
160                 bool force_disable_subvp;
161                 bool force_enable_subvp;
162                 unsigned int subvp_fw_processing_delay_us;
163                 unsigned int subvp_pstate_allow_width_us;
164                 unsigned int subvp_prefetch_end_to_mall_start_us;
165                 unsigned int subvp_swath_height_margin_lines;
166                 struct dml2_dc_svp_callbacks callbacks;
167         } svp_pstate;
168         struct dml2_soc_mall_info mall_cfg;
169         struct dml2_soc_bbox_overrides bbox_overrides;
170         unsigned int max_segments_per_hubp;
171         unsigned int det_segment_size;
172         bool map_dc_pipes_with_callbacks;
173 };
174
175 /*
176  * dml2_create - Creates dml2_context.
177  * @in_dc: dc.
178  * @config: dml2 configuration options.
179  * @dml2: Created dml2 context.
180  *
181  * Create and destroy of DML2 is done as part of dc_state creation
182  * and dc_state_free. DML2 IP, SOC and STATES are initialized at
183  * creation time.
184  *
185  * Return: True if dml2 is successfully created, false otherwise.
186  */
187 bool dml2_create(const struct dc *in_dc,
188                                  const struct dml2_configuration_options *config,
189                                  struct dml2_context **dml2);
190
191 void dml2_destroy(struct dml2_context *dml2);
192
193 /*
194  * dml2_validate - Determines if a display configuration is supported or not.
195  * @in_dc: dc.
196  * @context: dc_state to be validated.
197  * @fast_validate: Fast validate will not populate context.res_ctx.
198  *
199  * DML1.0 compatible interface for validation.
200  *
201  * Based on fast_validate option internally would call:
202  *
203  * -dml2_validate_and_build_resource - for non fast_validate option
204  * Calculates if dc_state can be supported on the SOC, and attempts to
205  * optimize the power management feature supports versus minimum clocks.
206  * If supported, also builds out_new_hw_state to represent the hw programming
207  * for the new dc state.
208  *
209  * -dml2_validate_only - for fast_validate option
210  * Calculates if dc_state can be supported on the SOC (i.e. at maximum
211  * clocks) with all mandatory power features enabled.
212
213  * Context: Two threads may not invoke this function concurrently unless they reference
214  *          separate dc_states for validation.
215  * Return: True if mode is supported, false otherwise.
216  */
217 bool dml2_validate(const struct dc *in_dc,
218                                    struct dc_state *context,
219                                    bool fast_validate);
220
221 /*
222  * dml2_extract_dram_and_fclk_change_support - Extracts the FCLK and UCLK change support info.
223  * @dml2: input dml2 context pointer.
224  * @fclk_change_support: output pointer holding the fclk change support info (vactive, vblank, unsupported).
225  * @dram_clk_change_support: output pointer holding the uclk change support info (vactive, vblank, unsupported).
226  */
227 void dml2_extract_dram_and_fclk_change_support(struct dml2_context *dml2,
228         unsigned int *fclk_change_support, unsigned int *dram_clk_change_support);
229
230 #endif //_DML2_WRAPPER_H_