drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26
  27 #ifndef __DML2_DISPLAY_MODE_VBA_H__
  28 #define __DML2_DISPLAY_MODE_VBA_H__
  29
  30 struct display_mode_lib;
  31
  32 void ModeSupportAndSystemConfiguration(struct display_mode_lib *mode_lib);
  33
  34 #define dml_get_attr_decl(attr) double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes)
  35
  36 dml_get_attr_decl(clk_dcf_deepsleep);
  37 dml_get_attr_decl(wm_urgent);
  38 dml_get_attr_decl(wm_memory_trip);
  39 dml_get_attr_decl(wm_writeback_urgent);
  40 dml_get_attr_decl(wm_stutter_exit);
  41 dml_get_attr_decl(wm_stutter_enter_exit);
  42 dml_get_attr_decl(wm_z8_stutter_exit);
  43 dml_get_attr_decl(wm_z8_stutter_enter_exit);
  44 dml_get_attr_decl(stutter_efficiency_z8);
  45 dml_get_attr_decl(stutter_num_bursts_z8);
  46 dml_get_attr_decl(wm_dram_clock_change);
  47 dml_get_attr_decl(wm_writeback_dram_clock_change);
  48 dml_get_attr_decl(stutter_efficiency_no_vblank);
  49 dml_get_attr_decl(stutter_efficiency);
  50 dml_get_attr_decl(stutter_period);
  51 dml_get_attr_decl(urgent_latency);
  52 dml_get_attr_decl(urgent_extra_latency);
  53 dml_get_attr_decl(nonurgent_latency);
  54 dml_get_attr_decl(dram_clock_change_latency);
  55 dml_get_attr_decl(dispclk_calculated);
  56 dml_get_attr_decl(total_data_read_bw);
  57 dml_get_attr_decl(return_bw);
  58 dml_get_attr_decl(tcalc);
  59 dml_get_attr_decl(fraction_of_urgent_bandwidth);
  60 dml_get_attr_decl(fraction_of_urgent_bandwidth_imm_flip);
  61 dml_get_attr_decl(cstate_max_cap_mode);
  62 dml_get_attr_decl(comp_buffer_size_kbytes);
  63 dml_get_attr_decl(pixel_chunk_size_in_kbyte);
  64 dml_get_attr_decl(alpha_pixel_chunk_size_in_kbyte);
  65 dml_get_attr_decl(meta_chunk_size_in_kbyte);
  66 dml_get_attr_decl(min_pixel_chunk_size_in_byte);
  67 dml_get_attr_decl(min_meta_chunk_size_in_byte);
  68 dml_get_attr_decl(fclk_watermark);
  69 dml_get_attr_decl(usr_retraining_watermark);
  70 dml_get_attr_decl(comp_buffer_reserved_space_kbytes);
  71 dml_get_attr_decl(comp_buffer_reserved_space_64bytes);
  72 dml_get_attr_decl(comp_buffer_reserved_space_zs);
  73 dml_get_attr_decl(unbounded_request_enabled);
  74
  75 #define dml_get_pipe_attr_decl(attr) double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes, unsigned int which_pipe)
  76
  77 dml_get_pipe_attr_decl(dsc_delay);
  78 dml_get_pipe_attr_decl(dppclk_calculated);
  79 dml_get_pipe_attr_decl(dscclk_calculated);
  80 dml_get_pipe_attr_decl(min_ttu_vblank);
  81 dml_get_pipe_attr_decl(min_ttu_vblank_in_us);
  82 dml_get_pipe_attr_decl(vratio_prefetch_l);
  83 dml_get_pipe_attr_decl(vratio_prefetch_c);
  84 dml_get_pipe_attr_decl(dst_x_after_scaler);
  85 dml_get_pipe_attr_decl(dst_y_after_scaler);
  86 dml_get_pipe_attr_decl(dst_y_per_vm_vblank);
  87 dml_get_pipe_attr_decl(dst_y_per_row_vblank);
  88 dml_get_pipe_attr_decl(dst_y_prefetch);
  89 dml_get_pipe_attr_decl(dst_y_per_vm_flip);
  90 dml_get_pipe_attr_decl(dst_y_per_row_flip);
  91 dml_get_pipe_attr_decl(dst_y_per_pte_row_nom_l);
  92 dml_get_pipe_attr_decl(dst_y_per_pte_row_nom_c);
  93 dml_get_pipe_attr_decl(dst_y_per_meta_row_nom_l);
  94 dml_get_pipe_attr_decl(dst_y_per_meta_row_nom_c);
  95 dml_get_pipe_attr_decl(dpte_row_height_linear_c);
  96 dml_get_pipe_attr_decl(swath_height_l);
  97 dml_get_pipe_attr_decl(swath_height_c);
  98 dml_get_pipe_attr_decl(det_stored_buffer_size_l_bytes);
  99 dml_get_pipe_attr_decl(det_stored_buffer_size_c_bytes);
 100 dml_get_pipe_attr_decl(dpte_group_size_in_bytes);
 101 dml_get_pipe_attr_decl(vm_group_size_in_bytes);
 102 dml_get_pipe_attr_decl(det_buffer_size_kbytes);
 103 dml_get_pipe_attr_decl(dpte_row_height_linear_l);
 104 dml_get_pipe_attr_decl(refcyc_per_pte_group_nom_l_in_us);
 105 dml_get_pipe_attr_decl(refcyc_per_pte_group_nom_c_in_us);
 106 dml_get_pipe_attr_decl(refcyc_per_pte_group_vblank_l_in_us);
 107 dml_get_pipe_attr_decl(refcyc_per_pte_group_vblank_c_in_us);
 108 dml_get_pipe_attr_decl(refcyc_per_pte_group_flip_l_in_us);
 109 dml_get_pipe_attr_decl(refcyc_per_pte_group_flip_c_in_us);
 110 dml_get_pipe_attr_decl(pte_buffer_mode);
 111 dml_get_pipe_attr_decl(refcyc_per_vm_group_vblank);
 112 dml_get_pipe_attr_decl(refcyc_per_vm_group_flip);
 113 dml_get_pipe_attr_decl(refcyc_per_vm_req_vblank);
 114 dml_get_pipe_attr_decl(refcyc_per_vm_req_flip);
 115 dml_get_pipe_attr_decl(refcyc_per_vm_group_vblank_in_us);
 116 dml_get_pipe_attr_decl(refcyc_per_vm_group_flip_in_us);
 117 dml_get_pipe_attr_decl(refcyc_per_vm_req_vblank_in_us);
 118 dml_get_pipe_attr_decl(refcyc_per_vm_req_flip_in_us);
 119 dml_get_pipe_attr_decl(refcyc_per_vm_dmdata_in_us);
 120 dml_get_pipe_attr_decl(dmdata_dl_delta_in_us);
 121 dml_get_pipe_attr_decl(refcyc_per_line_delivery_l_in_us);
 122 dml_get_pipe_attr_decl(refcyc_per_line_delivery_c_in_us);
 123 dml_get_pipe_attr_decl(refcyc_per_line_delivery_pre_l_in_us);
 124 dml_get_pipe_attr_decl(refcyc_per_line_delivery_pre_c_in_us);
 125 dml_get_pipe_attr_decl(refcyc_per_req_delivery_l_in_us);
 126 dml_get_pipe_attr_decl(refcyc_per_req_delivery_c_in_us);
 127 dml_get_pipe_attr_decl(refcyc_per_req_delivery_pre_l_in_us);
 128 dml_get_pipe_attr_decl(refcyc_per_req_delivery_pre_c_in_us);
 129 dml_get_pipe_attr_decl(refcyc_per_cursor_req_delivery_in_us);
 130 dml_get_pipe_attr_decl(refcyc_per_cursor_req_delivery_pre_in_us);
 131 dml_get_pipe_attr_decl(refcyc_per_meta_chunk_nom_l_in_us);
 132 dml_get_pipe_attr_decl(refcyc_per_meta_chunk_nom_c_in_us);
 133 dml_get_pipe_attr_decl(refcyc_per_meta_chunk_vblank_l_in_us);
 134 dml_get_pipe_attr_decl(refcyc_per_meta_chunk_vblank_c_in_us);
 135 dml_get_pipe_attr_decl(refcyc_per_meta_chunk_flip_l_in_us);
 136 dml_get_pipe_attr_decl(refcyc_per_meta_chunk_flip_c_in_us);
 137
 138 dml_get_pipe_attr_decl(vstartup);
 139 dml_get_pipe_attr_decl(vupdate_offset);
 140 dml_get_pipe_attr_decl(vupdate_width);
 141 dml_get_pipe_attr_decl(vready_offset);
 142 dml_get_pipe_attr_decl(vready_at_or_after_vsync);
 143 dml_get_pipe_attr_decl(min_dst_y_next_start);
 144 dml_get_pipe_attr_decl(vstartup_calculated);
 145 dml_get_pipe_attr_decl(subviewport_lines_needed_in_mall);
 146
 147 double get_total_immediate_flip_bytes(
 148                 struct display_mode_lib *mode_lib,
 149                 const display_e2e_pipe_params_st *pipes,
 150                 unsigned int num_pipes);
 151 double get_total_immediate_flip_bw(
 152                 struct display_mode_lib *mode_lib,
 153                 const display_e2e_pipe_params_st *pipes,
 154                 unsigned int num_pipes);
 155 double get_total_prefetch_bw(
 156                 struct display_mode_lib *mode_lib,
 157                 const display_e2e_pipe_params_st *pipes,
 158                 unsigned int num_pipes);
 159 unsigned int dml_get_voltage_level(
 160                 struct display_mode_lib *mode_lib,
 161                 const display_e2e_pipe_params_st *pipes,
 162                 unsigned int num_pipes);
 163
 164 unsigned int get_total_surface_size_in_mall_bytes(
 165                 struct display_mode_lib *mode_lib,
 166                 const display_e2e_pipe_params_st *pipes,
 167                 unsigned int num_pipes);
 168
 169 bool get_is_phantom_pipe(struct display_mode_lib *mode_lib,
 170                 const display_e2e_pipe_params_st *pipes,
 171                 unsigned int num_pipes,
 172                 unsigned int pipe_idx);
 173 void PixelClockAdjustmentForProgressiveToInterlaceUnit(struct display_mode_lib *mode_lib);
 174
 175 void Calculate256BBlockSizes(
 176                 enum source_format_class SourcePixelFormat,
 177                 enum dm_swizzle_mode SurfaceTiling,
 178                 unsigned int BytePerPixelY,
 179                 unsigned int BytePerPixelC,
 180                 unsigned int *BlockHeight256BytesY,
 181                 unsigned int *BlockHeight256BytesC,
 182                 unsigned int *BlockWidth256BytesY,
 183                 unsigned int *BlockWidth256BytesC);
 184
 185 struct dml32_CalculateSwathAndDETConfiguration {
 186         unsigned int MaximumSwathHeightY[DC__NUM_DPP__MAX];
 187         unsigned int MaximumSwathHeightC[DC__NUM_DPP__MAX];
 188         unsigned int RoundedUpMaxSwathSizeBytesY[DC__NUM_DPP__MAX];
 189         unsigned int RoundedUpMaxSwathSizeBytesC[DC__NUM_DPP__MAX];
 190         unsigned int RoundedUpSwathSizeBytesY;
 191         unsigned int RoundedUpSwathSizeBytesC;
 192         double SwathWidthdoubleDPP[DC__NUM_DPP__MAX];
 193         double SwathWidthdoubleDPPChroma[DC__NUM_DPP__MAX];
 194         unsigned int TotalActiveDPP;
 195         bool NoChromaSurfaces;
 196         unsigned int DETBufferSizeInKByteForSwathCalculation;
 197 };
 198
 199 struct dml32_CalculateVMRowAndSwath {
 200         unsigned int PTEBufferSizeInRequestsForLuma[DC__NUM_DPP__MAX];
 201         unsigned int PTEBufferSizeInRequestsForChroma[DC__NUM_DPP__MAX];
 202         unsigned int PDEAndMetaPTEBytesFrameY;
 203         unsigned int PDEAndMetaPTEBytesFrameC;
 204         unsigned int MetaRowByteY[DC__NUM_DPP__MAX];
 205         unsigned int MetaRowByteC[DC__NUM_DPP__MAX];
 206         unsigned int PixelPTEBytesPerRowY[DC__NUM_DPP__MAX];
 207         unsigned int PixelPTEBytesPerRowC[DC__NUM_DPP__MAX];
 208         unsigned int PixelPTEBytesPerRowY_one_row_per_frame[DC__NUM_DPP__MAX];
 209         unsigned int PixelPTEBytesPerRowC_one_row_per_frame[DC__NUM_DPP__MAX];
 210         unsigned int dpte_row_width_luma_ub_one_row_per_frame[DC__NUM_DPP__MAX];
 211         unsigned int dpte_row_height_luma_one_row_per_frame[DC__NUM_DPP__MAX];
 212         unsigned int dpte_row_width_chroma_ub_one_row_per_frame[DC__NUM_DPP__MAX];
 213         unsigned int dpte_row_height_chroma_one_row_per_frame[DC__NUM_DPP__MAX];
 214         bool one_row_per_frame_fits_in_buffer[DC__NUM_DPP__MAX];
 215 };
 216
 217 struct DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation {
 218         unsigned int dummy_integer_array[2][DC__NUM_DPP__MAX];
 219         double dummy_single_array[2][DC__NUM_DPP__MAX];
 220         unsigned int dummy_long_array[2][DC__NUM_DPP__MAX];
 221         double dummy_double_array[2][DC__NUM_DPP__MAX];
 222         bool dummy_boolean_array[DC__NUM_DPP__MAX];
 223         bool dummy_boolean;
 224         bool dummy_boolean2;
 225         enum output_encoder_class dummy_output_encoder_array[DC__NUM_DPP__MAX];
 226         DmlPipe SurfaceParameters[DC__NUM_DPP__MAX];
 227         bool dummy_boolean_array2[2][DC__NUM_DPP__MAX];
 228         unsigned int ReorderBytes;
 229         unsigned int VMDataOnlyReturnBW;
 230         double HostVMInefficiencyFactor;
 231         DmlPipe myPipe;
 232         SOCParametersList mmSOCParameters;
 233         double dummy_unit_vector[DC__NUM_DPP__MAX];
 234         double dummy_single[2];
 235         enum clock_change_support dummy_dramchange_support;
 236         enum dm_fclock_change_support dummy_fclkchange_support;
 237         bool dummy_USRRetrainingSupport;
 238 };
 239
 240 struct dml32_ModeSupportAndSystemConfigurationFull {
 241         unsigned int dummy_integer_array[22][DC__NUM_DPP__MAX];
 242         double dummy_double_array[2][DC__NUM_DPP__MAX];
 243         DmlPipe SurfParameters[DC__NUM_DPP__MAX];
 244         double dummy_single[5];
 245         double dummy_single2[5];
 246         SOCParametersList mSOCParameters;
 247         unsigned int MaximumSwathWidthSupportLuma;
 248         unsigned int MaximumSwathWidthSupportChroma;
 249         double DSTYAfterScaler[DC__NUM_DPP__MAX];
 250         double DSTXAfterScaler[DC__NUM_DPP__MAX];
 251         double MaxTotalVActiveRDBandwidth;
 252         bool dummy_boolean_array[2][DC__NUM_DPP__MAX];
 253         enum odm_combine_mode dummy_odm_mode[DC__NUM_DPP__MAX];
 254         DmlPipe myPipe;
 255         unsigned int dummy_integer[4];
 256         unsigned int TotalNumberOfActiveOTG;
 257         unsigned int TotalNumberOfActiveHDMIFRL;
 258         unsigned int TotalNumberOfActiveDP2p0;
 259         unsigned int TotalNumberOfActiveDP2p0Outputs;
 260         unsigned int TotalDSCUnitsRequired;
 261         unsigned int ReorderingBytes;
 262         unsigned int TotalSlots;
 263         unsigned int NumberOfDPPDSC;
 264         unsigned int NumberOfDPPNoDSC;
 265         unsigned int NextPrefetchModeState;
 266         bool MPCCombineMethodAsNeededForPStateChangeAndVoltage;
 267         bool MPCCombineMethodAsPossible;
 268         bool FullFrameMALLPStateMethod;
 269         bool SubViewportMALLPStateMethod;
 270         bool PhantomPipeMALLPStateMethod;
 271         bool NoChroma;
 272         bool TotalAvailablePipesSupportNoDSC;
 273         bool TotalAvailablePipesSupportDSC;
 274         enum odm_combine_mode ODMModeNoDSC;
 275         enum odm_combine_mode ODMModeDSC;
 276         double RequiredDISPCLKPerSurfaceNoDSC;
 277         double RequiredDISPCLKPerSurfaceDSC;
 278         double BWOfNonCombinedSurfaceOfMaximumBandwidth;
 279         double VMDataOnlyReturnBWPerState;
 280         double HostVMInefficiencyFactor;
 281         bool dummy_boolean[2];
 282 };
 283
 284 struct dummy_vars {
 285         struct DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation
 286         DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation;
 287         struct dml32_ModeSupportAndSystemConfigurationFull dml32_ModeSupportAndSystemConfigurationFull;
 288         struct dml32_CalculateSwathAndDETConfiguration dml32_CalculateSwathAndDETConfiguration;
 289         struct dml32_CalculateVMRowAndSwath dml32_CalculateVMRowAndSwath;
 290 };
 291
 292 struct vba_vars_st {
 293         ip_params_st ip;
 294         soc_bounding_box_st soc;
 295
 296         int maxMpcComb;
 297         bool UseMaximumVStartup;
 298
 299         double WritebackDISPCLK;
 300         double DPPCLKUsingSingleDPPLuma;
 301         double DPPCLKUsingSingleDPPChroma;
 302         double DISPCLKWithRamping;
 303         double DISPCLKWithoutRamping;
 304         double GlobalDPPCLK;
 305         double DISPCLKWithRampingRoundedToDFSGranularity;
 306         double DISPCLKWithoutRampingRoundedToDFSGranularity;
 307         double MaxDispclkRoundedToDFSGranularity;
 308         bool DCCEnabledAnyPlane;
 309         double ReturnBandwidthToDCN;
 310         unsigned int TotalActiveDPP;
 311         unsigned int TotalDCCActiveDPP;
 312         double UrgentRoundTripAndOutOfOrderLatency;
 313         double StutterPeriod;
 314         double FrameTimeForMinFullDETBufferingTime;
 315         double AverageReadBandwidth;
 316         double TotalRowReadBandwidth;
 317         double PartOfBurstThatFitsInROB;
 318         double StutterBurstTime;
 319         unsigned int NextPrefetchMode;
 320         double NextMaxVStartup;
 321         double VBlankTime;
 322         double SmallestVBlank;
 323         enum dm_prefetch_modes AllowForPStateChangeOrStutterInVBlankFinal; // Mode Support only
 324         double DCFCLKDeepSleepPerPlane[DC__NUM_DPP__MAX];
 325         double EffectiveDETPlusLBLinesLuma;
 326         double EffectiveDETPlusLBLinesChroma;
 327         double UrgentLatencySupportUsLuma;
 328         double UrgentLatencySupportUsChroma;
 329         unsigned int DSCFormatFactor;
 330
 331         bool DummyPStateCheck;
 332         bool DRAMClockChangeSupportsVActive;
 333         bool PrefetchModeSupported;
 334         bool PrefetchAndImmediateFlipSupported;
 335         enum self_refresh_affinity AllowDRAMSelfRefreshOrDRAMClockChangeInVblank; // Mode Support only
 336         double XFCRemoteSurfaceFlipDelay;
 337         double TInitXFill;
 338         double TslvChk;
 339         double SrcActiveDrainRate;
 340         bool ImmediateFlipSupported;
 341         enum mpc_combine_affinity WhenToDoMPCCombine; // Mode Support only
 342
 343         bool PrefetchERROR;
 344
 345         unsigned int VStartupLines;
 346         unsigned int ActiveDPPs;
 347         unsigned int LBLatencyHidingSourceLinesY;
 348         unsigned int LBLatencyHidingSourceLinesC;
 349         double ActiveDRAMClockChangeLatencyMargin[DC__NUM_DPP__MAX];
 350         double CachedActiveDRAMClockChangeLatencyMargin[DC__NUM_DPP__MAX]; // Cache in dml_get_voltage_level for debug purposes only
 351         double MinActiveDRAMClockChangeMargin;
 352         double InitFillLevel;
 353         double FinalFillMargin;
 354         double FinalFillLevel;
 355         double RemainingFillLevel;
 356         double TFinalxFill;
 357
 358         //
 359         // SOC Bounding Box Parameters
 360         //
 361         double SRExitTime;
 362         double SREnterPlusExitTime;
 363         double UrgentLatencyPixelDataOnly;
 364         double UrgentLatencyPixelMixedWithVMData;
 365         double UrgentLatencyVMDataOnly;
 366         double UrgentLatency; // max of the above three
 367         double USRRetrainingLatency;
 368         double SMNLatency;
 369         double FCLKChangeLatency;
 370         unsigned int MALLAllocatedForDCNFinal;
 371         double MaxAveragePercentOfIdealFabricBWDisplayCanUseInNormalSystemOperation;
 372         double MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperationSTROBE;
 373         double PercentOfIdealDRAMBWReceivedAfterUrgLatencySTROBE;
 374         double WritebackLatency;
 375         double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly; // Mode Support
 376         double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData; // Mode Support
 377         double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly; // Mode Support
 378         double MaxAveragePercentOfIdealSDPPortBWDisplayCanUseInNormalSystemOperation; // Mode Support
 379         double MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperation; // Mode Support
 380         double NumberOfChannels;
 381         double DRAMChannelWidth;
 382         double FabricDatapathToDCNDataReturn;
 383         double ReturnBusWidth;
 384         double Downspreading;
 385         double DISPCLKDPPCLKDSCCLKDownSpreading;
 386         double DISPCLKDPPCLKVCOSpeed;
 387         double RoundTripPingLatencyCycles;
 388         double UrgentOutOfOrderReturnPerChannel;
 389         double UrgentOutOfOrderReturnPerChannelPixelDataOnly;
 390         double UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData;
 391         double UrgentOutOfOrderReturnPerChannelVMDataOnly;
 392         unsigned int VMMPageSize;
 393         double DRAMClockChangeLatency;
 394         double XFCBusTransportTime;
 395         bool UseUrgentBurstBandwidth;
 396         double XFCXBUFLatencyTolerance;
 397
 398         //
 399         // IP Parameters
 400         //
 401         unsigned int ROBBufferSizeInKByte;
 402         unsigned int DETBufferSizeInKByte[DC__NUM_DPP__MAX];
 403         double DETBufferSizeInTime;
 404         unsigned int DPPOutputBufferPixels;
 405         unsigned int OPPOutputBufferLines;
 406         unsigned int PixelChunkSizeInKByte;
 407         double ReturnBW;
 408         bool GPUVMEnable;
 409         bool HostVMEnable;
 410         unsigned int GPUVMMaxPageTableLevels;
 411         unsigned int HostVMMaxPageTableLevels;
 412         unsigned int HostVMCachedPageTableLevels;
 413         unsigned int OverrideGPUVMPageTableLevels;
 414         unsigned int OverrideHostVMPageTableLevels;
 415         unsigned int MetaChunkSize;
 416         unsigned int MinMetaChunkSizeBytes;
 417         unsigned int WritebackChunkSize;
 418         bool ODMCapability;
 419         unsigned int NumberOfDSC;
 420         unsigned int LineBufferSize;
 421         unsigned int MaxLineBufferLines;
 422         unsigned int WritebackInterfaceLumaBufferSize;
 423         unsigned int WritebackInterfaceChromaBufferSize;
 424         unsigned int WritebackChromaLineBufferWidth;
 425         enum writeback_config WritebackConfiguration;
 426         double MaxDCHUBToPSCLThroughput;
 427         double MaxPSCLToLBThroughput;
 428         unsigned int PTEBufferSizeInRequestsLuma;
 429         unsigned int PTEBufferSizeInRequestsChroma;
 430         double DISPCLKRampingMargin;
 431         unsigned int MaxInterDCNTileRepeaters;
 432         bool XFCSupported;
 433         double XFCSlvChunkSize;
 434         double XFCFillBWOverhead;
 435         double XFCFillConstant;
 436         double XFCTSlvVupdateOffset;
 437         double XFCTSlvVupdateWidth;
 438         double XFCTSlvVreadyOffset;
 439         double DPPCLKDelaySubtotal;
 440         double DPPCLKDelaySCL;
 441         double DPPCLKDelaySCLLBOnly;
 442         double DPPCLKDelayCNVCFormater;
 443         double DPPCLKDelayCNVCCursor;
 444         double DISPCLKDelaySubtotal;
 445         bool ProgressiveToInterlaceUnitInOPP;
 446         unsigned int CompressedBufferSegmentSizeInkByteFinal;
 447         unsigned int CompbufReservedSpace64B;
 448         unsigned int CompbufReservedSpaceZs;
 449         unsigned int LineBufferSizeFinal;
 450         unsigned int MaximumPixelsPerLinePerDSCUnit;
 451         unsigned int AlphaPixelChunkSizeInKByte;
 452         double MinPixelChunkSizeBytes;
 453         unsigned int DCCMetaBufferSizeBytes;
 454         // Pipe/Plane Parameters
 455         int VoltageLevel;
 456         double FabricClock;
 457         double DRAMSpeed;
 458         double DISPCLK;
 459         double SOCCLK;
 460         double DCFCLK;
 461         unsigned int MaxTotalDETInKByte;
 462         unsigned int MinCompressedBufferSizeInKByte;
 463         unsigned int NumberOfActiveSurfaces;
 464         bool ViewportStationary[DC__NUM_DPP__MAX];
 465         unsigned int RefreshRate[DC__NUM_DPP__MAX];
 466         double       OutputBPP[DC__NUM_DPP__MAX];
 467         unsigned int GPUVMMinPageSizeKBytes[DC__NUM_DPP__MAX];
 468         bool SynchronizeTimingsFinal;
 469         bool SynchronizeDRRDisplaysForUCLKPStateChangeFinal;
 470         bool ForceOneRowForFrame[DC__NUM_DPP__MAX];
 471         unsigned int ViewportXStartY[DC__NUM_DPP__MAX];
 472         unsigned int ViewportXStartC[DC__NUM_DPP__MAX];
 473         enum dm_rotation_angle SourceRotation[DC__NUM_DPP__MAX];
 474         bool DRRDisplay[DC__NUM_DPP__MAX];
 475         bool PteBufferMode[DC__NUM_DPP__MAX];
 476         enum dm_output_type OutputType[DC__NUM_DPP__MAX];
 477         enum dm_output_rate OutputRate[DC__NUM_DPP__MAX];
 478
 479         unsigned int NumberOfActivePlanes;
 480         unsigned int NumberOfDSCSlices[DC__NUM_DPP__MAX];
 481         unsigned int ViewportWidth[DC__NUM_DPP__MAX];
 482         unsigned int ViewportHeight[DC__NUM_DPP__MAX];
 483         unsigned int ViewportYStartY[DC__NUM_DPP__MAX];
 484         unsigned int ViewportYStartC[DC__NUM_DPP__MAX];
 485         unsigned int PitchY[DC__NUM_DPP__MAX];
 486         unsigned int PitchC[DC__NUM_DPP__MAX];
 487         double HRatio[DC__NUM_DPP__MAX];
 488         double VRatio[DC__NUM_DPP__MAX];
 489         unsigned int htaps[DC__NUM_DPP__MAX];
 490         unsigned int vtaps[DC__NUM_DPP__MAX];
 491         unsigned int HTAPsChroma[DC__NUM_DPP__MAX];
 492         unsigned int VTAPsChroma[DC__NUM_DPP__MAX];
 493         unsigned int HTotal[DC__NUM_DPP__MAX];
 494         unsigned int VTotal[DC__NUM_DPP__MAX];
 495         unsigned int VTotal_Max[DC__NUM_DPP__MAX];
 496         unsigned int VTotal_Min[DC__NUM_DPP__MAX];
 497         int DPPPerPlane[DC__NUM_DPP__MAX];
 498         double PixelClock[DC__NUM_DPP__MAX];
 499         double PixelClockBackEnd[DC__NUM_DPP__MAX];
 500         bool DCCEnable[DC__NUM_DPP__MAX];
 501         bool FECEnable[DC__NUM_DPP__MAX];
 502         unsigned int DCCMetaPitchY[DC__NUM_DPP__MAX];
 503         unsigned int DCCMetaPitchC[DC__NUM_DPP__MAX];
 504         enum scan_direction_class SourceScan[DC__NUM_DPP__MAX];
 505         enum source_format_class SourcePixelFormat[DC__NUM_DPP__MAX];
 506         bool WritebackEnable[DC__NUM_DPP__MAX];
 507         unsigned int ActiveWritebacksPerPlane[DC__NUM_DPP__MAX];
 508         double WritebackDestinationWidth[DC__NUM_DPP__MAX];
 509         double WritebackDestinationHeight[DC__NUM_DPP__MAX];
 510         double WritebackSourceHeight[DC__NUM_DPP__MAX];
 511         enum source_format_class WritebackPixelFormat[DC__NUM_DPP__MAX];
 512         unsigned int WritebackLumaHTaps[DC__NUM_DPP__MAX];
 513         unsigned int WritebackLumaVTaps[DC__NUM_DPP__MAX];
 514         unsigned int WritebackChromaHTaps[DC__NUM_DPP__MAX];
 515         unsigned int WritebackChromaVTaps[DC__NUM_DPP__MAX];
 516         double WritebackHRatio[DC__NUM_DPP__MAX];
 517         double WritebackVRatio[DC__NUM_DPP__MAX];
 518         unsigned int HActive[DC__NUM_DPP__MAX];
 519         unsigned int VActive[DC__NUM_DPP__MAX];
 520         bool Interlace[DC__NUM_DPP__MAX];
 521         enum dm_swizzle_mode SurfaceTiling[DC__NUM_DPP__MAX];
 522         unsigned int ScalerRecoutWidth[DC__NUM_DPP__MAX];
 523         bool DynamicMetadataEnable[DC__NUM_DPP__MAX];
 524         int DynamicMetadataLinesBeforeActiveRequired[DC__NUM_DPP__MAX];
 525         unsigned int DynamicMetadataTransmittedBytes[DC__NUM_DPP__MAX];
 526         double DCCRate[DC__NUM_DPP__MAX];
 527         double AverageDCCCompressionRate;
 528         enum odm_combine_mode ODMCombineEnabled[DC__NUM_DPP__MAX];
 529         double OutputBpp[DC__NUM_DPP__MAX];
 530         bool DSCEnabled[DC__NUM_DPP__MAX];
 531         unsigned int DSCInputBitPerComponent[DC__NUM_DPP__MAX];
 532         enum output_format_class OutputFormat[DC__NUM_DPP__MAX];
 533         enum output_encoder_class Output[DC__NUM_DPP__MAX];
 534         bool skip_dio_check[DC__NUM_DPP__MAX];
 535         unsigned int BlendingAndTiming[DC__NUM_DPP__MAX];
 536         bool SynchronizedVBlank;
 537         unsigned int NumberOfCursors[DC__NUM_DPP__MAX];
 538         unsigned int CursorWidth[DC__NUM_DPP__MAX][DC__NUM_CURSOR__MAX];
 539         unsigned int CursorBPP[DC__NUM_DPP__MAX][DC__NUM_CURSOR__MAX];
 540         bool XFCEnabled[DC__NUM_DPP__MAX];
 541         bool ScalerEnabled[DC__NUM_DPP__MAX];
 542         unsigned int VBlankNom[DC__NUM_DPP__MAX];
 543         bool DisableUnboundRequestIfCompBufReservedSpaceNeedAdjustment;
 544
 545         // Intermediates/Informational
 546         bool ImmediateFlipSupport;
 547         unsigned int DETBufferSizeY[DC__NUM_DPP__MAX];
 548         unsigned int DETBufferSizeC[DC__NUM_DPP__MAX];
 549         unsigned int SwathHeightY[DC__NUM_DPP__MAX];
 550         unsigned int SwathHeightC[DC__NUM_DPP__MAX];
 551         unsigned int LBBitPerPixel[DC__NUM_DPP__MAX];
 552         double LastPixelOfLineExtraWatermark;
 553         double TotalDataReadBandwidth;
 554         unsigned int TotalActiveWriteback;
 555         unsigned int EffectiveLBLatencyHidingSourceLinesLuma;
 556         unsigned int EffectiveLBLatencyHidingSourceLinesChroma;
 557         double BandwidthAvailableForImmediateFlip;
 558         unsigned int PrefetchMode[DC__VOLTAGE_STATES][2];
 559         unsigned int PrefetchModePerState[DC__VOLTAGE_STATES][2];
 560         unsigned int MinPrefetchMode;
 561         unsigned int MaxPrefetchMode;
 562         bool AnyLinesForVMOrRowTooLarge;
 563         double MaxVStartup;
 564         bool IgnoreViewportPositioning;
 565         bool ErrorResult[DC__NUM_DPP__MAX];
 566         //
 567         // Calculated dml_ml->vba.Outputs
 568         //
 569         double DCFCLKDeepSleep;
 570         double UrgentWatermark;
 571         double UrgentExtraLatency;
 572         double WritebackUrgentWatermark;
 573         double StutterExitWatermark;
 574         double StutterEnterPlusExitWatermark;
 575         double DRAMClockChangeWatermark;
 576         double WritebackDRAMClockChangeWatermark;
 577         double StutterEfficiency;
 578         double StutterEfficiencyNotIncludingVBlank;
 579         double NonUrgentLatencyTolerance;
 580         double MinActiveDRAMClockChangeLatencySupported;
 581         double Z8StutterEfficiencyBestCase;
 582         unsigned int Z8NumberOfStutterBurstsPerFrameBestCase;
 583         double Z8StutterEfficiencyNotIncludingVBlankBestCase;
 584         double StutterPeriodBestCase;
 585         Watermarks      Watermark;
 586         bool DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE;
 587         unsigned int CompBufReservedSpaceKBytes;
 588         unsigned int CompBufReservedSpace64B;
 589         unsigned int CompBufReservedSpaceZs;
 590         bool CompBufReservedSpaceNeedAdjustment;
 591
 592         // These are the clocks calcuated by the library but they are not actually
 593         // used explicitly. They are fetched by tests and then possibly used. The
 594         // ultimate values to use are the ones specified by the parameters to DML
 595         double DISPCLK_calculated;
 596         double DPPCLK_calculated[DC__NUM_DPP__MAX];
 597
 598         bool ImmediateFlipSupportedSurface[DC__NUM_DPP__MAX];
 599
 600         bool Use_One_Row_For_Frame[DC__NUM_DPP__MAX];
 601         bool Use_One_Row_For_Frame_Flip[DC__NUM_DPP__MAX];
 602         unsigned int VUpdateOffsetPix[DC__NUM_DPP__MAX];
 603         double VUpdateWidthPix[DC__NUM_DPP__MAX];
 604         double VReadyOffsetPix[DC__NUM_DPP__MAX];
 605
 606         unsigned int TotImmediateFlipBytes;
 607         double TCalc;
 608
 609         display_e2e_pipe_params_st cache_pipes[DC__NUM_DPP__MAX];
 610         unsigned int cache_num_pipes;
 611         unsigned int pipe_plane[DC__NUM_DPP__MAX];
 612
 613         /* vba mode support */
 614         /*inputs*/
 615         bool SupportGFX7CompatibleTilingIn32bppAnd64bpp;
 616         double MaxHSCLRatio;
 617         double MaxVSCLRatio;
 618         unsigned int MaxNumWriteback;
 619         bool WritebackLumaAndChromaScalingSupported;
 620         bool Cursor64BppSupport;
 621         double DCFCLKPerState[DC__VOLTAGE_STATES];
 622         double DCFCLKState[DC__VOLTAGE_STATES][2];
 623         double FabricClockPerState[DC__VOLTAGE_STATES];
 624         double SOCCLKPerState[DC__VOLTAGE_STATES];
 625         double PHYCLKPerState[DC__VOLTAGE_STATES];
 626         double DTBCLKPerState[DC__VOLTAGE_STATES];
 627         double MaxDppclk[DC__VOLTAGE_STATES];
 628         double MaxDSCCLK[DC__VOLTAGE_STATES];
 629         double DRAMSpeedPerState[DC__VOLTAGE_STATES];
 630         double MaxDispclk[DC__VOLTAGE_STATES];
 631         int VoltageOverrideLevel;
 632         double PHYCLKD32PerState[DC__VOLTAGE_STATES];
 633
 634         /*outputs*/
 635         bool ScaleRatioAndTapsSupport;
 636         bool SourceFormatPixelAndScanSupport;
 637         double TotalBandwidthConsumedGBytePerSecond;
 638         bool DCCEnabledInAnyPlane;
 639         bool WritebackLatencySupport;
 640         bool WritebackModeSupport;
 641         bool Writeback10bpc420Supported;
 642         bool BandwidthSupport[DC__VOLTAGE_STATES];
 643         unsigned int TotalNumberOfActiveWriteback;
 644         double CriticalPoint;
 645         double ReturnBWToDCNPerState;
 646         bool IsErrorResult[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 647         bool prefetch_vm_bw_valid;
 648         bool prefetch_row_bw_valid;
 649         bool NumberOfOTGSupport;
 650         bool NonsupportedDSCInputBPC;
 651         bool WritebackScaleRatioAndTapsSupport;
 652         bool CursorSupport;
 653         bool PitchSupport;
 654         enum dm_validation_status ValidationStatus[DC__VOLTAGE_STATES];
 655
 656         /* Mode Support Reason */
 657         bool P2IWith420;
 658         bool DSCOnlyIfNecessaryWithBPP;
 659         bool DSC422NativeNotSupported;
 660         bool LinkRateDoesNotMatchDPVersion;
 661         bool LinkRateForMultistreamNotIndicated;
 662         bool BPPForMultistreamNotIndicated;
 663         bool MultistreamWithHDMIOreDP;
 664         bool MSOOrODMSplitWithNonDPLink;
 665         bool NotEnoughLanesForMSO;
 666         bool ViewportExceedsSurface;
 667
 668         bool ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified;
 669         bool ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe;
 670         bool InvalidCombinationOfMALLUseForPStateAndStaticScreen;
 671         bool InvalidCombinationOfMALLUseForPState;
 672
 673         enum dm_output_link_dp_rate OutputLinkDPRate[DC__NUM_DPP__MAX];
 674         double PrefetchLinesYThisState[DC__NUM_DPP__MAX];
 675         double PrefetchLinesCThisState[DC__NUM_DPP__MAX];
 676         double meta_row_bandwidth_this_state[DC__NUM_DPP__MAX];
 677         double dpte_row_bandwidth_this_state[DC__NUM_DPP__MAX];
 678         double DPTEBytesPerRowThisState[DC__NUM_DPP__MAX];
 679         double PDEAndMetaPTEBytesPerFrameThisState[DC__NUM_DPP__MAX];
 680         double MetaRowBytesThisState[DC__NUM_DPP__MAX];
 681         bool use_one_row_for_frame[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 682         bool use_one_row_for_frame_flip[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 683         bool use_one_row_for_frame_this_state[DC__NUM_DPP__MAX];
 684         bool use_one_row_for_frame_flip_this_state[DC__NUM_DPP__MAX];
 685
 686         unsigned int OutputTypeAndRatePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
 687         double RequiredDISPCLKPerSurface[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 688         unsigned int MicroTileHeightY[DC__NUM_DPP__MAX];
 689         unsigned int MicroTileHeightC[DC__NUM_DPP__MAX];
 690         unsigned int MicroTileWidthY[DC__NUM_DPP__MAX];
 691         unsigned int MicroTileWidthC[DC__NUM_DPP__MAX];
 692         bool ImmediateFlipRequiredFinal;
 693         bool DCCProgrammingAssumesScanDirectionUnknownFinal;
 694         bool EnoughWritebackUnits;
 695         bool ODMCombine2To1SupportCheckOK[DC__VOLTAGE_STATES];
 696         bool NumberOfDP2p0Support;
 697         unsigned int MaxNumDP2p0Streams;
 698         unsigned int MaxNumDP2p0Outputs;
 699         enum dm_output_type OutputTypePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
 700         enum dm_output_rate OutputRatePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
 701         double WritebackLineBufferLumaBufferSize;
 702         double WritebackLineBufferChromaBufferSize;
 703         double WritebackMinHSCLRatio;
 704         double WritebackMinVSCLRatio;
 705         double WritebackMaxHSCLRatio;
 706         double WritebackMaxVSCLRatio;
 707         double WritebackMaxHSCLTaps;
 708         double WritebackMaxVSCLTaps;
 709         unsigned int MaxNumDPP;
 710         unsigned int MaxNumOTG;
 711         double CursorBufferSize;
 712         double CursorChunkSize;
 713         unsigned int Mode;
 714         double OutputLinkDPLanes[DC__NUM_DPP__MAX];
 715         double ForcedOutputLinkBPP[DC__NUM_DPP__MAX]; // Mode Support only
 716         double ImmediateFlipBW[DC__NUM_DPP__MAX];
 717         double MaxMaxVStartup[DC__VOLTAGE_STATES][2];
 718
 719         double WritebackLumaVExtra;
 720         double WritebackChromaVExtra;
 721         double WritebackRequiredDISPCLK;
 722         double MaximumSwathWidthSupport;
 723         double MaximumSwathWidthInDETBuffer;
 724         double MaximumSwathWidthInLineBuffer;
 725         double MaxDispclkRoundedDownToDFSGranularity;
 726         double MaxDppclkRoundedDownToDFSGranularity;
 727         double PlaneRequiredDISPCLKWithoutODMCombine;
 728         double PlaneRequiredDISPCLKWithODMCombine;
 729         double PlaneRequiredDISPCLK;
 730         double TotalNumberOfActiveOTG;
 731         double FECOverhead;
 732         double EffectiveFECOverhead;
 733         double Outbpp;
 734         unsigned int OutbppDSC;
 735         double TotalDSCUnitsRequired;
 736         double bpp;
 737         unsigned int slices;
 738         double SwathWidthGranularityY;
 739         double RoundedUpMaxSwathSizeBytesY;
 740         double SwathWidthGranularityC;
 741         double RoundedUpMaxSwathSizeBytesC;
 742         double EffectiveDETLBLinesLuma;
 743         double EffectiveDETLBLinesChroma;
 744         double ProjectedDCFCLKDeepSleep[DC__VOLTAGE_STATES][2];
 745         double PDEAndMetaPTEBytesPerFrameY;
 746         double PDEAndMetaPTEBytesPerFrameC;
 747         unsigned int MetaRowBytesY;
 748         unsigned int MetaRowBytesC;
 749         unsigned int DPTEBytesPerRowC;
 750         unsigned int DPTEBytesPerRowY;
 751         double ExtraLatency;
 752         double TimeCalc;
 753         double TWait;
 754         double MaximumReadBandwidthWithPrefetch;
 755         double MaximumReadBandwidthWithoutPrefetch;
 756         double total_dcn_read_bw_with_flip;
 757         double total_dcn_read_bw_with_flip_no_urgent_burst;
 758         double FractionOfUrgentBandwidth;
 759         double FractionOfUrgentBandwidthImmediateFlip; // Mode Support debugging output
 760
 761         /* ms locals */
 762         double IdealSDPPortBandwidthPerState[DC__VOLTAGE_STATES][2];
 763         unsigned int NoOfDPP[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 764         int NoOfDPPThisState[DC__NUM_DPP__MAX];
 765         enum odm_combine_mode ODMCombineEnablePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
 766         double SwathWidthYThisState[DC__NUM_DPP__MAX];
 767         unsigned int SwathHeightCPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 768         unsigned int SwathHeightYThisState[DC__NUM_DPP__MAX];
 769         unsigned int SwathHeightCThisState[DC__NUM_DPP__MAX];
 770         double VRatioPreY[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 771         double VRatioPreC[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 772         double RequiredPrefetchPixelDataBWLuma[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 773         double RequiredPrefetchPixelDataBWChroma[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 774         double RequiredDPPCLK[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 775         double RequiredDPPCLKThisState[DC__NUM_DPP__MAX];
 776         bool PTEBufferSizeNotExceededY[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 777         bool PTEBufferSizeNotExceededC[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 778         bool BandwidthWithoutPrefetchSupported[DC__VOLTAGE_STATES][2];
 779         bool PrefetchSupported[DC__VOLTAGE_STATES][2];
 780         bool VRatioInPrefetchSupported[DC__VOLTAGE_STATES][2];
 781         double RequiredDISPCLK[DC__VOLTAGE_STATES][2];
 782         bool DISPCLK_DPPCLK_Support[DC__VOLTAGE_STATES][2];
 783         bool TotalAvailablePipesSupport[DC__VOLTAGE_STATES][2];
 784         unsigned int TotalNumberOfActiveDPP[DC__VOLTAGE_STATES][2];
 785         unsigned int TotalNumberOfDCCActiveDPP[DC__VOLTAGE_STATES][2];
 786         bool ModeSupport[DC__VOLTAGE_STATES][2];
 787         double ReturnBWPerState[DC__VOLTAGE_STATES][2];
 788         bool DIOSupport[DC__VOLTAGE_STATES];
 789         bool NotEnoughDSCUnits[DC__VOLTAGE_STATES];
 790         bool DSCCLKRequiredMoreThanSupported[DC__VOLTAGE_STATES];
 791         bool DTBCLKRequiredMoreThanSupported[DC__VOLTAGE_STATES];
 792         double UrgentRoundTripAndOutOfOrderLatencyPerState[DC__VOLTAGE_STATES];
 793         bool ROBSupport[DC__VOLTAGE_STATES][2];
 794         //based on rev 99: Dim DCCMetaBufferSizeSupport(NumberOfStates, 1) As Boolean
 795         bool DCCMetaBufferSizeSupport[DC__VOLTAGE_STATES][2];
 796         bool PTEBufferSizeNotExceeded[DC__VOLTAGE_STATES][2];
 797         bool TotalVerticalActiveBandwidthSupport[DC__VOLTAGE_STATES][2];
 798         double MaxTotalVerticalActiveAvailableBandwidth[DC__VOLTAGE_STATES][2];
 799         double PrefetchBW[DC__NUM_DPP__MAX];
 800         double PDEAndMetaPTEBytesPerFrame[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 801         double MetaRowBytes[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 802         double DPTEBytesPerRow[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 803         double PrefetchLinesY[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 804         double PrefetchLinesC[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 805         unsigned int MaxNumSwY[DC__NUM_DPP__MAX];
 806         unsigned int MaxNumSwC[DC__NUM_DPP__MAX];
 807         double PrefillY[DC__NUM_DPP__MAX];
 808         double PrefillC[DC__NUM_DPP__MAX];
 809         double LineTimesForPrefetch[DC__NUM_DPP__MAX];
 810         double LinesForMetaPTE[DC__NUM_DPP__MAX];
 811         double LinesForMetaAndDPTERow[DC__NUM_DPP__MAX];
 812         double MinDPPCLKUsingSingleDPP[DC__NUM_DPP__MAX];
 813         double SwathWidthYSingleDPP[DC__NUM_DPP__MAX];
 814         double BytePerPixelInDETY[DC__NUM_DPP__MAX];
 815         double BytePerPixelInDETC[DC__NUM_DPP__MAX];
 816         bool RequiresDSC[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
 817         unsigned int NumberOfDSCSlice[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
 818         double RequiresFEC[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
 819         double OutputBppPerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
 820         double DSCDelayPerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
 821         bool ViewportSizeSupport[DC__VOLTAGE_STATES][2];
 822         unsigned int Read256BlockHeightY[DC__NUM_DPP__MAX];
 823         unsigned int Read256BlockWidthY[DC__NUM_DPP__MAX];
 824         unsigned int Read256BlockHeightC[DC__NUM_DPP__MAX];
 825         unsigned int Read256BlockWidthC[DC__NUM_DPP__MAX];
 826         double MaxSwathHeightY[DC__NUM_DPP__MAX];
 827         double MaxSwathHeightC[DC__NUM_DPP__MAX];
 828         double MinSwathHeightY[DC__NUM_DPP__MAX];
 829         double MinSwathHeightC[DC__NUM_DPP__MAX];
 830         double ReadBandwidthLuma[DC__NUM_DPP__MAX];
 831         double ReadBandwidthChroma[DC__NUM_DPP__MAX];
 832         double ReadBandwidth[DC__NUM_DPP__MAX];
 833         double WriteBandwidth[DC__NUM_DPP__MAX];
 834         double PSCL_FACTOR[DC__NUM_DPP__MAX];
 835         double PSCL_FACTOR_CHROMA[DC__NUM_DPP__MAX];
 836         double MaximumVStartup[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 837         unsigned int MacroTileWidthY[DC__NUM_DPP__MAX];
 838         unsigned int MacroTileWidthC[DC__NUM_DPP__MAX];
 839         double AlignedDCCMetaPitch[DC__NUM_DPP__MAX];
 840         double AlignedYPitch[DC__NUM_DPP__MAX];
 841         double AlignedCPitch[DC__NUM_DPP__MAX];
 842         double MaximumSwathWidth[DC__NUM_DPP__MAX];
 843         double cursor_bw[DC__NUM_DPP__MAX];
 844         double cursor_bw_pre[DC__NUM_DPP__MAX];
 845         double Tno_bw[DC__NUM_DPP__MAX];
 846         double prefetch_vmrow_bw[DC__NUM_DPP__MAX];
 847         double DestinationLinesToRequestVMInImmediateFlip[DC__NUM_DPP__MAX];
 848         double DestinationLinesToRequestRowInImmediateFlip[DC__NUM_DPP__MAX];
 849         double final_flip_bw[DC__NUM_DPP__MAX];
 850         bool ImmediateFlipSupportedForState[DC__VOLTAGE_STATES][2];
 851         double WritebackDelay[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
 852         unsigned int vm_group_bytes[DC__NUM_DPP__MAX];
 853         unsigned int dpte_group_bytes[DC__NUM_DPP__MAX];
 854         unsigned int dpte_row_height[DC__NUM_DPP__MAX];
 855         unsigned int meta_req_height[DC__NUM_DPP__MAX];
 856         unsigned int meta_req_width[DC__NUM_DPP__MAX];
 857         unsigned int meta_row_height[DC__NUM_DPP__MAX];
 858         unsigned int meta_row_width[DC__NUM_DPP__MAX];
 859         unsigned int dpte_row_height_chroma[DC__NUM_DPP__MAX];
 860         unsigned int meta_req_height_chroma[DC__NUM_DPP__MAX];
 861         unsigned int meta_req_width_chroma[DC__NUM_DPP__MAX];
 862         unsigned int meta_row_height_chroma[DC__NUM_DPP__MAX];
 863         unsigned int meta_row_width_chroma[DC__NUM_DPP__MAX];
 864         bool ImmediateFlipSupportedForPipe[DC__NUM_DPP__MAX];
 865         double meta_row_bw[DC__NUM_DPP__MAX];
 866         double dpte_row_bw[DC__NUM_DPP__MAX];
 867         double DisplayPipeLineDeliveryTimeLuma[DC__NUM_DPP__MAX];                     // WM
 868         double DisplayPipeLineDeliveryTimeChroma[DC__NUM_DPP__MAX];                     // WM
 869         double DisplayPipeRequestDeliveryTimeLuma[DC__NUM_DPP__MAX];
 870         double DisplayPipeRequestDeliveryTimeChroma[DC__NUM_DPP__MAX];
 871         enum clock_change_support DRAMClockChangeSupport[DC__VOLTAGE_STATES][2];
 872         double UrgentBurstFactorCursor[DC__NUM_DPP__MAX];
 873         double UrgentBurstFactorCursorPre[DC__NUM_DPP__MAX];
 874         double UrgentBurstFactorLuma[DC__NUM_DPP__MAX];
 875         double UrgentBurstFactorLumaPre[DC__NUM_DPP__MAX];
 876         double UrgentBurstFactorChroma[DC__NUM_DPP__MAX];
 877         double UrgentBurstFactorChromaPre[DC__NUM_DPP__MAX];
 878
 879
 880         bool           MPCCombine[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 881         double         SwathWidthCSingleDPP[DC__NUM_DPP__MAX];
 882         double         MaximumSwathWidthInLineBufferLuma;
 883         double         MaximumSwathWidthInLineBufferChroma;
 884         double         MaximumSwathWidthLuma[DC__NUM_DPP__MAX];
 885         double         MaximumSwathWidthChroma[DC__NUM_DPP__MAX];
 886         enum odm_combine_mode odm_combine_dummy[DC__NUM_DPP__MAX];
 887         double         dummy1[DC__NUM_DPP__MAX];
 888         double         dummy2[DC__NUM_DPP__MAX];
 889         unsigned int   dummy3[DC__NUM_DPP__MAX];
 890         unsigned int   dummy4[DC__NUM_DPP__MAX];
 891         double         dummy5;
 892         double         dummy6;
 893         double         dummy7[DC__NUM_DPP__MAX];
 894         double         dummy8[DC__NUM_DPP__MAX];
 895         double         dummy13[DC__NUM_DPP__MAX];
 896         double         dummy_double_array[2][DC__NUM_DPP__MAX];
 897         unsigned int        dummyinteger3[DC__NUM_DPP__MAX];
 898         unsigned int        dummyinteger4[DC__NUM_DPP__MAX];
 899         unsigned int        dummyinteger5;
 900         unsigned int        dummyinteger6;
 901         unsigned int        dummyinteger7;
 902         unsigned int        dummyinteger8;
 903         unsigned int        dummyinteger9;
 904         unsigned int        dummyinteger10;
 905         unsigned int        dummyinteger11;
 906         unsigned int        dummy_integer_array[8][DC__NUM_DPP__MAX];
 907
 908         bool           dummysinglestring;
 909         bool           SingleDPPViewportSizeSupportPerPlane[DC__NUM_DPP__MAX];
 910         double         PlaneRequiredDISPCLKWithODMCombine2To1;
 911         double         PlaneRequiredDISPCLKWithODMCombine4To1;
 912         unsigned int   TotalNumberOfSingleDPPPlanes[DC__VOLTAGE_STATES][2];
 913         bool           LinkDSCEnable;
 914         bool           ODMCombine4To1SupportCheckOK[DC__VOLTAGE_STATES];
 915         enum odm_combine_mode ODMCombineEnableThisState[DC__NUM_DPP__MAX];
 916         double   SwathWidthCThisState[DC__NUM_DPP__MAX];
 917         bool           ViewportSizeSupportPerPlane[DC__NUM_DPP__MAX];
 918         double         AlignedDCCMetaPitchY[DC__NUM_DPP__MAX];
 919         double         AlignedDCCMetaPitchC[DC__NUM_DPP__MAX];
 920
 921         unsigned int NotEnoughUrgentLatencyHiding[DC__VOLTAGE_STATES][2];
 922         unsigned int NotEnoughUrgentLatencyHidingPre;
 923         int PTEBufferSizeInRequestsForLuma;
 924         int PTEBufferSizeInRequestsForChroma;
 925
 926         // Missing from VBA
 927         int dpte_group_bytes_chroma;
 928         unsigned int vm_group_bytes_chroma;
 929         double dst_x_after_scaler;
 930         double dst_y_after_scaler;
 931         unsigned int VStartupRequiredWhenNotEnoughTimeForDynamicMetadata;
 932
 933         /* perf locals*/
 934         double PrefetchBandwidth[DC__NUM_DPP__MAX];
 935         double VInitPreFillY[DC__NUM_DPP__MAX];
 936         double VInitPreFillC[DC__NUM_DPP__MAX];
 937         unsigned int MaxNumSwathY[DC__NUM_DPP__MAX];
 938         unsigned int MaxNumSwathC[DC__NUM_DPP__MAX];
 939         unsigned int VStartup[DC__NUM_DPP__MAX];
 940         double DSTYAfterScaler[DC__NUM_DPP__MAX];
 941         double DSTXAfterScaler[DC__NUM_DPP__MAX];
 942         bool AllowDRAMClockChangeDuringVBlank[DC__NUM_DPP__MAX];
 943         bool AllowDRAMSelfRefreshDuringVBlank[DC__NUM_DPP__MAX];
 944         double VRatioPrefetchY[DC__NUM_DPP__MAX];
 945         double VRatioPrefetchC[DC__NUM_DPP__MAX];
 946         double DestinationLinesForPrefetch[DC__NUM_DPP__MAX];
 947         double DestinationLinesToRequestVMInVBlank[DC__NUM_DPP__MAX];
 948         double DestinationLinesToRequestRowInVBlank[DC__NUM_DPP__MAX];
 949         double MinTTUVBlank[DC__NUM_DPP__MAX];
 950         double BytePerPixelDETY[DC__NUM_DPP__MAX];
 951         double BytePerPixelDETC[DC__NUM_DPP__MAX];
 952         double SwathWidthY[DC__NUM_DPP__MAX];
 953         double SwathWidthSingleDPPY[DC__NUM_DPP__MAX];
 954         double CursorRequestDeliveryTime[DC__NUM_DPP__MAX];
 955         double CursorRequestDeliveryTimePrefetch[DC__NUM_DPP__MAX];
 956         double ReadBandwidthPlaneLuma[DC__NUM_DPP__MAX];
 957         double ReadBandwidthPlaneChroma[DC__NUM_DPP__MAX];
 958         double DisplayPipeLineDeliveryTimeLumaPrefetch[DC__NUM_DPP__MAX];
 959         double DisplayPipeLineDeliveryTimeChromaPrefetch[DC__NUM_DPP__MAX];
 960         double DisplayPipeRequestDeliveryTimeLumaPrefetch[DC__NUM_DPP__MAX];
 961         double DisplayPipeRequestDeliveryTimeChromaPrefetch[DC__NUM_DPP__MAX];
 962         double PixelPTEBytesPerRow[DC__NUM_DPP__MAX];
 963         double PDEAndMetaPTEBytesFrame[DC__NUM_DPP__MAX];
 964         double MetaRowByte[DC__NUM_DPP__MAX];
 965         double PrefetchSourceLinesY[DC__NUM_DPP__MAX];
 966         double RequiredPrefetchPixDataBWLuma[DC__NUM_DPP__MAX];
 967         double RequiredPrefetchPixDataBWChroma[DC__NUM_DPP__MAX];
 968         double PrefetchSourceLinesC[DC__NUM_DPP__MAX];
 969         double PSCL_THROUGHPUT_LUMA[DC__NUM_DPP__MAX];
 970         double PSCL_THROUGHPUT_CHROMA[DC__NUM_DPP__MAX];
 971         double DSCCLK_calculated[DC__NUM_DPP__MAX];
 972         unsigned int DSCDelay[DC__NUM_DPP__MAX];
 973         unsigned int MaxVStartupLines[DC__NUM_DPP__MAX];
 974         double DPPCLKUsingSingleDPP[DC__NUM_DPP__MAX];
 975         double DPPCLK[DC__NUM_DPP__MAX];
 976         unsigned int DCCYMaxUncompressedBlock[DC__NUM_DPP__MAX];
 977         unsigned int DCCYMaxCompressedBlock[DC__NUM_DPP__MAX];
 978         unsigned int DCCYIndependent64ByteBlock[DC__NUM_DPP__MAX];
 979         double MaximumDCCCompressionYSurface[DC__NUM_DPP__MAX];
 980         unsigned int BlockHeight256BytesY[DC__NUM_DPP__MAX];
 981         unsigned int BlockHeight256BytesC[DC__NUM_DPP__MAX];
 982         unsigned int BlockWidth256BytesY[DC__NUM_DPP__MAX];
 983         unsigned int BlockWidth256BytesC[DC__NUM_DPP__MAX];
 984         double XFCSlaveVUpdateOffset[DC__NUM_DPP__MAX];
 985         double XFCSlaveVupdateWidth[DC__NUM_DPP__MAX];
 986         double XFCSlaveVReadyOffset[DC__NUM_DPP__MAX];
 987         double XFCTransferDelay[DC__NUM_DPP__MAX];
 988         double XFCPrechargeDelay[DC__NUM_DPP__MAX];
 989         double XFCRemoteSurfaceFlipLatency[DC__NUM_DPP__MAX];
 990         double XFCPrefetchMargin[DC__NUM_DPP__MAX];
 991         unsigned int dpte_row_width_luma_ub[DC__NUM_DPP__MAX];
 992         unsigned int dpte_row_width_chroma_ub[DC__NUM_DPP__MAX];
 993         double FullDETBufferingTimeY[DC__NUM_DPP__MAX];                     // WM
 994         double FullDETBufferingTimeC[DC__NUM_DPP__MAX];                     // WM
 995         double DST_Y_PER_PTE_ROW_NOM_L[DC__NUM_DPP__MAX];
 996         double DST_Y_PER_PTE_ROW_NOM_C[DC__NUM_DPP__MAX];
 997         double DST_Y_PER_META_ROW_NOM_L[DC__NUM_DPP__MAX];
 998         double TimePerMetaChunkNominal[DC__NUM_DPP__MAX];
 999         double TimePerMetaChunkVBlank[DC__NUM_DPP__MAX];
1000         double TimePerMetaChunkFlip[DC__NUM_DPP__MAX];
1001         unsigned int swath_width_luma_ub[DC__NUM_DPP__MAX];
1002         unsigned int swath_width_chroma_ub[DC__NUM_DPP__MAX];
1003         unsigned int PixelPTEReqWidthY[DC__NUM_DPP__MAX];
1004         unsigned int PixelPTEReqHeightY[DC__NUM_DPP__MAX];
1005         unsigned int PTERequestSizeY[DC__NUM_DPP__MAX];
1006         unsigned int PixelPTEReqWidthC[DC__NUM_DPP__MAX];
1007         unsigned int PixelPTEReqHeightC[DC__NUM_DPP__MAX];
1008         unsigned int PTERequestSizeC[DC__NUM_DPP__MAX];
1009         double time_per_pte_group_nom_luma[DC__NUM_DPP__MAX];
1010         double time_per_pte_group_nom_chroma[DC__NUM_DPP__MAX];
1011         double time_per_pte_group_vblank_luma[DC__NUM_DPP__MAX];
1012         double time_per_pte_group_vblank_chroma[DC__NUM_DPP__MAX];
1013         double time_per_pte_group_flip_luma[DC__NUM_DPP__MAX];
1014         double time_per_pte_group_flip_chroma[DC__NUM_DPP__MAX];
1015         double TimePerVMGroupVBlank[DC__NUM_DPP__MAX];
1016         double TimePerVMGroupFlip[DC__NUM_DPP__MAX];
1017         double TimePerVMRequestVBlank[DC__NUM_DPP__MAX];
1018         double TimePerVMRequestFlip[DC__NUM_DPP__MAX];
1019         unsigned int dpde0_bytes_per_frame_ub_l[DC__NUM_DPP__MAX];
1020         unsigned int meta_pte_bytes_per_frame_ub_l[DC__NUM_DPP__MAX];
1021         unsigned int dpde0_bytes_per_frame_ub_c[DC__NUM_DPP__MAX];
1022         unsigned int meta_pte_bytes_per_frame_ub_c[DC__NUM_DPP__MAX];
1023         double LinesToFinishSwathTransferStutterCriticalPlane;
1024         unsigned int BytePerPixelYCriticalPlane;
1025         double SwathWidthYCriticalPlane;
1026         double LinesInDETY[DC__NUM_DPP__MAX];
1027         double LinesInDETYRoundedDownToSwath[DC__NUM_DPP__MAX];
1028
1029         double SwathWidthSingleDPPC[DC__NUM_DPP__MAX];
1030         double SwathWidthC[DC__NUM_DPP__MAX];
1031         unsigned int BytePerPixelY[DC__NUM_DPP__MAX];
1032         unsigned int BytePerPixelC[DC__NUM_DPP__MAX];
1033         unsigned int dummyinteger1;
1034         unsigned int dummyinteger2;
1035         double FinalDRAMClockChangeLatency;
1036         double Tdmdl_vm[DC__NUM_DPP__MAX];
1037         double Tdmdl[DC__NUM_DPP__MAX];
1038         double TSetup[DC__NUM_DPP__MAX];
1039         unsigned int ThisVStartup;
1040         bool WritebackAllowDRAMClockChangeEndPosition[DC__NUM_DPP__MAX];
1041         double DST_Y_PER_META_ROW_NOM_C[DC__NUM_DPP__MAX];
1042         double TimePerChromaMetaChunkNominal[DC__NUM_DPP__MAX];
1043         double TimePerChromaMetaChunkVBlank[DC__NUM_DPP__MAX];
1044         double TimePerChromaMetaChunkFlip[DC__NUM_DPP__MAX];
1045         unsigned int DCCCMaxUncompressedBlock[DC__NUM_DPP__MAX];
1046         unsigned int DCCCMaxCompressedBlock[DC__NUM_DPP__MAX];
1047         double VStartupMargin;
1048         bool NotEnoughTimeForDynamicMetadata[DC__NUM_DPP__MAX];
1049
1050         /* Missing from VBA */
1051         unsigned int MaximumMaxVStartupLines;
1052         double FabricAndDRAMBandwidth;
1053         double LinesInDETLuma;
1054         double LinesInDETChroma;
1055         unsigned int ImmediateFlipBytes[DC__NUM_DPP__MAX];
1056         unsigned int LinesInDETC[DC__NUM_DPP__MAX];
1057         unsigned int LinesInDETCRoundedDownToSwath[DC__NUM_DPP__MAX];
1058         double UrgentLatencySupportUsPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1059         double UrgentLatencySupportUs[DC__NUM_DPP__MAX];
1060         double FabricAndDRAMBandwidthPerState[DC__VOLTAGE_STATES];
1061         bool UrgentLatencySupport[DC__VOLTAGE_STATES][2];
1062         unsigned int SwathWidthYPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1063         unsigned int SwathHeightYPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1064         double qual_row_bw[DC__NUM_DPP__MAX];
1065         double prefetch_row_bw[DC__NUM_DPP__MAX];
1066         double prefetch_vm_bw[DC__NUM_DPP__MAX];
1067
1068         double PTEGroupSize;
1069         unsigned int PDEProcessingBufIn64KBReqs;
1070
1071         double MaxTotalVActiveRDBandwidth;
1072         bool DoUrgentLatencyAdjustment;
1073         double UrgentLatencyAdjustmentFabricClockComponent;
1074         double UrgentLatencyAdjustmentFabricClockReference;
1075         double MinUrgentLatencySupportUs;
1076         double MinFullDETBufferingTime;
1077         double AverageReadBandwidthGBytePerSecond;
1078         bool   FirstMainPlane;
1079
1080         unsigned int ViewportWidthChroma[DC__NUM_DPP__MAX];
1081         unsigned int ViewportHeightChroma[DC__NUM_DPP__MAX];
1082         double HRatioChroma[DC__NUM_DPP__MAX];
1083         double VRatioChroma[DC__NUM_DPP__MAX];
1084         int WritebackSourceWidth[DC__NUM_DPP__MAX];
1085
1086         bool ModeIsSupported;
1087         bool ODMCombine4To1Supported;
1088
1089         unsigned int SurfaceWidthY[DC__NUM_DPP__MAX];
1090         unsigned int SurfaceWidthC[DC__NUM_DPP__MAX];
1091         unsigned int SurfaceHeightY[DC__NUM_DPP__MAX];
1092         unsigned int SurfaceHeightC[DC__NUM_DPP__MAX];
1093         unsigned int WritebackHTaps[DC__NUM_DPP__MAX];
1094         unsigned int WritebackVTaps[DC__NUM_DPP__MAX];
1095         bool DSCEnable[DC__NUM_DPP__MAX];
1096
1097         double DRAMClockChangeLatencyOverride;
1098
1099         double GPUVMMinPageSize;
1100         double HostVMMinPageSize;
1101
1102         bool   MPCCombineEnable[DC__NUM_DPP__MAX];
1103         unsigned int HostVMMaxNonCachedPageTableLevels;
1104         bool   DynamicMetadataVMEnabled;
1105         double       WritebackInterfaceBufferSize;
1106         double       WritebackLineBufferSize;
1107
1108         double DCCRateLuma[DC__NUM_DPP__MAX];
1109         double DCCRateChroma[DC__NUM_DPP__MAX];
1110
1111         double PHYCLKD18PerState[DC__VOLTAGE_STATES];
1112
1113         bool WritebackSupportInterleaveAndUsingWholeBufferForASingleStream;
1114         bool NumberOfHDMIFRLSupport;
1115         unsigned int MaxNumHDMIFRLOutputs;
1116         int    AudioSampleRate[DC__NUM_DPP__MAX];
1117         int    AudioSampleLayout[DC__NUM_DPP__MAX];
1118
1119         int PercentMarginOverMinimumRequiredDCFCLK;
1120         bool DynamicMetadataSupported[DC__VOLTAGE_STATES][2];
1121         enum immediate_flip_requirement ImmediateFlipRequirement[DC__NUM_DPP__MAX];
1122         unsigned int DETBufferSizeYThisState[DC__NUM_DPP__MAX];
1123         unsigned int DETBufferSizeCThisState[DC__NUM_DPP__MAX];
1124         bool NoUrgentLatencyHiding[DC__NUM_DPP__MAX];
1125         bool NoUrgentLatencyHidingPre[DC__NUM_DPP__MAX];
1126         int swath_width_luma_ub_this_state[DC__NUM_DPP__MAX];
1127         int swath_width_chroma_ub_this_state[DC__NUM_DPP__MAX];
1128         double UrgLatency[DC__VOLTAGE_STATES];
1129         double VActiveCursorBandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1130         double VActivePixelBandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1131         bool NoTimeForPrefetch[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1132         bool NoTimeForDynamicMetadata[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1133         double dpte_row_bandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1134         double meta_row_bandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1135         double DETBufferSizeYAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1136         double DETBufferSizeCAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1137         unsigned int swath_width_luma_ub_all_states[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1138         unsigned int swath_width_chroma_ub_all_states[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1139         bool NotUrgentLatencyHiding[DC__VOLTAGE_STATES][2];
1140         unsigned int SwathHeightYAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1141         unsigned int SwathHeightCAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1142         unsigned int SwathWidthYAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1143         unsigned int SwathWidthCAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1144         double TotalDPTERowBandwidth[DC__VOLTAGE_STATES][2];
1145         double TotalMetaRowBandwidth[DC__VOLTAGE_STATES][2];
1146         double TotalVActiveCursorBandwidth[DC__VOLTAGE_STATES][2];
1147         double TotalVActivePixelBandwidth[DC__VOLTAGE_STATES][2];
1148         double WritebackDelayTime[DC__NUM_DPP__MAX];
1149         unsigned int DCCYIndependentBlock[DC__NUM_DPP__MAX];
1150         unsigned int DCCCIndependentBlock[DC__NUM_DPP__MAX];
1151         unsigned int dummyinteger17;
1152         unsigned int dummyinteger18;
1153         unsigned int dummyinteger19;
1154         unsigned int dummyinteger20;
1155         unsigned int dummyinteger21;
1156         unsigned int dummyinteger22;
1157         unsigned int dummyinteger23;
1158         unsigned int dummyinteger24;
1159         unsigned int dummyinteger25;
1160         unsigned int dummyinteger26;
1161         unsigned int dummyinteger27;
1162         unsigned int dummyinteger28;
1163         unsigned int dummyinteger29;
1164         bool dummystring[DC__NUM_DPP__MAX];
1165         double BPP;
1166         enum odm_combine_policy ODMCombinePolicy;
1167         bool UseMinimumRequiredDCFCLK;
1168         bool ClampMinDCFCLK;
1169         bool AllowDramClockChangeOneDisplayVactive;
1170
1171         double MaxAveragePercentOfIdealFabricAndSDPPortBWDisplayCanUseInNormalSystemOperation;
1172         double PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency;
1173         double PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelMixedWithVMData;
1174         double PercentOfIdealDRAMBWReceivedAfterUrgLatencyVMDataOnly;
1175         double PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelDataOnly;
1176         double SRExitZ8Time;
1177         double SREnterPlusExitZ8Time;
1178         double Z8StutterExitWatermark;
1179         double Z8StutterEnterPlusExitWatermark;
1180         double Z8StutterEfficiencyNotIncludingVBlank;
1181         double Z8StutterEfficiency;
1182         double DCCFractionOfZeroSizeRequestsLuma[DC__NUM_DPP__MAX];
1183         double DCCFractionOfZeroSizeRequestsChroma[DC__NUM_DPP__MAX];
1184         double UrgBurstFactorCursor[DC__NUM_DPP__MAX];
1185         double UrgBurstFactorLuma[DC__NUM_DPP__MAX];
1186         double UrgBurstFactorChroma[DC__NUM_DPP__MAX];
1187         double UrgBurstFactorCursorPre[DC__NUM_DPP__MAX];
1188         double UrgBurstFactorLumaPre[DC__NUM_DPP__MAX];
1189         double UrgBurstFactorChromaPre[DC__NUM_DPP__MAX];
1190         bool NotUrgentLatencyHidingPre[DC__NUM_DPP__MAX];
1191         bool LinkCapacitySupport[DC__NUM_DPP__MAX];
1192         bool VREADY_AT_OR_AFTER_VSYNC[DC__NUM_DPP__MAX];
1193         unsigned int MIN_DST_Y_NEXT_START[DC__NUM_DPP__MAX];
1194         unsigned int VFrontPorch[DC__NUM_DPP__MAX];
1195         int ConfigReturnBufferSizeInKByte;
1196         enum unbounded_requesting_policy UseUnboundedRequesting;
1197         int CompressedBufferSegmentSizeInkByte;
1198         int CompressedBufferSizeInkByte;
1199         int MetaFIFOSizeInKEntries;
1200         int ZeroSizeBufferEntries;
1201         int COMPBUF_RESERVED_SPACE_64B;
1202         int COMPBUF_RESERVED_SPACE_ZS;
1203         bool UnboundedRequestEnabled;
1204         bool DSC422NativeSupport;
1205         bool NoEnoughUrgentLatencyHiding;
1206         bool NoEnoughUrgentLatencyHidingPre;
1207         int NumberOfStutterBurstsPerFrame;
1208         int Z8NumberOfStutterBurstsPerFrame;
1209         unsigned int MaximumDSCBitsPerComponent;
1210         unsigned int NotEnoughUrgentLatencyHidingA[DC__VOLTAGE_STATES][2];
1211         double ReadBandwidthSurfaceLuma[DC__NUM_DPP__MAX];
1212         double ReadBandwidthSurfaceChroma[DC__NUM_DPP__MAX];
1213         double SurfaceRequiredDISPCLKWithoutODMCombine;
1214         double SurfaceRequiredDISPCLK;
1215         double MinActiveFCLKChangeLatencySupported;
1216         int MinVoltageLevel;
1217         int MaxVoltageLevel;
1218         unsigned int TotalNumberOfSingleDPPSurfaces[DC__VOLTAGE_STATES][2];
1219         unsigned int CompressedBufferSizeInkByteAllStates[DC__VOLTAGE_STATES][2];
1220         unsigned int DETBufferSizeInKByteAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1221         unsigned int DETBufferSizeInKByteThisState[DC__NUM_DPP__MAX];
1222         unsigned int SurfaceSizeInMALL[DC__NUM_DPP__MAX];
1223         bool ExceededMALLSize;
1224         bool PTE_BUFFER_MODE[DC__NUM_DPP__MAX];
1225         unsigned int BIGK_FRAGMENT_SIZE[DC__NUM_DPP__MAX];
1226         unsigned int CompressedBufferSizeInkByteThisState;
1227         enum dm_fclock_change_support FCLKChangeSupport[DC__VOLTAGE_STATES][2];
1228         bool USRRetrainingSupport[DC__VOLTAGE_STATES][2];
1229         enum dm_use_mall_for_pstate_change_mode UsesMALLForPStateChange[DC__NUM_DPP__MAX];
1230         bool UnboundedRequestEnabledAllStates[DC__VOLTAGE_STATES][2];
1231         bool SingleDPPViewportSizeSupportPerSurface[DC__NUM_DPP__MAX];
1232         enum dm_use_mall_for_static_screen_mode UseMALLForStaticScreen[DC__NUM_DPP__MAX];
1233         bool UnboundedRequestEnabledThisState;
1234         bool DRAMClockChangeRequirementFinal;
1235         bool FCLKChangeRequirementFinal;
1236         bool USRRetrainingRequiredFinal;
1237         unsigned int DETSizeOverride[DC__NUM_DPP__MAX];
1238         unsigned int nomDETInKByte;
1239         enum mpc_combine_affinity  MPCCombineUse[DC__NUM_DPP__MAX];
1240         bool MPCCombineMethodIncompatible;
1241         unsigned int RequiredSlots[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
1242         bool ExceededMultistreamSlots[DC__VOLTAGE_STATES];
1243         enum odm_combine_policy ODMUse[DC__NUM_DPP__MAX];
1244         unsigned int OutputMultistreamId[DC__NUM_DPP__MAX];
1245         bool OutputMultistreamEn[DC__NUM_DPP__MAX];
1246         bool UsesMALLForStaticScreen[DC__NUM_DPP__MAX];
1247         double MaxActiveDRAMClockChangeLatencySupported[DC__NUM_DPP__MAX];
1248         double WritebackAllowFCLKChangeEndPosition[DC__NUM_DPP__MAX];
1249         bool PTEBufferSizeNotExceededPerState[DC__NUM_DPP__MAX]; // new in DML32
1250         bool DCCMetaBufferSizeNotExceededPerState[DC__NUM_DPP__MAX]; // new in DML32
1251         bool NotEnoughDSCSlices[DC__VOLTAGE_STATES];
1252         bool PixelsPerLinePerDSCUnitSupport[DC__VOLTAGE_STATES];
1253         bool DCCMetaBufferSizeNotExceeded[DC__VOLTAGE_STATES][2];
1254         unsigned int dpte_row_height_linear[DC__NUM_DPP__MAX];
1255         unsigned int dpte_row_height_linear_chroma[DC__NUM_DPP__MAX];
1256         unsigned int BlockHeightY[DC__NUM_DPP__MAX];
1257         unsigned int BlockHeightC[DC__NUM_DPP__MAX];
1258         unsigned int BlockWidthY[DC__NUM_DPP__MAX];
1259         unsigned int BlockWidthC[DC__NUM_DPP__MAX];
1260         unsigned int SubViewportLinesNeededInMALL[DC__NUM_DPP__MAX];
1261         bool VActiveBandwithSupport[DC__VOLTAGE_STATES][2];
1262         struct dummy_vars dummy_vars;
1263 };
1264
1265 bool CalculateMinAndMaxPrefetchMode(
1266                 enum self_refresh_affinity AllowDRAMSelfRefreshOrDRAMClockChangeInVblank,
1267                 unsigned int *MinPrefetchMode,
1268                 unsigned int *MaxPrefetchMode);
1269
1270 double CalculateWriteBackDISPCLK(
1271                 enum source_format_class WritebackPixelFormat,
1272                 double PixelClock,
1273                 double WritebackHRatio,
1274                 double WritebackVRatio,
1275                 unsigned int WritebackLumaHTaps,
1276                 unsigned int WritebackLumaVTaps,
1277                 unsigned int WritebackChromaHTaps,
1278                 unsigned int WritebackChromaVTaps,
1279                 double WritebackDestinationWidth,
1280                 unsigned int HTotal,
1281                 unsigned int WritebackChromaLineBufferWidth);
1282
1283 #endif /* _DML2_DISPLAY_MODE_VBA_H_ */