drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26
  27 #ifndef __DML2_DISPLAY_MODE_VBA_H__
  28 #define __DML2_DISPLAY_MODE_VBA_H__
  29
  30 struct display_mode_lib;
  31
  32 void ModeSupportAndSystemConfiguration(struct display_mode_lib *mode_lib);
  33
  34 #define dml_get_attr_decl(attr) double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes)
  35
  36 dml_get_attr_decl(clk_dcf_deepsleep);
  37 dml_get_attr_decl(wm_urgent);
  38 dml_get_attr_decl(wm_memory_trip);
  39 dml_get_attr_decl(wm_writeback_urgent);
  40 dml_get_attr_decl(wm_stutter_exit);
  41 dml_get_attr_decl(wm_stutter_enter_exit);
  42 dml_get_attr_decl(wm_z8_stutter_exit);
  43 dml_get_attr_decl(wm_z8_stutter_enter_exit);
  44 dml_get_attr_decl(stutter_efficiency_z8);
  45 dml_get_attr_decl(stutter_num_bursts_z8);
  46 dml_get_attr_decl(wm_dram_clock_change);
  47 dml_get_attr_decl(wm_writeback_dram_clock_change);
  48 dml_get_attr_decl(stutter_efficiency_no_vblank);
  49 dml_get_attr_decl(stutter_efficiency);
  50 dml_get_attr_decl(stutter_period);
  51 dml_get_attr_decl(urgent_latency);
  52 dml_get_attr_decl(urgent_extra_latency);
  53 dml_get_attr_decl(nonurgent_latency);
  54 dml_get_attr_decl(dram_clock_change_latency);
  55 dml_get_attr_decl(dispclk_calculated);
  56 dml_get_attr_decl(total_data_read_bw);
  57 dml_get_attr_decl(return_bw);
  58 dml_get_attr_decl(tcalc);
  59 dml_get_attr_decl(fraction_of_urgent_bandwidth);
  60 dml_get_attr_decl(fraction_of_urgent_bandwidth_imm_flip);
  61 dml_get_attr_decl(cstate_max_cap_mode);
  62 dml_get_attr_decl(comp_buffer_size_kbytes);
  63 dml_get_attr_decl(pixel_chunk_size_in_kbyte);
  64 dml_get_attr_decl(alpha_pixel_chunk_size_in_kbyte);
  65 dml_get_attr_decl(meta_chunk_size_in_kbyte);
  66 dml_get_attr_decl(min_pixel_chunk_size_in_byte);
  67 dml_get_attr_decl(min_meta_chunk_size_in_byte);
  68 dml_get_attr_decl(fclk_watermark);
  69 dml_get_attr_decl(usr_retraining_watermark);
  70 dml_get_attr_decl(comp_buffer_reserved_space_kbytes);
  71 dml_get_attr_decl(comp_buffer_reserved_space_64bytes);
  72 dml_get_attr_decl(comp_buffer_reserved_space_zs);
  73 dml_get_attr_decl(unbounded_request_enabled);
  74
  75 #define dml_get_pipe_attr_decl(attr) double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes, unsigned int which_pipe)
  76
  77 dml_get_pipe_attr_decl(dsc_delay);
  78 dml_get_pipe_attr_decl(dppclk_calculated);
  79 dml_get_pipe_attr_decl(dscclk_calculated);
  80 dml_get_pipe_attr_decl(min_ttu_vblank);
  81 dml_get_pipe_attr_decl(min_ttu_vblank_in_us);
  82 dml_get_pipe_attr_decl(vratio_prefetch_l);
  83 dml_get_pipe_attr_decl(vratio_prefetch_c);
  84 dml_get_pipe_attr_decl(dst_x_after_scaler);
  85 dml_get_pipe_attr_decl(dst_y_after_scaler);
  86 dml_get_pipe_attr_decl(dst_y_per_vm_vblank);
  87 dml_get_pipe_attr_decl(dst_y_per_row_vblank);
  88 dml_get_pipe_attr_decl(dst_y_prefetch);
  89 dml_get_pipe_attr_decl(dst_y_per_vm_flip);
  90 dml_get_pipe_attr_decl(dst_y_per_row_flip);
  91 dml_get_pipe_attr_decl(dst_y_per_pte_row_nom_l);
  92 dml_get_pipe_attr_decl(dst_y_per_pte_row_nom_c);
  93 dml_get_pipe_attr_decl(dst_y_per_meta_row_nom_l);
  94 dml_get_pipe_attr_decl(dst_y_per_meta_row_nom_c);
  95 dml_get_pipe_attr_decl(dpte_row_height_linear_c);
  96 dml_get_pipe_attr_decl(swath_height_l);
  97 dml_get_pipe_attr_decl(swath_height_c);
  98 dml_get_pipe_attr_decl(det_stored_buffer_size_l_bytes);
  99 dml_get_pipe_attr_decl(det_stored_buffer_size_c_bytes);
 100 dml_get_pipe_attr_decl(dpte_group_size_in_bytes);
 101 dml_get_pipe_attr_decl(vm_group_size_in_bytes);
 102 dml_get_pipe_attr_decl(det_buffer_size_kbytes);
 103 dml_get_pipe_attr_decl(dpte_row_height_linear_l);
 104 dml_get_pipe_attr_decl(refcyc_per_pte_group_nom_l_in_us);
 105 dml_get_pipe_attr_decl(refcyc_per_pte_group_nom_c_in_us);
 106 dml_get_pipe_attr_decl(refcyc_per_pte_group_vblank_l_in_us);
 107 dml_get_pipe_attr_decl(refcyc_per_pte_group_vblank_c_in_us);
 108 dml_get_pipe_attr_decl(refcyc_per_pte_group_flip_l_in_us);
 109 dml_get_pipe_attr_decl(refcyc_per_pte_group_flip_c_in_us);
 110 dml_get_pipe_attr_decl(pte_buffer_mode);
 111 dml_get_pipe_attr_decl(refcyc_per_vm_group_vblank);
 112 dml_get_pipe_attr_decl(refcyc_per_vm_group_flip);
 113 dml_get_pipe_attr_decl(refcyc_per_vm_req_vblank);
 114 dml_get_pipe_attr_decl(refcyc_per_vm_req_flip);
 115 dml_get_pipe_attr_decl(refcyc_per_vm_group_vblank_in_us);
 116 dml_get_pipe_attr_decl(refcyc_per_vm_group_flip_in_us);
 117 dml_get_pipe_attr_decl(refcyc_per_vm_req_vblank_in_us);
 118 dml_get_pipe_attr_decl(refcyc_per_vm_req_flip_in_us);
 119 dml_get_pipe_attr_decl(refcyc_per_vm_dmdata_in_us);
 120 dml_get_pipe_attr_decl(dmdata_dl_delta_in_us);
 121 dml_get_pipe_attr_decl(refcyc_per_line_delivery_l_in_us);
 122 dml_get_pipe_attr_decl(refcyc_per_line_delivery_c_in_us);
 123 dml_get_pipe_attr_decl(refcyc_per_line_delivery_pre_l_in_us);
 124 dml_get_pipe_attr_decl(refcyc_per_line_delivery_pre_c_in_us);
 125 dml_get_pipe_attr_decl(refcyc_per_req_delivery_l_in_us);
 126 dml_get_pipe_attr_decl(refcyc_per_req_delivery_c_in_us);
 127 dml_get_pipe_attr_decl(refcyc_per_req_delivery_pre_l_in_us);
 128 dml_get_pipe_attr_decl(refcyc_per_req_delivery_pre_c_in_us);
 129 dml_get_pipe_attr_decl(refcyc_per_cursor_req_delivery_in_us);
 130 dml_get_pipe_attr_decl(refcyc_per_cursor_req_delivery_pre_in_us);
 131 dml_get_pipe_attr_decl(refcyc_per_meta_chunk_nom_l_in_us);
 132 dml_get_pipe_attr_decl(refcyc_per_meta_chunk_nom_c_in_us);
 133 dml_get_pipe_attr_decl(refcyc_per_meta_chunk_vblank_l_in_us);
 134 dml_get_pipe_attr_decl(refcyc_per_meta_chunk_vblank_c_in_us);
 135 dml_get_pipe_attr_decl(refcyc_per_meta_chunk_flip_l_in_us);
 136 dml_get_pipe_attr_decl(refcyc_per_meta_chunk_flip_c_in_us);
 137
 138 dml_get_pipe_attr_decl(vstartup);
 139 dml_get_pipe_attr_decl(vupdate_offset);
 140 dml_get_pipe_attr_decl(vupdate_width);
 141 dml_get_pipe_attr_decl(vready_offset);
 142 dml_get_pipe_attr_decl(vready_at_or_after_vsync);
 143 dml_get_pipe_attr_decl(min_dst_y_next_start);
 144 dml_get_pipe_attr_decl(vstartup_calculated);
 145 dml_get_pipe_attr_decl(subviewport_lines_needed_in_mall);
 146
 147 double get_total_immediate_flip_bytes(
 148                 struct display_mode_lib *mode_lib,
 149                 const display_e2e_pipe_params_st *pipes,
 150                 unsigned int num_pipes);
 151 double get_total_immediate_flip_bw(
 152                 struct display_mode_lib *mode_lib,
 153                 const display_e2e_pipe_params_st *pipes,
 154                 unsigned int num_pipes);
 155 double get_total_prefetch_bw(
 156                 struct display_mode_lib *mode_lib,
 157                 const display_e2e_pipe_params_st *pipes,
 158                 unsigned int num_pipes);
 159 unsigned int dml_get_voltage_level(
 160                 struct display_mode_lib *mode_lib,
 161                 const display_e2e_pipe_params_st *pipes,
 162                 unsigned int num_pipes);
 163
 164 unsigned int get_total_surface_size_in_mall_bytes(
 165                 struct display_mode_lib *mode_lib,
 166                 const display_e2e_pipe_params_st *pipes,
 167                 unsigned int num_pipes);
 168
 169 bool get_is_phantom_pipe(struct display_mode_lib *mode_lib,
 170                 const display_e2e_pipe_params_st *pipes,
 171                 unsigned int num_pipes,
 172                 unsigned int pipe_idx);
 173 void PixelClockAdjustmentForProgressiveToInterlaceUnit(struct display_mode_lib *mode_lib);
 174
 175 void Calculate256BBlockSizes(
 176                 enum source_format_class SourcePixelFormat,
 177                 enum dm_swizzle_mode SurfaceTiling,
 178                 unsigned int BytePerPixelY,
 179                 unsigned int BytePerPixelC,
 180                 unsigned int *BlockHeight256BytesY,
 181                 unsigned int *BlockHeight256BytesC,
 182                 unsigned int *BlockWidth256BytesY,
 183                 unsigned int *BlockWidth256BytesC);
 184
 185 struct dml32_CalculateSwathAndDETConfiguration {
 186         unsigned int MaximumSwathHeightY[DC__NUM_DPP__MAX];
 187         unsigned int MaximumSwathHeightC[DC__NUM_DPP__MAX];
 188         unsigned int RoundedUpMaxSwathSizeBytesY[DC__NUM_DPP__MAX];
 189         unsigned int RoundedUpMaxSwathSizeBytesC[DC__NUM_DPP__MAX];
 190         unsigned int RoundedUpSwathSizeBytesY;
 191         unsigned int RoundedUpSwathSizeBytesC;
 192         double SwathWidthdoubleDPP[DC__NUM_DPP__MAX];
 193         double SwathWidthdoubleDPPChroma[DC__NUM_DPP__MAX];
 194         unsigned int TotalActiveDPP;
 195         bool NoChromaSurfaces;
 196         unsigned int DETBufferSizeInKByteForSwathCalculation;
 197 };
 198
 199 struct DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation {
 200         unsigned int dummy_integer_array[2][DC__NUM_DPP__MAX];
 201         double dummy_single_array[2][DC__NUM_DPP__MAX];
 202         unsigned int dummy_long_array[2][DC__NUM_DPP__MAX];
 203         double dummy_double_array[2][DC__NUM_DPP__MAX];
 204         bool dummy_boolean_array[DC__NUM_DPP__MAX];
 205         bool dummy_boolean;
 206         bool dummy_boolean2;
 207         enum output_encoder_class dummy_output_encoder_array[DC__NUM_DPP__MAX];
 208         DmlPipe SurfaceParameters[DC__NUM_DPP__MAX];
 209         bool dummy_boolean_array2[2][DC__NUM_DPP__MAX];
 210         unsigned int ReorderBytes;
 211         unsigned int VMDataOnlyReturnBW;
 212         double HostVMInefficiencyFactor;
 213         DmlPipe myPipe;
 214         SOCParametersList mmSOCParameters;
 215         double dummy_unit_vector[DC__NUM_DPP__MAX];
 216         double dummy_single[2];
 217         enum clock_change_support dummy_dramchange_support;
 218         enum dm_fclock_change_support dummy_fclkchange_support;
 219         bool dummy_USRRetrainingSupport;
 220 };
 221
 222 struct dml32_ModeSupportAndSystemConfigurationFull {
 223         unsigned int dummy_integer_array[22][DC__NUM_DPP__MAX];
 224         double dummy_double_array[2][DC__NUM_DPP__MAX];
 225         DmlPipe SurfParameters[DC__NUM_DPP__MAX];
 226         double dummy_single[5];
 227         double dummy_single2[5];
 228         SOCParametersList mSOCParameters;
 229         unsigned int MaximumSwathWidthSupportLuma;
 230         unsigned int MaximumSwathWidthSupportChroma;
 231         double DSTYAfterScaler[DC__NUM_DPP__MAX];
 232         double DSTXAfterScaler[DC__NUM_DPP__MAX];
 233         double MaxTotalVActiveRDBandwidth;
 234         bool dummy_boolean_array[2][DC__NUM_DPP__MAX];
 235         enum odm_combine_mode dummy_odm_mode[DC__NUM_DPP__MAX];
 236         DmlPipe myPipe;
 237         unsigned int dummy_integer[4];
 238         unsigned int TotalNumberOfActiveOTG;
 239         unsigned int TotalNumberOfActiveHDMIFRL;
 240         unsigned int TotalNumberOfActiveDP2p0;
 241         unsigned int TotalNumberOfActiveDP2p0Outputs;
 242         unsigned int TotalDSCUnitsRequired;
 243         unsigned int ReorderingBytes;
 244         unsigned int TotalSlots;
 245         unsigned int NumberOfDPPDSC;
 246         unsigned int NumberOfDPPNoDSC;
 247         unsigned int NextPrefetchModeState;
 248         bool MPCCombineMethodAsNeededForPStateChangeAndVoltage;
 249         bool MPCCombineMethodAsPossible;
 250         bool FullFrameMALLPStateMethod;
 251         bool SubViewportMALLPStateMethod;
 252         bool PhantomPipeMALLPStateMethod;
 253         bool NoChroma;
 254         bool TotalAvailablePipesSupportNoDSC;
 255         bool TotalAvailablePipesSupportDSC;
 256         enum odm_combine_mode ODMModeNoDSC;
 257         enum odm_combine_mode ODMModeDSC;
 258         double RequiredDISPCLKPerSurfaceNoDSC;
 259         double RequiredDISPCLKPerSurfaceDSC;
 260         double BWOfNonCombinedSurfaceOfMaximumBandwidth;
 261         double VMDataOnlyReturnBWPerState;
 262         double HostVMInefficiencyFactor;
 263         bool dummy_boolean[2];
 264 };
 265
 266 struct dummy_vars {
 267         struct DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation
 268         DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation;
 269         struct dml32_ModeSupportAndSystemConfigurationFull dml32_ModeSupportAndSystemConfigurationFull;
 270         struct dml32_CalculateSwathAndDETConfiguration dml32_CalculateSwathAndDETConfiguration;
 271 };
 272
 273 struct vba_vars_st {
 274         ip_params_st ip;
 275         soc_bounding_box_st soc;
 276
 277         int maxMpcComb;
 278         bool UseMaximumVStartup;
 279
 280         double WritebackDISPCLK;
 281         double DPPCLKUsingSingleDPPLuma;
 282         double DPPCLKUsingSingleDPPChroma;
 283         double DISPCLKWithRamping;
 284         double DISPCLKWithoutRamping;
 285         double GlobalDPPCLK;
 286         double DISPCLKWithRampingRoundedToDFSGranularity;
 287         double DISPCLKWithoutRampingRoundedToDFSGranularity;
 288         double MaxDispclkRoundedToDFSGranularity;
 289         bool DCCEnabledAnyPlane;
 290         double ReturnBandwidthToDCN;
 291         unsigned int TotalActiveDPP;
 292         unsigned int TotalDCCActiveDPP;
 293         double UrgentRoundTripAndOutOfOrderLatency;
 294         double StutterPeriod;
 295         double FrameTimeForMinFullDETBufferingTime;
 296         double AverageReadBandwidth;
 297         double TotalRowReadBandwidth;
 298         double PartOfBurstThatFitsInROB;
 299         double StutterBurstTime;
 300         unsigned int NextPrefetchMode;
 301         double NextMaxVStartup;
 302         double VBlankTime;
 303         double SmallestVBlank;
 304         enum dm_prefetch_modes AllowForPStateChangeOrStutterInVBlankFinal; // Mode Support only
 305         double DCFCLKDeepSleepPerPlane[DC__NUM_DPP__MAX];
 306         double EffectiveDETPlusLBLinesLuma;
 307         double EffectiveDETPlusLBLinesChroma;
 308         double UrgentLatencySupportUsLuma;
 309         double UrgentLatencySupportUsChroma;
 310         unsigned int DSCFormatFactor;
 311
 312         bool DummyPStateCheck;
 313         bool DRAMClockChangeSupportsVActive;
 314         bool PrefetchModeSupported;
 315         bool PrefetchAndImmediateFlipSupported;
 316         enum self_refresh_affinity AllowDRAMSelfRefreshOrDRAMClockChangeInVblank; // Mode Support only
 317         double XFCRemoteSurfaceFlipDelay;
 318         double TInitXFill;
 319         double TslvChk;
 320         double SrcActiveDrainRate;
 321         bool ImmediateFlipSupported;
 322         enum mpc_combine_affinity WhenToDoMPCCombine; // Mode Support only
 323
 324         bool PrefetchERROR;
 325
 326         unsigned int VStartupLines;
 327         unsigned int ActiveDPPs;
 328         unsigned int LBLatencyHidingSourceLinesY;
 329         unsigned int LBLatencyHidingSourceLinesC;
 330         double ActiveDRAMClockChangeLatencyMargin[DC__NUM_DPP__MAX];
 331         double CachedActiveDRAMClockChangeLatencyMargin[DC__NUM_DPP__MAX]; // Cache in dml_get_voltage_level for debug purposes only
 332         double MinActiveDRAMClockChangeMargin;
 333         double InitFillLevel;
 334         double FinalFillMargin;
 335         double FinalFillLevel;
 336         double RemainingFillLevel;
 337         double TFinalxFill;
 338
 339         //
 340         // SOC Bounding Box Parameters
 341         //
 342         double SRExitTime;
 343         double SREnterPlusExitTime;
 344         double UrgentLatencyPixelDataOnly;
 345         double UrgentLatencyPixelMixedWithVMData;
 346         double UrgentLatencyVMDataOnly;
 347         double UrgentLatency; // max of the above three
 348         double USRRetrainingLatency;
 349         double SMNLatency;
 350         double FCLKChangeLatency;
 351         unsigned int MALLAllocatedForDCNFinal;
 352         double MaxAveragePercentOfIdealFabricBWDisplayCanUseInNormalSystemOperation;
 353         double MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperationSTROBE;
 354         double PercentOfIdealDRAMBWReceivedAfterUrgLatencySTROBE;
 355         double WritebackLatency;
 356         double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly; // Mode Support
 357         double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData; // Mode Support
 358         double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly; // Mode Support
 359         double MaxAveragePercentOfIdealSDPPortBWDisplayCanUseInNormalSystemOperation; // Mode Support
 360         double MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperation; // Mode Support
 361         double NumberOfChannels;
 362         double DRAMChannelWidth;
 363         double FabricDatapathToDCNDataReturn;
 364         double ReturnBusWidth;
 365         double Downspreading;
 366         double DISPCLKDPPCLKDSCCLKDownSpreading;
 367         double DISPCLKDPPCLKVCOSpeed;
 368         double RoundTripPingLatencyCycles;
 369         double UrgentOutOfOrderReturnPerChannel;
 370         double UrgentOutOfOrderReturnPerChannelPixelDataOnly;
 371         double UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData;
 372         double UrgentOutOfOrderReturnPerChannelVMDataOnly;
 373         unsigned int VMMPageSize;
 374         double DRAMClockChangeLatency;
 375         double XFCBusTransportTime;
 376         bool UseUrgentBurstBandwidth;
 377         double XFCXBUFLatencyTolerance;
 378
 379         //
 380         // IP Parameters
 381         //
 382         unsigned int ROBBufferSizeInKByte;
 383         unsigned int DETBufferSizeInKByte[DC__NUM_DPP__MAX];
 384         double DETBufferSizeInTime;
 385         unsigned int DPPOutputBufferPixels;
 386         unsigned int OPPOutputBufferLines;
 387         unsigned int PixelChunkSizeInKByte;
 388         double ReturnBW;
 389         bool GPUVMEnable;
 390         bool HostVMEnable;
 391         unsigned int GPUVMMaxPageTableLevels;
 392         unsigned int HostVMMaxPageTableLevels;
 393         unsigned int HostVMCachedPageTableLevels;
 394         unsigned int OverrideGPUVMPageTableLevels;
 395         unsigned int OverrideHostVMPageTableLevels;
 396         unsigned int MetaChunkSize;
 397         unsigned int MinMetaChunkSizeBytes;
 398         unsigned int WritebackChunkSize;
 399         bool ODMCapability;
 400         unsigned int NumberOfDSC;
 401         unsigned int LineBufferSize;
 402         unsigned int MaxLineBufferLines;
 403         unsigned int WritebackInterfaceLumaBufferSize;
 404         unsigned int WritebackInterfaceChromaBufferSize;
 405         unsigned int WritebackChromaLineBufferWidth;
 406         enum writeback_config WritebackConfiguration;
 407         double MaxDCHUBToPSCLThroughput;
 408         double MaxPSCLToLBThroughput;
 409         unsigned int PTEBufferSizeInRequestsLuma;
 410         unsigned int PTEBufferSizeInRequestsChroma;
 411         double DISPCLKRampingMargin;
 412         unsigned int MaxInterDCNTileRepeaters;
 413         bool XFCSupported;
 414         double XFCSlvChunkSize;
 415         double XFCFillBWOverhead;
 416         double XFCFillConstant;
 417         double XFCTSlvVupdateOffset;
 418         double XFCTSlvVupdateWidth;
 419         double XFCTSlvVreadyOffset;
 420         double DPPCLKDelaySubtotal;
 421         double DPPCLKDelaySCL;
 422         double DPPCLKDelaySCLLBOnly;
 423         double DPPCLKDelayCNVCFormater;
 424         double DPPCLKDelayCNVCCursor;
 425         double DISPCLKDelaySubtotal;
 426         bool ProgressiveToInterlaceUnitInOPP;
 427         unsigned int CompressedBufferSegmentSizeInkByteFinal;
 428         unsigned int CompbufReservedSpace64B;
 429         unsigned int CompbufReservedSpaceZs;
 430         unsigned int LineBufferSizeFinal;
 431         unsigned int MaximumPixelsPerLinePerDSCUnit;
 432         unsigned int AlphaPixelChunkSizeInKByte;
 433         double MinPixelChunkSizeBytes;
 434         unsigned int DCCMetaBufferSizeBytes;
 435         // Pipe/Plane Parameters
 436         int VoltageLevel;
 437         double FabricClock;
 438         double DRAMSpeed;
 439         double DISPCLK;
 440         double SOCCLK;
 441         double DCFCLK;
 442         unsigned int MaxTotalDETInKByte;
 443         unsigned int MinCompressedBufferSizeInKByte;
 444         unsigned int NumberOfActiveSurfaces;
 445         bool ViewportStationary[DC__NUM_DPP__MAX];
 446         unsigned int RefreshRate[DC__NUM_DPP__MAX];
 447         double       OutputBPP[DC__NUM_DPP__MAX];
 448         unsigned int GPUVMMinPageSizeKBytes[DC__NUM_DPP__MAX];
 449         bool SynchronizeTimingsFinal;
 450         bool SynchronizeDRRDisplaysForUCLKPStateChangeFinal;
 451         bool ForceOneRowForFrame[DC__NUM_DPP__MAX];
 452         unsigned int ViewportXStartY[DC__NUM_DPP__MAX];
 453         unsigned int ViewportXStartC[DC__NUM_DPP__MAX];
 454         enum dm_rotation_angle SourceRotation[DC__NUM_DPP__MAX];
 455         bool DRRDisplay[DC__NUM_DPP__MAX];
 456         bool PteBufferMode[DC__NUM_DPP__MAX];
 457         enum dm_output_type OutputType[DC__NUM_DPP__MAX];
 458         enum dm_output_rate OutputRate[DC__NUM_DPP__MAX];
 459
 460         unsigned int NumberOfActivePlanes;
 461         unsigned int NumberOfDSCSlices[DC__NUM_DPP__MAX];
 462         unsigned int ViewportWidth[DC__NUM_DPP__MAX];
 463         unsigned int ViewportHeight[DC__NUM_DPP__MAX];
 464         unsigned int ViewportYStartY[DC__NUM_DPP__MAX];
 465         unsigned int ViewportYStartC[DC__NUM_DPP__MAX];
 466         unsigned int PitchY[DC__NUM_DPP__MAX];
 467         unsigned int PitchC[DC__NUM_DPP__MAX];
 468         double HRatio[DC__NUM_DPP__MAX];
 469         double VRatio[DC__NUM_DPP__MAX];
 470         unsigned int htaps[DC__NUM_DPP__MAX];
 471         unsigned int vtaps[DC__NUM_DPP__MAX];
 472         unsigned int HTAPsChroma[DC__NUM_DPP__MAX];
 473         unsigned int VTAPsChroma[DC__NUM_DPP__MAX];
 474         unsigned int HTotal[DC__NUM_DPP__MAX];
 475         unsigned int VTotal[DC__NUM_DPP__MAX];
 476         unsigned int VTotal_Max[DC__NUM_DPP__MAX];
 477         unsigned int VTotal_Min[DC__NUM_DPP__MAX];
 478         int DPPPerPlane[DC__NUM_DPP__MAX];
 479         double PixelClock[DC__NUM_DPP__MAX];
 480         double PixelClockBackEnd[DC__NUM_DPP__MAX];
 481         bool DCCEnable[DC__NUM_DPP__MAX];
 482         bool FECEnable[DC__NUM_DPP__MAX];
 483         unsigned int DCCMetaPitchY[DC__NUM_DPP__MAX];
 484         unsigned int DCCMetaPitchC[DC__NUM_DPP__MAX];
 485         enum scan_direction_class SourceScan[DC__NUM_DPP__MAX];
 486         enum source_format_class SourcePixelFormat[DC__NUM_DPP__MAX];
 487         bool WritebackEnable[DC__NUM_DPP__MAX];
 488         unsigned int ActiveWritebacksPerPlane[DC__NUM_DPP__MAX];
 489         double WritebackDestinationWidth[DC__NUM_DPP__MAX];
 490         double WritebackDestinationHeight[DC__NUM_DPP__MAX];
 491         double WritebackSourceHeight[DC__NUM_DPP__MAX];
 492         enum source_format_class WritebackPixelFormat[DC__NUM_DPP__MAX];
 493         unsigned int WritebackLumaHTaps[DC__NUM_DPP__MAX];
 494         unsigned int WritebackLumaVTaps[DC__NUM_DPP__MAX];
 495         unsigned int WritebackChromaHTaps[DC__NUM_DPP__MAX];
 496         unsigned int WritebackChromaVTaps[DC__NUM_DPP__MAX];
 497         double WritebackHRatio[DC__NUM_DPP__MAX];
 498         double WritebackVRatio[DC__NUM_DPP__MAX];
 499         unsigned int HActive[DC__NUM_DPP__MAX];
 500         unsigned int VActive[DC__NUM_DPP__MAX];
 501         bool Interlace[DC__NUM_DPP__MAX];
 502         enum dm_swizzle_mode SurfaceTiling[DC__NUM_DPP__MAX];
 503         unsigned int ScalerRecoutWidth[DC__NUM_DPP__MAX];
 504         bool DynamicMetadataEnable[DC__NUM_DPP__MAX];
 505         int DynamicMetadataLinesBeforeActiveRequired[DC__NUM_DPP__MAX];
 506         unsigned int DynamicMetadataTransmittedBytes[DC__NUM_DPP__MAX];
 507         double DCCRate[DC__NUM_DPP__MAX];
 508         double AverageDCCCompressionRate;
 509         enum odm_combine_mode ODMCombineEnabled[DC__NUM_DPP__MAX];
 510         double OutputBpp[DC__NUM_DPP__MAX];
 511         bool DSCEnabled[DC__NUM_DPP__MAX];
 512         unsigned int DSCInputBitPerComponent[DC__NUM_DPP__MAX];
 513         enum output_format_class OutputFormat[DC__NUM_DPP__MAX];
 514         enum output_encoder_class Output[DC__NUM_DPP__MAX];
 515         bool skip_dio_check[DC__NUM_DPP__MAX];
 516         unsigned int BlendingAndTiming[DC__NUM_DPP__MAX];
 517         bool SynchronizedVBlank;
 518         unsigned int NumberOfCursors[DC__NUM_DPP__MAX];
 519         unsigned int CursorWidth[DC__NUM_DPP__MAX][DC__NUM_CURSOR__MAX];
 520         unsigned int CursorBPP[DC__NUM_DPP__MAX][DC__NUM_CURSOR__MAX];
 521         bool XFCEnabled[DC__NUM_DPP__MAX];
 522         bool ScalerEnabled[DC__NUM_DPP__MAX];
 523         unsigned int VBlankNom[DC__NUM_DPP__MAX];
 524         bool DisableUnboundRequestIfCompBufReservedSpaceNeedAdjustment;
 525
 526         // Intermediates/Informational
 527         bool ImmediateFlipSupport;
 528         unsigned int DETBufferSizeY[DC__NUM_DPP__MAX];
 529         unsigned int DETBufferSizeC[DC__NUM_DPP__MAX];
 530         unsigned int SwathHeightY[DC__NUM_DPP__MAX];
 531         unsigned int SwathHeightC[DC__NUM_DPP__MAX];
 532         unsigned int LBBitPerPixel[DC__NUM_DPP__MAX];
 533         double LastPixelOfLineExtraWatermark;
 534         double TotalDataReadBandwidth;
 535         unsigned int TotalActiveWriteback;
 536         unsigned int EffectiveLBLatencyHidingSourceLinesLuma;
 537         unsigned int EffectiveLBLatencyHidingSourceLinesChroma;
 538         double BandwidthAvailableForImmediateFlip;
 539         unsigned int PrefetchMode[DC__VOLTAGE_STATES][2];
 540         unsigned int PrefetchModePerState[DC__VOLTAGE_STATES][2];
 541         unsigned int MinPrefetchMode;
 542         unsigned int MaxPrefetchMode;
 543         bool AnyLinesForVMOrRowTooLarge;
 544         double MaxVStartup;
 545         bool IgnoreViewportPositioning;
 546         bool ErrorResult[DC__NUM_DPP__MAX];
 547         //
 548         // Calculated dml_ml->vba.Outputs
 549         //
 550         double DCFCLKDeepSleep;
 551         double UrgentWatermark;
 552         double UrgentExtraLatency;
 553         double WritebackUrgentWatermark;
 554         double StutterExitWatermark;
 555         double StutterEnterPlusExitWatermark;
 556         double DRAMClockChangeWatermark;
 557         double WritebackDRAMClockChangeWatermark;
 558         double StutterEfficiency;
 559         double StutterEfficiencyNotIncludingVBlank;
 560         double NonUrgentLatencyTolerance;
 561         double MinActiveDRAMClockChangeLatencySupported;
 562         double Z8StutterEfficiencyBestCase;
 563         unsigned int Z8NumberOfStutterBurstsPerFrameBestCase;
 564         double Z8StutterEfficiencyNotIncludingVBlankBestCase;
 565         double StutterPeriodBestCase;
 566         Watermarks      Watermark;
 567         bool DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE;
 568         unsigned int CompBufReservedSpaceKBytes;
 569         unsigned int CompBufReservedSpace64B;
 570         unsigned int CompBufReservedSpaceZs;
 571         bool CompBufReservedSpaceNeedAdjustment;
 572
 573         // These are the clocks calcuated by the library but they are not actually
 574         // used explicitly. They are fetched by tests and then possibly used. The
 575         // ultimate values to use are the ones specified by the parameters to DML
 576         double DISPCLK_calculated;
 577         double DPPCLK_calculated[DC__NUM_DPP__MAX];
 578
 579         bool ImmediateFlipSupportedSurface[DC__NUM_DPP__MAX];
 580
 581         bool Use_One_Row_For_Frame[DC__NUM_DPP__MAX];
 582         bool Use_One_Row_For_Frame_Flip[DC__NUM_DPP__MAX];
 583         unsigned int VUpdateOffsetPix[DC__NUM_DPP__MAX];
 584         double VUpdateWidthPix[DC__NUM_DPP__MAX];
 585         double VReadyOffsetPix[DC__NUM_DPP__MAX];
 586
 587         unsigned int TotImmediateFlipBytes;
 588         double TCalc;
 589
 590         display_e2e_pipe_params_st cache_pipes[DC__NUM_DPP__MAX];
 591         unsigned int cache_num_pipes;
 592         unsigned int pipe_plane[DC__NUM_DPP__MAX];
 593
 594         /* vba mode support */
 595         /*inputs*/
 596         bool SupportGFX7CompatibleTilingIn32bppAnd64bpp;
 597         double MaxHSCLRatio;
 598         double MaxVSCLRatio;
 599         unsigned int MaxNumWriteback;
 600         bool WritebackLumaAndChromaScalingSupported;
 601         bool Cursor64BppSupport;
 602         double DCFCLKPerState[DC__VOLTAGE_STATES];
 603         double DCFCLKState[DC__VOLTAGE_STATES][2];
 604         double FabricClockPerState[DC__VOLTAGE_STATES];
 605         double SOCCLKPerState[DC__VOLTAGE_STATES];
 606         double PHYCLKPerState[DC__VOLTAGE_STATES];
 607         double DTBCLKPerState[DC__VOLTAGE_STATES];
 608         double MaxDppclk[DC__VOLTAGE_STATES];
 609         double MaxDSCCLK[DC__VOLTAGE_STATES];
 610         double DRAMSpeedPerState[DC__VOLTAGE_STATES];
 611         double MaxDispclk[DC__VOLTAGE_STATES];
 612         int VoltageOverrideLevel;
 613         double PHYCLKD32PerState[DC__VOLTAGE_STATES];
 614
 615         /*outputs*/
 616         bool ScaleRatioAndTapsSupport;
 617         bool SourceFormatPixelAndScanSupport;
 618         double TotalBandwidthConsumedGBytePerSecond;
 619         bool DCCEnabledInAnyPlane;
 620         bool WritebackLatencySupport;
 621         bool WritebackModeSupport;
 622         bool Writeback10bpc420Supported;
 623         bool BandwidthSupport[DC__VOLTAGE_STATES];
 624         unsigned int TotalNumberOfActiveWriteback;
 625         double CriticalPoint;
 626         double ReturnBWToDCNPerState;
 627         bool IsErrorResult[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 628         bool prefetch_vm_bw_valid;
 629         bool prefetch_row_bw_valid;
 630         bool NumberOfOTGSupport;
 631         bool NonsupportedDSCInputBPC;
 632         bool WritebackScaleRatioAndTapsSupport;
 633         bool CursorSupport;
 634         bool PitchSupport;
 635         enum dm_validation_status ValidationStatus[DC__VOLTAGE_STATES];
 636
 637         /* Mode Support Reason */
 638         bool P2IWith420;
 639         bool DSCOnlyIfNecessaryWithBPP;
 640         bool DSC422NativeNotSupported;
 641         bool LinkRateDoesNotMatchDPVersion;
 642         bool LinkRateForMultistreamNotIndicated;
 643         bool BPPForMultistreamNotIndicated;
 644         bool MultistreamWithHDMIOreDP;
 645         bool MSOOrODMSplitWithNonDPLink;
 646         bool NotEnoughLanesForMSO;
 647         bool ViewportExceedsSurface;
 648
 649         bool ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified;
 650         bool ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe;
 651         bool InvalidCombinationOfMALLUseForPStateAndStaticScreen;
 652         bool InvalidCombinationOfMALLUseForPState;
 653
 654         enum dm_output_link_dp_rate OutputLinkDPRate[DC__NUM_DPP__MAX];
 655         double PrefetchLinesYThisState[DC__NUM_DPP__MAX];
 656         double PrefetchLinesCThisState[DC__NUM_DPP__MAX];
 657         double meta_row_bandwidth_this_state[DC__NUM_DPP__MAX];
 658         double dpte_row_bandwidth_this_state[DC__NUM_DPP__MAX];
 659         double DPTEBytesPerRowThisState[DC__NUM_DPP__MAX];
 660         double PDEAndMetaPTEBytesPerFrameThisState[DC__NUM_DPP__MAX];
 661         double MetaRowBytesThisState[DC__NUM_DPP__MAX];
 662         bool use_one_row_for_frame[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 663         bool use_one_row_for_frame_flip[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 664         bool use_one_row_for_frame_this_state[DC__NUM_DPP__MAX];
 665         bool use_one_row_for_frame_flip_this_state[DC__NUM_DPP__MAX];
 666
 667         unsigned int OutputTypeAndRatePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
 668         double RequiredDISPCLKPerSurface[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 669         unsigned int MicroTileHeightY[DC__NUM_DPP__MAX];
 670         unsigned int MicroTileHeightC[DC__NUM_DPP__MAX];
 671         unsigned int MicroTileWidthY[DC__NUM_DPP__MAX];
 672         unsigned int MicroTileWidthC[DC__NUM_DPP__MAX];
 673         bool ImmediateFlipRequiredFinal;
 674         bool DCCProgrammingAssumesScanDirectionUnknownFinal;
 675         bool EnoughWritebackUnits;
 676         bool ODMCombine2To1SupportCheckOK[DC__VOLTAGE_STATES];
 677         bool NumberOfDP2p0Support;
 678         unsigned int MaxNumDP2p0Streams;
 679         unsigned int MaxNumDP2p0Outputs;
 680         enum dm_output_type OutputTypePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
 681         enum dm_output_rate OutputRatePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
 682         double WritebackLineBufferLumaBufferSize;
 683         double WritebackLineBufferChromaBufferSize;
 684         double WritebackMinHSCLRatio;
 685         double WritebackMinVSCLRatio;
 686         double WritebackMaxHSCLRatio;
 687         double WritebackMaxVSCLRatio;
 688         double WritebackMaxHSCLTaps;
 689         double WritebackMaxVSCLTaps;
 690         unsigned int MaxNumDPP;
 691         unsigned int MaxNumOTG;
 692         double CursorBufferSize;
 693         double CursorChunkSize;
 694         unsigned int Mode;
 695         double OutputLinkDPLanes[DC__NUM_DPP__MAX];
 696         double ForcedOutputLinkBPP[DC__NUM_DPP__MAX]; // Mode Support only
 697         double ImmediateFlipBW[DC__NUM_DPP__MAX];
 698         double MaxMaxVStartup[DC__VOLTAGE_STATES][2];
 699
 700         double WritebackLumaVExtra;
 701         double WritebackChromaVExtra;
 702         double WritebackRequiredDISPCLK;
 703         double MaximumSwathWidthSupport;
 704         double MaximumSwathWidthInDETBuffer;
 705         double MaximumSwathWidthInLineBuffer;
 706         double MaxDispclkRoundedDownToDFSGranularity;
 707         double MaxDppclkRoundedDownToDFSGranularity;
 708         double PlaneRequiredDISPCLKWithoutODMCombine;
 709         double PlaneRequiredDISPCLKWithODMCombine;
 710         double PlaneRequiredDISPCLK;
 711         double TotalNumberOfActiveOTG;
 712         double FECOverhead;
 713         double EffectiveFECOverhead;
 714         double Outbpp;
 715         unsigned int OutbppDSC;
 716         double TotalDSCUnitsRequired;
 717         double bpp;
 718         unsigned int slices;
 719         double SwathWidthGranularityY;
 720         double RoundedUpMaxSwathSizeBytesY;
 721         double SwathWidthGranularityC;
 722         double RoundedUpMaxSwathSizeBytesC;
 723         double EffectiveDETLBLinesLuma;
 724         double EffectiveDETLBLinesChroma;
 725         double ProjectedDCFCLKDeepSleep[DC__VOLTAGE_STATES][2];
 726         double PDEAndMetaPTEBytesPerFrameY;
 727         double PDEAndMetaPTEBytesPerFrameC;
 728         unsigned int MetaRowBytesY;
 729         unsigned int MetaRowBytesC;
 730         unsigned int DPTEBytesPerRowC;
 731         unsigned int DPTEBytesPerRowY;
 732         double ExtraLatency;
 733         double TimeCalc;
 734         double TWait;
 735         double MaximumReadBandwidthWithPrefetch;
 736         double MaximumReadBandwidthWithoutPrefetch;
 737         double total_dcn_read_bw_with_flip;
 738         double total_dcn_read_bw_with_flip_no_urgent_burst;
 739         double FractionOfUrgentBandwidth;
 740         double FractionOfUrgentBandwidthImmediateFlip; // Mode Support debugging output
 741
 742         /* ms locals */
 743         double IdealSDPPortBandwidthPerState[DC__VOLTAGE_STATES][2];
 744         unsigned int NoOfDPP[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 745         int NoOfDPPThisState[DC__NUM_DPP__MAX];
 746         enum odm_combine_mode ODMCombineEnablePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
 747         double SwathWidthYThisState[DC__NUM_DPP__MAX];
 748         unsigned int SwathHeightCPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 749         unsigned int SwathHeightYThisState[DC__NUM_DPP__MAX];
 750         unsigned int SwathHeightCThisState[DC__NUM_DPP__MAX];
 751         double VRatioPreY[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 752         double VRatioPreC[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 753         double RequiredPrefetchPixelDataBWLuma[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 754         double RequiredPrefetchPixelDataBWChroma[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 755         double RequiredDPPCLK[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 756         double RequiredDPPCLKThisState[DC__NUM_DPP__MAX];
 757         bool PTEBufferSizeNotExceededY[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 758         bool PTEBufferSizeNotExceededC[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 759         bool BandwidthWithoutPrefetchSupported[DC__VOLTAGE_STATES][2];
 760         bool PrefetchSupported[DC__VOLTAGE_STATES][2];
 761         bool VRatioInPrefetchSupported[DC__VOLTAGE_STATES][2];
 762         double RequiredDISPCLK[DC__VOLTAGE_STATES][2];
 763         bool DISPCLK_DPPCLK_Support[DC__VOLTAGE_STATES][2];
 764         bool TotalAvailablePipesSupport[DC__VOLTAGE_STATES][2];
 765         unsigned int TotalNumberOfActiveDPP[DC__VOLTAGE_STATES][2];
 766         unsigned int TotalNumberOfDCCActiveDPP[DC__VOLTAGE_STATES][2];
 767         bool ModeSupport[DC__VOLTAGE_STATES][2];
 768         double ReturnBWPerState[DC__VOLTAGE_STATES][2];
 769         bool DIOSupport[DC__VOLTAGE_STATES];
 770         bool NotEnoughDSCUnits[DC__VOLTAGE_STATES];
 771         bool DSCCLKRequiredMoreThanSupported[DC__VOLTAGE_STATES];
 772         bool DTBCLKRequiredMoreThanSupported[DC__VOLTAGE_STATES];
 773         double UrgentRoundTripAndOutOfOrderLatencyPerState[DC__VOLTAGE_STATES];
 774         bool ROBSupport[DC__VOLTAGE_STATES][2];
 775         //based on rev 99: Dim DCCMetaBufferSizeSupport(NumberOfStates, 1) As Boolean
 776         bool DCCMetaBufferSizeSupport[DC__VOLTAGE_STATES][2];
 777         bool PTEBufferSizeNotExceeded[DC__VOLTAGE_STATES][2];
 778         bool TotalVerticalActiveBandwidthSupport[DC__VOLTAGE_STATES][2];
 779         double MaxTotalVerticalActiveAvailableBandwidth[DC__VOLTAGE_STATES][2];
 780         double PrefetchBW[DC__NUM_DPP__MAX];
 781         double PDEAndMetaPTEBytesPerFrame[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 782         double MetaRowBytes[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 783         double DPTEBytesPerRow[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 784         double PrefetchLinesY[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 785         double PrefetchLinesC[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 786         unsigned int MaxNumSwY[DC__NUM_DPP__MAX];
 787         unsigned int MaxNumSwC[DC__NUM_DPP__MAX];
 788         double PrefillY[DC__NUM_DPP__MAX];
 789         double PrefillC[DC__NUM_DPP__MAX];
 790         double LineTimesForPrefetch[DC__NUM_DPP__MAX];
 791         double LinesForMetaPTE[DC__NUM_DPP__MAX];
 792         double LinesForMetaAndDPTERow[DC__NUM_DPP__MAX];
 793         double MinDPPCLKUsingSingleDPP[DC__NUM_DPP__MAX];
 794         double SwathWidthYSingleDPP[DC__NUM_DPP__MAX];
 795         double BytePerPixelInDETY[DC__NUM_DPP__MAX];
 796         double BytePerPixelInDETC[DC__NUM_DPP__MAX];
 797         bool RequiresDSC[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
 798         unsigned int NumberOfDSCSlice[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
 799         double RequiresFEC[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
 800         double OutputBppPerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
 801         double DSCDelayPerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
 802         bool ViewportSizeSupport[DC__VOLTAGE_STATES][2];
 803         unsigned int Read256BlockHeightY[DC__NUM_DPP__MAX];
 804         unsigned int Read256BlockWidthY[DC__NUM_DPP__MAX];
 805         unsigned int Read256BlockHeightC[DC__NUM_DPP__MAX];
 806         unsigned int Read256BlockWidthC[DC__NUM_DPP__MAX];
 807         double MaxSwathHeightY[DC__NUM_DPP__MAX];
 808         double MaxSwathHeightC[DC__NUM_DPP__MAX];
 809         double MinSwathHeightY[DC__NUM_DPP__MAX];
 810         double MinSwathHeightC[DC__NUM_DPP__MAX];
 811         double ReadBandwidthLuma[DC__NUM_DPP__MAX];
 812         double ReadBandwidthChroma[DC__NUM_DPP__MAX];
 813         double ReadBandwidth[DC__NUM_DPP__MAX];
 814         double WriteBandwidth[DC__NUM_DPP__MAX];
 815         double PSCL_FACTOR[DC__NUM_DPP__MAX];
 816         double PSCL_FACTOR_CHROMA[DC__NUM_DPP__MAX];
 817         double MaximumVStartup[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 818         unsigned int MacroTileWidthY[DC__NUM_DPP__MAX];
 819         unsigned int MacroTileWidthC[DC__NUM_DPP__MAX];
 820         double AlignedDCCMetaPitch[DC__NUM_DPP__MAX];
 821         double AlignedYPitch[DC__NUM_DPP__MAX];
 822         double AlignedCPitch[DC__NUM_DPP__MAX];
 823         double MaximumSwathWidth[DC__NUM_DPP__MAX];
 824         double cursor_bw[DC__NUM_DPP__MAX];
 825         double cursor_bw_pre[DC__NUM_DPP__MAX];
 826         double Tno_bw[DC__NUM_DPP__MAX];
 827         double prefetch_vmrow_bw[DC__NUM_DPP__MAX];
 828         double DestinationLinesToRequestVMInImmediateFlip[DC__NUM_DPP__MAX];
 829         double DestinationLinesToRequestRowInImmediateFlip[DC__NUM_DPP__MAX];
 830         double final_flip_bw[DC__NUM_DPP__MAX];
 831         bool ImmediateFlipSupportedForState[DC__VOLTAGE_STATES][2];
 832         double WritebackDelay[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
 833         unsigned int vm_group_bytes[DC__NUM_DPP__MAX];
 834         unsigned int dpte_group_bytes[DC__NUM_DPP__MAX];
 835         unsigned int dpte_row_height[DC__NUM_DPP__MAX];
 836         unsigned int meta_req_height[DC__NUM_DPP__MAX];
 837         unsigned int meta_req_width[DC__NUM_DPP__MAX];
 838         unsigned int meta_row_height[DC__NUM_DPP__MAX];
 839         unsigned int meta_row_width[DC__NUM_DPP__MAX];
 840         unsigned int dpte_row_height_chroma[DC__NUM_DPP__MAX];
 841         unsigned int meta_req_height_chroma[DC__NUM_DPP__MAX];
 842         unsigned int meta_req_width_chroma[DC__NUM_DPP__MAX];
 843         unsigned int meta_row_height_chroma[DC__NUM_DPP__MAX];
 844         unsigned int meta_row_width_chroma[DC__NUM_DPP__MAX];
 845         bool ImmediateFlipSupportedForPipe[DC__NUM_DPP__MAX];
 846         double meta_row_bw[DC__NUM_DPP__MAX];
 847         double dpte_row_bw[DC__NUM_DPP__MAX];
 848         double DisplayPipeLineDeliveryTimeLuma[DC__NUM_DPP__MAX];                     // WM
 849         double DisplayPipeLineDeliveryTimeChroma[DC__NUM_DPP__MAX];                     // WM
 850         double DisplayPipeRequestDeliveryTimeLuma[DC__NUM_DPP__MAX];
 851         double DisplayPipeRequestDeliveryTimeChroma[DC__NUM_DPP__MAX];
 852         enum clock_change_support DRAMClockChangeSupport[DC__VOLTAGE_STATES][2];
 853         double UrgentBurstFactorCursor[DC__NUM_DPP__MAX];
 854         double UrgentBurstFactorCursorPre[DC__NUM_DPP__MAX];
 855         double UrgentBurstFactorLuma[DC__NUM_DPP__MAX];
 856         double UrgentBurstFactorLumaPre[DC__NUM_DPP__MAX];
 857         double UrgentBurstFactorChroma[DC__NUM_DPP__MAX];
 858         double UrgentBurstFactorChromaPre[DC__NUM_DPP__MAX];
 859
 860
 861         bool           MPCCombine[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 862         double         SwathWidthCSingleDPP[DC__NUM_DPP__MAX];
 863         double         MaximumSwathWidthInLineBufferLuma;
 864         double         MaximumSwathWidthInLineBufferChroma;
 865         double         MaximumSwathWidthLuma[DC__NUM_DPP__MAX];
 866         double         MaximumSwathWidthChroma[DC__NUM_DPP__MAX];
 867         enum odm_combine_mode odm_combine_dummy[DC__NUM_DPP__MAX];
 868         double         dummy1[DC__NUM_DPP__MAX];
 869         double         dummy2[DC__NUM_DPP__MAX];
 870         unsigned int   dummy3[DC__NUM_DPP__MAX];
 871         unsigned int   dummy4[DC__NUM_DPP__MAX];
 872         double         dummy5;
 873         double         dummy6;
 874         double         dummy7[DC__NUM_DPP__MAX];
 875         double         dummy8[DC__NUM_DPP__MAX];
 876         double         dummy13[DC__NUM_DPP__MAX];
 877         double         dummy_double_array[2][DC__NUM_DPP__MAX];
 878         unsigned int        dummyinteger3[DC__NUM_DPP__MAX];
 879         unsigned int        dummyinteger4[DC__NUM_DPP__MAX];
 880         unsigned int        dummyinteger5;
 881         unsigned int        dummyinteger6;
 882         unsigned int        dummyinteger7;
 883         unsigned int        dummyinteger8;
 884         unsigned int        dummyinteger9;
 885         unsigned int        dummyinteger10;
 886         unsigned int        dummyinteger11;
 887         unsigned int        dummy_integer_array[8][DC__NUM_DPP__MAX];
 888
 889         bool           dummysinglestring;
 890         bool           SingleDPPViewportSizeSupportPerPlane[DC__NUM_DPP__MAX];
 891         double         PlaneRequiredDISPCLKWithODMCombine2To1;
 892         double         PlaneRequiredDISPCLKWithODMCombine4To1;
 893         unsigned int   TotalNumberOfSingleDPPPlanes[DC__VOLTAGE_STATES][2];
 894         bool           LinkDSCEnable;
 895         bool           ODMCombine4To1SupportCheckOK[DC__VOLTAGE_STATES];
 896         enum odm_combine_mode ODMCombineEnableThisState[DC__NUM_DPP__MAX];
 897         double   SwathWidthCThisState[DC__NUM_DPP__MAX];
 898         bool           ViewportSizeSupportPerPlane[DC__NUM_DPP__MAX];
 899         double         AlignedDCCMetaPitchY[DC__NUM_DPP__MAX];
 900         double         AlignedDCCMetaPitchC[DC__NUM_DPP__MAX];
 901
 902         unsigned int NotEnoughUrgentLatencyHiding[DC__VOLTAGE_STATES][2];
 903         unsigned int NotEnoughUrgentLatencyHidingPre;
 904         int PTEBufferSizeInRequestsForLuma;
 905         int PTEBufferSizeInRequestsForChroma;
 906
 907         // Missing from VBA
 908         int dpte_group_bytes_chroma;
 909         unsigned int vm_group_bytes_chroma;
 910         double dst_x_after_scaler;
 911         double dst_y_after_scaler;
 912         unsigned int VStartupRequiredWhenNotEnoughTimeForDynamicMetadata;
 913
 914         /* perf locals*/
 915         double PrefetchBandwidth[DC__NUM_DPP__MAX];
 916         double VInitPreFillY[DC__NUM_DPP__MAX];
 917         double VInitPreFillC[DC__NUM_DPP__MAX];
 918         unsigned int MaxNumSwathY[DC__NUM_DPP__MAX];
 919         unsigned int MaxNumSwathC[DC__NUM_DPP__MAX];
 920         unsigned int VStartup[DC__NUM_DPP__MAX];
 921         double DSTYAfterScaler[DC__NUM_DPP__MAX];
 922         double DSTXAfterScaler[DC__NUM_DPP__MAX];
 923         bool AllowDRAMClockChangeDuringVBlank[DC__NUM_DPP__MAX];
 924         bool AllowDRAMSelfRefreshDuringVBlank[DC__NUM_DPP__MAX];
 925         double VRatioPrefetchY[DC__NUM_DPP__MAX];
 926         double VRatioPrefetchC[DC__NUM_DPP__MAX];
 927         double DestinationLinesForPrefetch[DC__NUM_DPP__MAX];
 928         double DestinationLinesToRequestVMInVBlank[DC__NUM_DPP__MAX];
 929         double DestinationLinesToRequestRowInVBlank[DC__NUM_DPP__MAX];
 930         double MinTTUVBlank[DC__NUM_DPP__MAX];
 931         double BytePerPixelDETY[DC__NUM_DPP__MAX];
 932         double BytePerPixelDETC[DC__NUM_DPP__MAX];
 933         double SwathWidthY[DC__NUM_DPP__MAX];
 934         double SwathWidthSingleDPPY[DC__NUM_DPP__MAX];
 935         double CursorRequestDeliveryTime[DC__NUM_DPP__MAX];
 936         double CursorRequestDeliveryTimePrefetch[DC__NUM_DPP__MAX];
 937         double ReadBandwidthPlaneLuma[DC__NUM_DPP__MAX];
 938         double ReadBandwidthPlaneChroma[DC__NUM_DPP__MAX];
 939         double DisplayPipeLineDeliveryTimeLumaPrefetch[DC__NUM_DPP__MAX];
 940         double DisplayPipeLineDeliveryTimeChromaPrefetch[DC__NUM_DPP__MAX];
 941         double DisplayPipeRequestDeliveryTimeLumaPrefetch[DC__NUM_DPP__MAX];
 942         double DisplayPipeRequestDeliveryTimeChromaPrefetch[DC__NUM_DPP__MAX];
 943         double PixelPTEBytesPerRow[DC__NUM_DPP__MAX];
 944         double PDEAndMetaPTEBytesFrame[DC__NUM_DPP__MAX];
 945         double MetaRowByte[DC__NUM_DPP__MAX];
 946         double PrefetchSourceLinesY[DC__NUM_DPP__MAX];
 947         double RequiredPrefetchPixDataBWLuma[DC__NUM_DPP__MAX];
 948         double RequiredPrefetchPixDataBWChroma[DC__NUM_DPP__MAX];
 949         double PrefetchSourceLinesC[DC__NUM_DPP__MAX];
 950         double PSCL_THROUGHPUT_LUMA[DC__NUM_DPP__MAX];
 951         double PSCL_THROUGHPUT_CHROMA[DC__NUM_DPP__MAX];
 952         double DSCCLK_calculated[DC__NUM_DPP__MAX];
 953         unsigned int DSCDelay[DC__NUM_DPP__MAX];
 954         unsigned int MaxVStartupLines[DC__NUM_DPP__MAX];
 955         double DPPCLKUsingSingleDPP[DC__NUM_DPP__MAX];
 956         double DPPCLK[DC__NUM_DPP__MAX];
 957         unsigned int DCCYMaxUncompressedBlock[DC__NUM_DPP__MAX];
 958         unsigned int DCCYMaxCompressedBlock[DC__NUM_DPP__MAX];
 959         unsigned int DCCYIndependent64ByteBlock[DC__NUM_DPP__MAX];
 960         double MaximumDCCCompressionYSurface[DC__NUM_DPP__MAX];
 961         unsigned int BlockHeight256BytesY[DC__NUM_DPP__MAX];
 962         unsigned int BlockHeight256BytesC[DC__NUM_DPP__MAX];
 963         unsigned int BlockWidth256BytesY[DC__NUM_DPP__MAX];
 964         unsigned int BlockWidth256BytesC[DC__NUM_DPP__MAX];
 965         double XFCSlaveVUpdateOffset[DC__NUM_DPP__MAX];
 966         double XFCSlaveVupdateWidth[DC__NUM_DPP__MAX];
 967         double XFCSlaveVReadyOffset[DC__NUM_DPP__MAX];
 968         double XFCTransferDelay[DC__NUM_DPP__MAX];
 969         double XFCPrechargeDelay[DC__NUM_DPP__MAX];
 970         double XFCRemoteSurfaceFlipLatency[DC__NUM_DPP__MAX];
 971         double XFCPrefetchMargin[DC__NUM_DPP__MAX];
 972         unsigned int dpte_row_width_luma_ub[DC__NUM_DPP__MAX];
 973         unsigned int dpte_row_width_chroma_ub[DC__NUM_DPP__MAX];
 974         double FullDETBufferingTimeY[DC__NUM_DPP__MAX];                     // WM
 975         double FullDETBufferingTimeC[DC__NUM_DPP__MAX];                     // WM
 976         double DST_Y_PER_PTE_ROW_NOM_L[DC__NUM_DPP__MAX];
 977         double DST_Y_PER_PTE_ROW_NOM_C[DC__NUM_DPP__MAX];
 978         double DST_Y_PER_META_ROW_NOM_L[DC__NUM_DPP__MAX];
 979         double TimePerMetaChunkNominal[DC__NUM_DPP__MAX];
 980         double TimePerMetaChunkVBlank[DC__NUM_DPP__MAX];
 981         double TimePerMetaChunkFlip[DC__NUM_DPP__MAX];
 982         unsigned int swath_width_luma_ub[DC__NUM_DPP__MAX];
 983         unsigned int swath_width_chroma_ub[DC__NUM_DPP__MAX];
 984         unsigned int PixelPTEReqWidthY[DC__NUM_DPP__MAX];
 985         unsigned int PixelPTEReqHeightY[DC__NUM_DPP__MAX];
 986         unsigned int PTERequestSizeY[DC__NUM_DPP__MAX];
 987         unsigned int PixelPTEReqWidthC[DC__NUM_DPP__MAX];
 988         unsigned int PixelPTEReqHeightC[DC__NUM_DPP__MAX];
 989         unsigned int PTERequestSizeC[DC__NUM_DPP__MAX];
 990         double time_per_pte_group_nom_luma[DC__NUM_DPP__MAX];
 991         double time_per_pte_group_nom_chroma[DC__NUM_DPP__MAX];
 992         double time_per_pte_group_vblank_luma[DC__NUM_DPP__MAX];
 993         double time_per_pte_group_vblank_chroma[DC__NUM_DPP__MAX];
 994         double time_per_pte_group_flip_luma[DC__NUM_DPP__MAX];
 995         double time_per_pte_group_flip_chroma[DC__NUM_DPP__MAX];
 996         double TimePerVMGroupVBlank[DC__NUM_DPP__MAX];
 997         double TimePerVMGroupFlip[DC__NUM_DPP__MAX];
 998         double TimePerVMRequestVBlank[DC__NUM_DPP__MAX];
 999         double TimePerVMRequestFlip[DC__NUM_DPP__MAX];
1000         unsigned int dpde0_bytes_per_frame_ub_l[DC__NUM_DPP__MAX];
1001         unsigned int meta_pte_bytes_per_frame_ub_l[DC__NUM_DPP__MAX];
1002         unsigned int dpde0_bytes_per_frame_ub_c[DC__NUM_DPP__MAX];
1003         unsigned int meta_pte_bytes_per_frame_ub_c[DC__NUM_DPP__MAX];
1004         double LinesToFinishSwathTransferStutterCriticalPlane;
1005         unsigned int BytePerPixelYCriticalPlane;
1006         double SwathWidthYCriticalPlane;
1007         double LinesInDETY[DC__NUM_DPP__MAX];
1008         double LinesInDETYRoundedDownToSwath[DC__NUM_DPP__MAX];
1009
1010         double SwathWidthSingleDPPC[DC__NUM_DPP__MAX];
1011         double SwathWidthC[DC__NUM_DPP__MAX];
1012         unsigned int BytePerPixelY[DC__NUM_DPP__MAX];
1013         unsigned int BytePerPixelC[DC__NUM_DPP__MAX];
1014         unsigned int dummyinteger1;
1015         unsigned int dummyinteger2;
1016         double FinalDRAMClockChangeLatency;
1017         double Tdmdl_vm[DC__NUM_DPP__MAX];
1018         double Tdmdl[DC__NUM_DPP__MAX];
1019         double TSetup[DC__NUM_DPP__MAX];
1020         unsigned int ThisVStartup;
1021         bool WritebackAllowDRAMClockChangeEndPosition[DC__NUM_DPP__MAX];
1022         double DST_Y_PER_META_ROW_NOM_C[DC__NUM_DPP__MAX];
1023         double TimePerChromaMetaChunkNominal[DC__NUM_DPP__MAX];
1024         double TimePerChromaMetaChunkVBlank[DC__NUM_DPP__MAX];
1025         double TimePerChromaMetaChunkFlip[DC__NUM_DPP__MAX];
1026         unsigned int DCCCMaxUncompressedBlock[DC__NUM_DPP__MAX];
1027         unsigned int DCCCMaxCompressedBlock[DC__NUM_DPP__MAX];
1028         double VStartupMargin;
1029         bool NotEnoughTimeForDynamicMetadata[DC__NUM_DPP__MAX];
1030
1031         /* Missing from VBA */
1032         unsigned int MaximumMaxVStartupLines;
1033         double FabricAndDRAMBandwidth;
1034         double LinesInDETLuma;
1035         double LinesInDETChroma;
1036         unsigned int ImmediateFlipBytes[DC__NUM_DPP__MAX];
1037         unsigned int LinesInDETC[DC__NUM_DPP__MAX];
1038         unsigned int LinesInDETCRoundedDownToSwath[DC__NUM_DPP__MAX];
1039         double UrgentLatencySupportUsPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1040         double UrgentLatencySupportUs[DC__NUM_DPP__MAX];
1041         double FabricAndDRAMBandwidthPerState[DC__VOLTAGE_STATES];
1042         bool UrgentLatencySupport[DC__VOLTAGE_STATES][2];
1043         unsigned int SwathWidthYPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1044         unsigned int SwathHeightYPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1045         double qual_row_bw[DC__NUM_DPP__MAX];
1046         double prefetch_row_bw[DC__NUM_DPP__MAX];
1047         double prefetch_vm_bw[DC__NUM_DPP__MAX];
1048
1049         double PTEGroupSize;
1050         unsigned int PDEProcessingBufIn64KBReqs;
1051
1052         double MaxTotalVActiveRDBandwidth;
1053         bool DoUrgentLatencyAdjustment;
1054         double UrgentLatencyAdjustmentFabricClockComponent;
1055         double UrgentLatencyAdjustmentFabricClockReference;
1056         double MinUrgentLatencySupportUs;
1057         double MinFullDETBufferingTime;
1058         double AverageReadBandwidthGBytePerSecond;
1059         bool   FirstMainPlane;
1060
1061         unsigned int ViewportWidthChroma[DC__NUM_DPP__MAX];
1062         unsigned int ViewportHeightChroma[DC__NUM_DPP__MAX];
1063         double HRatioChroma[DC__NUM_DPP__MAX];
1064         double VRatioChroma[DC__NUM_DPP__MAX];
1065         int WritebackSourceWidth[DC__NUM_DPP__MAX];
1066
1067         bool ModeIsSupported;
1068         bool ODMCombine4To1Supported;
1069
1070         unsigned int SurfaceWidthY[DC__NUM_DPP__MAX];
1071         unsigned int SurfaceWidthC[DC__NUM_DPP__MAX];
1072         unsigned int SurfaceHeightY[DC__NUM_DPP__MAX];
1073         unsigned int SurfaceHeightC[DC__NUM_DPP__MAX];
1074         unsigned int WritebackHTaps[DC__NUM_DPP__MAX];
1075         unsigned int WritebackVTaps[DC__NUM_DPP__MAX];
1076         bool DSCEnable[DC__NUM_DPP__MAX];
1077
1078         double DRAMClockChangeLatencyOverride;
1079
1080         double GPUVMMinPageSize;
1081         double HostVMMinPageSize;
1082
1083         bool   MPCCombineEnable[DC__NUM_DPP__MAX];
1084         unsigned int HostVMMaxNonCachedPageTableLevels;
1085         bool   DynamicMetadataVMEnabled;
1086         double       WritebackInterfaceBufferSize;
1087         double       WritebackLineBufferSize;
1088
1089         double DCCRateLuma[DC__NUM_DPP__MAX];
1090         double DCCRateChroma[DC__NUM_DPP__MAX];
1091
1092         double PHYCLKD18PerState[DC__VOLTAGE_STATES];
1093
1094         bool WritebackSupportInterleaveAndUsingWholeBufferForASingleStream;
1095         bool NumberOfHDMIFRLSupport;
1096         unsigned int MaxNumHDMIFRLOutputs;
1097         int    AudioSampleRate[DC__NUM_DPP__MAX];
1098         int    AudioSampleLayout[DC__NUM_DPP__MAX];
1099
1100         int PercentMarginOverMinimumRequiredDCFCLK;
1101         bool DynamicMetadataSupported[DC__VOLTAGE_STATES][2];
1102         enum immediate_flip_requirement ImmediateFlipRequirement[DC__NUM_DPP__MAX];
1103         unsigned int DETBufferSizeYThisState[DC__NUM_DPP__MAX];
1104         unsigned int DETBufferSizeCThisState[DC__NUM_DPP__MAX];
1105         bool NoUrgentLatencyHiding[DC__NUM_DPP__MAX];
1106         bool NoUrgentLatencyHidingPre[DC__NUM_DPP__MAX];
1107         int swath_width_luma_ub_this_state[DC__NUM_DPP__MAX];
1108         int swath_width_chroma_ub_this_state[DC__NUM_DPP__MAX];
1109         double UrgLatency[DC__VOLTAGE_STATES];
1110         double VActiveCursorBandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1111         double VActivePixelBandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1112         bool NoTimeForPrefetch[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1113         bool NoTimeForDynamicMetadata[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1114         double dpte_row_bandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1115         double meta_row_bandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1116         double DETBufferSizeYAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1117         double DETBufferSizeCAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1118         unsigned int swath_width_luma_ub_all_states[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1119         unsigned int swath_width_chroma_ub_all_states[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1120         bool NotUrgentLatencyHiding[DC__VOLTAGE_STATES][2];
1121         unsigned int SwathHeightYAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1122         unsigned int SwathHeightCAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1123         unsigned int SwathWidthYAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1124         unsigned int SwathWidthCAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1125         double TotalDPTERowBandwidth[DC__VOLTAGE_STATES][2];
1126         double TotalMetaRowBandwidth[DC__VOLTAGE_STATES][2];
1127         double TotalVActiveCursorBandwidth[DC__VOLTAGE_STATES][2];
1128         double TotalVActivePixelBandwidth[DC__VOLTAGE_STATES][2];
1129         double WritebackDelayTime[DC__NUM_DPP__MAX];
1130         unsigned int DCCYIndependentBlock[DC__NUM_DPP__MAX];
1131         unsigned int DCCCIndependentBlock[DC__NUM_DPP__MAX];
1132         unsigned int dummyinteger17;
1133         unsigned int dummyinteger18;
1134         unsigned int dummyinteger19;
1135         unsigned int dummyinteger20;
1136         unsigned int dummyinteger21;
1137         unsigned int dummyinteger22;
1138         unsigned int dummyinteger23;
1139         unsigned int dummyinteger24;
1140         unsigned int dummyinteger25;
1141         unsigned int dummyinteger26;
1142         unsigned int dummyinteger27;
1143         unsigned int dummyinteger28;
1144         unsigned int dummyinteger29;
1145         bool dummystring[DC__NUM_DPP__MAX];
1146         double BPP;
1147         enum odm_combine_policy ODMCombinePolicy;
1148         bool UseMinimumRequiredDCFCLK;
1149         bool ClampMinDCFCLK;
1150         bool AllowDramClockChangeOneDisplayVactive;
1151
1152         double MaxAveragePercentOfIdealFabricAndSDPPortBWDisplayCanUseInNormalSystemOperation;
1153         double PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency;
1154         double PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelMixedWithVMData;
1155         double PercentOfIdealDRAMBWReceivedAfterUrgLatencyVMDataOnly;
1156         double PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelDataOnly;
1157         double SRExitZ8Time;
1158         double SREnterPlusExitZ8Time;
1159         double Z8StutterExitWatermark;
1160         double Z8StutterEnterPlusExitWatermark;
1161         double Z8StutterEfficiencyNotIncludingVBlank;
1162         double Z8StutterEfficiency;
1163         double DCCFractionOfZeroSizeRequestsLuma[DC__NUM_DPP__MAX];
1164         double DCCFractionOfZeroSizeRequestsChroma[DC__NUM_DPP__MAX];
1165         double UrgBurstFactorCursor[DC__NUM_DPP__MAX];
1166         double UrgBurstFactorLuma[DC__NUM_DPP__MAX];
1167         double UrgBurstFactorChroma[DC__NUM_DPP__MAX];
1168         double UrgBurstFactorCursorPre[DC__NUM_DPP__MAX];
1169         double UrgBurstFactorLumaPre[DC__NUM_DPP__MAX];
1170         double UrgBurstFactorChromaPre[DC__NUM_DPP__MAX];
1171         bool NotUrgentLatencyHidingPre[DC__NUM_DPP__MAX];
1172         bool LinkCapacitySupport[DC__NUM_DPP__MAX];
1173         bool VREADY_AT_OR_AFTER_VSYNC[DC__NUM_DPP__MAX];
1174         unsigned int MIN_DST_Y_NEXT_START[DC__NUM_DPP__MAX];
1175         unsigned int VFrontPorch[DC__NUM_DPP__MAX];
1176         int ConfigReturnBufferSizeInKByte;
1177         enum unbounded_requesting_policy UseUnboundedRequesting;
1178         int CompressedBufferSegmentSizeInkByte;
1179         int CompressedBufferSizeInkByte;
1180         int MetaFIFOSizeInKEntries;
1181         int ZeroSizeBufferEntries;
1182         int COMPBUF_RESERVED_SPACE_64B;
1183         int COMPBUF_RESERVED_SPACE_ZS;
1184         bool UnboundedRequestEnabled;
1185         bool DSC422NativeSupport;
1186         bool NoEnoughUrgentLatencyHiding;
1187         bool NoEnoughUrgentLatencyHidingPre;
1188         int NumberOfStutterBurstsPerFrame;
1189         int Z8NumberOfStutterBurstsPerFrame;
1190         unsigned int MaximumDSCBitsPerComponent;
1191         unsigned int NotEnoughUrgentLatencyHidingA[DC__VOLTAGE_STATES][2];
1192         double ReadBandwidthSurfaceLuma[DC__NUM_DPP__MAX];
1193         double ReadBandwidthSurfaceChroma[DC__NUM_DPP__MAX];
1194         double SurfaceRequiredDISPCLKWithoutODMCombine;
1195         double SurfaceRequiredDISPCLK;
1196         double MinActiveFCLKChangeLatencySupported;
1197         int MinVoltageLevel;
1198         int MaxVoltageLevel;
1199         unsigned int TotalNumberOfSingleDPPSurfaces[DC__VOLTAGE_STATES][2];
1200         unsigned int CompressedBufferSizeInkByteAllStates[DC__VOLTAGE_STATES][2];
1201         unsigned int DETBufferSizeInKByteAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1202         unsigned int DETBufferSizeInKByteThisState[DC__NUM_DPP__MAX];
1203         unsigned int SurfaceSizeInMALL[DC__NUM_DPP__MAX];
1204         bool ExceededMALLSize;
1205         bool PTE_BUFFER_MODE[DC__NUM_DPP__MAX];
1206         unsigned int BIGK_FRAGMENT_SIZE[DC__NUM_DPP__MAX];
1207         unsigned int CompressedBufferSizeInkByteThisState;
1208         enum dm_fclock_change_support FCLKChangeSupport[DC__VOLTAGE_STATES][2];
1209         bool USRRetrainingSupport[DC__VOLTAGE_STATES][2];
1210         enum dm_use_mall_for_pstate_change_mode UsesMALLForPStateChange[DC__NUM_DPP__MAX];
1211         bool UnboundedRequestEnabledAllStates[DC__VOLTAGE_STATES][2];
1212         bool SingleDPPViewportSizeSupportPerSurface[DC__NUM_DPP__MAX];
1213         enum dm_use_mall_for_static_screen_mode UseMALLForStaticScreen[DC__NUM_DPP__MAX];
1214         bool UnboundedRequestEnabledThisState;
1215         bool DRAMClockChangeRequirementFinal;
1216         bool FCLKChangeRequirementFinal;
1217         bool USRRetrainingRequiredFinal;
1218         unsigned int DETSizeOverride[DC__NUM_DPP__MAX];
1219         unsigned int nomDETInKByte;
1220         enum mpc_combine_affinity  MPCCombineUse[DC__NUM_DPP__MAX];
1221         bool MPCCombineMethodIncompatible;
1222         unsigned int RequiredSlots[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
1223         bool ExceededMultistreamSlots[DC__VOLTAGE_STATES];
1224         enum odm_combine_policy ODMUse[DC__NUM_DPP__MAX];
1225         unsigned int OutputMultistreamId[DC__NUM_DPP__MAX];
1226         bool OutputMultistreamEn[DC__NUM_DPP__MAX];
1227         bool UsesMALLForStaticScreen[DC__NUM_DPP__MAX];
1228         double MaxActiveDRAMClockChangeLatencySupported[DC__NUM_DPP__MAX];
1229         double WritebackAllowFCLKChangeEndPosition[DC__NUM_DPP__MAX];
1230         bool PTEBufferSizeNotExceededPerState[DC__NUM_DPP__MAX]; // new in DML32
1231         bool DCCMetaBufferSizeNotExceededPerState[DC__NUM_DPP__MAX]; // new in DML32
1232         bool NotEnoughDSCSlices[DC__VOLTAGE_STATES];
1233         bool PixelsPerLinePerDSCUnitSupport[DC__VOLTAGE_STATES];
1234         bool DCCMetaBufferSizeNotExceeded[DC__VOLTAGE_STATES][2];
1235         unsigned int dpte_row_height_linear[DC__NUM_DPP__MAX];
1236         unsigned int dpte_row_height_linear_chroma[DC__NUM_DPP__MAX];
1237         unsigned int BlockHeightY[DC__NUM_DPP__MAX];
1238         unsigned int BlockHeightC[DC__NUM_DPP__MAX];
1239         unsigned int BlockWidthY[DC__NUM_DPP__MAX];
1240         unsigned int BlockWidthC[DC__NUM_DPP__MAX];
1241         unsigned int SubViewportLinesNeededInMALL[DC__NUM_DPP__MAX];
1242         bool VActiveBandwithSupport[DC__VOLTAGE_STATES][2];
1243         struct dummy_vars dummy_vars;
1244 };
1245
1246 bool CalculateMinAndMaxPrefetchMode(
1247                 enum self_refresh_affinity AllowDRAMSelfRefreshOrDRAMClockChangeInVblank,
1248                 unsigned int *MinPrefetchMode,
1249                 unsigned int *MaxPrefetchMode);
1250
1251 double CalculateWriteBackDISPCLK(
1252                 enum source_format_class WritebackPixelFormat,
1253                 double PixelClock,
1254                 double WritebackHRatio,
1255                 double WritebackVRatio,
1256                 unsigned int WritebackLumaHTaps,
1257                 unsigned int WritebackLumaVTaps,
1258                 unsigned int WritebackChromaHTaps,
1259                 unsigned int WritebackChromaVTaps,
1260                 double WritebackDestinationWidth,
1261                 unsigned int HTotal,
1262                 unsigned int WritebackChromaLineBufferWidth);
1263
1264 #endif /* _DML2_DISPLAY_MODE_VBA_H_ */