drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 #ifndef __DISPLAY_MODE_STRUCTS_H__
  26 #define __DISPLAY_MODE_STRUCTS_H__
  27
  28 #define MAX_CLOCK_LIMIT_STATES 8
  29
  30 typedef struct _vcs_dpi_voltage_scaling_st voltage_scaling_st;
  31 typedef struct _vcs_dpi_soc_bounding_box_st soc_bounding_box_st;
  32 typedef struct _vcs_dpi_ip_params_st ip_params_st;
  33 typedef struct _vcs_dpi_display_pipe_source_params_st display_pipe_source_params_st;
  34 typedef struct _vcs_dpi_display_output_params_st display_output_params_st;
  35 typedef struct _vcs_dpi_scaler_ratio_depth_st scaler_ratio_depth_st;
  36 typedef struct _vcs_dpi_scaler_taps_st scaler_taps_st;
  37 typedef struct _vcs_dpi_display_pipe_dest_params_st display_pipe_dest_params_st;
  38 typedef struct _vcs_dpi_display_pipe_params_st display_pipe_params_st;
  39 typedef struct _vcs_dpi_display_clocks_and_cfg_st display_clocks_and_cfg_st;
  40 typedef struct _vcs_dpi_display_e2e_pipe_params_st display_e2e_pipe_params_st;
  41 typedef struct _vcs_dpi_display_data_rq_misc_params_st display_data_rq_misc_params_st;
  42 typedef struct _vcs_dpi_display_data_rq_sizing_params_st display_data_rq_sizing_params_st;
  43 typedef struct _vcs_dpi_display_data_rq_dlg_params_st display_data_rq_dlg_params_st;
  44 typedef struct _vcs_dpi_display_rq_dlg_params_st display_rq_dlg_params_st;
  45 typedef struct _vcs_dpi_display_rq_sizing_params_st display_rq_sizing_params_st;
  46 typedef struct _vcs_dpi_display_rq_misc_params_st display_rq_misc_params_st;
  47 typedef struct _vcs_dpi_display_rq_params_st display_rq_params_st;
  48 typedef struct _vcs_dpi_display_dlg_regs_st display_dlg_regs_st;
  49 typedef struct _vcs_dpi_display_ttu_regs_st display_ttu_regs_st;
  50 typedef struct _vcs_dpi_display_data_rq_regs_st display_data_rq_regs_st;
  51 typedef struct _vcs_dpi_display_rq_regs_st display_rq_regs_st;
  52 typedef struct _vcs_dpi_display_dlg_sys_params_st display_dlg_sys_params_st;
  53 typedef struct _vcs_dpi_display_arb_params_st display_arb_params_st;
  54
  55 struct _vcs_dpi_voltage_scaling_st {
  56         int state;
  57         double dscclk_mhz;
  58         double dcfclk_mhz;
  59         double socclk_mhz;
  60         double phyclk_d18_mhz;
  61         double dram_speed_mts;
  62         double fabricclk_mhz;
  63         double dispclk_mhz;
  64         double phyclk_mhz;
  65         double dppclk_mhz;
  66 };
  67
  68 struct _vcs_dpi_soc_bounding_box_st {
  69         double sr_exit_time_us;
  70         double sr_enter_plus_exit_time_us;
  71         double urgent_latency_us;
  72         double urgent_latency_pixel_data_only_us;
  73         double urgent_latency_pixel_mixed_with_vm_data_us;
  74         double urgent_latency_vm_data_only_us;
  75         double writeback_latency_us;
  76         double ideal_dram_bw_after_urgent_percent;
  77         double pct_ideal_dram_sdp_bw_after_urgent_pixel_only; // PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly
  78         double pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm;
  79         double pct_ideal_dram_sdp_bw_after_urgent_vm_only;
  80         double max_avg_sdp_bw_use_normal_percent;
  81         double max_avg_dram_bw_use_normal_percent;
  82         unsigned int max_request_size_bytes;
  83         double downspread_percent;
  84         double dram_page_open_time_ns;
  85         double dram_rw_turnaround_time_ns;
  86         double dram_return_buffer_per_channel_bytes;
  87         double dram_channel_width_bytes;
  88         double fabric_datapath_to_dcn_data_return_bytes;
  89         double dcn_downspread_percent;
  90         double dispclk_dppclk_vco_speed_mhz;
  91         double dfs_vco_period_ps;
  92         unsigned int urgent_out_of_order_return_per_channel_pixel_only_bytes;
  93         unsigned int urgent_out_of_order_return_per_channel_pixel_and_vm_bytes;
  94         unsigned int urgent_out_of_order_return_per_channel_vm_only_bytes;
  95         unsigned int round_trip_ping_latency_dcfclk_cycles;
  96         unsigned int urgent_out_of_order_return_per_channel_bytes;
  97         unsigned int channel_interleave_bytes;
  98         unsigned int num_banks;
  99         unsigned int num_chans;
 100         unsigned int vmm_page_size_bytes;
 101         unsigned int hostvm_min_page_size_bytes;
 102         unsigned int gpuvm_min_page_size_bytes;
 103         double dram_clock_change_latency_us;
 104         double dummy_pstate_latency_us;
 105         double writeback_dram_clock_change_latency_us;
 106         unsigned int return_bus_width_bytes;
 107         unsigned int voltage_override;
 108         double xfc_bus_transport_time_us;
 109         double xfc_xbuf_latency_tolerance_us;
 110         int use_urgent_burst_bw;
 111         unsigned int num_states;
 112         struct _vcs_dpi_voltage_scaling_st clock_limits[MAX_CLOCK_LIMIT_STATES];
 113         bool do_urgent_latency_adjustment;
 114         double urgent_latency_adjustment_fabric_clock_component_us;
 115         double urgent_latency_adjustment_fabric_clock_reference_mhz;
 116         bool disable_dram_clock_change_vactive_support;
 117 };
 118
 119 struct _vcs_dpi_ip_params_st {
 120         bool gpuvm_enable;
 121         bool hostvm_enable;
 122         unsigned int gpuvm_max_page_table_levels;
 123         unsigned int hostvm_max_page_table_levels;
 124         unsigned int hostvm_cached_page_table_levels;
 125         unsigned int pte_group_size_bytes;
 126         unsigned int max_inter_dcn_tile_repeaters;
 127         unsigned int num_dsc;
 128         unsigned int odm_capable;
 129         unsigned int rob_buffer_size_kbytes;
 130         unsigned int det_buffer_size_kbytes;
 131         unsigned int dpte_buffer_size_in_pte_reqs_luma;
 132         unsigned int dpte_buffer_size_in_pte_reqs_chroma;
 133         unsigned int pde_proc_buffer_size_64k_reqs;
 134         unsigned int dpp_output_buffer_pixels;
 135         unsigned int opp_output_buffer_lines;
 136         unsigned int pixel_chunk_size_kbytes;
 137         unsigned char pte_enable;
 138         unsigned int pte_chunk_size_kbytes;
 139         unsigned int meta_chunk_size_kbytes;
 140         unsigned int writeback_chunk_size_kbytes;
 141         unsigned int line_buffer_size_bits;
 142         unsigned int max_line_buffer_lines;
 143         unsigned int writeback_luma_buffer_size_kbytes;
 144         unsigned int writeback_chroma_buffer_size_kbytes;
 145         unsigned int writeback_chroma_line_buffer_width_pixels;
 146
 147         unsigned int writeback_interface_buffer_size_kbytes;
 148         unsigned int writeback_line_buffer_buffer_size;
 149
 150         unsigned int writeback_10bpc420_supported;
 151         double writeback_max_hscl_ratio;
 152         double writeback_max_vscl_ratio;
 153         double writeback_min_hscl_ratio;
 154         double writeback_min_vscl_ratio;
 155         unsigned int writeback_max_hscl_taps;
 156         unsigned int writeback_max_vscl_taps;
 157         unsigned int writeback_line_buffer_luma_buffer_size;
 158         unsigned int writeback_line_buffer_chroma_buffer_size;
 159
 160         unsigned int max_page_table_levels;
 161         unsigned int max_num_dpp;
 162         unsigned int max_num_otg;
 163         unsigned int cursor_chunk_size;
 164         unsigned int cursor_buffer_size;
 165         unsigned int max_num_wb;
 166         unsigned int max_dchub_pscl_bw_pix_per_clk;
 167         unsigned int max_pscl_lb_bw_pix_per_clk;
 168         unsigned int max_lb_vscl_bw_pix_per_clk;
 169         unsigned int max_vscl_hscl_bw_pix_per_clk;
 170         double max_hscl_ratio;
 171         double max_vscl_ratio;
 172         unsigned int hscl_mults;
 173         unsigned int vscl_mults;
 174         unsigned int max_hscl_taps;
 175         unsigned int max_vscl_taps;
 176         unsigned int xfc_supported;
 177         unsigned int ptoi_supported;
 178         unsigned int gfx7_compat_tiling_supported;
 179
 180         bool odm_combine_4to1_supported;
 181         bool dynamic_metadata_vm_enabled;
 182         unsigned int max_num_hdmi_frl_outputs;
 183
 184         unsigned int xfc_fill_constant_bytes;
 185         double dispclk_ramp_margin_percent;
 186         double xfc_fill_bw_overhead_percent;
 187         double underscan_factor;
 188         unsigned int min_vblank_lines;
 189         unsigned int dppclk_delay_subtotal;
 190         unsigned int dispclk_delay_subtotal;
 191         unsigned int dcfclk_cstate_latency;
 192         unsigned int dppclk_delay_scl;
 193         unsigned int dppclk_delay_scl_lb_only;
 194         unsigned int dppclk_delay_cnvc_formatter;
 195         unsigned int dppclk_delay_cnvc_cursor;
 196         unsigned int is_line_buffer_bpp_fixed;
 197         unsigned int line_buffer_fixed_bpp;
 198         unsigned int dcc_supported;
 199
 200         unsigned int IsLineBufferBppFixed;
 201         unsigned int LineBufferFixedBpp;
 202         unsigned int can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one;
 203         unsigned int bug_forcing_LC_req_same_size_fixed;
 204 };
 205
 206 struct _vcs_dpi_display_xfc_params_st {
 207         double xfc_tslv_vready_offset_us;
 208         double xfc_tslv_vupdate_width_us;
 209         double xfc_tslv_vupdate_offset_us;
 210         int xfc_slv_chunk_size_bytes;
 211 };
 212
 213 struct _vcs_dpi_display_pipe_source_params_st {
 214         int source_format;
 215         unsigned char dcc;
 216         unsigned int dcc_rate;
 217         unsigned char dcc_use_global;
 218         unsigned char vm;
 219         bool gpuvm;    // gpuvm enabled
 220         bool hostvm;    // hostvm enabled
 221         bool gpuvm_levels_force_en;
 222         unsigned int gpuvm_levels_force;
 223         bool hostvm_levels_force_en;
 224         unsigned int hostvm_levels_force;
 225         int source_scan;
 226         int sw_mode;
 227         int macro_tile_size;
 228         unsigned int surface_height_y;
 229         unsigned int viewport_width;
 230         unsigned int viewport_height;
 231         unsigned int viewport_y_y;
 232         unsigned int viewport_y_c;
 233         unsigned int viewport_width_c;
 234         unsigned int viewport_height_c;
 235         unsigned int data_pitch;
 236         unsigned int data_pitch_c;
 237         unsigned int meta_pitch;
 238         unsigned int meta_pitch_c;
 239         unsigned int cur0_src_width;
 240         int cur0_bpp;
 241         unsigned int cur1_src_width;
 242         int cur1_bpp;
 243         int num_cursors;
 244         unsigned char is_hsplit;
 245         unsigned char dynamic_metadata_enable;
 246         unsigned int dynamic_metadata_lines_before_active;
 247         unsigned int dynamic_metadata_xmit_bytes;
 248         unsigned int hsplit_grp;
 249         unsigned char xfc_enable;
 250         unsigned char xfc_slave;
 251         unsigned char immediate_flip;
 252         struct _vcs_dpi_display_xfc_params_st xfc_params;
 253         //for vstartuplines calculation freesync
 254         unsigned char v_total_min;
 255         unsigned char v_total_max;
 256 };
 257 struct writeback_st {
 258         int wb_src_height;
 259         int wb_src_width;
 260         int wb_dst_width;
 261         int wb_dst_height;
 262         int wb_pixel_format;
 263         int wb_htaps_luma;
 264         int wb_vtaps_luma;
 265         int wb_htaps_chroma;
 266         int wb_vtaps_chroma;
 267         double wb_hratio;
 268         double wb_vratio;
 269 };
 270
 271 struct _vcs_dpi_display_output_params_st {
 272         int dp_lanes;
 273         double output_bpp;
 274         int dsc_enable;
 275         int wb_enable;
 276         int num_active_wb;
 277         int output_bpc;
 278         int output_type;
 279         int output_format;
 280         int dsc_slices;
 281         int max_audio_sample_rate;
 282         struct writeback_st wb;
 283 };
 284
 285 struct _vcs_dpi_scaler_ratio_depth_st {
 286         double hscl_ratio;
 287         double vscl_ratio;
 288         double hscl_ratio_c;
 289         double vscl_ratio_c;
 290         double vinit;
 291         double vinit_c;
 292         double vinit_bot;
 293         double vinit_bot_c;
 294         int lb_depth;
 295         int scl_enable;
 296 };
 297
 298 struct _vcs_dpi_scaler_taps_st {
 299         unsigned int htaps;
 300         unsigned int vtaps;
 301         unsigned int htaps_c;
 302         unsigned int vtaps_c;
 303 };
 304
 305 struct _vcs_dpi_display_pipe_dest_params_st {
 306         unsigned int recout_width;
 307         unsigned int recout_height;
 308         unsigned int full_recout_width;
 309         unsigned int full_recout_height;
 310         unsigned int hblank_start;
 311         unsigned int hblank_end;
 312         unsigned int vblank_start;
 313         unsigned int vblank_end;
 314         unsigned int htotal;
 315         unsigned int vtotal;
 316         unsigned int vactive;
 317         unsigned int hactive;
 318         unsigned int vstartup_start;
 319         unsigned int vupdate_offset;
 320         unsigned int vupdate_width;
 321         unsigned int vready_offset;
 322         unsigned char interlaced;
 323         unsigned char embedded;
 324         double pixel_rate_mhz;
 325         unsigned char synchronized_vblank_all_planes;
 326         unsigned char otg_inst;
 327         unsigned char odm_combine;
 328         unsigned char use_maximum_vstartup;
 329         unsigned int vtotal_max;
 330         unsigned int vtotal_min;
 331 };
 332
 333 struct _vcs_dpi_display_pipe_params_st {
 334         display_pipe_source_params_st src;
 335         display_pipe_dest_params_st dest;
 336         scaler_ratio_depth_st scale_ratio_depth;
 337         scaler_taps_st scale_taps;
 338 };
 339
 340 struct _vcs_dpi_display_clocks_and_cfg_st {
 341         int voltage;
 342         double dppclk_mhz;
 343         double refclk_mhz;
 344         double dispclk_mhz;
 345         double dcfclk_mhz;
 346         double socclk_mhz;
 347 };
 348
 349 struct _vcs_dpi_display_e2e_pipe_params_st {
 350         display_pipe_params_st pipe;
 351         display_output_params_st dout;
 352         display_clocks_and_cfg_st clks_cfg;
 353 };
 354
 355 struct _vcs_dpi_display_data_rq_misc_params_st {
 356         unsigned int full_swath_bytes;
 357         unsigned int stored_swath_bytes;
 358         unsigned int blk256_height;
 359         unsigned int blk256_width;
 360         unsigned int req_height;
 361         unsigned int req_width;
 362 };
 363
 364 struct _vcs_dpi_display_data_rq_sizing_params_st {
 365         unsigned int chunk_bytes;
 366         unsigned int min_chunk_bytes;
 367         unsigned int meta_chunk_bytes;
 368         unsigned int min_meta_chunk_bytes;
 369         unsigned int mpte_group_bytes;
 370         unsigned int dpte_group_bytes;
 371 };
 372
 373 struct _vcs_dpi_display_data_rq_dlg_params_st {
 374         unsigned int swath_width_ub;
 375         unsigned int swath_height;
 376         unsigned int req_per_swath_ub;
 377         unsigned int meta_pte_bytes_per_frame_ub;
 378         unsigned int dpte_req_per_row_ub;
 379         unsigned int dpte_groups_per_row_ub;
 380         unsigned int dpte_row_height;
 381         unsigned int dpte_bytes_per_row_ub;
 382         unsigned int meta_chunks_per_row_ub;
 383         unsigned int meta_req_per_row_ub;
 384         unsigned int meta_row_height;
 385         unsigned int meta_bytes_per_row_ub;
 386 };
 387
 388 struct _vcs_dpi_display_rq_dlg_params_st {
 389         display_data_rq_dlg_params_st rq_l;
 390         display_data_rq_dlg_params_st rq_c;
 391 };
 392
 393 struct _vcs_dpi_display_rq_sizing_params_st {
 394         display_data_rq_sizing_params_st rq_l;
 395         display_data_rq_sizing_params_st rq_c;
 396 };
 397
 398 struct _vcs_dpi_display_rq_misc_params_st {
 399         display_data_rq_misc_params_st rq_l;
 400         display_data_rq_misc_params_st rq_c;
 401 };
 402
 403 struct _vcs_dpi_display_rq_params_st {
 404         unsigned char yuv420;
 405         unsigned char yuv420_10bpc;
 406         unsigned char rgbe_alpha;
 407         display_rq_misc_params_st misc;
 408         display_rq_sizing_params_st sizing;
 409         display_rq_dlg_params_st dlg;
 410 };
 411
 412 struct _vcs_dpi_display_dlg_regs_st {
 413         unsigned int refcyc_h_blank_end;
 414         unsigned int dlg_vblank_end;
 415         unsigned int min_dst_y_next_start;
 416         unsigned int refcyc_per_htotal;
 417         unsigned int refcyc_x_after_scaler;
 418         unsigned int dst_y_after_scaler;
 419         unsigned int dst_y_prefetch;
 420         unsigned int dst_y_per_vm_vblank;
 421         unsigned int dst_y_per_row_vblank;
 422         unsigned int dst_y_per_vm_flip;
 423         unsigned int dst_y_per_row_flip;
 424         unsigned int ref_freq_to_pix_freq;
 425         unsigned int vratio_prefetch;
 426         unsigned int vratio_prefetch_c;
 427         unsigned int refcyc_per_pte_group_vblank_l;
 428         unsigned int refcyc_per_pte_group_vblank_c;
 429         unsigned int refcyc_per_meta_chunk_vblank_l;
 430         unsigned int refcyc_per_meta_chunk_vblank_c;
 431         unsigned int refcyc_per_pte_group_flip_l;
 432         unsigned int refcyc_per_pte_group_flip_c;
 433         unsigned int refcyc_per_meta_chunk_flip_l;
 434         unsigned int refcyc_per_meta_chunk_flip_c;
 435         unsigned int dst_y_per_pte_row_nom_l;
 436         unsigned int dst_y_per_pte_row_nom_c;
 437         unsigned int refcyc_per_pte_group_nom_l;
 438         unsigned int refcyc_per_pte_group_nom_c;
 439         unsigned int dst_y_per_meta_row_nom_l;
 440         unsigned int dst_y_per_meta_row_nom_c;
 441         unsigned int refcyc_per_meta_chunk_nom_l;
 442         unsigned int refcyc_per_meta_chunk_nom_c;
 443         unsigned int refcyc_per_line_delivery_pre_l;
 444         unsigned int refcyc_per_line_delivery_pre_c;
 445         unsigned int refcyc_per_line_delivery_l;
 446         unsigned int refcyc_per_line_delivery_c;
 447         unsigned int chunk_hdl_adjust_cur0;
 448         unsigned int chunk_hdl_adjust_cur1;
 449         unsigned int vready_after_vcount0;
 450         unsigned int dst_y_offset_cur0;
 451         unsigned int dst_y_offset_cur1;
 452         unsigned int xfc_reg_transfer_delay;
 453         unsigned int xfc_reg_precharge_delay;
 454         unsigned int xfc_reg_remote_surface_flip_latency;
 455         unsigned int xfc_reg_prefetch_margin;
 456         unsigned int dst_y_delta_drq_limit;
 457         unsigned int refcyc_per_vm_group_vblank;
 458         unsigned int refcyc_per_vm_group_flip;
 459         unsigned int refcyc_per_vm_req_vblank;
 460         unsigned int refcyc_per_vm_req_flip;
 461         unsigned int refcyc_per_vm_dmdata;
 462 };
 463
 464 struct _vcs_dpi_display_ttu_regs_st {
 465         unsigned int qos_level_low_wm;
 466         unsigned int qos_level_high_wm;
 467         unsigned int min_ttu_vblank;
 468         unsigned int qos_level_flip;
 469         unsigned int refcyc_per_req_delivery_l;
 470         unsigned int refcyc_per_req_delivery_c;
 471         unsigned int refcyc_per_req_delivery_cur0;
 472         unsigned int refcyc_per_req_delivery_cur1;
 473         unsigned int refcyc_per_req_delivery_pre_l;
 474         unsigned int refcyc_per_req_delivery_pre_c;
 475         unsigned int refcyc_per_req_delivery_pre_cur0;
 476         unsigned int refcyc_per_req_delivery_pre_cur1;
 477         unsigned int qos_level_fixed_l;
 478         unsigned int qos_level_fixed_c;
 479         unsigned int qos_level_fixed_cur0;
 480         unsigned int qos_level_fixed_cur1;
 481         unsigned int qos_ramp_disable_l;
 482         unsigned int qos_ramp_disable_c;
 483         unsigned int qos_ramp_disable_cur0;
 484         unsigned int qos_ramp_disable_cur1;
 485 };
 486
 487 struct _vcs_dpi_display_data_rq_regs_st {
 488         unsigned int chunk_size;
 489         unsigned int min_chunk_size;
 490         unsigned int meta_chunk_size;
 491         unsigned int min_meta_chunk_size;
 492         unsigned int dpte_group_size;
 493         unsigned int mpte_group_size;
 494         unsigned int swath_height;
 495         unsigned int pte_row_height_linear;
 496 };
 497
 498 struct _vcs_dpi_display_rq_regs_st {
 499         display_data_rq_regs_st rq_regs_l;
 500         display_data_rq_regs_st rq_regs_c;
 501         unsigned int drq_expansion_mode;
 502         unsigned int prq_expansion_mode;
 503         unsigned int mrq_expansion_mode;
 504         unsigned int crq_expansion_mode;
 505         unsigned int plane1_base_address;
 506 };
 507
 508 struct _vcs_dpi_display_dlg_sys_params_st {
 509         double t_mclk_wm_us;
 510         double t_urg_wm_us;
 511         double t_sr_wm_us;
 512         double t_extra_us;
 513         double mem_trip_us;
 514         double t_srx_delay_us;
 515         double deepsleep_dcfclk_mhz;
 516         double total_flip_bw;
 517         unsigned int total_flip_bytes;
 518 };
 519
 520 struct _vcs_dpi_display_arb_params_st {
 521         int max_req_outstanding;
 522         int min_req_outstanding;
 523         int sat_level_us;
 524 };
 525
 526 #endif /*__DISPLAY_MODE_STRUCTS_H__*/