drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright 2022 Advanced Micro Devices, Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: AMD
  24  *
  25  */
  26 #include "dcn32_fpu.h"
  27 #include "dcn32/dcn32_resource.h"
  28 #include "dcn20/dcn20_resource.h"
  29 #include "display_mode_vba_util_32.h"
  30 // We need this includes for WATERMARKS_* defines
  31 #include "clk_mgr/dcn32/dcn32_smu13_driver_if.h"
  32
  33 struct _vcs_dpi_ip_params_st dcn3_2_ip = {
  34         .gpuvm_enable = 0,
  35         .gpuvm_max_page_table_levels = 4,
  36         .hostvm_enable = 0,
  37         .rob_buffer_size_kbytes = 128,
  38         .det_buffer_size_kbytes = DCN3_2_DEFAULT_DET_SIZE,
  39         .config_return_buffer_size_in_kbytes = 1280,
  40         .compressed_buffer_segment_size_in_kbytes = 64,
  41         .meta_fifo_size_in_kentries = 22,
  42         .zero_size_buffer_entries = 512,
  43         .compbuf_reserved_space_64b = 256,
  44         .compbuf_reserved_space_zs = 64,
  45         .dpp_output_buffer_pixels = 2560,
  46         .opp_output_buffer_lines = 1,
  47         .pixel_chunk_size_kbytes = 8,
  48         .alpha_pixel_chunk_size_kbytes = 4,
  49         .min_pixel_chunk_size_bytes = 1024,
  50         .dcc_meta_buffer_size_bytes = 6272,
  51         .meta_chunk_size_kbytes = 2,
  52         .min_meta_chunk_size_bytes = 256,
  53         .writeback_chunk_size_kbytes = 8,
  54         .ptoi_supported = false,
  55         .num_dsc = 4,
  56         .maximum_dsc_bits_per_component = 12,
  57         .maximum_pixels_per_line_per_dsc_unit = 6016,
  58         .dsc422_native_support = true,
  59         .is_line_buffer_bpp_fixed = true,
  60         .line_buffer_fixed_bpp = 57,
  61         .line_buffer_size_bits = 1171920,
  62         .max_line_buffer_lines = 32,
  63         .writeback_interface_buffer_size_kbytes = 90,
  64         .max_num_dpp = 4,
  65         .max_num_otg = 4,
  66         .max_num_hdmi_frl_outputs = 1,
  67         .max_num_wb = 1,
  68         .max_dchub_pscl_bw_pix_per_clk = 4,
  69         .max_pscl_lb_bw_pix_per_clk = 2,
  70         .max_lb_vscl_bw_pix_per_clk = 4,
  71         .max_vscl_hscl_bw_pix_per_clk = 4,
  72         .max_hscl_ratio = 6,
  73         .max_vscl_ratio = 6,
  74         .max_hscl_taps = 8,
  75         .max_vscl_taps = 8,
  76         .dpte_buffer_size_in_pte_reqs_luma = 64,
  77         .dpte_buffer_size_in_pte_reqs_chroma = 34,
  78         .dispclk_ramp_margin_percent = 1,
  79         .max_inter_dcn_tile_repeaters = 8,
  80         .cursor_buffer_size = 16,
  81         .cursor_chunk_size = 2,
  82         .writeback_line_buffer_buffer_size = 0,
  83         .writeback_min_hscl_ratio = 1,
  84         .writeback_min_vscl_ratio = 1,
  85         .writeback_max_hscl_ratio = 1,
  86         .writeback_max_vscl_ratio = 1,
  87         .writeback_max_hscl_taps = 1,
  88         .writeback_max_vscl_taps = 1,
  89         .dppclk_delay_subtotal = 47,
  90         .dppclk_delay_scl = 50,
  91         .dppclk_delay_scl_lb_only = 16,
  92         .dppclk_delay_cnvc_formatter = 28,
  93         .dppclk_delay_cnvc_cursor = 6,
  94         .dispclk_delay_subtotal = 125,
  95         .dynamic_metadata_vm_enabled = false,
  96         .odm_combine_4to1_supported = false,
  97         .dcc_supported = true,
  98         .max_num_dp2p0_outputs = 2,
  99         .max_num_dp2p0_streams = 4,
 100 };
 101
 102 struct _vcs_dpi_soc_bounding_box_st dcn3_2_soc = {
 103         .clock_limits = {
 104                 {
 105                         .state = 0,
 106                         .dcfclk_mhz = 1564.0,
 107                         .fabricclk_mhz = 400.0,
 108                         .dispclk_mhz = 2150.0,
 109                         .dppclk_mhz = 2150.0,
 110                         .phyclk_mhz = 810.0,
 111                         .phyclk_d18_mhz = 667.0,
 112                         .phyclk_d32_mhz = 625.0,
 113                         .socclk_mhz = 1200.0,
 114                         .dscclk_mhz = 716.667,
 115                         .dram_speed_mts = 16000.0,
 116                         .dtbclk_mhz = 1564.0,
 117                 },
 118         },
 119         .num_states = 1,
 120         .sr_exit_time_us = 5.20,
 121         .sr_enter_plus_exit_time_us = 9.60,
 122         .sr_exit_z8_time_us = 285.0,
 123         .sr_enter_plus_exit_z8_time_us = 320,
 124         .writeback_latency_us = 12.0,
 125         .round_trip_ping_latency_dcfclk_cycles = 263,
 126         .urgent_latency_pixel_data_only_us = 4.0,
 127         .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
 128         .urgent_latency_vm_data_only_us = 4.0,
 129         .fclk_change_latency_us = 20,
 130         .usr_retraining_latency_us = 2,
 131         .smn_latency_us = 2,
 132         .mall_allocated_for_dcn_mbytes = 64,
 133         .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
 134         .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
 135         .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
 136         .pct_ideal_sdp_bw_after_urgent = 100.0,
 137         .pct_ideal_fabric_bw_after_urgent = 67.0,
 138         .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 20.0,
 139         .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0, // N/A, for now keep as is until DML implemented
 140         .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0, // N/A, for now keep as is until DML implemented
 141         .pct_ideal_dram_bw_after_urgent_strobe = 67.0,
 142         .max_avg_sdp_bw_use_normal_percent = 80.0,
 143         .max_avg_fabric_bw_use_normal_percent = 60.0,
 144         .max_avg_dram_bw_use_normal_strobe_percent = 50.0,
 145         .max_avg_dram_bw_use_normal_percent = 15.0,
 146         .num_chans = 8,
 147         .dram_channel_width_bytes = 2,
 148         .fabric_datapath_to_dcn_data_return_bytes = 64,
 149         .return_bus_width_bytes = 64,
 150         .downspread_percent = 0.38,
 151         .dcn_downspread_percent = 0.5,
 152         .dram_clock_change_latency_us = 400,
 153         .dispclk_dppclk_vco_speed_mhz = 4300.0,
 154         .do_urgent_latency_adjustment = true,
 155         .urgent_latency_adjustment_fabric_clock_component_us = 1.0,
 156         .urgent_latency_adjustment_fabric_clock_reference_mhz = 1000,
 157 };
 158
 159 void dcn32_build_wm_range_table_fpu(struct clk_mgr_internal *clk_mgr)
 160 {
 161         /* defaults */
 162         double pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dram_clock_change_latency_us;
 163         double fclk_change_latency_us = clk_mgr->base.ctx->dc->dml.soc.fclk_change_latency_us;
 164         double sr_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_exit_time_us;
 165         double sr_enter_plus_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_enter_plus_exit_time_us;
 166         /* For min clocks use as reported by PM FW and report those as min */
 167         uint16_t min_uclk_mhz                   = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz;
 168         uint16_t min_dcfclk_mhz                 = clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz;
 169         uint16_t setb_min_uclk_mhz              = min_uclk_mhz;
 170         uint16_t dcfclk_mhz_for_the_second_state = clk_mgr->base.ctx->dc->dml.soc.clock_limits[2].dcfclk_mhz;
 171
 172         dc_assert_fp_enabled();
 173
 174         /* For Set B ranges use min clocks state 2 when available, and report those to PM FW */
 175         if (dcfclk_mhz_for_the_second_state)
 176                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = dcfclk_mhz_for_the_second_state;
 177         else
 178                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz;
 179
 180         if (clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz)
 181                 setb_min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz;
 182
 183         /* Set A - Normal - default values */
 184         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].valid = true;
 185         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us = pstate_latency_us;
 186         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us = fclk_change_latency_us;
 187         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us = sr_exit_time_us;
 188         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;
 189         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE;
 190         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;
 191         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF;
 192         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = min_uclk_mhz;
 193         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 0xFFFF;
 194
 195         /* Set B - Performance - higher clocks, using DPM[2] DCFCLK and UCLK */
 196         clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].valid = true;
 197         clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us = pstate_latency_us;
 198         clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.fclk_change_latency_us = fclk_change_latency_us;
 199         clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us = sr_exit_time_us;
 200         clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;
 201         clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE;
 202         clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_dcfclk = 0xFFFF;
 203         clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_uclk = setb_min_uclk_mhz;
 204         clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_uclk = 0xFFFF;
 205
 206         /* Set C - Dummy P-State - P-State latency set to "dummy p-state" value */
 207         /* 'DalDummyClockChangeLatencyNs' registry key option set to 0x7FFFFFFF can be used to disable Set C for dummy p-state */
 208         if (clk_mgr->base.ctx->dc->bb_overrides.dummy_clock_change_latency_ns != 0x7FFFFFFF) {
 209                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].valid = true;
 210                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us = 38;
 211                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.fclk_change_latency_us = fclk_change_latency_us;
 212                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us = sr_exit_time_us;
 213                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;
 214                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.wm_type = WATERMARKS_DUMMY_PSTATE;
 215                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;
 216                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_dcfclk = 0xFFFF;
 217                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_uclk = min_uclk_mhz;
 218                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_uclk = 0xFFFF;
 219                 clk_mgr->base.bw_params->dummy_pstate_table[0].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz * 16;
 220                 clk_mgr->base.bw_params->dummy_pstate_table[0].dummy_pstate_latency_us = 38;
 221                 clk_mgr->base.bw_params->dummy_pstate_table[1].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[1].memclk_mhz * 16;
 222                 clk_mgr->base.bw_params->dummy_pstate_table[1].dummy_pstate_latency_us = 9;
 223                 clk_mgr->base.bw_params->dummy_pstate_table[2].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz * 16;
 224                 clk_mgr->base.bw_params->dummy_pstate_table[2].dummy_pstate_latency_us = 8;
 225                 clk_mgr->base.bw_params->dummy_pstate_table[3].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[3].memclk_mhz * 16;
 226                 clk_mgr->base.bw_params->dummy_pstate_table[3].dummy_pstate_latency_us = 5;
 227         }
 228         /* Set D - MALL - SR enter and exit time specific to MALL, TBD after bringup or later phase for now use DRAM values / 2 */
 229         /* For MALL DRAM clock change latency is N/A, for watermak calculations use lowest value dummy P state latency */
 230         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].valid = true;
 231         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us = clk_mgr->base.bw_params->dummy_pstate_table[3].dummy_pstate_latency_us;
 232         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.fclk_change_latency_us = fclk_change_latency_us;
 233         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us = sr_exit_time_us / 2; // TBD
 234         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us / 2; // TBD
 235         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.wm_type = WATERMARKS_MALL;
 236         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;
 237         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_dcfclk = 0xFFFF;
 238         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_uclk = min_uclk_mhz;
 239         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_uclk = 0xFFFF;
 240 }
 241
 242 /**
 243  * dcn32_helper_populate_phantom_dlg_params - Get DLG params for phantom pipes
 244  * and populate pipe_ctx with those params.
 245  *
 246  * This function must be called AFTER the phantom pipes are added to context
 247  * and run through DML (so that the DLG params for the phantom pipes can be
 248  * populated), and BEFORE we program the timing for the phantom pipes.
 249  *
 250  * @dc: [in] current dc state
 251  * @context: [in] new dc state
 252  * @pipes: [in] DML pipe params array
 253  * @pipe_cnt: [in] DML pipe count
 254  */
 255 void dcn32_helper_populate_phantom_dlg_params(struct dc *dc,
 256                                               struct dc_state *context,
 257                                               display_e2e_pipe_params_st *pipes,
 258                                               int pipe_cnt)
 259 {
 260         uint32_t i, pipe_idx;
 261
 262         dc_assert_fp_enabled();
 263
 264         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
 265                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 266
 267                 if (!pipe->stream)
 268                         continue;
 269
 270                 if (pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) {
 271                         pipes[pipe_idx].pipe.dest.vstartup_start =
 272                                 get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
 273                         pipes[pipe_idx].pipe.dest.vupdate_offset =
 274                                 get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
 275                         pipes[pipe_idx].pipe.dest.vupdate_width =
 276                                 get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
 277                         pipes[pipe_idx].pipe.dest.vready_offset =
 278                                 get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
 279                         pipe->pipe_dlg_param = pipes[pipe_idx].pipe.dest;
 280                 }
 281                 pipe_idx++;
 282         }
 283 }
 284
 285 bool dcn32_predict_pipe_split(struct dc_state *context, display_pipe_params_st pipe, int index)
 286 {
 287         double pscl_throughput;
 288         double pscl_throughput_chroma;
 289         double dpp_clk_single_dpp, clock;
 290         double clk_frequency = 0.0;
 291         double vco_speed = context->bw_ctx.dml.soc.dispclk_dppclk_vco_speed_mhz;
 292
 293         dc_assert_fp_enabled();
 294
 295         dml32_CalculateSinglePipeDPPCLKAndSCLThroughput(pipe.scale_ratio_depth.hscl_ratio,
 296                                                         pipe.scale_ratio_depth.hscl_ratio_c,
 297                                                         pipe.scale_ratio_depth.vscl_ratio,
 298                                                         pipe.scale_ratio_depth.vscl_ratio_c,
 299                                                         context->bw_ctx.dml.ip.max_dchub_pscl_bw_pix_per_clk,
 300                                                         context->bw_ctx.dml.ip.max_pscl_lb_bw_pix_per_clk,
 301                                                         pipe.dest.pixel_rate_mhz,
 302                                                         pipe.src.source_format,
 303                                                         pipe.scale_taps.htaps,
 304                                                         pipe.scale_taps.htaps_c,
 305                                                         pipe.scale_taps.vtaps,
 306                                                         pipe.scale_taps.vtaps_c,
 307                                                         /* Output */
 308                                                         &pscl_throughput, &pscl_throughput_chroma,
 309                                                         &dpp_clk_single_dpp);
 310
 311         clock = dpp_clk_single_dpp * (1 + context->bw_ctx.dml.soc.dcn_downspread_percent / 100);
 312
 313         if (clock > 0)
 314                 clk_frequency = vco_speed * 4.0 / ((int)(vco_speed * 4.0));
 315
 316         if (clk_frequency > context->bw_ctx.dml.soc.clock_limits[index].dppclk_mhz)
 317                 return true;
 318         else
 319                 return false;
 320 }
 321
 322 static float calculate_net_bw_in_kbytes_sec(struct _vcs_dpi_voltage_scaling_st *entry)
 323 {
 324         float memory_bw_kbytes_sec;
 325         float fabric_bw_kbytes_sec;
 326         float sdp_bw_kbytes_sec;
 327         float limiting_bw_kbytes_sec;
 328
 329         memory_bw_kbytes_sec = entry->dram_speed_mts *
 330                                 dcn3_2_soc.num_chans *
 331                                 dcn3_2_soc.dram_channel_width_bytes *
 332                                 ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100);
 333
 334         fabric_bw_kbytes_sec = entry->fabricclk_mhz *
 335                                 dcn3_2_soc.return_bus_width_bytes *
 336                                 ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100);
 337
 338         sdp_bw_kbytes_sec = entry->dcfclk_mhz *
 339                                 dcn3_2_soc.return_bus_width_bytes *
 340                                 ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100);
 341
 342         limiting_bw_kbytes_sec = memory_bw_kbytes_sec;
 343
 344         if (fabric_bw_kbytes_sec < limiting_bw_kbytes_sec)
 345                 limiting_bw_kbytes_sec = fabric_bw_kbytes_sec;
 346
 347         if (sdp_bw_kbytes_sec < limiting_bw_kbytes_sec)
 348                 limiting_bw_kbytes_sec = sdp_bw_kbytes_sec;
 349
 350         return limiting_bw_kbytes_sec;
 351 }
 352
 353 void insert_entry_into_table_sorted(struct _vcs_dpi_voltage_scaling_st *table,
 354                                     unsigned int *num_entries,
 355                                     struct _vcs_dpi_voltage_scaling_st *entry)
 356 {
 357         int i = 0;
 358         int index = 0;
 359         float net_bw_of_new_state = 0;
 360
 361         dc_assert_fp_enabled();
 362
 363         if (*num_entries == 0) {
 364                 table[0] = *entry;
 365                 (*num_entries)++;
 366         } else {
 367                 net_bw_of_new_state = calculate_net_bw_in_kbytes_sec(entry);
 368                 while (net_bw_of_new_state > calculate_net_bw_in_kbytes_sec(&table[index])) {
 369                         index++;
 370                         if (index >= *num_entries)
 371                                 break;
 372                 }
 373
 374                 for (i = *num_entries; i > index; i--)
 375                         table[i] = table[i - 1];
 376
 377                 table[index] = *entry;
 378                 (*num_entries)++;
 379         }
 380 }
 381
 382 /**
 383  * dcn32_set_phantom_stream_timing: Set timing params for the phantom stream
 384  *
 385  * Set timing params of the phantom stream based on calculated output from DML.
 386  * This function first gets the DML pipe index using the DC pipe index, then
 387  * calls into DML (get_subviewport_lines_needed_in_mall) to get the number of
 388  * lines required for SubVP MCLK switching and assigns to the phantom stream
 389  * accordingly.
 390  *
 391  * - The number of SubVP lines calculated in DML does not take into account
 392  * FW processing delays and required pstate allow width, so we must include
 393  * that separately.
 394  *
 395  * - Set phantom backporch = vstartup of main pipe
 396  *
 397  * @dc: current dc state
 398  * @context: new dc state
 399  * @ref_pipe: Main pipe for the phantom stream
 400  * @pipes: DML pipe params
 401  * @pipe_cnt: number of DML pipes
 402  * @dc_pipe_idx: DC pipe index for the main pipe (i.e. ref_pipe)
 403  */
 404 void dcn32_set_phantom_stream_timing(struct dc *dc,
 405                                      struct dc_state *context,
 406                                      struct pipe_ctx *ref_pipe,
 407                                      struct dc_stream_state *phantom_stream,
 408                                      display_e2e_pipe_params_st *pipes,
 409                                      unsigned int pipe_cnt,
 410                                      unsigned int dc_pipe_idx)
 411 {
 412         unsigned int i, pipe_idx;
 413         struct pipe_ctx *pipe;
 414         uint32_t phantom_vactive, phantom_bp, pstate_width_fw_delay_lines;
 415         unsigned int vlevel = context->bw_ctx.dml.vba.VoltageLevel;
 416         unsigned int dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
 417         unsigned int socclk = context->bw_ctx.dml.vba.SOCCLKPerState[vlevel];
 418
 419         dc_assert_fp_enabled();
 420
 421         // Find DML pipe index (pipe_idx) using dc_pipe_idx
 422         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
 423                 pipe = &context->res_ctx.pipe_ctx[i];
 424
 425                 if (!pipe->stream)
 426                         continue;
 427
 428                 if (i == dc_pipe_idx)
 429                         break;
 430
 431                 pipe_idx++;
 432         }
 433
 434         // Calculate lines required for pstate allow width and FW processing delays
 435         pstate_width_fw_delay_lines = ((double)(dc->caps.subvp_fw_processing_delay_us +
 436                         dc->caps.subvp_pstate_allow_width_us) / 1000000) *
 437                         (ref_pipe->stream->timing.pix_clk_100hz * 100) /
 438                         (double)ref_pipe->stream->timing.h_total;
 439
 440         // Update clks_cfg for calling into recalculate
 441         pipes[0].clks_cfg.voltage = vlevel;
 442         pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
 443         pipes[0].clks_cfg.socclk_mhz = socclk;
 444
 445         // DML calculation for MALL region doesn't take into account FW delay
 446         // and required pstate allow width for multi-display cases
 447         phantom_vactive = get_subviewport_lines_needed_in_mall(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx) +
 448                                 pstate_width_fw_delay_lines;
 449
 450         // For backporch of phantom pipe, use vstartup of the main pipe
 451         phantom_bp = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
 452
 453         phantom_stream->dst.y = 0;
 454         phantom_stream->dst.height = phantom_vactive;
 455         phantom_stream->src.y = 0;
 456         phantom_stream->src.height = phantom_vactive;
 457
 458         phantom_stream->timing.v_addressable = phantom_vactive;
 459         phantom_stream->timing.v_front_porch = 1;
 460         phantom_stream->timing.v_total = phantom_stream->timing.v_addressable +
 461                                                 phantom_stream->timing.v_front_porch +
 462                                                 phantom_stream->timing.v_sync_width +
 463                                                 phantom_bp;
 464 }
 465
 466 /**
 467  * dcn32_get_num_free_pipes: Calculate number of free pipes
 468  *
 469  * This function assumes that a "used" pipe is a pipe that has
 470  * both a stream and a plane assigned to it.
 471  *
 472  * @dc: current dc state
 473  * @context: new dc state
 474  *
 475  * Return:
 476  * Number of free pipes available in the context
 477  */
 478 static unsigned int dcn32_get_num_free_pipes(struct dc *dc, struct dc_state *context)
 479 {
 480         unsigned int i;
 481         unsigned int free_pipes = 0;
 482         unsigned int num_pipes = 0;
 483
 484         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 485                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 486
 487                 if (pipe->stream && !pipe->top_pipe) {
 488                         while (pipe) {
 489                                 num_pipes++;
 490                                 pipe = pipe->bottom_pipe;
 491                         }
 492                 }
 493         }
 494
 495         free_pipes = dc->res_pool->pipe_count - num_pipes;
 496         return free_pipes;
 497 }
 498
 499 /**
 500  * dcn32_assign_subvp_pipe: Function to decide which pipe will use Sub-VP.
 501  *
 502  * We enter this function if we are Sub-VP capable (i.e. enough pipes available)
 503  * and regular P-State switching (i.e. VACTIVE/VBLANK) is not supported, or if
 504  * we are forcing SubVP P-State switching on the current config.
 505  *
 506  * The number of pipes used for the chosen surface must be less than or equal to the
 507  * number of free pipes available.
 508  *
 509  * In general we choose surfaces with the longest frame time first (better for SubVP + VBLANK).
 510  * For multi-display cases the ActiveDRAMClockChangeMargin doesn't provide enough info on its own
 511  * for determining which should be the SubVP pipe (need a way to determine if a pipe / plane doesn't
 512  * support MCLK switching naturally [i.e. ACTIVE or VBLANK]).
 513  *
 514  * @param dc: current dc state
 515  * @param context: new dc state
 516  * @param index: [out] dc pipe index for the pipe chosen to have phantom pipes assigned
 517  *
 518  * Return:
 519  * True if a valid pipe assignment was found for Sub-VP. Otherwise false.
 520  */
 521 static bool dcn32_assign_subvp_pipe(struct dc *dc,
 522                                     struct dc_state *context,
 523                                     unsigned int *index)
 524 {
 525         unsigned int i, pipe_idx;
 526         unsigned int max_frame_time = 0;
 527         bool valid_assignment_found = false;
 528         unsigned int free_pipes = dcn32_get_num_free_pipes(dc, context);
 529         bool current_assignment_freesync = false;
 530
 531         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
 532                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 533                 unsigned int num_pipes = 0;
 534                 unsigned int refresh_rate = 0;
 535
 536                 if (!pipe->stream)
 537                         continue;
 538
 539                 // Round up
 540                 refresh_rate = (pipe->stream->timing.pix_clk_100hz * 100 +
 541                                 pipe->stream->timing.v_total * pipe->stream->timing.h_total - 1)
 542                                 / (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total);
 543                 if (pipe->plane_state && !pipe->top_pipe &&
 544                                 pipe->stream->mall_stream_config.type == SUBVP_NONE && refresh_rate < 120) {
 545                         while (pipe) {
 546                                 num_pipes++;
 547                                 pipe = pipe->bottom_pipe;
 548                         }
 549
 550                         pipe = &context->res_ctx.pipe_ctx[i];
 551                         if (num_pipes <= free_pipes) {
 552                                 struct dc_stream_state *stream = pipe->stream;
 553                                 unsigned int frame_us = (stream->timing.v_total * stream->timing.h_total /
 554                                                 (double)(stream->timing.pix_clk_100hz * 100)) * 1000000;
 555                                 if (frame_us > max_frame_time && !stream->ignore_msa_timing_param) {
 556                                         *index = i;
 557                                         max_frame_time = frame_us;
 558                                         valid_assignment_found = true;
 559                                         current_assignment_freesync = false;
 560                                 /* For the 2-Freesync display case, still choose the one with the
 561                              * longest frame time
 562                              */
 563                                 } else if (stream->ignore_msa_timing_param && (!valid_assignment_found ||
 564                                                 (current_assignment_freesync && frame_us > max_frame_time))) {
 565                                         *index = i;
 566                                         valid_assignment_found = true;
 567                                         current_assignment_freesync = true;
 568                                 }
 569                         }
 570                 }
 571                 pipe_idx++;
 572         }
 573         return valid_assignment_found;
 574 }
 575
 576 /**
 577  * dcn32_enough_pipes_for_subvp: Function to check if there are "enough" pipes for SubVP.
 578  *
 579  * This function returns true if there are enough free pipes
 580  * to create the required phantom pipes for any given stream
 581  * (that does not already have phantom pipe assigned).
 582  *
 583  * e.g. For a 2 stream config where the first stream uses one
 584  * pipe and the second stream uses 2 pipes (i.e. pipe split),
 585  * this function will return true because there is 1 remaining
 586  * pipe which can be used as the phantom pipe for the non pipe
 587  * split pipe.
 588  *
 589  * @dc: current dc state
 590  * @context: new dc state
 591  *
 592  * Return:
 593  * True if there are enough free pipes to assign phantom pipes to at least one
 594  * stream that does not already have phantom pipes assigned. Otherwise false.
 595  */
 596 static bool dcn32_enough_pipes_for_subvp(struct dc *dc, struct dc_state *context)
 597 {
 598         unsigned int i, split_cnt, free_pipes;
 599         unsigned int min_pipe_split = dc->res_pool->pipe_count + 1; // init as max number of pipes + 1
 600         bool subvp_possible = false;
 601
 602         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 603                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 604
 605                 // Find the minimum pipe split count for non SubVP pipes
 606                 if (pipe->stream && !pipe->top_pipe &&
 607                     pipe->stream->mall_stream_config.type == SUBVP_NONE) {
 608                         split_cnt = 0;
 609                         while (pipe) {
 610                                 split_cnt++;
 611                                 pipe = pipe->bottom_pipe;
 612                         }
 613
 614                         if (split_cnt < min_pipe_split)
 615                                 min_pipe_split = split_cnt;
 616                 }
 617         }
 618
 619         free_pipes = dcn32_get_num_free_pipes(dc, context);
 620
 621         // SubVP only possible if at least one pipe is being used (i.e. free_pipes
 622         // should not equal to the pipe_count)
 623         if (free_pipes >= min_pipe_split && free_pipes < dc->res_pool->pipe_count)
 624                 subvp_possible = true;
 625
 626         return subvp_possible;
 627 }
 628
 629 /**
 630  * subvp_subvp_schedulable: Determine if SubVP + SubVP config is schedulable
 631  *
 632  * High level algorithm:
 633  * 1. Find longest microschedule length (in us) between the two SubVP pipes
 634  * 2. Check if the worst case overlap (VBLANK in middle of ACTIVE) for both
 635  * pipes still allows for the maximum microschedule to fit in the active
 636  * region for both pipes.
 637  *
 638  * @dc: current dc state
 639  * @context: new dc state
 640  *
 641  * Return:
 642  * bool - True if the SubVP + SubVP config is schedulable, false otherwise
 643  */
 644 static bool subvp_subvp_schedulable(struct dc *dc, struct dc_state *context)
 645 {
 646         struct pipe_ctx *subvp_pipes[2];
 647         struct dc_stream_state *phantom = NULL;
 648         uint32_t microschedule_lines = 0;
 649         uint32_t index = 0;
 650         uint32_t i;
 651         uint32_t max_microschedule_us = 0;
 652         int32_t vactive1_us, vactive2_us, vblank1_us, vblank2_us;
 653
 654         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 655                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 656                 uint32_t time_us = 0;
 657
 658                 /* Loop to calculate the maximum microschedule time between the two SubVP pipes,
 659                  * and also to store the two main SubVP pipe pointers in subvp_pipes[2].
 660                  */
 661                 if (pipe->stream && pipe->plane_state && !pipe->top_pipe &&
 662                     pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
 663                         phantom = pipe->stream->mall_stream_config.paired_stream;
 664                         microschedule_lines = (phantom->timing.v_total - phantom->timing.v_front_porch) +
 665                                         phantom->timing.v_addressable;
 666
 667                         // Round up when calculating microschedule time (+ 1 at the end)
 668                         time_us = (microschedule_lines * phantom->timing.h_total) /
 669                                         (double)(phantom->timing.pix_clk_100hz * 100) * 1000000 +
 670                                                 dc->caps.subvp_prefetch_end_to_mall_start_us +
 671                                                 dc->caps.subvp_fw_processing_delay_us + 1;
 672                         if (time_us > max_microschedule_us)
 673                                 max_microschedule_us = time_us;
 674
 675                         subvp_pipes[index] = pipe;
 676                         index++;
 677
 678                         // Maximum 2 SubVP pipes
 679                         if (index == 2)
 680                                 break;
 681                 }
 682         }
 683         vactive1_us = ((subvp_pipes[0]->stream->timing.v_addressable * subvp_pipes[0]->stream->timing.h_total) /
 684                         (double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000;
 685         vactive2_us = ((subvp_pipes[1]->stream->timing.v_addressable * subvp_pipes[1]->stream->timing.h_total) /
 686                                 (double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000;
 687         vblank1_us = (((subvp_pipes[0]->stream->timing.v_total - subvp_pipes[0]->stream->timing.v_addressable) *
 688                         subvp_pipes[0]->stream->timing.h_total) /
 689                         (double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000;
 690         vblank2_us = (((subvp_pipes[1]->stream->timing.v_total - subvp_pipes[1]->stream->timing.v_addressable) *
 691                         subvp_pipes[1]->stream->timing.h_total) /
 692                         (double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000;
 693
 694         if ((vactive1_us - vblank2_us) / 2 > max_microschedule_us &&
 695             (vactive2_us - vblank1_us) / 2 > max_microschedule_us)
 696                 return true;
 697
 698         return false;
 699 }
 700
 701 /**
 702  * subvp_drr_schedulable: Determine if SubVP + DRR config is schedulable
 703  *
 704  * High level algorithm:
 705  * 1. Get timing for SubVP pipe, phantom pipe, and DRR pipe
 706  * 2. Determine the frame time for the DRR display when adding required margin for MCLK switching
 707  * (the margin is equal to the MALL region + DRR margin (500us))
 708  * 3.If (SubVP Active - Prefetch > Stretched DRR frame + max(MALL region, Stretched DRR frame))
 709  * then report the configuration as supported
 710  *
 711  * @dc: current dc state
 712  * @context: new dc state
 713  * @drr_pipe: DRR pipe_ctx for the SubVP + DRR config
 714  *
 715  * Return:
 716  * bool - True if the SubVP + DRR config is schedulable, false otherwise
 717  */
 718 static bool subvp_drr_schedulable(struct dc *dc, struct dc_state *context, struct pipe_ctx *drr_pipe)
 719 {
 720         bool schedulable = false;
 721         uint32_t i;
 722         struct pipe_ctx *pipe = NULL;
 723         struct dc_crtc_timing *main_timing = NULL;
 724         struct dc_crtc_timing *phantom_timing = NULL;
 725         struct dc_crtc_timing *drr_timing = NULL;
 726         int16_t prefetch_us = 0;
 727         int16_t mall_region_us = 0;
 728         int16_t drr_frame_us = 0;       // nominal frame time
 729         int16_t subvp_active_us = 0;
 730         int16_t stretched_drr_us = 0;
 731         int16_t drr_stretched_vblank_us = 0;
 732         int16_t max_vblank_mallregion = 0;
 733
 734         // Find SubVP pipe
 735         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 736                 pipe = &context->res_ctx.pipe_ctx[i];
 737
 738                 // We check for master pipe, but it shouldn't matter since we only need
 739                 // the pipe for timing info (stream should be same for any pipe splits)
 740                 if (!pipe->stream || !pipe->plane_state || pipe->top_pipe || pipe->prev_odm_pipe)
 741                         continue;
 742
 743                 // Find the SubVP pipe
 744                 if (pipe->stream->mall_stream_config.type == SUBVP_MAIN)
 745                         break;
 746         }
 747
 748         main_timing = &pipe->stream->timing;
 749         phantom_timing = &pipe->stream->mall_stream_config.paired_stream->timing;
 750         drr_timing = &drr_pipe->stream->timing;
 751         prefetch_us = (phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total /
 752                         (double)(phantom_timing->pix_clk_100hz * 100) * 1000000 +
 753                         dc->caps.subvp_prefetch_end_to_mall_start_us;
 754         subvp_active_us = main_timing->v_addressable * main_timing->h_total /
 755                         (double)(main_timing->pix_clk_100hz * 100) * 1000000;
 756         drr_frame_us = drr_timing->v_total * drr_timing->h_total /
 757                         (double)(drr_timing->pix_clk_100hz * 100) * 1000000;
 758         // P-State allow width and FW delays already included phantom_timing->v_addressable
 759         mall_region_us = phantom_timing->v_addressable * phantom_timing->h_total /
 760                         (double)(phantom_timing->pix_clk_100hz * 100) * 1000000;
 761         stretched_drr_us = drr_frame_us + mall_region_us + SUBVP_DRR_MARGIN_US;
 762         drr_stretched_vblank_us = (drr_timing->v_total - drr_timing->v_addressable) * drr_timing->h_total /
 763                         (double)(drr_timing->pix_clk_100hz * 100) * 1000000 + (stretched_drr_us - drr_frame_us);
 764         max_vblank_mallregion = drr_stretched_vblank_us > mall_region_us ? drr_stretched_vblank_us : mall_region_us;
 765
 766         /* We consider SubVP + DRR schedulable if the stretched frame duration of the DRR display (i.e. the
 767          * highest refresh rate + margin that can support UCLK P-State switch) passes the static analysis
 768          * for VBLANK: (VACTIVE region of the SubVP pipe can fit the MALL prefetch, VBLANK frame time,
 769          * and the max of (VBLANK blanking time, MALL region)).
 770          */
 771         if (stretched_drr_us < (1 / (double)drr_timing->min_refresh_in_uhz) * 1000000 * 1000000 &&
 772                         subvp_active_us - prefetch_us - stretched_drr_us - max_vblank_mallregion > 0)
 773                 schedulable = true;
 774
 775         return schedulable;
 776 }
 777
 778
 779 /**
 780  * subvp_vblank_schedulable: Determine if SubVP + VBLANK config is schedulable
 781  *
 782  * High level algorithm:
 783  * 1. Get timing for SubVP pipe, phantom pipe, and VBLANK pipe
 784  * 2. If (SubVP Active - Prefetch > Vblank Frame Time + max(MALL region, Vblank blanking time))
 785  * then report the configuration as supported
 786  * 3. If the VBLANK display is DRR, then take the DRR static schedulability path
 787  *
 788  * @dc: current dc state
 789  * @context: new dc state
 790  *
 791  * Return:
 792  * bool - True if the SubVP + VBLANK/DRR config is schedulable, false otherwise
 793  */
 794 static bool subvp_vblank_schedulable(struct dc *dc, struct dc_state *context)
 795 {
 796         struct pipe_ctx *pipe = NULL;
 797         struct pipe_ctx *subvp_pipe = NULL;
 798         bool found = false;
 799         bool schedulable = false;
 800         uint32_t i = 0;
 801         uint8_t vblank_index = 0;
 802         uint16_t prefetch_us = 0;
 803         uint16_t mall_region_us = 0;
 804         uint16_t vblank_frame_us = 0;
 805         uint16_t subvp_active_us = 0;
 806         uint16_t vblank_blank_us = 0;
 807         uint16_t max_vblank_mallregion = 0;
 808         struct dc_crtc_timing *main_timing = NULL;
 809         struct dc_crtc_timing *phantom_timing = NULL;
 810         struct dc_crtc_timing *vblank_timing = NULL;
 811
 812         /* For SubVP + VBLANK/DRR cases, we assume there can only be
 813          * a single VBLANK/DRR display. If DML outputs SubVP + VBLANK
 814          * is supported, it is either a single VBLANK case or two VBLANK
 815          * displays which are synchronized (in which case they have identical
 816          * timings).
 817          */
 818         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 819                 pipe = &context->res_ctx.pipe_ctx[i];
 820
 821                 // We check for master pipe, but it shouldn't matter since we only need
 822                 // the pipe for timing info (stream should be same for any pipe splits)
 823                 if (!pipe->stream || !pipe->plane_state || pipe->top_pipe || pipe->prev_odm_pipe)
 824                         continue;
 825
 826                 if (!found && pipe->stream->mall_stream_config.type == SUBVP_NONE) {
 827                         // Found pipe which is not SubVP or Phantom (i.e. the VBLANK pipe).
 828                         vblank_index = i;
 829                         found = true;
 830                 }
 831
 832                 if (!subvp_pipe && pipe->stream->mall_stream_config.type == SUBVP_MAIN)
 833                         subvp_pipe = pipe;
 834         }
 835         // Use ignore_msa_timing_param flag to identify as DRR
 836         if (found && context->res_ctx.pipe_ctx[vblank_index].stream->ignore_msa_timing_param) {
 837                 // SUBVP + DRR case
 838                 schedulable = subvp_drr_schedulable(dc, context, &context->res_ctx.pipe_ctx[vblank_index]);
 839         } else if (found) {
 840                 main_timing = &subvp_pipe->stream->timing;
 841                 phantom_timing = &subvp_pipe->stream->mall_stream_config.paired_stream->timing;
 842                 vblank_timing = &context->res_ctx.pipe_ctx[vblank_index].stream->timing;
 843                 // Prefetch time is equal to VACTIVE + BP + VSYNC of the phantom pipe
 844                 // Also include the prefetch end to mallstart delay time
 845                 prefetch_us = (phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total /
 846                                 (double)(phantom_timing->pix_clk_100hz * 100) * 1000000 +
 847                                 dc->caps.subvp_prefetch_end_to_mall_start_us;
 848                 // P-State allow width and FW delays already included phantom_timing->v_addressable
 849                 mall_region_us = phantom_timing->v_addressable * phantom_timing->h_total /
 850                                 (double)(phantom_timing->pix_clk_100hz * 100) * 1000000;
 851                 vblank_frame_us = vblank_timing->v_total * vblank_timing->h_total /
 852                                 (double)(vblank_timing->pix_clk_100hz * 100) * 1000000;
 853                 vblank_blank_us =  (vblank_timing->v_total - vblank_timing->v_addressable) * vblank_timing->h_total /
 854                                 (double)(vblank_timing->pix_clk_100hz * 100) * 1000000;
 855                 subvp_active_us = main_timing->v_addressable * main_timing->h_total /
 856                                 (double)(main_timing->pix_clk_100hz * 100) * 1000000;
 857                 max_vblank_mallregion = vblank_blank_us > mall_region_us ? vblank_blank_us : mall_region_us;
 858
 859                 // Schedulable if VACTIVE region of the SubVP pipe can fit the MALL prefetch, VBLANK frame time,
 860                 // and the max of (VBLANK blanking time, MALL region)
 861                 // TODO: Possibly add some margin (i.e. the below conditions should be [...] > X instead of [...] > 0)
 862                 if (subvp_active_us - prefetch_us - vblank_frame_us - max_vblank_mallregion > 0)
 863                         schedulable = true;
 864         }
 865         return schedulable;
 866 }
 867
 868 /**
 869  * subvp_validate_static_schedulability: Check which SubVP case is calculated and handle
 870  * static analysis based on the case.
 871  *
 872  * Three cases:
 873  * 1. SubVP + SubVP
 874  * 2. SubVP + VBLANK (DRR checked internally)
 875  * 3. SubVP + VACTIVE (currently unsupported)
 876  *
 877  * @dc: current dc state
 878  * @context: new dc state
 879  * @vlevel: Voltage level calculated by DML
 880  *
 881  * Return:
 882  * bool - True if statically schedulable, false otherwise
 883  */
 884 static bool subvp_validate_static_schedulability(struct dc *dc,
 885                                 struct dc_state *context,
 886                                 int vlevel)
 887 {
 888         bool schedulable = true;        // true by default for single display case
 889         struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
 890         uint32_t i, pipe_idx;
 891         uint8_t subvp_count = 0;
 892         uint8_t vactive_count = 0;
 893
 894         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
 895                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 896
 897                 if (!pipe->stream)
 898                         continue;
 899
 900                 if (pipe->plane_state && !pipe->top_pipe &&
 901                                 pipe->stream->mall_stream_config.type == SUBVP_MAIN)
 902                         subvp_count++;
 903
 904                 // Count how many planes that aren't SubVP/phantom are capable of VACTIVE
 905                 // switching (SubVP + VACTIVE unsupported). In situations where we force
 906                 // SubVP for a VACTIVE plane, we don't want to increment the vactive_count.
 907                 if (vba->ActiveDRAMClockChangeLatencyMargin[vba->pipe_plane[pipe_idx]] > 0 &&
 908                     pipe->stream->mall_stream_config.type == SUBVP_NONE) {
 909                         vactive_count++;
 910                 }
 911                 pipe_idx++;
 912         }
 913
 914         if (subvp_count == 2) {
 915                 // Static schedulability check for SubVP + SubVP case
 916                 schedulable = subvp_subvp_schedulable(dc, context);
 917         } else if (vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_vblank_w_mall_sub_vp) {
 918                 // Static schedulability check for SubVP + VBLANK case. Also handle the case where
 919                 // DML outputs SubVP + VBLANK + VACTIVE (DML will report as SubVP + VBLANK)
 920                 if (vactive_count > 0)
 921                         schedulable = false;
 922                 else
 923                         schedulable = subvp_vblank_schedulable(dc, context);
 924         } else if (vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_vactive_w_mall_sub_vp &&
 925                         vactive_count > 0) {
 926                 // For single display SubVP cases, DML will output dm_dram_clock_change_vactive_w_mall_sub_vp by default.
 927                 // We tell the difference between SubVP vs. SubVP + VACTIVE by checking the vactive_count.
 928                 // SubVP + VACTIVE currently unsupported
 929                 schedulable = false;
 930         }
 931         return schedulable;
 932 }
 933
 934 void dcn32_full_validate_bw_helper(struct dc *dc,
 935                                    struct dc_state *context,
 936                                    display_e2e_pipe_params_st *pipes,
 937                                    int *vlevel,
 938                                    int *split,
 939                                    bool *merge,
 940                                    int *pipe_cnt)
 941 {
 942         struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
 943         unsigned int dc_pipe_idx = 0;
 944         bool found_supported_config = false;
 945         struct pipe_ctx *pipe = NULL;
 946         uint32_t non_subvp_pipes = 0;
 947         bool drr_pipe_found = false;
 948         uint32_t drr_pipe_index = 0;
 949         uint32_t i = 0;
 950
 951         dc_assert_fp_enabled();
 952
 953         /*
 954          * DML favors voltage over p-state, but we're more interested in
 955          * supporting p-state over voltage. We can't support p-state in
 956          * prefetch mode > 0 so try capping the prefetch mode to start.
 957          */
 958         context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final =
 959                         dm_prefetch_support_uclk_fclk_and_stutter;
 960         *vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt);
 961         /* This may adjust vlevel and maxMpcComb */
 962         if (*vlevel < context->bw_ctx.dml.soc.num_states)
 963                 *vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge);
 964
 965         /* Conditions for setting up phantom pipes for SubVP:
 966          * 1. Not force disable SubVP
 967          * 2. Full update (i.e. !fast_validate)
 968          * 3. Enough pipes are available to support SubVP (TODO: Which pipes will use VACTIVE / VBLANK / SUBVP?)
 969          * 4. Display configuration passes validation
 970          * 5. (Config doesn't support MCLK in VACTIVE/VBLANK || dc->debug.force_subvp_mclk_switch)
 971          */
 972         if (!dc->debug.force_disable_subvp && dcn32_all_pipes_have_stream_and_plane(dc, context) &&
 973             !dcn32_mpo_in_use(context) && (*vlevel == context->bw_ctx.dml.soc.num_states ||
 974             vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported ||
 975             dc->debug.force_subvp_mclk_switch)) {
 976
 977                 dcn32_merge_pipes_for_subvp(dc, context);
 978
 979                 while (!found_supported_config && dcn32_enough_pipes_for_subvp(dc, context) &&
 980                         dcn32_assign_subvp_pipe(dc, context, &dc_pipe_idx)) {
 981                         /* For the case where *vlevel = num_states, bandwidth validation has failed for this config.
 982                          * Adding phantom pipes won't change the validation result, so change the DML input param
 983                          * for P-State support before adding phantom pipes and recalculating the DML result.
 984                          * However, this case is only applicable for SubVP + DRR cases because the prefetch mode
 985                          * will not allow for switch in VBLANK. The DRR display must have it's VBLANK stretched
 986                          * enough to support MCLK switching.
 987                          */
 988                         if (*vlevel == context->bw_ctx.dml.soc.num_states) {
 989                                 context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final =
 990                                                                 dm_prefetch_support_stutter;
 991                                 /* There are params (such as FabricClock) that need to be recalculated
 992                                  * after validation fails (otherwise it will be 0). Calculation for
 993                                  * phantom vactive requires call into DML, so we must ensure all the
 994                                  * vba params are valid otherwise we'll get incorrect phantom vactive.
 995                                  */
 996                                 *vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt);
 997                         }
 998
 999                         dc->res_pool->funcs->add_phantom_pipes(dc, context, pipes, *pipe_cnt, dc_pipe_idx);
1000
1001                         *pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, false);
1002                         // Populate dppclk to trigger a recalculate in dml_get_voltage_level
1003                         // so the phantom pipe DLG params can be assigned correctly.
1004                         pipes[0].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, *pipe_cnt, 0);
1005                         *vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt);
1006
1007                         if (*vlevel < context->bw_ctx.dml.soc.num_states &&
1008                             vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] != dm_dram_clock_change_unsupported
1009                             && subvp_validate_static_schedulability(dc, context, *vlevel)) {
1010                                 found_supported_config = true;
1011                         } else if (*vlevel < context->bw_ctx.dml.soc.num_states &&
1012                                         vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported) {
1013                                 /* Case where 1 SubVP is added, and DML reports MCLK unsupported. This handles
1014                                  * the case for SubVP + DRR, where the DRR display does not support MCLK switch
1015                                  * at it's native refresh rate / timing.
1016                                  */
1017                                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1018                                         pipe = &context->res_ctx.pipe_ctx[i];
1019                                         if (pipe->stream && pipe->plane_state && !pipe->top_pipe &&
1020                                             pipe->stream->mall_stream_config.type == SUBVP_NONE) {
1021                                                 non_subvp_pipes++;
1022                                                 // Use ignore_msa_timing_param flag to identify as DRR
1023                                                 if (pipe->stream->ignore_msa_timing_param) {
1024                                                         drr_pipe_found = true;
1025                                                         drr_pipe_index = i;
1026                                                 }
1027                                         }
1028                                 }
1029                                 // If there is only 1 remaining non SubVP pipe that is DRR, check static
1030                                 // schedulability for SubVP + DRR.
1031                                 if (non_subvp_pipes == 1 && drr_pipe_found) {
1032                                         found_supported_config = subvp_drr_schedulable(dc, context,
1033                                                                                        &context->res_ctx.pipe_ctx[drr_pipe_index]);
1034                                 }
1035                         }
1036                 }
1037
1038                 // If SubVP pipe config is unsupported (or cannot be used for UCLK switching)
1039                 // remove phantom pipes and repopulate dml pipes
1040                 if (!found_supported_config) {
1041                         dc->res_pool->funcs->remove_phantom_pipes(dc, context);
1042                         vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] = dm_dram_clock_change_unsupported;
1043                         *pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, false);
1044                 } else {
1045                         // only call dcn20_validate_apply_pipe_split_flags if we found a supported config
1046                         memset(split, 0, MAX_PIPES * sizeof(int));
1047                         memset(merge, 0, MAX_PIPES * sizeof(bool));
1048                         *vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge);
1049
1050                         // Most populate phantom DLG params before programming hardware / timing for phantom pipe
1051                         DC_FP_START();
1052                         dcn32_helper_populate_phantom_dlg_params(dc, context, pipes, *pipe_cnt);
1053                         DC_FP_END();
1054
1055                         // Note: We can't apply the phantom pipes to hardware at this time. We have to wait
1056                         // until driver has acquired the DMCUB lock to do it safely.
1057                 }
1058         }
1059 }
1060