drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26
  27 #include "../display_mode_lib.h"
  28 #include "../display_mode_vba.h"
  29 #include "../dml_inline_defs.h"
  30 #include "display_rq_dlg_calc_21.h"
  31
  32 /*
  33  * NOTE:
  34  *   This file is gcc-parseable HW gospel, coming straight from HW engineers.
  35  *
  36  * It doesn't adhere to Linux kernel style and sometimes will do things in odd
  37  * ways. Unless there is something clearly wrong with it the code should
  38  * remain as-is as it provides us with a guarantee from HW that it is correct.
  39  */
  40
  41 static void calculate_ttu_cursor(
  42                 struct display_mode_lib *mode_lib,
  43                 double *refcyc_per_req_delivery_pre_cur,
  44                 double *refcyc_per_req_delivery_cur,
  45                 double refclk_freq_in_mhz,
  46                 double ref_freq_to_pix_freq,
  47                 double hscale_pixel_rate_l,
  48                 double hscl_ratio,
  49                 double vratio_pre_l,
  50                 double vratio_l,
  51                 unsigned int cur_width,
  52                 enum cursor_bpp cur_bpp);
  53
  54 static unsigned int get_bytes_per_element(enum source_format_class source_format, bool is_chroma)
  55 {
  56         unsigned int ret_val = 0;
  57
  58         if (source_format == dm_444_16) {
  59                 if (!is_chroma)
  60                         ret_val = 2;
  61         } else if (source_format == dm_444_32) {
  62                 if (!is_chroma)
  63                         ret_val = 4;
  64         } else if (source_format == dm_444_64) {
  65                 if (!is_chroma)
  66                         ret_val = 8;
  67         } else if (source_format == dm_420_8) {
  68                 if (is_chroma)
  69                         ret_val = 2;
  70                 else
  71                         ret_val = 1;
  72         } else if (source_format == dm_420_10) {
  73                 if (is_chroma)
  74                         ret_val = 4;
  75                 else
  76                         ret_val = 2;
  77         } else if (source_format == dm_444_8) {
  78                 ret_val = 1;
  79         }
  80         return ret_val;
  81 }
  82
  83 static bool is_dual_plane(enum source_format_class source_format)
  84 {
  85         bool ret_val = false;
  86
  87         if ((source_format == dm_420_8) || (source_format == dm_420_10))
  88                 ret_val = true;
  89
  90         return ret_val;
  91 }
  92
  93 static double get_refcyc_per_delivery(
  94                 struct display_mode_lib *mode_lib,
  95                 double refclk_freq_in_mhz,
  96                 double pclk_freq_in_mhz,
  97                 bool odm_combine,
  98                 unsigned int recout_width,
  99                 unsigned int hactive,
 100                 double vratio,
 101                 double hscale_pixel_rate,
 102                 unsigned int delivery_width,
 103                 unsigned int req_per_swath_ub)
 104 {
 105         double refcyc_per_delivery = 0.0;
 106
 107         if (vratio <= 1.0) {
 108                 if (odm_combine)
 109                         refcyc_per_delivery = (double) refclk_freq_in_mhz
 110                                         * dml_min((double) recout_width, (double) hactive / 2.0)
 111                                         / pclk_freq_in_mhz / (double) req_per_swath_ub;
 112                 else
 113                         refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) recout_width
 114                                         / pclk_freq_in_mhz / (double) req_per_swath_ub;
 115         } else {
 116                 refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) delivery_width
 117                                 / (double) hscale_pixel_rate / (double) req_per_swath_ub;
 118         }
 119
 120         dml_print("DML_DLG: %s: refclk_freq_in_mhz = %3.2f\n", __func__, refclk_freq_in_mhz);
 121         dml_print("DML_DLG: %s: pclk_freq_in_mhz   = %3.2f\n", __func__, pclk_freq_in_mhz);
 122         dml_print("DML_DLG: %s: recout_width       = %d\n", __func__, recout_width);
 123         dml_print("DML_DLG: %s: vratio             = %3.2f\n", __func__, vratio);
 124         dml_print("DML_DLG: %s: req_per_swath_ub   = %d\n", __func__, req_per_swath_ub);
 125         dml_print("DML_DLG: %s: refcyc_per_delivery= %3.2f\n", __func__, refcyc_per_delivery);
 126
 127         return refcyc_per_delivery;
 128
 129 }
 130
 131 static unsigned int get_blk_size_bytes(const enum source_macro_tile_size tile_size)
 132 {
 133         if (tile_size == dm_256k_tile)
 134                 return (256 * 1024);
 135         else if (tile_size == dm_64k_tile)
 136                 return (64 * 1024);
 137         else
 138                 return (4 * 1024);
 139 }
 140
 141 static void extract_rq_sizing_regs(
 142                 struct display_mode_lib *mode_lib,
 143                 display_data_rq_regs_st *rq_regs,
 144                 const display_data_rq_sizing_params_st rq_sizing)
 145 {
 146         dml_print("DML_DLG: %s: rq_sizing param\n", __func__);
 147         print__data_rq_sizing_params_st(mode_lib, rq_sizing);
 148
 149         rq_regs->chunk_size = dml_log2(rq_sizing.chunk_bytes) - 10;
 150
 151         if (rq_sizing.min_chunk_bytes == 0)
 152                 rq_regs->min_chunk_size = 0;
 153         else
 154                 rq_regs->min_chunk_size = dml_log2(rq_sizing.min_chunk_bytes) - 8 + 1;
 155
 156         rq_regs->meta_chunk_size = dml_log2(rq_sizing.meta_chunk_bytes) - 10;
 157         if (rq_sizing.min_meta_chunk_bytes == 0)
 158                 rq_regs->min_meta_chunk_size = 0;
 159         else
 160                 rq_regs->min_meta_chunk_size = dml_log2(rq_sizing.min_meta_chunk_bytes) - 6 + 1;
 161
 162         rq_regs->dpte_group_size = dml_log2(rq_sizing.dpte_group_bytes) - 6;
 163         rq_regs->mpte_group_size = dml_log2(rq_sizing.mpte_group_bytes) - 6;
 164 }
 165
 166 static void extract_rq_regs(
 167                 struct display_mode_lib *mode_lib,
 168                 display_rq_regs_st *rq_regs,
 169                 const display_rq_params_st rq_param)
 170 {
 171         unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024;
 172         unsigned int detile_buf_plane1_addr = 0;
 173
 174         extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), rq_param.sizing.rq_l);
 175
 176         rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(
 177                         dml_log2(rq_param.dlg.rq_l.dpte_row_height),
 178                         1) - 3;
 179
 180         if (rq_param.yuv420) {
 181                 extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), rq_param.sizing.rq_c);
 182                 rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(
 183                                 dml_log2(rq_param.dlg.rq_c.dpte_row_height),
 184                                 1) - 3;
 185         }
 186
 187         rq_regs->rq_regs_l.swath_height = dml_log2(rq_param.dlg.rq_l.swath_height);
 188         rq_regs->rq_regs_c.swath_height = dml_log2(rq_param.dlg.rq_c.swath_height);
 189
 190         // FIXME: take the max between luma, chroma chunk size?
 191         // okay for now, as we are setting chunk_bytes to 8kb anyways
 192         if (rq_param.sizing.rq_l.chunk_bytes >= 32 * 1024) { //32kb
 193                 rq_regs->drq_expansion_mode = 0;
 194         } else {
 195                 rq_regs->drq_expansion_mode = 2;
 196         }
 197         rq_regs->prq_expansion_mode = 1;
 198         rq_regs->mrq_expansion_mode = 1;
 199         rq_regs->crq_expansion_mode = 1;
 200
 201         if (rq_param.yuv420) {
 202                 if ((double) rq_param.misc.rq_l.stored_swath_bytes
 203                                 / (double) rq_param.misc.rq_c.stored_swath_bytes <= 1.5) {
 204                         detile_buf_plane1_addr = (detile_buf_size_in_bytes / 2.0 / 64.0); // half to chroma
 205                 } else {
 206                         detile_buf_plane1_addr = dml_round_to_multiple(
 207                                         (unsigned int) ((2.0 * detile_buf_size_in_bytes) / 3.0),
 208                                         256,
 209                                         0) / 64.0; // 2/3 to chroma
 210                 }
 211         }
 212         rq_regs->plane1_base_address = detile_buf_plane1_addr;
 213 }
 214
 215 static void handle_det_buf_split(
 216                 struct display_mode_lib *mode_lib,
 217                 display_rq_params_st *rq_param,
 218                 const display_pipe_source_params_st pipe_src_param)
 219 {
 220         unsigned int total_swath_bytes = 0;
 221         unsigned int swath_bytes_l = 0;
 222         unsigned int swath_bytes_c = 0;
 223         unsigned int full_swath_bytes_packed_l = 0;
 224         unsigned int full_swath_bytes_packed_c = 0;
 225         bool req128_l = false;
 226         bool req128_c = false;
 227         bool surf_linear = (pipe_src_param.sw_mode == dm_sw_linear);
 228         bool surf_vert = (pipe_src_param.source_scan == dm_vert);
 229         unsigned int log2_swath_height_l = 0;
 230         unsigned int log2_swath_height_c = 0;
 231         unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024;
 232
 233         full_swath_bytes_packed_l = rq_param->misc.rq_l.full_swath_bytes;
 234         full_swath_bytes_packed_c = rq_param->misc.rq_c.full_swath_bytes;
 235
 236         if (rq_param->yuv420_10bpc) {
 237                 full_swath_bytes_packed_l = dml_round_to_multiple(
 238                                 rq_param->misc.rq_l.full_swath_bytes * 2 / 3,
 239                                 256,
 240                                 1) + 256;
 241                 full_swath_bytes_packed_c = dml_round_to_multiple(
 242                                 rq_param->misc.rq_c.full_swath_bytes * 2 / 3,
 243                                 256,
 244                                 1) + 256;
 245         }
 246
 247         if (rq_param->yuv420) {
 248                 total_swath_bytes = 2 * full_swath_bytes_packed_l + 2 * full_swath_bytes_packed_c;
 249
 250                 if (total_swath_bytes <= detile_buf_size_in_bytes) { //full 256b request
 251                         req128_l = false;
 252                         req128_c = false;
 253                         swath_bytes_l = full_swath_bytes_packed_l;
 254                         swath_bytes_c = full_swath_bytes_packed_c;
 255                 } else { //128b request (for luma only for yuv420 8bpc)
 256                         req128_l = true;
 257                         req128_c = false;
 258                         swath_bytes_l = full_swath_bytes_packed_l / 2;
 259                         swath_bytes_c = full_swath_bytes_packed_c;
 260                 }
 261                 // Note: assumption, the config that pass in will fit into
 262                 //       the detiled buffer.
 263         } else {
 264                 total_swath_bytes = 2 * full_swath_bytes_packed_l;
 265
 266                 if (total_swath_bytes <= detile_buf_size_in_bytes)
 267                         req128_l = false;
 268                 else
 269                         req128_l = true;
 270
 271                 swath_bytes_l = total_swath_bytes;
 272                 swath_bytes_c = 0;
 273         }
 274         rq_param->misc.rq_l.stored_swath_bytes = swath_bytes_l;
 275         rq_param->misc.rq_c.stored_swath_bytes = swath_bytes_c;
 276
 277         if (surf_linear) {
 278                 log2_swath_height_l = 0;
 279                 log2_swath_height_c = 0;
 280         } else if (!surf_vert) {
 281                 log2_swath_height_l = dml_log2(rq_param->misc.rq_l.blk256_height) - req128_l;
 282                 log2_swath_height_c = dml_log2(rq_param->misc.rq_c.blk256_height) - req128_c;
 283         } else {
 284                 log2_swath_height_l = dml_log2(rq_param->misc.rq_l.blk256_width) - req128_l;
 285                 log2_swath_height_c = dml_log2(rq_param->misc.rq_c.blk256_width) - req128_c;
 286         }
 287         rq_param->dlg.rq_l.swath_height = 1 << log2_swath_height_l;
 288         rq_param->dlg.rq_c.swath_height = 1 << log2_swath_height_c;
 289
 290         dml_print("DML_DLG: %s: req128_l = %0d\n", __func__, req128_l);
 291         dml_print("DML_DLG: %s: req128_c = %0d\n", __func__, req128_c);
 292         dml_print(
 293                         "DML_DLG: %s: full_swath_bytes_packed_l = %0d\n",
 294                         __func__,
 295                         full_swath_bytes_packed_l);
 296         dml_print(
 297                         "DML_DLG: %s: full_swath_bytes_packed_c = %0d\n",
 298                         __func__,
 299                         full_swath_bytes_packed_c);
 300 }
 301
 302 static void get_meta_and_pte_attr(
 303                 struct display_mode_lib *mode_lib,
 304                 display_data_rq_dlg_params_st *rq_dlg_param,
 305                 display_data_rq_misc_params_st *rq_misc_param,
 306                 display_data_rq_sizing_params_st *rq_sizing_param,
 307                 unsigned int vp_width,
 308                 unsigned int vp_height,
 309                 unsigned int data_pitch,
 310                 unsigned int meta_pitch,
 311                 unsigned int source_format,
 312                 unsigned int tiling,
 313                 unsigned int macro_tile_size,
 314                 unsigned int source_scan,
 315                 unsigned int hostvm_enable,
 316                 unsigned int is_chroma)
 317 {
 318         bool surf_linear = (tiling == dm_sw_linear);
 319         bool surf_vert = (source_scan == dm_vert);
 320
 321         unsigned int bytes_per_element;
 322         unsigned int bytes_per_element_y = get_bytes_per_element(
 323                         (enum source_format_class) (source_format),
 324                         false);
 325         unsigned int bytes_per_element_c = get_bytes_per_element(
 326                         (enum source_format_class) (source_format),
 327                         true);
 328
 329         unsigned int blk256_width = 0;
 330         unsigned int blk256_height = 0;
 331
 332         unsigned int blk256_width_y = 0;
 333         unsigned int blk256_height_y = 0;
 334         unsigned int blk256_width_c = 0;
 335         unsigned int blk256_height_c = 0;
 336         unsigned int log2_bytes_per_element;
 337         unsigned int log2_blk256_width;
 338         unsigned int log2_blk256_height;
 339         unsigned int blk_bytes;
 340         unsigned int log2_blk_bytes;
 341         unsigned int log2_blk_height;
 342         unsigned int log2_blk_width;
 343         unsigned int log2_meta_req_bytes;
 344         unsigned int log2_meta_req_height;
 345         unsigned int log2_meta_req_width;
 346         unsigned int meta_req_width;
 347         unsigned int meta_req_height;
 348         unsigned int log2_meta_row_height;
 349         unsigned int meta_row_width_ub;
 350         unsigned int log2_meta_chunk_bytes;
 351         unsigned int log2_meta_chunk_height;
 352
 353         //full sized meta chunk width in unit of data elements
 354         unsigned int log2_meta_chunk_width;
 355         unsigned int log2_min_meta_chunk_bytes;
 356         unsigned int min_meta_chunk_width;
 357         unsigned int meta_chunk_width;
 358         unsigned int meta_chunk_per_row_int;
 359         unsigned int meta_row_remainder;
 360         unsigned int meta_chunk_threshold;
 361         unsigned int meta_blk_bytes;
 362         unsigned int meta_blk_height;
 363         unsigned int meta_blk_width;
 364         unsigned int meta_surface_bytes;
 365         unsigned int vmpg_bytes;
 366         unsigned int meta_pte_req_per_frame_ub;
 367         unsigned int meta_pte_bytes_per_frame_ub;
 368         const unsigned int log2_vmpg_bytes = dml_log2(mode_lib->soc.vmm_page_size_bytes);
 369         const unsigned int dpte_buf_in_pte_reqs =
 370                 mode_lib->ip.dpte_buffer_size_in_pte_reqs_luma + mode_lib->ip.dpte_buffer_size_in_pte_reqs_chroma;
 371         const unsigned int pde_proc_buffer_size_64k_reqs =
 372                         mode_lib->ip.pde_proc_buffer_size_64k_reqs;
 373
 374         unsigned int log2_vmpg_height = 0;
 375         unsigned int log2_vmpg_width = 0;
 376         unsigned int log2_dpte_req_height_ptes = 0;
 377         unsigned int log2_dpte_req_height = 0;
 378         unsigned int log2_dpte_req_width = 0;
 379         unsigned int log2_dpte_row_height_linear = 0;
 380         unsigned int log2_dpte_row_height = 0;
 381         unsigned int log2_dpte_group_width = 0;
 382         unsigned int dpte_row_width_ub = 0;
 383         unsigned int dpte_req_height = 0;
 384         unsigned int dpte_req_width = 0;
 385         unsigned int dpte_group_width = 0;
 386         unsigned int log2_dpte_group_bytes = 0;
 387         unsigned int log2_dpte_group_length = 0;
 388         unsigned int pde_buf_entries;
 389         bool yuv420 = (source_format == dm_420_8 || source_format == dm_420_10);
 390
 391         Calculate256BBlockSizes(
 392                         (enum source_format_class) (source_format),
 393                         (enum dm_swizzle_mode) (tiling),
 394                         bytes_per_element_y,
 395                         bytes_per_element_c,
 396                         &blk256_height_y,
 397                         &blk256_height_c,
 398                         &blk256_width_y,
 399                         &blk256_width_c);
 400
 401         if (!is_chroma) {
 402                 blk256_width = blk256_width_y;
 403                 blk256_height = blk256_height_y;
 404                 bytes_per_element = bytes_per_element_y;
 405         } else {
 406                 blk256_width = blk256_width_c;
 407                 blk256_height = blk256_height_c;
 408                 bytes_per_element = bytes_per_element_c;
 409         }
 410
 411         log2_bytes_per_element = dml_log2(bytes_per_element);
 412
 413         dml_print("DML_DLG: %s: surf_linear        = %d\n", __func__, surf_linear);
 414         dml_print("DML_DLG: %s: surf_vert          = %d\n", __func__, surf_vert);
 415         dml_print("DML_DLG: %s: blk256_width       = %d\n", __func__, blk256_width);
 416         dml_print("DML_DLG: %s: blk256_height      = %d\n", __func__, blk256_height);
 417
 418         log2_blk256_width = dml_log2((double) blk256_width);
 419         log2_blk256_height = dml_log2((double) blk256_height);
 420         blk_bytes = surf_linear ?
 421                         256 : get_blk_size_bytes((enum source_macro_tile_size) macro_tile_size);
 422         log2_blk_bytes = dml_log2((double) blk_bytes);
 423         log2_blk_height = 0;
 424         log2_blk_width = 0;
 425
 426         // remember log rule
 427         // "+" in log is multiply
 428         // "-" in log is divide
 429         // "/2" is like square root
 430         // blk is vertical biased
 431         if (tiling != dm_sw_linear)
 432                 log2_blk_height = log2_blk256_height
 433                                 + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1);
 434         else
 435                 log2_blk_height = 0;  // blk height of 1
 436
 437         log2_blk_width = log2_blk_bytes - log2_bytes_per_element - log2_blk_height;
 438
 439         if (!surf_vert) {
 440                 rq_dlg_param->swath_width_ub = dml_round_to_multiple(vp_width - 1, blk256_width, 1)
 441                                 + blk256_width;
 442                 rq_dlg_param->req_per_swath_ub = rq_dlg_param->swath_width_ub >> log2_blk256_width;
 443         } else {
 444                 rq_dlg_param->swath_width_ub = dml_round_to_multiple(
 445                                 vp_height - 1,
 446                                 blk256_height,
 447                                 1) + blk256_height;
 448                 rq_dlg_param->req_per_swath_ub = rq_dlg_param->swath_width_ub >> log2_blk256_height;
 449         }
 450
 451         if (!surf_vert)
 452                 rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_height
 453                                 * bytes_per_element;
 454         else
 455                 rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_width
 456                                 * bytes_per_element;
 457
 458         rq_misc_param->blk256_height = blk256_height;
 459         rq_misc_param->blk256_width = blk256_width;
 460
 461         // -------
 462         // meta
 463         // -------
 464         log2_meta_req_bytes = 6; // meta request is 64b and is 8x8byte meta element
 465
 466         // each 64b meta request for dcn is 8x8 meta elements and
 467         // a meta element covers one 256b block of the the data surface.
 468         log2_meta_req_height = log2_blk256_height + 3; // meta req is 8x8 byte, each byte represent 1 blk256
 469         log2_meta_req_width = log2_meta_req_bytes + 8 - log2_bytes_per_element
 470                         - log2_meta_req_height;
 471         meta_req_width = 1 << log2_meta_req_width;
 472         meta_req_height = 1 << log2_meta_req_height;
 473         log2_meta_row_height = 0;
 474         meta_row_width_ub = 0;
 475
 476         // the dimensions of a meta row are meta_row_width x meta_row_height in elements.
 477         // calculate upper bound of the meta_row_width
 478         if (!surf_vert) {
 479                 log2_meta_row_height = log2_meta_req_height;
 480                 meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1)
 481                                 + meta_req_width;
 482                 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width;
 483         } else {
 484                 log2_meta_row_height = log2_meta_req_width;
 485                 meta_row_width_ub = dml_round_to_multiple(vp_height - 1, meta_req_height, 1)
 486                                 + meta_req_height;
 487                 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_height;
 488         }
 489         rq_dlg_param->meta_bytes_per_row_ub = rq_dlg_param->meta_req_per_row_ub * 64;
 490
 491         rq_dlg_param->meta_row_height = 1 << log2_meta_row_height;
 492
 493         log2_meta_chunk_bytes = dml_log2(rq_sizing_param->meta_chunk_bytes);
 494         log2_meta_chunk_height = log2_meta_row_height;
 495
 496         //full sized meta chunk width in unit of data elements
 497         log2_meta_chunk_width = log2_meta_chunk_bytes + 8 - log2_bytes_per_element
 498                         - log2_meta_chunk_height;
 499         log2_min_meta_chunk_bytes = dml_log2(rq_sizing_param->min_meta_chunk_bytes);
 500         min_meta_chunk_width = 1
 501                         << (log2_min_meta_chunk_bytes + 8 - log2_bytes_per_element
 502                                         - log2_meta_chunk_height);
 503         meta_chunk_width = 1 << log2_meta_chunk_width;
 504         meta_chunk_per_row_int = (unsigned int) (meta_row_width_ub / meta_chunk_width);
 505         meta_row_remainder = meta_row_width_ub % meta_chunk_width;
 506         meta_chunk_threshold = 0;
 507         meta_blk_bytes = 4096;
 508         meta_blk_height = blk256_height * 64;
 509         meta_blk_width = meta_blk_bytes * 256 / bytes_per_element / meta_blk_height;
 510         meta_surface_bytes = meta_pitch
 511                         * (dml_round_to_multiple(vp_height - 1, meta_blk_height, 1)
 512                                         + meta_blk_height) * bytes_per_element / 256;
 513         vmpg_bytes = mode_lib->soc.vmm_page_size_bytes;
 514         meta_pte_req_per_frame_ub = (dml_round_to_multiple(
 515                         meta_surface_bytes - vmpg_bytes,
 516                         8 * vmpg_bytes,
 517                         1) + 8 * vmpg_bytes) / (8 * vmpg_bytes);
 518         meta_pte_bytes_per_frame_ub = meta_pte_req_per_frame_ub * 64; //64B mpte request
 519         rq_dlg_param->meta_pte_bytes_per_frame_ub = meta_pte_bytes_per_frame_ub;
 520
 521         dml_print("DML_DLG: %s: meta_blk_height             = %d\n", __func__, meta_blk_height);
 522         dml_print("DML_DLG: %s: meta_blk_width              = %d\n", __func__, meta_blk_width);
 523         dml_print("DML_DLG: %s: meta_surface_bytes          = %d\n", __func__, meta_surface_bytes);
 524         dml_print(
 525                         "DML_DLG: %s: meta_pte_req_per_frame_ub   = %d\n",
 526                         __func__,
 527                         meta_pte_req_per_frame_ub);
 528         dml_print(
 529                         "DML_DLG: %s: meta_pte_bytes_per_frame_ub = %d\n",
 530                         __func__,
 531                         meta_pte_bytes_per_frame_ub);
 532
 533         if (!surf_vert)
 534                 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width;
 535         else
 536                 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height;
 537
 538         if (meta_row_remainder <= meta_chunk_threshold)
 539                 rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 1;
 540         else
 541                 rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 2;
 542
 543         // ------
 544         // dpte
 545         // ------
 546         if (surf_linear) {
 547                 log2_vmpg_height = 0;   // one line high
 548         } else {
 549                 log2_vmpg_height = (log2_vmpg_bytes - 8) / 2 + log2_blk256_height;
 550         }
 551         log2_vmpg_width = log2_vmpg_bytes - log2_bytes_per_element - log2_vmpg_height;
 552
 553         // only 3 possible shapes for dpte request in dimensions of ptes: 8x1, 4x2, 2x4.
 554         if (surf_linear) { //one 64B PTE request returns 8 PTEs
 555                 log2_dpte_req_height_ptes = 0;
 556                 log2_dpte_req_width = log2_vmpg_width + 3;
 557                 log2_dpte_req_height = 0;
 558         } else if (log2_blk_bytes == 12) { //4KB tile means 4kB page size
 559                                            //one 64B req gives 8x1 PTEs for 4KB tile
 560                 log2_dpte_req_height_ptes = 0;
 561                 log2_dpte_req_width = log2_blk_width + 3;
 562                 log2_dpte_req_height = log2_blk_height + 0;
 563         } else if ((log2_blk_bytes >= 16) && (log2_vmpg_bytes == 12)) { // tile block >= 64KB
 564                                                                         //two 64B reqs of 2x4 PTEs give 16 PTEs to cover 64KB
 565                 log2_dpte_req_height_ptes = 4;
 566                 log2_dpte_req_width = log2_blk256_width + 4; // log2_64KB_width
 567                 log2_dpte_req_height = log2_blk256_height + 4; // log2_64KB_height
 568         } else { //64KB page size and must 64KB tile block
 569                  //one 64B req gives 8x1 PTEs for 64KB tile
 570                 log2_dpte_req_height_ptes = 0;
 571                 log2_dpte_req_width = log2_blk_width + 3;
 572                 log2_dpte_req_height = log2_blk_height + 0;
 573         }
 574
 575         // The dpte request dimensions in data elements is dpte_req_width x dpte_req_height
 576         // log2_vmpg_width is how much 1 pte represent, now calculating how much a 64b pte req represent
 577         // That depends on the pte shape (i.e. 8x1, 4x2, 2x4)
 578         //log2_dpte_req_height    = log2_vmpg_height + log2_dpte_req_height_ptes;
 579         //log2_dpte_req_width     = log2_vmpg_width + log2_dpte_req_width_ptes;
 580         dpte_req_height = 1 << log2_dpte_req_height;
 581         dpte_req_width = 1 << log2_dpte_req_width;
 582
 583         // calculate pitch dpte row buffer can hold
 584         // round the result down to a power of two.
 585         pde_buf_entries =
 586                         yuv420 ? (pde_proc_buffer_size_64k_reqs >> 1) : pde_proc_buffer_size_64k_reqs;
 587         if (surf_linear) {
 588                 unsigned int dpte_row_height;
 589
 590                 log2_dpte_row_height_linear = dml_floor(
 591                                 dml_log2(
 592                                                 dml_min(
 593                                                                 64 * 1024 * pde_buf_entries
 594                                                                                 / bytes_per_element,
 595                                                                 dpte_buf_in_pte_reqs
 596                                                                                 * dpte_req_width)
 597                                                                 / data_pitch),
 598                                 1);
 599
 600                 ASSERT(log2_dpte_row_height_linear >= 3);
 601
 602                 if (log2_dpte_row_height_linear > 7)
 603                         log2_dpte_row_height_linear = 7;
 604
 605                 log2_dpte_row_height = log2_dpte_row_height_linear;
 606                 // For linear, the dpte row is pitch dependent and the pte requests wrap at the pitch boundary.
 607                 // the dpte_row_width_ub is the upper bound of data_pitch*dpte_row_height in elements with this unique buffering.
 608                 dpte_row_height = 1 << log2_dpte_row_height;
 609                 dpte_row_width_ub = dml_round_to_multiple(
 610                                 data_pitch * dpte_row_height - 1,
 611                                 dpte_req_width,
 612                                 1) + dpte_req_width;
 613                 rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width;
 614         } else {
 615                 // the upper bound of the dpte_row_width without dependency on viewport position follows.
 616                 // for tiled mode, row height is the same as req height and row store up to vp size upper bound
 617                 if (!surf_vert) {
 618                         log2_dpte_row_height = log2_dpte_req_height;
 619                         dpte_row_width_ub = dml_round_to_multiple(vp_width - 1, dpte_req_width, 1)
 620                                         + dpte_req_width;
 621                         rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width;
 622                 } else {
 623                         log2_dpte_row_height =
 624                                         (log2_blk_width < log2_dpte_req_width) ?
 625                                                         log2_blk_width : log2_dpte_req_width;
 626                         dpte_row_width_ub = dml_round_to_multiple(vp_height - 1, dpte_req_height, 1)
 627                                         + dpte_req_height;
 628                         rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_height;
 629                 }
 630         }
 631         if (log2_blk_bytes >= 16 && log2_vmpg_bytes == 12) // tile block >= 64KB
 632                 rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 128; //2*64B dpte request
 633         else
 634                 rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 64; //64B dpte request
 635
 636         rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height;
 637
 638         // the dpte_group_bytes is reduced for the specific case of vertical
 639         // access of a tile surface that has dpte request of 8x1 ptes.
 640
 641         if (hostvm_enable)
 642                 rq_sizing_param->dpte_group_bytes = 512;
 643         else {
 644                 if (!surf_linear & (log2_dpte_req_height_ptes == 0) & surf_vert) //reduced, in this case, will have page fault within a group
 645                         rq_sizing_param->dpte_group_bytes = 512;
 646                 else
 647                         //full size
 648                         rq_sizing_param->dpte_group_bytes = 2048;
 649         }
 650
 651         //since pte request size is 64byte, the number of data pte requests per full sized group is as follows.
 652         log2_dpte_group_bytes = dml_log2(rq_sizing_param->dpte_group_bytes);
 653         log2_dpte_group_length = log2_dpte_group_bytes - 6; //length in 64b requests
 654
 655         // full sized data pte group width in elements
 656         if (!surf_vert)
 657                 log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_width;
 658         else
 659                 log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_height;
 660
 661         //But if the tile block >=64KB and the page size is 4KB, then each dPTE request is 2*64B
 662         if ((log2_blk_bytes >= 16) && (log2_vmpg_bytes == 12)) // tile block >= 64KB
 663                 log2_dpte_group_width = log2_dpte_group_width - 1;
 664
 665         dpte_group_width = 1 << log2_dpte_group_width;
 666
 667         // since dpte groups are only aligned to dpte_req_width and not dpte_group_width,
 668         // the upper bound for the dpte groups per row is as follows.
 669         rq_dlg_param->dpte_groups_per_row_ub = dml_ceil(
 670                         (double) dpte_row_width_ub / dpte_group_width,
 671                         1);
 672 }
 673
 674 static void get_surf_rq_param(
 675                 struct display_mode_lib *mode_lib,
 676                 display_data_rq_sizing_params_st *rq_sizing_param,
 677                 display_data_rq_dlg_params_st *rq_dlg_param,
 678                 display_data_rq_misc_params_st *rq_misc_param,
 679                 const display_pipe_params_st pipe_param,
 680                 bool is_chroma)
 681 {
 682         bool mode_422 = false;
 683         unsigned int vp_width = 0;
 684         unsigned int vp_height = 0;
 685         unsigned int data_pitch = 0;
 686         unsigned int meta_pitch = 0;
 687         unsigned int ppe = mode_422 ? 2 : 1;
 688
 689         // FIXME check if ppe apply for both luma and chroma in 422 case
 690         if (is_chroma) {
 691                 vp_width = pipe_param.src.viewport_width_c / ppe;
 692                 vp_height = pipe_param.src.viewport_height_c;
 693                 data_pitch = pipe_param.src.data_pitch_c;
 694                 meta_pitch = pipe_param.src.meta_pitch_c;
 695         } else {
 696                 vp_width = pipe_param.src.viewport_width / ppe;
 697                 vp_height = pipe_param.src.viewport_height;
 698                 data_pitch = pipe_param.src.data_pitch;
 699                 meta_pitch = pipe_param.src.meta_pitch;
 700         }
 701
 702         if (pipe_param.dest.odm_combine) {
 703                 unsigned int access_dir;
 704                 unsigned int full_src_vp_width;
 705                 unsigned int hactive_half;
 706                 unsigned int src_hactive_half;
 707                 access_dir = (pipe_param.src.source_scan == dm_vert); // vp access direction: horizontal or vertical accessed
 708                 hactive_half  = pipe_param.dest.hactive / 2;
 709                 if (is_chroma) {
 710                         full_src_vp_width = pipe_param.scale_ratio_depth.hscl_ratio_c * pipe_param.dest.full_recout_width;
 711                         src_hactive_half  = pipe_param.scale_ratio_depth.hscl_ratio_c * hactive_half;
 712                 } else {
 713                         full_src_vp_width = pipe_param.scale_ratio_depth.hscl_ratio * pipe_param.dest.full_recout_width;
 714                         src_hactive_half  = pipe_param.scale_ratio_depth.hscl_ratio * hactive_half;
 715                 }
 716
 717                 if (access_dir == 0) {
 718                         vp_width = dml_min(full_src_vp_width, src_hactive_half);
 719                         dml_print("DML_DLG: %s: vp_width = %d\n", __func__, vp_width);
 720                 } else {
 721                         vp_height = dml_min(full_src_vp_width, src_hactive_half);
 722                         dml_print("DML_DLG: %s: vp_height = %d\n", __func__, vp_height);
 723
 724                 }
 725                 dml_print("DML_DLG: %s: full_src_vp_width = %d\n", __func__, full_src_vp_width);
 726                 dml_print("DML_DLG: %s: hactive_half = %d\n", __func__, hactive_half);
 727                 dml_print("DML_DLG: %s: src_hactive_half = %d\n", __func__, src_hactive_half);
 728         }
 729         rq_sizing_param->chunk_bytes = 8192;
 730
 731         if (rq_sizing_param->chunk_bytes == 64 * 1024)
 732                 rq_sizing_param->min_chunk_bytes = 0;
 733         else
 734                 rq_sizing_param->min_chunk_bytes = 1024;
 735
 736         rq_sizing_param->meta_chunk_bytes = 2048;
 737         rq_sizing_param->min_meta_chunk_bytes = 256;
 738
 739         if (pipe_param.src.hostvm)
 740                 rq_sizing_param->mpte_group_bytes = 512;
 741         else
 742                 rq_sizing_param->mpte_group_bytes = 2048;
 743
 744         get_meta_and_pte_attr(
 745                         mode_lib,
 746                         rq_dlg_param,
 747                         rq_misc_param,
 748                         rq_sizing_param,
 749                         vp_width,
 750                         vp_height,
 751                         data_pitch,
 752                         meta_pitch,
 753                         pipe_param.src.source_format,
 754                         pipe_param.src.sw_mode,
 755                         pipe_param.src.macro_tile_size,
 756                         pipe_param.src.source_scan,
 757                         pipe_param.src.hostvm,
 758                         is_chroma);
 759 }
 760
 761 static void dml_rq_dlg_get_rq_params(
 762                 struct display_mode_lib *mode_lib,
 763                 display_rq_params_st *rq_param,
 764                 const display_pipe_params_st pipe_param)
 765 {
 766         // get param for luma surface
 767         rq_param->yuv420 = pipe_param.src.source_format == dm_420_8
 768                         || pipe_param.src.source_format == dm_420_10;
 769         rq_param->yuv420_10bpc = pipe_param.src.source_format == dm_420_10;
 770
 771         get_surf_rq_param(
 772                         mode_lib,
 773                         &(rq_param->sizing.rq_l),
 774                         &(rq_param->dlg.rq_l),
 775                         &(rq_param->misc.rq_l),
 776                         pipe_param,
 777                         0);
 778
 779         if (is_dual_plane((enum source_format_class) (pipe_param.src.source_format))) {
 780                 // get param for chroma surface
 781                 get_surf_rq_param(
 782                                 mode_lib,
 783                                 &(rq_param->sizing.rq_c),
 784                                 &(rq_param->dlg.rq_c),
 785                                 &(rq_param->misc.rq_c),
 786                                 pipe_param,
 787                                 1);
 788         }
 789
 790         // calculate how to split the det buffer space between luma and chroma
 791         handle_det_buf_split(mode_lib, rq_param, pipe_param.src);
 792         print__rq_params_st(mode_lib, *rq_param);
 793 }
 794
 795 void dml21_rq_dlg_get_rq_reg(
 796                 struct display_mode_lib *mode_lib,
 797                 display_rq_regs_st *rq_regs,
 798                 const display_pipe_params_st pipe_param)
 799 {
 800         display_rq_params_st rq_param = {0};
 801
 802         memset(rq_regs, 0, sizeof(*rq_regs));
 803         dml_rq_dlg_get_rq_params(mode_lib, &rq_param, pipe_param);
 804         extract_rq_regs(mode_lib, rq_regs, rq_param);
 805
 806         print__rq_regs_st(mode_lib, *rq_regs);
 807 }
 808
 809 // Note: currently taken in as is.
 810 // Nice to decouple code from hw register implement and extract code that are repeated for luma and chroma.
 811 static void dml_rq_dlg_get_dlg_params(
 812                 struct display_mode_lib *mode_lib,
 813                 const display_e2e_pipe_params_st *e2e_pipe_param,
 814                 const unsigned int num_pipes,
 815                 const unsigned int pipe_idx,
 816                 display_dlg_regs_st *disp_dlg_regs,
 817                 display_ttu_regs_st *disp_ttu_regs,
 818                 const display_rq_dlg_params_st rq_dlg_param,
 819                 const display_dlg_sys_params_st dlg_sys_param,
 820                 const bool cstate_en,
 821                 const bool pstate_en)
 822 {
 823         const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src;
 824         const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest;
 825         const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout;
 826         const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg;
 827         const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth;
 828         const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps;
 829
 830         // -------------------------
 831         // Section 1.15.2.1: OTG dependent Params
 832         // -------------------------
 833         // Timing
 834         unsigned int htotal = dst->htotal;
 835         //    unsigned int hblank_start = dst.hblank_start; // TODO: Remove
 836         unsigned int hblank_end = dst->hblank_end;
 837         unsigned int vblank_start = dst->vblank_start;
 838         unsigned int vblank_end = dst->vblank_end;
 839         unsigned int min_vblank = mode_lib->ip.min_vblank_lines;
 840
 841         double dppclk_freq_in_mhz = clks->dppclk_mhz;
 842         double dispclk_freq_in_mhz = clks->dispclk_mhz;
 843         double refclk_freq_in_mhz = clks->refclk_mhz;
 844         double pclk_freq_in_mhz = dst->pixel_rate_mhz;
 845         bool interlaced = dst->interlaced;
 846
 847         double ref_freq_to_pix_freq = refclk_freq_in_mhz / pclk_freq_in_mhz;
 848
 849         double min_dcfclk_mhz;
 850         double t_calc_us;
 851         double min_ttu_vblank;
 852
 853         double min_dst_y_ttu_vblank;
 854         unsigned int dlg_vblank_start;
 855         bool dual_plane;
 856         bool mode_422;
 857         unsigned int access_dir;
 858         unsigned int vp_height_l;
 859         unsigned int vp_width_l;
 860         unsigned int vp_height_c;
 861         unsigned int vp_width_c;
 862
 863         // Scaling
 864         unsigned int htaps_l;
 865         unsigned int htaps_c;
 866         double hratio_l;
 867         double hratio_c;
 868         double vratio_l;
 869         double vratio_c;
 870         bool scl_enable;
 871
 872         double line_time_in_us;
 873         //    double vinit_l;
 874         //    double vinit_c;
 875         //    double vinit_bot_l;
 876         //    double vinit_bot_c;
 877
 878         //    unsigned int swath_height_l;
 879         unsigned int swath_width_ub_l;
 880         //    unsigned int dpte_bytes_per_row_ub_l;
 881         unsigned int dpte_groups_per_row_ub_l;
 882         //    unsigned int meta_pte_bytes_per_frame_ub_l;
 883         //    unsigned int meta_bytes_per_row_ub_l;
 884
 885         //    unsigned int swath_height_c;
 886         unsigned int swath_width_ub_c;
 887         //   unsigned int dpte_bytes_per_row_ub_c;
 888         unsigned int dpte_groups_per_row_ub_c;
 889
 890         unsigned int meta_chunks_per_row_ub_l;
 891         unsigned int meta_chunks_per_row_ub_c;
 892         unsigned int vupdate_offset;
 893         unsigned int vupdate_width;
 894         unsigned int vready_offset;
 895
 896         unsigned int dppclk_delay_subtotal;
 897         unsigned int dispclk_delay_subtotal;
 898         unsigned int pixel_rate_delay_subtotal;
 899
 900         unsigned int vstartup_start;
 901         unsigned int dst_x_after_scaler;
 902         unsigned int dst_y_after_scaler;
 903         double line_wait;
 904         double dst_y_prefetch;
 905         double dst_y_per_vm_vblank;
 906         double dst_y_per_row_vblank;
 907         double dst_y_per_vm_flip;
 908         double dst_y_per_row_flip;
 909         double max_dst_y_per_vm_vblank;
 910         double max_dst_y_per_row_vblank;
 911         double lsw;
 912         double vratio_pre_l;
 913         double vratio_pre_c;
 914         unsigned int req_per_swath_ub_l;
 915         unsigned int req_per_swath_ub_c;
 916         unsigned int meta_row_height_l;
 917         unsigned int meta_row_height_c;
 918         unsigned int swath_width_pixels_ub_l;
 919         unsigned int swath_width_pixels_ub_c;
 920         unsigned int scaler_rec_in_width_l;
 921         unsigned int scaler_rec_in_width_c;
 922         unsigned int dpte_row_height_l;
 923         unsigned int dpte_row_height_c;
 924         double hscale_pixel_rate_l;
 925         double hscale_pixel_rate_c;
 926         double min_hratio_fact_l;
 927         double min_hratio_fact_c;
 928         double refcyc_per_line_delivery_pre_l;
 929         double refcyc_per_line_delivery_pre_c;
 930         double refcyc_per_line_delivery_l;
 931         double refcyc_per_line_delivery_c;
 932
 933         double refcyc_per_req_delivery_pre_l;
 934         double refcyc_per_req_delivery_pre_c;
 935         double refcyc_per_req_delivery_l;
 936         double refcyc_per_req_delivery_c;
 937
 938         unsigned int full_recout_width;
 939         double xfc_transfer_delay;
 940         double xfc_precharge_delay;
 941         double xfc_remote_surface_flip_latency;
 942         double xfc_dst_y_delta_drq_limit;
 943         double xfc_prefetch_margin;
 944         double refcyc_per_req_delivery_pre_cur0;
 945         double refcyc_per_req_delivery_cur0;
 946         double refcyc_per_req_delivery_pre_cur1;
 947         double refcyc_per_req_delivery_cur1;
 948
 949         memset(disp_dlg_regs, 0, sizeof(*disp_dlg_regs));
 950         memset(disp_ttu_regs, 0, sizeof(*disp_ttu_regs));
 951
 952         dml_print("DML_DLG: %s:  cstate_en = %d\n", __func__, cstate_en);
 953         dml_print("DML_DLG: %s:  pstate_en = %d\n", __func__, pstate_en);
 954
 955         dml_print("DML_DLG: %s: dppclk_freq_in_mhz     = %3.2f\n", __func__, dppclk_freq_in_mhz);
 956         dml_print("DML_DLG: %s: dispclk_freq_in_mhz    = %3.2f\n", __func__, dispclk_freq_in_mhz);
 957         dml_print("DML_DLG: %s: refclk_freq_in_mhz     = %3.2f\n", __func__, refclk_freq_in_mhz);
 958         dml_print("DML_DLG: %s: pclk_freq_in_mhz       = %3.2f\n", __func__, pclk_freq_in_mhz);
 959         dml_print("DML_DLG: %s: interlaced             = %d\n", __func__, interlaced);
 960         ASSERT(ref_freq_to_pix_freq < 4.0);
 961
 962         disp_dlg_regs->ref_freq_to_pix_freq =
 963                         (unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19));
 964         disp_dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal
 965                         * dml_pow(2, 8));
 966         disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits
 967         disp_dlg_regs->refcyc_h_blank_end = (unsigned int) ((double) hblank_end
 968                         * (double) ref_freq_to_pix_freq);
 969         ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int)dml_pow(2, 13));
 970
 971         min_dcfclk_mhz = dlg_sys_param.deepsleep_dcfclk_mhz;
 972         t_calc_us = get_tcalc(mode_lib, e2e_pipe_param, num_pipes);
 973         min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
 974
 975         min_dst_y_ttu_vblank = min_ttu_vblank * pclk_freq_in_mhz / (double) htotal;
 976         dlg_vblank_start = interlaced ? (vblank_start / 2) : vblank_start;
 977
 978         disp_dlg_regs->min_dst_y_next_start = (unsigned int) (((double) dlg_vblank_start) * dml_pow(2, 2));
 979         ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int)dml_pow(2, 18));
 980
 981         dml_print(
 982                         "DML_DLG: %s: min_dcfclk_mhz                         = %3.2f\n",
 983                         __func__,
 984                         min_dcfclk_mhz);
 985         dml_print(
 986                         "DML_DLG: %s: min_ttu_vblank                         = %3.2f\n",
 987                         __func__,
 988                         min_ttu_vblank);
 989         dml_print(
 990                         "DML_DLG: %s: min_dst_y_ttu_vblank                   = %3.2f\n",
 991                         __func__,
 992                         min_dst_y_ttu_vblank);
 993         dml_print(
 994                         "DML_DLG: %s: t_calc_us                              = %3.2f\n",
 995                         __func__,
 996                         t_calc_us);
 997         dml_print(
 998                         "DML_DLG: %s: disp_dlg_regs->min_dst_y_next_start    = 0x%0x\n",
 999                         __func__,
1000                         disp_dlg_regs->min_dst_y_next_start);
1001         dml_print(
1002                         "DML_DLG: %s: ref_freq_to_pix_freq                   = %3.2f\n",
1003                         __func__,
1004                         ref_freq_to_pix_freq);
1005
1006         // -------------------------
1007         // Section 1.15.2.2: Prefetch, Active and TTU
1008         // -------------------------
1009         // Prefetch Calc
1010         // Source
1011         //             dcc_en              = src.dcc;
1012         dual_plane = is_dual_plane((enum source_format_class) (src->source_format));
1013         mode_422 = false; // FIXME
1014         access_dir = (src->source_scan == dm_vert); // vp access direction: horizontal or vertical accessed
1015                                                     //      bytes_per_element_l = get_bytes_per_element(source_format_class(src.source_format), 0);
1016                                                     //      bytes_per_element_c = get_bytes_per_element(source_format_class(src.source_format), 1);
1017         vp_height_l = src->viewport_height;
1018         vp_width_l = src->viewport_width;
1019         vp_height_c = src->viewport_height_c;
1020         vp_width_c = src->viewport_width_c;
1021
1022         // Scaling
1023         htaps_l = taps->htaps;
1024         htaps_c = taps->htaps_c;
1025         hratio_l = scl->hscl_ratio;
1026         hratio_c = scl->hscl_ratio_c;
1027         vratio_l = scl->vscl_ratio;
1028         vratio_c = scl->vscl_ratio_c;
1029         scl_enable = scl->scl_enable;
1030
1031         line_time_in_us = (htotal / pclk_freq_in_mhz);
1032         swath_width_ub_l = rq_dlg_param.rq_l.swath_width_ub;
1033         dpte_groups_per_row_ub_l = rq_dlg_param.rq_l.dpte_groups_per_row_ub;
1034         swath_width_ub_c = rq_dlg_param.rq_c.swath_width_ub;
1035         dpte_groups_per_row_ub_c = rq_dlg_param.rq_c.dpte_groups_per_row_ub;
1036
1037         meta_chunks_per_row_ub_l = rq_dlg_param.rq_l.meta_chunks_per_row_ub;
1038         meta_chunks_per_row_ub_c = rq_dlg_param.rq_c.meta_chunks_per_row_ub;
1039         vupdate_offset = dst->vupdate_offset;
1040         vupdate_width = dst->vupdate_width;
1041         vready_offset = dst->vready_offset;
1042
1043         dppclk_delay_subtotal = mode_lib->ip.dppclk_delay_subtotal;
1044         dispclk_delay_subtotal = mode_lib->ip.dispclk_delay_subtotal;
1045
1046         if (scl_enable)
1047                 dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_scl;
1048         else
1049                 dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_scl_lb_only;
1050
1051         dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_cnvc_formatter
1052                         + src->num_cursors * mode_lib->ip.dppclk_delay_cnvc_cursor;
1053
1054         if (dout->dsc_enable) {
1055                 double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
1056
1057                 dispclk_delay_subtotal += dsc_delay;
1058         }
1059
1060         pixel_rate_delay_subtotal = dppclk_delay_subtotal * pclk_freq_in_mhz / dppclk_freq_in_mhz
1061                         + dispclk_delay_subtotal * pclk_freq_in_mhz / dispclk_freq_in_mhz;
1062
1063         vstartup_start = dst->vstartup_start;
1064         if (interlaced) {
1065                 if (vstartup_start / 2.0
1066                                 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal
1067                                 <= vblank_end / 2.0)
1068                         disp_dlg_regs->vready_after_vcount0 = 1;
1069                 else
1070                         disp_dlg_regs->vready_after_vcount0 = 0;
1071         } else {
1072                 if (vstartup_start
1073                                 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal
1074                                 <= vblank_end)
1075                         disp_dlg_regs->vready_after_vcount0 = 1;
1076                 else
1077                         disp_dlg_regs->vready_after_vcount0 = 0;
1078         }
1079
1080         // TODO: Where is this coming from?
1081         if (interlaced)
1082                 vstartup_start = vstartup_start / 2;
1083
1084         // TODO: What if this min_vblank doesn't match the value in the dml_config_settings.cpp?
1085         if (vstartup_start >= min_vblank) {
1086                 dml_print(
1087                                 "WARNING: DML_DLG: %s: vblank_start=%d vblank_end=%d\n",
1088                                 __func__,
1089                                 vblank_start,
1090                                 vblank_end);
1091                 dml_print(
1092                                 "WARNING: DML_DLG: %s: vstartup_start=%d should be less than min_vblank=%d\n",
1093                                 __func__,
1094                                 vstartup_start,
1095                                 min_vblank);
1096                 min_vblank = vstartup_start + 1;
1097                 dml_print(
1098                                 "WARNING: DML_DLG: %s: vstartup_start=%d should be less than min_vblank=%d\n",
1099                                 __func__,
1100                                 vstartup_start,
1101                                 min_vblank);
1102         }
1103
1104         dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
1105         dst_y_after_scaler = get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
1106
1107         dml_print("DML_DLG: %s: htotal                                 = %d\n", __func__, htotal);
1108         dml_print(
1109                         "DML_DLG: %s: pixel_rate_delay_subtotal              = %d\n",
1110                         __func__,
1111                         pixel_rate_delay_subtotal);
1112         dml_print(
1113                         "DML_DLG: %s: dst_x_after_scaler                     = %d\n",
1114                         __func__,
1115                         dst_x_after_scaler);
1116         dml_print(
1117                         "DML_DLG: %s: dst_y_after_scaler                     = %d\n",
1118                         __func__,
1119                         dst_y_after_scaler);
1120
1121         // Lwait
1122         // TODO: Should this be urgent_latency_pixel_mixed_with_vm_data_us?
1123         line_wait = mode_lib->soc.urgent_latency_pixel_data_only_us;
1124         if (cstate_en)
1125                 line_wait = dml_max(mode_lib->soc.sr_enter_plus_exit_time_us, line_wait);
1126         if (pstate_en)
1127                 line_wait = dml_max(
1128                                 mode_lib->soc.dram_clock_change_latency_us
1129                                                 + mode_lib->soc.urgent_latency_pixel_data_only_us, // TODO: Should this be urgent_latency_pixel_mixed_with_vm_data_us?
1130                                 line_wait);
1131         line_wait = line_wait / line_time_in_us;
1132
1133         dst_y_prefetch = get_dst_y_prefetch(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
1134         dml_print("DML_DLG: %s: dst_y_prefetch (after rnd) = %3.2f\n", __func__, dst_y_prefetch);
1135
1136         dst_y_per_vm_vblank = get_dst_y_per_vm_vblank(
1137                         mode_lib,
1138                         e2e_pipe_param,
1139                         num_pipes,
1140                         pipe_idx);
1141         dst_y_per_row_vblank = get_dst_y_per_row_vblank(
1142                         mode_lib,
1143                         e2e_pipe_param,
1144                         num_pipes,
1145                         pipe_idx);
1146         dst_y_per_vm_flip = get_dst_y_per_vm_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
1147         dst_y_per_row_flip = get_dst_y_per_row_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
1148
1149         max_dst_y_per_vm_vblank = 32.0;
1150         max_dst_y_per_row_vblank = 16.0;
1151
1152         // magic!
1153         if (htotal <= 75) {
1154                 min_vblank = 300;
1155                 max_dst_y_per_vm_vblank = 100.0;
1156                 max_dst_y_per_row_vblank = 100.0;
1157         }
1158
1159         dml_print("DML_DLG: %s: dst_y_per_vm_flip    = %3.2f\n", __func__, dst_y_per_vm_flip);
1160         dml_print("DML_DLG: %s: dst_y_per_row_flip   = %3.2f\n", __func__, dst_y_per_row_flip);
1161         dml_print("DML_DLG: %s: dst_y_per_vm_vblank  = %3.2f\n", __func__, dst_y_per_vm_vblank);
1162         dml_print("DML_DLG: %s: dst_y_per_row_vblank = %3.2f\n", __func__, dst_y_per_row_vblank);
1163
1164         ASSERT(dst_y_per_vm_vblank < max_dst_y_per_vm_vblank);
1165         ASSERT(dst_y_per_row_vblank < max_dst_y_per_row_vblank);
1166
1167         ASSERT(dst_y_prefetch > (dst_y_per_vm_vblank + dst_y_per_row_vblank));
1168         lsw = dst_y_prefetch - (dst_y_per_vm_vblank + dst_y_per_row_vblank);
1169
1170         dml_print("DML_DLG: %s: lsw = %3.2f\n", __func__, lsw);
1171
1172         vratio_pre_l = get_vratio_prefetch_l(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
1173         vratio_pre_c = get_vratio_prefetch_c(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
1174
1175         dml_print("DML_DLG: %s: vratio_pre_l=%3.2f\n", __func__, vratio_pre_l);
1176         dml_print("DML_DLG: %s: vratio_pre_c=%3.2f\n", __func__, vratio_pre_c);
1177
1178         // Active
1179         req_per_swath_ub_l = rq_dlg_param.rq_l.req_per_swath_ub;
1180         req_per_swath_ub_c = rq_dlg_param.rq_c.req_per_swath_ub;
1181         meta_row_height_l = rq_dlg_param.rq_l.meta_row_height;
1182         meta_row_height_c = rq_dlg_param.rq_c.meta_row_height;
1183         swath_width_pixels_ub_l = 0;
1184         swath_width_pixels_ub_c = 0;
1185         scaler_rec_in_width_l = 0;
1186         scaler_rec_in_width_c = 0;
1187         dpte_row_height_l = rq_dlg_param.rq_l.dpte_row_height;
1188         dpte_row_height_c = rq_dlg_param.rq_c.dpte_row_height;
1189
1190         if (mode_422) {
1191                 swath_width_pixels_ub_l = swath_width_ub_l * 2;  // *2 for 2 pixel per element
1192                 swath_width_pixels_ub_c = swath_width_ub_c * 2;
1193         } else {
1194                 swath_width_pixels_ub_l = swath_width_ub_l * 1;
1195                 swath_width_pixels_ub_c = swath_width_ub_c * 1;
1196         }
1197
1198         hscale_pixel_rate_l = 0.;
1199         hscale_pixel_rate_c = 0.;
1200         min_hratio_fact_l = 1.0;
1201         min_hratio_fact_c = 1.0;
1202
1203         if (hratio_l <= 1)
1204                 min_hratio_fact_l = 2.0;
1205         else if (htaps_l <= 6) {
1206                 if ((hratio_l * 2.0) > 4.0)
1207                         min_hratio_fact_l = 4.0;
1208                 else
1209                         min_hratio_fact_l = hratio_l * 2.0;
1210         } else {
1211                 if (hratio_l > 4.0)
1212                         min_hratio_fact_l = 4.0;
1213                 else
1214                         min_hratio_fact_l = hratio_l;
1215         }
1216
1217         hscale_pixel_rate_l = min_hratio_fact_l * dppclk_freq_in_mhz;
1218
1219         if (hratio_c <= 1)
1220                 min_hratio_fact_c = 2.0;
1221         else if (htaps_c <= 6) {
1222                 if ((hratio_c * 2.0) > 4.0)
1223                         min_hratio_fact_c = 4.0;
1224                 else
1225                         min_hratio_fact_c = hratio_c * 2.0;
1226         } else {
1227                 if (hratio_c > 4.0)
1228                         min_hratio_fact_c = 4.0;
1229                 else
1230                         min_hratio_fact_c = hratio_c;
1231         }
1232
1233         hscale_pixel_rate_c = min_hratio_fact_c * dppclk_freq_in_mhz;
1234
1235         refcyc_per_line_delivery_pre_l = 0.;
1236         refcyc_per_line_delivery_pre_c = 0.;
1237         refcyc_per_line_delivery_l = 0.;
1238         refcyc_per_line_delivery_c = 0.;
1239
1240         refcyc_per_req_delivery_pre_l = 0.;
1241         refcyc_per_req_delivery_pre_c = 0.;
1242         refcyc_per_req_delivery_l = 0.;
1243         refcyc_per_req_delivery_c = 0.;
1244
1245         full_recout_width = 0;
1246         // In ODM
1247         if (src->is_hsplit) {
1248                 // This "hack"  is only allowed (and valid) for MPC combine. In ODM
1249                 // combine, you MUST specify the full_recout_width...according to Oswin
1250                 if (dst->full_recout_width == 0 && !dst->odm_combine) {
1251                         dml_print(
1252                                         "DML_DLG: %s: Warning: full_recout_width not set in hsplit mode\n",
1253                                         __func__);
1254                         full_recout_width = dst->recout_width * 2; // assume half split for dcn1
1255                 } else
1256                         full_recout_width = dst->full_recout_width;
1257         } else
1258                 full_recout_width = dst->recout_width;
1259
1260         // As of DCN2, mpc_combine and odm_combine are mutually exclusive
1261         refcyc_per_line_delivery_pre_l = get_refcyc_per_delivery(
1262                         mode_lib,
1263                         refclk_freq_in_mhz,
1264                         pclk_freq_in_mhz,
1265                         dst->odm_combine,
1266                         full_recout_width,
1267                         dst->hactive,
1268                         vratio_pre_l,
1269                         hscale_pixel_rate_l,
1270                         swath_width_pixels_ub_l,
1271                         1); // per line
1272
1273         refcyc_per_line_delivery_l = get_refcyc_per_delivery(
1274                         mode_lib,
1275                         refclk_freq_in_mhz,
1276                         pclk_freq_in_mhz,
1277                         dst->odm_combine,
1278                         full_recout_width,
1279                         dst->hactive,
1280                         vratio_l,
1281                         hscale_pixel_rate_l,
1282                         swath_width_pixels_ub_l,
1283                         1); // per line
1284
1285         dml_print("DML_DLG: %s: full_recout_width              = %d\n", __func__, full_recout_width);
1286         dml_print(
1287                         "DML_DLG: %s: hscale_pixel_rate_l            = %3.2f\n",
1288                         __func__,
1289                         hscale_pixel_rate_l);
1290         dml_print(
1291                         "DML_DLG: %s: refcyc_per_line_delivery_pre_l = %3.2f\n",
1292                         __func__,
1293                         refcyc_per_line_delivery_pre_l);
1294         dml_print(
1295                         "DML_DLG: %s: refcyc_per_line_delivery_l     = %3.2f\n",
1296                         __func__,
1297                         refcyc_per_line_delivery_l);
1298
1299         if (dual_plane) {
1300                 refcyc_per_line_delivery_pre_c = get_refcyc_per_delivery(
1301                                 mode_lib,
1302                                 refclk_freq_in_mhz,
1303                                 pclk_freq_in_mhz,
1304                                 dst->odm_combine,
1305                                 full_recout_width,
1306                                 dst->hactive,
1307                                 vratio_pre_c,
1308                                 hscale_pixel_rate_c,
1309                                 swath_width_pixels_ub_c,
1310                                 1); // per line
1311
1312                 refcyc_per_line_delivery_c = get_refcyc_per_delivery(
1313                                 mode_lib,
1314                                 refclk_freq_in_mhz,
1315                                 pclk_freq_in_mhz,
1316                                 dst->odm_combine,
1317                                 full_recout_width,
1318                                 dst->hactive,
1319                                 vratio_c,
1320                                 hscale_pixel_rate_c,
1321                                 swath_width_pixels_ub_c,
1322                                 1);  // per line
1323
1324                 dml_print(
1325                                 "DML_DLG: %s: refcyc_per_line_delivery_pre_c = %3.2f\n",
1326                                 __func__,
1327                                 refcyc_per_line_delivery_pre_c);
1328                 dml_print(
1329                                 "DML_DLG: %s: refcyc_per_line_delivery_c     = %3.2f\n",
1330                                 __func__,
1331                                 refcyc_per_line_delivery_c);
1332         }
1333
1334         // TTU - Luma / Chroma
1335         if (access_dir) {  // vertical access
1336                 scaler_rec_in_width_l = vp_height_l;
1337                 scaler_rec_in_width_c = vp_height_c;
1338         } else {
1339                 scaler_rec_in_width_l = vp_width_l;
1340                 scaler_rec_in_width_c = vp_width_c;
1341         }
1342
1343         refcyc_per_req_delivery_pre_l = get_refcyc_per_delivery(
1344                         mode_lib,
1345                         refclk_freq_in_mhz,
1346                         pclk_freq_in_mhz,
1347                         dst->odm_combine,
1348                         full_recout_width,
1349                         dst->hactive,
1350                         vratio_pre_l,
1351                         hscale_pixel_rate_l,
1352                         scaler_rec_in_width_l,
1353                         req_per_swath_ub_l);  // per req
1354         refcyc_per_req_delivery_l = get_refcyc_per_delivery(
1355                         mode_lib,
1356                         refclk_freq_in_mhz,
1357                         pclk_freq_in_mhz,
1358                         dst->odm_combine,
1359                         full_recout_width,
1360                         dst->hactive,
1361                         vratio_l,
1362                         hscale_pixel_rate_l,
1363                         scaler_rec_in_width_l,
1364                         req_per_swath_ub_l);  // per req
1365
1366         dml_print(
1367                         "DML_DLG: %s: refcyc_per_req_delivery_pre_l = %3.2f\n",
1368                         __func__,
1369                         refcyc_per_req_delivery_pre_l);
1370         dml_print(
1371                         "DML_DLG: %s: refcyc_per_req_delivery_l     = %3.2f\n",
1372                         __func__,
1373                         refcyc_per_req_delivery_l);
1374
1375         ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13));
1376         ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13));
1377
1378         if (dual_plane) {
1379                 refcyc_per_req_delivery_pre_c = get_refcyc_per_delivery(
1380                                 mode_lib,
1381                                 refclk_freq_in_mhz,
1382                                 pclk_freq_in_mhz,
1383                                 dst->odm_combine,
1384                                 full_recout_width,
1385                                 dst->hactive,
1386                                 vratio_pre_c,
1387                                 hscale_pixel_rate_c,
1388                                 scaler_rec_in_width_c,
1389                                 req_per_swath_ub_c);  // per req
1390                 refcyc_per_req_delivery_c = get_refcyc_per_delivery(
1391                                 mode_lib,
1392                                 refclk_freq_in_mhz,
1393                                 pclk_freq_in_mhz,
1394                                 dst->odm_combine,
1395                                 full_recout_width,
1396                                 dst->hactive,
1397                                 vratio_c,
1398                                 hscale_pixel_rate_c,
1399                                 scaler_rec_in_width_c,
1400                                 req_per_swath_ub_c);  // per req
1401
1402                 dml_print(
1403                                 "DML_DLG: %s: refcyc_per_req_delivery_pre_c = %3.2f\n",
1404                                 __func__,
1405                                 refcyc_per_req_delivery_pre_c);
1406                 dml_print(
1407                                 "DML_DLG: %s: refcyc_per_req_delivery_c     = %3.2f\n",
1408                                 __func__,
1409                                 refcyc_per_req_delivery_c);
1410
1411                 ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13));
1412                 ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13));
1413         }
1414
1415         // XFC
1416         xfc_transfer_delay = get_xfc_transfer_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
1417         xfc_precharge_delay = get_xfc_precharge_delay(
1418                         mode_lib,
1419                         e2e_pipe_param,
1420                         num_pipes,
1421                         pipe_idx);
1422         xfc_remote_surface_flip_latency = get_xfc_remote_surface_flip_latency(
1423                         mode_lib,
1424                         e2e_pipe_param,
1425                         num_pipes,
1426                         pipe_idx);
1427         xfc_dst_y_delta_drq_limit = xfc_remote_surface_flip_latency;
1428         xfc_prefetch_margin = get_xfc_prefetch_margin(
1429                         mode_lib,
1430                         e2e_pipe_param,
1431                         num_pipes,
1432                         pipe_idx);
1433
1434         // TTU - Cursor
1435         refcyc_per_req_delivery_pre_cur0 = 0.0;
1436         refcyc_per_req_delivery_cur0 = 0.0;
1437         if (src->num_cursors > 0) {
1438                 calculate_ttu_cursor(
1439                                 mode_lib,
1440                                 &refcyc_per_req_delivery_pre_cur0,
1441                                 &refcyc_per_req_delivery_cur0,
1442                                 refclk_freq_in_mhz,
1443                                 ref_freq_to_pix_freq,
1444                                 hscale_pixel_rate_l,
1445                                 scl->hscl_ratio,
1446                                 vratio_pre_l,
1447                                 vratio_l,
1448                                 src->cur0_src_width,
1449                                 (enum cursor_bpp) (src->cur0_bpp));
1450         }
1451
1452         refcyc_per_req_delivery_pre_cur1 = 0.0;
1453         refcyc_per_req_delivery_cur1 = 0.0;
1454         if (src->num_cursors > 1) {
1455                 calculate_ttu_cursor(
1456                                 mode_lib,
1457                                 &refcyc_per_req_delivery_pre_cur1,
1458                                 &refcyc_per_req_delivery_cur1,
1459                                 refclk_freq_in_mhz,
1460                                 ref_freq_to_pix_freq,
1461                                 hscale_pixel_rate_l,
1462                                 scl->hscl_ratio,
1463                                 vratio_pre_l,
1464                                 vratio_l,
1465                                 src->cur1_src_width,
1466                                 (enum cursor_bpp) (src->cur1_bpp));
1467         }
1468
1469         // TTU - Misc
1470         // all hard-coded
1471
1472         // Assignment to register structures
1473         disp_dlg_regs->dst_y_after_scaler = dst_y_after_scaler; // in terms of line
1474         disp_dlg_regs->refcyc_x_after_scaler = dst_x_after_scaler * ref_freq_to_pix_freq; // in terms of refclk
1475         ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int)dml_pow(2, 13));
1476         disp_dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2));
1477         disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2));
1478         disp_dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2));
1479         disp_dlg_regs->dst_y_per_vm_flip = (unsigned int) (dst_y_per_vm_flip * dml_pow(2, 2));
1480         disp_dlg_regs->dst_y_per_row_flip = (unsigned int) (dst_y_per_row_flip * dml_pow(2, 2));
1481
1482         disp_dlg_regs->vratio_prefetch = (unsigned int) (vratio_pre_l * dml_pow(2, 19));
1483         disp_dlg_regs->vratio_prefetch_c = (unsigned int) (vratio_pre_c * dml_pow(2, 19));
1484
1485         dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_vm_vblank  = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_vm_vblank);
1486         dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_row_vblank = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_row_vblank);
1487         dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_vm_flip    = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_vm_flip);
1488         dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_row_flip   = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_row_flip);
1489
1490         disp_dlg_regs->refcyc_per_pte_group_vblank_l =
1491                         (unsigned int) (dst_y_per_row_vblank * (double) htotal
1492                                         * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_l);
1493         ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int)dml_pow(2, 13));
1494
1495         if (dual_plane) {
1496                 disp_dlg_regs->refcyc_per_pte_group_vblank_c = (unsigned int) (dst_y_per_row_vblank
1497                                 * (double) htotal * ref_freq_to_pix_freq
1498                                 / (double) dpte_groups_per_row_ub_c);
1499                 ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c
1500                                 < (unsigned int)dml_pow(2, 13));
1501         }
1502
1503         disp_dlg_regs->refcyc_per_meta_chunk_vblank_l =
1504                         (unsigned int) (dst_y_per_row_vblank * (double) htotal
1505                                         * ref_freq_to_pix_freq / (double) meta_chunks_per_row_ub_l);
1506         ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int)dml_pow(2, 13));
1507
1508         disp_dlg_regs->refcyc_per_meta_chunk_vblank_c =
1509                         disp_dlg_regs->refcyc_per_meta_chunk_vblank_l; // dcc for 4:2:0 is not supported in dcn1.0.  assigned to be the same as _l for now
1510
1511         disp_dlg_regs->refcyc_per_pte_group_flip_l = (unsigned int) (dst_y_per_row_flip * htotal
1512                         * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_l;
1513         disp_dlg_regs->refcyc_per_meta_chunk_flip_l = (unsigned int) (dst_y_per_row_flip * htotal
1514                         * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_l;
1515
1516         if (dual_plane) {
1517                 disp_dlg_regs->refcyc_per_pte_group_flip_c = (unsigned int) (dst_y_per_row_flip
1518                                 * htotal * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_c;
1519                 disp_dlg_regs->refcyc_per_meta_chunk_flip_c = (unsigned int) (dst_y_per_row_flip
1520                                 * htotal * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_c;
1521         }
1522
1523         disp_dlg_regs->refcyc_per_vm_group_vblank   = get_refcyc_per_vm_group_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz;
1524         disp_dlg_regs->refcyc_per_vm_group_flip     = get_refcyc_per_vm_group_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz;
1525         disp_dlg_regs->refcyc_per_vm_req_vblank     = get_refcyc_per_vm_req_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10);
1526         disp_dlg_regs->refcyc_per_vm_req_flip       = get_refcyc_per_vm_req_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10);
1527
1528         // Clamp to max for now
1529         if (disp_dlg_regs->refcyc_per_vm_group_vblank >= (unsigned int)dml_pow(2, 23))
1530                 disp_dlg_regs->refcyc_per_vm_group_vblank = dml_pow(2, 23) - 1;
1531
1532         if (disp_dlg_regs->refcyc_per_vm_group_flip >= (unsigned int)dml_pow(2, 23))
1533                 disp_dlg_regs->refcyc_per_vm_group_flip = dml_pow(2, 23) - 1;
1534
1535         if (disp_dlg_regs->refcyc_per_vm_req_vblank >= (unsigned int)dml_pow(2, 23))
1536                 disp_dlg_regs->refcyc_per_vm_req_vblank = dml_pow(2, 23) - 1;
1537
1538         if (disp_dlg_regs->refcyc_per_vm_req_flip >= (unsigned int)dml_pow(2, 23))
1539                 disp_dlg_regs->refcyc_per_vm_req_flip = dml_pow(2, 23) - 1;
1540         disp_dlg_regs->dst_y_per_pte_row_nom_l = (unsigned int) ((double) dpte_row_height_l
1541                         / (double) vratio_l * dml_pow(2, 2));
1542         ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int)dml_pow(2, 17));
1543
1544         if (dual_plane) {
1545                 disp_dlg_regs->dst_y_per_pte_row_nom_c = (unsigned int) ((double) dpte_row_height_c
1546                                 / (double) vratio_c * dml_pow(2, 2));
1547                 if (disp_dlg_regs->dst_y_per_pte_row_nom_c >= (unsigned int) dml_pow(2, 17)) {
1548                         dml_print(
1549                                         "DML_DLG: %s: Warning dst_y_per_pte_row_nom_c %u larger than supported by register format U15.2 %u\n",
1550                                         __func__,
1551                                         disp_dlg_regs->dst_y_per_pte_row_nom_c,
1552                                         (unsigned int)dml_pow(2, 17) - 1);
1553                 }
1554         }
1555
1556         disp_dlg_regs->dst_y_per_meta_row_nom_l = (unsigned int) ((double) meta_row_height_l
1557                         / (double) vratio_l * dml_pow(2, 2));
1558         ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int)dml_pow(2, 17));
1559
1560         disp_dlg_regs->dst_y_per_meta_row_nom_c = disp_dlg_regs->dst_y_per_meta_row_nom_l; // TODO: dcc for 4:2:0 is not supported in dcn1.0.  assigned to be the same as _l for now
1561
1562         dml_print(
1563                         "DML: Trow: %fus\n",
1564                         line_time_in_us * (double)dpte_row_height_l / (double)vratio_l);
1565
1566         disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int) ((double) dpte_row_height_l
1567                         / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq
1568                         / (double) dpte_groups_per_row_ub_l);
1569         if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23))
1570                 disp_dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1;
1571         disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int) ((double) meta_row_height_l
1572                         / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq
1573                         / (double) meta_chunks_per_row_ub_l);
1574         if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23))
1575                 disp_dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1;
1576
1577         if (dual_plane) {
1578                 disp_dlg_regs->refcyc_per_pte_group_nom_c =
1579                                 (unsigned int) ((double) dpte_row_height_c / (double) vratio_c
1580                                                 * (double) htotal * ref_freq_to_pix_freq
1581                                                 / (double) dpte_groups_per_row_ub_c);
1582                 if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23))
1583                         disp_dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1;
1584
1585                 // TODO: Is this the right calculation? Does htotal need to be halved?
1586                 disp_dlg_regs->refcyc_per_meta_chunk_nom_c =
1587                                 (unsigned int) ((double) meta_row_height_c / (double) vratio_c
1588                                                 * (double) htotal * ref_freq_to_pix_freq
1589                                                 / (double) meta_chunks_per_row_ub_c);
1590                 if (disp_dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int) dml_pow(2, 23))
1591                         disp_dlg_regs->refcyc_per_meta_chunk_nom_c = dml_pow(2, 23) - 1;
1592         }
1593
1594         disp_dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int) dml_floor(
1595                         refcyc_per_line_delivery_pre_l, 1);
1596         disp_dlg_regs->refcyc_per_line_delivery_l = (unsigned int) dml_floor(
1597                         refcyc_per_line_delivery_l, 1);
1598         ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int)dml_pow(2, 13));
1599         ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int)dml_pow(2, 13));
1600
1601         disp_dlg_regs->refcyc_per_line_delivery_pre_c = (unsigned int) dml_floor(
1602                         refcyc_per_line_delivery_pre_c, 1);
1603         disp_dlg_regs->refcyc_per_line_delivery_c = (unsigned int) dml_floor(
1604                         refcyc_per_line_delivery_c, 1);
1605         ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int)dml_pow(2, 13));
1606         ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int)dml_pow(2, 13));
1607
1608         disp_dlg_regs->chunk_hdl_adjust_cur0 = 3;
1609         disp_dlg_regs->dst_y_offset_cur0 = 0;
1610         disp_dlg_regs->chunk_hdl_adjust_cur1 = 3;
1611         disp_dlg_regs->dst_y_offset_cur1 = 0;
1612
1613         disp_dlg_regs->xfc_reg_transfer_delay = xfc_transfer_delay;
1614         disp_dlg_regs->xfc_reg_precharge_delay = xfc_precharge_delay;
1615         disp_dlg_regs->xfc_reg_remote_surface_flip_latency = xfc_remote_surface_flip_latency;
1616         disp_dlg_regs->xfc_reg_prefetch_margin = dml_ceil(
1617                         xfc_prefetch_margin * refclk_freq_in_mhz, 1);
1618
1619         // slave has to have this value also set to off
1620         if (src->xfc_enable && !src->xfc_slave)
1621                 disp_dlg_regs->dst_y_delta_drq_limit = dml_ceil(xfc_dst_y_delta_drq_limit, 1);
1622         else
1623                 disp_dlg_regs->dst_y_delta_drq_limit = 0x7fff; // off
1624
1625         disp_ttu_regs->refcyc_per_req_delivery_pre_l = (unsigned int) (refcyc_per_req_delivery_pre_l
1626                         * dml_pow(2, 10));
1627         disp_ttu_regs->refcyc_per_req_delivery_l = (unsigned int) (refcyc_per_req_delivery_l
1628                         * dml_pow(2, 10));
1629         disp_ttu_regs->refcyc_per_req_delivery_pre_c = (unsigned int) (refcyc_per_req_delivery_pre_c
1630                         * dml_pow(2, 10));
1631         disp_ttu_regs->refcyc_per_req_delivery_c = (unsigned int) (refcyc_per_req_delivery_c
1632                         * dml_pow(2, 10));
1633         disp_ttu_regs->refcyc_per_req_delivery_pre_cur0 =
1634                         (unsigned int) (refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10));
1635         disp_ttu_regs->refcyc_per_req_delivery_cur0 = (unsigned int) (refcyc_per_req_delivery_cur0
1636                         * dml_pow(2, 10));
1637         disp_ttu_regs->refcyc_per_req_delivery_pre_cur1 =
1638                         (unsigned int) (refcyc_per_req_delivery_pre_cur1 * dml_pow(2, 10));
1639         disp_ttu_regs->refcyc_per_req_delivery_cur1 = (unsigned int) (refcyc_per_req_delivery_cur1
1640                         * dml_pow(2, 10));
1641         disp_ttu_regs->qos_level_low_wm = 0;
1642         ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14));
1643         disp_ttu_regs->qos_level_high_wm = (unsigned int) (4.0 * (double) htotal
1644                         * ref_freq_to_pix_freq);
1645         ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14));
1646
1647         disp_ttu_regs->qos_level_flip = 14;
1648         disp_ttu_regs->qos_level_fixed_l = 8;
1649         disp_ttu_regs->qos_level_fixed_c = 8;
1650         disp_ttu_regs->qos_level_fixed_cur0 = 8;
1651         disp_ttu_regs->qos_ramp_disable_l = 0;
1652         disp_ttu_regs->qos_ramp_disable_c = 0;
1653         disp_ttu_regs->qos_ramp_disable_cur0 = 0;
1654
1655         disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz;
1656         ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24));
1657
1658         print__ttu_regs_st(mode_lib, *disp_ttu_regs);
1659         print__dlg_regs_st(mode_lib, *disp_dlg_regs);
1660 }
1661
1662 void dml21_rq_dlg_get_dlg_reg(
1663                 struct display_mode_lib *mode_lib,
1664                 display_dlg_regs_st *dlg_regs,
1665                 display_ttu_regs_st *ttu_regs,
1666                 display_e2e_pipe_params_st *e2e_pipe_param,
1667                 const unsigned int num_pipes,
1668                 const unsigned int pipe_idx,
1669                 const bool cstate_en,
1670                 const bool pstate_en,
1671                 const bool vm_en,
1672                 const bool ignore_viewport_pos,
1673                 const bool immediate_flip_support)
1674 {
1675         display_rq_params_st rq_param = {0};
1676         display_dlg_sys_params_st dlg_sys_param = {0};
1677
1678         // Get watermark and Tex.
1679         dlg_sys_param.t_urg_wm_us = get_wm_urgent(mode_lib, e2e_pipe_param, num_pipes);
1680         dlg_sys_param.deepsleep_dcfclk_mhz = get_clk_dcf_deepsleep(
1681                         mode_lib,
1682                         e2e_pipe_param,
1683                         num_pipes);
1684         dlg_sys_param.t_extra_us = get_urgent_extra_latency(mode_lib, e2e_pipe_param, num_pipes);
1685         dlg_sys_param.mem_trip_us = get_wm_memory_trip(mode_lib, e2e_pipe_param, num_pipes);
1686         dlg_sys_param.t_mclk_wm_us = get_wm_dram_clock_change(mode_lib, e2e_pipe_param, num_pipes);
1687         dlg_sys_param.t_sr_wm_us = get_wm_stutter_enter_exit(mode_lib, e2e_pipe_param, num_pipes);
1688         dlg_sys_param.total_flip_bw = get_total_immediate_flip_bw(
1689                         mode_lib,
1690                         e2e_pipe_param,
1691                         num_pipes);
1692         dlg_sys_param.total_flip_bytes = get_total_immediate_flip_bytes(
1693                         mode_lib,
1694                         e2e_pipe_param,
1695                         num_pipes);
1696         dlg_sys_param.t_srx_delay_us = mode_lib->ip.dcfclk_cstate_latency
1697                         / dlg_sys_param.deepsleep_dcfclk_mhz; // TODO: Deprecated
1698
1699         print__dlg_sys_params_st(mode_lib, dlg_sys_param);
1700
1701         // system parameter calculation done
1702
1703         dml_print("DML_DLG: Calculation for pipe[%d] start\n\n", pipe_idx);
1704         dml_rq_dlg_get_rq_params(mode_lib, &rq_param, e2e_pipe_param[pipe_idx].pipe);
1705         dml_rq_dlg_get_dlg_params(
1706                         mode_lib,
1707                         e2e_pipe_param,
1708                         num_pipes,
1709                         pipe_idx,
1710                         dlg_regs,
1711                         ttu_regs,
1712                         rq_param.dlg,
1713                         dlg_sys_param,
1714                         cstate_en,
1715                         pstate_en);
1716         dml_print("DML_DLG: Calculation for pipe[%d] end\n", pipe_idx);
1717 }
1718
1719 void dml_rq_dlg_get_arb_params(struct display_mode_lib *mode_lib, display_arb_params_st *arb_param)
1720 {
1721         memset(arb_param, 0, sizeof(*arb_param));
1722         arb_param->max_req_outstanding = 256;
1723         arb_param->min_req_outstanding = 68;
1724         arb_param->sat_level_us = 60;
1725 }
1726
1727 static void calculate_ttu_cursor(
1728                 struct display_mode_lib *mode_lib,
1729                 double *refcyc_per_req_delivery_pre_cur,
1730                 double *refcyc_per_req_delivery_cur,
1731                 double refclk_freq_in_mhz,
1732                 double ref_freq_to_pix_freq,
1733                 double hscale_pixel_rate_l,
1734                 double hscl_ratio,
1735                 double vratio_pre_l,
1736                 double vratio_l,
1737                 unsigned int cur_width,
1738                 enum cursor_bpp cur_bpp)
1739 {
1740         unsigned int cur_src_width = cur_width;
1741         unsigned int cur_req_size = 0;
1742         unsigned int cur_req_width = 0;
1743         double cur_width_ub = 0.0;
1744         double cur_req_per_width = 0.0;
1745         double hactive_cur = 0.0;
1746
1747         ASSERT(cur_src_width <= 256);
1748
1749         *refcyc_per_req_delivery_pre_cur = 0.0;
1750         *refcyc_per_req_delivery_cur = 0.0;
1751         if (cur_src_width > 0) {
1752                 unsigned int cur_bit_per_pixel = 0;
1753
1754                 if (cur_bpp == dm_cur_2bit) {
1755                         cur_req_size = 64; // byte
1756                         cur_bit_per_pixel = 2;
1757                 } else { // 32bit
1758                         cur_bit_per_pixel = 32;
1759                         if (cur_src_width >= 1 && cur_src_width <= 16)
1760                                 cur_req_size = 64;
1761                         else if (cur_src_width >= 17 && cur_src_width <= 31)
1762                                 cur_req_size = 128;
1763                         else
1764                                 cur_req_size = 256;
1765                 }
1766
1767                 cur_req_width = (double) cur_req_size / ((double) cur_bit_per_pixel / 8.0);
1768                 cur_width_ub = dml_ceil((double) cur_src_width / (double) cur_req_width, 1)
1769                                 * (double) cur_req_width;
1770                 cur_req_per_width = cur_width_ub / (double) cur_req_width;
1771                 hactive_cur = (double) cur_src_width / hscl_ratio; // FIXME: oswin to think about what to do for cursor
1772
1773                 if (vratio_pre_l <= 1.0) {
1774                         *refcyc_per_req_delivery_pre_cur = hactive_cur * ref_freq_to_pix_freq
1775                                         / (double) cur_req_per_width;
1776                 } else {
1777                         *refcyc_per_req_delivery_pre_cur = (double) refclk_freq_in_mhz
1778                                         * (double) cur_src_width / hscale_pixel_rate_l
1779                                         / (double) cur_req_per_width;
1780                 }
1781
1782                 ASSERT(*refcyc_per_req_delivery_pre_cur < dml_pow(2, 13));
1783
1784                 if (vratio_l <= 1.0) {
1785                         *refcyc_per_req_delivery_cur = hactive_cur * ref_freq_to_pix_freq
1786                                         / (double) cur_req_per_width;
1787                 } else {
1788                         *refcyc_per_req_delivery_cur = (double) refclk_freq_in_mhz
1789                                         * (double) cur_src_width / hscale_pixel_rate_l
1790                                         / (double) cur_req_per_width;
1791                 }
1792
1793                 dml_print(
1794                                 "DML_DLG: %s: cur_req_width                     = %d\n",
1795                                 __func__,
1796                                 cur_req_width);
1797                 dml_print(
1798                                 "DML_DLG: %s: cur_width_ub                      = %3.2f\n",
1799                                 __func__,
1800                                 cur_width_ub);
1801                 dml_print(
1802                                 "DML_DLG: %s: cur_req_per_width                 = %3.2f\n",
1803                                 __func__,
1804                                 cur_req_per_width);
1805                 dml_print(
1806                                 "DML_DLG: %s: hactive_cur                       = %3.2f\n",
1807                                 __func__,
1808                                 hactive_cur);
1809                 dml_print(
1810                                 "DML_DLG: %s: refcyc_per_req_delivery_pre_cur   = %3.2f\n",
1811                                 __func__,
1812                                 *refcyc_per_req_delivery_pre_cur);
1813                 dml_print(
1814                                 "DML_DLG: %s: refcyc_per_req_delivery_cur       = %3.2f\n",
1815                                 __func__,
1816                                 *refcyc_per_req_delivery_cur);
1817
1818                 ASSERT(*refcyc_per_req_delivery_cur < dml_pow(2, 13));
1819         }
1820 }
1821