drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright 2021 Advanced Micro Devices, Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: AMD
  24  *
  25  */
  26
  27 #include "resource.h"
  28 #include "clk_mgr.h"
  29 #include "dc_link_dp.h"
  30 #include "dchubbub.h"
  31 #include "dcn20/dcn20_resource.h"
  32 #include "dcn21/dcn21_resource.h"
  33
  34 #include "dcn20_fpu.h"
  35
  36 #define DC_LOGGER_INIT(logger)
  37
  38 #ifndef MAX
  39 #define MAX(X, Y) ((X) > (Y) ? (X) : (Y))
  40 #endif
  41 #ifndef MIN
  42 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
  43 #endif
  44
  45 /**
  46  * DOC: DCN2x FPU manipulation Overview
  47  *
  48  * The DCN architecture relies on FPU operations, which require special
  49  * compilation flags and the use of kernel_fpu_begin/end functions; ideally, we
  50  * want to avoid spreading FPU access across multiple files. With this idea in
  51  * mind, this file aims to centralize all DCN20 and DCN2.1 (DCN2x) functions
  52  * that require FPU access in a single place. Code in this file follows the
  53  * following code pattern:
  54  *
  55  * 1. Functions that use FPU operations should be isolated in static functions.
  56  * 2. The FPU functions should have the noinline attribute to ensure anything
  57  *    that deals with FP register is contained within this call.
  58  * 3. All function that needs to be accessed outside this file requires a
  59  *    public interface that not uses any FPU reference.
  60  * 4. Developers **must not** use DC_FP_START/END in this file, but they need
  61  *    to ensure that the caller invokes it before access any function available
  62  *    in this file. For this reason, public functions in this file must invoke
  63  *    dc_assert_fp_enabled();
  64  *
  65  * Let's expand a little bit more the idea in the code pattern. To fully
  66  * isolate FPU operations in a single place, we must avoid situations where
  67  * compilers spill FP values to registers due to FP enable in a specific C
  68  * file. Note that even if we isolate all FPU functions in a single file and
  69  * call its interface from other files, the compiler might enable the use of
  70  * FPU before we call DC_FP_START. Nevertheless, it is the programmer's
  71  * responsibility to invoke DC_FP_START/END in the correct place. To highlight
  72  * situations where developers forgot to use the FP protection before calling
  73  * the DC FPU interface functions, we introduce a helper that checks if the
  74  * function is invoked under FP protection. If not, it will trigger a kernel
  75  * warning.
  76  */
  77
  78 struct _vcs_dpi_ip_params_st dcn2_0_ip = {
  79         .odm_capable = 1,
  80         .gpuvm_enable = 0,
  81         .hostvm_enable = 0,
  82         .gpuvm_max_page_table_levels = 4,
  83         .hostvm_max_page_table_levels = 4,
  84         .hostvm_cached_page_table_levels = 0,
  85         .pte_group_size_bytes = 2048,
  86         .num_dsc = 6,
  87         .rob_buffer_size_kbytes = 168,
  88         .det_buffer_size_kbytes = 164,
  89         .dpte_buffer_size_in_pte_reqs_luma = 84,
  90         .pde_proc_buffer_size_64k_reqs = 48,
  91         .dpp_output_buffer_pixels = 2560,
  92         .opp_output_buffer_lines = 1,
  93         .pixel_chunk_size_kbytes = 8,
  94         .pte_chunk_size_kbytes = 2,
  95         .meta_chunk_size_kbytes = 2,
  96         .writeback_chunk_size_kbytes = 2,
  97         .line_buffer_size_bits = 789504,
  98         .is_line_buffer_bpp_fixed = 0,
  99         .line_buffer_fixed_bpp = 0,
 100         .dcc_supported = true,
 101         .max_line_buffer_lines = 12,
 102         .writeback_luma_buffer_size_kbytes = 12,
 103         .writeback_chroma_buffer_size_kbytes = 8,
 104         .writeback_chroma_line_buffer_width_pixels = 4,
 105         .writeback_max_hscl_ratio = 1,
 106         .writeback_max_vscl_ratio = 1,
 107         .writeback_min_hscl_ratio = 1,
 108         .writeback_min_vscl_ratio = 1,
 109         .writeback_max_hscl_taps = 12,
 110         .writeback_max_vscl_taps = 12,
 111         .writeback_line_buffer_luma_buffer_size = 0,
 112         .writeback_line_buffer_chroma_buffer_size = 14643,
 113         .cursor_buffer_size = 8,
 114         .cursor_chunk_size = 2,
 115         .max_num_otg = 6,
 116         .max_num_dpp = 6,
 117         .max_num_wb = 1,
 118         .max_dchub_pscl_bw_pix_per_clk = 4,
 119         .max_pscl_lb_bw_pix_per_clk = 2,
 120         .max_lb_vscl_bw_pix_per_clk = 4,
 121         .max_vscl_hscl_bw_pix_per_clk = 4,
 122         .max_hscl_ratio = 8,
 123         .max_vscl_ratio = 8,
 124         .hscl_mults = 4,
 125         .vscl_mults = 4,
 126         .max_hscl_taps = 8,
 127         .max_vscl_taps = 8,
 128         .dispclk_ramp_margin_percent = 1,
 129         .underscan_factor = 1.10,
 130         .min_vblank_lines = 32, //
 131         .dppclk_delay_subtotal = 77, //
 132         .dppclk_delay_scl_lb_only = 16,
 133         .dppclk_delay_scl = 50,
 134         .dppclk_delay_cnvc_formatter = 8,
 135         .dppclk_delay_cnvc_cursor = 6,
 136         .dispclk_delay_subtotal = 87, //
 137         .dcfclk_cstate_latency = 10, // SRExitTime
 138         .max_inter_dcn_tile_repeaters = 8,
 139         .xfc_supported = true,
 140         .xfc_fill_bw_overhead_percent = 10.0,
 141         .xfc_fill_constant_bytes = 0,
 142         .number_of_cursors = 1,
 143 };
 144
 145 struct _vcs_dpi_ip_params_st dcn2_0_nv14_ip = {
 146         .odm_capable = 1,
 147         .gpuvm_enable = 0,
 148         .hostvm_enable = 0,
 149         .gpuvm_max_page_table_levels = 4,
 150         .hostvm_max_page_table_levels = 4,
 151         .hostvm_cached_page_table_levels = 0,
 152         .num_dsc = 5,
 153         .rob_buffer_size_kbytes = 168,
 154         .det_buffer_size_kbytes = 164,
 155         .dpte_buffer_size_in_pte_reqs_luma = 84,
 156         .dpte_buffer_size_in_pte_reqs_chroma = 42,//todo
 157         .dpp_output_buffer_pixels = 2560,
 158         .opp_output_buffer_lines = 1,
 159         .pixel_chunk_size_kbytes = 8,
 160         .pte_enable = 1,
 161         .max_page_table_levels = 4,
 162         .pte_chunk_size_kbytes = 2,
 163         .meta_chunk_size_kbytes = 2,
 164         .writeback_chunk_size_kbytes = 2,
 165         .line_buffer_size_bits = 789504,
 166         .is_line_buffer_bpp_fixed = 0,
 167         .line_buffer_fixed_bpp = 0,
 168         .dcc_supported = true,
 169         .max_line_buffer_lines = 12,
 170         .writeback_luma_buffer_size_kbytes = 12,
 171         .writeback_chroma_buffer_size_kbytes = 8,
 172         .writeback_chroma_line_buffer_width_pixels = 4,
 173         .writeback_max_hscl_ratio = 1,
 174         .writeback_max_vscl_ratio = 1,
 175         .writeback_min_hscl_ratio = 1,
 176         .writeback_min_vscl_ratio = 1,
 177         .writeback_max_hscl_taps = 12,
 178         .writeback_max_vscl_taps = 12,
 179         .writeback_line_buffer_luma_buffer_size = 0,
 180         .writeback_line_buffer_chroma_buffer_size = 14643,
 181         .cursor_buffer_size = 8,
 182         .cursor_chunk_size = 2,
 183         .max_num_otg = 5,
 184         .max_num_dpp = 5,
 185         .max_num_wb = 1,
 186         .max_dchub_pscl_bw_pix_per_clk = 4,
 187         .max_pscl_lb_bw_pix_per_clk = 2,
 188         .max_lb_vscl_bw_pix_per_clk = 4,
 189         .max_vscl_hscl_bw_pix_per_clk = 4,
 190         .max_hscl_ratio = 8,
 191         .max_vscl_ratio = 8,
 192         .hscl_mults = 4,
 193         .vscl_mults = 4,
 194         .max_hscl_taps = 8,
 195         .max_vscl_taps = 8,
 196         .dispclk_ramp_margin_percent = 1,
 197         .underscan_factor = 1.10,
 198         .min_vblank_lines = 32, //
 199         .dppclk_delay_subtotal = 77, //
 200         .dppclk_delay_scl_lb_only = 16,
 201         .dppclk_delay_scl = 50,
 202         .dppclk_delay_cnvc_formatter = 8,
 203         .dppclk_delay_cnvc_cursor = 6,
 204         .dispclk_delay_subtotal = 87, //
 205         .dcfclk_cstate_latency = 10, // SRExitTime
 206         .max_inter_dcn_tile_repeaters = 8,
 207         .xfc_supported = true,
 208         .xfc_fill_bw_overhead_percent = 10.0,
 209         .xfc_fill_constant_bytes = 0,
 210         .ptoi_supported = 0,
 211         .number_of_cursors = 1,
 212 };
 213
 214 struct _vcs_dpi_soc_bounding_box_st dcn2_0_soc = {
 215         /* Defaults that get patched on driver load from firmware. */
 216         .clock_limits = {
 217                         {
 218                                 .state = 0,
 219                                 .dcfclk_mhz = 560.0,
 220                                 .fabricclk_mhz = 560.0,
 221                                 .dispclk_mhz = 513.0,
 222                                 .dppclk_mhz = 513.0,
 223                                 .phyclk_mhz = 540.0,
 224                                 .socclk_mhz = 560.0,
 225                                 .dscclk_mhz = 171.0,
 226                                 .dram_speed_mts = 8960.0,
 227                         },
 228                         {
 229                                 .state = 1,
 230                                 .dcfclk_mhz = 694.0,
 231                                 .fabricclk_mhz = 694.0,
 232                                 .dispclk_mhz = 642.0,
 233                                 .dppclk_mhz = 642.0,
 234                                 .phyclk_mhz = 600.0,
 235                                 .socclk_mhz = 694.0,
 236                                 .dscclk_mhz = 214.0,
 237                                 .dram_speed_mts = 11104.0,
 238                         },
 239                         {
 240                                 .state = 2,
 241                                 .dcfclk_mhz = 875.0,
 242                                 .fabricclk_mhz = 875.0,
 243                                 .dispclk_mhz = 734.0,
 244                                 .dppclk_mhz = 734.0,
 245                                 .phyclk_mhz = 810.0,
 246                                 .socclk_mhz = 875.0,
 247                                 .dscclk_mhz = 245.0,
 248                                 .dram_speed_mts = 14000.0,
 249                         },
 250                         {
 251                                 .state = 3,
 252                                 .dcfclk_mhz = 1000.0,
 253                                 .fabricclk_mhz = 1000.0,
 254                                 .dispclk_mhz = 1100.0,
 255                                 .dppclk_mhz = 1100.0,
 256                                 .phyclk_mhz = 810.0,
 257                                 .socclk_mhz = 1000.0,
 258                                 .dscclk_mhz = 367.0,
 259                                 .dram_speed_mts = 16000.0,
 260                         },
 261                         {
 262                                 .state = 4,
 263                                 .dcfclk_mhz = 1200.0,
 264                                 .fabricclk_mhz = 1200.0,
 265                                 .dispclk_mhz = 1284.0,
 266                                 .dppclk_mhz = 1284.0,
 267                                 .phyclk_mhz = 810.0,
 268                                 .socclk_mhz = 1200.0,
 269                                 .dscclk_mhz = 428.0,
 270                                 .dram_speed_mts = 16000.0,
 271                         },
 272                         /*Extra state, no dispclk ramping*/
 273                         {
 274                                 .state = 5,
 275                                 .dcfclk_mhz = 1200.0,
 276                                 .fabricclk_mhz = 1200.0,
 277                                 .dispclk_mhz = 1284.0,
 278                                 .dppclk_mhz = 1284.0,
 279                                 .phyclk_mhz = 810.0,
 280                                 .socclk_mhz = 1200.0,
 281                                 .dscclk_mhz = 428.0,
 282                                 .dram_speed_mts = 16000.0,
 283                         },
 284                 },
 285         .num_states = 5,
 286         .sr_exit_time_us = 8.6,
 287         .sr_enter_plus_exit_time_us = 10.9,
 288         .urgent_latency_us = 4.0,
 289         .urgent_latency_pixel_data_only_us = 4.0,
 290         .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
 291         .urgent_latency_vm_data_only_us = 4.0,
 292         .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
 293         .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
 294         .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
 295         .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0,
 296         .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0,
 297         .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
 298         .max_avg_sdp_bw_use_normal_percent = 40.0,
 299         .max_avg_dram_bw_use_normal_percent = 40.0,
 300         .writeback_latency_us = 12.0,
 301         .ideal_dram_bw_after_urgent_percent = 40.0,
 302         .max_request_size_bytes = 256,
 303         .dram_channel_width_bytes = 2,
 304         .fabric_datapath_to_dcn_data_return_bytes = 64,
 305         .dcn_downspread_percent = 0.5,
 306         .downspread_percent = 0.38,
 307         .dram_page_open_time_ns = 50.0,
 308         .dram_rw_turnaround_time_ns = 17.5,
 309         .dram_return_buffer_per_channel_bytes = 8192,
 310         .round_trip_ping_latency_dcfclk_cycles = 131,
 311         .urgent_out_of_order_return_per_channel_bytes = 256,
 312         .channel_interleave_bytes = 256,
 313         .num_banks = 8,
 314         .num_chans = 16,
 315         .vmm_page_size_bytes = 4096,
 316         .dram_clock_change_latency_us = 404.0,
 317         .dummy_pstate_latency_us = 5.0,
 318         .writeback_dram_clock_change_latency_us = 23.0,
 319         .return_bus_width_bytes = 64,
 320         .dispclk_dppclk_vco_speed_mhz = 3850,
 321         .xfc_bus_transport_time_us = 20,
 322         .xfc_xbuf_latency_tolerance_us = 4,
 323         .use_urgent_burst_bw = 0
 324 };
 325
 326 struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv14_soc = {
 327         .clock_limits = {
 328                         {
 329                                 .state = 0,
 330                                 .dcfclk_mhz = 560.0,
 331                                 .fabricclk_mhz = 560.0,
 332                                 .dispclk_mhz = 513.0,
 333                                 .dppclk_mhz = 513.0,
 334                                 .phyclk_mhz = 540.0,
 335                                 .socclk_mhz = 560.0,
 336                                 .dscclk_mhz = 171.0,
 337                                 .dram_speed_mts = 8960.0,
 338                         },
 339                         {
 340                                 .state = 1,
 341                                 .dcfclk_mhz = 694.0,
 342                                 .fabricclk_mhz = 694.0,
 343                                 .dispclk_mhz = 642.0,
 344                                 .dppclk_mhz = 642.0,
 345                                 .phyclk_mhz = 600.0,
 346                                 .socclk_mhz = 694.0,
 347                                 .dscclk_mhz = 214.0,
 348                                 .dram_speed_mts = 11104.0,
 349                         },
 350                         {
 351                                 .state = 2,
 352                                 .dcfclk_mhz = 875.0,
 353                                 .fabricclk_mhz = 875.0,
 354                                 .dispclk_mhz = 734.0,
 355                                 .dppclk_mhz = 734.0,
 356                                 .phyclk_mhz = 810.0,
 357                                 .socclk_mhz = 875.0,
 358                                 .dscclk_mhz = 245.0,
 359                                 .dram_speed_mts = 14000.0,
 360                         },
 361                         {
 362                                 .state = 3,
 363                                 .dcfclk_mhz = 1000.0,
 364                                 .fabricclk_mhz = 1000.0,
 365                                 .dispclk_mhz = 1100.0,
 366                                 .dppclk_mhz = 1100.0,
 367                                 .phyclk_mhz = 810.0,
 368                                 .socclk_mhz = 1000.0,
 369                                 .dscclk_mhz = 367.0,
 370                                 .dram_speed_mts = 16000.0,
 371                         },
 372                         {
 373                                 .state = 4,
 374                                 .dcfclk_mhz = 1200.0,
 375                                 .fabricclk_mhz = 1200.0,
 376                                 .dispclk_mhz = 1284.0,
 377                                 .dppclk_mhz = 1284.0,
 378                                 .phyclk_mhz = 810.0,
 379                                 .socclk_mhz = 1200.0,
 380                                 .dscclk_mhz = 428.0,
 381                                 .dram_speed_mts = 16000.0,
 382                         },
 383                         /*Extra state, no dispclk ramping*/
 384                         {
 385                                 .state = 5,
 386                                 .dcfclk_mhz = 1200.0,
 387                                 .fabricclk_mhz = 1200.0,
 388                                 .dispclk_mhz = 1284.0,
 389                                 .dppclk_mhz = 1284.0,
 390                                 .phyclk_mhz = 810.0,
 391                                 .socclk_mhz = 1200.0,
 392                                 .dscclk_mhz = 428.0,
 393                                 .dram_speed_mts = 16000.0,
 394                         },
 395                 },
 396         .num_states = 5,
 397         .sr_exit_time_us = 11.6,
 398         .sr_enter_plus_exit_time_us = 13.9,
 399         .urgent_latency_us = 4.0,
 400         .urgent_latency_pixel_data_only_us = 4.0,
 401         .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
 402         .urgent_latency_vm_data_only_us = 4.0,
 403         .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
 404         .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
 405         .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
 406         .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0,
 407         .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0,
 408         .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
 409         .max_avg_sdp_bw_use_normal_percent = 40.0,
 410         .max_avg_dram_bw_use_normal_percent = 40.0,
 411         .writeback_latency_us = 12.0,
 412         .ideal_dram_bw_after_urgent_percent = 40.0,
 413         .max_request_size_bytes = 256,
 414         .dram_channel_width_bytes = 2,
 415         .fabric_datapath_to_dcn_data_return_bytes = 64,
 416         .dcn_downspread_percent = 0.5,
 417         .downspread_percent = 0.38,
 418         .dram_page_open_time_ns = 50.0,
 419         .dram_rw_turnaround_time_ns = 17.5,
 420         .dram_return_buffer_per_channel_bytes = 8192,
 421         .round_trip_ping_latency_dcfclk_cycles = 131,
 422         .urgent_out_of_order_return_per_channel_bytes = 256,
 423         .channel_interleave_bytes = 256,
 424         .num_banks = 8,
 425         .num_chans = 8,
 426         .vmm_page_size_bytes = 4096,
 427         .dram_clock_change_latency_us = 404.0,
 428         .dummy_pstate_latency_us = 5.0,
 429         .writeback_dram_clock_change_latency_us = 23.0,
 430         .return_bus_width_bytes = 64,
 431         .dispclk_dppclk_vco_speed_mhz = 3850,
 432         .xfc_bus_transport_time_us = 20,
 433         .xfc_xbuf_latency_tolerance_us = 4,
 434         .use_urgent_burst_bw = 0
 435 };
 436
 437 struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv12_soc = { 0 };
 438
 439 struct _vcs_dpi_ip_params_st dcn2_1_ip = {
 440         .odm_capable = 1,
 441         .gpuvm_enable = 1,
 442         .hostvm_enable = 1,
 443         .gpuvm_max_page_table_levels = 1,
 444         .hostvm_max_page_table_levels = 4,
 445         .hostvm_cached_page_table_levels = 2,
 446         .num_dsc = 3,
 447         .rob_buffer_size_kbytes = 168,
 448         .det_buffer_size_kbytes = 164,
 449         .dpte_buffer_size_in_pte_reqs_luma = 44,
 450         .dpte_buffer_size_in_pte_reqs_chroma = 42,//todo
 451         .dpp_output_buffer_pixels = 2560,
 452         .opp_output_buffer_lines = 1,
 453         .pixel_chunk_size_kbytes = 8,
 454         .pte_enable = 1,
 455         .max_page_table_levels = 4,
 456         .pte_chunk_size_kbytes = 2,
 457         .meta_chunk_size_kbytes = 2,
 458         .min_meta_chunk_size_bytes = 256,
 459         .writeback_chunk_size_kbytes = 2,
 460         .line_buffer_size_bits = 789504,
 461         .is_line_buffer_bpp_fixed = 0,
 462         .line_buffer_fixed_bpp = 0,
 463         .dcc_supported = true,
 464         .max_line_buffer_lines = 12,
 465         .writeback_luma_buffer_size_kbytes = 12,
 466         .writeback_chroma_buffer_size_kbytes = 8,
 467         .writeback_chroma_line_buffer_width_pixels = 4,
 468         .writeback_max_hscl_ratio = 1,
 469         .writeback_max_vscl_ratio = 1,
 470         .writeback_min_hscl_ratio = 1,
 471         .writeback_min_vscl_ratio = 1,
 472         .writeback_max_hscl_taps = 12,
 473         .writeback_max_vscl_taps = 12,
 474         .writeback_line_buffer_luma_buffer_size = 0,
 475         .writeback_line_buffer_chroma_buffer_size = 14643,
 476         .cursor_buffer_size = 8,
 477         .cursor_chunk_size = 2,
 478         .max_num_otg = 4,
 479         .max_num_dpp = 4,
 480         .max_num_wb = 1,
 481         .max_dchub_pscl_bw_pix_per_clk = 4,
 482         .max_pscl_lb_bw_pix_per_clk = 2,
 483         .max_lb_vscl_bw_pix_per_clk = 4,
 484         .max_vscl_hscl_bw_pix_per_clk = 4,
 485         .max_hscl_ratio = 4,
 486         .max_vscl_ratio = 4,
 487         .hscl_mults = 4,
 488         .vscl_mults = 4,
 489         .max_hscl_taps = 8,
 490         .max_vscl_taps = 8,
 491         .dispclk_ramp_margin_percent = 1,
 492         .underscan_factor = 1.10,
 493         .min_vblank_lines = 32, //
 494         .dppclk_delay_subtotal = 77, //
 495         .dppclk_delay_scl_lb_only = 16,
 496         .dppclk_delay_scl = 50,
 497         .dppclk_delay_cnvc_formatter = 8,
 498         .dppclk_delay_cnvc_cursor = 6,
 499         .dispclk_delay_subtotal = 87, //
 500         .dcfclk_cstate_latency = 10, // SRExitTime
 501         .max_inter_dcn_tile_repeaters = 8,
 502
 503         .xfc_supported = false,
 504         .xfc_fill_bw_overhead_percent = 10.0,
 505         .xfc_fill_constant_bytes = 0,
 506         .ptoi_supported = 0,
 507         .number_of_cursors = 1,
 508 };
 509
 510 struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = {
 511         .clock_limits = {
 512                         {
 513                                 .state = 0,
 514                                 .dcfclk_mhz = 400.0,
 515                                 .fabricclk_mhz = 400.0,
 516                                 .dispclk_mhz = 600.0,
 517                                 .dppclk_mhz = 400.00,
 518                                 .phyclk_mhz = 600.0,
 519                                 .socclk_mhz = 278.0,
 520                                 .dscclk_mhz = 205.67,
 521                                 .dram_speed_mts = 1600.0,
 522                         },
 523                         {
 524                                 .state = 1,
 525                                 .dcfclk_mhz = 464.52,
 526                                 .fabricclk_mhz = 800.0,
 527                                 .dispclk_mhz = 654.55,
 528                                 .dppclk_mhz = 626.09,
 529                                 .phyclk_mhz = 600.0,
 530                                 .socclk_mhz = 278.0,
 531                                 .dscclk_mhz = 205.67,
 532                                 .dram_speed_mts = 1600.0,
 533                         },
 534                         {
 535                                 .state = 2,
 536                                 .dcfclk_mhz = 514.29,
 537                                 .fabricclk_mhz = 933.0,
 538                                 .dispclk_mhz = 757.89,
 539                                 .dppclk_mhz = 685.71,
 540                                 .phyclk_mhz = 600.0,
 541                                 .socclk_mhz = 278.0,
 542                                 .dscclk_mhz = 287.67,
 543                                 .dram_speed_mts = 1866.0,
 544                         },
 545                         {
 546                                 .state = 3,
 547                                 .dcfclk_mhz = 576.00,
 548                                 .fabricclk_mhz = 1067.0,
 549                                 .dispclk_mhz = 847.06,
 550                                 .dppclk_mhz = 757.89,
 551                                 .phyclk_mhz = 600.0,
 552                                 .socclk_mhz = 715.0,
 553                                 .dscclk_mhz = 318.334,
 554                                 .dram_speed_mts = 2134.0,
 555                         },
 556                         {
 557                                 .state = 4,
 558                                 .dcfclk_mhz = 626.09,
 559                                 .fabricclk_mhz = 1200.0,
 560                                 .dispclk_mhz = 900.00,
 561                                 .dppclk_mhz = 847.06,
 562                                 .phyclk_mhz = 810.0,
 563                                 .socclk_mhz = 953.0,
 564                                 .dscclk_mhz = 489.0,
 565                                 .dram_speed_mts = 2400.0,
 566                         },
 567                         {
 568                                 .state = 5,
 569                                 .dcfclk_mhz = 685.71,
 570                                 .fabricclk_mhz = 1333.0,
 571                                 .dispclk_mhz = 1028.57,
 572                                 .dppclk_mhz = 960.00,
 573                                 .phyclk_mhz = 810.0,
 574                                 .socclk_mhz = 278.0,
 575                                 .dscclk_mhz = 287.67,
 576                                 .dram_speed_mts = 2666.0,
 577                         },
 578                         {
 579                                 .state = 6,
 580                                 .dcfclk_mhz = 757.89,
 581                                 .fabricclk_mhz = 1467.0,
 582                                 .dispclk_mhz = 1107.69,
 583                                 .dppclk_mhz = 1028.57,
 584                                 .phyclk_mhz = 810.0,
 585                                 .socclk_mhz = 715.0,
 586                                 .dscclk_mhz = 318.334,
 587                                 .dram_speed_mts = 3200.0,
 588                         },
 589                         {
 590                                 .state = 7,
 591                                 .dcfclk_mhz = 847.06,
 592                                 .fabricclk_mhz = 1600.0,
 593                                 .dispclk_mhz = 1395.0,
 594                                 .dppclk_mhz = 1285.00,
 595                                 .phyclk_mhz = 1325.0,
 596                                 .socclk_mhz = 953.0,
 597                                 .dscclk_mhz = 489.0,
 598                                 .dram_speed_mts = 4266.0,
 599                         },
 600                         /*Extra state, no dispclk ramping*/
 601                         {
 602                                 .state = 8,
 603                                 .dcfclk_mhz = 847.06,
 604                                 .fabricclk_mhz = 1600.0,
 605                                 .dispclk_mhz = 1395.0,
 606                                 .dppclk_mhz = 1285.0,
 607                                 .phyclk_mhz = 1325.0,
 608                                 .socclk_mhz = 953.0,
 609                                 .dscclk_mhz = 489.0,
 610                                 .dram_speed_mts = 4266.0,
 611                         },
 612
 613                 },
 614
 615         .sr_exit_time_us = 12.5,
 616         .sr_enter_plus_exit_time_us = 17.0,
 617         .urgent_latency_us = 4.0,
 618         .urgent_latency_pixel_data_only_us = 4.0,
 619         .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
 620         .urgent_latency_vm_data_only_us = 4.0,
 621         .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
 622         .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
 623         .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
 624         .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0,
 625         .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 75.0,
 626         .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
 627         .max_avg_sdp_bw_use_normal_percent = 60.0,
 628         .max_avg_dram_bw_use_normal_percent = 100.0,
 629         .writeback_latency_us = 12.0,
 630         .max_request_size_bytes = 256,
 631         .dram_channel_width_bytes = 4,
 632         .fabric_datapath_to_dcn_data_return_bytes = 32,
 633         .dcn_downspread_percent = 0.5,
 634         .downspread_percent = 0.38,
 635         .dram_page_open_time_ns = 50.0,
 636         .dram_rw_turnaround_time_ns = 17.5,
 637         .dram_return_buffer_per_channel_bytes = 8192,
 638         .round_trip_ping_latency_dcfclk_cycles = 128,
 639         .urgent_out_of_order_return_per_channel_bytes = 4096,
 640         .channel_interleave_bytes = 256,
 641         .num_banks = 8,
 642         .num_chans = 4,
 643         .vmm_page_size_bytes = 4096,
 644         .dram_clock_change_latency_us = 23.84,
 645         .return_bus_width_bytes = 64,
 646         .dispclk_dppclk_vco_speed_mhz = 3600,
 647         .xfc_bus_transport_time_us = 4,
 648         .xfc_xbuf_latency_tolerance_us = 4,
 649         .use_urgent_burst_bw = 1,
 650         .num_states = 8
 651 };
 652
 653 void dcn20_populate_dml_writeback_from_context(struct dc *dc,
 654                                                struct resource_context *res_ctx,
 655                                                display_e2e_pipe_params_st *pipes)
 656 {
 657         int pipe_cnt, i;
 658
 659         dc_assert_fp_enabled();
 660
 661         for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
 662                 struct dc_writeback_info *wb_info = &res_ctx->pipe_ctx[i].stream->writeback_info[0];
 663
 664                 if (!res_ctx->pipe_ctx[i].stream)
 665                         continue;
 666
 667                 /* Set writeback information */
 668                 pipes[pipe_cnt].dout.wb_enable = (wb_info->wb_enabled == true) ? 1 : 0;
 669                 pipes[pipe_cnt].dout.num_active_wb++;
 670                 pipes[pipe_cnt].dout.wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_height;
 671                 pipes[pipe_cnt].dout.wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_width;
 672                 pipes[pipe_cnt].dout.wb.wb_dst_width = wb_info->dwb_params.dest_width;
 673                 pipes[pipe_cnt].dout.wb.wb_dst_height = wb_info->dwb_params.dest_height;
 674                 pipes[pipe_cnt].dout.wb.wb_htaps_luma = 1;
 675                 pipes[pipe_cnt].dout.wb.wb_vtaps_luma = 1;
 676                 pipes[pipe_cnt].dout.wb.wb_htaps_chroma = wb_info->dwb_params.scaler_taps.h_taps_c;
 677                 pipes[pipe_cnt].dout.wb.wb_vtaps_chroma = wb_info->dwb_params.scaler_taps.v_taps_c;
 678                 pipes[pipe_cnt].dout.wb.wb_hratio = 1.0;
 679                 pipes[pipe_cnt].dout.wb.wb_vratio = 1.0;
 680                 if (wb_info->dwb_params.out_format == dwb_scaler_mode_yuv420) {
 681                         if (wb_info->dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC)
 682                                 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_8;
 683                         else
 684                                 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_10;
 685                 } else {
 686                         pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_444_32;
 687                 }
 688
 689                 pipe_cnt++;
 690         }
 691 }
 692
 693 void dcn20_fpu_set_wb_arb_params(struct mcif_arb_params *wb_arb_params,
 694                                 struct dc_state *context,
 695                                 display_e2e_pipe_params_st *pipes,
 696                                 int pipe_cnt, int i)
 697 {
 698        int k;
 699
 700        dc_assert_fp_enabled();
 701
 702        for (k = 0; k < sizeof(wb_arb_params->cli_watermark)/sizeof(wb_arb_params->cli_watermark[0]); k++) {
 703                wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 704                wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 705        }
 706        wb_arb_params->time_per_pixel = 16.0 * 1000 / (context->res_ctx.pipe_ctx[i].stream->phy_pix_clk / 1000); /* 4 bit fraction, ms */
 707 }
 708
 709 static bool is_dtbclk_required(struct dc *dc, struct dc_state *context)
 710 {
 711         int i;
 712         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 713                 if (!context->res_ctx.pipe_ctx[i].stream)
 714                         continue;
 715                 if (is_dp_128b_132b_signal(&context->res_ctx.pipe_ctx[i]))
 716                         return true;
 717         }
 718         return false;
 719 }
 720
 721 static enum dcn_zstate_support_state  decide_zstate_support(struct dc *dc, struct dc_state *context)
 722 {
 723         int plane_count;
 724         int i;
 725         unsigned int optimized_min_dst_y_next_start_us;
 726
 727         plane_count = 0;
 728         optimized_min_dst_y_next_start_us = 0;
 729         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 730                 if (context->res_ctx.pipe_ctx[i].plane_state)
 731                         plane_count++;
 732         }
 733
 734         /*
 735          * Z9 and Z10 allowed cases:
 736          *      1. 0 Planes enabled
 737          *      2. single eDP, on link 0, 1 plane and stutter period > 5ms
 738          * Z10 only cases:
 739          *      1. single eDP, on link 0, 1 plane and stutter period >= 5ms
 740          * Zstate not allowed cases:
 741          *      1. Everything else
 742          */
 743         if (plane_count == 0)
 744                 return DCN_ZSTATE_SUPPORT_ALLOW;
 745         else if (context->stream_count == 1 &&  context->streams[0]->signal == SIGNAL_TYPE_EDP) {
 746                 struct dc_link *link = context->streams[0]->sink->link;
 747                 struct dc_stream_status *stream_status = &context->stream_status[0];
 748
 749                 if (dc_extended_blank_supported(dc)) {
 750                         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 751                                 if (context->res_ctx.pipe_ctx[i].stream == context->streams[0]
 752                                         && context->res_ctx.pipe_ctx[i].stream->adjust.v_total_min == context->res_ctx.pipe_ctx[i].stream->adjust.v_total_max
 753                                         && context->res_ctx.pipe_ctx[i].stream->adjust.v_total_min > context->res_ctx.pipe_ctx[i].stream->timing.v_total) {
 754                                                 optimized_min_dst_y_next_start_us =
 755                                                         context->res_ctx.pipe_ctx[i].dlg_regs.optimized_min_dst_y_next_start_us;
 756                                                 break;
 757                                 }
 758                         }
 759                 }
 760                 /* zstate only supported on PWRSEQ0  and when there's <2 planes*/
 761                 if (link->link_index != 0 || stream_status->plane_count > 1)
 762                         return DCN_ZSTATE_SUPPORT_DISALLOW;
 763
 764                 if (context->bw_ctx.dml.vba.StutterPeriod > 5000.0 || optimized_min_dst_y_next_start_us > 5000)
 765                         return DCN_ZSTATE_SUPPORT_ALLOW;
 766                 else if (link->psr_settings.psr_version == DC_PSR_VERSION_1 && !dc->debug.disable_psr)
 767                         return DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY;
 768                 else
 769                         return DCN_ZSTATE_SUPPORT_DISALLOW;
 770         } else
 771                 return DCN_ZSTATE_SUPPORT_DISALLOW;
 772 }
 773
 774 void dcn20_calculate_dlg_params(
 775                 struct dc *dc, struct dc_state *context,
 776                 display_e2e_pipe_params_st *pipes,
 777                 int pipe_cnt,
 778                 int vlevel)
 779 {
 780         int i, pipe_idx;
 781
 782         dc_assert_fp_enabled();
 783
 784         /* Writeback MCIF_WB arbitration parameters */
 785         dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt);
 786
 787         context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000;
 788         context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000;
 789         context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000;
 790         context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16;
 791
 792         if (dc->debug.min_dram_clk_khz > context->bw_ctx.bw.dcn.clk.dramclk_khz)
 793                 context->bw_ctx.bw.dcn.clk.dramclk_khz = dc->debug.min_dram_clk_khz;
 794
 795         context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000;
 796         context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000;
 797         context->bw_ctx.bw.dcn.clk.p_state_change_support =
 798                 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]
 799                                                         != dm_dram_clock_change_unsupported;
 800         context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
 801
 802         context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context);
 803
 804         if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz)
 805                 context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz;
 806
 807         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
 808                 if (!context->res_ctx.pipe_ctx[i].stream)
 809                         continue;
 810                 pipes[pipe_idx].pipe.dest.vstartup_start = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
 811                 pipes[pipe_idx].pipe.dest.vupdate_offset = get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
 812                 pipes[pipe_idx].pipe.dest.vupdate_width = get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
 813                 pipes[pipe_idx].pipe.dest.vready_offset = get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
 814                 if (context->res_ctx.pipe_ctx[i].stream->mall_stream_config.type == SUBVP_PHANTOM) {
 815                         // Phantom pipe requires that DET_SIZE = 0 and no unbounded requests
 816                         context->res_ctx.pipe_ctx[i].det_buffer_size_kb = 0;
 817                         context->res_ctx.pipe_ctx[i].unbounded_req = false;
 818                 } else {
 819                         context->res_ctx.pipe_ctx[i].det_buffer_size_kb = context->bw_ctx.dml.ip.det_buffer_size_kbytes;
 820                         context->res_ctx.pipe_ctx[i].unbounded_req = pipes[pipe_idx].pipe.src.unbounded_req_mode;
 821                 }
 822                 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
 823                         context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
 824                 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz =
 825                                                 pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
 826                 context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;
 827                 pipe_idx++;
 828         }
 829         /*save a original dppclock copy*/
 830         context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz;
 831         context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz;
 832         context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz * 1000;
 833         context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz * 1000;
 834
 835         context->bw_ctx.bw.dcn.compbuf_size_kb = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes
 836                                                 - context->bw_ctx.dml.ip.det_buffer_size_kbytes * pipe_idx;
 837
 838         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
 839                 bool cstate_en = context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != 2;
 840
 841                 if (!context->res_ctx.pipe_ctx[i].stream)
 842                         continue;
 843
 844                 if (dc->ctx->dce_version == DCN_VERSION_2_01)
 845                         cstate_en = false;
 846
 847                 context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg(&context->bw_ctx.dml,
 848                                 &context->res_ctx.pipe_ctx[i].dlg_regs,
 849                                 &context->res_ctx.pipe_ctx[i].ttu_regs,
 850                                 pipes,
 851                                 pipe_cnt,
 852                                 pipe_idx,
 853                                 cstate_en,
 854                                 context->bw_ctx.bw.dcn.clk.p_state_change_support,
 855                                 false, false, true);
 856
 857                 context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg(&context->bw_ctx.dml,
 858                                 &context->res_ctx.pipe_ctx[i].rq_regs,
 859                                 &pipes[pipe_idx].pipe);
 860                 pipe_idx++;
 861         }
 862         context->bw_ctx.bw.dcn.clk.zstate_support = decide_zstate_support(dc, context);
 863 }
 864
 865 static void swizzle_to_dml_params(
 866                 enum swizzle_mode_values swizzle,
 867                 unsigned int *sw_mode)
 868 {
 869         switch (swizzle) {
 870         case DC_SW_LINEAR:
 871                 *sw_mode = dm_sw_linear;
 872                 break;
 873         case DC_SW_4KB_S:
 874                 *sw_mode = dm_sw_4kb_s;
 875                 break;
 876         case DC_SW_4KB_S_X:
 877                 *sw_mode = dm_sw_4kb_s_x;
 878                 break;
 879         case DC_SW_4KB_D:
 880                 *sw_mode = dm_sw_4kb_d;
 881                 break;
 882         case DC_SW_4KB_D_X:
 883                 *sw_mode = dm_sw_4kb_d_x;
 884                 break;
 885         case DC_SW_64KB_S:
 886                 *sw_mode = dm_sw_64kb_s;
 887                 break;
 888         case DC_SW_64KB_S_X:
 889                 *sw_mode = dm_sw_64kb_s_x;
 890                 break;
 891         case DC_SW_64KB_S_T:
 892                 *sw_mode = dm_sw_64kb_s_t;
 893                 break;
 894         case DC_SW_64KB_D:
 895                 *sw_mode = dm_sw_64kb_d;
 896                 break;
 897         case DC_SW_64KB_D_X:
 898                 *sw_mode = dm_sw_64kb_d_x;
 899                 break;
 900         case DC_SW_64KB_D_T:
 901                 *sw_mode = dm_sw_64kb_d_t;
 902                 break;
 903         case DC_SW_64KB_R_X:
 904                 *sw_mode = dm_sw_64kb_r_x;
 905                 break;
 906         case DC_SW_VAR_S:
 907                 *sw_mode = dm_sw_var_s;
 908                 break;
 909         case DC_SW_VAR_S_X:
 910                 *sw_mode = dm_sw_var_s_x;
 911                 break;
 912         case DC_SW_VAR_D:
 913                 *sw_mode = dm_sw_var_d;
 914                 break;
 915         case DC_SW_VAR_D_X:
 916                 *sw_mode = dm_sw_var_d_x;
 917                 break;
 918         case DC_SW_VAR_R_X:
 919                 *sw_mode = dm_sw_var_r_x;
 920                 break;
 921         default:
 922                 ASSERT(0); /* Not supported */
 923                 break;
 924         }
 925 }
 926
 927 int dcn20_populate_dml_pipes_from_context(
 928                 struct dc *dc,
 929                 struct dc_state *context,
 930                 display_e2e_pipe_params_st *pipes,
 931                 bool fast_validate)
 932 {
 933         int pipe_cnt, i;
 934         bool synchronized_vblank = true;
 935         struct resource_context *res_ctx = &context->res_ctx;
 936
 937         dc_assert_fp_enabled();
 938
 939         for (i = 0, pipe_cnt = -1; i < dc->res_pool->pipe_count; i++) {
 940                 if (!res_ctx->pipe_ctx[i].stream)
 941                         continue;
 942
 943                 if (pipe_cnt < 0) {
 944                         pipe_cnt = i;
 945                         continue;
 946                 }
 947
 948                 if (res_ctx->pipe_ctx[pipe_cnt].stream == res_ctx->pipe_ctx[i].stream)
 949                         continue;
 950
 951                 if (dc->debug.disable_timing_sync ||
 952                         (!resource_are_streams_timing_synchronizable(
 953                                 res_ctx->pipe_ctx[pipe_cnt].stream,
 954                                 res_ctx->pipe_ctx[i].stream) &&
 955                         !resource_are_vblanks_synchronizable(
 956                                 res_ctx->pipe_ctx[pipe_cnt].stream,
 957                                 res_ctx->pipe_ctx[i].stream))) {
 958                         synchronized_vblank = false;
 959                         break;
 960                 }
 961         }
 962
 963         for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
 964                 struct dc_crtc_timing *timing = &res_ctx->pipe_ctx[i].stream->timing;
 965                 unsigned int v_total;
 966                 unsigned int front_porch;
 967                 int output_bpc;
 968                 struct audio_check aud_check = {0};
 969
 970                 if (!res_ctx->pipe_ctx[i].stream)
 971                         continue;
 972
 973                 v_total = timing->v_total;
 974                 front_porch = timing->v_front_porch;
 975
 976                 /* todo:
 977                 pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = 0;
 978                 pipes[pipe_cnt].pipe.src.dcc = 0;
 979                 pipes[pipe_cnt].pipe.src.vm = 0;*/
 980
 981                 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
 982
 983                 pipes[pipe_cnt].dout.dsc_enable = res_ctx->pipe_ctx[i].stream->timing.flags.DSC;
 984                 /* todo: rotation?*/
 985                 pipes[pipe_cnt].dout.dsc_slices = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.num_slices_h;
 986                 if (res_ctx->pipe_ctx[i].stream->use_dynamic_meta) {
 987                         pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = true;
 988                         /* 1/2 vblank */
 989                         pipes[pipe_cnt].pipe.src.dynamic_metadata_lines_before_active =
 990                                 (v_total - timing->v_addressable
 991                                         - timing->v_border_top - timing->v_border_bottom) / 2;
 992                         /* 36 bytes dp, 32 hdmi */
 993                         pipes[pipe_cnt].pipe.src.dynamic_metadata_xmit_bytes =
 994                                 dc_is_dp_signal(res_ctx->pipe_ctx[i].stream->signal) ? 36 : 32;
 995                 }
 996                 pipes[pipe_cnt].pipe.src.dcc = false;
 997                 pipes[pipe_cnt].pipe.src.dcc_rate = 1;
 998                 pipes[pipe_cnt].pipe.dest.synchronized_vblank_all_planes = synchronized_vblank;
 999                 pipes[pipe_cnt].pipe.dest.hblank_start = timing->h_total - timing->h_front_porch;
1000                 pipes[pipe_cnt].pipe.dest.hblank_end = pipes[pipe_cnt].pipe.dest.hblank_start
1001                                 - timing->h_addressable
1002                                 - timing->h_border_left
1003                                 - timing->h_border_right;
1004                 pipes[pipe_cnt].pipe.dest.vblank_start = v_total - front_porch;
1005                 pipes[pipe_cnt].pipe.dest.vblank_end = pipes[pipe_cnt].pipe.dest.vblank_start
1006                                 - timing->v_addressable
1007                                 - timing->v_border_top
1008                                 - timing->v_border_bottom;
1009                 pipes[pipe_cnt].pipe.dest.htotal = timing->h_total;
1010                 pipes[pipe_cnt].pipe.dest.vtotal = v_total;
1011                 pipes[pipe_cnt].pipe.dest.hactive =
1012                         timing->h_addressable + timing->h_border_left + timing->h_border_right;
1013                 pipes[pipe_cnt].pipe.dest.vactive =
1014                         timing->v_addressable + timing->v_border_top + timing->v_border_bottom;
1015                 pipes[pipe_cnt].pipe.dest.interlaced = timing->flags.INTERLACE;
1016                 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz = timing->pix_clk_100hz/10000.0;
1017                 if (timing->timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1018                         pipes[pipe_cnt].pipe.dest.pixel_rate_mhz *= 2;
1019                 pipes[pipe_cnt].pipe.dest.otg_inst = res_ctx->pipe_ctx[i].stream_res.tg->inst;
1020                 pipes[pipe_cnt].dout.dp_lanes = 4;
1021                 if (res_ctx->pipe_ctx[i].stream->link) {
1022                         switch (res_ctx->pipe_ctx[i].stream->link->cur_link_settings.link_rate) {
1023                         case LINK_RATE_HIGH:
1024                                 pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_hbr;
1025                                 break;
1026                         case LINK_RATE_HIGH2:
1027                                 pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_hbr2;
1028                                 break;
1029                         case LINK_RATE_HIGH3:
1030                                 pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_hbr3;
1031                                 break;
1032                         case LINK_RATE_UHBR10:
1033                                 pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_uhbr10;
1034                                 break;
1035                         case LINK_RATE_UHBR13_5:
1036                                 pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_uhbr13p5;
1037                                 break;
1038                         case LINK_RATE_UHBR20:
1039                                 pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_uhbr20;
1040                                 break;
1041                         default:
1042                                 pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_na;
1043                                 break;
1044                         }
1045                 }
1046                 pipes[pipe_cnt].dout.is_virtual = 0;
1047                 pipes[pipe_cnt].pipe.dest.vtotal_min = res_ctx->pipe_ctx[i].stream->adjust.v_total_min;
1048                 pipes[pipe_cnt].pipe.dest.vtotal_max = res_ctx->pipe_ctx[i].stream->adjust.v_total_max;
1049                 switch (get_num_odm_splits(&res_ctx->pipe_ctx[i])) {
1050                 case 1:
1051                         pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_2to1;
1052                         break;
1053                 case 3:
1054                         pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_4to1;
1055                         break;
1056                 default:
1057                         pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_disabled;
1058                 }
1059                 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;
1060                 if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state
1061                                 == res_ctx->pipe_ctx[i].plane_state) {
1062                         struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].top_pipe;
1063                         int split_idx = 0;
1064
1065                         while (first_pipe->top_pipe && first_pipe->top_pipe->plane_state
1066                                         == res_ctx->pipe_ctx[i].plane_state) {
1067                                 first_pipe = first_pipe->top_pipe;
1068                                 split_idx++;
1069                         }
1070                         /* Treat 4to1 mpc combine as an mpo of 2 2-to-1 combines */
1071                         if (split_idx == 0)
1072                                 pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx;
1073                         else if (split_idx == 1)
1074                                 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;
1075                         else if (split_idx == 2)
1076                                 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].top_pipe->pipe_idx;
1077                 } else if (res_ctx->pipe_ctx[i].prev_odm_pipe) {
1078                         struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].prev_odm_pipe;
1079
1080                         while (first_pipe->prev_odm_pipe)
1081                                 first_pipe = first_pipe->prev_odm_pipe;
1082                         pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx;
1083                 }
1084
1085                 switch (res_ctx->pipe_ctx[i].stream->signal) {
1086                 case SIGNAL_TYPE_DISPLAY_PORT_MST:
1087                 case SIGNAL_TYPE_DISPLAY_PORT:
1088                         pipes[pipe_cnt].dout.output_type = dm_dp;
1089                         break;
1090                 case SIGNAL_TYPE_EDP:
1091                         pipes[pipe_cnt].dout.output_type = dm_edp;
1092                         break;
1093                 case SIGNAL_TYPE_HDMI_TYPE_A:
1094                 case SIGNAL_TYPE_DVI_SINGLE_LINK:
1095                 case SIGNAL_TYPE_DVI_DUAL_LINK:
1096                         pipes[pipe_cnt].dout.output_type = dm_hdmi;
1097                         break;
1098                 default:
1099                         /* In case there is no signal, set dp with 4 lanes to allow max config */
1100                         pipes[pipe_cnt].dout.is_virtual = 1;
1101                         pipes[pipe_cnt].dout.output_type = dm_dp;
1102                         pipes[pipe_cnt].dout.dp_lanes = 4;
1103                         pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_hbr2;
1104                 }
1105
1106                 switch (res_ctx->pipe_ctx[i].stream->timing.display_color_depth) {
1107                 case COLOR_DEPTH_666:
1108                         output_bpc = 6;
1109                         break;
1110                 case COLOR_DEPTH_888:
1111                         output_bpc = 8;
1112                         break;
1113                 case COLOR_DEPTH_101010:
1114                         output_bpc = 10;
1115                         break;
1116                 case COLOR_DEPTH_121212:
1117                         output_bpc = 12;
1118                         break;
1119                 case COLOR_DEPTH_141414:
1120                         output_bpc = 14;
1121                         break;
1122                 case COLOR_DEPTH_161616:
1123                         output_bpc = 16;
1124                         break;
1125                 case COLOR_DEPTH_999:
1126                         output_bpc = 9;
1127                         break;
1128                 case COLOR_DEPTH_111111:
1129                         output_bpc = 11;
1130                         break;
1131                 default:
1132                         output_bpc = 8;
1133                         break;
1134                 }
1135
1136                 switch (res_ctx->pipe_ctx[i].stream->timing.pixel_encoding) {
1137                 case PIXEL_ENCODING_RGB:
1138                 case PIXEL_ENCODING_YCBCR444:
1139                         pipes[pipe_cnt].dout.output_format = dm_444;
1140                         pipes[pipe_cnt].dout.output_bpp = output_bpc * 3;
1141                         break;
1142                 case PIXEL_ENCODING_YCBCR420:
1143                         pipes[pipe_cnt].dout.output_format = dm_420;
1144                         pipes[pipe_cnt].dout.output_bpp = (output_bpc * 3.0) / 2;
1145                         break;
1146                 case PIXEL_ENCODING_YCBCR422:
1147                         if (res_ctx->pipe_ctx[i].stream->timing.flags.DSC &&
1148                             !res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.ycbcr422_simple)
1149                                 pipes[pipe_cnt].dout.output_format = dm_n422;
1150                         else
1151                                 pipes[pipe_cnt].dout.output_format = dm_s422;
1152                         pipes[pipe_cnt].dout.output_bpp = output_bpc * 2;
1153                         break;
1154                 default:
1155                         pipes[pipe_cnt].dout.output_format = dm_444;
1156                         pipes[pipe_cnt].dout.output_bpp = output_bpc * 3;
1157                 }
1158
1159                 if (res_ctx->pipe_ctx[i].stream->timing.flags.DSC)
1160                         pipes[pipe_cnt].dout.output_bpp = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.bits_per_pixel / 16.0;
1161
1162                 /* todo: default max for now, until there is logic reflecting this in dc*/
1163                 pipes[pipe_cnt].dout.dsc_input_bpc = 12;
1164                 /*fill up the audio sample rate (unit in kHz)*/
1165                 get_audio_check(&res_ctx->pipe_ctx[i].stream->audio_info, &aud_check);
1166                 pipes[pipe_cnt].dout.max_audio_sample_rate = aud_check.max_audiosample_rate / 1000;
1167                 /*
1168                  * For graphic plane, cursor number is 1, nv12 is 0
1169                  * bw calculations due to cursor on/off
1170                  */
1171                 if (res_ctx->pipe_ctx[i].plane_state &&
1172                                 (res_ctx->pipe_ctx[i].plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE ||
1173                                  res_ctx->pipe_ctx[i].stream->mall_stream_config.type == SUBVP_PHANTOM))
1174                         pipes[pipe_cnt].pipe.src.num_cursors = 0;
1175                 else
1176                         pipes[pipe_cnt].pipe.src.num_cursors = dc->dml.ip.number_of_cursors;
1177
1178                 pipes[pipe_cnt].pipe.src.cur0_src_width = 256;
1179                 pipes[pipe_cnt].pipe.src.cur0_bpp = dm_cur_32bit;
1180
1181                 if (!res_ctx->pipe_ctx[i].plane_state) {
1182                         pipes[pipe_cnt].pipe.src.is_hsplit = pipes[pipe_cnt].pipe.dest.odm_combine != dm_odm_combine_mode_disabled;
1183                         pipes[pipe_cnt].pipe.src.source_scan = dm_horz;
1184                         pipes[pipe_cnt].pipe.src.source_rotation = dm_rotation_0;
1185                         pipes[pipe_cnt].pipe.src.sw_mode = dm_sw_4kb_s;
1186                         pipes[pipe_cnt].pipe.src.macro_tile_size = dm_64k_tile;
1187                         pipes[pipe_cnt].pipe.src.viewport_width = timing->h_addressable;
1188                         if (pipes[pipe_cnt].pipe.src.viewport_width > 1920)
1189                                 pipes[pipe_cnt].pipe.src.viewport_width = 1920;
1190                         pipes[pipe_cnt].pipe.src.viewport_height = timing->v_addressable;
1191                         if (pipes[pipe_cnt].pipe.src.viewport_height > 1080)
1192                                 pipes[pipe_cnt].pipe.src.viewport_height = 1080;
1193                         pipes[pipe_cnt].pipe.src.surface_height_y = pipes[pipe_cnt].pipe.src.viewport_height;
1194                         pipes[pipe_cnt].pipe.src.surface_width_y = pipes[pipe_cnt].pipe.src.viewport_width;
1195                         pipes[pipe_cnt].pipe.src.surface_height_c = pipes[pipe_cnt].pipe.src.viewport_height;
1196                         pipes[pipe_cnt].pipe.src.surface_width_c = pipes[pipe_cnt].pipe.src.viewport_width;
1197                         pipes[pipe_cnt].pipe.src.data_pitch = ((pipes[pipe_cnt].pipe.src.viewport_width + 255) / 256) * 256;
1198                         pipes[pipe_cnt].pipe.src.source_format = dm_444_32;
1199                         pipes[pipe_cnt].pipe.dest.recout_width = pipes[pipe_cnt].pipe.src.viewport_width; /*vp_width/hratio*/
1200                         pipes[pipe_cnt].pipe.dest.recout_height = pipes[pipe_cnt].pipe.src.viewport_height; /*vp_height/vratio*/
1201                         pipes[pipe_cnt].pipe.dest.full_recout_width = pipes[pipe_cnt].pipe.dest.recout_width;  /*when is_hsplit != 1*/
1202                         pipes[pipe_cnt].pipe.dest.full_recout_height = pipes[pipe_cnt].pipe.dest.recout_height; /*when is_hsplit != 1*/
1203                         pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16;
1204                         pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = 1.0;
1205                         pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = 1.0;
1206                         pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable = 0; /*Lb only or Full scl*/
1207                         pipes[pipe_cnt].pipe.scale_taps.htaps = 1;
1208                         pipes[pipe_cnt].pipe.scale_taps.vtaps = 1;
1209                         pipes[pipe_cnt].pipe.dest.vtotal_min = v_total;
1210                         pipes[pipe_cnt].pipe.dest.vtotal_max = v_total;
1211
1212                         if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_2to1) {
1213                                 pipes[pipe_cnt].pipe.src.viewport_width /= 2;
1214                                 pipes[pipe_cnt].pipe.dest.recout_width /= 2;
1215                         } else if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_4to1) {
1216                                 pipes[pipe_cnt].pipe.src.viewport_width /= 4;
1217                                 pipes[pipe_cnt].pipe.dest.recout_width /= 4;
1218                         }
1219                 } else {
1220                         struct dc_plane_state *pln = res_ctx->pipe_ctx[i].plane_state;
1221                         struct scaler_data *scl = &res_ctx->pipe_ctx[i].plane_res.scl_data;
1222
1223                         pipes[pipe_cnt].pipe.src.immediate_flip = pln->flip_immediate;
1224                         pipes[pipe_cnt].pipe.src.is_hsplit = (res_ctx->pipe_ctx[i].bottom_pipe && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln)
1225                                         || (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln)
1226                                         || pipes[pipe_cnt].pipe.dest.odm_combine != dm_odm_combine_mode_disabled;
1227
1228                         /* stereo is not split */
1229                         if (pln->stereo_format == PLANE_STEREO_FORMAT_SIDE_BY_SIDE ||
1230                             pln->stereo_format == PLANE_STEREO_FORMAT_TOP_AND_BOTTOM) {
1231                                 pipes[pipe_cnt].pipe.src.is_hsplit = false;
1232                                 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;
1233                         }
1234
1235                         pipes[pipe_cnt].pipe.src.source_scan = pln->rotation == ROTATION_ANGLE_90
1236                                         || pln->rotation == ROTATION_ANGLE_270 ? dm_vert : dm_horz;
1237                         switch (pln->rotation) {
1238                         case ROTATION_ANGLE_0:
1239                                 pipes[pipe_cnt].pipe.src.source_rotation = dm_rotation_0;
1240                                 break;
1241                         case ROTATION_ANGLE_90:
1242                                 pipes[pipe_cnt].pipe.src.source_rotation = dm_rotation_90;
1243                                 break;
1244                         case ROTATION_ANGLE_180:
1245                                 pipes[pipe_cnt].pipe.src.source_rotation = dm_rotation_180;
1246                                 break;
1247                         case ROTATION_ANGLE_270:
1248                                 pipes[pipe_cnt].pipe.src.source_rotation = dm_rotation_270;
1249                                 break;
1250                         default:
1251                                 break;
1252                         }
1253                         pipes[pipe_cnt].pipe.src.viewport_y_y = scl->viewport.y;
1254                         pipes[pipe_cnt].pipe.src.viewport_y_c = scl->viewport_c.y;
1255                         pipes[pipe_cnt].pipe.src.viewport_x_y = scl->viewport.x;
1256                         pipes[pipe_cnt].pipe.src.viewport_x_c = scl->viewport_c.x;
1257                         pipes[pipe_cnt].pipe.src.viewport_width = scl->viewport.width;
1258                         pipes[pipe_cnt].pipe.src.viewport_width_c = scl->viewport_c.width;
1259                         pipes[pipe_cnt].pipe.src.viewport_height = scl->viewport.height;
1260                         pipes[pipe_cnt].pipe.src.viewport_height_c = scl->viewport_c.height;
1261                         pipes[pipe_cnt].pipe.src.viewport_width_max = pln->src_rect.width;
1262                         pipes[pipe_cnt].pipe.src.viewport_height_max = pln->src_rect.height;
1263                         pipes[pipe_cnt].pipe.src.surface_width_y = pln->plane_size.surface_size.width;
1264                         pipes[pipe_cnt].pipe.src.surface_height_y = pln->plane_size.surface_size.height;
1265                         pipes[pipe_cnt].pipe.src.surface_width_c = pln->plane_size.chroma_size.width;
1266                         pipes[pipe_cnt].pipe.src.surface_height_c = pln->plane_size.chroma_size.height;
1267                         if (pln->format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA
1268                                         || pln->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
1269                                 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch;
1270                                 pipes[pipe_cnt].pipe.src.data_pitch_c = pln->plane_size.chroma_pitch;
1271                                 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch;
1272                                 pipes[pipe_cnt].pipe.src.meta_pitch_c = pln->dcc.meta_pitch_c;
1273                         } else {
1274                                 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch;
1275                                 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch;
1276                         }
1277                         pipes[pipe_cnt].pipe.src.dcc = pln->dcc.enable;
1278                         pipes[pipe_cnt].pipe.dest.recout_width = scl->recout.width;
1279                         pipes[pipe_cnt].pipe.dest.recout_height = scl->recout.height;
1280                         pipes[pipe_cnt].pipe.dest.full_recout_height = scl->recout.height;
1281                         pipes[pipe_cnt].pipe.dest.full_recout_width = scl->recout.width;
1282                         if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_2to1)
1283                                 pipes[pipe_cnt].pipe.dest.full_recout_width *= 2;
1284                         else if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_4to1)
1285                                 pipes[pipe_cnt].pipe.dest.full_recout_width *= 4;
1286                         else {
1287                                 struct pipe_ctx *split_pipe = res_ctx->pipe_ctx[i].bottom_pipe;
1288
1289                                 while (split_pipe && split_pipe->plane_state == pln) {
1290                                         pipes[pipe_cnt].pipe.dest.full_recout_width += split_pipe->plane_res.scl_data.recout.width;
1291                                         split_pipe = split_pipe->bottom_pipe;
1292                                 }
1293                                 split_pipe = res_ctx->pipe_ctx[i].top_pipe;
1294                                 while (split_pipe && split_pipe->plane_state == pln) {
1295                                         pipes[pipe_cnt].pipe.dest.full_recout_width += split_pipe->plane_res.scl_data.recout.width;
1296                                         split_pipe = split_pipe->top_pipe;
1297                                 }
1298                         }
1299
1300                         pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16;
1301                         pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = (double) scl->ratios.horz.value / (1ULL<<32);
1302                         pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio_c = (double) scl->ratios.horz_c.value / (1ULL<<32);
1303                         pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = (double) scl->ratios.vert.value / (1ULL<<32);
1304                         pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio_c = (double) scl->ratios.vert_c.value / (1ULL<<32);
1305                         pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable =
1306                                         scl->ratios.vert.value != dc_fixpt_one.value
1307                                         || scl->ratios.horz.value != dc_fixpt_one.value
1308                                         || scl->ratios.vert_c.value != dc_fixpt_one.value
1309                                         || scl->ratios.horz_c.value != dc_fixpt_one.value /*Lb only or Full scl*/
1310                                         || dc->debug.always_scale; /*support always scale*/
1311                         pipes[pipe_cnt].pipe.scale_taps.htaps = scl->taps.h_taps;
1312                         pipes[pipe_cnt].pipe.scale_taps.htaps_c = scl->taps.h_taps_c;
1313                         pipes[pipe_cnt].pipe.scale_taps.vtaps = scl->taps.v_taps;
1314                         pipes[pipe_cnt].pipe.scale_taps.vtaps_c = scl->taps.v_taps_c;
1315
1316                         pipes[pipe_cnt].pipe.src.macro_tile_size =
1317                                         swizzle_mode_to_macro_tile_size(pln->tiling_info.gfx9.swizzle);
1318                         swizzle_to_dml_params(pln->tiling_info.gfx9.swizzle,
1319                                         &pipes[pipe_cnt].pipe.src.sw_mode);
1320
1321                         switch (pln->format) {
1322                         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
1323                         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
1324                                 pipes[pipe_cnt].pipe.src.source_format = dm_420_8;
1325                                 break;
1326                         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
1327                         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
1328                                 pipes[pipe_cnt].pipe.src.source_format = dm_420_10;
1329                                 break;
1330                         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
1331                         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
1332                         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
1333                         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
1334                                 pipes[pipe_cnt].pipe.src.source_format = dm_444_64;
1335                                 break;
1336                         case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
1337                         case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
1338                                 pipes[pipe_cnt].pipe.src.source_format = dm_444_16;
1339                                 break;
1340                         case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
1341                                 pipes[pipe_cnt].pipe.src.source_format = dm_444_8;
1342                                 break;
1343                         case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
1344                                 pipes[pipe_cnt].pipe.src.source_format = dm_rgbe_alpha;
1345                                 break;
1346                         default:
1347                                 pipes[pipe_cnt].pipe.src.source_format = dm_444_32;
1348                                 break;
1349                         }
1350                 }
1351
1352                 pipe_cnt++;
1353         }
1354
1355         /* populate writeback information */
1356         dc->res_pool->funcs->populate_dml_writeback_from_context(dc, res_ctx, pipes);
1357
1358         return pipe_cnt;
1359 }
1360
1361 void dcn20_calculate_wm(
1362                 struct dc *dc, struct dc_state *context,
1363                 display_e2e_pipe_params_st *pipes,
1364                 int *out_pipe_cnt,
1365                 int *pipe_split_from,
1366                 int vlevel,
1367                 bool fast_validate)
1368 {
1369         int pipe_cnt, i, pipe_idx;
1370
1371         dc_assert_fp_enabled();
1372
1373         for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1374                 if (!context->res_ctx.pipe_ctx[i].stream)
1375                         continue;
1376
1377                 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
1378                 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
1379
1380                 if (pipe_split_from[i] < 0) {
1381                         pipes[pipe_cnt].clks_cfg.dppclk_mhz =
1382                                         context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
1383                         if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)
1384                                 pipes[pipe_cnt].pipe.dest.odm_combine =
1385                                                 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx];
1386                         else
1387                                 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
1388                         pipe_idx++;
1389                 } else {
1390                         pipes[pipe_cnt].clks_cfg.dppclk_mhz =
1391                                         context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
1392                         if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i])
1393                                 pipes[pipe_cnt].pipe.dest.odm_combine =
1394                                                 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_split_from[i]];
1395                         else
1396                                 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
1397                 }
1398
1399                 if (dc->config.forced_clocks) {
1400                         pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
1401                         pipes[pipe_cnt].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
1402                 }
1403                 if (dc->debug.min_disp_clk_khz > pipes[pipe_cnt].clks_cfg.dispclk_mhz * 1000)
1404                         pipes[pipe_cnt].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
1405                 if (dc->debug.min_dpp_clk_khz > pipes[pipe_cnt].clks_cfg.dppclk_mhz * 1000)
1406                         pipes[pipe_cnt].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
1407
1408                 pipe_cnt++;
1409         }
1410
1411         if (pipe_cnt != pipe_idx) {
1412                 if (dc->res_pool->funcs->populate_dml_pipes)
1413                         pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
1414                                 context, pipes, fast_validate);
1415                 else
1416                         pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
1417                                 context, pipes, fast_validate);
1418         }
1419
1420         *out_pipe_cnt = pipe_cnt;
1421
1422         pipes[0].clks_cfg.voltage = vlevel;
1423         pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
1424         pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
1425
1426         /* only pipe 0 is read for voltage and dcf/soc clocks */
1427         if (vlevel < 1) {
1428                 pipes[0].clks_cfg.voltage = 1;
1429                 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].dcfclk_mhz;
1430                 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].socclk_mhz;
1431         }
1432         context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1433         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1434         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1435         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1436         context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1437         context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1438         context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1439         context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1440
1441         if (vlevel < 2) {
1442                 pipes[0].clks_cfg.voltage = 2;
1443                 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
1444                 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
1445         }
1446         context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1447         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1448         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1449         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1450         context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1451         context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1452         context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1453
1454         if (vlevel < 3) {
1455                 pipes[0].clks_cfg.voltage = 3;
1456                 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
1457                 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
1458         }
1459         context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1460         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1461         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1462         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1463         context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1464         context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1465         context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1466
1467         pipes[0].clks_cfg.voltage = vlevel;
1468         pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
1469         pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
1470         context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1471         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1472         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1473         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1474         context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1475         context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1476         context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1477 }
1478
1479 void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb,
1480                 struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states)
1481 {
1482         struct _vcs_dpi_voltage_scaling_st calculated_states[DC__VOLTAGE_STATES];
1483         int i;
1484         int num_calculated_states = 0;
1485         int min_dcfclk = 0;
1486
1487         dc_assert_fp_enabled();
1488
1489         if (num_states == 0)
1490                 return;
1491
1492         memset(calculated_states, 0, sizeof(calculated_states));
1493
1494         if (dc->bb_overrides.min_dcfclk_mhz > 0)
1495                 min_dcfclk = dc->bb_overrides.min_dcfclk_mhz;
1496         else {
1497                 if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev))
1498                         min_dcfclk = 310;
1499                 else
1500                         // Accounting for SOC/DCF relationship, we can go as high as
1501                         // 506Mhz in Vmin.
1502                         min_dcfclk = 506;
1503         }
1504
1505         for (i = 0; i < num_states; i++) {
1506                 int min_fclk_required_by_uclk;
1507                 calculated_states[i].state = i;
1508                 calculated_states[i].dram_speed_mts = uclk_states[i] * 16 / 1000;
1509
1510                 // FCLK:UCLK ratio is 1.08
1511                 min_fclk_required_by_uclk = div_u64(((unsigned long long)uclk_states[i]) * 1080,
1512                         1000000);
1513
1514                 calculated_states[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ?
1515                                 min_dcfclk : min_fclk_required_by_uclk;
1516
1517                 calculated_states[i].socclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->socClockInKhz / 1000) ?
1518                                 max_clocks->socClockInKhz / 1000 : calculated_states[i].fabricclk_mhz;
1519
1520                 calculated_states[i].dcfclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->dcfClockInKhz / 1000) ?
1521                                 max_clocks->dcfClockInKhz / 1000 : calculated_states[i].fabricclk_mhz;
1522
1523                 calculated_states[i].dispclk_mhz = max_clocks->displayClockInKhz / 1000;
1524                 calculated_states[i].dppclk_mhz = max_clocks->displayClockInKhz / 1000;
1525                 calculated_states[i].dscclk_mhz = max_clocks->displayClockInKhz / (1000 * 3);
1526
1527                 calculated_states[i].phyclk_mhz = max_clocks->phyClockInKhz / 1000;
1528
1529                 num_calculated_states++;
1530         }
1531
1532         calculated_states[num_calculated_states - 1].socclk_mhz = max_clocks->socClockInKhz / 1000;
1533         calculated_states[num_calculated_states - 1].fabricclk_mhz = max_clocks->socClockInKhz / 1000;
1534         calculated_states[num_calculated_states - 1].dcfclk_mhz = max_clocks->dcfClockInKhz / 1000;
1535
1536         memcpy(bb->clock_limits, calculated_states, sizeof(bb->clock_limits));
1537         bb->num_states = num_calculated_states;
1538
1539         // Duplicate the last state, DML always an extra state identical to max state to work
1540         memcpy(&bb->clock_limits[num_calculated_states], &bb->clock_limits[num_calculated_states - 1], sizeof(struct _vcs_dpi_voltage_scaling_st));
1541         bb->clock_limits[num_calculated_states].state = bb->num_states;
1542 }
1543
1544 void dcn20_cap_soc_clocks(
1545                 struct _vcs_dpi_soc_bounding_box_st *bb,
1546                 struct pp_smu_nv_clock_table max_clocks)
1547 {
1548         int i;
1549
1550         dc_assert_fp_enabled();
1551
1552         // First pass - cap all clocks higher than the reported max
1553         for (i = 0; i < bb->num_states; i++) {
1554                 if ((bb->clock_limits[i].dcfclk_mhz > (max_clocks.dcfClockInKhz / 1000))
1555                                 && max_clocks.dcfClockInKhz != 0)
1556                         bb->clock_limits[i].dcfclk_mhz = (max_clocks.dcfClockInKhz / 1000);
1557
1558                 if ((bb->clock_limits[i].dram_speed_mts > (max_clocks.uClockInKhz / 1000) * 16)
1559                                                 && max_clocks.uClockInKhz != 0)
1560                         bb->clock_limits[i].dram_speed_mts = (max_clocks.uClockInKhz / 1000) * 16;
1561
1562                 if ((bb->clock_limits[i].fabricclk_mhz > (max_clocks.fabricClockInKhz / 1000))
1563                                                 && max_clocks.fabricClockInKhz != 0)
1564                         bb->clock_limits[i].fabricclk_mhz = (max_clocks.fabricClockInKhz / 1000);
1565
1566                 if ((bb->clock_limits[i].dispclk_mhz > (max_clocks.displayClockInKhz / 1000))
1567                                                 && max_clocks.displayClockInKhz != 0)
1568                         bb->clock_limits[i].dispclk_mhz = (max_clocks.displayClockInKhz / 1000);
1569
1570                 if ((bb->clock_limits[i].dppclk_mhz > (max_clocks.dppClockInKhz / 1000))
1571                                                 && max_clocks.dppClockInKhz != 0)
1572                         bb->clock_limits[i].dppclk_mhz = (max_clocks.dppClockInKhz / 1000);
1573
1574                 if ((bb->clock_limits[i].phyclk_mhz > (max_clocks.phyClockInKhz / 1000))
1575                                                 && max_clocks.phyClockInKhz != 0)
1576                         bb->clock_limits[i].phyclk_mhz = (max_clocks.phyClockInKhz / 1000);
1577
1578                 if ((bb->clock_limits[i].socclk_mhz > (max_clocks.socClockInKhz / 1000))
1579                                                 && max_clocks.socClockInKhz != 0)
1580                         bb->clock_limits[i].socclk_mhz = (max_clocks.socClockInKhz / 1000);
1581
1582                 if ((bb->clock_limits[i].dscclk_mhz > (max_clocks.dscClockInKhz / 1000))
1583                                                 && max_clocks.dscClockInKhz != 0)
1584                         bb->clock_limits[i].dscclk_mhz = (max_clocks.dscClockInKhz / 1000);
1585         }
1586
1587         // Second pass - remove all duplicate clock states
1588         for (i = bb->num_states - 1; i > 1; i--) {
1589                 bool duplicate = true;
1590
1591                 if (bb->clock_limits[i-1].dcfclk_mhz != bb->clock_limits[i].dcfclk_mhz)
1592                         duplicate = false;
1593                 if (bb->clock_limits[i-1].dispclk_mhz != bb->clock_limits[i].dispclk_mhz)
1594                         duplicate = false;
1595                 if (bb->clock_limits[i-1].dppclk_mhz != bb->clock_limits[i].dppclk_mhz)
1596                         duplicate = false;
1597                 if (bb->clock_limits[i-1].dram_speed_mts != bb->clock_limits[i].dram_speed_mts)
1598                         duplicate = false;
1599                 if (bb->clock_limits[i-1].dscclk_mhz != bb->clock_limits[i].dscclk_mhz)
1600                         duplicate = false;
1601                 if (bb->clock_limits[i-1].fabricclk_mhz != bb->clock_limits[i].fabricclk_mhz)
1602                         duplicate = false;
1603                 if (bb->clock_limits[i-1].phyclk_mhz != bb->clock_limits[i].phyclk_mhz)
1604                         duplicate = false;
1605                 if (bb->clock_limits[i-1].socclk_mhz != bb->clock_limits[i].socclk_mhz)
1606                         duplicate = false;
1607
1608                 if (duplicate)
1609                         bb->num_states--;
1610         }
1611 }
1612
1613 void dcn20_patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
1614 {
1615         dc_assert_fp_enabled();
1616
1617         if ((int)(bb->sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns
1618                         && dc->bb_overrides.sr_exit_time_ns) {
1619                 bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;
1620         }
1621
1622         if ((int)(bb->sr_enter_plus_exit_time_us * 1000)
1623                                 != dc->bb_overrides.sr_enter_plus_exit_time_ns
1624                         && dc->bb_overrides.sr_enter_plus_exit_time_ns) {
1625                 bb->sr_enter_plus_exit_time_us =
1626                                 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
1627         }
1628
1629         if ((int)(bb->urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns
1630                         && dc->bb_overrides.urgent_latency_ns) {
1631                 bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
1632         }
1633
1634         if ((int)(bb->dram_clock_change_latency_us * 1000)
1635                                 != dc->bb_overrides.dram_clock_change_latency_ns
1636                         && dc->bb_overrides.dram_clock_change_latency_ns) {
1637                 bb->dram_clock_change_latency_us =
1638                                 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
1639         }
1640
1641         if ((int)(bb->dummy_pstate_latency_us * 1000)
1642                                 != dc->bb_overrides.dummy_clock_change_latency_ns
1643                         && dc->bb_overrides.dummy_clock_change_latency_ns) {
1644                 bb->dummy_pstate_latency_us =
1645                                 dc->bb_overrides.dummy_clock_change_latency_ns / 1000.0;
1646         }
1647 }
1648
1649 static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *context,
1650                 bool fast_validate)
1651 {
1652         bool out = false;
1653
1654         BW_VAL_TRACE_SETUP();
1655
1656         int vlevel = 0;
1657         int pipe_split_from[MAX_PIPES];
1658         int pipe_cnt = 0;
1659         display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_ATOMIC);
1660         DC_LOGGER_INIT(dc->ctx->logger);
1661
1662         BW_VAL_TRACE_COUNT();
1663
1664         out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel, fast_validate);
1665
1666         if (pipe_cnt == 0)
1667                 goto validate_out;
1668
1669         if (!out)
1670                 goto validate_fail;
1671
1672         BW_VAL_TRACE_END_VOLTAGE_LEVEL();
1673
1674         if (fast_validate) {
1675                 BW_VAL_TRACE_SKIP(fast);
1676                 goto validate_out;
1677         }
1678
1679         dcn20_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel, fast_validate);
1680         dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
1681
1682         BW_VAL_TRACE_END_WATERMARKS();
1683
1684         goto validate_out;
1685
1686 validate_fail:
1687         DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
1688                 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
1689
1690         BW_VAL_TRACE_SKIP(fail);
1691         out = false;
1692
1693 validate_out:
1694         kfree(pipes);
1695
1696         BW_VAL_TRACE_FINISH();
1697
1698         return out;
1699 }
1700
1701 bool dcn20_validate_bandwidth_fp(struct dc *dc,
1702                                 struct dc_state *context,
1703                                 bool fast_validate)
1704 {
1705        bool voltage_supported = false;
1706        bool full_pstate_supported = false;
1707        bool dummy_pstate_supported = false;
1708        double p_state_latency_us;
1709
1710        dc_assert_fp_enabled();
1711
1712        p_state_latency_us = context->bw_ctx.dml.soc.dram_clock_change_latency_us;
1713        context->bw_ctx.dml.soc.disable_dram_clock_change_vactive_support =
1714                dc->debug.disable_dram_clock_change_vactive_support;
1715        context->bw_ctx.dml.soc.allow_dram_clock_one_display_vactive =
1716                dc->debug.enable_dram_clock_change_one_display_vactive;
1717
1718        /*Unsafe due to current pipe merge and split logic*/
1719        ASSERT(context != dc->current_state);
1720
1721        if (fast_validate) {
1722                return dcn20_validate_bandwidth_internal(dc, context, true);
1723        }
1724
1725        // Best case, we support full UCLK switch latency
1726        voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);
1727        full_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;
1728
1729        if (context->bw_ctx.dml.soc.dummy_pstate_latency_us == 0 ||
1730                (voltage_supported && full_pstate_supported)) {
1731                context->bw_ctx.bw.dcn.clk.p_state_change_support = full_pstate_supported;
1732                goto restore_dml_state;
1733        }
1734
1735        // Fallback: Try to only support G6 temperature read latency
1736        context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latency_us;
1737
1738        voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);
1739        dummy_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;
1740
1741        if (voltage_supported && (dummy_pstate_supported || !(context->stream_count))) {
1742                context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
1743                goto restore_dml_state;
1744        }
1745
1746        // ERROR: fallback is supposed to always work.
1747        ASSERT(false);
1748
1749 restore_dml_state:
1750        context->bw_ctx.dml.soc.dram_clock_change_latency_us = p_state_latency_us;
1751        return voltage_supported;
1752 }
1753
1754 void dcn20_fpu_set_wm_ranges(int i,
1755                             struct pp_smu_wm_range_sets *ranges,
1756                             struct _vcs_dpi_soc_bounding_box_st *loaded_bb)
1757 {
1758        dc_assert_fp_enabled();
1759
1760        ranges->reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0;
1761        ranges->reader_wm_sets[i].max_fill_clk_mhz = loaded_bb->clock_limits[i].dram_speed_mts / 16;
1762 }
1763
1764 void dcn20_fpu_adjust_dppclk(struct vba_vars_st *v,
1765                             int vlevel,
1766                             int max_mpc_comb,
1767                             int pipe_idx,
1768                             bool is_validating_bw)
1769 {
1770        dc_assert_fp_enabled();
1771
1772        if (is_validating_bw)
1773                v->RequiredDPPCLK[vlevel][max_mpc_comb][pipe_idx] *= 2;
1774        else
1775                v->RequiredDPPCLK[vlevel][max_mpc_comb][pipe_idx] /= 2;
1776 }
1777
1778 int dcn21_populate_dml_pipes_from_context(struct dc *dc,
1779                                           struct dc_state *context,
1780                                           display_e2e_pipe_params_st *pipes,
1781                                           bool fast_validate)
1782 {
1783         uint32_t pipe_cnt;
1784         int i;
1785
1786         dc_assert_fp_enabled();
1787
1788         pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
1789
1790         for (i = 0; i < pipe_cnt; i++) {
1791
1792                 pipes[i].pipe.src.hostvm = dc->res_pool->hubbub->riommu_active;
1793                 pipes[i].pipe.src.gpuvm = 1;
1794         }
1795
1796         return pipe_cnt;
1797 }
1798
1799 static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
1800 {
1801         int i;
1802
1803         if (dc->bb_overrides.sr_exit_time_ns) {
1804                 for (i = 0; i < WM_SET_COUNT; i++) {
1805                           dc->clk_mgr->bw_params->wm_table.entries[i].sr_exit_time_us =
1806                                           dc->bb_overrides.sr_exit_time_ns / 1000.0;
1807                 }
1808         }
1809
1810         if (dc->bb_overrides.sr_enter_plus_exit_time_ns) {
1811                 for (i = 0; i < WM_SET_COUNT; i++) {
1812                           dc->clk_mgr->bw_params->wm_table.entries[i].sr_enter_plus_exit_time_us =
1813                                           dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
1814                 }
1815         }
1816
1817         if (dc->bb_overrides.urgent_latency_ns) {
1818                 bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
1819         }
1820
1821         if (dc->bb_overrides.dram_clock_change_latency_ns) {
1822                 for (i = 0; i < WM_SET_COUNT; i++) {
1823                         dc->clk_mgr->bw_params->wm_table.entries[i].pstate_latency_us =
1824                                 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
1825                 }
1826         }
1827 }
1828
1829 static void calculate_wm_set_for_vlevel(int vlevel,
1830                                         struct wm_range_table_entry *table_entry,
1831                                         struct dcn_watermarks *wm_set,
1832                                         struct display_mode_lib *dml,
1833                                         display_e2e_pipe_params_st *pipes,
1834                                         int pipe_cnt)
1835 {
1836         double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us;
1837
1838         ASSERT(vlevel < dml->soc.num_states);
1839         /* only pipe 0 is read for voltage and dcf/soc clocks */
1840         pipes[0].clks_cfg.voltage = vlevel;
1841         pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz;
1842         pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz;
1843
1844         dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us;
1845         dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us;
1846         dml->soc.sr_enter_plus_exit_time_us = table_entry->sr_enter_plus_exit_time_us;
1847
1848         wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000;
1849         wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000;
1850         wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000;
1851         wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000;
1852         wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000;
1853         wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000;
1854         wm_set->frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000;
1855         wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt) * 1000;
1856         dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached;
1857 }
1858
1859 static void dcn21_calculate_wm(struct dc *dc, struct dc_state *context,
1860                         display_e2e_pipe_params_st *pipes,
1861                         int *out_pipe_cnt,
1862                         int *pipe_split_from,
1863                         int vlevel_req,
1864                         bool fast_validate)
1865 {
1866         int pipe_cnt, i, pipe_idx;
1867         int vlevel, vlevel_max;
1868         struct wm_range_table_entry *table_entry;
1869         struct clk_bw_params *bw_params = dc->clk_mgr->bw_params;
1870
1871         ASSERT(bw_params);
1872
1873         patch_bounding_box(dc, &context->bw_ctx.dml.soc);
1874
1875         for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1876                         if (!context->res_ctx.pipe_ctx[i].stream)
1877                                 continue;
1878
1879                         pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
1880                         pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb];
1881
1882                         if (pipe_split_from[i] < 0) {
1883                                 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
1884                                                 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
1885                                 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)
1886                                         pipes[pipe_cnt].pipe.dest.odm_combine =
1887                                                         context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_idx];
1888                                 else
1889                                         pipes[pipe_cnt].pipe.dest.odm_combine = 0;
1890                                 pipe_idx++;
1891                         } else {
1892                                 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
1893                                                 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
1894                                 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i])
1895                                         pipes[pipe_cnt].pipe.dest.odm_combine =
1896                                                         context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_split_from[i]];
1897                                 else
1898                                         pipes[pipe_cnt].pipe.dest.odm_combine = 0;
1899                         }
1900                         pipe_cnt++;
1901         }
1902
1903         if (pipe_cnt != pipe_idx) {
1904                 if (dc->res_pool->funcs->populate_dml_pipes)
1905                         pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
1906                                 context, pipes, fast_validate);
1907                 else
1908                         pipe_cnt = dcn21_populate_dml_pipes_from_context(dc,
1909                                 context, pipes, fast_validate);
1910         }
1911
1912         *out_pipe_cnt = pipe_cnt;
1913
1914         vlevel_max = bw_params->clk_table.num_entries - 1;
1915
1916
1917         /* WM Set D */
1918         table_entry = &bw_params->wm_table.entries[WM_D];
1919         if (table_entry->wm_type == WM_TYPE_RETRAINING)
1920                 vlevel = 0;
1921         else
1922                 vlevel = vlevel_max;
1923         calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d,
1924                                                 &context->bw_ctx.dml, pipes, pipe_cnt);
1925         /* WM Set C */
1926         table_entry = &bw_params->wm_table.entries[WM_C];
1927         vlevel = MIN(MAX(vlevel_req, 3), vlevel_max);
1928         calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c,
1929                                                 &context->bw_ctx.dml, pipes, pipe_cnt);
1930         /* WM Set B */
1931         table_entry = &bw_params->wm_table.entries[WM_B];
1932         vlevel = MIN(MAX(vlevel_req, 2), vlevel_max);
1933         calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b,
1934                                                 &context->bw_ctx.dml, pipes, pipe_cnt);
1935
1936         /* WM Set A */
1937         table_entry = &bw_params->wm_table.entries[WM_A];
1938         vlevel = MIN(vlevel_req, vlevel_max);
1939         calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a,
1940                                                 &context->bw_ctx.dml, pipes, pipe_cnt);
1941 }
1942
1943 bool dcn21_validate_bandwidth_fp(struct dc *dc,
1944                                  struct dc_state *context,
1945                                  bool fast_validate)
1946 {
1947         bool out = false;
1948
1949         BW_VAL_TRACE_SETUP();
1950
1951         int vlevel = 0;
1952         int pipe_split_from[MAX_PIPES];
1953         int pipe_cnt = 0;
1954         display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_ATOMIC);
1955         DC_LOGGER_INIT(dc->ctx->logger);
1956
1957         BW_VAL_TRACE_COUNT();
1958
1959         dc_assert_fp_enabled();
1960
1961         /*Unsafe due to current pipe merge and split logic*/
1962         ASSERT(context != dc->current_state);
1963
1964         out = dcn21_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel, fast_validate);
1965
1966         if (pipe_cnt == 0)
1967                 goto validate_out;
1968
1969         if (!out)
1970                 goto validate_fail;
1971
1972         BW_VAL_TRACE_END_VOLTAGE_LEVEL();
1973
1974         if (fast_validate) {
1975                 BW_VAL_TRACE_SKIP(fast);
1976                 goto validate_out;
1977         }
1978
1979         dcn21_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel, fast_validate);
1980         dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
1981
1982         BW_VAL_TRACE_END_WATERMARKS();
1983
1984         goto validate_out;
1985
1986 validate_fail:
1987         DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
1988                         dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
1989
1990         BW_VAL_TRACE_SKIP(fail);
1991         out = false;
1992
1993 validate_out:
1994         kfree(pipes);
1995
1996         BW_VAL_TRACE_FINISH();
1997
1998         return out;
1999 }
2000
2001 static struct _vcs_dpi_voltage_scaling_st construct_low_pstate_lvl(struct clk_limit_table *clk_table, unsigned int high_voltage_lvl)
2002 {
2003         struct _vcs_dpi_voltage_scaling_st low_pstate_lvl;
2004         int i;
2005
2006         low_pstate_lvl.state = 1;
2007         low_pstate_lvl.dcfclk_mhz = clk_table->entries[0].dcfclk_mhz;
2008         low_pstate_lvl.fabricclk_mhz = clk_table->entries[0].fclk_mhz;
2009         low_pstate_lvl.socclk_mhz = clk_table->entries[0].socclk_mhz;
2010         low_pstate_lvl.dram_speed_mts = clk_table->entries[0].memclk_mhz * 2;
2011
2012         low_pstate_lvl.dispclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dispclk_mhz;
2013         low_pstate_lvl.dppclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dppclk_mhz;
2014         low_pstate_lvl.dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[high_voltage_lvl].dram_bw_per_chan_gbps;
2015         low_pstate_lvl.dscclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dscclk_mhz;
2016         low_pstate_lvl.dtbclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dtbclk_mhz;
2017         low_pstate_lvl.phyclk_d18_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].phyclk_d18_mhz;
2018         low_pstate_lvl.phyclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].phyclk_mhz;
2019
2020         for (i = clk_table->num_entries; i > 1; i--)
2021                 clk_table->entries[i] = clk_table->entries[i-1];
2022         clk_table->entries[1] = clk_table->entries[0];
2023         clk_table->num_entries++;
2024
2025         return low_pstate_lvl;
2026 }
2027
2028 void dcn21_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
2029 {
2030         struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool);
2031         struct clk_limit_table *clk_table = &bw_params->clk_table;
2032         struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
2033         unsigned int i, closest_clk_lvl = 0, k = 0;
2034         int j;
2035
2036         dc_assert_fp_enabled();
2037
2038         dcn2_1_ip.max_num_otg = pool->base.res_cap->num_timing_generator;
2039         dcn2_1_ip.max_num_dpp = pool->base.pipe_count;
2040         dcn2_1_soc.num_chans = bw_params->num_channels;
2041
2042         ASSERT(clk_table->num_entries);
2043         /* Copy dcn2_1_soc.clock_limits to clock_limits to avoid copying over null states later */
2044         for (i = 0; i < dcn2_1_soc.num_states + 1; i++) {
2045                 clock_limits[i] = dcn2_1_soc.clock_limits[i];
2046         }
2047
2048         for (i = 0; i < clk_table->num_entries; i++) {
2049                 /* loop backwards*/
2050                 for (closest_clk_lvl = 0, j = dcn2_1_soc.num_states - 1; j >= 0; j--) {
2051                         if ((unsigned int) dcn2_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) {
2052                                 closest_clk_lvl = j;
2053                                 break;
2054                         }
2055                 }
2056
2057                 /* clk_table[1] is reserved for min DF PState.  skip here to fill in later. */
2058                 if (i == 1)
2059                         k++;
2060
2061                 clock_limits[k].state = k;
2062                 clock_limits[k].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
2063                 clock_limits[k].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
2064                 clock_limits[k].socclk_mhz = clk_table->entries[i].socclk_mhz;
2065                 clock_limits[k].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;
2066
2067                 clock_limits[k].dispclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
2068                 clock_limits[k].dppclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
2069                 clock_limits[k].dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
2070                 clock_limits[k].dscclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
2071                 clock_limits[k].dtbclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
2072                 clock_limits[k].phyclk_d18_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
2073                 clock_limits[k].phyclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
2074
2075                 k++;
2076         }
2077         for (i = 0; i < clk_table->num_entries + 1; i++)
2078                 dcn2_1_soc.clock_limits[i] = clock_limits[i];
2079         if (clk_table->num_entries) {
2080                 dcn2_1_soc.num_states = clk_table->num_entries + 1;
2081                 /* fill in min DF PState */
2082                 dcn2_1_soc.clock_limits[1] = construct_low_pstate_lvl(clk_table, closest_clk_lvl);
2083                 /* duplicate last level */
2084                 dcn2_1_soc.clock_limits[dcn2_1_soc.num_states] = dcn2_1_soc.clock_limits[dcn2_1_soc.num_states - 1];
2085                 dcn2_1_soc.clock_limits[dcn2_1_soc.num_states].state = dcn2_1_soc.num_states;
2086         }
2087
2088         dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);
2089 }