drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c

   1 /* SPDX-License-Identifier: MIT */
   2 /*
   3  * Copyright 2023 Advanced Micro Devices, Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include "dm_services.h"
  26 #include "dc.h"
  27
  28 #include "dcn31/dcn31_init.h"
  29 #include "dcn35/dcn35_init.h"
  30
  31 #include "resource.h"
  32 #include "include/irq_service_interface.h"
  33 #include "dcn35_resource.h"
  34 #include "dml2/dml2_wrapper.h"
  35
  36 #include "dcn20/dcn20_resource.h"
  37 #include "dcn30/dcn30_resource.h"
  38 #include "dcn31/dcn31_resource.h"
  39 #include "dcn32/dcn32_resource.h"
  40
  41 #include "dcn10/dcn10_ipp.h"
  42 #include "dcn30/dcn30_hubbub.h"
  43 #include "dcn31/dcn31_hubbub.h"
  44 #include "dcn35/dcn35_hubbub.h"
  45 #include "dcn32/dcn32_mpc.h"
  46 #include "dcn35/dcn35_hubp.h"
  47 #include "irq/dcn35/irq_service_dcn35.h"
  48 #include "dcn35/dcn35_dpp.h"
  49 #include "dcn35/dcn35_optc.h"
  50 #include "dcn20/dcn20_hwseq.h"
  51 #include "dcn30/dcn30_hwseq.h"
  52 #include "dce110/dce110_hw_sequencer.h"
  53 #include "dcn35/dcn35_opp.h"
  54 #include "dcn35/dcn35_dsc.h"
  55 #include "dcn30/dcn30_vpg.h"
  56 #include "dcn30/dcn30_afmt.h"
  57 #include "dcn31/dcn31_dio_link_encoder.h"
  58 #include "dcn35/dcn35_dio_stream_encoder.h"
  59 #include "dcn31/dcn31_hpo_dp_stream_encoder.h"
  60 #include "dcn31/dcn31_hpo_dp_link_encoder.h"
  61 #include "dcn32/dcn32_hpo_dp_link_encoder.h"
  62 #include "link.h"
  63 #include "dcn31/dcn31_apg.h"
  64 #include "dcn32/dcn32_dio_link_encoder.h"
  65 #include "dcn31/dcn31_vpg.h"
  66 #include "dcn31/dcn31_afmt.h"
  67 #include "dce/dce_clock_source.h"
  68 #include "dce/dce_audio.h"
  69 #include "dce/dce_hwseq.h"
  70 #include "clk_mgr.h"
  71 #include "virtual/virtual_stream_encoder.h"
  72 #include "dce110/dce110_resource.h"
  73 #include "dml/display_mode_vba.h"
  74 #include "dcn35/dcn35_dccg.h"
  75 #include "dcn35/dcn35_pg_cntl.h"
  76 #include "dcn10/dcn10_resource.h"
  77 #include "dcn31/dcn31_panel_cntl.h"
  78 #include "dcn35_hwseq.h"
  79 #include "dcn35_dio_link_encoder.h"
  80 #include "dml/dcn31/dcn31_fpu.h" /*todo*/
  81 #include "dml/dcn35/dcn35_fpu.h"
  82 #include "dcn35/dcn35_dwb.h"
  83 #include "dcn35/dcn35_mmhubbub.h"
  84
  85 #include "dcn/dcn_3_5_0_offset.h"
  86 #include "dcn/dcn_3_5_0_sh_mask.h"
  87 #include "nbio/nbio_7_11_0_offset.h"
  88 #include "mmhub/mmhub_3_3_0_offset.h"
  89 #include "mmhub/mmhub_3_3_0_sh_mask.h"
  90
  91 #define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT                   0x0
  92 #define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK                     0x0000000FL
  93
  94 #include "reg_helper.h"
  95 #include "dce/dmub_abm.h"
  96 #include "dce/dmub_psr.h"
  97 #include "dce/dce_aux.h"
  98 #include "dce/dce_i2c.h"
  99 #include "dml/dcn31/display_mode_vba_31.h" /*temp*/
 100 #include "vm_helper.h"
 101 #include "dcn20/dcn20_vmid.h"
 102
 103 #include "link_enc_cfg.h"
 104 #define DC_LOGGER_INIT(logger)
 105
 106 enum dcn35_clk_src_array_id {
 107         DCN35_CLK_SRC_PLL0,
 108         DCN35_CLK_SRC_PLL1,
 109         DCN35_CLK_SRC_PLL2,
 110         DCN35_CLK_SRC_PLL3,
 111         DCN35_CLK_SRC_PLL4,
 112         DCN35_CLK_SRC_TOTAL
 113 };
 114
 115 /* begin *********************
 116  * macros to expend register list macro defined in HW object header file
 117  */
 118
 119 /* DCN */
 120 /* TODO awful hack. fixup dcn20_dwb.h */
 121 #undef BASE_INNER
 122 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
 123
 124 #define BASE(seg) BASE_INNER(seg)
 125
 126 #define SR(reg_name)\
 127                 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) +  \
 128                                         reg ## reg_name
 129
 130 #define SR_ARR(reg_name, id) \
 131         REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
 132
 133 #define SR_ARR_INIT(reg_name, id, value) \
 134         REG_STRUCT[id].reg_name = value
 135
 136 #define SRI(reg_name, block, id)\
 137         REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 138                                         reg ## block ## id ## _ ## reg_name
 139
 140 #define SRI_ARR(reg_name, block, id)\
 141         REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 142                 reg ## block ## id ## _ ## reg_name
 143
 144 #define SR_ARR_I2C(reg_name, id) \
 145         REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
 146
 147 #define SRI_ARR_I2C(reg_name, block, id)\
 148         REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 149                 reg ## block ## id ## _ ## reg_name
 150
 151 #define SRI_ARR_ALPHABET(reg_name, block, index, id)\
 152         REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 153                 reg ## block ## id ## _ ## reg_name
 154
 155 #define SRI2(reg_name, block, id)\
 156         .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
 157                                         reg ## reg_name
 158
 159 #define SRI2_ARR(reg_name, block, id)\
 160         REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) +  \
 161                 reg ## reg_name
 162
 163 #define SRIR(var_name, reg_name, block, id)\
 164         .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 165                                         reg ## block ## id ## _ ## reg_name
 166
 167 #define SRII(reg_name, block, id)\
 168         REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 169                                         reg ## block ## id ## _ ## reg_name
 170
 171 #define SRII_ARR_2(reg_name, block, id, inst)\
 172         REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 173                 reg ## block ## id ## _ ## reg_name
 174
 175 #define SRII_MPC_RMU(reg_name, block, id)\
 176         .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 177                                         reg ## block ## id ## _ ## reg_name
 178
 179 #define SRII_DWB(reg_name, temp_name, block, id)\
 180         REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
 181                 reg ## block ## id ## _ ## temp_name
 182
 183 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \
 184         .field_name = reg_name ## __ ## field_name ## post_fix
 185
 186 #define DCCG_SRII(reg_name, block, id)\
 187         REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 188                 reg ## block ## id ## _ ## reg_name
 189
 190 #define VUPDATE_SRII(reg_name, block, id)\
 191         REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
 192                 reg ## reg_name ## _ ## block ## id
 193
 194 /* NBIO */
 195 #define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg]
 196
 197 #define NBIO_BASE(seg) \
 198         NBIO_BASE_INNER(seg)
 199
 200 #define NBIO_SR(reg_name)\
 201         REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \
 202                                 regBIF_BX2_ ## reg_name
 203
 204 #define NBIO_SR_ARR(reg_name, id)\
 205         REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \
 206                 regBIF_BX2_ ## reg_name
 207
 208 #define bios_regs_init() \
 209                 ( \
 210                 NBIO_SR(BIOS_SCRATCH_3),\
 211                 NBIO_SR(BIOS_SCRATCH_6)\
 212                 )
 213
 214 static struct bios_registers bios_regs;
 215
 216 #define clk_src_regs_init(index, pllid)\
 217         CS_COMMON_REG_LIST_DCN3_0_RI(index, pllid)
 218
 219 static struct dce110_clk_src_regs clk_src_regs[5];
 220
 221 static const struct dce110_clk_src_shift cs_shift = {
 222                 CS_COMMON_MASK_SH_LIST_DCN3_1_4(__SHIFT)
 223 };
 224
 225 static const struct dce110_clk_src_mask cs_mask = {
 226                 CS_COMMON_MASK_SH_LIST_DCN3_1_4(_MASK)
 227 };
 228
 229 #define abm_regs_init(id)\
 230                 ABM_DCN32_REG_LIST_RI(id)
 231
 232 static struct dce_abm_registers abm_regs[4];
 233
 234 static const struct dce_abm_shift abm_shift = {
 235                 ABM_MASK_SH_LIST_DCN35(__SHIFT)
 236 };
 237
 238 static const struct dce_abm_mask abm_mask = {
 239                 ABM_MASK_SH_LIST_DCN35(_MASK)
 240 };
 241
 242 #define audio_regs_init(id)\
 243                 AUD_COMMON_REG_LIST_RI(id)
 244
 245 static struct dce_audio_registers audio_regs[7];
 246
 247
 248 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
 249                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
 250                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
 251                 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
 252
 253 static const struct dce_audio_shift audio_shift = {
 254                 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
 255 };
 256
 257 static const struct dce_audio_mask audio_mask = {
 258                 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
 259 };
 260
 261 #define vpg_regs_init(id)\
 262         VPG_DCN31_REG_LIST_RI(id)
 263
 264 static struct dcn31_vpg_registers vpg_regs[10];
 265
 266 static const struct dcn31_vpg_shift vpg_shift = {
 267         DCN31_VPG_MASK_SH_LIST(__SHIFT)
 268 };
 269
 270 static const struct dcn31_vpg_mask vpg_mask = {
 271         DCN31_VPG_MASK_SH_LIST(_MASK)
 272 };
 273
 274 #define afmt_regs_init(id)\
 275         AFMT_DCN31_REG_LIST_RI(id)
 276
 277 static struct dcn31_afmt_registers afmt_regs[6];
 278
 279 static const struct dcn31_afmt_shift afmt_shift = {
 280         DCN31_AFMT_MASK_SH_LIST(__SHIFT)
 281 };
 282
 283 static const struct dcn31_afmt_mask afmt_mask = {
 284         DCN31_AFMT_MASK_SH_LIST(_MASK)
 285 };
 286
 287 #define apg_regs_init(id)\
 288         APG_DCN31_REG_LIST_RI(id)
 289
 290 static struct dcn31_apg_registers apg_regs[4];
 291
 292 static const struct dcn31_apg_shift apg_shift = {
 293         DCN31_APG_MASK_SH_LIST(__SHIFT)
 294 };
 295
 296 static const struct dcn31_apg_mask apg_mask = {
 297         DCN31_APG_MASK_SH_LIST(_MASK)
 298 };
 299
 300 #define stream_enc_regs_init(id)\
 301         SE_DCN35_REG_LIST_RI(id)
 302
 303 static struct dcn10_stream_enc_registers stream_enc_regs[5];
 304
 305 static const struct dcn10_stream_encoder_shift se_shift = {
 306                 SE_COMMON_MASK_SH_LIST_DCN35(__SHIFT)
 307 };
 308
 309 static const struct dcn10_stream_encoder_mask se_mask = {
 310                 SE_COMMON_MASK_SH_LIST_DCN35(_MASK)
 311 };
 312
 313 #define aux_regs_init(id)\
 314         DCN2_AUX_REG_LIST_RI(id)
 315
 316 static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5];
 317
 318 #define hpd_regs_init(id)\
 319         HPD_REG_LIST_RI(id)
 320
 321 static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5];
 322
 323
 324 static const struct dce110_aux_registers_shift aux_shift = {
 325         DCN_AUX_MASK_SH_LIST(__SHIFT)
 326 };
 327
 328 static const struct dce110_aux_registers_mask aux_mask = {
 329         DCN_AUX_MASK_SH_LIST(_MASK)
 330 };
 331
 332 #define link_regs_init(id, phyid)\
 333         ( \
 334         LE_DCN35_REG_LIST_RI(id), \
 335         UNIPHY_DCN2_REG_LIST_RI(id, phyid)\
 336         )
 337
 338 static struct dcn10_link_enc_registers link_enc_regs[5];
 339
 340 static const struct dcn10_link_enc_shift le_shift = {
 341         LINK_ENCODER_MASK_SH_LIST_DCN35(__SHIFT), \
 342         //DPCS_DCN31_MASK_SH_LIST(__SHIFT)
 343 };
 344
 345 static const struct dcn10_link_enc_mask le_mask = {
 346         LINK_ENCODER_MASK_SH_LIST_DCN35(_MASK), \
 347         //DPCS_DCN31_MASK_SH_LIST(_MASK)
 348 };
 349
 350 #define hpo_dp_stream_encoder_reg_init(id)\
 351         DCN3_1_HPO_DP_STREAM_ENC_REG_LIST_RI(id)
 352
 353 static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4];
 354
 355 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
 356         DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
 357 };
 358
 359 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
 360         DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
 361 };
 362
 363 #define hpo_dp_link_encoder_reg_init(id)\
 364         DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id)
 365         /*DCN3_1_RDPCSTX_REG_LIST(0),*/
 366         /*DCN3_1_RDPCSTX_REG_LIST(1),*/
 367         /*DCN3_1_RDPCSTX_REG_LIST(2),*/
 368         /*DCN3_1_RDPCSTX_REG_LIST(3),*/
 369
 370 static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[2];
 371
 372 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
 373         DCN3_1_HPO_DP_LINK_ENC_COMMON_MASK_SH_LIST(__SHIFT)
 374 };
 375
 376 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
 377         DCN3_1_HPO_DP_LINK_ENC_COMMON_MASK_SH_LIST(_MASK)
 378 };
 379
 380 #define dpp_regs_init(id)\
 381         DPP_REG_LIST_DCN35_RI(id)
 382
 383 static struct dcn3_dpp_registers dpp_regs[4];
 384
 385 static const struct dcn35_dpp_shift tf_shift = {
 386                 DPP_REG_LIST_SH_MASK_DCN35(__SHIFT)
 387 };
 388
 389 static const struct dcn35_dpp_mask tf_mask = {
 390                 DPP_REG_LIST_SH_MASK_DCN35(_MASK)
 391 };
 392
 393 #define opp_regs_init(id)\
 394         OPP_REG_LIST_DCN35_RI(id)
 395
 396 static struct dcn35_opp_registers opp_regs[4];
 397
 398 static const struct dcn35_opp_shift opp_shift = {
 399         OPP_MASK_SH_LIST_DCN35(__SHIFT)
 400 };
 401
 402 static const struct dcn35_opp_mask opp_mask = {
 403         OPP_MASK_SH_LIST_DCN35(_MASK)
 404 };
 405
 406 #define aux_engine_regs_init(id)\
 407         ( \
 408         AUX_COMMON_REG_LIST0_RI(id), \
 409         SR_ARR_INIT(AUXN_IMPCAL, id, 0), \
 410         SR_ARR_INIT(AUXP_IMPCAL, id, 0), \
 411         SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK) \
 412         )
 413
 414 static struct dce110_aux_registers aux_engine_regs[5];
 415
 416 #define dwbc_regs_dcn3_init(id)\
 417         DWBC_COMMON_REG_LIST_DCN30_RI(id)
 418
 419 static struct dcn30_dwbc_registers dwbc35_regs[1];
 420
 421 static const struct dcn35_dwbc_shift dwbc35_shift = {
 422         DWBC_COMMON_MASK_SH_LIST_DCN35(__SHIFT)
 423 };
 424
 425 static const struct dcn35_dwbc_mask dwbc35_mask = {
 426         DWBC_COMMON_MASK_SH_LIST_DCN35(_MASK)
 427 };
 428
 429 #define mcif_wb_regs_dcn3_init(id)\
 430         MCIF_WB_COMMON_REG_LIST_DCN3_5_RI(id)
 431
 432 static struct dcn35_mmhubbub_registers mcif_wb35_regs[1];
 433
 434 static const struct dcn35_mmhubbub_shift mcif_wb35_shift = {
 435         MCIF_WB_COMMON_MASK_SH_LIST_DCN3_5(__SHIFT)
 436 };
 437
 438 static const struct dcn35_mmhubbub_mask mcif_wb35_mask = {
 439         MCIF_WB_COMMON_MASK_SH_LIST_DCN3_5(_MASK)
 440 };
 441
 442 #define dsc_regsDCN35_init(id)\
 443         DSC_REG_LIST_DCN20_RI(id)
 444
 445 static struct dcn20_dsc_registers dsc_regs[4];
 446
 447 static const struct dcn35_dsc_shift dsc_shift = {
 448         DSC_REG_LIST_SH_MASK_DCN35(__SHIFT)
 449 };
 450
 451 static const struct dcn35_dsc_mask dsc_mask = {
 452         DSC_REG_LIST_SH_MASK_DCN35(_MASK)
 453 };
 454
 455 static struct dcn30_mpc_registers mpc_regs;
 456
 457 #define dcn_mpc_regs_init() \
 458         MPC_REG_LIST_DCN3_2_RI(0),\
 459         MPC_REG_LIST_DCN3_2_RI(1),\
 460         MPC_REG_LIST_DCN3_2_RI(2),\
 461         MPC_REG_LIST_DCN3_2_RI(3),\
 462         MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0),\
 463         MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1),\
 464         MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2),\
 465         MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3),\
 466         MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0)
 467
 468 static const struct dcn30_mpc_shift mpc_shift = {
 469         MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
 470 };
 471
 472 static const struct dcn30_mpc_mask mpc_mask = {
 473         MPC_COMMON_MASK_SH_LIST_DCN32(_MASK)
 474 };
 475
 476 #define optc_regs_init(id)\
 477         OPTC_COMMON_REG_LIST_DCN3_5_RI(id)
 478
 479 static struct dcn_optc_registers optc_regs[4];
 480
 481 static const struct dcn_optc_shift optc_shift = {
 482         OPTC_COMMON_MASK_SH_LIST_DCN3_5(__SHIFT)
 483 };
 484
 485 static const struct dcn_optc_mask optc_mask = {
 486         OPTC_COMMON_MASK_SH_LIST_DCN3_5(_MASK)
 487 };
 488
 489 #define hubp_regs_init(id)\
 490         HUBP_REG_LIST_DCN30_RI(id)
 491
 492 static struct dcn_hubp2_registers hubp_regs[4];
 493
 494
 495 static const struct dcn35_hubp2_shift hubp_shift = {
 496                 HUBP_MASK_SH_LIST_DCN35(__SHIFT)
 497 };
 498
 499 static const struct dcn35_hubp2_mask hubp_mask = {
 500                 HUBP_MASK_SH_LIST_DCN35(_MASK)
 501 };
 502
 503 static struct dcn_hubbub_registers hubbub_reg;
 504
 505 #define hubbub_reg_init()\
 506                 HUBBUB_REG_LIST_DCN35(0)
 507
 508 static const struct dcn_hubbub_shift hubbub_shift = {
 509                 HUBBUB_MASK_SH_LIST_DCN35(__SHIFT)
 510 };
 511
 512 static const struct dcn_hubbub_mask hubbub_mask = {
 513                 HUBBUB_MASK_SH_LIST_DCN35(_MASK)
 514 };
 515
 516 static struct dccg_registers dccg_regs;
 517
 518 #define dccg_regs_init()\
 519         DCCG_REG_LIST_DCN35()
 520
 521 static const struct dccg_shift dccg_shift = {
 522                 DCCG_MASK_SH_LIST_DCN35(__SHIFT)
 523 };
 524
 525 static const struct dccg_mask dccg_mask = {
 526                 DCCG_MASK_SH_LIST_DCN35(_MASK)
 527 };
 528
 529 static struct pg_cntl_registers pg_cntl_regs;
 530
 531 #define pg_cntl_dcn35_regs_init() \
 532         PG_CNTL_REG_LIST_DCN35()
 533
 534 static const struct pg_cntl_shift pg_cntl_shift = {
 535                 PG_CNTL_MASK_SH_LIST_DCN35(__SHIFT)
 536 };
 537
 538 static const struct pg_cntl_mask pg_cntl_mask = {
 539                 PG_CNTL_MASK_SH_LIST_DCN35(_MASK)
 540 };
 541
 542 #define SRII2(reg_name_pre, reg_name_post, id)\
 543         .reg_name_pre ## _ ##  reg_name_post[id] = BASE(reg ## reg_name_pre \
 544                         ## id ## _ ## reg_name_post ## _BASE_IDX) + \
 545                         reg ## reg_name_pre ## id ## _ ## reg_name_post
 546
 547 static struct dce_hwseq_registers hwseq_reg;
 548
 549 #define hwseq_reg_init()\
 550         HWSEQ_DCN35_REG_LIST()
 551
 552 #define HWSEQ_DCN35_MASK_SH_LIST(mask_sh)\
 553         HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
 554         HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
 555         HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \
 556         HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 557         HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 558         HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 559         HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 560         HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 561         HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 562         HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 563         HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 564         HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 565         HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 566         HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 567         HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 568         HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 569         HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 570         HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 571         HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 572         HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 573         HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 574         HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 575         HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 576         HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 577         HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 578         HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 579         HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 580         HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 581         HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 582         HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 583         HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 584         HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 585         HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 586         HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 587         HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 588         HWS_SF(, DOMAIN22_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 589         HWS_SF(, DOMAIN23_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 590         HWS_SF(, DOMAIN24_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 591         HWS_SF(, DOMAIN25_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 592         HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
 593         HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
 594         HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
 595         HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
 596         HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
 597         HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \
 598         HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh),\
 599         HWS_SF(, DMU_CLK_CNTL, DISPCLK_R_DMU_GATE_DIS, mask_sh),\
 600         HWS_SF(, DMU_CLK_CNTL, DISPCLK_G_RBBMIF_GATE_DIS, mask_sh),\
 601         HWS_SF(, DMU_CLK_CNTL, RBBMIF_FGCG_REP_DIS, mask_sh),\
 602         HWS_SF(, DMU_CLK_CNTL, DPREFCLK_ALLOW_DS_CLKSTOP, mask_sh),\
 603         HWS_SF(, DMU_CLK_CNTL, DISPCLK_ALLOW_DS_CLKSTOP, mask_sh),\
 604         HWS_SF(, DMU_CLK_CNTL, DPPCLK_ALLOW_DS_CLKSTOP, mask_sh),\
 605         HWS_SF(, DMU_CLK_CNTL, DTBCLK_ALLOW_DS_CLKSTOP, mask_sh),\
 606         HWS_SF(, DMU_CLK_CNTL, DCFCLK_ALLOW_DS_CLKSTOP, mask_sh),\
 607         HWS_SF(, DMU_CLK_CNTL, DPIACLK_ALLOW_DS_CLKSTOP, mask_sh),\
 608         HWS_SF(, DMU_CLK_CNTL, LONO_FGCG_REP_DIS, mask_sh),\
 609         HWS_SF(, DMU_CLK_CNTL, LONO_DISPCLK_GATE_DISABLE, mask_sh),\
 610         HWS_SF(, DMU_CLK_CNTL, LONO_SOCCLK_GATE_DISABLE, mask_sh),\
 611         HWS_SF(, DMU_CLK_CNTL, LONO_DMCUBCLK_GATE_DISABLE, mask_sh)
 612
 613 static const struct dce_hwseq_shift hwseq_shift = {
 614                 HWSEQ_DCN35_MASK_SH_LIST(__SHIFT)
 615 };
 616
 617 static const struct dce_hwseq_mask hwseq_mask = {
 618                 HWSEQ_DCN35_MASK_SH_LIST(_MASK)
 619 };
 620
 621 #define vmid_regs_init(id)\
 622                 DCN20_VMID_REG_LIST_RI(id)
 623
 624 static struct dcn_vmid_registers vmid_regs[16];
 625
 626 static const struct dcn20_vmid_shift vmid_shifts = {
 627                 DCN20_VMID_MASK_SH_LIST(__SHIFT)
 628 };
 629
 630 static const struct dcn20_vmid_mask vmid_masks = {
 631                 DCN20_VMID_MASK_SH_LIST(_MASK)
 632 };
 633
 634 static const struct resource_caps res_cap_dcn35 = {
 635         .num_timing_generator = 4,
 636         .num_opp = 4,
 637         .num_video_plane = 4,
 638         .num_audio = 5,
 639         .num_stream_encoder = 5,
 640         .num_dig_link_enc = 5,
 641         .num_hpo_dp_stream_encoder = 4,
 642         .num_hpo_dp_link_encoder = 2,
 643         .num_pll = 4,/*1 c10 edp, 3xc20 combo PHY*/
 644         .num_dwb = 1,
 645         .num_ddc = 5,
 646         .num_vmid = 16,
 647         .num_mpc_3dlut = 2,
 648         .num_dsc = 4,
 649 };
 650
 651 static const struct dc_plane_cap plane_cap = {
 652         .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
 653         .per_pixel_alpha = true,
 654
 655         .pixel_format_support = {
 656                         .argb8888 = true,
 657                         .nv12 = true,
 658                         .fp16 = true,
 659                         .p010 = true,
 660                         .ayuv = false,
 661         },
 662
 663         .max_upscale_factor = {
 664                         .argb8888 = 16000,
 665                         .nv12 = 16000,
 666                         .fp16 = 16000
 667         },
 668
 669         // 6:1 downscaling ratio: 1000/6 = 166.666
 670         .max_downscale_factor = {
 671                         .argb8888 = 167,
 672                         .nv12 = 167,
 673                         .fp16 = 167
 674         },
 675         64,
 676         64
 677 };
 678
 679 static const struct dc_debug_options debug_defaults_drv = {
 680         .disable_dmcu = true,
 681         .force_abm_enable = false,
 682         .timing_trace = false,
 683         .clock_trace = true,
 684         .disable_pplib_clock_request = false,
 685         .pipe_split_policy = MPC_SPLIT_AVOID,
 686         .force_single_disp_pipe_split = false,
 687         .disable_dcc = DCC_ENABLE,
 688         .disable_dpp_power_gate = true,
 689         .disable_hubp_power_gate = true,
 690         .disable_clock_gate = true,
 691         .disable_dsc_power_gate = true,
 692         .vsr_support = true,
 693         .performance_trace = false,
 694         .max_downscale_src_width = 4096,/*upto true 4k*/
 695         .disable_pplib_wm_range = false,
 696         .scl_reset_length10 = true,
 697         .sanity_checks = false,
 698         .underflow_assert_delay_us = 0xFFFFFFFF,
 699         .dwb_fi_phase = -1, // -1 = disable,
 700         .dmub_command_table = true,
 701         .pstate_enabled = false,
 702         .use_max_lb = true,
 703         .enable_mem_low_power = {
 704                 .bits = {
 705                         .vga = false,
 706                         .i2c = true,
 707                         .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
 708                         .dscl = true,
 709                         .cm = true,
 710                         .mpc = true,
 711                         .optc = true,
 712                         .vpg = true,
 713                         .afmt = true,
 714                 }
 715         },
 716         .root_clock_optimization = {
 717                 .bits = {
 718                         .dpp = true,
 719                         .dsc = true,/*dscclk and dsc pg*/
 720                         .hdmistream = false,
 721                         .hdmichar = false,
 722                         .dpstream = false,
 723                         .symclk32_se = false,
 724                         .symclk32_le = false,
 725                         .symclk_fe = false,
 726                         .physymclk = false,
 727                         .dpiasymclk = false,
 728                 }
 729         },
 730         .seamless_boot_odm_combine = DML_FAIL_SOURCE_PIXEL_FORMAT,
 731         .enable_z9_disable_interface = true, /* Allow support for the PMFW interface for disable Z9*/
 732         .using_dml2 = true,
 733         .support_eDP1_5 = true,
 734         .enable_hpo_pg_support = false,
 735         .enable_legacy_fast_update = true,
 736         .enable_single_display_2to1_odm_policy = false,
 737         .disable_idle_power_optimizations = true,
 738         .dmcub_emulation = false,
 739         .disable_boot_optimizations = false,
 740         .disable_unbounded_requesting = false,
 741         .disable_mem_low_power = false,
 742         .enable_hpo_pg_support = false,
 743         //must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions
 744         .enable_double_buffered_dsc_pg_support = true,
 745         .enable_dp_dig_pixel_rate_div_policy = 1,
 746         .disable_z10 = false,
 747         .ignore_pg = true,
 748         .psp_disabled_wa = true,
 749         .ips2_eval_delay_us = 200,
 750         .ips2_entry_delay_us = 400
 751 };
 752
 753 static const struct dc_panel_config panel_config_defaults = {
 754         .psr = {
 755                 .disable_psr = false,
 756                 .disallow_psrsu = false,
 757         },
 758         .ilr = {
 759                 .optimize_edp_link_rate = true,
 760         },
 761 };
 762
 763 static void dcn35_dpp_destroy(struct dpp **dpp)
 764 {
 765         kfree(TO_DCN20_DPP(*dpp));
 766         *dpp = NULL;
 767 }
 768
 769 static struct dpp *dcn35_dpp_create(struct dc_context *ctx, uint32_t inst)
 770 {
 771         struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
 772         bool success = (dpp != NULL);
 773
 774         if (!success)
 775                 return NULL;
 776
 777 #undef REG_STRUCT
 778 #define REG_STRUCT dpp_regs
 779         dpp_regs_init(0),
 780         dpp_regs_init(1),
 781         dpp_regs_init(2),
 782         dpp_regs_init(3);
 783
 784         success = dpp35_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift,
 785                                   &tf_mask);
 786         if (success) {
 787                 dpp35_set_fgcg(
 788                         dpp,
 789                         ctx->dc->debug.enable_fine_grain_clock_gating.bits.dpp);
 790                 return &dpp->base;
 791         }
 792
 793         BREAK_TO_DEBUGGER();
 794         kfree(dpp);
 795         return NULL;
 796 }
 797
 798 static struct output_pixel_processor *dcn35_opp_create(
 799         struct dc_context *ctx, uint32_t inst)
 800 {
 801         struct dcn20_opp *opp =
 802                 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
 803
 804         if (!opp) {
 805                 BREAK_TO_DEBUGGER();
 806                 return NULL;
 807         }
 808
 809 #undef REG_STRUCT
 810 #define REG_STRUCT opp_regs
 811         opp_regs_init(0),
 812         opp_regs_init(1),
 813         opp_regs_init(2),
 814         opp_regs_init(3);
 815
 816         dcn35_opp_construct(opp, ctx, inst,
 817                         &opp_regs[inst], &opp_shift, &opp_mask);
 818
 819         dcn35_opp_set_fgcg(opp, ctx->dc->debug.enable_fine_grain_clock_gating.bits.opp);
 820
 821         return &opp->base;
 822 }
 823
 824 static struct dce_aux *dcn31_aux_engine_create(
 825         struct dc_context *ctx,
 826         uint32_t inst)
 827 {
 828         struct aux_engine_dce110 *aux_engine =
 829                 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
 830
 831         if (!aux_engine)
 832                 return NULL;
 833
 834 #undef REG_STRUCT
 835 #define REG_STRUCT aux_engine_regs
 836         aux_engine_regs_init(0),
 837         aux_engine_regs_init(1),
 838         aux_engine_regs_init(2),
 839         aux_engine_regs_init(3),
 840         aux_engine_regs_init(4);
 841
 842         dce110_aux_engine_construct(aux_engine, ctx, inst,
 843                                     SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
 844                                     &aux_engine_regs[inst],
 845                                         &aux_mask,
 846                                         &aux_shift,
 847                                         ctx->dc->caps.extended_aux_timeout_support);
 848
 849         return &aux_engine->base;
 850 }
 851
 852 #define i2c_inst_regs_init(id)\
 853         I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id)
 854
 855 static struct dce_i2c_registers i2c_hw_regs[5];
 856
 857 static const struct dce_i2c_shift i2c_shifts = {
 858                 I2C_COMMON_MASK_SH_LIST_DCN35(__SHIFT)
 859 };
 860
 861 static const struct dce_i2c_mask i2c_masks = {
 862                 I2C_COMMON_MASK_SH_LIST_DCN35(_MASK)
 863 };
 864
 865 /* ========================================================== */
 866
 867 /*
 868  * DPIA index | Preferred Encoder     |    Host Router
 869  *   0        |      C                |       0
 870  *   1        |      First Available  |       0
 871  *   2        |      D                |       1
 872  *   3        |      First Available  |       1
 873  */
 874 /* ========================================================== */
 875 static const enum engine_id dpia_to_preferred_enc_id_table[] = {
 876                 ENGINE_ID_DIGC,
 877                 ENGINE_ID_DIGC,
 878                 ENGINE_ID_DIGD,
 879                 ENGINE_ID_DIGD
 880 };
 881
 882 static enum engine_id dcn35_get_preferred_eng_id_dpia(unsigned int dpia_index)
 883 {
 884         return dpia_to_preferred_enc_id_table[dpia_index];
 885 }
 886
 887 static struct dce_i2c_hw *dcn31_i2c_hw_create(
 888         struct dc_context *ctx,
 889         uint32_t inst)
 890 {
 891         struct dce_i2c_hw *dce_i2c_hw =
 892                 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
 893
 894         if (!dce_i2c_hw)
 895                 return NULL;
 896
 897 #undef REG_STRUCT
 898 #define REG_STRUCT i2c_hw_regs
 899         i2c_inst_regs_init(1),
 900         i2c_inst_regs_init(2),
 901         i2c_inst_regs_init(3),
 902         i2c_inst_regs_init(4),
 903         i2c_inst_regs_init(5);
 904
 905         dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
 906                                     &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
 907
 908         return dce_i2c_hw;
 909 }
 910 static struct mpc *dcn35_mpc_create(
 911                 struct dc_context *ctx,
 912                 int num_mpcc,
 913                 int num_rmu)
 914 {
 915         struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), GFP_KERNEL);
 916
 917         if (!mpc30)
 918                 return NULL;
 919
 920 #undef REG_STRUCT
 921 #define REG_STRUCT mpc_regs
 922         dcn_mpc_regs_init();
 923
 924         dcn32_mpc_construct(mpc30, ctx,
 925                         &mpc_regs,
 926                         &mpc_shift,
 927                         &mpc_mask,
 928                         num_mpcc,
 929                         num_rmu);
 930
 931         return &mpc30->base;
 932 }
 933
 934 static struct hubbub *dcn35_hubbub_create(struct dc_context *ctx)
 935 {
 936         int i;
 937
 938         struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),
 939                                           GFP_KERNEL);
 940
 941         if (!hubbub3)
 942                 return NULL;
 943
 944 #undef REG_STRUCT
 945 #define REG_STRUCT hubbub_reg
 946         hubbub_reg_init();
 947
 948 #undef REG_STRUCT
 949 #define REG_STRUCT vmid_regs
 950         vmid_regs_init(0),
 951         vmid_regs_init(1),
 952         vmid_regs_init(2),
 953         vmid_regs_init(3),
 954         vmid_regs_init(4),
 955         vmid_regs_init(5),
 956         vmid_regs_init(6),
 957         vmid_regs_init(7),
 958         vmid_regs_init(8),
 959         vmid_regs_init(9),
 960         vmid_regs_init(10),
 961         vmid_regs_init(11),
 962         vmid_regs_init(12),
 963         vmid_regs_init(13),
 964         vmid_regs_init(14),
 965         vmid_regs_init(15);
 966
 967         hubbub35_construct(hubbub3, ctx,
 968                         &hubbub_reg,
 969                         &hubbub_shift,
 970                         &hubbub_mask,
 971                         384,/*ctx->dc->dml.ip.det_buffer_size_kbytes,*/
 972                         8, /*ctx->dc->dml.ip.pixel_chunk_size_kbytes,*/
 973                         1792 /*ctx->dc->dml.ip.config_return_buffer_size_in_kbytes*/);
 974
 975
 976         for (i = 0; i < res_cap_dcn35.num_vmid; i++) {
 977                 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
 978
 979                 vmid->ctx = ctx;
 980
 981                 vmid->regs = &vmid_regs[i];
 982                 vmid->shifts = &vmid_shifts;
 983                 vmid->masks = &vmid_masks;
 984         }
 985
 986         return &hubbub3->base;
 987 }
 988
 989 static struct timing_generator *dcn35_timing_generator_create(
 990                 struct dc_context *ctx,
 991                 uint32_t instance)
 992 {
 993         struct optc *tgn10 =
 994                 kzalloc(sizeof(struct optc), GFP_KERNEL);
 995
 996         if (!tgn10)
 997                 return NULL;
 998
 999 #undef REG_STRUCT
1000 #define REG_STRUCT optc_regs
1001         optc_regs_init(0),
1002         optc_regs_init(1),
1003         optc_regs_init(2),
1004         optc_regs_init(3);
1005
1006         tgn10->base.inst = instance;
1007         tgn10->base.ctx = ctx;
1008
1009         tgn10->tg_regs = &optc_regs[instance];
1010         tgn10->tg_shift = &optc_shift;
1011         tgn10->tg_mask = &optc_mask;
1012
1013         dcn35_timing_generator_init(tgn10);
1014
1015         return &tgn10->base;
1016 }
1017
1018 static const struct encoder_feature_support link_enc_feature = {
1019                 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1020                 .max_hdmi_pixel_clock = 600000,
1021                 .hdmi_ycbcr420_supported = true,
1022                 .dp_ycbcr420_supported = true,
1023                 .fec_supported = true,
1024                 .flags.bits.IS_HBR2_CAPABLE = true,
1025                 .flags.bits.IS_HBR3_CAPABLE = true,
1026                 .flags.bits.IS_TPS3_CAPABLE = true,
1027                 .flags.bits.IS_TPS4_CAPABLE = true
1028 };
1029
1030 static struct link_encoder *dcn35_link_encoder_create(
1031         struct dc_context *ctx,
1032         const struct encoder_init_data *enc_init_data)
1033 {
1034         struct dcn20_link_encoder *enc20 =
1035                 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1036
1037         if (!enc20)
1038                 return NULL;
1039
1040 #undef REG_STRUCT
1041 #define REG_STRUCT link_enc_aux_regs
1042         aux_regs_init(0),
1043         aux_regs_init(1),
1044         aux_regs_init(2),
1045         aux_regs_init(3),
1046         aux_regs_init(4);
1047
1048 #undef REG_STRUCT
1049 #define REG_STRUCT link_enc_hpd_regs
1050         hpd_regs_init(0),
1051         hpd_regs_init(1),
1052         hpd_regs_init(2),
1053         hpd_regs_init(3),
1054         hpd_regs_init(4);
1055
1056 #undef REG_STRUCT
1057 #define REG_STRUCT link_enc_regs
1058         link_regs_init(0, A),
1059         link_regs_init(1, B),
1060         link_regs_init(2, C),
1061         link_regs_init(3, D),
1062         link_regs_init(4, E);
1063
1064         dcn35_link_encoder_construct(enc20,
1065                         enc_init_data,
1066                         &link_enc_feature,
1067                         &link_enc_regs[enc_init_data->transmitter],
1068                         &link_enc_aux_regs[enc_init_data->channel - 1],
1069                         &link_enc_hpd_regs[enc_init_data->hpd_source],
1070                         &le_shift,
1071                         &le_mask);
1072
1073         return &enc20->enc10.base;
1074 }
1075
1076 /* Create a minimal link encoder object not associated with a particular
1077  * physical connector.
1078  * resource_funcs.link_enc_create_minimal
1079  */
1080 static struct link_encoder *dcn31_link_enc_create_minimal(
1081                 struct dc_context *ctx, enum engine_id eng_id)
1082 {
1083         struct dcn20_link_encoder *enc20;
1084
1085         if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
1086                 return NULL;
1087
1088         enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1089         if (!enc20)
1090                 return NULL;
1091
1092         dcn31_link_encoder_construct_minimal(
1093                         enc20,
1094                         ctx,
1095                         &link_enc_feature,
1096                         &link_enc_regs[eng_id - ENGINE_ID_DIGA],
1097                         eng_id);
1098
1099         return &enc20->enc10.base;
1100 }
1101
1102 static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1103 {
1104         struct dcn31_panel_cntl *panel_cntl =
1105                 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL);
1106
1107         if (!panel_cntl)
1108                 return NULL;
1109
1110         dcn31_panel_cntl_construct(panel_cntl, init_data);
1111
1112         return &panel_cntl->base;
1113 }
1114
1115 static void read_dce_straps(
1116         struct dc_context *ctx,
1117         struct resource_straps *straps)
1118 {
1119         generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),
1120                 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1121
1122 }
1123
1124 static struct audio *dcn31_create_audio(
1125                 struct dc_context *ctx, unsigned int inst)
1126 {
1127
1128 #undef REG_STRUCT
1129 #define REG_STRUCT audio_regs
1130         audio_regs_init(0),
1131         audio_regs_init(1),
1132         audio_regs_init(2),
1133         audio_regs_init(3),
1134         audio_regs_init(4);
1135         audio_regs_init(5);
1136         audio_regs_init(6);
1137
1138         return dce_audio_create(ctx, inst,
1139                         &audio_regs[inst], &audio_shift, &audio_mask);
1140 }
1141
1142 static struct vpg *dcn31_vpg_create(
1143         struct dc_context *ctx,
1144         uint32_t inst)
1145 {
1146         struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL);
1147
1148         if (!vpg31)
1149                 return NULL;
1150
1151 #undef REG_STRUCT
1152 #define REG_STRUCT vpg_regs
1153         vpg_regs_init(0),
1154         vpg_regs_init(1),
1155         vpg_regs_init(2),
1156         vpg_regs_init(3),
1157         vpg_regs_init(4),
1158         vpg_regs_init(5),
1159         vpg_regs_init(6),
1160         vpg_regs_init(7),
1161         vpg_regs_init(8),
1162         vpg_regs_init(9);
1163
1164         vpg31_construct(vpg31, ctx, inst,
1165                         &vpg_regs[inst],
1166                         &vpg_shift,
1167                         &vpg_mask);
1168
1169         return &vpg31->base;
1170 }
1171
1172 static struct afmt *dcn31_afmt_create(
1173         struct dc_context *ctx,
1174         uint32_t inst)
1175 {
1176         struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL);
1177
1178         if (!afmt31)
1179                 return NULL;
1180
1181 #undef REG_STRUCT
1182 #define REG_STRUCT afmt_regs
1183         afmt_regs_init(0),
1184         afmt_regs_init(1),
1185         afmt_regs_init(2),
1186         afmt_regs_init(3),
1187         afmt_regs_init(4),
1188         afmt_regs_init(5);
1189
1190         afmt31_construct(afmt31, ctx, inst,
1191                         &afmt_regs[inst],
1192                         &afmt_shift,
1193                         &afmt_mask);
1194
1195         // Light sleep by default, no need to power down here
1196
1197         return &afmt31->base;
1198 }
1199
1200 static struct apg *dcn31_apg_create(
1201         struct dc_context *ctx,
1202         uint32_t inst)
1203 {
1204         struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL);
1205
1206         if (!apg31)
1207                 return NULL;
1208
1209 #undef REG_STRUCT
1210 #define REG_STRUCT apg_regs
1211         apg_regs_init(0),
1212         apg_regs_init(1),
1213         apg_regs_init(2),
1214         apg_regs_init(3);
1215
1216         apg31_construct(apg31, ctx, inst,
1217                         &apg_regs[inst],
1218                         &apg_shift,
1219                         &apg_mask);
1220
1221         return &apg31->base;
1222 }
1223
1224 static struct stream_encoder *dcn35_stream_encoder_create(
1225         enum engine_id eng_id,
1226         struct dc_context *ctx)
1227 {
1228         struct dcn10_stream_encoder *enc1;
1229         struct vpg *vpg;
1230         struct afmt *afmt;
1231         int vpg_inst;
1232         int afmt_inst;
1233
1234         /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1235         if (eng_id <= ENGINE_ID_DIGF) {
1236                 vpg_inst = eng_id;
1237                 afmt_inst = eng_id;
1238         } else
1239                 return NULL;
1240
1241         enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1242         vpg = dcn31_vpg_create(ctx, vpg_inst);
1243         afmt = dcn31_afmt_create(ctx, afmt_inst);
1244
1245         if (!enc1 || !vpg || !afmt) {
1246                 kfree(enc1);
1247                 kfree(vpg);
1248                 kfree(afmt);
1249                 return NULL;
1250         }
1251
1252 #undef REG_STRUCT
1253 #define REG_STRUCT stream_enc_regs
1254         stream_enc_regs_init(0),
1255         stream_enc_regs_init(1),
1256         stream_enc_regs_init(2),
1257         stream_enc_regs_init(3),
1258         stream_enc_regs_init(4);
1259
1260         dcn35_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1261                                         eng_id, vpg, afmt,
1262                                         &stream_enc_regs[eng_id],
1263                                         &se_shift, &se_mask);
1264
1265         return &enc1->base;
1266 }
1267
1268 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create(
1269         enum engine_id eng_id,
1270         struct dc_context *ctx)
1271 {
1272         struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1273         struct vpg *vpg;
1274         struct apg *apg;
1275         uint32_t hpo_dp_inst;
1276         uint32_t vpg_inst;
1277         uint32_t apg_inst;
1278
1279         ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1280         hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1281
1282         /* Mapping of VPG register blocks to HPO DP block instance:
1283          * VPG[6] -> HPO_DP[0]
1284          * VPG[7] -> HPO_DP[1]
1285          * VPG[8] -> HPO_DP[2]
1286          * VPG[9] -> HPO_DP[3]
1287          */
1288         vpg_inst = hpo_dp_inst + 6;
1289
1290         /* Mapping of APG register blocks to HPO DP block instance:
1291          * APG[0] -> HPO_DP[0]
1292          * APG[1] -> HPO_DP[1]
1293          * APG[2] -> HPO_DP[2]
1294          * APG[3] -> HPO_DP[3]
1295          */
1296         apg_inst = hpo_dp_inst;
1297
1298         /* allocate HPO stream encoder and create VPG sub-block */
1299         hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL);
1300         vpg = dcn31_vpg_create(ctx, vpg_inst);
1301         apg = dcn31_apg_create(ctx, apg_inst);
1302
1303         if (!hpo_dp_enc31 || !vpg || !apg) {
1304                 kfree(hpo_dp_enc31);
1305                 kfree(vpg);
1306                 kfree(apg);
1307                 return NULL;
1308         }
1309
1310 #undef REG_STRUCT
1311 #define REG_STRUCT hpo_dp_stream_enc_regs
1312         hpo_dp_stream_encoder_reg_init(0),
1313         hpo_dp_stream_encoder_reg_init(1),
1314         hpo_dp_stream_encoder_reg_init(2),
1315         hpo_dp_stream_encoder_reg_init(3);
1316
1317         dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1318                                         hpo_dp_inst, eng_id, vpg, apg,
1319                                         &hpo_dp_stream_enc_regs[hpo_dp_inst],
1320                                         &hpo_dp_se_shift, &hpo_dp_se_mask);
1321
1322         return &hpo_dp_enc31->base;
1323 }
1324
1325 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create(
1326         uint8_t inst,
1327         struct dc_context *ctx)
1328 {
1329         struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1330
1331         /* allocate HPO link encoder */
1332         hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);
1333
1334 #undef REG_STRUCT
1335 #define REG_STRUCT hpo_dp_link_enc_regs
1336         hpo_dp_link_encoder_reg_init(0),
1337         hpo_dp_link_encoder_reg_init(1);
1338
1339         hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,
1340                                         &hpo_dp_link_enc_regs[inst],
1341                                         &hpo_dp_le_shift, &hpo_dp_le_mask);
1342
1343         return &hpo_dp_enc31->base;
1344 }
1345
1346 static struct dce_hwseq *dcn35_hwseq_create(
1347         struct dc_context *ctx)
1348 {
1349         struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1350
1351 #undef REG_STRUCT
1352 #define REG_STRUCT hwseq_reg
1353         hwseq_reg_init();
1354
1355         if (hws) {
1356                 hws->ctx = ctx;
1357                 hws->regs = &hwseq_reg;
1358                 hws->shifts = &hwseq_shift;
1359                 hws->masks = &hwseq_mask;
1360         }
1361         return hws;
1362 }
1363 static const struct resource_create_funcs res_create_funcs = {
1364         .read_dce_straps = read_dce_straps,
1365         .create_audio = dcn31_create_audio,
1366         .create_stream_encoder = dcn35_stream_encoder_create,
1367         .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,
1368         .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,
1369         .create_hwseq = dcn35_hwseq_create,
1370 };
1371
1372 static void dcn35_resource_destruct(struct dcn35_resource_pool *pool)
1373 {
1374         unsigned int i;
1375
1376         for (i = 0; i < pool->base.stream_enc_count; i++) {
1377                 if (pool->base.stream_enc[i] != NULL) {
1378                         if (pool->base.stream_enc[i]->vpg != NULL) {
1379                                 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1380                                 pool->base.stream_enc[i]->vpg = NULL;
1381                         }
1382                         if (pool->base.stream_enc[i]->afmt != NULL) {
1383                                 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1384                                 pool->base.stream_enc[i]->afmt = NULL;
1385                         }
1386                         kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1387                         pool->base.stream_enc[i] = NULL;
1388                 }
1389         }
1390
1391         for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1392                 if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1393                         if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1394                                 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1395                                 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1396                         }
1397                         if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1398                                 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1399                                 pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1400                         }
1401                         kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1402                         pool->base.hpo_dp_stream_enc[i] = NULL;
1403                 }
1404         }
1405
1406         for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1407                 if (pool->base.hpo_dp_link_enc[i] != NULL) {
1408                         kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1409                         pool->base.hpo_dp_link_enc[i] = NULL;
1410                 }
1411         }
1412
1413         for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1414                 if (pool->base.dscs[i] != NULL)
1415                         dcn20_dsc_destroy(&pool->base.dscs[i]);
1416         }
1417
1418         if (pool->base.mpc != NULL) {
1419                 kfree(TO_DCN20_MPC(pool->base.mpc));
1420                 pool->base.mpc = NULL;
1421         }
1422         if (pool->base.hubbub != NULL) {
1423                 kfree(pool->base.hubbub);
1424                 pool->base.hubbub = NULL;
1425         }
1426         for (i = 0; i < pool->base.pipe_count; i++) {
1427                 if (pool->base.dpps[i] != NULL)
1428                         dcn35_dpp_destroy(&pool->base.dpps[i]);
1429
1430                 if (pool->base.ipps[i] != NULL)
1431                         pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1432
1433                 if (pool->base.hubps[i] != NULL) {
1434                         kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1435                         pool->base.hubps[i] = NULL;
1436                 }
1437
1438                 if (pool->base.irqs != NULL) {
1439                         dal_irq_service_destroy(&pool->base.irqs);
1440                 }
1441         }
1442
1443         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1444                 if (pool->base.engines[i] != NULL)
1445                         dce110_engine_destroy(&pool->base.engines[i]);
1446                 if (pool->base.hw_i2cs[i] != NULL) {
1447                         kfree(pool->base.hw_i2cs[i]);
1448                         pool->base.hw_i2cs[i] = NULL;
1449                 }
1450                 if (pool->base.sw_i2cs[i] != NULL) {
1451                         kfree(pool->base.sw_i2cs[i]);
1452                         pool->base.sw_i2cs[i] = NULL;
1453                 }
1454         }
1455
1456         for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1457                 if (pool->base.opps[i] != NULL)
1458                         pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1459         }
1460
1461         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1462                 if (pool->base.timing_generators[i] != NULL)    {
1463                         kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1464                         pool->base.timing_generators[i] = NULL;
1465                 }
1466         }
1467
1468         for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1469                 if (pool->base.dwbc[i] != NULL) {
1470                         kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1471                         pool->base.dwbc[i] = NULL;
1472                 }
1473                 if (pool->base.mcif_wb[i] != NULL) {
1474                         kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1475                         pool->base.mcif_wb[i] = NULL;
1476                 }
1477         }
1478
1479         for (i = 0; i < pool->base.audio_count; i++) {
1480                 if (pool->base.audios[i])
1481                         dce_aud_destroy(&pool->base.audios[i]);
1482         }
1483
1484         for (i = 0; i < pool->base.clk_src_count; i++) {
1485                 if (pool->base.clock_sources[i] != NULL) {
1486                         dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1487                         pool->base.clock_sources[i] = NULL;
1488                 }
1489         }
1490
1491         for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1492                 if (pool->base.mpc_lut[i] != NULL) {
1493                         dc_3dlut_func_release(pool->base.mpc_lut[i]);
1494                         pool->base.mpc_lut[i] = NULL;
1495                 }
1496                 if (pool->base.mpc_shaper[i] != NULL) {
1497                         dc_transfer_func_release(pool->base.mpc_shaper[i]);
1498                         pool->base.mpc_shaper[i] = NULL;
1499                 }
1500         }
1501
1502         if (pool->base.dp_clock_source != NULL) {
1503                 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1504                 pool->base.dp_clock_source = NULL;
1505         }
1506
1507         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1508                 if (pool->base.multiple_abms[i] != NULL)
1509                         dce_abm_destroy(&pool->base.multiple_abms[i]);
1510         }
1511
1512         if (pool->base.psr != NULL)
1513                 dmub_psr_destroy(&pool->base.psr);
1514
1515         if (pool->base.pg_cntl != NULL)
1516                 dcn_pg_cntl_destroy(&pool->base.pg_cntl);
1517
1518         if (pool->base.dccg != NULL)
1519                 dcn_dccg_destroy(&pool->base.dccg);
1520 }
1521
1522 static struct hubp *dcn35_hubp_create(
1523         struct dc_context *ctx,
1524         uint32_t inst)
1525 {
1526         struct dcn20_hubp *hubp2 =
1527                 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1528
1529         if (!hubp2)
1530                 return NULL;
1531
1532 #undef REG_STRUCT
1533 #define REG_STRUCT hubp_regs
1534         hubp_regs_init(0),
1535         hubp_regs_init(1),
1536         hubp_regs_init(2),
1537         hubp_regs_init(3);
1538
1539         if (hubp35_construct(hubp2, ctx, inst,
1540                         &hubp_regs[inst], &hubp_shift, &hubp_mask))
1541                 return &hubp2->base;
1542
1543         BREAK_TO_DEBUGGER();
1544         kfree(hubp2);
1545         return NULL;
1546 }
1547
1548 static void dcn35_dwbc_init(struct dcn30_dwbc *dwbc30, struct dc_context *ctx)
1549 {
1550         dcn35_dwbc_set_fgcg(
1551                 dwbc30, ctx->dc->debug.enable_fine_grain_clock_gating.bits.dwb);
1552 }
1553
1554 static bool dcn35_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1555 {
1556         int i;
1557         uint32_t pipe_count = pool->res_cap->num_dwb;
1558
1559         for (i = 0; i < pipe_count; i++) {
1560                 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1561                                                     GFP_KERNEL);
1562
1563                 if (!dwbc30) {
1564                         dm_error("DC: failed to create dwbc30!\n");
1565                         return false;
1566                 }
1567
1568 #undef REG_STRUCT
1569 #define REG_STRUCT dwbc35_regs
1570                 dwbc_regs_dcn3_init(0);
1571
1572                 dcn35_dwbc_construct(dwbc30, ctx,
1573                                 &dwbc35_regs[i],
1574                                 &dwbc35_shift,
1575                                 &dwbc35_mask,
1576                                 i);
1577
1578                 pool->dwbc[i] = &dwbc30->base;
1579
1580                 dcn35_dwbc_init(dwbc30, ctx);
1581         }
1582         return true;
1583 }
1584
1585 static void dcn35_mmhubbub_init(struct dcn30_mmhubbub *mcif_wb30,
1586                                 struct dc_context *ctx)
1587 {
1588         dcn35_mmhubbub_set_fgcg(
1589                 mcif_wb30,
1590                 ctx->dc->debug.enable_fine_grain_clock_gating.bits.mmhubbub);
1591 }
1592
1593 static bool dcn35_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1594 {
1595         int i;
1596         uint32_t pipe_count = pool->res_cap->num_dwb;
1597
1598         for (i = 0; i < pipe_count; i++) {
1599                 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1600                                                     GFP_KERNEL);
1601
1602                 if (!mcif_wb30) {
1603                         dm_error("DC: failed to create mcif_wb30!\n");
1604                         return false;
1605                 }
1606
1607 #undef REG_STRUCT
1608 #define REG_STRUCT mcif_wb35_regs
1609                 mcif_wb_regs_dcn3_init(0);
1610
1611                 dcn35_mmhubbub_construct(mcif_wb30, ctx,
1612                                 &mcif_wb35_regs[i],
1613                                 &mcif_wb35_shift,
1614                                 &mcif_wb35_mask,
1615                                 i);
1616
1617                 dcn35_mmhubbub_init(mcif_wb30, ctx);
1618
1619                 pool->mcif_wb[i] = &mcif_wb30->base;
1620         }
1621         return true;
1622 }
1623
1624 static struct display_stream_compressor *dcn35_dsc_create(
1625         struct dc_context *ctx, uint32_t inst)
1626 {
1627         struct dcn20_dsc *dsc =
1628                 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1629
1630         if (!dsc) {
1631                 BREAK_TO_DEBUGGER();
1632                 return NULL;
1633         }
1634
1635 #undef REG_STRUCT
1636 #define REG_STRUCT dsc_regs
1637         dsc_regsDCN35_init(0),
1638         dsc_regsDCN35_init(1),
1639         dsc_regsDCN35_init(2),
1640         dsc_regsDCN35_init(3);
1641
1642         dsc35_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1643         dsc35_set_fgcg(dsc,
1644                        ctx->dc->debug.enable_fine_grain_clock_gating.bits.dsc);
1645         return &dsc->base;
1646 }
1647
1648 static void dcn35_destroy_resource_pool(struct resource_pool **pool)
1649 {
1650         struct dcn35_resource_pool *dcn35_pool = TO_DCN35_RES_POOL(*pool);
1651
1652         dcn35_resource_destruct(dcn35_pool);
1653         kfree(dcn35_pool);
1654         *pool = NULL;
1655 }
1656
1657 static struct clock_source *dcn35_clock_source_create(
1658                 struct dc_context *ctx,
1659                 struct dc_bios *bios,
1660                 enum clock_source_id id,
1661                 const struct dce110_clk_src_regs *regs,
1662                 bool dp_clk_src)
1663 {
1664         struct dce110_clk_src *clk_src =
1665                 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1666
1667         if (!clk_src)
1668                 return NULL;
1669
1670         if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
1671                         regs, &cs_shift, &cs_mask)) {
1672                 clk_src->base.dp_clk_src = dp_clk_src;
1673                 return &clk_src->base;
1674         }
1675
1676         BREAK_TO_DEBUGGER();
1677         return NULL;
1678 }
1679
1680 static struct dc_cap_funcs cap_funcs = {
1681         .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1682 };
1683
1684 static void dcn35_get_panel_config_defaults(struct dc_panel_config *panel_config)
1685 {
1686         *panel_config = panel_config_defaults;
1687 }
1688
1689
1690 static bool dcn35_validate_bandwidth(struct dc *dc,
1691                 struct dc_state *context,
1692                 bool fast_validate)
1693 {
1694         bool out = false;
1695
1696         out = dml2_validate(dc, context, fast_validate);
1697
1698         return out;
1699 }
1700
1701
1702 static struct resource_funcs dcn35_res_pool_funcs = {
1703         .destroy = dcn35_destroy_resource_pool,
1704         .link_enc_create = dcn35_link_encoder_create,
1705         .link_enc_create_minimal = dcn31_link_enc_create_minimal,
1706         .link_encs_assign = link_enc_cfg_link_encs_assign,
1707         .link_enc_unassign = link_enc_cfg_link_enc_unassign,
1708         .panel_cntl_create = dcn31_panel_cntl_create,
1709         .validate_bandwidth = dcn35_validate_bandwidth,
1710         .calculate_wm_and_dlg = NULL,
1711         .update_soc_for_wm_a = dcn31_update_soc_for_wm_a,
1712         .populate_dml_pipes = dcn35_populate_dml_pipes_from_context_fpu,
1713         .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
1714         .release_pipe = dcn20_release_pipe,
1715         .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1716         .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1717         .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1718         .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1719         .set_mcif_arb_params = dcn30_set_mcif_arb_params,
1720         .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1721         .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1722         .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1723         .update_bw_bounding_box = dcn35_update_bw_bounding_box_fpu,
1724         .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1725         .get_panel_config_defaults = dcn35_get_panel_config_defaults,
1726         .get_preferred_eng_id_dpia = dcn35_get_preferred_eng_id_dpia,
1727 };
1728
1729 static bool dcn35_resource_construct(
1730         uint8_t num_virtual_links,
1731         struct dc *dc,
1732         struct dcn35_resource_pool *pool)
1733 {
1734         int i;
1735         struct dc_context *ctx = dc->ctx;
1736         struct irq_service_init_data init_data;
1737
1738 #undef REG_STRUCT
1739 #define REG_STRUCT bios_regs
1740         bios_regs_init();
1741
1742 #undef REG_STRUCT
1743 #define REG_STRUCT clk_src_regs
1744         clk_src_regs_init(0, A),
1745         clk_src_regs_init(1, B),
1746         clk_src_regs_init(2, C),
1747         clk_src_regs_init(3, D),
1748         clk_src_regs_init(4, E);
1749
1750 #undef REG_STRUCT
1751 #define REG_STRUCT abm_regs
1752         abm_regs_init(0),
1753         abm_regs_init(1),
1754         abm_regs_init(2),
1755         abm_regs_init(3);
1756
1757 #undef REG_STRUCT
1758 #define REG_STRUCT dccg_regs
1759         dccg_regs_init();
1760
1761         ctx->dc_bios->regs = &bios_regs;
1762
1763         pool->base.res_cap = &res_cap_dcn35;
1764
1765         pool->base.funcs = &dcn35_res_pool_funcs;
1766
1767         /*************************************************
1768          *  Resource + asic cap harcoding                *
1769          *************************************************/
1770         pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1771         pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1772         pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
1773         dc->caps.max_downscale_ratio = 600;
1774         dc->caps.i2c_speed_in_khz = 100;
1775         dc->caps.i2c_speed_in_khz_hdcp = 100;
1776         dc->caps.max_cursor_size = 256;
1777         dc->caps.min_horizontal_blanking_period = 80;
1778         dc->caps.dmdata_alloc_size = 2048;
1779         dc->caps.max_slave_planes = 2;
1780         dc->caps.max_slave_yuv_planes = 2;
1781         dc->caps.max_slave_rgb_planes = 2;
1782         dc->caps.post_blend_color_processing = true;
1783         dc->caps.force_dp_tps4_for_cp2520 = true;
1784         if (dc->config.forceHBR2CP2520)
1785                 dc->caps.force_dp_tps4_for_cp2520 = false;
1786         dc->caps.dp_hpo = true;
1787         dc->caps.dp_hdmi21_pcon_support = true;
1788
1789         dc->caps.edp_dsc_support = true;
1790         dc->caps.extended_aux_timeout_support = true;
1791         dc->caps.dmcub_support = true;
1792         dc->caps.is_apu = true;
1793         dc->caps.seamless_odm = true;
1794
1795         dc->caps.zstate_support = true;
1796         dc->caps.ips_support = true;
1797         dc->caps.max_v_total = (1 << 15) - 1;
1798
1799         /* Color pipeline capabilities */
1800         dc->caps.color.dpp.dcn_arch = 1;
1801         dc->caps.color.dpp.input_lut_shared = 0;
1802         dc->caps.color.dpp.icsc = 1;
1803         dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1804         dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1805         dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1806         dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1807         dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1808         dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1809         dc->caps.color.dpp.post_csc = 1;
1810         dc->caps.color.dpp.gamma_corr = 1;
1811         dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1812
1813         dc->caps.color.dpp.hw_3d_lut = 1;
1814         dc->caps.color.dpp.ogam_ram = 0;  // no OGAM in DPP since DCN1
1815         // no OGAM ROM on DCN301
1816         dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1817         dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1818         dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1819         dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1820         dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1821         dc->caps.color.dpp.ocsc = 0;
1822
1823         dc->caps.color.mpc.gamut_remap = 1;
1824         dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
1825         dc->caps.color.mpc.ogam_ram = 1;
1826         dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1827         dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1828         dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1829         dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1830         dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1831         dc->caps.color.mpc.ocsc = 1;
1832
1833         dc->caps.max_disp_clock_khz_at_vmin = 669154;
1834
1835         /* Use pipe context based otg sync logic */
1836         dc->config.use_pipe_ctx_sync_logic = true;
1837         dc->config.use_default_clock_table = true;
1838         /* read VBIOS LTTPR caps */
1839         {
1840                 if (ctx->dc_bios->funcs->get_lttpr_caps) {
1841                         enum bp_result bp_query_result;
1842                         uint8_t is_vbios_lttpr_enable = 0;
1843
1844                         bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1845                         dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1846                 }
1847
1848                 /* interop bit is implicit */
1849                 {
1850                         dc->caps.vbios_lttpr_aware = true;
1851                 }
1852         }
1853
1854         if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1855                 dc->debug = debug_defaults_drv;
1856
1857         // Init the vm_helper
1858         if (dc->vm_helper)
1859                 vm_helper_init(dc->vm_helper, 16);
1860
1861         /*************************************************
1862          *  Create resources                             *
1863          *************************************************/
1864
1865         /* Clock Sources for Pixel Clock*/
1866         pool->base.clock_sources[DCN35_CLK_SRC_PLL0] =
1867                         dcn35_clock_source_create(ctx, ctx->dc_bios,
1868                                 CLOCK_SOURCE_COMBO_PHY_PLL0,
1869                                 &clk_src_regs[0], false);
1870         pool->base.clock_sources[DCN35_CLK_SRC_PLL1] =
1871                         dcn35_clock_source_create(ctx, ctx->dc_bios,
1872                                 CLOCK_SOURCE_COMBO_PHY_PLL1,
1873                                 &clk_src_regs[1], false);
1874         pool->base.clock_sources[DCN35_CLK_SRC_PLL2] =
1875                         dcn35_clock_source_create(ctx, ctx->dc_bios,
1876                                 CLOCK_SOURCE_COMBO_PHY_PLL2,
1877                                 &clk_src_regs[2], false);
1878         pool->base.clock_sources[DCN35_CLK_SRC_PLL3] =
1879                         dcn35_clock_source_create(ctx, ctx->dc_bios,
1880                                 CLOCK_SOURCE_COMBO_PHY_PLL3,
1881                                 &clk_src_regs[3], false);
1882         pool->base.clock_sources[DCN35_CLK_SRC_PLL4] =
1883                         dcn35_clock_source_create(ctx, ctx->dc_bios,
1884                                 CLOCK_SOURCE_COMBO_PHY_PLL4,
1885                                 &clk_src_regs[4], false);
1886
1887         pool->base.clk_src_count = DCN35_CLK_SRC_TOTAL;
1888
1889         /* todo: not reuse phy_pll registers */
1890         pool->base.dp_clock_source =
1891                         dcn35_clock_source_create(ctx, ctx->dc_bios,
1892                                 CLOCK_SOURCE_ID_DP_DTO,
1893                                 &clk_src_regs[0], true);
1894
1895         for (i = 0; i < pool->base.clk_src_count; i++) {
1896                 if (pool->base.clock_sources[i] == NULL) {
1897                         dm_error("DC: failed to create clock sources!\n");
1898                         BREAK_TO_DEBUGGER();
1899                         goto create_fail;
1900                 }
1901         }
1902         /*temp till dml2 fully work without dml1*/
1903         dml_init_instance(&dc->dml, &dcn3_5_soc, &dcn3_5_ip, DML_PROJECT_DCN31);
1904
1905         /* TODO: DCCG */
1906         pool->base.dccg = dccg35_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1907         if (pool->base.dccg == NULL) {
1908                 dm_error("DC: failed to create dccg!\n");
1909                 BREAK_TO_DEBUGGER();
1910                 goto create_fail;
1911         }
1912
1913 #undef REG_STRUCT
1914 #define REG_STRUCT pg_cntl_regs
1915         pg_cntl_dcn35_regs_init();
1916
1917         pool->base.pg_cntl = pg_cntl35_create(ctx, &pg_cntl_regs, &pg_cntl_shift, &pg_cntl_mask);
1918         if (pool->base.pg_cntl == NULL) {
1919                 dm_error("DC: failed to create power gate control!\n");
1920                 BREAK_TO_DEBUGGER();
1921                 goto create_fail;
1922         }
1923
1924         /* TODO: IRQ */
1925         init_data.ctx = dc->ctx;
1926         pool->base.irqs = dal_irq_service_dcn35_create(&init_data);
1927         if (!pool->base.irqs)
1928                 goto create_fail;
1929
1930         /* HUBBUB */
1931         pool->base.hubbub = dcn35_hubbub_create(ctx);
1932         if (pool->base.hubbub == NULL) {
1933                 BREAK_TO_DEBUGGER();
1934                 dm_error("DC: failed to create hubbub!\n");
1935                 goto create_fail;
1936         }
1937
1938         /* HUBPs, DPPs, OPPs and TGs */
1939         for (i = 0; i < pool->base.pipe_count; i++) {
1940                 pool->base.hubps[i] = dcn35_hubp_create(ctx, i);
1941                 if (pool->base.hubps[i] == NULL) {
1942                         BREAK_TO_DEBUGGER();
1943                         dm_error(
1944                                 "DC: failed to create hubps!\n");
1945                         goto create_fail;
1946                 }
1947
1948                 pool->base.dpps[i] = dcn35_dpp_create(ctx, i);
1949                 if (pool->base.dpps[i] == NULL) {
1950                         BREAK_TO_DEBUGGER();
1951                         dm_error(
1952                                 "DC: failed to create dpps!\n");
1953                         goto create_fail;
1954                 }
1955         }
1956
1957         for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1958                 pool->base.opps[i] = dcn35_opp_create(ctx, i);
1959                 if (pool->base.opps[i] == NULL) {
1960                         BREAK_TO_DEBUGGER();
1961                         dm_error(
1962                                 "DC: failed to create output pixel processor!\n");
1963                         goto create_fail;
1964                 }
1965         }
1966
1967         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1968                 pool->base.timing_generators[i] = dcn35_timing_generator_create(
1969                                 ctx, i);
1970                 if (pool->base.timing_generators[i] == NULL) {
1971                         BREAK_TO_DEBUGGER();
1972                         dm_error("DC: failed to create tg!\n");
1973                         goto create_fail;
1974                 }
1975         }
1976         pool->base.timing_generator_count = i;
1977
1978         /* PSR */
1979         pool->base.psr = dmub_psr_create(ctx);
1980         if (pool->base.psr == NULL) {
1981                 dm_error("DC: failed to create psr obj!\n");
1982                 BREAK_TO_DEBUGGER();
1983                 goto create_fail;
1984         }
1985
1986         /* ABM */
1987         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1988                 pool->base.multiple_abms[i] = dmub_abm_create(ctx,
1989                                 &abm_regs[i],
1990                                 &abm_shift,
1991                                 &abm_mask);
1992                 if (pool->base.multiple_abms[i] == NULL) {
1993                         dm_error("DC: failed to create abm for pipe %d!\n", i);
1994                         BREAK_TO_DEBUGGER();
1995                         goto create_fail;
1996                 }
1997         }
1998
1999         /* MPC and DSC */
2000         pool->base.mpc = dcn35_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
2001         if (pool->base.mpc == NULL) {
2002                 BREAK_TO_DEBUGGER();
2003                 dm_error("DC: failed to create mpc!\n");
2004                 goto create_fail;
2005         }
2006
2007         for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2008                 pool->base.dscs[i] = dcn35_dsc_create(ctx, i);
2009                 if (pool->base.dscs[i] == NULL) {
2010                         BREAK_TO_DEBUGGER();
2011                         dm_error("DC: failed to create display stream compressor %d!\n", i);
2012                         goto create_fail;
2013                 }
2014         }
2015
2016         /* DWB and MMHUBBUB */
2017         if (!dcn35_dwbc_create(ctx, &pool->base)) {
2018                 BREAK_TO_DEBUGGER();
2019                 dm_error("DC: failed to create dwbc!\n");
2020                 goto create_fail;
2021         }
2022
2023         if (!dcn35_mmhubbub_create(ctx, &pool->base)) {
2024                 BREAK_TO_DEBUGGER();
2025                 dm_error("DC: failed to create mcif_wb!\n");
2026                 goto create_fail;
2027         }
2028
2029         /* AUX and I2C */
2030         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2031                 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i);
2032                 if (pool->base.engines[i] == NULL) {
2033                         BREAK_TO_DEBUGGER();
2034                         dm_error(
2035                                 "DC:failed to create aux engine!!\n");
2036                         goto create_fail;
2037                 }
2038                 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);
2039                 if (pool->base.hw_i2cs[i] == NULL) {
2040                         BREAK_TO_DEBUGGER();
2041                         dm_error(
2042                                 "DC:failed to create hw i2c!!\n");
2043                         goto create_fail;
2044                 }
2045                 pool->base.sw_i2cs[i] = NULL;
2046         }
2047
2048         /* DCN3.5 has 6 DPIA */
2049         pool->base.usb4_dpia_count = 4;
2050         if (dc->debug.dpia_debug.bits.disable_dpia)
2051                 pool->base.usb4_dpia_count = 0;
2052
2053         /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2054         if (!resource_construct(num_virtual_links, dc, &pool->base,
2055                         &res_create_funcs))
2056                 goto create_fail;
2057
2058         /* HW Sequencer and Plane caps */
2059         dcn35_hw_sequencer_construct(dc);
2060
2061         dc->caps.max_planes =  pool->base.pipe_count;
2062
2063         for (i = 0; i < dc->caps.max_planes; ++i)
2064                 dc->caps.planes[i] = plane_cap;
2065
2066         dc->cap_funcs = cap_funcs;
2067
2068         dc->dcn_ip->max_num_dpp = pool->base.pipe_count;
2069
2070         dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;
2071         dc->dml2_options.use_native_pstate_optimization = true;
2072         dc->dml2_options.use_native_soc_bb_construction = true;
2073         if (dc->config.EnableMinDispClkODM)
2074                 dc->dml2_options.minimize_dispclk_using_odm = true;
2075         dc->dml2_options.enable_windowed_mpo_odm = dc->config.enable_windowed_mpo_odm;
2076
2077         dc->dml2_options.callbacks.dc = dc;
2078         dc->dml2_options.callbacks.build_scaling_params = &resource_build_scaling_params;
2079         dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;
2080         dc->dml2_options.callbacks.acquire_secondary_pipe_for_mpc_odm = &dc_resource_acquire_secondary_pipe_for_mpc_odm_legacy;
2081         dc->dml2_options.max_segments_per_hubp = 24;
2082
2083         dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;/*todo*/
2084
2085         if (dc->config.sdpif_request_limit_words_per_umc == 0)
2086                 dc->config.sdpif_request_limit_words_per_umc = 16;/*todo*/
2087
2088         return true;
2089
2090 create_fail:
2091
2092         dcn35_resource_destruct(pool);
2093
2094         return false;
2095 }
2096
2097 struct resource_pool *dcn35_create_resource_pool(
2098                 const struct dc_init_data *init_data,
2099                 struct dc *dc)
2100 {
2101         struct dcn35_resource_pool *pool =
2102                 kzalloc(sizeof(struct dcn35_resource_pool), GFP_KERNEL);
2103
2104         if (!pool)
2105                 return NULL;
2106
2107         if (dcn35_resource_construct(init_data->num_virtual_links, dc, pool))
2108                 return &pool->base;
2109
2110         BREAK_TO_DEBUGGER();
2111         kfree(pool);
2112         return NULL;
2113 }