1 /* SPDX-License-Identifier: MIT */
3 * Copyright 2023 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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25 #ifndef __DC_HWSS_DCN35_H__
26 #define __DC_HWSS_DCN35_H__
28 #include "hw_sequencer_private.h"
32 void dcn35_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);
34 void dcn35_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on);
36 void dcn35_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool clock_on);
38 void dcn35_enable_power_gating_plane(struct dce_hwseq *hws, bool enable);
40 void dcn35_set_dmu_fgcg(struct dce_hwseq *hws, bool enable);
42 void dcn35_init_hw(struct dc *dc);
44 void dcn35_disable_link_output(struct dc_link *link,
45 const struct link_resource *link_res,
46 enum signal_type signal);
48 void dcn35_power_down_on_boot(struct dc *dc);
50 bool dcn35_apply_idle_power_optimizations(struct dc *dc, bool enable);
52 void dcn35_z10_restore(const struct dc *dc);
54 void dcn35_init_pipes(struct dc *dc, struct dc_state *context);
55 void dcn35_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx);
56 void dcn35_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx,
57 struct dc_state *context);
58 void dcn35_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx);
60 void dcn35_calc_blocks_to_gate(struct dc *dc, struct dc_state *context,
61 struct pg_block_update *update_state);
62 void dcn35_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context,
63 struct pg_block_update *update_state);
64 void dcn35_block_power_control(struct dc *dc,
65 struct pg_block_update *update_state, bool power_on);
66 void dcn35_root_clock_control(struct dc *dc,
67 struct pg_block_update *update_state, bool power_on);
69 void dcn35_prepare_bandwidth(
71 struct dc_state *context);
73 void dcn35_optimize_bandwidth(
75 struct dc_state *context);
77 void dcn35_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable);
78 void dcn35_dsc_pg_control(
79 struct dce_hwseq *hws,
80 unsigned int dsc_inst,
83 void dcn35_set_idle_state(const struct dc *dc, bool allow_idle);
84 uint32_t dcn35_get_idle_state(const struct dc *dc);
85 #endif /* __DC_HWSS_DCN35_H__ */