drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright 2022 Advanced Micro Devices, Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: AMD
  24  *
  25  */
  26
  27 #include "dm_services.h"
  28 #include "dc.h"
  29
  30 #include "dcn32_init.h"
  31
  32 #include "resource.h"
  33 #include "include/irq_service_interface.h"
  34 #include "dcn32_resource.h"
  35
  36 #include "dcn20/dcn20_resource.h"
  37 #include "dcn30/dcn30_resource.h"
  38
  39 #include "dcn10/dcn10_ipp.h"
  40 #include "dcn30/dcn30_hubbub.h"
  41 #include "dcn31/dcn31_hubbub.h"
  42 #include "dcn32/dcn32_hubbub.h"
  43 #include "dcn32/dcn32_mpc.h"
  44 #include "dcn32_hubp.h"
  45 #include "irq/dcn32/irq_service_dcn32.h"
  46 #include "dcn32/dcn32_dpp.h"
  47 #include "dcn32/dcn32_optc.h"
  48 #include "dcn20/dcn20_hwseq.h"
  49 #include "dcn30/dcn30_hwseq.h"
  50 #include "dce110/dce110_hw_sequencer.h"
  51 #include "dcn30/dcn30_opp.h"
  52 #include "dcn20/dcn20_dsc.h"
  53 #include "dcn30/dcn30_vpg.h"
  54 #include "dcn30/dcn30_afmt.h"
  55 #include "dcn30/dcn30_dio_stream_encoder.h"
  56 #include "dcn32/dcn32_dio_stream_encoder.h"
  57 #include "dcn31/dcn31_hpo_dp_stream_encoder.h"
  58 #include "dcn31/dcn31_hpo_dp_link_encoder.h"
  59 #include "dcn32/dcn32_hpo_dp_link_encoder.h"
  60 #include "dc_link_dp.h"
  61 #include "dcn31/dcn31_apg.h"
  62 #include "dcn31/dcn31_dio_link_encoder.h"
  63 #include "dcn32/dcn32_dio_link_encoder.h"
  64 #include "dce/dce_clock_source.h"
  65 #include "dce/dce_audio.h"
  66 #include "dce/dce_hwseq.h"
  67 #include "clk_mgr.h"
  68 #include "virtual/virtual_stream_encoder.h"
  69 #include "dml/display_mode_vba.h"
  70 #include "dcn32/dcn32_dccg.h"
  71 #include "dcn10/dcn10_resource.h"
  72 #include "dc_link_ddc.h"
  73 #include "dcn31/dcn31_panel_cntl.h"
  74
  75 #include "dcn30/dcn30_dwb.h"
  76 #include "dcn32/dcn32_mmhubbub.h"
  77
  78 #include "dcn/dcn_3_2_0_offset.h"
  79 #include "dcn/dcn_3_2_0_sh_mask.h"
  80 #include "nbio/nbio_4_3_0_offset.h"
  81
  82 #include "reg_helper.h"
  83 #include "dce/dmub_abm.h"
  84 #include "dce/dmub_psr.h"
  85 #include "dce/dce_aux.h"
  86 #include "dce/dce_i2c.h"
  87
  88 #include "dml/dcn30/display_mode_vba_30.h"
  89 #include "vm_helper.h"
  90 #include "dcn20/dcn20_vmid.h"
  91
  92 #define DCN_BASE__INST0_SEG1                       0x000000C0
  93 #define DCN_BASE__INST0_SEG2                       0x000034C0
  94 #define DCN_BASE__INST0_SEG3                       0x00009000
  95 #define NBIO_BASE__INST0_SEG1                      0x00000014
  96
  97 #define MAX_INSTANCE                                        6
  98 #define MAX_SEGMENT                                         6
  99
 100 struct IP_BASE_INSTANCE {
 101         unsigned int segment[MAX_SEGMENT];
 102 };
 103
 104 struct IP_BASE {
 105         struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
 106 };
 107
 108 static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } },
 109                                         { { 0, 0, 0, 0, 0, 0 } },
 110                                         { { 0, 0, 0, 0, 0, 0 } },
 111                                         { { 0, 0, 0, 0, 0, 0 } },
 112                                         { { 0, 0, 0, 0, 0, 0 } },
 113                                         { { 0, 0, 0, 0, 0, 0 } } } };
 114
 115 #define DC_LOGGER_INIT(logger)
 116
 117 #define DCN3_2_DEFAULT_DET_SIZE 256
 118 #define DCN3_2_MAX_DET_SIZE 1152
 119 #define DCN3_2_MIN_DET_SIZE 128
 120 #define DCN3_2_MIN_COMPBUF_SIZE_KB 128
 121
 122 struct _vcs_dpi_ip_params_st dcn3_2_ip = {
 123         .gpuvm_enable = 1,
 124         .gpuvm_max_page_table_levels = 1,
 125         .hostvm_enable = 0,
 126         .rob_buffer_size_kbytes = 128,
 127         .det_buffer_size_kbytes = DCN3_2_DEFAULT_DET_SIZE,
 128         .config_return_buffer_size_in_kbytes = 1280,
 129         .compressed_buffer_segment_size_in_kbytes = 64,
 130         .meta_fifo_size_in_kentries = 22,
 131         .zero_size_buffer_entries = 512,
 132         .compbuf_reserved_space_64b = 256,
 133         .compbuf_reserved_space_zs = 64,
 134         .dpp_output_buffer_pixels = 2560,
 135         .opp_output_buffer_lines = 1,
 136         .pixel_chunk_size_kbytes = 8,
 137         .alpha_pixel_chunk_size_kbytes = 4, // not appearing in spreadsheet, match c code from hw team
 138         .min_pixel_chunk_size_bytes = 1024,
 139         .dcc_meta_buffer_size_bytes = 6272,
 140         .meta_chunk_size_kbytes = 2,
 141         .min_meta_chunk_size_bytes = 256,
 142         .writeback_chunk_size_kbytes = 8,
 143         .ptoi_supported = false,
 144         .num_dsc = 4,
 145         .maximum_dsc_bits_per_component = 12,
 146         .maximum_pixels_per_line_per_dsc_unit = 6016,
 147         .dsc422_native_support = true,
 148         .is_line_buffer_bpp_fixed = true,
 149         .line_buffer_fixed_bpp = 57,
 150         .line_buffer_size_bits = 1171920, //DPP doc, DCN3_2_DisplayMode_73.xlsm still shows as 986880 bits with 48 bpp
 151         .max_line_buffer_lines = 32,
 152         .writeback_interface_buffer_size_kbytes = 90,
 153         .max_num_dpp = 4,
 154         .max_num_otg = 4,
 155         .max_num_hdmi_frl_outputs = 1,
 156         .max_num_wb = 1,
 157         .max_dchub_pscl_bw_pix_per_clk = 4,
 158         .max_pscl_lb_bw_pix_per_clk = 2,
 159         .max_lb_vscl_bw_pix_per_clk = 4,
 160         .max_vscl_hscl_bw_pix_per_clk = 4,
 161         .max_hscl_ratio = 6,
 162         .max_vscl_ratio = 6,
 163         .max_hscl_taps = 8,
 164         .max_vscl_taps = 8,
 165         .dpte_buffer_size_in_pte_reqs_luma = 64,
 166         .dpte_buffer_size_in_pte_reqs_chroma = 34,
 167         .dispclk_ramp_margin_percent = 1,
 168         .max_inter_dcn_tile_repeaters = 8,
 169         .cursor_buffer_size = 16,
 170         .cursor_chunk_size = 2,
 171         .writeback_line_buffer_buffer_size = 0,
 172         .writeback_min_hscl_ratio = 1,
 173         .writeback_min_vscl_ratio = 1,
 174         .writeback_max_hscl_ratio = 1,
 175         .writeback_max_vscl_ratio = 1,
 176         .writeback_max_hscl_taps = 1,
 177         .writeback_max_vscl_taps = 1,
 178         .dppclk_delay_subtotal = 47,
 179         .dppclk_delay_scl = 50,
 180         .dppclk_delay_scl_lb_only = 16,
 181         .dppclk_delay_cnvc_formatter = 28,
 182         .dppclk_delay_cnvc_cursor = 6,
 183         .dispclk_delay_subtotal = 125,
 184         .dynamic_metadata_vm_enabled = false,
 185         .odm_combine_4to1_supported = false,
 186         .dcc_supported = true,
 187         .max_num_dp2p0_outputs = 2,
 188         .max_num_dp2p0_streams = 4,
 189 };
 190
 191 struct _vcs_dpi_soc_bounding_box_st dcn3_2_soc = {
 192         .clock_limits = {
 193                 {
 194                         .state = 0,
 195                         .dcfclk_mhz = 1564.0,
 196                         .fabricclk_mhz = 400.0,
 197                         .dispclk_mhz = 2150.0,
 198                         .dppclk_mhz = 2150.0,
 199                         .phyclk_mhz = 810.0,
 200                         .phyclk_d18_mhz = 667.0,
 201                         .phyclk_d32_mhz = 625.0,
 202                         .socclk_mhz = 1200.0,
 203                         .dscclk_mhz = 716.667,
 204                         .dram_speed_mts = 1600.0,
 205                         .dtbclk_mhz = 1564.0,
 206                 },
 207         },
 208         .num_states = 1,
 209         .sr_exit_time_us = 5.20,
 210         .sr_enter_plus_exit_time_us = 9.60,
 211         .sr_exit_z8_time_us = 285.0,
 212         .sr_enter_plus_exit_z8_time_us = 320,
 213         .writeback_latency_us = 12.0,
 214         .round_trip_ping_latency_dcfclk_cycles = 263,
 215         .urgent_latency_pixel_data_only_us = 4.0,
 216         .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
 217         .urgent_latency_vm_data_only_us = 4.0,
 218         .fclk_change_latency_us = 20,
 219         .usr_retraining_latency_us = 2,
 220         .smn_latency_us = 2,
 221         .mall_allocated_for_dcn_mbytes = 64,
 222         .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
 223         .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
 224         .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
 225         .pct_ideal_sdp_bw_after_urgent = 100.0,
 226         .pct_ideal_fabric_bw_after_urgent = 67.0,
 227         .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 20.0,
 228         .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0, // N/A, for now keep as is until DML implemented
 229         .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0, // N/A, for now keep as is until DML implemented
 230         .pct_ideal_dram_bw_after_urgent_strobe = 67.0,
 231         .max_avg_sdp_bw_use_normal_percent = 80.0,
 232         .max_avg_fabric_bw_use_normal_percent = 60.0,
 233         .max_avg_dram_bw_use_normal_strobe_percent = 50.0,
 234         .max_avg_dram_bw_use_normal_percent = 15.0,
 235         .num_chans = 8,
 236         .dram_channel_width_bytes = 2,
 237         .fabric_datapath_to_dcn_data_return_bytes = 64,
 238         .return_bus_width_bytes = 64,
 239         .downspread_percent = 0.38,
 240         .dcn_downspread_percent = 0.5,
 241         .dram_clock_change_latency_us = 400,
 242         .dispclk_dppclk_vco_speed_mhz = 4300.0,
 243         .do_urgent_latency_adjustment = true,
 244         .urgent_latency_adjustment_fabric_clock_component_us = 1.0,
 245         .urgent_latency_adjustment_fabric_clock_reference_mhz = 1000,
 246 };
 247
 248 enum dcn32_clk_src_array_id {
 249         DCN32_CLK_SRC_PLL0,
 250         DCN32_CLK_SRC_PLL1,
 251         DCN32_CLK_SRC_PLL2,
 252         DCN32_CLK_SRC_PLL3,
 253         DCN32_CLK_SRC_PLL4,
 254         DCN32_CLK_SRC_TOTAL
 255 };
 256
 257 /* begin *********************
 258  * macros to expend register list macro defined in HW object header file
 259  */
 260
 261 /* DCN */
 262 /* TODO awful hack. fixup dcn20_dwb.h */
 263 #undef BASE_INNER
 264 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
 265
 266 #define BASE(seg) BASE_INNER(seg)
 267
 268 #define SR(reg_name)\
 269                 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) +  \
 270                                         reg ## reg_name
 271
 272 #define SRI(reg_name, block, id)\
 273         .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 274                                         reg ## block ## id ## _ ## reg_name
 275
 276 #define SRI2(reg_name, block, id)\
 277         .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
 278                                         reg ## reg_name
 279
 280 #define SRIR(var_name, reg_name, block, id)\
 281         .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 282                                         reg ## block ## id ## _ ## reg_name
 283
 284 #define SRII(reg_name, block, id)\
 285         .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 286                                         reg ## block ## id ## _ ## reg_name
 287
 288 #define SRII_MPC_RMU(reg_name, block, id)\
 289         .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 290                                         reg ## block ## id ## _ ## reg_name
 291
 292 #define SRII_DWB(reg_name, temp_name, block, id)\
 293         .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
 294                                         reg ## block ## id ## _ ## temp_name
 295
 296 #define DCCG_SRII(reg_name, block, id)\
 297         .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 298                                         reg ## block ## id ## _ ## reg_name
 299
 300 #define VUPDATE_SRII(reg_name, block, id)\
 301         .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
 302                                         reg ## reg_name ## _ ## block ## id
 303
 304 /* NBIO */
 305 #define NBIO_BASE_INNER(seg) \
 306         NBIO_BASE__INST0_SEG ## seg
 307
 308 #define NBIO_BASE(seg) \
 309         NBIO_BASE_INNER(seg)
 310
 311 #define NBIO_SR(reg_name)\
 312                 .reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
 313                                         regBIF_BX0_ ## reg_name
 314
 315 #define CTX ctx
 316 #define REG(reg_name) \
 317         (DCN_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
 318
 319 static const struct bios_registers bios_regs = {
 320                 NBIO_SR(BIOS_SCRATCH_3),
 321                 NBIO_SR(BIOS_SCRATCH_6)
 322 };
 323
 324 #define clk_src_regs(index, pllid)\
 325 [index] = {\
 326         CS_COMMON_REG_LIST_DCN3_0(index, pllid),\
 327 }
 328
 329 static const struct dce110_clk_src_regs clk_src_regs[] = {
 330         clk_src_regs(0, A),
 331         clk_src_regs(1, B),
 332         clk_src_regs(2, C),
 333         clk_src_regs(3, D),
 334         clk_src_regs(4, E)
 335 };
 336
 337 static const struct dce110_clk_src_shift cs_shift = {
 338                 CS_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT)
 339 };
 340
 341 static const struct dce110_clk_src_mask cs_mask = {
 342                 CS_COMMON_MASK_SH_LIST_DCN3_2(_MASK)
 343 };
 344
 345 #define abm_regs(id)\
 346 [id] = {\
 347                 ABM_DCN32_REG_LIST(id)\
 348 }
 349
 350 static const struct dce_abm_registers abm_regs[] = {
 351                 abm_regs(0),
 352                 abm_regs(1),
 353                 abm_regs(2),
 354                 abm_regs(3),
 355 };
 356
 357 static const struct dce_abm_shift abm_shift = {
 358                 ABM_MASK_SH_LIST_DCN32(__SHIFT)
 359 };
 360
 361 static const struct dce_abm_mask abm_mask = {
 362                 ABM_MASK_SH_LIST_DCN32(_MASK)
 363 };
 364
 365 #define audio_regs(id)\
 366 [id] = {\
 367                 AUD_COMMON_REG_LIST(id)\
 368 }
 369
 370 static const struct dce_audio_registers audio_regs[] = {
 371         audio_regs(0),
 372         audio_regs(1),
 373         audio_regs(2),
 374         audio_regs(3),
 375         audio_regs(4)
 376 };
 377
 378 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
 379                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
 380                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
 381                 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
 382
 383 static const struct dce_audio_shift audio_shift = {
 384                 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
 385 };
 386
 387 static const struct dce_audio_mask audio_mask = {
 388                 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
 389 };
 390
 391 #define vpg_regs(id)\
 392 [id] = {\
 393         VPG_DCN3_REG_LIST(id)\
 394 }
 395
 396 static const struct dcn30_vpg_registers vpg_regs[] = {
 397         vpg_regs(0),
 398         vpg_regs(1),
 399         vpg_regs(2),
 400         vpg_regs(3),
 401         vpg_regs(4),
 402         vpg_regs(5),
 403         vpg_regs(6),
 404         vpg_regs(7),
 405         vpg_regs(8),
 406         vpg_regs(9),
 407 };
 408
 409 static const struct dcn30_vpg_shift vpg_shift = {
 410         DCN3_VPG_MASK_SH_LIST(__SHIFT)
 411 };
 412
 413 static const struct dcn30_vpg_mask vpg_mask = {
 414         DCN3_VPG_MASK_SH_LIST(_MASK)
 415 };
 416
 417 #define afmt_regs(id)\
 418 [id] = {\
 419         AFMT_DCN3_REG_LIST(id)\
 420 }
 421
 422 static const struct dcn30_afmt_registers afmt_regs[] = {
 423         afmt_regs(0),
 424         afmt_regs(1),
 425         afmt_regs(2),
 426         afmt_regs(3),
 427         afmt_regs(4),
 428         afmt_regs(5)
 429 };
 430
 431 static const struct dcn30_afmt_shift afmt_shift = {
 432         DCN3_AFMT_MASK_SH_LIST(__SHIFT)
 433 };
 434
 435 static const struct dcn30_afmt_mask afmt_mask = {
 436         DCN3_AFMT_MASK_SH_LIST(_MASK)
 437 };
 438
 439 #define apg_regs(id)\
 440 [id] = {\
 441         APG_DCN31_REG_LIST(id)\
 442 }
 443
 444 static const struct dcn31_apg_registers apg_regs[] = {
 445         apg_regs(0),
 446         apg_regs(1),
 447         apg_regs(2),
 448         apg_regs(3)
 449 };
 450
 451 static const struct dcn31_apg_shift apg_shift = {
 452         DCN31_APG_MASK_SH_LIST(__SHIFT)
 453 };
 454
 455 static const struct dcn31_apg_mask apg_mask = {
 456                 DCN31_APG_MASK_SH_LIST(_MASK)
 457 };
 458
 459 #define stream_enc_regs(id)\
 460 [id] = {\
 461         SE_DCN32_REG_LIST(id)\
 462 }
 463
 464 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
 465         stream_enc_regs(0),
 466         stream_enc_regs(1),
 467         stream_enc_regs(2),
 468         stream_enc_regs(3),
 469         stream_enc_regs(4)
 470 };
 471
 472 static const struct dcn10_stream_encoder_shift se_shift = {
 473                 SE_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
 474 };
 475
 476 static const struct dcn10_stream_encoder_mask se_mask = {
 477                 SE_COMMON_MASK_SH_LIST_DCN32(_MASK)
 478 };
 479
 480
 481 #define aux_regs(id)\
 482 [id] = {\
 483         DCN2_AUX_REG_LIST(id)\
 484 }
 485
 486 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
 487                 aux_regs(0),
 488                 aux_regs(1),
 489                 aux_regs(2),
 490                 aux_regs(3),
 491                 aux_regs(4)
 492 };
 493
 494 #define hpd_regs(id)\
 495 [id] = {\
 496         HPD_REG_LIST(id)\
 497 }
 498
 499 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
 500                 hpd_regs(0),
 501                 hpd_regs(1),
 502                 hpd_regs(2),
 503                 hpd_regs(3),
 504                 hpd_regs(4)
 505 };
 506
 507 #define link_regs(id, phyid)\
 508 [id] = {\
 509         LE_DCN31_REG_LIST(id), \
 510         UNIPHY_DCN2_REG_LIST(phyid), \
 511         /*DPCS_DCN31_REG_LIST(id),*/ \
 512 }
 513
 514 static const struct dcn10_link_enc_registers link_enc_regs[] = {
 515         link_regs(0, A),
 516         link_regs(1, B),
 517         link_regs(2, C),
 518         link_regs(3, D),
 519         link_regs(4, E)
 520 };
 521
 522 static const struct dcn10_link_enc_shift le_shift = {
 523         LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \
 524         //DPCS_DCN31_MASK_SH_LIST(__SHIFT)
 525 };
 526
 527 static const struct dcn10_link_enc_mask le_mask = {
 528         LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \
 529
 530         //DPCS_DCN31_MASK_SH_LIST(_MASK)
 531 };
 532
 533 #define hpo_dp_stream_encoder_reg_list(id)\
 534 [id] = {\
 535         DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\
 536 }
 537
 538 static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = {
 539         hpo_dp_stream_encoder_reg_list(0),
 540         hpo_dp_stream_encoder_reg_list(1),
 541         hpo_dp_stream_encoder_reg_list(2),
 542         hpo_dp_stream_encoder_reg_list(3),
 543 };
 544
 545 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
 546         DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
 547 };
 548
 549 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
 550         DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
 551 };
 552
 553
 554 #define hpo_dp_link_encoder_reg_list(id)\
 555 [id] = {\
 556         DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\
 557         /*DCN3_1_RDPCSTX_REG_LIST(0),*/\
 558         /*DCN3_1_RDPCSTX_REG_LIST(1),*/\
 559         /*DCN3_1_RDPCSTX_REG_LIST(2),*/\
 560         /*DCN3_1_RDPCSTX_REG_LIST(3),*/\
 561         /*DCN3_1_RDPCSTX_REG_LIST(4)*/\
 562 }
 563
 564 static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = {
 565         hpo_dp_link_encoder_reg_list(0),
 566         hpo_dp_link_encoder_reg_list(1),
 567 };
 568
 569 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
 570         DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)
 571 };
 572
 573 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
 574         DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)
 575 };
 576
 577 #define dpp_regs(id)\
 578 [id] = {\
 579         DPP_REG_LIST_DCN30_COMMON(id),\
 580 }
 581
 582 static const struct dcn3_dpp_registers dpp_regs[] = {
 583         dpp_regs(0),
 584         dpp_regs(1),
 585         dpp_regs(2),
 586         dpp_regs(3)
 587 };
 588
 589 static const struct dcn3_dpp_shift tf_shift = {
 590                 DPP_REG_LIST_SH_MASK_DCN30_COMMON(__SHIFT)
 591 };
 592
 593 static const struct dcn3_dpp_mask tf_mask = {
 594                 DPP_REG_LIST_SH_MASK_DCN30_COMMON(_MASK)
 595 };
 596
 597
 598 #define opp_regs(id)\
 599 [id] = {\
 600         OPP_REG_LIST_DCN30(id),\
 601 }
 602
 603 static const struct dcn20_opp_registers opp_regs[] = {
 604         opp_regs(0),
 605         opp_regs(1),
 606         opp_regs(2),
 607         opp_regs(3)
 608 };
 609
 610 static const struct dcn20_opp_shift opp_shift = {
 611         OPP_MASK_SH_LIST_DCN20(__SHIFT)
 612 };
 613
 614 static const struct dcn20_opp_mask opp_mask = {
 615         OPP_MASK_SH_LIST_DCN20(_MASK)
 616 };
 617
 618 #define aux_engine_regs(id)\
 619 [id] = {\
 620         AUX_COMMON_REG_LIST0(id), \
 621         .AUXN_IMPCAL = 0, \
 622         .AUXP_IMPCAL = 0, \
 623         .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
 624 }
 625
 626 static const struct dce110_aux_registers aux_engine_regs[] = {
 627                 aux_engine_regs(0),
 628                 aux_engine_regs(1),
 629                 aux_engine_regs(2),
 630                 aux_engine_regs(3),
 631                 aux_engine_regs(4)
 632 };
 633
 634 static const struct dce110_aux_registers_shift aux_shift = {
 635         DCN_AUX_MASK_SH_LIST(__SHIFT)
 636 };
 637
 638 static const struct dce110_aux_registers_mask aux_mask = {
 639         DCN_AUX_MASK_SH_LIST(_MASK)
 640 };
 641
 642
 643 #define dwbc_regs_dcn3(id)\
 644 [id] = {\
 645         DWBC_COMMON_REG_LIST_DCN30(id),\
 646 }
 647
 648 static const struct dcn30_dwbc_registers dwbc30_regs[] = {
 649         dwbc_regs_dcn3(0),
 650 };
 651
 652 static const struct dcn30_dwbc_shift dwbc30_shift = {
 653         DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 654 };
 655
 656 static const struct dcn30_dwbc_mask dwbc30_mask = {
 657         DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
 658 };
 659
 660 #define mcif_wb_regs_dcn3(id)\
 661 [id] = {\
 662         MCIF_WB_COMMON_REG_LIST_DCN32(id),\
 663 }
 664
 665 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
 666         mcif_wb_regs_dcn3(0)
 667 };
 668
 669 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
 670         MCIF_WB_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
 671 };
 672
 673 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
 674         MCIF_WB_COMMON_MASK_SH_LIST_DCN32(_MASK)
 675 };
 676
 677 #define dsc_regsDCN20(id)\
 678 [id] = {\
 679         DSC_REG_LIST_DCN20(id)\
 680 }
 681
 682 static const struct dcn20_dsc_registers dsc_regs[] = {
 683         dsc_regsDCN20(0),
 684         dsc_regsDCN20(1),
 685         dsc_regsDCN20(2),
 686         dsc_regsDCN20(3)
 687 };
 688
 689 static const struct dcn20_dsc_shift dsc_shift = {
 690         DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
 691 };
 692
 693 static const struct dcn20_dsc_mask dsc_mask = {
 694         DSC_REG_LIST_SH_MASK_DCN20(_MASK)
 695 };
 696
 697 static const struct dcn30_mpc_registers mpc_regs = {
 698                 MPC_REG_LIST_DCN3_0(0),
 699                 MPC_REG_LIST_DCN3_0(1),
 700                 MPC_REG_LIST_DCN3_0(2),
 701                 MPC_REG_LIST_DCN3_0(3),
 702                 MPC_OUT_MUX_REG_LIST_DCN3_0(0),
 703                 MPC_OUT_MUX_REG_LIST_DCN3_0(1),
 704                 MPC_OUT_MUX_REG_LIST_DCN3_0(2),
 705                 MPC_OUT_MUX_REG_LIST_DCN3_0(3),
 706                 MPC_MCM_REG_LIST_DCN32(0),
 707                 MPC_MCM_REG_LIST_DCN32(1),
 708                 MPC_MCM_REG_LIST_DCN32(2),
 709                 MPC_MCM_REG_LIST_DCN32(3),
 710                 MPC_DWB_MUX_REG_LIST_DCN3_0(0),
 711 };
 712
 713 static const struct dcn30_mpc_shift mpc_shift = {
 714         MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
 715 };
 716
 717 static const struct dcn30_mpc_mask mpc_mask = {
 718         MPC_COMMON_MASK_SH_LIST_DCN32(_MASK)
 719 };
 720
 721 #define optc_regs(id)\
 722 [id] = {OPTC_COMMON_REG_LIST_DCN3_2(id)}
 723
 724 //#ifdef DIAGS_BUILD
 725 //static struct dcn_optc_registers optc_regs[] = {
 726 //#else
 727 static const struct dcn_optc_registers optc_regs[] = {
 728 //#endif
 729         optc_regs(0),
 730         optc_regs(1),
 731         optc_regs(2),
 732         optc_regs(3)
 733 };
 734
 735 static const struct dcn_optc_shift optc_shift = {
 736         OPTC_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT)
 737 };
 738
 739 static const struct dcn_optc_mask optc_mask = {
 740         OPTC_COMMON_MASK_SH_LIST_DCN3_2(_MASK)
 741 };
 742
 743 #define hubp_regs(id)\
 744 [id] = {\
 745         HUBP_REG_LIST_DCN32(id)\
 746 }
 747
 748 static const struct dcn_hubp2_registers hubp_regs[] = {
 749                 hubp_regs(0),
 750                 hubp_regs(1),
 751                 hubp_regs(2),
 752                 hubp_regs(3)
 753 };
 754
 755
 756 static const struct dcn_hubp2_shift hubp_shift = {
 757                 HUBP_MASK_SH_LIST_DCN32(__SHIFT)
 758 };
 759
 760 static const struct dcn_hubp2_mask hubp_mask = {
 761                 HUBP_MASK_SH_LIST_DCN32(_MASK)
 762 };
 763 static const struct dcn_hubbub_registers hubbub_reg = {
 764                 HUBBUB_REG_LIST_DCN32(0)
 765 };
 766
 767 static const struct dcn_hubbub_shift hubbub_shift = {
 768                 HUBBUB_MASK_SH_LIST_DCN32(__SHIFT)
 769 };
 770
 771 static const struct dcn_hubbub_mask hubbub_mask = {
 772                 HUBBUB_MASK_SH_LIST_DCN32(_MASK)
 773 };
 774
 775 static const struct dccg_registers dccg_regs = {
 776                 DCCG_REG_LIST_DCN32()
 777 };
 778
 779 static const struct dccg_shift dccg_shift = {
 780                 DCCG_MASK_SH_LIST_DCN32(__SHIFT)
 781 };
 782
 783 static const struct dccg_mask dccg_mask = {
 784                 DCCG_MASK_SH_LIST_DCN32(_MASK)
 785 };
 786
 787
 788 #define SRII2(reg_name_pre, reg_name_post, id)\
 789         .reg_name_pre ## _ ##  reg_name_post[id] = BASE(reg ## reg_name_pre \
 790                         ## id ## _ ## reg_name_post ## _BASE_IDX) + \
 791                         reg ## reg_name_pre ## id ## _ ## reg_name_post
 792
 793
 794 #define HWSEQ_DCN32_REG_LIST()\
 795         SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
 796         SR(DIO_MEM_PWR_CTRL), \
 797         SR(ODM_MEM_PWR_CTRL3), \
 798         SR(MMHUBBUB_MEM_PWR_CNTL), \
 799         SR(DCCG_GATE_DISABLE_CNTL), \
 800         SR(DCCG_GATE_DISABLE_CNTL2), \
 801         SR(DCFCLK_CNTL),\
 802         SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
 803         SRII(PIXEL_RATE_CNTL, OTG, 0), \
 804         SRII(PIXEL_RATE_CNTL, OTG, 1),\
 805         SRII(PIXEL_RATE_CNTL, OTG, 2),\
 806         SRII(PIXEL_RATE_CNTL, OTG, 3),\
 807         SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
 808         SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
 809         SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
 810         SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
 811         SR(MICROSECOND_TIME_BASE_DIV), \
 812         SR(MILLISECOND_TIME_BASE_DIV), \
 813         SR(DISPCLK_FREQ_CHANGE_CNTL), \
 814         SR(RBBMIF_TIMEOUT_DIS), \
 815         SR(RBBMIF_TIMEOUT_DIS_2), \
 816         SR(DCHUBBUB_CRC_CTRL), \
 817         SR(DPP_TOP0_DPP_CRC_CTRL), \
 818         SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
 819         SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
 820         SR(MPC_CRC_CTRL), \
 821         SR(MPC_CRC_RESULT_GB), \
 822         SR(MPC_CRC_RESULT_C), \
 823         SR(MPC_CRC_RESULT_AR), \
 824         SR(DOMAIN0_PG_CONFIG), \
 825         SR(DOMAIN1_PG_CONFIG), \
 826         SR(DOMAIN2_PG_CONFIG), \
 827         SR(DOMAIN3_PG_CONFIG), \
 828         SR(DOMAIN16_PG_CONFIG), \
 829         SR(DOMAIN17_PG_CONFIG), \
 830         SR(DOMAIN18_PG_CONFIG), \
 831         SR(DOMAIN19_PG_CONFIG), \
 832         SR(DOMAIN0_PG_STATUS), \
 833         SR(DOMAIN1_PG_STATUS), \
 834         SR(DOMAIN2_PG_STATUS), \
 835         SR(DOMAIN3_PG_STATUS), \
 836         SR(DOMAIN16_PG_STATUS), \
 837         SR(DOMAIN17_PG_STATUS), \
 838         SR(DOMAIN18_PG_STATUS), \
 839         SR(DOMAIN19_PG_STATUS), \
 840         SR(D1VGA_CONTROL), \
 841         SR(D2VGA_CONTROL), \
 842         SR(D3VGA_CONTROL), \
 843         SR(D4VGA_CONTROL), \
 844         SR(D5VGA_CONTROL), \
 845         SR(D6VGA_CONTROL), \
 846         SR(DC_IP_REQUEST_CNTL), \
 847         SR(AZALIA_AUDIO_DTO), \
 848         SR(AZALIA_CONTROLLER_CLOCK_GATING)
 849
 850 static const struct dce_hwseq_registers hwseq_reg = {
 851                 HWSEQ_DCN32_REG_LIST()
 852 };
 853
 854 #define HWSEQ_DCN32_MASK_SH_LIST(mask_sh)\
 855         HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
 856         HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
 857         HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 858         HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 859         HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 860         HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 861         HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 862         HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 863         HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 864         HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 865         HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 866         HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 867         HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 868         HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 869         HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 870         HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 871         HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 872         HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 873         HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 874         HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 875         HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 876         HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 877         HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 878         HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 879         HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 880         HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 881         HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
 882         HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
 883         HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
 884         HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
 885         HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
 886         HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh)
 887
 888 static const struct dce_hwseq_shift hwseq_shift = {
 889                 HWSEQ_DCN32_MASK_SH_LIST(__SHIFT)
 890 };
 891
 892 static const struct dce_hwseq_mask hwseq_mask = {
 893                 HWSEQ_DCN32_MASK_SH_LIST(_MASK)
 894 };
 895 #define vmid_regs(id)\
 896 [id] = {\
 897                 DCN20_VMID_REG_LIST(id)\
 898 }
 899
 900 static const struct dcn_vmid_registers vmid_regs[] = {
 901         vmid_regs(0),
 902         vmid_regs(1),
 903         vmid_regs(2),
 904         vmid_regs(3),
 905         vmid_regs(4),
 906         vmid_regs(5),
 907         vmid_regs(6),
 908         vmid_regs(7),
 909         vmid_regs(8),
 910         vmid_regs(9),
 911         vmid_regs(10),
 912         vmid_regs(11),
 913         vmid_regs(12),
 914         vmid_regs(13),
 915         vmid_regs(14),
 916         vmid_regs(15)
 917 };
 918
 919 static const struct dcn20_vmid_shift vmid_shifts = {
 920                 DCN20_VMID_MASK_SH_LIST(__SHIFT)
 921 };
 922
 923 static const struct dcn20_vmid_mask vmid_masks = {
 924                 DCN20_VMID_MASK_SH_LIST(_MASK)
 925 };
 926
 927 static const struct resource_caps res_cap_dcn32 = {
 928         .num_timing_generator = 4,
 929         .num_opp = 4,
 930         .num_video_plane = 4,
 931         .num_audio = 5,
 932         .num_stream_encoder = 5,
 933         .num_hpo_dp_stream_encoder = 4,
 934         .num_hpo_dp_link_encoder = 2,
 935         .num_pll = 5,
 936         .num_dwb = 1,
 937         .num_ddc = 5,
 938         .num_vmid = 16,
 939         .num_mpc_3dlut = 4,
 940         .num_dsc = 4,
 941 };
 942
 943 static const struct dc_plane_cap plane_cap = {
 944         .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
 945         .blends_with_above = true,
 946         .blends_with_below = true,
 947         .per_pixel_alpha = true,
 948
 949         .pixel_format_support = {
 950                         .argb8888 = true,
 951                         .nv12 = true,
 952                         .fp16 = true,
 953                         .p010 = true,
 954                         .ayuv = false,
 955         },
 956
 957         .max_upscale_factor = {
 958                         .argb8888 = 16000,
 959                         .nv12 = 16000,
 960                         .fp16 = 16000
 961         },
 962
 963         // 6:1 downscaling ratio: 1000/6 = 166.666
 964         .max_downscale_factor = {
 965                         .argb8888 = 167,
 966                         .nv12 = 167,
 967                         .fp16 = 167
 968         },
 969         64,
 970         64
 971 };
 972
 973 static const struct dc_debug_options debug_defaults_drv = {
 974         .disable_dmcu = true,
 975         .force_abm_enable = false,
 976         .timing_trace = false,
 977         .clock_trace = true,
 978         .disable_pplib_clock_request = false,
 979         .disable_idle_power_optimizations = true,
 980         .pipe_split_policy = MPC_SPLIT_DYNAMIC,
 981         .force_single_disp_pipe_split = false,
 982         .disable_dcc = DCC_ENABLE,
 983         .vsr_support = true,
 984         .performance_trace = false,
 985         .max_downscale_src_width = 7680,/*upto 8K*/
 986         .disable_pplib_wm_range = false,
 987         .scl_reset_length10 = true,
 988         .sanity_checks = false,
 989         .underflow_assert_delay_us = 0xFFFFFFFF,
 990         .dwb_fi_phase = -1, // -1 = disable,
 991         .dmub_command_table = true,
 992         .enable_mem_low_power = {
 993                 .bits = {
 994                         .vga = false,
 995                         .i2c = false,
 996                         .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
 997                         .dscl = false,
 998                         .cm = false,
 999                         .mpc = false,
1000                         .optc = true,
1001                 }
1002         },
1003         .use_max_lb = true,
1004         .force_disable_subvp = true
1005 };
1006
1007 static const struct dc_debug_options debug_defaults_diags = {
1008         .disable_dmcu = true,
1009         .force_abm_enable = false,
1010         .timing_trace = true,
1011         .clock_trace = true,
1012         .disable_dpp_power_gate = true,
1013         .disable_hubp_power_gate = true,
1014         .disable_dsc_power_gate = true,
1015         .disable_clock_gate = true,
1016         .disable_pplib_clock_request = true,
1017         .disable_pplib_wm_range = true,
1018         .disable_stutter = false,
1019         .scl_reset_length10 = true,
1020         .dwb_fi_phase = -1, // -1 = disable
1021         .dmub_command_table = true,
1022         .enable_tri_buf = true,
1023         .use_max_lb = true,
1024         .force_disable_subvp = true
1025 };
1026
1027 static struct dce_aux *dcn32_aux_engine_create(
1028         struct dc_context *ctx,
1029         uint32_t inst)
1030 {
1031         struct aux_engine_dce110 *aux_engine =
1032                 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
1033
1034         if (!aux_engine)
1035                 return NULL;
1036
1037         dce110_aux_engine_construct(aux_engine, ctx, inst,
1038                                     SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
1039                                     &aux_engine_regs[inst],
1040                                         &aux_mask,
1041                                         &aux_shift,
1042                                         ctx->dc->caps.extended_aux_timeout_support);
1043
1044         return &aux_engine->base;
1045 }
1046 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }
1047
1048 static const struct dce_i2c_registers i2c_hw_regs[] = {
1049                 i2c_inst_regs(1),
1050                 i2c_inst_regs(2),
1051                 i2c_inst_regs(3),
1052                 i2c_inst_regs(4),
1053                 i2c_inst_regs(5),
1054 };
1055
1056 static const struct dce_i2c_shift i2c_shifts = {
1057                 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
1058 };
1059
1060 static const struct dce_i2c_mask i2c_masks = {
1061                 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
1062 };
1063
1064 static struct dce_i2c_hw *dcn32_i2c_hw_create(
1065         struct dc_context *ctx,
1066         uint32_t inst)
1067 {
1068         struct dce_i2c_hw *dce_i2c_hw =
1069                 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
1070
1071         if (!dce_i2c_hw)
1072                 return NULL;
1073
1074         dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
1075                                     &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
1076
1077         return dce_i2c_hw;
1078 }
1079
1080 static struct clock_source *dcn32_clock_source_create(
1081                 struct dc_context *ctx,
1082                 struct dc_bios *bios,
1083                 enum clock_source_id id,
1084                 const struct dce110_clk_src_regs *regs,
1085                 bool dp_clk_src)
1086 {
1087         struct dce110_clk_src *clk_src =
1088                 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1089
1090         if (!clk_src)
1091                 return NULL;
1092
1093         if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
1094                         regs, &cs_shift, &cs_mask)) {
1095                 clk_src->base.dp_clk_src = dp_clk_src;
1096                 return &clk_src->base;
1097         }
1098
1099         BREAK_TO_DEBUGGER();
1100         return NULL;
1101 }
1102
1103 static struct hubbub *dcn32_hubbub_create(struct dc_context *ctx)
1104 {
1105         int i;
1106
1107         struct dcn20_hubbub *hubbub2 = kzalloc(sizeof(struct dcn20_hubbub),
1108                                           GFP_KERNEL);
1109
1110         if (!hubbub2)
1111                 return NULL;
1112
1113         hubbub32_construct(hubbub2, ctx,
1114                         &hubbub_reg,
1115                         &hubbub_shift,
1116                         &hubbub_mask,
1117                         ctx->dc->dml.ip.det_buffer_size_kbytes,
1118                         ctx->dc->dml.ip.pixel_chunk_size_kbytes,
1119                         ctx->dc->dml.ip.config_return_buffer_size_in_kbytes);
1120
1121
1122         for (i = 0; i < res_cap_dcn32.num_vmid; i++) {
1123                 struct dcn20_vmid *vmid = &hubbub2->vmid[i];
1124
1125                 vmid->ctx = ctx;
1126
1127                 vmid->regs = &vmid_regs[i];
1128                 vmid->shifts = &vmid_shifts;
1129                 vmid->masks = &vmid_masks;
1130         }
1131
1132         return &hubbub2->base;
1133 }
1134
1135 static struct hubp *dcn32_hubp_create(
1136         struct dc_context *ctx,
1137         uint32_t inst)
1138 {
1139         struct dcn20_hubp *hubp2 =
1140                 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1141
1142         if (!hubp2)
1143                 return NULL;
1144
1145         if (hubp32_construct(hubp2, ctx, inst,
1146                         &hubp_regs[inst], &hubp_shift, &hubp_mask))
1147                 return &hubp2->base;
1148
1149         BREAK_TO_DEBUGGER();
1150         kfree(hubp2);
1151         return NULL;
1152 }
1153
1154 static void dcn32_dpp_destroy(struct dpp **dpp)
1155 {
1156         kfree(TO_DCN30_DPP(*dpp));
1157         *dpp = NULL;
1158 }
1159
1160 static struct dpp *dcn32_dpp_create(
1161         struct dc_context *ctx,
1162         uint32_t inst)
1163 {
1164         struct dcn3_dpp *dpp3 =
1165                 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
1166
1167         if (!dpp3)
1168                 return NULL;
1169
1170         if (dpp32_construct(dpp3, ctx, inst,
1171                         &dpp_regs[inst], &tf_shift, &tf_mask))
1172                 return &dpp3->base;
1173
1174         BREAK_TO_DEBUGGER();
1175         kfree(dpp3);
1176         return NULL;
1177 }
1178
1179 static struct mpc *dcn32_mpc_create(
1180                 struct dc_context *ctx,
1181                 int num_mpcc,
1182                 int num_rmu)
1183 {
1184         struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
1185                                           GFP_KERNEL);
1186
1187         if (!mpc30)
1188                 return NULL;
1189
1190         dcn32_mpc_construct(mpc30, ctx,
1191                         &mpc_regs,
1192                         &mpc_shift,
1193                         &mpc_mask,
1194                         num_mpcc,
1195                         num_rmu);
1196
1197         return &mpc30->base;
1198 }
1199
1200 static struct output_pixel_processor *dcn32_opp_create(
1201         struct dc_context *ctx, uint32_t inst)
1202 {
1203         struct dcn20_opp *opp2 =
1204                 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
1205
1206         if (!opp2) {
1207                 BREAK_TO_DEBUGGER();
1208                 return NULL;
1209         }
1210
1211         dcn20_opp_construct(opp2, ctx, inst,
1212                         &opp_regs[inst], &opp_shift, &opp_mask);
1213         return &opp2->base;
1214 }
1215
1216
1217 static struct timing_generator *dcn32_timing_generator_create(
1218                 struct dc_context *ctx,
1219                 uint32_t instance)
1220 {
1221         struct optc *tgn10 =
1222                 kzalloc(sizeof(struct optc), GFP_KERNEL);
1223
1224         if (!tgn10)
1225                 return NULL;
1226
1227         tgn10->base.inst = instance;
1228         tgn10->base.ctx = ctx;
1229
1230         tgn10->tg_regs = &optc_regs[instance];
1231         tgn10->tg_shift = &optc_shift;
1232         tgn10->tg_mask = &optc_mask;
1233
1234         dcn32_timing_generator_init(tgn10);
1235
1236         return &tgn10->base;
1237 }
1238
1239 static const struct encoder_feature_support link_enc_feature = {
1240                 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1241                 .max_hdmi_pixel_clock = 600000,
1242                 .hdmi_ycbcr420_supported = true,
1243                 .dp_ycbcr420_supported = true,
1244                 .fec_supported = true,
1245                 .flags.bits.IS_HBR2_CAPABLE = true,
1246                 .flags.bits.IS_HBR3_CAPABLE = true,
1247                 .flags.bits.IS_TPS3_CAPABLE = true,
1248                 .flags.bits.IS_TPS4_CAPABLE = true
1249 };
1250
1251 static struct link_encoder *dcn32_link_encoder_create(
1252         const struct encoder_init_data *enc_init_data)
1253 {
1254         struct dcn20_link_encoder *enc20 =
1255                 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1256
1257         if (!enc20)
1258                 return NULL;
1259
1260         dcn32_link_encoder_construct(enc20,
1261                         enc_init_data,
1262                         &link_enc_feature,
1263                         &link_enc_regs[enc_init_data->transmitter],
1264                         &link_enc_aux_regs[enc_init_data->channel - 1],
1265                         &link_enc_hpd_regs[enc_init_data->hpd_source],
1266                         &le_shift,
1267                         &le_mask);
1268
1269         return &enc20->enc10.base;
1270 }
1271
1272 struct panel_cntl *dcn32_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1273 {
1274         struct dcn31_panel_cntl *panel_cntl =
1275                 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL);
1276
1277         if (!panel_cntl)
1278                 return NULL;
1279
1280         dcn31_panel_cntl_construct(panel_cntl, init_data);
1281
1282         return &panel_cntl->base;
1283 }
1284
1285 static void read_dce_straps(
1286         struct dc_context *ctx,
1287         struct resource_straps *straps)
1288 {
1289         generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),
1290                 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1291
1292 }
1293
1294 static struct audio *dcn32_create_audio(
1295                 struct dc_context *ctx, unsigned int inst)
1296 {
1297         return dce_audio_create(ctx, inst,
1298                         &audio_regs[inst], &audio_shift, &audio_mask);
1299 }
1300
1301 static struct vpg *dcn32_vpg_create(
1302         struct dc_context *ctx,
1303         uint32_t inst)
1304 {
1305         struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL);
1306
1307         if (!vpg3)
1308                 return NULL;
1309
1310         vpg3_construct(vpg3, ctx, inst,
1311                         &vpg_regs[inst],
1312                         &vpg_shift,
1313                         &vpg_mask);
1314
1315         return &vpg3->base;
1316 }
1317
1318 static struct afmt *dcn32_afmt_create(
1319         struct dc_context *ctx,
1320         uint32_t inst)
1321 {
1322         struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);
1323
1324         if (!afmt3)
1325                 return NULL;
1326
1327         afmt3_construct(afmt3, ctx, inst,
1328                         &afmt_regs[inst],
1329                         &afmt_shift,
1330                         &afmt_mask);
1331
1332         return &afmt3->base;
1333 }
1334
1335 static struct apg *dcn31_apg_create(
1336         struct dc_context *ctx,
1337         uint32_t inst)
1338 {
1339         struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL);
1340
1341         if (!apg31)
1342                 return NULL;
1343
1344         apg31_construct(apg31, ctx, inst,
1345                         &apg_regs[inst],
1346                         &apg_shift,
1347                         &apg_mask);
1348
1349         return &apg31->base;
1350 }
1351
1352 static struct stream_encoder *dcn32_stream_encoder_create(
1353         enum engine_id eng_id,
1354         struct dc_context *ctx)
1355 {
1356         struct dcn10_stream_encoder *enc1;
1357         struct vpg *vpg;
1358         struct afmt *afmt;
1359         int vpg_inst;
1360         int afmt_inst;
1361
1362         /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1363         if (eng_id <= ENGINE_ID_DIGF) {
1364                 vpg_inst = eng_id;
1365                 afmt_inst = eng_id;
1366         } else
1367                 return NULL;
1368
1369         enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1370         vpg = dcn32_vpg_create(ctx, vpg_inst);
1371         afmt = dcn32_afmt_create(ctx, afmt_inst);
1372
1373         if (!enc1 || !vpg || !afmt) {
1374                 kfree(enc1);
1375                 kfree(vpg);
1376                 kfree(afmt);
1377                 return NULL;
1378         }
1379
1380         dcn32_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1381                                         eng_id, vpg, afmt,
1382                                         &stream_enc_regs[eng_id],
1383                                         &se_shift, &se_mask);
1384
1385         return &enc1->base;
1386 }
1387
1388 static struct hpo_dp_stream_encoder *dcn32_hpo_dp_stream_encoder_create(
1389         enum engine_id eng_id,
1390         struct dc_context *ctx)
1391 {
1392         struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1393         struct vpg *vpg;
1394         struct apg *apg;
1395         uint32_t hpo_dp_inst;
1396         uint32_t vpg_inst;
1397         uint32_t apg_inst;
1398
1399         ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1400         hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1401
1402         /* Mapping of VPG register blocks to HPO DP block instance:
1403          * VPG[6] -> HPO_DP[0]
1404          * VPG[7] -> HPO_DP[1]
1405          * VPG[8] -> HPO_DP[2]
1406          * VPG[9] -> HPO_DP[3]
1407          */
1408         vpg_inst = hpo_dp_inst + 6;
1409
1410         /* Mapping of APG register blocks to HPO DP block instance:
1411          * APG[0] -> HPO_DP[0]
1412          * APG[1] -> HPO_DP[1]
1413          * APG[2] -> HPO_DP[2]
1414          * APG[3] -> HPO_DP[3]
1415          */
1416         apg_inst = hpo_dp_inst;
1417
1418         /* allocate HPO stream encoder and create VPG sub-block */
1419         hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL);
1420         vpg = dcn32_vpg_create(ctx, vpg_inst);
1421         apg = dcn31_apg_create(ctx, apg_inst);
1422
1423         if (!hpo_dp_enc31 || !vpg || !apg) {
1424                 kfree(hpo_dp_enc31);
1425                 kfree(vpg);
1426                 kfree(apg);
1427                 return NULL;
1428         }
1429
1430         dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1431                                         hpo_dp_inst, eng_id, vpg, apg,
1432                                         &hpo_dp_stream_enc_regs[hpo_dp_inst],
1433                                         &hpo_dp_se_shift, &hpo_dp_se_mask);
1434
1435         return &hpo_dp_enc31->base;
1436 }
1437
1438 static struct hpo_dp_link_encoder *dcn32_hpo_dp_link_encoder_create(
1439         uint8_t inst,
1440         struct dc_context *ctx)
1441 {
1442         struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1443
1444         /* allocate HPO link encoder */
1445         hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);
1446
1447         hpo_dp_link_encoder32_construct(hpo_dp_enc31, ctx, inst,
1448                                         &hpo_dp_link_enc_regs[inst],
1449                                         &hpo_dp_le_shift, &hpo_dp_le_mask);
1450
1451         return &hpo_dp_enc31->base;
1452 }
1453
1454 static struct dce_hwseq *dcn32_hwseq_create(
1455         struct dc_context *ctx)
1456 {
1457         struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1458
1459         if (hws) {
1460                 hws->ctx = ctx;
1461                 hws->regs = &hwseq_reg;
1462                 hws->shifts = &hwseq_shift;
1463                 hws->masks = &hwseq_mask;
1464         }
1465         return hws;
1466 }
1467 static const struct resource_create_funcs res_create_funcs = {
1468         .read_dce_straps = read_dce_straps,
1469         .create_audio = dcn32_create_audio,
1470         .create_stream_encoder = dcn32_stream_encoder_create,
1471         .create_hpo_dp_stream_encoder = dcn32_hpo_dp_stream_encoder_create,
1472         .create_hpo_dp_link_encoder = dcn32_hpo_dp_link_encoder_create,
1473         .create_hwseq = dcn32_hwseq_create,
1474 };
1475
1476 static const struct resource_create_funcs res_create_maximus_funcs = {
1477         .read_dce_straps = NULL,
1478         .create_audio = NULL,
1479         .create_stream_encoder = NULL,
1480         .create_hpo_dp_stream_encoder = dcn32_hpo_dp_stream_encoder_create,
1481         .create_hpo_dp_link_encoder = dcn32_hpo_dp_link_encoder_create,
1482         .create_hwseq = dcn32_hwseq_create,
1483 };
1484
1485 static void dcn32_resource_destruct(struct dcn32_resource_pool *pool)
1486 {
1487         unsigned int i;
1488
1489         for (i = 0; i < pool->base.stream_enc_count; i++) {
1490                 if (pool->base.stream_enc[i] != NULL) {
1491                         if (pool->base.stream_enc[i]->vpg != NULL) {
1492                                 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1493                                 pool->base.stream_enc[i]->vpg = NULL;
1494                         }
1495                         if (pool->base.stream_enc[i]->afmt != NULL) {
1496                                 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1497                                 pool->base.stream_enc[i]->afmt = NULL;
1498                         }
1499                         kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1500                         pool->base.stream_enc[i] = NULL;
1501                 }
1502         }
1503
1504         for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1505                 if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1506                         if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1507                                 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1508                                 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1509                         }
1510                         if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1511                                 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1512                                 pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1513                         }
1514                         kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1515                         pool->base.hpo_dp_stream_enc[i] = NULL;
1516                 }
1517         }
1518
1519         for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1520                 if (pool->base.hpo_dp_link_enc[i] != NULL) {
1521                         kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1522                         pool->base.hpo_dp_link_enc[i] = NULL;
1523                 }
1524         }
1525
1526         for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1527                 if (pool->base.dscs[i] != NULL)
1528                         dcn20_dsc_destroy(&pool->base.dscs[i]);
1529         }
1530
1531         if (pool->base.mpc != NULL) {
1532                 kfree(TO_DCN20_MPC(pool->base.mpc));
1533                 pool->base.mpc = NULL;
1534         }
1535         if (pool->base.hubbub != NULL) {
1536                 kfree(TO_DCN20_HUBBUB(pool->base.hubbub));
1537                 pool->base.hubbub = NULL;
1538         }
1539         for (i = 0; i < pool->base.pipe_count; i++) {
1540                 if (pool->base.dpps[i] != NULL)
1541                         dcn32_dpp_destroy(&pool->base.dpps[i]);
1542
1543                 if (pool->base.ipps[i] != NULL)
1544                         pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1545
1546                 if (pool->base.hubps[i] != NULL) {
1547                         kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1548                         pool->base.hubps[i] = NULL;
1549                 }
1550
1551                 if (pool->base.irqs != NULL) {
1552                         dal_irq_service_destroy(&pool->base.irqs);
1553                 }
1554         }
1555
1556         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1557                 if (pool->base.engines[i] != NULL)
1558                         dce110_engine_destroy(&pool->base.engines[i]);
1559                 if (pool->base.hw_i2cs[i] != NULL) {
1560                         kfree(pool->base.hw_i2cs[i]);
1561                         pool->base.hw_i2cs[i] = NULL;
1562                 }
1563                 if (pool->base.sw_i2cs[i] != NULL) {
1564                         kfree(pool->base.sw_i2cs[i]);
1565                         pool->base.sw_i2cs[i] = NULL;
1566                 }
1567         }
1568
1569         for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1570                 if (pool->base.opps[i] != NULL)
1571                         pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1572         }
1573
1574         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1575                 if (pool->base.timing_generators[i] != NULL)    {
1576                         kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1577                         pool->base.timing_generators[i] = NULL;
1578                 }
1579         }
1580
1581         for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1582                 if (pool->base.dwbc[i] != NULL) {
1583                         kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1584                         pool->base.dwbc[i] = NULL;
1585                 }
1586                 if (pool->base.mcif_wb[i] != NULL) {
1587                         kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1588                         pool->base.mcif_wb[i] = NULL;
1589                 }
1590         }
1591
1592         for (i = 0; i < pool->base.audio_count; i++) {
1593                 if (pool->base.audios[i])
1594                         dce_aud_destroy(&pool->base.audios[i]);
1595         }
1596
1597         for (i = 0; i < pool->base.clk_src_count; i++) {
1598                 if (pool->base.clock_sources[i] != NULL) {
1599                         dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1600                         pool->base.clock_sources[i] = NULL;
1601                 }
1602         }
1603
1604         for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1605                 if (pool->base.mpc_lut[i] != NULL) {
1606                         dc_3dlut_func_release(pool->base.mpc_lut[i]);
1607                         pool->base.mpc_lut[i] = NULL;
1608                 }
1609                 if (pool->base.mpc_shaper[i] != NULL) {
1610                         dc_transfer_func_release(pool->base.mpc_shaper[i]);
1611                         pool->base.mpc_shaper[i] = NULL;
1612                 }
1613         }
1614
1615         if (pool->base.dp_clock_source != NULL) {
1616                 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1617                 pool->base.dp_clock_source = NULL;
1618         }
1619
1620         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1621                 if (pool->base.multiple_abms[i] != NULL)
1622                         dce_abm_destroy(&pool->base.multiple_abms[i]);
1623         }
1624
1625         if (pool->base.psr != NULL)
1626                 dmub_psr_destroy(&pool->base.psr);
1627
1628         if (pool->base.dccg != NULL)
1629                 dcn_dccg_destroy(&pool->base.dccg);
1630
1631         if (pool->base.oem_device != NULL)
1632                 dal_ddc_service_destroy(&pool->base.oem_device);
1633 }
1634
1635
1636 static bool dcn32_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1637 {
1638         int i;
1639         uint32_t dwb_count = pool->res_cap->num_dwb;
1640
1641         for (i = 0; i < dwb_count; i++) {
1642                 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1643                                                     GFP_KERNEL);
1644
1645                 if (!dwbc30) {
1646                         dm_error("DC: failed to create dwbc30!\n");
1647                         return false;
1648                 }
1649
1650                 dcn30_dwbc_construct(dwbc30, ctx,
1651                                 &dwbc30_regs[i],
1652                                 &dwbc30_shift,
1653                                 &dwbc30_mask,
1654                                 i);
1655
1656                 pool->dwbc[i] = &dwbc30->base;
1657         }
1658         return true;
1659 }
1660
1661 static bool dcn32_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1662 {
1663         int i;
1664         uint32_t dwb_count = pool->res_cap->num_dwb;
1665
1666         for (i = 0; i < dwb_count; i++) {
1667                 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1668                                                     GFP_KERNEL);
1669
1670                 if (!mcif_wb30) {
1671                         dm_error("DC: failed to create mcif_wb30!\n");
1672                         return false;
1673                 }
1674
1675                 dcn32_mmhubbub_construct(mcif_wb30, ctx,
1676                                 &mcif_wb30_regs[i],
1677                                 &mcif_wb30_shift,
1678                                 &mcif_wb30_mask,
1679                                 i);
1680
1681                 pool->mcif_wb[i] = &mcif_wb30->base;
1682         }
1683         return true;
1684 }
1685
1686 static struct display_stream_compressor *dcn32_dsc_create(
1687         struct dc_context *ctx, uint32_t inst)
1688 {
1689         struct dcn20_dsc *dsc =
1690                 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1691
1692         if (!dsc) {
1693                 BREAK_TO_DEBUGGER();
1694                 return NULL;
1695         }
1696
1697         dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1698
1699         dsc->max_image_width = 6016;
1700
1701         return &dsc->base;
1702 }
1703
1704 static void dcn32_destroy_resource_pool(struct resource_pool **pool)
1705 {
1706         struct dcn32_resource_pool *dcn32_pool = TO_DCN32_RES_POOL(*pool);
1707
1708         dcn32_resource_destruct(dcn32_pool);
1709         kfree(dcn32_pool);
1710         *pool = NULL;
1711 }
1712
1713 bool dcn32_acquire_post_bldn_3dlut(
1714                 struct resource_context *res_ctx,
1715                 const struct resource_pool *pool,
1716                 int mpcc_id,
1717                 struct dc_3dlut **lut,
1718                 struct dc_transfer_func **shaper)
1719 {
1720         bool ret = false;
1721         union dc_3dlut_state *state;
1722
1723         ASSERT(*lut == NULL && *shaper == NULL);
1724         *lut = NULL;
1725         *shaper = NULL;
1726
1727         if (!res_ctx->is_mpc_3dlut_acquired[mpcc_id]) {
1728                 *lut = pool->mpc_lut[mpcc_id];
1729                 *shaper = pool->mpc_shaper[mpcc_id];
1730                 state = &pool->mpc_lut[mpcc_id]->state;
1731                 res_ctx->is_mpc_3dlut_acquired[mpcc_id] = true;
1732                 ret = true;
1733         }
1734         return ret;
1735 }
1736
1737 bool dcn32_release_post_bldn_3dlut(
1738                 struct resource_context *res_ctx,
1739                 const struct resource_pool *pool,
1740                 struct dc_3dlut **lut,
1741                 struct dc_transfer_func **shaper)
1742 {
1743         int i;
1744         bool ret = false;
1745
1746         for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
1747                 if (pool->mpc_lut[i] == *lut && pool->mpc_shaper[i] == *shaper) {
1748                         res_ctx->is_mpc_3dlut_acquired[i] = false;
1749                         pool->mpc_lut[i]->state.raw = 0;
1750                         *lut = NULL;
1751                         *shaper = NULL;
1752                         ret = true;
1753                         break;
1754                 }
1755         }
1756         return ret;
1757 }
1758
1759 /**
1760  ********************************************************************************************
1761  * dcn32_get_num_free_pipes: Calculate number of free pipes
1762  *
1763  * This function assumes that a "used" pipe is a pipe that has
1764  * both a stream and a plane assigned to it.
1765  *
1766  * @param [in] dc: current dc state
1767  * @param [in] context: new dc state
1768  *
1769  * @return: Number of free pipes available in the context
1770  *
1771  ********************************************************************************************
1772  */
1773 static unsigned int dcn32_get_num_free_pipes(struct dc *dc, struct dc_state *context)
1774 {
1775         unsigned int i;
1776         unsigned int free_pipes = 0;
1777         unsigned int num_pipes = 0;
1778
1779         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1780                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1781
1782                 if (pipe->stream && pipe->plane_state && !pipe->top_pipe) {
1783                         while (pipe) {
1784                                 num_pipes++;
1785                                 pipe = pipe->bottom_pipe;
1786                         }
1787                 }
1788         }
1789
1790         free_pipes = dc->res_pool->pipe_count - num_pipes;
1791         return free_pipes;
1792 }
1793
1794 /**
1795  ********************************************************************************************
1796  * dcn32_assign_subvp_pipe: Function to decide which pipe will use Sub-VP.
1797  *
1798  * We enter this function if we are Sub-VP capable (i.e. enough pipes available)
1799  * and regular P-State switching (i.e. VACTIVE/VBLANK) is not supported, or if
1800  * we are forcing SubVP P-State switching on the current config.
1801  *
1802  * The number of pipes used for the chosen surface must be less than or equal to the
1803  * number of free pipes available.
1804  *
1805  * In general we choose surfaces that have ActiveDRAMClockChangeLatencyMargin <= 0 first,
1806  * then among those surfaces we choose the one with the smallest VBLANK time. We only consider
1807  * surfaces with ActiveDRAMClockChangeLatencyMargin > 0 if we are forcing a Sub-VP config.
1808  *
1809  * @param [in] dc: current dc state
1810  * @param [in] context: new dc state
1811  * @param [out] index: dc pipe index for the pipe chosen to have phantom pipes assigned
1812  *
1813  * @return: True if a valid pipe assignment was found for Sub-VP. Otherwise false.
1814  *
1815  ********************************************************************************************
1816  */
1817
1818 static bool dcn32_assign_subvp_pipe(struct dc *dc,
1819                 struct dc_state *context,
1820                 unsigned int *index)
1821 {
1822         unsigned int i, pipe_idx;
1823         unsigned int min_vblank_us = INT_MAX;
1824         struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
1825         bool valid_assignment_found = false;
1826         unsigned int free_pipes = dcn32_get_num_free_pipes(dc, context);
1827
1828         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1829                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1830                 unsigned int num_pipes = 0;
1831
1832                 if (!pipe->stream)
1833                         continue;
1834
1835                 if (pipe->plane_state && !pipe->top_pipe &&
1836                                 pipe->stream->mall_stream_config.type == SUBVP_NONE) {
1837                         while (pipe) {
1838                                 num_pipes++;
1839                                 pipe = pipe->bottom_pipe;
1840                         }
1841
1842                         pipe = &context->res_ctx.pipe_ctx[i];
1843                         if (num_pipes <= free_pipes) {
1844                                 struct dc_stream_state *stream = pipe->stream;
1845                                 unsigned int vblank_us = ((stream->timing.v_total - stream->timing.v_addressable) *
1846                                                         stream->timing.h_total /
1847                                                         (double)(stream->timing.pix_clk_100hz * 100)) * 1000000;
1848                                 if (vba->ActiveDRAMClockChangeLatencyMargin[vba->pipe_plane[pipe_idx]] <= 0 &&
1849                                                 vblank_us < min_vblank_us) {
1850                                         *index = i;
1851                                         min_vblank_us = vblank_us;
1852                                         valid_assignment_found = true;
1853                                 } else if (vba->ActiveDRAMClockChangeLatencyMargin[vba->pipe_plane[pipe_idx]] > 0 &&
1854                                                 dc->debug.force_subvp_mclk_switch && !valid_assignment_found) {
1855                                         // Handle case for forcing Sub-VP config. In this case we can assign
1856                                         // phantom pipes to a surface that has active margin > 0.
1857                                         *index = i;
1858                                         valid_assignment_found = true;
1859                                 }
1860                         }
1861                 }
1862                 pipe_idx++;
1863         }
1864         return valid_assignment_found;
1865 }
1866
1867 /**
1868  * ***************************************************************************************
1869  * dcn32_enough_pipes_for_subvp: Function to check if there are "enough" pipes for SubVP.
1870  *
1871  * This function returns true if there are enough free pipes
1872  * to create the required phantom pipes for any given stream
1873  * (that does not already have phantom pipe assigned).
1874  *
1875  * e.g. For a 2 stream config where the first stream uses one
1876  * pipe and the second stream uses 2 pipes (i.e. pipe split),
1877  * this function will return true because there is 1 remaining
1878  * pipe which can be used as the phantom pipe for the non pipe
1879  * split pipe.
1880  *
1881  * @param [in] dc: current dc state
1882  * @param [in] context: new dc state
1883  *
1884  * @return: True if there are enough free pipes to assign phantom pipes to at least one
1885  *          stream that does not already have phantom pipes assigned. Otherwise false.
1886  *
1887  * ***************************************************************************************
1888  */
1889 static bool dcn32_enough_pipes_for_subvp(struct dc *dc, struct dc_state *context)
1890 {
1891         unsigned int i, split_cnt, free_pipes;
1892         unsigned int min_pipe_split = dc->res_pool->pipe_count + 1; // init as max number of pipes + 1
1893         bool subvp_possible = false;
1894
1895         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1896                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1897
1898                 // Find the minimum pipe split count for non SubVP pipes
1899                 if (pipe->stream && pipe->plane_state && !pipe->top_pipe &&
1900                                 pipe->stream->mall_stream_config.type == SUBVP_NONE) {
1901                         split_cnt = 0;
1902                         while (pipe) {
1903                                 split_cnt++;
1904                                 pipe = pipe->bottom_pipe;
1905                         }
1906
1907                         if (split_cnt < min_pipe_split)
1908                                 min_pipe_split = split_cnt;
1909                 }
1910         }
1911
1912         free_pipes = dcn32_get_num_free_pipes(dc, context);
1913
1914         // SubVP only possible if at least one pipe is being used (i.e. free_pipes
1915         // should not equal to the pipe_count)
1916         if (free_pipes >= min_pipe_split && free_pipes < dc->res_pool->pipe_count)
1917                 subvp_possible = true;
1918
1919         return subvp_possible;
1920 }
1921
1922 static void dcn32_enable_phantom_plane(struct dc *dc,
1923                 struct dc_state *context,
1924                 struct dc_stream_state *phantom_stream,
1925                 unsigned int dc_pipe_idx)
1926 {
1927         struct dc_plane_state *phantom_plane = NULL;
1928         struct dc_plane_state *prev_phantom_plane = NULL;
1929         struct pipe_ctx *curr_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx];
1930
1931         while (curr_pipe) {
1932                 if (curr_pipe->top_pipe && curr_pipe->top_pipe->plane_state == curr_pipe->plane_state)
1933                         phantom_plane = prev_phantom_plane;
1934                 else
1935                         phantom_plane = dc_create_plane_state(dc);
1936
1937                 memcpy(&phantom_plane->address, &curr_pipe->plane_state->address, sizeof(phantom_plane->address));
1938                 memcpy(&phantom_plane->scaling_quality, &curr_pipe->plane_state->scaling_quality,
1939                                 sizeof(phantom_plane->scaling_quality));
1940                 memcpy(&phantom_plane->src_rect, &curr_pipe->plane_state->src_rect, sizeof(phantom_plane->src_rect));
1941                 memcpy(&phantom_plane->dst_rect, &curr_pipe->plane_state->dst_rect, sizeof(phantom_plane->dst_rect));
1942                 memcpy(&phantom_plane->clip_rect, &curr_pipe->plane_state->clip_rect, sizeof(phantom_plane->clip_rect));
1943                 memcpy(&phantom_plane->plane_size, &curr_pipe->plane_state->plane_size,
1944                                 sizeof(phantom_plane->plane_size));
1945                 memcpy(&phantom_plane->tiling_info, &curr_pipe->plane_state->tiling_info,
1946                                 sizeof(phantom_plane->tiling_info));
1947                 memcpy(&phantom_plane->dcc, &curr_pipe->plane_state->dcc, sizeof(phantom_plane->dcc));
1948                 phantom_plane->format = curr_pipe->plane_state->format;
1949                 phantom_plane->rotation = curr_pipe->plane_state->rotation;
1950                 phantom_plane->visible = curr_pipe->plane_state->visible;
1951
1952                 /* Shadow pipe has small viewport. */
1953                 phantom_plane->clip_rect.y = 0;
1954                 phantom_plane->clip_rect.height = phantom_stream->timing.v_addressable;
1955
1956                 dc_add_plane_to_context(dc, phantom_stream, phantom_plane, context);
1957
1958                 curr_pipe = curr_pipe->bottom_pipe;
1959                 prev_phantom_plane = phantom_plane;
1960         }
1961 }
1962
1963 /**
1964  * ***************************************************************************************
1965  * dcn32_set_phantom_stream_timing: Set timing params for the phantom stream
1966  *
1967  * Set timing params of the phantom stream based on calculated output from DML.
1968  * This function first gets the DML pipe index using the DC pipe index, then
1969  * calls into DML (get_subviewport_lines_needed_in_mall) to get the number of
1970  * lines required for SubVP MCLK switching and assigns to the phantom stream
1971  * accordingly.
1972  *
1973  * - The number of SubVP lines calculated in DML does not take into account
1974  * FW processing delays and required pstate allow width, so we must include
1975  * that separately.
1976  *
1977  * - Set phantom backporch = vstartup of main pipe
1978  *
1979  * @param [in] dc: current dc state
1980  * @param [in] context: new dc state
1981  * @param [in] ref_pipe: Main pipe for the phantom stream
1982  * @param [in] pipes: DML pipe params
1983  * @param [in] pipe_cnt: number of DML pipes
1984  * @param [in] dc_pipe_idx: DC pipe index for the main pipe (i.e. ref_pipe)
1985  *
1986  * @return: void
1987  *
1988  * ***************************************************************************************
1989  */
1990 static void dcn32_set_phantom_stream_timing(struct dc *dc,
1991                 struct dc_state *context,
1992                 struct pipe_ctx *ref_pipe,
1993                 struct dc_stream_state *phantom_stream,
1994                 display_e2e_pipe_params_st *pipes,
1995                 unsigned int pipe_cnt,
1996                 unsigned int dc_pipe_idx)
1997 {
1998         unsigned int i, pipe_idx;
1999         struct pipe_ctx *pipe;
2000         uint32_t phantom_vactive, phantom_bp, pstate_width_fw_delay_lines;
2001         unsigned int vlevel = context->bw_ctx.dml.vba.VoltageLevel;
2002         unsigned int dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
2003         unsigned int socclk = context->bw_ctx.dml.vba.SOCCLKPerState[vlevel];
2004
2005         // Find DML pipe index (pipe_idx) using dc_pipe_idx
2006         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2007                 pipe = &context->res_ctx.pipe_ctx[i];
2008
2009                 if (!pipe->stream)
2010                         continue;
2011
2012                 if (i == dc_pipe_idx)
2013                         break;
2014
2015                 pipe_idx++;
2016         }
2017
2018         // Calculate lines required for pstate allow width and FW processing delays
2019         pstate_width_fw_delay_lines = ((double)(dc->caps.subvp_fw_processing_delay_us +
2020                         dc->caps.subvp_pstate_allow_width_us) / 1000000) *
2021                         (ref_pipe->stream->timing.pix_clk_100hz * 100) /
2022                         (double)ref_pipe->stream->timing.h_total;
2023
2024         // Update clks_cfg for calling into recalculate
2025         pipes[0].clks_cfg.voltage = vlevel;
2026         pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
2027         pipes[0].clks_cfg.socclk_mhz = socclk;
2028
2029         // DML calculation for MALL region doesn't take into account FW delay
2030         // and required pstate allow width for multi-display cases
2031         phantom_vactive = get_subviewport_lines_needed_in_mall(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx) +
2032                                 pstate_width_fw_delay_lines;
2033
2034         // For backporch of phantom pipe, use vstartup of the main pipe
2035         phantom_bp = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
2036
2037         phantom_stream->dst.y = 0;
2038         phantom_stream->dst.height = phantom_vactive;
2039         phantom_stream->src.y = 0;
2040         phantom_stream->src.height = phantom_vactive;
2041
2042         phantom_stream->timing.v_addressable = phantom_vactive;
2043         phantom_stream->timing.v_front_porch = 1;
2044         phantom_stream->timing.v_total = phantom_stream->timing.v_addressable +
2045                                                 phantom_stream->timing.v_front_porch +
2046                                                 phantom_stream->timing.v_sync_width +
2047                                                 phantom_bp;
2048 }
2049
2050 static struct dc_stream_state *dcn32_enable_phantom_stream(struct dc *dc,
2051                 struct dc_state *context,
2052                 display_e2e_pipe_params_st *pipes,
2053                 unsigned int pipe_cnt,
2054                 unsigned int dc_pipe_idx)
2055 {
2056         struct dc_stream_state *phantom_stream = NULL;
2057         struct pipe_ctx *ref_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx];
2058
2059         phantom_stream = dc_create_stream_for_sink(ref_pipe->stream->sink);
2060         phantom_stream->signal = SIGNAL_TYPE_VIRTUAL;
2061         phantom_stream->dpms_off = true;
2062         phantom_stream->mall_stream_config.type = SUBVP_PHANTOM;
2063         phantom_stream->mall_stream_config.paired_stream = ref_pipe->stream;
2064         ref_pipe->stream->mall_stream_config.type = SUBVP_MAIN;
2065         ref_pipe->stream->mall_stream_config.paired_stream = phantom_stream;
2066
2067         /* stream has limited viewport and small timing */
2068         memcpy(&phantom_stream->timing, &ref_pipe->stream->timing, sizeof(phantom_stream->timing));
2069         memcpy(&phantom_stream->src, &ref_pipe->stream->src, sizeof(phantom_stream->src));
2070         memcpy(&phantom_stream->dst, &ref_pipe->stream->dst, sizeof(phantom_stream->dst));
2071         dcn32_set_phantom_stream_timing(dc, context, ref_pipe, phantom_stream, pipes, pipe_cnt, dc_pipe_idx);
2072
2073         dc_add_stream_to_ctx(dc, context, phantom_stream);
2074         return phantom_stream;
2075 }
2076
2077 void dcn32_remove_phantom_pipes(struct dc *dc, struct dc_state *context)
2078 {
2079         int i;
2080         bool removed_pipe = false;
2081
2082         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2083                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2084                 // build scaling params for phantom pipes
2085                 if (pipe->plane_state && pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) {
2086                         dc_rem_all_planes_for_stream(dc, pipe->stream, context);
2087                         dc_remove_stream_from_ctx(dc, context, pipe->stream);
2088                         removed_pipe = true;
2089                 }
2090
2091                 // Clear all phantom stream info
2092                 if (pipe->stream) {
2093                         pipe->stream->mall_stream_config.type = SUBVP_NONE;
2094                         pipe->stream->mall_stream_config.paired_stream = NULL;
2095                 }
2096         }
2097         if (removed_pipe)
2098                 dc->hwss.apply_ctx_to_hw(dc, context);
2099 }
2100
2101 /* TODO: Input to this function should indicate which pipe indexes (or streams)
2102  * require a phantom pipe / stream
2103  */
2104 void dcn32_add_phantom_pipes(struct dc *dc, struct dc_state *context,
2105                 display_e2e_pipe_params_st *pipes,
2106                 unsigned int pipe_cnt,
2107                 unsigned int index)
2108 {
2109         struct dc_stream_state *phantom_stream = NULL;
2110         unsigned int i;
2111
2112         // The index of the DC pipe passed into this function is guarenteed to
2113         // be a valid candidate for SubVP (i.e. has a plane, stream, doesn't
2114         // already have phantom pipe assigned, etc.) by previous checks.
2115         phantom_stream = dcn32_enable_phantom_stream(dc, context, pipes, pipe_cnt, index);
2116         dcn32_enable_phantom_plane(dc, context, phantom_stream, index);
2117
2118         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2119                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2120
2121                 // Build scaling params for phantom pipes which were newly added.
2122                 // We determine which phantom pipes were added by comparing with
2123                 // the phantom stream.
2124                 if (pipe->plane_state && pipe->stream && pipe->stream == phantom_stream &&
2125                                 pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) {
2126                         pipe->stream->use_dynamic_meta = false;
2127                         pipe->plane_state->flip_immediate = false;
2128                         if (!resource_build_scaling_params(pipe)) {
2129                                 // Log / remove phantom pipes since failed to build scaling params
2130                         }
2131                 }
2132         }
2133 }
2134
2135 static bool dcn32_split_stream_for_mpc_or_odm(
2136                 const struct dc *dc,
2137                 struct resource_context *res_ctx,
2138                 struct pipe_ctx *pri_pipe,
2139                 struct pipe_ctx *sec_pipe,
2140                 bool odm)
2141 {
2142         int pipe_idx = sec_pipe->pipe_idx;
2143         const struct resource_pool *pool = dc->res_pool;
2144
2145         if (pri_pipe->plane_state) {
2146                 /* ODM + window MPO, where MPO window is on left half only */
2147                 if (pri_pipe->plane_state->clip_rect.x + pri_pipe->plane_state->clip_rect.width <=
2148                                 pri_pipe->stream->src.x + pri_pipe->stream->src.width/2)
2149                         return true;
2150
2151                 /* ODM + window MPO, where MPO window is on right half only */
2152                 if (pri_pipe->plane_state->clip_rect.x >= pri_pipe->stream->src.width/2)
2153                         return true;
2154         }
2155
2156         *sec_pipe = *pri_pipe;
2157
2158         sec_pipe->pipe_idx = pipe_idx;
2159         sec_pipe->plane_res.mi = pool->mis[pipe_idx];
2160         sec_pipe->plane_res.hubp = pool->hubps[pipe_idx];
2161         sec_pipe->plane_res.ipp = pool->ipps[pipe_idx];
2162         sec_pipe->plane_res.xfm = pool->transforms[pipe_idx];
2163         sec_pipe->plane_res.dpp = pool->dpps[pipe_idx];
2164         sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst;
2165         sec_pipe->stream_res.dsc = NULL;
2166         if (odm) {
2167                 if (pri_pipe->next_odm_pipe) {
2168                         ASSERT(pri_pipe->next_odm_pipe != sec_pipe);
2169                         sec_pipe->next_odm_pipe = pri_pipe->next_odm_pipe;
2170                         sec_pipe->next_odm_pipe->prev_odm_pipe = sec_pipe;
2171                 }
2172                 if (pri_pipe->top_pipe && pri_pipe->top_pipe->next_odm_pipe) {
2173                         pri_pipe->top_pipe->next_odm_pipe->bottom_pipe = sec_pipe;
2174                         sec_pipe->top_pipe = pri_pipe->top_pipe->next_odm_pipe;
2175                 }
2176                 if (pri_pipe->bottom_pipe && pri_pipe->bottom_pipe->next_odm_pipe) {
2177                         pri_pipe->bottom_pipe->next_odm_pipe->top_pipe = sec_pipe;
2178                         sec_pipe->bottom_pipe = pri_pipe->bottom_pipe->next_odm_pipe;
2179                 }
2180                 pri_pipe->next_odm_pipe = sec_pipe;
2181                 sec_pipe->prev_odm_pipe = pri_pipe;
2182                 ASSERT(sec_pipe->top_pipe == NULL);
2183
2184                 if (!sec_pipe->top_pipe)
2185                         sec_pipe->stream_res.opp = pool->opps[pipe_idx];
2186                 else
2187                         sec_pipe->stream_res.opp = sec_pipe->top_pipe->stream_res.opp;
2188                 if (sec_pipe->stream->timing.flags.DSC == 1) {
2189                         dcn20_acquire_dsc(dc, res_ctx, &sec_pipe->stream_res.dsc, pipe_idx);
2190                         ASSERT(sec_pipe->stream_res.dsc);
2191                         if (sec_pipe->stream_res.dsc == NULL)
2192                                 return false;
2193                 }
2194         } else {
2195                 if (pri_pipe->bottom_pipe) {
2196                         ASSERT(pri_pipe->bottom_pipe != sec_pipe);
2197                         sec_pipe->bottom_pipe = pri_pipe->bottom_pipe;
2198                         sec_pipe->bottom_pipe->top_pipe = sec_pipe;
2199                 }
2200                 pri_pipe->bottom_pipe = sec_pipe;
2201                 sec_pipe->top_pipe = pri_pipe;
2202
2203                 ASSERT(pri_pipe->plane_state);
2204         }
2205
2206         return true;
2207 }
2208
2209 static struct pipe_ctx *dcn32_find_split_pipe(
2210                 struct dc *dc,
2211                 struct dc_state *context,
2212                 int old_index)
2213 {
2214         struct pipe_ctx *pipe = NULL;
2215         int i;
2216
2217         if (old_index >= 0 && context->res_ctx.pipe_ctx[old_index].stream == NULL) {
2218                 pipe = &context->res_ctx.pipe_ctx[old_index];
2219                 pipe->pipe_idx = old_index;
2220         }
2221
2222         if (!pipe)
2223                 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
2224                         if (dc->current_state->res_ctx.pipe_ctx[i].top_pipe == NULL
2225                                         && dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe == NULL) {
2226                                 if (context->res_ctx.pipe_ctx[i].stream == NULL) {
2227                                         pipe = &context->res_ctx.pipe_ctx[i];
2228                                         pipe->pipe_idx = i;
2229                                         break;
2230                                 }
2231                         }
2232                 }
2233
2234         /*
2235          * May need to fix pipes getting tossed from 1 opp to another on flip
2236          * Add for debugging transient underflow during topology updates:
2237          * ASSERT(pipe);
2238          */
2239         if (!pipe)
2240                 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
2241                         if (context->res_ctx.pipe_ctx[i].stream == NULL) {
2242                                 pipe = &context->res_ctx.pipe_ctx[i];
2243                                 pipe->pipe_idx = i;
2244                                 break;
2245                         }
2246                 }
2247
2248         return pipe;
2249 }
2250
2251
2252 /**
2253  * ***************************************************************************************
2254  * subvp_subvp_schedulable: Determine if SubVP + SubVP config is schedulable
2255  *
2256  * High level algorithm:
2257  * 1. Find longest microschedule length (in us) between the two SubVP pipes
2258  * 2. Check if the worst case overlap (VBLANK in middle of ACTIVE) for both
2259  * pipes still allows for the maximum microschedule to fit in the active
2260  * region for both pipes.
2261  *
2262  * @param [in] dc: current dc state
2263  * @param [in] context: new dc state
2264  *
2265  * @return: bool - True if the SubVP + SubVP config is schedulable, false otherwise
2266  *
2267  * ***************************************************************************************
2268  */
2269 static bool subvp_subvp_schedulable(struct dc *dc, struct dc_state *context)
2270 {
2271         struct pipe_ctx *subvp_pipes[2];
2272         struct dc_stream_state *phantom = NULL;
2273         uint32_t microschedule_lines = 0;
2274         uint32_t index = 0;
2275         uint32_t i;
2276         uint32_t max_microschedule_us = 0;
2277         int32_t vactive1_us, vactive2_us, vblank1_us, vblank2_us;
2278
2279         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2280                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2281                 uint32_t time_us = 0;
2282
2283                 /* Loop to calculate the maximum microschedule time between the two SubVP pipes,
2284                  * and also to store the two main SubVP pipe pointers in subvp_pipes[2].
2285                  */
2286                 if (pipe->stream && pipe->plane_state && !pipe->top_pipe &&
2287                                 pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
2288                         phantom = pipe->stream->mall_stream_config.paired_stream;
2289                         microschedule_lines = (phantom->timing.v_total - phantom->timing.v_front_porch) +
2290                                         phantom->timing.v_addressable;
2291
2292                         // Round up when calculating microschedule time
2293                         time_us = ((microschedule_lines * phantom->timing.h_total +
2294                                         phantom->timing.pix_clk_100hz * 100 - 1) /
2295                                         (double)(phantom->timing.pix_clk_100hz * 100)) * 1000000 +
2296                                                 dc->caps.subvp_prefetch_end_to_mall_start_us +
2297                                                 dc->caps.subvp_fw_processing_delay_us;
2298                         if (time_us > max_microschedule_us)
2299                                 max_microschedule_us = time_us;
2300
2301                         subvp_pipes[index] = pipe;
2302                         index++;
2303
2304                         // Maximum 2 SubVP pipes
2305                         if (index == 2)
2306                                 break;
2307                 }
2308         }
2309         vactive1_us = ((subvp_pipes[0]->stream->timing.v_addressable * subvp_pipes[0]->stream->timing.h_total) /
2310                         (double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000;
2311         vactive2_us = ((subvp_pipes[1]->stream->timing.v_addressable * subvp_pipes[1]->stream->timing.h_total) /
2312                                 (double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000;
2313         vblank1_us = (((subvp_pipes[0]->stream->timing.v_total - subvp_pipes[0]->stream->timing.v_addressable) *
2314                         subvp_pipes[0]->stream->timing.h_total) /
2315                         (double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000;
2316         vblank2_us = (((subvp_pipes[1]->stream->timing.v_total - subvp_pipes[1]->stream->timing.v_addressable) *
2317                         subvp_pipes[1]->stream->timing.h_total) /
2318                         (double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000;
2319
2320         if ((vactive1_us - vblank2_us) / 2 > max_microschedule_us &&
2321                         (vactive2_us - vblank1_us) / 2 > max_microschedule_us)
2322                 return true;
2323
2324         return false;
2325 }
2326
2327 /**
2328  * ***************************************************************************************
2329  * subvp_drr_schedulable: Determine if SubVP + DRR config is schedulable
2330  *
2331  * High level algorithm:
2332  * 1. Get timing for SubVP pipe, phantom pipe, and DRR pipe
2333  * 2. Determine the frame time for the DRR display when adding required margin for MCLK switching
2334  * (the margin is equal to the MALL region + DRR margin (500us))
2335  * 3.If (SubVP Active - Prefetch > Stretched DRR frame + max(MALL region, Stretched DRR frame))
2336  * then report the configuration as supported
2337  *
2338  * @param [in] dc: current dc state
2339  * @param [in] context: new dc state
2340  * @param [in] drr_pipe: DRR pipe_ctx for the SubVP + DRR config
2341  *
2342  * @return: bool - True if the SubVP + DRR config is schedulable, false otherwise
2343  *
2344  * ***************************************************************************************
2345  */
2346 static bool subvp_drr_schedulable(struct dc *dc, struct dc_state *context, struct pipe_ctx *drr_pipe)
2347 {
2348         bool schedulable = false;
2349         uint32_t i;
2350         struct pipe_ctx *pipe = NULL;
2351         struct dc_crtc_timing *main_timing = NULL;
2352         struct dc_crtc_timing *phantom_timing = NULL;
2353         struct dc_crtc_timing *drr_timing = NULL;
2354         int16_t prefetch_us = 0;
2355         int16_t mall_region_us = 0;
2356         int16_t drr_frame_us = 0;       // nominal frame time
2357         int16_t subvp_active_us = 0;
2358         int16_t stretched_drr_us = 0;
2359         int16_t drr_stretched_vblank_us = 0;
2360         int16_t max_vblank_mallregion = 0;
2361
2362         // Find SubVP pipe
2363         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2364                 pipe = &context->res_ctx.pipe_ctx[i];
2365
2366                 // We check for master pipe, but it shouldn't matter since we only need
2367                 // the pipe for timing info (stream should be same for any pipe splits)
2368                 if (!pipe->stream || !pipe->plane_state || pipe->top_pipe || pipe->prev_odm_pipe)
2369                         continue;
2370
2371                 // Find the SubVP pipe
2372                 if (pipe->stream->mall_stream_config.type == SUBVP_MAIN)
2373                         break;
2374         }
2375
2376         main_timing = &pipe->stream->timing;
2377         phantom_timing = &pipe->stream->mall_stream_config.paired_stream->timing;
2378         drr_timing = &drr_pipe->stream->timing;
2379         prefetch_us = (phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total /
2380                         (double)(phantom_timing->pix_clk_100hz * 100) * 1000000 +
2381                         dc->caps.subvp_prefetch_end_to_mall_start_us;
2382         subvp_active_us = main_timing->v_addressable * main_timing->h_total /
2383                         (double)(main_timing->pix_clk_100hz * 100) * 1000000;
2384         drr_frame_us = drr_timing->v_total * drr_timing->h_total /
2385                         (double)(drr_timing->pix_clk_100hz * 100) * 1000000;
2386         // P-State allow width and FW delays already included phantom_timing->v_addressable
2387         mall_region_us = phantom_timing->v_addressable * phantom_timing->h_total /
2388                         (double)(phantom_timing->pix_clk_100hz * 100) * 1000000;
2389         stretched_drr_us = drr_frame_us + mall_region_us + SUBVP_DRR_MARGIN_US;
2390         drr_stretched_vblank_us = (drr_timing->v_total - drr_timing->v_addressable) * drr_timing->h_total /
2391                         (double)(drr_timing->pix_clk_100hz * 100) * 1000000 + (stretched_drr_us - drr_frame_us);
2392         max_vblank_mallregion = drr_stretched_vblank_us > mall_region_us ? drr_stretched_vblank_us : mall_region_us;
2393
2394         /* We consider SubVP + DRR schedulable if the stretched frame duration of the DRR display (i.e. the
2395          * highest refresh rate + margin that can support UCLK P-State switch) passes the static analysis
2396          * for VBLANK: (VACTIVE region of the SubVP pipe can fit the MALL prefetch, VBLANK frame time,
2397          * and the max of (VBLANK blanking time, MALL region)).
2398          */
2399         if (stretched_drr_us < (1 / (double)drr_timing->min_refresh_in_uhz) * 1000000 * 1000000 &&
2400                         subvp_active_us - prefetch_us - stretched_drr_us - max_vblank_mallregion > 0)
2401                 schedulable = true;
2402
2403         return schedulable;
2404 }
2405
2406 /**
2407  * ***************************************************************************************
2408  * subvp_vblank_schedulable: Determine if SubVP + VBLANK config is schedulable
2409  *
2410  * High level algorithm:
2411  * 1. Get timing for SubVP pipe, phantom pipe, and VBLANK pipe
2412  * 2. If (SubVP Active - Prefetch > Vblank Frame Time + max(MALL region, Vblank blanking time))
2413  * then report the configuration as supported
2414  * 3. If the VBLANK display is DRR, then take the DRR static schedulability path
2415  *
2416  * @param [in] dc: current dc state
2417  * @param [in] context: new dc state
2418  *
2419  * @return: bool - True if the SubVP + VBLANK/DRR config is schedulable, false otherwise
2420  *
2421  * ***************************************************************************************
2422  */
2423 static bool subvp_vblank_schedulable(struct dc *dc, struct dc_state *context)
2424 {
2425         struct pipe_ctx *pipe = NULL;
2426         struct pipe_ctx *subvp_pipe = NULL;
2427         bool found = false;
2428         bool schedulable = false;
2429         uint32_t i = 0;
2430         uint8_t vblank_index = 0;
2431         int16_t prefetch_us = 0;
2432         int16_t mall_region_us = 0;
2433         int16_t vblank_frame_us = 0;
2434         int16_t subvp_active_us = 0;
2435         int16_t vblank_blank_us = 0;
2436         int16_t max_vblank_mallregion = 0;
2437         struct dc_crtc_timing *main_timing = NULL;
2438         struct dc_crtc_timing *phantom_timing = NULL;
2439         struct dc_crtc_timing *vblank_timing = NULL;
2440
2441         /* For SubVP + VBLANK/DRR cases, we assume there can only be
2442          * a single VBLANK/DRR display. If DML outputs SubVP + VBLANK
2443          * is supported, it is either a single VBLANK case or two VBLANK
2444          * displays which are synchronized (in which case they have identical
2445          * timings).
2446          */
2447         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2448                 pipe = &context->res_ctx.pipe_ctx[i];
2449
2450                 // We check for master pipe, but it shouldn't matter since we only need
2451                 // the pipe for timing info (stream should be same for any pipe splits)
2452                 if (!pipe->stream || !pipe->plane_state || pipe->top_pipe || pipe->prev_odm_pipe)
2453                         continue;
2454
2455                 if (!found && pipe->stream->mall_stream_config.type == SUBVP_NONE) {
2456                         // Found pipe which is not SubVP or Phantom (i.e. the VBLANK pipe).
2457                         vblank_index = i;
2458                         found = true;
2459                 }
2460
2461                 if (!subvp_pipe && pipe->stream->mall_stream_config.type == SUBVP_MAIN)
2462                         subvp_pipe = pipe;
2463         }
2464         // Use ignore_msa_timing_param flag to identify as DRR
2465         if (found && pipe->stream->ignore_msa_timing_param) {
2466                 // SUBVP + DRR case
2467                 schedulable = subvp_drr_schedulable(dc, context, &context->res_ctx.pipe_ctx[vblank_index]);
2468         } else if (found) {
2469                 main_timing = &subvp_pipe->stream->timing;
2470                 phantom_timing = &subvp_pipe->stream->mall_stream_config.paired_stream->timing;
2471                 vblank_timing = &context->res_ctx.pipe_ctx[vblank_index].stream->timing;
2472                 // Prefetch time is equal to VACTIVE + BP + VSYNC of the phantom pipe
2473                 // Also include the prefetch end to mallstart delay time
2474                 prefetch_us = (phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total /
2475                                 (double)(phantom_timing->pix_clk_100hz * 100) * 1000000 +
2476                                 dc->caps.subvp_prefetch_end_to_mall_start_us;
2477                 // P-State allow width and FW delays already included phantom_timing->v_addressable
2478                 mall_region_us = phantom_timing->v_addressable * phantom_timing->h_total /
2479                                 (double)(phantom_timing->pix_clk_100hz * 100) * 1000000;
2480                 vblank_frame_us = vblank_timing->v_total * vblank_timing->h_total /
2481                                 (double)(vblank_timing->pix_clk_100hz * 100) * 1000000;
2482                 vblank_blank_us =  (vblank_timing->v_total - vblank_timing->v_addressable) * vblank_timing->h_total /
2483                                 (double)(vblank_timing->pix_clk_100hz * 100) * 1000000;
2484                 subvp_active_us = main_timing->v_addressable * main_timing->h_total /
2485                                 (double)(main_timing->pix_clk_100hz * 100) * 1000000;
2486                 max_vblank_mallregion = vblank_blank_us > mall_region_us ? vblank_blank_us : mall_region_us;
2487
2488                 // Schedulable if VACTIVE region of the SubVP pipe can fit the MALL prefetch, VBLANK frame time,
2489                 // and the max of (VBLANK blanking time, MALL region)
2490                 // TODO: Possibly add some margin (i.e. the below conditions should be [...] > X instead of [...] > 0)
2491                 if (subvp_active_us - prefetch_us - vblank_frame_us - max_vblank_mallregion > 0)
2492                         schedulable = true;
2493         }
2494         return schedulable;
2495 }
2496
2497 /**
2498  * ********************************************************************************************
2499  * subvp_validate_static_schedulability: Check which SubVP case is calculated and handle
2500  * static analysis based on the case.
2501  *
2502  * Three cases:
2503  * 1. SubVP + SubVP
2504  * 2. SubVP + VBLANK (DRR checked internally)
2505  * 3. SubVP + VACTIVE (currently unsupported)
2506  *
2507  * @param [in] dc: current dc state
2508  * @param [in] context: new dc state
2509  * @param [in] vlevel: Voltage level calculated by DML
2510  *
2511  * @return: bool - True if statically schedulable, false otherwise
2512  *
2513  * ********************************************************************************************
2514  */
2515 static bool subvp_validate_static_schedulability(struct dc *dc,
2516                                 struct dc_state *context,
2517                                 int vlevel)
2518 {
2519         bool schedulable = true;        // true by default for single display case
2520         struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
2521         uint32_t i, pipe_idx;
2522         uint8_t subvp_count = 0;
2523         uint8_t vactive_count = 0;
2524
2525         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2526                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2527
2528                 if (!pipe->stream)
2529                         continue;
2530
2531                 if (pipe->plane_state && !pipe->top_pipe &&
2532                                 pipe->stream->mall_stream_config.type == SUBVP_MAIN)
2533                         subvp_count++;
2534
2535                 // Count how many planes are capable of VACTIVE switching (SubVP + VACTIVE unsupported)
2536                 if (vba->ActiveDRAMClockChangeLatencyMargin[vba->pipe_plane[pipe_idx]] > 0) {
2537                         vactive_count++;
2538                 }
2539                 pipe_idx++;
2540         }
2541
2542         if (subvp_count == 2) {
2543                 // Static schedulability check for SubVP + SubVP case
2544                 schedulable = subvp_subvp_schedulable(dc, context);
2545         } else if (vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_vblank_w_mall_sub_vp) {
2546                 // Static schedulability check for SubVP + VBLANK case. Also handle the case where
2547                 // DML outputs SubVP + VBLANK + VACTIVE (DML will report as SubVP + VBLANK)
2548                 if (vactive_count > 0)
2549                         schedulable = false;
2550                 else
2551                         schedulable = subvp_vblank_schedulable(dc, context);
2552         } else if (vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_vactive_w_mall_sub_vp) {
2553                 // SubVP + VACTIVE currently unsupported
2554                 schedulable = false;
2555         }
2556         return schedulable;
2557 }
2558
2559 static void dcn32_full_validate_bw_helper(struct dc *dc,
2560                 struct dc_state *context,
2561                 display_e2e_pipe_params_st *pipes,
2562                 int *vlevel,
2563                 int *split,
2564                 bool *merge,
2565                 int *pipe_cnt)
2566 {
2567         struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
2568         unsigned int dc_pipe_idx = 0;
2569         bool found_supported_config = false;
2570         struct pipe_ctx *pipe = NULL;
2571         uint32_t non_subvp_pipes = 0;
2572         bool drr_pipe_found = false;
2573         uint32_t drr_pipe_index = 0;
2574         uint32_t i = 0;
2575
2576         /*
2577          * DML favors voltage over p-state, but we're more interested in
2578          * supporting p-state over voltage. We can't support p-state in
2579          * prefetch mode > 0 so try capping the prefetch mode to start.
2580          */
2581         context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final =
2582                         dm_prefetch_support_uclk_fclk_and_stutter;
2583         *vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt);
2584         /* This may adjust vlevel and maxMpcComb */
2585         if (*vlevel < context->bw_ctx.dml.soc.num_states)
2586                 *vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge);
2587
2588         /* Conditions for setting up phantom pipes for SubVP:
2589          * 1. Not force disable SubVP
2590          * 2. Full update (i.e. !fast_validate)
2591          * 3. Enough pipes are available to support SubVP (TODO: Which pipes will use VACTIVE / VBLANK / SUBVP?)
2592          * 4. Display configuration passes validation
2593          * 5. (Config doesn't support MCLK in VACTIVE/VBLANK || dc->debug.force_subvp_mclk_switch)
2594          */
2595         if (!dc->debug.force_disable_subvp &&
2596                         (*vlevel == context->bw_ctx.dml.soc.num_states ||
2597                         vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported ||
2598                         dc->debug.force_subvp_mclk_switch)) {
2599
2600                 while (!found_supported_config && dcn32_enough_pipes_for_subvp(dc, context) &&
2601                                 dcn32_assign_subvp_pipe(dc, context, &dc_pipe_idx)) {
2602
2603                         dc->res_pool->funcs->add_phantom_pipes(dc, context, pipes, *pipe_cnt, dc_pipe_idx);
2604
2605                         *pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, false);
2606                         *vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt);
2607
2608                         if (*vlevel < context->bw_ctx.dml.soc.num_states &&
2609                                         vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] != dm_dram_clock_change_unsupported
2610                                         && subvp_validate_static_schedulability(dc, context, *vlevel)) {
2611                                 found_supported_config = true;
2612                         } else if (*vlevel < context->bw_ctx.dml.soc.num_states &&
2613                                         vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported) {
2614                                 /* Case where 1 SubVP is added, and DML reports MCLK unsupported. This handles
2615                                  * the case for SubVP + DRR, where the DRR display does not support MCLK switch
2616                                  * at it's native refresh rate / timing.
2617                                  */
2618                                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2619                                         pipe = &context->res_ctx.pipe_ctx[i];
2620                                         if (pipe->stream && pipe->plane_state && !pipe->top_pipe &&
2621                                                         pipe->stream->mall_stream_config.type == SUBVP_NONE) {
2622                                                 non_subvp_pipes++;
2623                                                 // Use ignore_msa_timing_param flag to identify as DRR
2624                                                 if (pipe->stream->ignore_msa_timing_param) {
2625                                                         drr_pipe_found = true;
2626                                                         drr_pipe_index = i;
2627                                                 }
2628                                         }
2629                                 }
2630                                 // If there is only 1 remaining non SubVP pipe that is DRR, check static
2631                                 // schedulability for SubVP + DRR.
2632                                 if (non_subvp_pipes == 1 && drr_pipe_found) {
2633                                         found_supported_config = subvp_drr_schedulable(dc,
2634                                                         context, &context->res_ctx.pipe_ctx[drr_pipe_index]);
2635                                 }
2636                         }
2637                 }
2638
2639                 // If SubVP pipe config is unsupported (or cannot be used for UCLK switching)
2640                 // remove phantom pipes and repopulate dml pipes
2641                 if (!found_supported_config) {
2642                         dc->res_pool->funcs->remove_phantom_pipes(dc, context);
2643                         *pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, false);
2644                 } else {
2645                         // only call dcn20_validate_apply_pipe_split_flags if we found a supported config
2646                         memset(split, 0, MAX_PIPES * sizeof(int));
2647                         memset(merge, 0, MAX_PIPES * sizeof(bool));
2648                         *vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge);
2649
2650                         // If found a supported SubVP config, phantom pipes were added to the context.
2651                         // Program timing for the phantom pipes.
2652                         dc->hwss.apply_ctx_to_hw(dc, context);
2653                 }
2654         }
2655 }
2656
2657 static bool dcn32_internal_validate_bw(
2658                 struct dc *dc,
2659                 struct dc_state *context,
2660                 display_e2e_pipe_params_st *pipes,
2661                 int *pipe_cnt_out,
2662                 int *vlevel_out,
2663                 bool fast_validate)
2664 {
2665         bool out = false;
2666         bool repopulate_pipes = false;
2667         int split[MAX_PIPES] = { 0 };
2668         bool merge[MAX_PIPES] = { false };
2669         bool newly_split[MAX_PIPES] = { false };
2670         int pipe_cnt, i, pipe_idx, vlevel;
2671         struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
2672
2673         ASSERT(pipes);
2674         if (!pipes)
2675                 return false;
2676
2677         // For each full update, remove all existing phantom pipes first
2678         dc->res_pool->funcs->remove_phantom_pipes(dc, context);
2679
2680         dc->res_pool->funcs->update_soc_for_wm_a(dc, context);
2681
2682         pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
2683
2684         if (!pipe_cnt) {
2685                 out = true;
2686                 goto validate_out;
2687         }
2688
2689         dml_log_pipe_params(&context->bw_ctx.dml, pipes, pipe_cnt);
2690
2691         if (!fast_validate) {
2692                 dcn32_full_validate_bw_helper(dc, context, pipes, &vlevel, split, merge, &pipe_cnt);
2693         }
2694
2695         if (fast_validate || vlevel == context->bw_ctx.dml.soc.num_states ||
2696                         vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported) {
2697                 /*
2698                  * If mode is unsupported or there's still no p-state support then
2699                  * fall back to favoring voltage.
2700                  *
2701                  * We don't actually support prefetch mode 2, so require that we
2702                  * at least support prefetch mode 1.
2703                  */
2704                 context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final =
2705                                 dm_prefetch_support_stutter;
2706
2707                 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
2708                 if (vlevel < context->bw_ctx.dml.soc.num_states) {
2709                         memset(split, 0, MAX_PIPES * sizeof(int));
2710                         memset(merge, 0, MAX_PIPES * sizeof(bool));
2711                         vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
2712                 }
2713         }
2714
2715         dml_log_mode_support_params(&context->bw_ctx.dml);
2716
2717         if (vlevel == context->bw_ctx.dml.soc.num_states)
2718                 goto validate_fail;
2719
2720         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2721                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2722                 struct pipe_ctx *mpo_pipe = pipe->bottom_pipe;
2723
2724                 if (!pipe->stream)
2725                         continue;
2726
2727                 /* We only support full screen mpo with ODM */
2728                 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled
2729                                 && pipe->plane_state && mpo_pipe
2730                                 && memcmp(&mpo_pipe->plane_res.scl_data.recout,
2731                                                 &pipe->plane_res.scl_data.recout,
2732                                                 sizeof(struct rect)) != 0) {
2733                         ASSERT(mpo_pipe->plane_state != pipe->plane_state);
2734                         goto validate_fail;
2735                 }
2736                 pipe_idx++;
2737         }
2738
2739         /* merge pipes if necessary */
2740         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2741                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2742
2743                 /*skip pipes that don't need merging*/
2744                 if (!merge[i])
2745                         continue;
2746
2747                 /* if ODM merge we ignore mpc tree, mpo pipes will have their own flags */
2748                 if (pipe->prev_odm_pipe) {
2749                         /*split off odm pipe*/
2750                         pipe->prev_odm_pipe->next_odm_pipe = pipe->next_odm_pipe;
2751                         if (pipe->next_odm_pipe)
2752                                 pipe->next_odm_pipe->prev_odm_pipe = pipe->prev_odm_pipe;
2753
2754                         pipe->bottom_pipe = NULL;
2755                         pipe->next_odm_pipe = NULL;
2756                         pipe->plane_state = NULL;
2757                         pipe->stream = NULL;
2758                         pipe->top_pipe = NULL;
2759                         pipe->prev_odm_pipe = NULL;
2760                         if (pipe->stream_res.dsc)
2761                                 dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc);
2762                         memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));
2763                         memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));
2764                         repopulate_pipes = true;
2765                 } else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) {
2766                         struct pipe_ctx *top_pipe = pipe->top_pipe;
2767                         struct pipe_ctx *bottom_pipe = pipe->bottom_pipe;
2768
2769                         top_pipe->bottom_pipe = bottom_pipe;
2770                         if (bottom_pipe)
2771                                 bottom_pipe->top_pipe = top_pipe;
2772
2773                         pipe->top_pipe = NULL;
2774                         pipe->bottom_pipe = NULL;
2775                         pipe->plane_state = NULL;
2776                         pipe->stream = NULL;
2777                         memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));
2778                         memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));
2779                         repopulate_pipes = true;
2780                 } else
2781                         ASSERT(0); /* Should never try to merge master pipe */
2782
2783         }
2784
2785         for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
2786                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2787                 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
2788                 struct pipe_ctx *hsplit_pipe = NULL;
2789                 bool odm;
2790                 int old_index = -1;
2791
2792                 if (!pipe->stream || newly_split[i])
2793                         continue;
2794
2795                 pipe_idx++;
2796                 odm = vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled;
2797
2798                 if (!pipe->plane_state && !odm)
2799                         continue;
2800
2801                 if (split[i]) {
2802                         if (odm) {
2803                                 if (split[i] == 4 && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe)
2804                                         old_index = old_pipe->next_odm_pipe->next_odm_pipe->pipe_idx;
2805                                 else if (old_pipe->next_odm_pipe)
2806                                         old_index = old_pipe->next_odm_pipe->pipe_idx;
2807                         } else {
2808                                 if (split[i] == 4 && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe &&
2809                                                 old_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
2810                                         old_index = old_pipe->bottom_pipe->bottom_pipe->pipe_idx;
2811                                 else if (old_pipe->bottom_pipe &&
2812                                                 old_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
2813                                         old_index = old_pipe->bottom_pipe->pipe_idx;
2814                         }
2815                         hsplit_pipe = dcn32_find_split_pipe(dc, context, old_index);
2816                         ASSERT(hsplit_pipe);
2817                         if (!hsplit_pipe)
2818                                 goto validate_fail;
2819
2820                         if (!dcn32_split_stream_for_mpc_or_odm(
2821                                         dc, &context->res_ctx,
2822                                         pipe, hsplit_pipe, odm))
2823                                 goto validate_fail;
2824
2825                         newly_split[hsplit_pipe->pipe_idx] = true;
2826                         repopulate_pipes = true;
2827                 }
2828                 if (split[i] == 4) {
2829                         struct pipe_ctx *pipe_4to1;
2830
2831                         if (odm && old_pipe->next_odm_pipe)
2832                                 old_index = old_pipe->next_odm_pipe->pipe_idx;
2833                         else if (!odm && old_pipe->bottom_pipe &&
2834                                                 old_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
2835                                 old_index = old_pipe->bottom_pipe->pipe_idx;
2836                         else
2837                                 old_index = -1;
2838                         pipe_4to1 = dcn32_find_split_pipe(dc, context, old_index);
2839                         ASSERT(pipe_4to1);
2840                         if (!pipe_4to1)
2841                                 goto validate_fail;
2842                         if (!dcn32_split_stream_for_mpc_or_odm(
2843                                         dc, &context->res_ctx,
2844                                         pipe, pipe_4to1, odm))
2845                                 goto validate_fail;
2846                         newly_split[pipe_4to1->pipe_idx] = true;
2847
2848                         if (odm && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe
2849                                         && old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe)
2850                                 old_index = old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe->pipe_idx;
2851                         else if (!odm && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe &&
2852                                         old_pipe->bottom_pipe->bottom_pipe->bottom_pipe &&
2853                                         old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
2854                                 old_index = old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->pipe_idx;
2855                         else
2856                                 old_index = -1;
2857                         pipe_4to1 = dcn32_find_split_pipe(dc, context, old_index);
2858                         ASSERT(pipe_4to1);
2859                         if (!pipe_4to1)
2860                                 goto validate_fail;
2861                         if (!dcn32_split_stream_for_mpc_or_odm(
2862                                         dc, &context->res_ctx,
2863                                         hsplit_pipe, pipe_4to1, odm))
2864                                 goto validate_fail;
2865                         newly_split[pipe_4to1->pipe_idx] = true;
2866                 }
2867                 if (odm)
2868                         dcn20_build_mapped_resource(dc, context, pipe->stream);
2869         }
2870
2871         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2872                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2873
2874                 if (pipe->plane_state) {
2875                         if (!resource_build_scaling_params(pipe))
2876                                 goto validate_fail;
2877                 }
2878         }
2879
2880         /* Actual dsc count per stream dsc validation*/
2881         if (!dcn20_validate_dsc(dc, context)) {
2882                 vba->ValidationStatus[vba->soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE;
2883                 goto validate_fail;
2884         }
2885
2886         if (repopulate_pipes)
2887                 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
2888         *vlevel_out = vlevel;
2889         *pipe_cnt_out = pipe_cnt;
2890
2891         out = true;
2892         goto validate_out;
2893
2894 validate_fail:
2895         out = false;
2896
2897 validate_out:
2898         return out;
2899 }
2900
2901 bool dcn32_validate_bandwidth(struct dc *dc,
2902                 struct dc_state *context,
2903                 bool fast_validate)
2904 {
2905         bool out = false;
2906
2907         BW_VAL_TRACE_SETUP();
2908
2909         int vlevel = 0;
2910         int pipe_cnt = 0;
2911         display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
2912         DC_LOGGER_INIT(dc->ctx->logger);
2913
2914         BW_VAL_TRACE_COUNT();
2915
2916     DC_FP_START();
2917         out = dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate);
2918     DC_FP_END();
2919
2920         if (pipe_cnt == 0)
2921                 goto validate_out;
2922
2923         if (!out)
2924                 goto validate_fail;
2925
2926         BW_VAL_TRACE_END_VOLTAGE_LEVEL();
2927
2928         if (fast_validate) {
2929                 BW_VAL_TRACE_SKIP(fast);
2930                 goto validate_out;
2931         }
2932
2933         dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);
2934
2935         BW_VAL_TRACE_END_WATERMARKS();
2936
2937         goto validate_out;
2938
2939 validate_fail:
2940         DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
2941                 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
2942
2943         BW_VAL_TRACE_SKIP(fail);
2944         out = false;
2945
2946 validate_out:
2947         kfree(pipes);
2948
2949         BW_VAL_TRACE_FINISH();
2950
2951         return out;
2952 }
2953
2954
2955 static bool is_dual_plane(enum surface_pixel_format format)
2956 {
2957         return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA;
2958 }
2959
2960 int dcn32_populate_dml_pipes_from_context(
2961         struct dc *dc, struct dc_state *context,
2962         display_e2e_pipe_params_st *pipes,
2963         bool fast_validate)
2964 {
2965         int i, pipe_cnt;
2966         struct resource_context *res_ctx = &context->res_ctx;
2967         struct pipe_ctx *pipe;
2968
2969         dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
2970
2971         for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
2972                 struct dc_crtc_timing *timing;
2973
2974                 if (!res_ctx->pipe_ctx[i].stream)
2975                         continue;
2976                 pipe = &res_ctx->pipe_ctx[i];
2977                 timing = &pipe->stream->timing;
2978
2979                 pipes[pipe_cnt].pipe.src.gpuvm = true;
2980                 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0;
2981                 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0;
2982                 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;
2983                 pipes[pipe_cnt].pipe.src.gpuvm_min_page_size_kbytes = 256; // according to spreadsheet
2984                 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
2985                 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_19;
2986
2987                 switch (pipe->stream->mall_stream_config.type) {
2988                 case SUBVP_MAIN:
2989                         pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_sub_viewport;
2990                         break;
2991                 case SUBVP_PHANTOM:
2992                         pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_phantom_pipe;
2993                         pipes[pipe_cnt].pipe.src.use_mall_for_static_screen = dm_use_mall_static_screen_enable;
2994                         break;
2995                 case SUBVP_NONE:
2996                         pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_disable;
2997                         pipes[pipe_cnt].pipe.src.use_mall_for_static_screen = dm_use_mall_static_screen_disable;
2998                         break;
2999                 default:
3000                         break;
3001                 }
3002
3003                 pipes[pipe_cnt].dout.dsc_input_bpc = 0;
3004                 if (pipes[pipe_cnt].dout.dsc_enable) {
3005                         switch (timing->display_color_depth) {
3006                         case COLOR_DEPTH_888:
3007                                 pipes[pipe_cnt].dout.dsc_input_bpc = 8;
3008                                 break;
3009                         case COLOR_DEPTH_101010:
3010                                 pipes[pipe_cnt].dout.dsc_input_bpc = 10;
3011                                 break;
3012                         case COLOR_DEPTH_121212:
3013                                 pipes[pipe_cnt].dout.dsc_input_bpc = 12;
3014                                 break;
3015                         default:
3016                                 ASSERT(0);
3017                                 break;
3018                         }
3019                 }
3020                 pipe_cnt++;
3021         }
3022
3023         switch (pipe_cnt) {
3024         case 1:
3025                 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_2_MAX_DET_SIZE;
3026                 if (pipe->plane_state && !dc->debug.disable_z9_mpc) {
3027                         if (!is_dual_plane(pipe->plane_state->format)) {
3028                                 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_2_DEFAULT_DET_SIZE;
3029                                 pipes[0].pipe.src.unbounded_req_mode = true;
3030                                 if (pipe->plane_state->src_rect.width >= 5120 &&
3031                                         pipe->plane_state->src_rect.height >= 2880)
3032                                         context->bw_ctx.dml.ip.det_buffer_size_kbytes = 320; // 5K or higher
3033                         }
3034                 }
3035                 break;
3036         case 2:
3037                 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_2_MAX_DET_SIZE / 2; // 576 KB (9 segments)
3038                 break;
3039         case 3:
3040                 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_2_MAX_DET_SIZE / 3; // 384 KB (6 segments)
3041                 break;
3042         case 4:
3043         default:
3044                 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_2_DEFAULT_DET_SIZE; // 256 KB (4 segments)
3045                 break;
3046         }
3047
3048         return pipe_cnt;
3049 }
3050
3051 void dcn32_calculate_wm_and_dlg_fp(
3052                 struct dc *dc, struct dc_state *context,
3053                 display_e2e_pipe_params_st *pipes,
3054                 int pipe_cnt,
3055                 int vlevel)
3056 {
3057         int i, pipe_idx, vlevel_temp = 0;
3058
3059         double dcfclk = dcn3_2_soc.clock_limits[0].dcfclk_mhz;
3060         double dcfclk_from_validation = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
3061         unsigned int min_dram_speed_mts = context->bw_ctx.dml.vba.DRAMSpeed;
3062         bool pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] !=
3063                         dm_dram_clock_change_unsupported;
3064
3065         /* Set B:
3066          * For Set B calculations use clocks from clock_limits[2] when available i.e. when SMU is present,
3067          * otherwise use arbitrary low value from spreadsheet for DCFCLK as lower is safer for watermark
3068          * calculations to cover bootup clocks.
3069          * DCFCLK: soc.clock_limits[2] when available
3070          * UCLK: soc.clock_limits[2] when available
3071          */
3072         if (dcn3_2_soc.num_states > 2) {
3073                 vlevel_temp = 2;
3074                 dcfclk = dcn3_2_soc.clock_limits[2].dcfclk_mhz;
3075         } else
3076                 dcfclk = 615; //DCFCLK Vmin_lv
3077
3078         pipes[0].clks_cfg.voltage = vlevel_temp;
3079         pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
3080         pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel_temp].socclk_mhz;
3081
3082         if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) {
3083                 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us;
3084                 context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.fclk_change_latency_us;
3085                 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us;
3086                 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us;
3087         }
3088         context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3089         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3090         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3091         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3092         context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3093         context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3094         context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3095         context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3096         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3097         context->bw_ctx.bw.dcn.watermarks.b.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3098
3099         /* Set D:
3100          * All clocks min.
3101          * DCFCLK: Min, as reported by PM FW when available
3102          * UCLK  : Min, as reported by PM FW when available
3103          * sr_enter_exit/sr_exit should be lower than used for DRAM (TBD after bringup or later, use as decided in Clk Mgr)
3104          */
3105
3106         if (dcn3_2_soc.num_states > 2) {
3107                 vlevel_temp = 0;
3108                 dcfclk = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz;
3109         } else
3110                 dcfclk = 615; //DCFCLK Vmin_lv
3111
3112         pipes[0].clks_cfg.voltage = vlevel_temp;
3113         pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
3114         pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel_temp].socclk_mhz;
3115
3116         if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].valid) {
3117                 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us;
3118                 context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.fclk_change_latency_us;
3119                 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us;
3120                 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us;
3121         }
3122         context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3123         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3124         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3125         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3126         context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3127         context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3128         context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3129         context->bw_ctx.bw.dcn.watermarks.d.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3130         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3131         context->bw_ctx.bw.dcn.watermarks.d.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3132
3133         /* Set C, for Dummy P-State:
3134          * All clocks min.
3135          * DCFCLK: Min, as reported by PM FW, when available
3136          * UCLK  : Min,  as reported by PM FW, when available
3137          * pstate latency as per UCLK state dummy pstate latency
3138          */
3139
3140         if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) {
3141                 unsigned int min_dram_speed_mts_margin = 160;
3142
3143                 if ((!pstate_en))
3144                         min_dram_speed_mts = dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz * 16;
3145
3146                 /* find largest table entry that is lower than dram speed, but lower than DPM0 still uses DPM0 */
3147                 for (i = 3; i > 0; i--)
3148                         if (min_dram_speed_mts + min_dram_speed_mts_margin > dc->clk_mgr->bw_params->dummy_pstate_table[i].dram_speed_mts)
3149                                 break;
3150
3151                 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->dummy_pstate_table[i].dummy_pstate_latency_us;
3152                 context->bw_ctx.dml.soc.dummy_pstate_latency_us = dc->clk_mgr->bw_params->dummy_pstate_table[i].dummy_pstate_latency_us;
3153                 context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.fclk_change_latency_us;
3154                 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us;
3155                 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us;
3156         }
3157         context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3158         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3159         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3160         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3161         context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3162         context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3163         context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3164         context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3165         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3166         context->bw_ctx.bw.dcn.watermarks.c.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3167
3168         if ((!pstate_en) && (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid)) {
3169                 /* The only difference between A and C is p-state latency, if p-state is not supported
3170                  * with full p-state latency we want to calculate DLG based on dummy p-state latency,
3171                  * Set A p-state watermark set to 0 on DCN32, when p-state unsupported, for now keep as DCN32.
3172                  */
3173                 context->bw_ctx.bw.dcn.watermarks.a = context->bw_ctx.bw.dcn.watermarks.c;
3174                 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 0;
3175         } else {
3176                 /* Set A:
3177                  * All clocks min.
3178                  * DCFCLK: Min, as reported by PM FW, when available
3179                  * UCLK: Min, as reported by PM FW, when available
3180                  */
3181                 dc->res_pool->funcs->update_soc_for_wm_a(dc, context);
3182                 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3183                 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3184                 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3185                 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3186                 context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3187                 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3188                 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3189                 context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3190                 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3191                 context->bw_ctx.bw.dcn.watermarks.a.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3192         }
3193
3194         pipes[0].clks_cfg.voltage = vlevel;
3195         pipes[0].clks_cfg.dcfclk_mhz = dcfclk_from_validation;
3196         pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
3197
3198         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
3199                 if (!context->res_ctx.pipe_ctx[i].stream)
3200                         continue;
3201
3202                 pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt);
3203                 pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
3204
3205                 if (dc->config.forced_clocks) {
3206                         pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
3207                         pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
3208                 }
3209                 if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000)
3210                         pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
3211                 if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
3212                         pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
3213
3214                 pipe_idx++;
3215         }
3216
3217         context->perf_params.stutter_period_us = context->bw_ctx.dml.vba.StutterPeriod;
3218
3219         dcn32_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
3220
3221         if (!pstate_en)
3222                 /* Restore full p-state latency */
3223                 context->bw_ctx.dml.soc.dram_clock_change_latency_us =
3224                                 dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
3225 }
3226
3227 static struct dc_cap_funcs cap_funcs = {
3228         .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
3229 };
3230
3231
3232 static void dcn32_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts,
3233                 unsigned int *optimal_dcfclk,
3234                 unsigned int *optimal_fclk)
3235 {
3236         double bw_from_dram, bw_from_dram1, bw_from_dram2;
3237
3238         bw_from_dram1 = uclk_mts * dcn3_2_soc.num_chans *
3239                 dcn3_2_soc.dram_channel_width_bytes * (dcn3_2_soc.max_avg_dram_bw_use_normal_percent / 100);
3240         bw_from_dram2 = uclk_mts * dcn3_2_soc.num_chans *
3241                 dcn3_2_soc.dram_channel_width_bytes * (dcn3_2_soc.max_avg_sdp_bw_use_normal_percent / 100);
3242
3243         bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2;
3244
3245         if (optimal_fclk)
3246                 *optimal_fclk = bw_from_dram /
3247                 (dcn3_2_soc.fabric_datapath_to_dcn_data_return_bytes * (dcn3_2_soc.max_avg_sdp_bw_use_normal_percent / 100));
3248
3249         if (optimal_dcfclk)
3250                 *optimal_dcfclk =  bw_from_dram /
3251                 (dcn3_2_soc.return_bus_width_bytes * (dcn3_2_soc.max_avg_sdp_bw_use_normal_percent / 100));
3252 }
3253
3254 void dcn32_calculate_wm_and_dlg(
3255                 struct dc *dc, struct dc_state *context,
3256                 display_e2e_pipe_params_st *pipes,
3257                 int pipe_cnt,
3258                 int vlevel)
3259 {
3260     DC_FP_START();
3261     dcn32_calculate_wm_and_dlg_fp(
3262                 dc, context,
3263                 pipes,
3264                 pipe_cnt,
3265                 vlevel);
3266     DC_FP_END();
3267 }
3268
3269 static bool is_dtbclk_required(struct dc *dc, struct dc_state *context)
3270 {
3271         int i;
3272
3273         for (i = 0; i < dc->res_pool->pipe_count; i++) {
3274                 if (!context->res_ctx.pipe_ctx[i].stream)
3275                         continue;
3276                 if (is_dp_128b_132b_signal(&context->res_ctx.pipe_ctx[i]))
3277                         return true;
3278         }
3279         return false;
3280 }
3281
3282 void dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes,
3283                 int pipe_cnt, int vlevel)
3284 {
3285         int i, pipe_idx;
3286         bool usr_retraining_support = false;
3287
3288         /* Writeback MCIF_WB arbitration parameters */
3289         dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt);
3290
3291         context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000;
3292         context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000;
3293         context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000;
3294         context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16;
3295         context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000;
3296         context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000;
3297         context->bw_ctx.bw.dcn.clk.p_state_change_support =
3298                         context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]
3299                                         != dm_dram_clock_change_unsupported;
3300
3301         /*
3302          * TODO: needs FAMS
3303          * Pstate change might not be supported by hardware, but it might be
3304          * possible with firmware driven vertical blank stretching.
3305          */
3306         // context->bw_ctx.bw.dcn.clk.p_state_change_support |= context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching;
3307         context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
3308         context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context);
3309         if (context->bw_ctx.dml.vba.FCLKChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] == dm_fclock_change_unsupported)
3310                 context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = false;
3311         else
3312                 context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = true;
3313
3314         usr_retraining_support = context->bw_ctx.dml.vba.USRRetrainingSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
3315         ASSERT(usr_retraining_support);
3316
3317         if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz)
3318                 context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz;
3319
3320         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
3321                 if (!context->res_ctx.pipe_ctx[i].stream)
3322                         continue;
3323                 pipes[pipe_idx].pipe.dest.vstartup_start = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt,
3324                                 pipe_idx);
3325                 pipes[pipe_idx].pipe.dest.vupdate_offset = get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt,
3326                                 pipe_idx);
3327                 pipes[pipe_idx].pipe.dest.vupdate_width = get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt,
3328                                 pipe_idx);
3329                 pipes[pipe_idx].pipe.dest.vready_offset = get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt,
3330                                 pipe_idx);
3331                 if (context->res_ctx.pipe_ctx[i].stream->mall_stream_config.type == SUBVP_PHANTOM) {
3332                         // Phantom pipe requires that DET_SIZE = 0 and no unbounded requests
3333                         context->res_ctx.pipe_ctx[i].det_buffer_size_kb = 0;
3334                         context->res_ctx.pipe_ctx[i].unbounded_req = false;
3335                 } else {
3336                         context->res_ctx.pipe_ctx[i].det_buffer_size_kb =
3337                                         context->bw_ctx.dml.ip.det_buffer_size_kbytes;
3338                         context->res_ctx.pipe_ctx[i].unbounded_req = pipes[pipe_idx].pipe.src.unbounded_req_mode;
3339                 }
3340                 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
3341                         context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
3342                 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
3343                 context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;
3344                 pipe_idx++;
3345         }
3346         /*save a original dppclock copy*/
3347         context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz;
3348         context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz;
3349         context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz
3350                         * 1000;
3351         context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz
3352                         * 1000;
3353
3354         context->bw_ctx.bw.dcn.compbuf_size_kb = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes
3355                         - context->bw_ctx.dml.ip.det_buffer_size_kbytes * pipe_idx;
3356
3357         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
3358
3359                 if (!context->res_ctx.pipe_ctx[i].stream)
3360                         continue;
3361
3362                 context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg_v2(&context->bw_ctx.dml,
3363                                 &context->res_ctx.pipe_ctx[i].dlg_regs, &context->res_ctx.pipe_ctx[i].ttu_regs, pipes,
3364                                 pipe_cnt, pipe_idx);
3365
3366                 context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg_v2(&context->res_ctx.pipe_ctx[i].rq_regs,
3367                                 &context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
3368
3369                 pipe_idx++;
3370         }
3371 }
3372
3373 /* dcn32_update_bw_bounding_box
3374  * This would override some dcn3_2 ip_or_soc initial parameters hardcoded from spreadsheet
3375  * with actual values as per dGPU SKU:
3376  * -with passed few options from dc->config
3377  * -with dentist_vco_frequency from Clk Mgr (currently hardcoded, but might need to get it from PM FW)
3378  * -with passed latency values (passed in ns units) in dc-> bb override for debugging purposes
3379  * -with passed latencies from VBIOS (in 100_ns units) if available for certain dGPU SKU
3380  * -with number of DRAM channels from VBIOS (which differ for certain dGPU SKU of the same ASIC)
3381  * -clocks levels with passed clk_table entries from Clk Mgr as reported by PM FW for different
3382  *  clocks (which might differ for certain dGPU SKU of the same ASIC)
3383  */
3384 static void dcn32_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
3385 {
3386         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
3387
3388                 /* Overrides from dc->config options */
3389                 dcn3_2_ip.clamp_min_dcfclk = dc->config.clamp_min_dcfclk;
3390
3391                 /* Override from passed dc->bb_overrides if available*/
3392                 if ((int)(dcn3_2_soc.sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns
3393                                 && dc->bb_overrides.sr_exit_time_ns) {
3394                         dcn3_2_soc.sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;
3395                 }
3396
3397                 if ((int)(dcn3_2_soc.sr_enter_plus_exit_time_us * 1000)
3398                                 != dc->bb_overrides.sr_enter_plus_exit_time_ns
3399                                 && dc->bb_overrides.sr_enter_plus_exit_time_ns) {
3400                         dcn3_2_soc.sr_enter_plus_exit_time_us =
3401                                 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
3402                 }
3403
3404                 if ((int)(dcn3_2_soc.urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns
3405                         && dc->bb_overrides.urgent_latency_ns) {
3406                         dcn3_2_soc.urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
3407                 }
3408
3409                 if ((int)(dcn3_2_soc.dram_clock_change_latency_us * 1000)
3410                                 != dc->bb_overrides.dram_clock_change_latency_ns
3411                                 && dc->bb_overrides.dram_clock_change_latency_ns) {
3412                         dcn3_2_soc.dram_clock_change_latency_us =
3413                                 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
3414                 }
3415
3416                 if ((int)(dcn3_2_soc.dummy_pstate_latency_us * 1000)
3417                                 != dc->bb_overrides.dummy_clock_change_latency_ns
3418                                 && dc->bb_overrides.dummy_clock_change_latency_ns) {
3419                         dcn3_2_soc.dummy_pstate_latency_us =
3420                                 dc->bb_overrides.dummy_clock_change_latency_ns / 1000.0;
3421                 }
3422
3423                 /* Override from VBIOS if VBIOS bb_info available */
3424                 if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {
3425                         struct bp_soc_bb_info bb_info = {0};
3426
3427                         if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {
3428                                 if (bb_info.dram_clock_change_latency_100ns > 0)
3429                                         dcn3_2_soc.dram_clock_change_latency_us = bb_info.dram_clock_change_latency_100ns * 10;
3430
3431                         if (bb_info.dram_sr_enter_exit_latency_100ns > 0)
3432                                 dcn3_2_soc.sr_enter_plus_exit_time_us = bb_info.dram_sr_enter_exit_latency_100ns * 10;
3433
3434                         if (bb_info.dram_sr_exit_latency_100ns > 0)
3435                                 dcn3_2_soc.sr_exit_time_us = bb_info.dram_sr_exit_latency_100ns * 10;
3436                         }
3437                 }
3438
3439                 /* Override from VBIOS for num_chan */
3440                 if (dc->ctx->dc_bios->vram_info.num_chans)
3441                         dcn3_2_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans;
3442
3443                 if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes)
3444                         dcn3_2_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes;
3445
3446         }
3447
3448         /* Override dispclk_dppclk_vco_speed_mhz from Clk Mgr */
3449         dcn3_2_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
3450         dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
3451
3452         /* Overrides Clock levelsfrom CLK Mgr table entries as reported by PM FW */
3453         if ((!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) && (bw_params->clk_table.entries[0].memclk_mhz)) {
3454                 unsigned int i = 0, j = 0, num_states = 0;
3455
3456                 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0};
3457                 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0};
3458                 unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0};
3459                 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0};
3460
3461                 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {615, 906, 1324, 1564};
3462                 unsigned int num_dcfclk_sta_targets = 4, num_uclk_states = 0;
3463                 unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0;
3464
3465                 for (i = 0; i < MAX_NUM_DPM_LVL; i++) {
3466                         if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz)
3467                                 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
3468                         if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz)
3469                                 max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
3470                         if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz)
3471                                 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
3472                         if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz)
3473                                 max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
3474                 }
3475                 if (!max_dcfclk_mhz)
3476                         max_dcfclk_mhz = dcn3_2_soc.clock_limits[0].dcfclk_mhz;
3477                 if (!max_dispclk_mhz)
3478                         max_dispclk_mhz = dcn3_2_soc.clock_limits[0].dispclk_mhz;
3479                 if (!max_dppclk_mhz)
3480                         max_dppclk_mhz = dcn3_2_soc.clock_limits[0].dppclk_mhz;
3481                 if (!max_phyclk_mhz)
3482                         max_phyclk_mhz = dcn3_2_soc.clock_limits[0].phyclk_mhz;
3483
3484                 if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
3485                         // If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array
3486                         dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz;
3487                         num_dcfclk_sta_targets++;
3488                 } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
3489                         // If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates
3490                         for (i = 0; i < num_dcfclk_sta_targets; i++) {
3491                                 if (dcfclk_sta_targets[i] > max_dcfclk_mhz) {
3492                                         dcfclk_sta_targets[i] = max_dcfclk_mhz;
3493                                         break;
3494                                 }
3495                         }
3496                         // Update size of array since we "removed" duplicates
3497                         num_dcfclk_sta_targets = i + 1;
3498                 }
3499
3500                 num_uclk_states = bw_params->clk_table.num_entries;
3501
3502                 // Calculate optimal dcfclk for each uclk
3503                 for (i = 0; i < num_uclk_states; i++) {
3504                         dcn32_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16,
3505                                         &optimal_dcfclk_for_uclk[i], NULL);
3506                         if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) {
3507                                 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz;
3508                         }
3509                 }
3510
3511                 // Calculate optimal uclk for each dcfclk sta target
3512                 for (i = 0; i < num_dcfclk_sta_targets; i++) {
3513                         for (j = 0; j < num_uclk_states; j++) {
3514                                 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {
3515                                         optimal_uclk_for_dcfclk_sta_targets[i] =
3516                                                         bw_params->clk_table.entries[j].memclk_mhz * 16;
3517                                         break;
3518                                 }
3519                         }
3520                 }
3521
3522                 i = 0;
3523                 j = 0;
3524                 // create the final dcfclk and uclk table
3525                 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) {
3526                         if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) {
3527                                 dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
3528                                 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
3529                         } else {
3530                                 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
3531                                         dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
3532                                         dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
3533                                 } else {
3534                                         j = num_uclk_states;
3535                                 }
3536                         }
3537                 }
3538
3539                 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) {
3540                         dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
3541                         dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
3542                 }
3543
3544                 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES &&
3545                                 optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
3546                         dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
3547                         dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
3548                 }
3549
3550                 dcn3_2_soc.num_states = num_states;
3551                 for (i = 0; i < dcn3_2_soc.num_states; i++) {
3552                         dcn3_2_soc.clock_limits[i].state = i;
3553                         dcn3_2_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i];
3554                         dcn3_2_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i];
3555
3556                         /* Fill all states with max values of all these clocks */
3557                         dcn3_2_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz;
3558                         dcn3_2_soc.clock_limits[i].dppclk_mhz  = max_dppclk_mhz;
3559                         dcn3_2_soc.clock_limits[i].phyclk_mhz  = max_phyclk_mhz;
3560                         dcn3_2_soc.clock_limits[i].dscclk_mhz  = max_dispclk_mhz / 3;
3561
3562                         /* Populate from bw_params for DTBCLK, SOCCLK */
3563                         if (!bw_params->clk_table.entries[i].dtbclk_mhz && i > 0)
3564                                 dcn3_2_soc.clock_limits[i].dtbclk_mhz  = dcn3_2_soc.clock_limits[i-1].dtbclk_mhz;
3565                         else
3566                                 dcn3_2_soc.clock_limits[i].dtbclk_mhz  = bw_params->clk_table.entries[i].dtbclk_mhz;
3567
3568                         if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0)
3569                                 dcn3_2_soc.clock_limits[i].socclk_mhz = dcn3_2_soc.clock_limits[i-1].socclk_mhz;
3570                         else
3571                                 dcn3_2_soc.clock_limits[i].socclk_mhz = bw_params->clk_table.entries[i].socclk_mhz;
3572
3573                         if (!dram_speed_mts[i] && i > 0)
3574                                 dcn3_2_soc.clock_limits[i].dram_speed_mts = dcn3_2_soc.clock_limits[i-1].dram_speed_mts;
3575                         else
3576                                 dcn3_2_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i];
3577
3578                         /* These clocks cannot come from bw_params, always fill from dcn3_2_soc[0] */
3579                         /* PHYCLK_D18, PHYCLK_D32 */
3580                         dcn3_2_soc.clock_limits[i].phyclk_d18_mhz = dcn3_2_soc.clock_limits[0].phyclk_d18_mhz;
3581                         dcn3_2_soc.clock_limits[i].phyclk_d32_mhz = dcn3_2_soc.clock_limits[0].phyclk_d32_mhz;
3582                 }
3583
3584                 /* Re-init DML with updated bb */
3585                 dml_init_instance(&dc->dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32);
3586                 if (dc->current_state)
3587                         dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32);
3588         }
3589 }
3590
3591 static struct resource_funcs dcn32_res_pool_funcs = {
3592         .destroy = dcn32_destroy_resource_pool,
3593         .link_enc_create = dcn32_link_encoder_create,
3594         .link_enc_create_minimal = NULL,
3595         .panel_cntl_create = dcn32_panel_cntl_create,
3596         .validate_bandwidth = dcn32_validate_bandwidth,
3597         .calculate_wm_and_dlg = dcn32_calculate_wm_and_dlg,
3598         .populate_dml_pipes = dcn32_populate_dml_pipes_from_context,
3599         .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
3600         .add_stream_to_ctx = dcn30_add_stream_to_ctx,
3601         .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
3602         .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
3603         .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
3604         .set_mcif_arb_params = dcn30_set_mcif_arb_params,
3605         .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
3606         .acquire_post_bldn_3dlut = dcn32_acquire_post_bldn_3dlut,
3607         .release_post_bldn_3dlut = dcn32_release_post_bldn_3dlut,
3608         .update_bw_bounding_box = dcn32_update_bw_bounding_box,
3609         .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
3610         .update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
3611         .add_phantom_pipes = dcn32_add_phantom_pipes,
3612         .remove_phantom_pipes = dcn32_remove_phantom_pipes,
3613 };
3614
3615
3616 static bool dcn32_resource_construct(
3617         uint8_t num_virtual_links,
3618         struct dc *dc,
3619         struct dcn32_resource_pool *pool)
3620 {
3621         int i, j;
3622         struct dc_context *ctx = dc->ctx;
3623         struct irq_service_init_data init_data;
3624         struct ddc_service_init_data ddc_init_data = {0};
3625         uint32_t pipe_fuses = 0;
3626         uint32_t num_pipes  = 4;
3627
3628     DC_FP_START();
3629
3630         ctx->dc_bios->regs = &bios_regs;
3631
3632         pool->base.res_cap = &res_cap_dcn32;
3633         /* max number of pipes for ASIC before checking for pipe fuses */
3634         num_pipes  = pool->base.res_cap->num_timing_generator;
3635         pipe_fuses = REG_READ(CC_DC_PIPE_DIS);
3636
3637         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++)
3638                 if (pipe_fuses & 1 << i)
3639                         num_pipes--;
3640
3641         if (pipe_fuses & 1)
3642                 ASSERT(0); //Unexpected - Pipe 0 should always be fully functional!
3643
3644         if (pipe_fuses & CC_DC_PIPE_DIS__DC_FULL_DIS_MASK)
3645                 ASSERT(0); //Entire DCN is harvested!
3646
3647         /* within dml lib, initial value is hard coded, if ASIC pipe is fused, the
3648          * value will be changed, update max_num_dpp and max_num_otg for dml.
3649          */
3650         dcn3_2_ip.max_num_dpp = num_pipes;
3651         dcn3_2_ip.max_num_otg = num_pipes;
3652
3653         pool->base.funcs = &dcn32_res_pool_funcs;
3654
3655         /*************************************************
3656          *  Resource + asic cap harcoding                *
3657          *************************************************/
3658         pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
3659         pool->base.timing_generator_count = num_pipes;
3660         pool->base.pipe_count = num_pipes;
3661         pool->base.mpcc_count = num_pipes;
3662         dc->caps.max_downscale_ratio = 600;
3663         dc->caps.i2c_speed_in_khz = 100;
3664         dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/
3665         dc->caps.max_cursor_size = 256;
3666         dc->caps.min_horizontal_blanking_period = 80;
3667         dc->caps.dmdata_alloc_size = 2048;
3668         dc->caps.mall_size_per_mem_channel = 0;
3669         dc->caps.mall_size_total = 0;
3670         dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
3671
3672         dc->caps.cache_line_size = 64;
3673         dc->caps.cache_num_ways = 16;
3674         dc->caps.max_cab_allocation_bytes = 67108864; // 64MB = 1024 * 1024 * 64
3675         dc->caps.subvp_fw_processing_delay_us = 15;
3676         dc->caps.subvp_prefetch_end_to_mall_start_us = 15;
3677         dc->caps.subvp_pstate_allow_width_us = 20;
3678         dc->caps.subvp_vertical_int_margin_us = 30;
3679
3680         dc->caps.max_slave_planes = 2;
3681         dc->caps.max_slave_yuv_planes = 2;
3682         dc->caps.max_slave_rgb_planes = 2;
3683         dc->caps.post_blend_color_processing = true;
3684         dc->caps.force_dp_tps4_for_cp2520 = true;
3685         dc->caps.dp_hpo = true;
3686         dc->caps.edp_dsc_support = true;
3687         dc->caps.extended_aux_timeout_support = true;
3688         dc->caps.dmcub_support = true;
3689
3690         /* Color pipeline capabilities */
3691         dc->caps.color.dpp.dcn_arch = 1;
3692         dc->caps.color.dpp.input_lut_shared = 0;
3693         dc->caps.color.dpp.icsc = 1;
3694         dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
3695         dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
3696         dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
3697         dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
3698         dc->caps.color.dpp.dgam_rom_caps.pq = 1;
3699         dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
3700         dc->caps.color.dpp.post_csc = 1;
3701         dc->caps.color.dpp.gamma_corr = 1;
3702         dc->caps.color.dpp.dgam_rom_for_yuv = 0;
3703
3704         dc->caps.color.dpp.hw_3d_lut = 1;
3705         dc->caps.color.dpp.ogam_ram = 0;  //Blnd Gam also removed
3706         // no OGAM ROM on DCN2 and later ASICs
3707         dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
3708         dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
3709         dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
3710         dc->caps.color.dpp.ogam_rom_caps.pq = 0;
3711         dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
3712         dc->caps.color.dpp.ocsc = 0;
3713
3714         dc->caps.color.mpc.gamut_remap = 1;
3715         dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC
3716         dc->caps.color.mpc.ogam_ram = 1;
3717         dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
3718         dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
3719         dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
3720         dc->caps.color.mpc.ogam_rom_caps.pq = 0;
3721         dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
3722         dc->caps.color.mpc.ocsc = 1;
3723
3724         /* Use pipe context based otg sync logic */
3725         dc->config.use_pipe_ctx_sync_logic = true;
3726
3727         /* read VBIOS LTTPR caps */
3728         {
3729                 if (ctx->dc_bios->funcs->get_lttpr_caps) {
3730                         enum bp_result bp_query_result;
3731                         uint8_t is_vbios_lttpr_enable = 0;
3732
3733                         bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
3734                         dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
3735                 }
3736
3737                 /* interop bit is implicit */
3738                 {
3739                         dc->caps.vbios_lttpr_aware = true;
3740                 }
3741         }
3742
3743         if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
3744                 dc->debug = debug_defaults_drv;
3745         else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
3746                 dc->debug = debug_defaults_diags;
3747         } else
3748                 dc->debug = debug_defaults_diags;
3749         // Init the vm_helper
3750         if (dc->vm_helper)
3751                 vm_helper_init(dc->vm_helper, 16);
3752
3753         /*************************************************
3754          *  Create resources                             *
3755          *************************************************/
3756
3757         /* Clock Sources for Pixel Clock*/
3758         pool->base.clock_sources[DCN32_CLK_SRC_PLL0] =
3759                         dcn32_clock_source_create(ctx, ctx->dc_bios,
3760                                 CLOCK_SOURCE_COMBO_PHY_PLL0,
3761                                 &clk_src_regs[0], false);
3762         pool->base.clock_sources[DCN32_CLK_SRC_PLL1] =
3763                         dcn32_clock_source_create(ctx, ctx->dc_bios,
3764                                 CLOCK_SOURCE_COMBO_PHY_PLL1,
3765                                 &clk_src_regs[1], false);
3766         pool->base.clock_sources[DCN32_CLK_SRC_PLL2] =
3767                         dcn32_clock_source_create(ctx, ctx->dc_bios,
3768                                 CLOCK_SOURCE_COMBO_PHY_PLL2,
3769                                 &clk_src_regs[2], false);
3770         pool->base.clock_sources[DCN32_CLK_SRC_PLL3] =
3771                         dcn32_clock_source_create(ctx, ctx->dc_bios,
3772                                 CLOCK_SOURCE_COMBO_PHY_PLL3,
3773                                 &clk_src_regs[3], false);
3774         pool->base.clock_sources[DCN32_CLK_SRC_PLL4] =
3775                         dcn32_clock_source_create(ctx, ctx->dc_bios,
3776                                 CLOCK_SOURCE_COMBO_PHY_PLL4,
3777                                 &clk_src_regs[4], false);
3778
3779         pool->base.clk_src_count = DCN32_CLK_SRC_TOTAL;
3780
3781         /* todo: not reuse phy_pll registers */
3782         pool->base.dp_clock_source =
3783                         dcn32_clock_source_create(ctx, ctx->dc_bios,
3784                                 CLOCK_SOURCE_ID_DP_DTO,
3785                                 &clk_src_regs[0], true);
3786
3787         for (i = 0; i < pool->base.clk_src_count; i++) {
3788                 if (pool->base.clock_sources[i] == NULL) {
3789                         dm_error("DC: failed to create clock sources!\n");
3790                         BREAK_TO_DEBUGGER();
3791                         goto create_fail;
3792                 }
3793         }
3794
3795         /* DCCG */
3796         pool->base.dccg = dccg32_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
3797         if (pool->base.dccg == NULL) {
3798                 dm_error("DC: failed to create dccg!\n");
3799                 BREAK_TO_DEBUGGER();
3800                 goto create_fail;
3801         }
3802
3803         /* DML */
3804         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
3805                 dml_init_instance(&dc->dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32);
3806
3807         /* IRQ Service */
3808         init_data.ctx = dc->ctx;
3809         pool->base.irqs = dal_irq_service_dcn32_create(&init_data);
3810         if (!pool->base.irqs)
3811                 goto create_fail;
3812
3813         /* HUBBUB */
3814         pool->base.hubbub = dcn32_hubbub_create(ctx);
3815         if (pool->base.hubbub == NULL) {
3816                 BREAK_TO_DEBUGGER();
3817                 dm_error("DC: failed to create hubbub!\n");
3818                 goto create_fail;
3819         }
3820
3821         /* HUBPs, DPPs, OPPs, TGs, ABMs */
3822         for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) {
3823
3824                 /* if pipe is disabled, skip instance of HW pipe,
3825                  * i.e, skip ASIC register instance
3826                  */
3827                 if (pipe_fuses & 1 << i)
3828                         continue;
3829
3830                 /* HUBPs */
3831                 pool->base.hubps[j] = dcn32_hubp_create(ctx, i);
3832                 if (pool->base.hubps[j] == NULL) {
3833                         BREAK_TO_DEBUGGER();
3834                         dm_error(
3835                                 "DC: failed to create hubps!\n");
3836                         goto create_fail;
3837                 }
3838
3839                 /* DPPs */
3840                 pool->base.dpps[j] = dcn32_dpp_create(ctx, i);
3841                 if (pool->base.dpps[j] == NULL) {
3842                         BREAK_TO_DEBUGGER();
3843                         dm_error(
3844                                 "DC: failed to create dpps!\n");
3845                         goto create_fail;
3846                 }
3847
3848                 /* OPPs */
3849                 pool->base.opps[j] = dcn32_opp_create(ctx, i);
3850                 if (pool->base.opps[j] == NULL) {
3851                         BREAK_TO_DEBUGGER();
3852                         dm_error(
3853                                 "DC: failed to create output pixel processor!\n");
3854                         goto create_fail;
3855                 }
3856
3857                 /* TGs */
3858                 pool->base.timing_generators[j] = dcn32_timing_generator_create(
3859                                 ctx, i);
3860                 if (pool->base.timing_generators[j] == NULL) {
3861                         BREAK_TO_DEBUGGER();
3862                         dm_error("DC: failed to create tg!\n");
3863                         goto create_fail;
3864                 }
3865
3866                 /* ABMs */
3867                 pool->base.multiple_abms[j] = dmub_abm_create(ctx,
3868                                 &abm_regs[i],
3869                                 &abm_shift,
3870                                 &abm_mask);
3871                 if (pool->base.multiple_abms[j] == NULL) {
3872                         dm_error("DC: failed to create abm for pipe %d!\n", i);
3873                         BREAK_TO_DEBUGGER();
3874                         goto create_fail;
3875                 }
3876
3877                 /* index for resource pool arrays for next valid pipe */
3878                 j++;
3879         }
3880
3881         /* PSR */
3882         pool->base.psr = dmub_psr_create(ctx);
3883         if (pool->base.psr == NULL) {
3884                 dm_error("DC: failed to create psr obj!\n");
3885                 BREAK_TO_DEBUGGER();
3886                 goto create_fail;
3887         }
3888
3889         /* MPCCs */
3890         pool->base.mpc = dcn32_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_cap->num_mpc_3dlut);
3891         if (pool->base.mpc == NULL) {
3892                 BREAK_TO_DEBUGGER();
3893                 dm_error("DC: failed to create mpc!\n");
3894                 goto create_fail;
3895         }
3896
3897         /* DSCs */
3898         for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
3899                 pool->base.dscs[i] = dcn32_dsc_create(ctx, i);
3900                 if (pool->base.dscs[i] == NULL) {
3901                         BREAK_TO_DEBUGGER();
3902                         dm_error("DC: failed to create display stream compressor %d!\n", i);
3903                         goto create_fail;
3904                 }
3905         }
3906
3907         /* DWB */
3908         if (!dcn32_dwbc_create(ctx, &pool->base)) {
3909                 BREAK_TO_DEBUGGER();
3910                 dm_error("DC: failed to create dwbc!\n");
3911                 goto create_fail;
3912         }
3913
3914         /* MMHUBBUB */
3915         if (!dcn32_mmhubbub_create(ctx, &pool->base)) {
3916                 BREAK_TO_DEBUGGER();
3917                 dm_error("DC: failed to create mcif_wb!\n");
3918                 goto create_fail;
3919         }
3920
3921         /* AUX and I2C */
3922         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
3923                 pool->base.engines[i] = dcn32_aux_engine_create(ctx, i);
3924                 if (pool->base.engines[i] == NULL) {
3925                         BREAK_TO_DEBUGGER();
3926                         dm_error(
3927                                 "DC:failed to create aux engine!!\n");
3928                         goto create_fail;
3929                 }
3930                 pool->base.hw_i2cs[i] = dcn32_i2c_hw_create(ctx, i);
3931                 if (pool->base.hw_i2cs[i] == NULL) {
3932                         BREAK_TO_DEBUGGER();
3933                         dm_error(
3934                                 "DC:failed to create hw i2c!!\n");
3935                         goto create_fail;
3936                 }
3937                 pool->base.sw_i2cs[i] = NULL;
3938         }
3939
3940         /* Audio, HWSeq, Stream Encoders including HPO and virtual, MPC 3D LUTs */
3941         if (!resource_construct(num_virtual_links, dc, &pool->base,
3942                         (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
3943                         &res_create_funcs : &res_create_maximus_funcs)))
3944                         goto create_fail;
3945
3946         /* HW Sequencer init functions and Plane caps */
3947         dcn32_hw_sequencer_init_functions(dc);
3948
3949         dc->caps.max_planes =  pool->base.pipe_count;
3950
3951         for (i = 0; i < dc->caps.max_planes; ++i)
3952                 dc->caps.planes[i] = plane_cap;
3953
3954         dc->cap_funcs = cap_funcs;
3955
3956         if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
3957                 ddc_init_data.ctx = dc->ctx;
3958                 ddc_init_data.link = NULL;
3959                 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
3960                 ddc_init_data.id.enum_id = 0;
3961                 ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
3962                 pool->base.oem_device = dal_ddc_service_create(&ddc_init_data);
3963         } else {
3964                 pool->base.oem_device = NULL;
3965         }
3966
3967     DC_FP_END();
3968
3969         return true;
3970
3971 create_fail:
3972
3973     DC_FP_END();
3974
3975         dcn32_resource_destruct(pool);
3976
3977         return false;
3978 }
3979
3980 struct resource_pool *dcn32_create_resource_pool(
3981                 const struct dc_init_data *init_data,
3982                 struct dc *dc)
3983 {
3984         struct dcn32_resource_pool *pool =
3985                 kzalloc(sizeof(struct dcn32_resource_pool), GFP_KERNEL);
3986
3987         if (!pool)
3988                 return NULL;
3989
3990         if (dcn32_resource_construct(init_data->num_virtual_links, dc, pool))
3991                 return &pool->base;
3992
3993         BREAK_TO_DEBUGGER();
3994         kfree(pool);
3995         return NULL;
3996 }