drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26
  27 #include "dm_services.h"
  28 #include "dm_helpers.h"
  29 #include "core_types.h"
  30 #include "resource.h"
  31 #include "dccg.h"
  32 #include "dce/dce_hwseq.h"
  33 #include "dcn30/dcn30_cm_common.h"
  34 #include "reg_helper.h"
  35 #include "abm.h"
  36 #include "hubp.h"
  37 #include "dchubbub.h"
  38 #include "timing_generator.h"
  39 #include "opp.h"
  40 #include "ipp.h"
  41 #include "mpc.h"
  42 #include "mcif_wb.h"
  43 #include "dc_dmub_srv.h"
  44 #include "link_hwss.h"
  45 #include "dpcd_defs.h"
  46 #include "dcn32_hwseq.h"
  47 #include "clk_mgr.h"
  48 #include "dsc.h"
  49 #include "dcn20/dcn20_optc.h"
  50 #include "dmub_subvp_state.h"
  51 #include "dce/dmub_hw_lock_mgr.h"
  52 #include "dc_link_dp.h"
  53 #include "dmub/inc/dmub_subvp_state.h"
  54
  55 #define DC_LOGGER_INIT(logger)
  56
  57 #define CTX \
  58         hws->ctx
  59 #define REG(reg)\
  60         hws->regs->reg
  61 #define DC_LOGGER \
  62                 dc->ctx->logger
  63
  64
  65 #undef FN
  66 #define FN(reg_name, field_name) \
  67         hws->shifts->field_name, hws->masks->field_name
  68
  69 void dcn32_dsc_pg_control(
  70                 struct dce_hwseq *hws,
  71                 unsigned int dsc_inst,
  72                 bool power_on)
  73 {
  74         uint32_t power_gate = power_on ? 0 : 1;
  75         uint32_t pwr_status = power_on ? 0 : 2;
  76         uint32_t org_ip_request_cntl = 0;
  77
  78         if (hws->ctx->dc->debug.disable_dsc_power_gate)
  79                 return;
  80
  81         REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
  82         if (org_ip_request_cntl == 0)
  83                 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
  84
  85         switch (dsc_inst) {
  86         case 0: /* DSC0 */
  87                 REG_UPDATE(DOMAIN16_PG_CONFIG,
  88                                 DOMAIN_POWER_GATE, power_gate);
  89
  90                 REG_WAIT(DOMAIN16_PG_STATUS,
  91                                 DOMAIN_PGFSM_PWR_STATUS, pwr_status,
  92                                 1, 1000);
  93                 break;
  94         case 1: /* DSC1 */
  95                 REG_UPDATE(DOMAIN17_PG_CONFIG,
  96                                 DOMAIN_POWER_GATE, power_gate);
  97
  98                 REG_WAIT(DOMAIN17_PG_STATUS,
  99                                 DOMAIN_PGFSM_PWR_STATUS, pwr_status,
 100                                 1, 1000);
 101                 break;
 102         case 2: /* DSC2 */
 103                 REG_UPDATE(DOMAIN18_PG_CONFIG,
 104                                 DOMAIN_POWER_GATE, power_gate);
 105
 106                 REG_WAIT(DOMAIN18_PG_STATUS,
 107                                 DOMAIN_PGFSM_PWR_STATUS, pwr_status,
 108                                 1, 1000);
 109                 break;
 110         case 3: /* DSC3 */
 111                 REG_UPDATE(DOMAIN19_PG_CONFIG,
 112                                 DOMAIN_POWER_GATE, power_gate);
 113
 114                 REG_WAIT(DOMAIN19_PG_STATUS,
 115                                 DOMAIN_PGFSM_PWR_STATUS, pwr_status,
 116                                 1, 1000);
 117                 break;
 118         default:
 119                 BREAK_TO_DEBUGGER();
 120                 break;
 121         }
 122
 123         if (org_ip_request_cntl == 0)
 124                 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
 125 }
 126
 127
 128 void dcn32_enable_power_gating_plane(
 129         struct dce_hwseq *hws,
 130         bool enable)
 131 {
 132         bool force_on = true; /* disable power gating */
 133
 134         if (enable)
 135                 force_on = false;
 136
 137         /* DCHUBP0/1/2/3 */
 138         REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
 139         REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
 140         REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
 141         REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
 142
 143         /* DCS0/1/2/3 */
 144         REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
 145         REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
 146         REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
 147         REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
 148 }
 149
 150 void dcn32_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on)
 151 {
 152         uint32_t power_gate = power_on ? 0 : 1;
 153         uint32_t pwr_status = power_on ? 0 : 2;
 154
 155         if (hws->ctx->dc->debug.disable_hubp_power_gate)
 156                 return;
 157
 158         if (REG(DOMAIN0_PG_CONFIG) == 0)
 159                 return;
 160
 161         switch (hubp_inst) {
 162         case 0:
 163                 REG_SET(DOMAIN0_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
 164                 REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
 165                 break;
 166         case 1:
 167                 REG_SET(DOMAIN1_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
 168                 REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
 169                 break;
 170         case 2:
 171                 REG_SET(DOMAIN2_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
 172                 REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
 173                 break;
 174         case 3:
 175                 REG_SET(DOMAIN3_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
 176                 REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
 177                 break;
 178         default:
 179                 BREAK_TO_DEBUGGER();
 180                 break;
 181         }
 182 }
 183
 184 static bool dcn32_check_no_memory_request_for_cab(struct dc *dc)
 185 {
 186         int i;
 187
 188     /* First, check no-memory-request case */
 189         for (i = 0; i < dc->current_state->stream_count; i++) {
 190                 if (dc->current_state->stream_status[i].plane_count)
 191                         /* Fail eligibility on a visible stream */
 192                         break;
 193         }
 194
 195         if (i == dc->current_state->stream_count)
 196                 return true;
 197
 198         return false;
 199 }
 200
 201 /* This function takes in the start address and surface size to be cached in CAB
 202  * and calculates the total number of cache lines required to store the surface.
 203  * The number of cache lines used for each surface is calculated independently of
 204  * one another. For example, if there is a primary surface(1), meta surface(2), and
 205  * cursor(3), this function should be called 3 times to calculate the number of cache
 206  * lines used for each of those surfaces.
 207  */
 208 static uint32_t dcn32_cache_lines_for_surface(struct dc *dc, uint32_t surface_size, uint64_t start_address)
 209 {
 210         uint32_t lines_used = 1;
 211         uint32_t num_cached_bytes = 0;
 212         uint32_t remaining_size = 0;
 213         uint32_t cache_line_size = dc->caps.cache_line_size;
 214         uint32_t remainder = 0;
 215
 216         /* 1. Calculate surface size minus the number of bytes stored
 217          * in the first cache line (all bytes in first cache line might
 218          * not be fully used).
 219          */
 220         div_u64_rem(start_address, cache_line_size, &remainder);
 221         num_cached_bytes = cache_line_size - remainder;
 222         remaining_size = surface_size - num_cached_bytes;
 223
 224         /* 2. Calculate number of cache lines that will be fully used with
 225          * the remaining number of bytes to be stored.
 226          */
 227         lines_used += (remaining_size / cache_line_size);
 228
 229         /* 3. Check if we need an extra line due to the remaining size not being
 230          * a multiple of CACHE_LINE_SIZE.
 231          */
 232         if (remaining_size % cache_line_size > 0)
 233                 lines_used++;
 234
 235         return lines_used;
 236 }
 237
 238 /* This function loops through every surface that needs to be cached in CAB for SS,
 239  * and calculates the total number of ways required to store all surfaces (primary,
 240  * meta, cursor).
 241  */
 242 static uint32_t dcn32_calculate_cab_allocation(struct dc *dc, struct dc_state *ctx)
 243 {
 244         uint8_t i, j;
 245         struct dc_stream_state *stream = NULL;
 246         struct dc_plane_state *plane = NULL;
 247         uint32_t surface_size = 0;
 248         uint32_t cursor_size = 0;
 249         uint32_t cache_lines_used = 0;
 250         uint32_t total_lines = 0;
 251         uint32_t lines_per_way = 0;
 252         uint32_t num_ways = 0;
 253
 254         for (i = 0; i < ctx->stream_count; i++) {
 255                 stream = ctx->streams[i];
 256
 257                 // Don't include PSR surface in the total surface size for CAB allocation
 258                 if (stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED)
 259                         continue;
 260
 261                 if (ctx->stream_status[i].plane_count == 0)
 262                         continue;
 263
 264                 // For each stream, loop through each plane to calculate the number of cache
 265                 // lines required to store the surface in CAB
 266                 for (j = 0; j < ctx->stream_status[i].plane_count; j++) {
 267                         plane = ctx->stream_status[i].plane_states[j];
 268
 269                         // Calculate total surface size
 270                         surface_size = plane->plane_size.surface_pitch *
 271                                         plane->plane_size.surface_size.height *
 272                                         (plane->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ? 8 : 4);
 273
 274                         // Convert surface size + starting address to number of cache lines required
 275                         // (alignment accounted for)
 276                         cache_lines_used += dcn32_cache_lines_for_surface(dc, surface_size,
 277                                         plane->address.grph.addr.quad_part);
 278
 279                         if (plane->address.grph.meta_addr.quad_part) {
 280                                 // Meta surface
 281                                 cache_lines_used += dcn32_cache_lines_for_surface(dc, surface_size,
 282                                                 plane->address.grph.meta_addr.quad_part);
 283                         }
 284                 }
 285
 286                 // Include cursor size for CAB allocation
 287                 if (stream->cursor_position.enable && plane->address.grph.cursor_cache_addr.quad_part) {
 288                         cursor_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size;
 289                         switch (stream->cursor_attributes.color_format) {
 290                         case CURSOR_MODE_MONO:
 291                                 cursor_size /= 2;
 292                                 break;
 293                         case CURSOR_MODE_COLOR_1BIT_AND:
 294                         case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:
 295                         case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:
 296                                 cursor_size *= 4;
 297                                 break;
 298
 299                         case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED:
 300                         case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED:
 301                                 cursor_size *= 8;
 302                                 break;
 303                         }
 304                         cache_lines_used += dcn32_cache_lines_for_surface(dc, surface_size,
 305                                         plane->address.grph.cursor_cache_addr.quad_part);
 306                 }
 307         }
 308
 309         // Convert number of cache lines required to number of ways
 310         total_lines = dc->caps.max_cab_allocation_bytes / dc->caps.cache_line_size;
 311         lines_per_way = total_lines / dc->caps.cache_num_ways;
 312         num_ways = cache_lines_used / lines_per_way;
 313
 314         if (cache_lines_used % lines_per_way > 0)
 315                 num_ways++;
 316
 317         return num_ways;
 318 }
 319
 320 bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable)
 321 {
 322         union dmub_rb_cmd cmd;
 323         uint8_t ways;
 324
 325         if (!dc->ctx->dmub_srv)
 326                 return false;
 327
 328         if (enable) {
 329                 if (dc->current_state) {
 330
 331                         /* 1. Check no memory request case for CAB.
 332                          * If no memory request case, send CAB_ACTION NO_DF_REQ DMUB message
 333                          */
 334                         if (dcn32_check_no_memory_request_for_cab(dc)) {
 335                                 /* Enable no-memory-requests case */
 336                                 memset(&cmd, 0, sizeof(cmd));
 337                                 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS;
 338                                 cmd.cab.header.sub_type = DMUB_CMD__CAB_NO_DCN_REQ;
 339                                 cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header);
 340
 341                                 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
 342                                 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
 343
 344                                 return true;
 345                         }
 346
 347                         /* 2. Check if all surfaces can fit in CAB.
 348                          * If surfaces can fit into CAB, send CAB_ACTION_ALLOW DMUB message
 349                          * and configure HUBP's to fetch from MALL
 350                          */
 351                         ways = dcn32_calculate_cab_allocation(dc, dc->current_state);
 352                         if (ways <= dc->caps.cache_num_ways) {
 353                                 memset(&cmd, 0, sizeof(cmd));
 354                                 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS;
 355                                 cmd.cab.header.sub_type = DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB;
 356                                 cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header);
 357                                 cmd.cab.cab_alloc_ways = ways;
 358
 359                                 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
 360                                 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
 361
 362                                 return true;
 363                         }
 364
 365                 }
 366                 return false;
 367         }
 368
 369         /* Disable CAB */
 370         memset(&cmd, 0, sizeof(cmd));
 371         cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS;
 372         cmd.cab.header.sub_type = DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION;
 373         cmd.cab.header.payload_bytes =
 374                         sizeof(cmd.cab) - sizeof(cmd.cab.header);
 375
 376         dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
 377         dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
 378         dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);
 379
 380         return true;
 381 }
 382
 383 /* Send DMCUB message with SubVP pipe info
 384  * - For each pipe in context, populate payload with required SubVP information
 385  *   if the pipe is using SubVP for MCLK switch
 386  * - This function must be called while the DMUB HW lock is acquired by driver
 387  */
 388 void dcn32_commit_subvp_config(struct dc *dc, struct dc_state *context)
 389 {
 390 /*
 391         int i;
 392         bool enable_subvp = false;
 393
 394         if (!dc->ctx || !dc->ctx->dmub_srv)
 395                 return;
 396
 397         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 398                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
 399
 400                 if (pipe_ctx->stream && pipe_ctx->stream->mall_stream_config.paired_stream &&
 401                                 pipe_ctx->stream->mall_stream_config.type == SUBVP_MAIN) {
 402                         // There is at least 1 SubVP pipe, so enable SubVP
 403                         enable_subvp = true;
 404                         break;
 405                 }
 406         }
 407         dc_dmub_setup_subvp_dmub_command(dc, context, enable_subvp);
 408 */
 409 }
 410
 411 /* Sub-Viewport DMUB lock needs to be acquired by driver whenever SubVP is active and:
 412  * 1. Any full update for any SubVP main pipe
 413  * 2. Any immediate flip for any SubVP pipe
 414  * 3. Any flip for DRR pipe
 415  * 4. If SubVP was previously in use (i.e. in old context)
 416  */
 417 void dcn32_subvp_pipe_control_lock(struct dc *dc,
 418                 struct dc_state *context,
 419                 bool lock,
 420                 bool should_lock_all_pipes,
 421                 struct pipe_ctx *top_pipe_to_program,
 422                 bool subvp_prev_use)
 423 {
 424         unsigned int i = 0;
 425         bool subvp_immediate_flip = false;
 426         bool subvp_in_use = false;
 427         struct pipe_ctx *pipe;
 428
 429         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 430                 pipe = &context->res_ctx.pipe_ctx[i];
 431
 432                 if (pipe->stream && pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
 433                         subvp_in_use = true;
 434                         break;
 435                 }
 436         }
 437
 438         if (top_pipe_to_program && top_pipe_to_program->stream && top_pipe_to_program->plane_state) {
 439                 if (top_pipe_to_program->stream->mall_stream_config.type == SUBVP_MAIN &&
 440                                 top_pipe_to_program->plane_state->flip_immediate)
 441                         subvp_immediate_flip = true;
 442         }
 443
 444         // Don't need to lock for DRR VSYNC flips -- FW will wait for DRR pending update cleared.
 445         if ((subvp_in_use && (should_lock_all_pipes || subvp_immediate_flip)) || (!subvp_in_use && subvp_prev_use)) {
 446                 union dmub_inbox0_cmd_lock_hw hw_lock_cmd = { 0 };
 447
 448                 if (!lock) {
 449                         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 450                                 pipe = &context->res_ctx.pipe_ctx[i];
 451                                 if (pipe->stream && pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_MAIN &&
 452                                                 should_lock_all_pipes)
 453                                         pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VBLANK);
 454                         }
 455                 }
 456
 457                 hw_lock_cmd.bits.command_code = DMUB_INBOX0_CMD__HW_LOCK;
 458                 hw_lock_cmd.bits.hw_lock_client = HW_LOCK_CLIENT_DRIVER;
 459                 hw_lock_cmd.bits.lock = lock;
 460                 hw_lock_cmd.bits.should_release = !lock;
 461                 dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd);
 462         }
 463 }
 464
 465
 466 static bool dcn32_set_mpc_shaper_3dlut(
 467         struct pipe_ctx *pipe_ctx, const struct dc_stream_state *stream)
 468 {
 469         struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
 470         int mpcc_id = pipe_ctx->plane_res.hubp->inst;
 471         struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
 472         bool result = false;
 473
 474         const struct pwl_params *shaper_lut = NULL;
 475         //get the shaper lut params
 476         if (stream->func_shaper) {
 477                 if (stream->func_shaper->type == TF_TYPE_HWPWL)
 478                         shaper_lut = &stream->func_shaper->pwl;
 479                 else if (stream->func_shaper->type == TF_TYPE_DISTRIBUTED_POINTS) {
 480                         cm_helper_translate_curve_to_hw_format(
 481                                         stream->func_shaper,
 482                                         &dpp_base->shaper_params, true);
 483                         shaper_lut = &dpp_base->shaper_params;
 484                 }
 485         }
 486
 487         if (stream->lut3d_func &&
 488                 stream->lut3d_func->state.bits.initialized == 1) {
 489
 490                 result = mpc->funcs->program_3dlut(mpc,
 491                                                                 &stream->lut3d_func->lut_3d,
 492                                                                 mpcc_id);
 493
 494                 result = mpc->funcs->program_shaper(mpc,
 495                                                                 shaper_lut,
 496                                                                 mpcc_id);
 497         }
 498
 499         return result;
 500 }
 501
 502 bool dcn32_set_mcm_luts(
 503         struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
 504 {
 505         struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
 506         int mpcc_id = pipe_ctx->plane_res.hubp->inst;
 507         struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
 508         bool result = true;
 509         struct pwl_params *lut_params = NULL;
 510
 511         // 1D LUT
 512         if (plane_state->blend_tf) {
 513                 if (plane_state->blend_tf->type == TF_TYPE_HWPWL)
 514                         lut_params = &plane_state->blend_tf->pwl;
 515                 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) {
 516                         cm_helper_translate_curve_to_hw_format(
 517                                         plane_state->blend_tf,
 518                                         &dpp_base->regamma_params, false);
 519                         lut_params = &dpp_base->regamma_params;
 520                 }
 521         }
 522         result = mpc->funcs->program_1dlut(mpc, lut_params, mpcc_id);
 523
 524         // Shaper
 525         if (plane_state->in_shaper_func) {
 526                 if (plane_state->in_shaper_func->type == TF_TYPE_HWPWL)
 527                         lut_params = &plane_state->in_shaper_func->pwl;
 528                 else if (plane_state->in_shaper_func->type == TF_TYPE_DISTRIBUTED_POINTS) {
 529                         // TODO: dpp_base replace
 530                         ASSERT(false);
 531                         cm_helper_translate_curve_to_hw_format(
 532                                         plane_state->in_shaper_func,
 533                                         &dpp_base->shaper_params, true);
 534                         lut_params = &dpp_base->shaper_params;
 535                 }
 536         }
 537
 538         result = mpc->funcs->program_shaper(mpc, lut_params, mpcc_id);
 539
 540         // 3D
 541         if (plane_state->lut3d_func && plane_state->lut3d_func->state.bits.initialized == 1)
 542                 result = mpc->funcs->program_3dlut(mpc, &plane_state->lut3d_func->lut_3d, mpcc_id);
 543         else
 544                 result = mpc->funcs->program_3dlut(mpc, NULL, mpcc_id);
 545
 546         return result;
 547 }
 548
 549 bool dcn32_set_input_transfer_func(struct dc *dc,
 550                                 struct pipe_ctx *pipe_ctx,
 551                                 const struct dc_plane_state *plane_state)
 552 {
 553         struct dce_hwseq *hws = dc->hwseq;
 554         struct mpc *mpc = dc->res_pool->mpc;
 555         struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
 556
 557         enum dc_transfer_func_predefined tf;
 558         bool result = true;
 559         struct pwl_params *params = NULL;
 560
 561         if (mpc == NULL || plane_state == NULL)
 562                 return false;
 563
 564         tf = TRANSFER_FUNCTION_UNITY;
 565
 566         if (plane_state->in_transfer_func &&
 567                 plane_state->in_transfer_func->type == TF_TYPE_PREDEFINED)
 568                 tf = plane_state->in_transfer_func->tf;
 569
 570         dpp_base->funcs->dpp_set_pre_degam(dpp_base, tf);
 571
 572         if (plane_state->in_transfer_func) {
 573                 if (plane_state->in_transfer_func->type == TF_TYPE_HWPWL)
 574                         params = &plane_state->in_transfer_func->pwl;
 575                 else if (plane_state->in_transfer_func->type == TF_TYPE_DISTRIBUTED_POINTS &&
 576                         cm3_helper_translate_curve_to_hw_format(plane_state->in_transfer_func,
 577                                         &dpp_base->degamma_params, false))
 578                         params = &dpp_base->degamma_params;
 579         }
 580
 581         result = dpp_base->funcs->dpp_program_gamcor_lut(dpp_base, params);
 582
 583         if (result &&
 584                         pipe_ctx->stream_res.opp &&
 585                         pipe_ctx->stream_res.opp->ctx &&
 586                         hws->funcs.set_mcm_luts)
 587                 result = hws->funcs.set_mcm_luts(pipe_ctx, plane_state);
 588
 589         return result;
 590 }
 591
 592 bool dcn32_set_output_transfer_func(struct dc *dc,
 593                                 struct pipe_ctx *pipe_ctx,
 594                                 const struct dc_stream_state *stream)
 595 {
 596         int mpcc_id = pipe_ctx->plane_res.hubp->inst;
 597         struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
 598         struct pwl_params *params = NULL;
 599         bool ret = false;
 600
 601         /* program OGAM or 3DLUT only for the top pipe*/
 602         if (pipe_ctx->top_pipe == NULL) {
 603                 /*program shaper and 3dlut in MPC*/
 604                 ret = dcn32_set_mpc_shaper_3dlut(pipe_ctx, stream);
 605                 if (ret == false && mpc->funcs->set_output_gamma && stream->out_transfer_func) {
 606                         if (stream->out_transfer_func->type == TF_TYPE_HWPWL)
 607                                 params = &stream->out_transfer_func->pwl;
 608                         else if (pipe_ctx->stream->out_transfer_func->type ==
 609                                         TF_TYPE_DISTRIBUTED_POINTS &&
 610                                         cm3_helper_translate_curve_to_hw_format(
 611                                         stream->out_transfer_func,
 612                                         &mpc->blender_params, false))
 613                                 params = &mpc->blender_params;
 614                  /* there are no ROM LUTs in OUTGAM */
 615                 if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED)
 616                         BREAK_TO_DEBUGGER();
 617                 }
 618         }
 619
 620         mpc->funcs->set_output_gamma(mpc, mpcc_id, params);
 621         return ret;
 622 }
 623
 624 /* Program P-State force value according to if pipe is using SubVP or not:
 625  * 1. Reset P-State force on all pipes first
 626  * 2. For each main pipe, force P-State disallow (P-State allow moderated by DMUB)
 627  */
 628 void dcn32_subvp_update_force_pstate(struct dc *dc, struct dc_state *context)
 629 {
 630         int i;
 631         int num_subvp = 0;
 632         /* Unforce p-state for each pipe
 633          */
 634         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 635                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 636                 struct hubp *hubp = pipe->plane_res.hubp;
 637
 638                 if (hubp && hubp->funcs->hubp_update_force_pstate_disallow)
 639                         hubp->funcs->hubp_update_force_pstate_disallow(hubp, false);
 640                 if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_MAIN)
 641                         num_subvp++;
 642         }
 643
 644         if (num_subvp == 0)
 645                 return;
 646
 647         /* Loop through each pipe -- for each subvp main pipe force p-state allow equal to false.
 648          */
 649         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 650                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 651
 652                 // For SubVP + DRR, also force disallow on the DRR pipe
 653                 // (We will force allow in the DMUB sequence -- some DRR timings by default won't allow P-State so we have
 654                 // to force once the vblank is stretched).
 655                 if (pipe->stream && pipe->plane_state && (pipe->stream->mall_stream_config.type == SUBVP_MAIN ||
 656                                 (pipe->stream->mall_stream_config.type == SUBVP_NONE && pipe->stream->ignore_msa_timing_param))) {
 657                         struct hubp *hubp = pipe->plane_res.hubp;
 658
 659                         if (hubp && hubp->funcs->hubp_update_force_pstate_disallow)
 660                                 hubp->funcs->hubp_update_force_pstate_disallow(hubp, true);
 661                 }
 662         }
 663 }
 664
 665 /* Update MALL_SEL register based on if pipe / plane
 666  * is a phantom pipe, main pipe, and if using MALL
 667  * for SS.
 668  */
 669 void dcn32_update_mall_sel(struct dc *dc, struct dc_state *context)
 670 {
 671         int i;
 672         unsigned int num_ways = dcn32_calculate_cab_allocation(dc, context);
 673         bool cache_cursor = false;
 674
 675         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 676                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 677                 struct hubp *hubp = pipe->plane_res.hubp;
 678
 679                 if (pipe->stream && pipe->plane_state && hubp && hubp->funcs->hubp_update_mall_sel) {
 680                         if (hubp->curs_attr.width * hubp->curs_attr.height * 4 > 16384)
 681                                 cache_cursor = true;
 682
 683                         if (pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) {
 684                                         hubp->funcs->hubp_update_mall_sel(hubp, 1, false);
 685                         } else {
 686                                 hubp->funcs->hubp_update_mall_sel(hubp,
 687                                         num_ways <= dc->caps.cache_num_ways &&
 688                                         pipe->stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED ? 2 : 0,
 689                                                         cache_cursor);
 690                         }
 691                 }
 692         }
 693 }
 694
 695 /* Program the sub-viewport pipe configuration after the main / phantom pipes
 696  * have been programmed in hardware.
 697  * 1. Update force P-State for all the main pipes (disallow P-state)
 698  * 2. Update MALL_SEL register
 699  * 3. Program FORCE_ONE_ROW_FOR_FRAME for main subvp pipes
 700  */
 701 void dcn32_program_mall_pipe_config(struct dc *dc, struct dc_state *context)
 702 {
 703         int i;
 704         struct dce_hwseq *hws = dc->hwseq;
 705
 706         // Don't force p-state disallow -- can't block dummy p-state
 707
 708         // Update MALL_SEL register for each pipe
 709         if (hws && hws->funcs.update_mall_sel)
 710                 hws->funcs.update_mall_sel(dc, context);
 711
 712         // Program FORCE_ONE_ROW_FOR_FRAME and CURSOR_REQ_MODE for main subvp pipes
 713         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 714                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 715                 struct hubp *hubp = pipe->plane_res.hubp;
 716
 717                 if (pipe->stream && hubp && hubp->funcs->hubp_prepare_subvp_buffering) {
 718                         /* TODO - remove setting CURSOR_REQ_MODE to 0 for legacy cases
 719                          *      - need to investigate single pipe MPO + SubVP case to
 720                          *        see if CURSOR_REQ_MODE will be back to 1 for SubVP
 721                          *        when it should be 0 for MPO
 722                          */
 723                         if (pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
 724                                 hubp->funcs->hubp_prepare_subvp_buffering(hubp, true);
 725                         }
 726                 }
 727         }
 728 }
 729
 730 void dcn32_init_hw(struct dc *dc)
 731 {
 732         struct abm **abms = dc->res_pool->multiple_abms;
 733         struct dce_hwseq *hws = dc->hwseq;
 734         struct dc_bios *dcb = dc->ctx->dc_bios;
 735         struct resource_pool *res_pool = dc->res_pool;
 736         int i;
 737         int edp_num;
 738         uint32_t backlight = MAX_BACKLIGHT_LEVEL;
 739
 740         if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
 741                 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
 742
 743         // Initialize the dccg
 744         if (res_pool->dccg->funcs->dccg_init)
 745                 res_pool->dccg->funcs->dccg_init(res_pool->dccg);
 746
 747         if (!dcb->funcs->is_accelerated_mode(dcb)) {
 748                 hws->funcs.bios_golden_init(dc);
 749                 hws->funcs.disable_vga(dc->hwseq);
 750         }
 751
 752         // Set default OPTC memory power states
 753         if (dc->debug.enable_mem_low_power.bits.optc) {
 754                 // Shutdown when unassigned and light sleep in VBLANK
 755                 REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1);
 756         }
 757
 758         if (dc->debug.enable_mem_low_power.bits.vga) {
 759                 // Power down VGA memory
 760                 REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1);
 761         }
 762
 763         if (dc->ctx->dc_bios->fw_info_valid) {
 764                 res_pool->ref_clocks.xtalin_clock_inKhz =
 765                                 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
 766
 767                 if (res_pool->dccg && res_pool->hubbub) {
 768                         (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
 769                                         dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
 770                                         &res_pool->ref_clocks.dccg_ref_clock_inKhz);
 771
 772                         (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
 773                                         res_pool->ref_clocks.dccg_ref_clock_inKhz,
 774                                         &res_pool->ref_clocks.dchub_ref_clock_inKhz);
 775                 } else {
 776                         // Not all ASICs have DCCG sw component
 777                         res_pool->ref_clocks.dccg_ref_clock_inKhz =
 778                                         res_pool->ref_clocks.xtalin_clock_inKhz;
 779                         res_pool->ref_clocks.dchub_ref_clock_inKhz =
 780                                         res_pool->ref_clocks.xtalin_clock_inKhz;
 781                 }
 782         } else
 783                 ASSERT_CRITICAL(false);
 784
 785         for (i = 0; i < dc->link_count; i++) {
 786                 /* Power up AND update implementation according to the
 787                  * required signal (which may be different from the
 788                  * default signal on connector).
 789                  */
 790                 struct dc_link *link = dc->links[i];
 791
 792                 link->link_enc->funcs->hw_init(link->link_enc);
 793
 794                 /* Check for enabled DIG to identify enabled display */
 795                 if (link->link_enc->funcs->is_dig_enabled &&
 796                         link->link_enc->funcs->is_dig_enabled(link->link_enc)) {
 797                         link->link_status.link_active = true;
 798                         if (link->link_enc->funcs->fec_is_active &&
 799                                         link->link_enc->funcs->fec_is_active(link->link_enc))
 800                                 link->fec_state = dc_link_fec_enabled;
 801                 }
 802         }
 803
 804         /* Power gate DSCs */
 805         for (i = 0; i < res_pool->res_cap->num_dsc; i++)
 806                 if (hws->funcs.dsc_pg_control != NULL)
 807                         hws->funcs.dsc_pg_control(hws, res_pool->dscs[i]->inst, false);
 808
 809         /* we want to turn off all dp displays before doing detection */
 810         dc_link_blank_all_dp_displays(dc);
 811
 812         /* If taking control over from VBIOS, we may want to optimize our first
 813          * mode set, so we need to skip powering down pipes until we know which
 814          * pipes we want to use.
 815          * Otherwise, if taking control is not possible, we need to power
 816          * everything down.
 817          */
 818         if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) {
 819                 hws->funcs.init_pipes(dc, dc->current_state);
 820                 if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)
 821                         dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,
 822                                         !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);
 823         }
 824
 825         /* In headless boot cases, DIG may be turned
 826          * on which causes HW/SW discrepancies.
 827          * To avoid this, power down hardware on boot
 828          * if DIG is turned on and seamless boot not enabled
 829          */
 830         if (!dc->config.seamless_boot_edp_requested) {
 831                 struct dc_link *edp_links[MAX_NUM_EDP];
 832                 struct dc_link *edp_link;
 833
 834                 get_edp_links(dc, edp_links, &edp_num);
 835                 if (edp_num) {
 836                         for (i = 0; i < edp_num; i++) {
 837                                 edp_link = edp_links[i];
 838                                 if (edp_link->link_enc->funcs->is_dig_enabled &&
 839                                                 edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) &&
 840                                                 dc->hwss.edp_backlight_control &&
 841                                                 dc->hwss.power_down &&
 842                                                 dc->hwss.edp_power_control) {
 843                                         dc->hwss.edp_backlight_control(edp_link, false);
 844                                         dc->hwss.power_down(dc);
 845                                         dc->hwss.edp_power_control(edp_link, false);
 846                                 }
 847                         }
 848                 } else {
 849                         for (i = 0; i < dc->link_count; i++) {
 850                                 struct dc_link *link = dc->links[i];
 851
 852                                 if (link->link_enc->funcs->is_dig_enabled &&
 853                                                 link->link_enc->funcs->is_dig_enabled(link->link_enc) &&
 854                                                 dc->hwss.power_down) {
 855                                         dc->hwss.power_down(dc);
 856                                         break;
 857                                 }
 858
 859                         }
 860                 }
 861         }
 862
 863         for (i = 0; i < res_pool->audio_count; i++) {
 864                 struct audio *audio = res_pool->audios[i];
 865
 866                 audio->funcs->hw_init(audio);
 867         }
 868
 869         for (i = 0; i < dc->link_count; i++) {
 870                 struct dc_link *link = dc->links[i];
 871
 872                 if (link->panel_cntl)
 873                         backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl);
 874         }
 875
 876         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 877                 if (abms[i] != NULL && abms[i]->funcs != NULL)
 878                         abms[i]->funcs->abm_init(abms[i], backlight);
 879         }
 880
 881         /* power AFMT HDMI memory TODO: may move to dis/en output save power*/
 882         REG_WRITE(DIO_MEM_PWR_CTRL, 0);
 883
 884         if (!dc->debug.disable_clock_gate) {
 885                 /* enable all DCN clock gating */
 886                 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
 887
 888                 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
 889
 890                 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
 891         }
 892         if (hws->funcs.enable_power_gating_plane)
 893                 hws->funcs.enable_power_gating_plane(dc->hwseq, true);
 894
 895         if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks)
 896                 dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);
 897
 898         if (dc->clk_mgr->funcs->notify_wm_ranges)
 899                 dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);
 900
 901         if (dc->clk_mgr->funcs->set_hard_max_memclk)
 902                 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
 903
 904         if (dc->res_pool->hubbub->funcs->force_pstate_change_control)
 905                 dc->res_pool->hubbub->funcs->force_pstate_change_control(
 906                                 dc->res_pool->hubbub, false, false);
 907
 908         if (dc->res_pool->hubbub->funcs->init_crb)
 909                 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);
 910
 911         // Get DMCUB capabilities
 912         if (dc->ctx->dmub_srv) {
 913                 dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv->dmub);
 914                 dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;
 915         }
 916 }
 917
 918 static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream,
 919                 int opp_cnt)
 920 {
 921         bool hblank_halved = optc2_is_two_pixels_per_containter(&stream->timing);
 922         int flow_ctrl_cnt;
 923
 924         if (opp_cnt >= 2)
 925                 hblank_halved = true;
 926
 927         flow_ctrl_cnt = stream->timing.h_total - stream->timing.h_addressable -
 928                         stream->timing.h_border_left -
 929                         stream->timing.h_border_right;
 930
 931         if (hblank_halved)
 932                 flow_ctrl_cnt /= 2;
 933
 934         /* ODM combine 4:1 case */
 935         if (opp_cnt == 4)
 936                 flow_ctrl_cnt /= 2;
 937
 938         return flow_ctrl_cnt;
 939 }
 940
 941 static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
 942 {
 943         struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;
 944         struct dc_stream_state *stream = pipe_ctx->stream;
 945         struct pipe_ctx *odm_pipe;
 946         int opp_cnt = 1;
 947
 948         ASSERT(dsc);
 949         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
 950                 opp_cnt++;
 951
 952         if (enable) {
 953                 struct dsc_config dsc_cfg;
 954                 struct dsc_optc_config dsc_optc_cfg;
 955                 enum optc_dsc_mode optc_dsc_mode;
 956
 957                 /* Enable DSC hw block */
 958                 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt;
 959                 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;
 960                 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
 961                 dsc_cfg.color_depth = stream->timing.display_color_depth;
 962                 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;
 963                 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
 964                 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0);
 965                 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
 966
 967                 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg);
 968                 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);
 969                 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
 970                         struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc;
 971
 972                         ASSERT(odm_dsc);
 973                         odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg);
 974                         odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst);
 975                 }
 976                 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt;
 977                 dsc_cfg.pic_width *= opp_cnt;
 978
 979                 optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED;
 980
 981                 /* Enable DSC in OPTC */
 982                 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst);
 983                 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg,
 984                                                         optc_dsc_mode,
 985                                                         dsc_optc_cfg.bytes_per_pixel,
 986                                                         dsc_optc_cfg.slice_width);
 987         } else {
 988                 /* disable DSC in OPTC */
 989                 pipe_ctx->stream_res.tg->funcs->set_dsc_config(
 990                                 pipe_ctx->stream_res.tg,
 991                                 OPTC_DSC_DISABLED, 0, 0);
 992
 993                 /* disable DSC block */
 994                 dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc);
 995                 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
 996                         ASSERT(odm_pipe->stream_res.dsc);
 997                         odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc);
 998                 }
 999         }
1000 }
1001
1002 /*
1003 * Given any pipe_ctx, return the total ODM combine factor, and optionally return
1004 * the OPPids which are used
1005 * */
1006 static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, unsigned int *opp_instances)
1007 {
1008         unsigned int opp_count = 1;
1009         struct pipe_ctx *odm_pipe;
1010
1011         /* First get to the top pipe */
1012         for (odm_pipe = pipe_ctx; odm_pipe->prev_odm_pipe; odm_pipe = odm_pipe->prev_odm_pipe)
1013                 ;
1014
1015         /* First pipe is always used */
1016         if (opp_instances)
1017                 opp_instances[0] = odm_pipe->stream_res.opp->inst;
1018
1019         /* Find and count odm pipes, if any */
1020         for (odm_pipe = odm_pipe->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
1021                 if (opp_instances)
1022                         opp_instances[opp_count] = odm_pipe->stream_res.opp->inst;
1023                 opp_count++;
1024         }
1025
1026         return opp_count;
1027 }
1028
1029 void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)
1030 {
1031         struct pipe_ctx *odm_pipe;
1032         int opp_cnt = 0;
1033         int opp_inst[MAX_PIPES] = {0};
1034         bool rate_control_2x_pclk = (pipe_ctx->stream->timing.flags.INTERLACE || optc2_is_two_pixels_per_containter(&pipe_ctx->stream->timing));
1035         struct mpc_dwb_flow_control flow_control;
1036         struct mpc *mpc = dc->res_pool->mpc;
1037         int i;
1038
1039         opp_cnt = get_odm_config(pipe_ctx, opp_inst);
1040
1041         if (opp_cnt > 1)
1042                 pipe_ctx->stream_res.tg->funcs->set_odm_combine(
1043                                 pipe_ctx->stream_res.tg,
1044                                 opp_inst, opp_cnt,
1045                                 &pipe_ctx->stream->timing);
1046         else
1047                 pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
1048                                 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
1049
1050         rate_control_2x_pclk = rate_control_2x_pclk || opp_cnt > 1;
1051         flow_control.flow_ctrl_mode = 0;
1052         flow_control.flow_ctrl_cnt0 = 0x80;
1053         flow_control.flow_ctrl_cnt1 = calc_mpc_flow_ctrl_cnt(pipe_ctx->stream, opp_cnt);
1054         if (mpc->funcs->set_out_rate_control) {
1055                 for (i = 0; i < opp_cnt; ++i) {
1056                         mpc->funcs->set_out_rate_control(
1057                                         mpc, opp_inst[i],
1058                                         true,
1059                                         rate_control_2x_pclk,
1060                                         &flow_control);
1061                 }
1062         }
1063
1064         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
1065                 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control(
1066                                 odm_pipe->stream_res.opp,
1067                                 true);
1068         }
1069
1070         // Don't program pixel clock after link is already enabled
1071 /*      if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
1072                         pipe_ctx->clock_source,
1073                         &pipe_ctx->stream_res.pix_clk_params,
1074                         &pipe_ctx->pll_settings)) {
1075                 BREAK_TO_DEBUGGER();
1076         }*/
1077
1078         if (pipe_ctx->stream_res.dsc)
1079                 update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC);
1080 }
1081
1082 unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div)
1083 {
1084         struct dc_stream_state *stream = pipe_ctx->stream;
1085         unsigned int odm_combine_factor = 0;
1086         struct dc *dc = pipe_ctx->stream->ctx->dc;
1087         bool two_pix_per_container = false;
1088
1089         // For phantom pipes, use the same programming as the main pipes
1090         if (pipe_ctx->stream->mall_stream_config.type == SUBVP_PHANTOM) {
1091                 stream = pipe_ctx->stream->mall_stream_config.paired_stream;
1092         }
1093         two_pix_per_container = optc2_is_two_pixels_per_containter(&stream->timing);
1094         odm_combine_factor = get_odm_config(pipe_ctx, NULL);
1095
1096         if (is_dp_128b_132b_signal(pipe_ctx)) {
1097                 *k2_div = PIXEL_RATE_DIV_BY_1;
1098         } else if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) || dc_is_dvi_signal(pipe_ctx->stream->signal)) {
1099                 *k1_div = PIXEL_RATE_DIV_BY_1;
1100                 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
1101                         *k2_div = PIXEL_RATE_DIV_BY_2;
1102                 else
1103                         *k2_div = PIXEL_RATE_DIV_BY_4;
1104         } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
1105                 if (two_pix_per_container) {
1106                         *k1_div = PIXEL_RATE_DIV_BY_1;
1107                         *k2_div = PIXEL_RATE_DIV_BY_2;
1108                 } else {
1109                         *k1_div = PIXEL_RATE_DIV_BY_1;
1110                         *k2_div = PIXEL_RATE_DIV_BY_4;
1111                         if ((odm_combine_factor == 2) || dc->debug.enable_dp_dig_pixel_rate_div_policy)
1112                                 *k2_div = PIXEL_RATE_DIV_BY_2;
1113                 }
1114         }
1115
1116         if ((*k1_div == PIXEL_RATE_DIV_NA) && (*k2_div == PIXEL_RATE_DIV_NA))
1117                 ASSERT(false);
1118
1119         return odm_combine_factor;
1120 }
1121
1122 void dcn32_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx)
1123 {
1124         uint32_t pix_per_cycle = 1;
1125         uint32_t odm_combine_factor = 1;
1126
1127         if (!pipe_ctx || !pipe_ctx->stream || !pipe_ctx->stream_res.stream_enc)
1128                 return;
1129
1130         odm_combine_factor = get_odm_config(pipe_ctx, NULL);
1131         if (optc2_is_two_pixels_per_containter(&pipe_ctx->stream->timing) || odm_combine_factor > 1
1132                 || dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx))
1133                 pix_per_cycle = 2;
1134
1135         if (pipe_ctx->stream_res.stream_enc->funcs->set_input_mode)
1136                 pipe_ctx->stream_res.stream_enc->funcs->set_input_mode(pipe_ctx->stream_res.stream_enc,
1137                                 pix_per_cycle);
1138 }
1139
1140 void dcn32_unblank_stream(struct pipe_ctx *pipe_ctx,
1141                 struct dc_link_settings *link_settings)
1142 {
1143         struct encoder_unblank_param params = {0};
1144         struct dc_stream_state *stream = pipe_ctx->stream;
1145         struct dc_link *link = stream->link;
1146         struct dce_hwseq *hws = link->dc->hwseq;
1147         struct pipe_ctx *odm_pipe;
1148         struct dc *dc = pipe_ctx->stream->ctx->dc;
1149         uint32_t pix_per_cycle = 1;
1150
1151         params.opp_cnt = 1;
1152         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
1153                 params.opp_cnt++;
1154
1155         /* only 3 items below are used by unblank */
1156         params.timing = pipe_ctx->stream->timing;
1157
1158         params.link_settings.link_rate = link_settings->link_rate;
1159
1160         if (is_dp_128b_132b_signal(pipe_ctx)) {
1161                 /* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */
1162                 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_unblank(
1163                                 pipe_ctx->stream_res.hpo_dp_stream_enc,
1164                                 pipe_ctx->stream_res.tg->inst);
1165         } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
1166                 if (optc2_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt > 1
1167                         || dc->debug.enable_dp_dig_pixel_rate_div_policy) {
1168                         params.timing.pix_clk_100hz /= 2;
1169                         pix_per_cycle = 2;
1170                 }
1171                 pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine(
1172                                 pipe_ctx->stream_res.stream_enc, pix_per_cycle > 1);
1173                 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, &params);
1174         }
1175
1176         if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP)
1177                 hws->funcs.edp_backlight_control(link, true);
1178 }
1179
1180 bool dcn32_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx)
1181 {
1182         struct dc *dc = pipe_ctx->stream->ctx->dc;
1183
1184         if (dc_is_dp_signal(pipe_ctx->stream->signal) && !is_dp_128b_132b_signal(pipe_ctx) &&
1185                 dc->debug.enable_dp_dig_pixel_rate_div_policy)
1186                 return true;
1187         return false;
1188 }