drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26
  27 #include "dm_services.h"
  28 #include "dm_helpers.h"
  29 #include "core_types.h"
  30 #include "resource.h"
  31 #include "dccg.h"
  32 #include "dce/dce_hwseq.h"
  33 #include "dcn30/dcn30_cm_common.h"
  34 #include "reg_helper.h"
  35 #include "abm.h"
  36 #include "hubp.h"
  37 #include "dchubbub.h"
  38 #include "timing_generator.h"
  39 #include "opp.h"
  40 #include "ipp.h"
  41 #include "mpc.h"
  42 #include "mcif_wb.h"
  43 #include "dc_dmub_srv.h"
  44 #include "link_hwss.h"
  45 #include "dpcd_defs.h"
  46 #include "dcn32_hwseq.h"
  47 #include "clk_mgr.h"
  48 #include "dsc.h"
  49 #include "dcn20/dcn20_optc.h"
  50 #include "dmub_subvp_state.h"
  51 #include "dce/dmub_hw_lock_mgr.h"
  52 #include "dc_link_dp.h"
  53 #include "dmub/inc/dmub_subvp_state.h"
  54
  55 #define DC_LOGGER_INIT(logger)
  56
  57 #define CTX \
  58         hws->ctx
  59 #define REG(reg)\
  60         hws->regs->reg
  61 #define DC_LOGGER \
  62                 dc->ctx->logger
  63
  64
  65 #undef FN
  66 #define FN(reg_name, field_name) \
  67         hws->shifts->field_name, hws->masks->field_name
  68
  69 void dcn32_dsc_pg_control(
  70                 struct dce_hwseq *hws,
  71                 unsigned int dsc_inst,
  72                 bool power_on)
  73 {
  74         uint32_t power_gate = power_on ? 0 : 1;
  75         uint32_t pwr_status = power_on ? 0 : 2;
  76         uint32_t org_ip_request_cntl = 0;
  77
  78         if (hws->ctx->dc->debug.disable_dsc_power_gate)
  79                 return;
  80
  81         REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
  82         if (org_ip_request_cntl == 0)
  83                 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
  84
  85         switch (dsc_inst) {
  86         case 0: /* DSC0 */
  87                 REG_UPDATE(DOMAIN16_PG_CONFIG,
  88                                 DOMAIN_POWER_GATE, power_gate);
  89
  90                 REG_WAIT(DOMAIN16_PG_STATUS,
  91                                 DOMAIN_PGFSM_PWR_STATUS, pwr_status,
  92                                 1, 1000);
  93                 break;
  94         case 1: /* DSC1 */
  95                 REG_UPDATE(DOMAIN17_PG_CONFIG,
  96                                 DOMAIN_POWER_GATE, power_gate);
  97
  98                 REG_WAIT(DOMAIN17_PG_STATUS,
  99                                 DOMAIN_PGFSM_PWR_STATUS, pwr_status,
 100                                 1, 1000);
 101                 break;
 102         case 2: /* DSC2 */
 103                 REG_UPDATE(DOMAIN18_PG_CONFIG,
 104                                 DOMAIN_POWER_GATE, power_gate);
 105
 106                 REG_WAIT(DOMAIN18_PG_STATUS,
 107                                 DOMAIN_PGFSM_PWR_STATUS, pwr_status,
 108                                 1, 1000);
 109                 break;
 110         case 3: /* DSC3 */
 111                 REG_UPDATE(DOMAIN19_PG_CONFIG,
 112                                 DOMAIN_POWER_GATE, power_gate);
 113
 114                 REG_WAIT(DOMAIN19_PG_STATUS,
 115                                 DOMAIN_PGFSM_PWR_STATUS, pwr_status,
 116                                 1, 1000);
 117                 break;
 118         default:
 119                 BREAK_TO_DEBUGGER();
 120                 break;
 121         }
 122
 123         if (org_ip_request_cntl == 0)
 124                 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
 125 }
 126
 127
 128 void dcn32_enable_power_gating_plane(
 129         struct dce_hwseq *hws,
 130         bool enable)
 131 {
 132         bool force_on = true; /* disable power gating */
 133
 134         if (enable)
 135                 force_on = false;
 136
 137         /* DCHUBP0/1/2/3 */
 138         REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
 139         REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
 140         REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
 141         REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
 142
 143         /* DCS0/1/2/3 */
 144         REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
 145         REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
 146         REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
 147         REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
 148 }
 149
 150 void dcn32_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on)
 151 {
 152         uint32_t power_gate = power_on ? 0 : 1;
 153         uint32_t pwr_status = power_on ? 0 : 2;
 154
 155         if (hws->ctx->dc->debug.disable_hubp_power_gate)
 156                 return;
 157
 158         if (REG(DOMAIN0_PG_CONFIG) == 0)
 159                 return;
 160
 161         switch (hubp_inst) {
 162         case 0:
 163                 REG_SET(DOMAIN0_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
 164                 REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
 165                 break;
 166         case 1:
 167                 REG_SET(DOMAIN1_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
 168                 REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
 169                 break;
 170         case 2:
 171                 REG_SET(DOMAIN2_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
 172                 REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
 173                 break;
 174         case 3:
 175                 REG_SET(DOMAIN3_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
 176                 REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
 177                 break;
 178         default:
 179                 BREAK_TO_DEBUGGER();
 180                 break;
 181         }
 182 }
 183
 184 static bool dcn32_check_no_memory_request_for_cab(struct dc *dc)
 185 {
 186         int i;
 187
 188     /* First, check no-memory-request case */
 189         for (i = 0; i < dc->current_state->stream_count; i++) {
 190                 if (dc->current_state->stream_status[i].plane_count)
 191                         /* Fail eligibility on a visible stream */
 192                         break;
 193         }
 194
 195         if (i == dc->current_state->stream_count)
 196                 return true;
 197
 198         return false;
 199 }
 200
 201 /* This function takes in the start address and surface size to be cached in CAB
 202  * and calculates the total number of cache lines required to store the surface.
 203  * The number of cache lines used for each surface is calculated independently of
 204  * one another. For example, if there is a primary surface(1), meta surface(2), and
 205  * cursor(3), this function should be called 3 times to calculate the number of cache
 206  * lines used for each of those surfaces.
 207  */
 208 static uint32_t dcn32_cache_lines_for_surface(struct dc *dc, uint32_t surface_size, uint64_t start_address)
 209 {
 210         uint32_t lines_used = 1;
 211         uint32_t num_cached_bytes = 0;
 212         uint32_t remaining_size = 0;
 213         uint32_t cache_line_size = dc->caps.cache_line_size;
 214         uint32_t remainder = 0;
 215
 216         /* 1. Calculate surface size minus the number of bytes stored
 217          * in the first cache line (all bytes in first cache line might
 218          * not be fully used).
 219          */
 220         div_u64_rem(start_address, cache_line_size, &remainder);
 221         num_cached_bytes = cache_line_size - remainder;
 222         remaining_size = surface_size - num_cached_bytes;
 223
 224         /* 2. Calculate number of cache lines that will be fully used with
 225          * the remaining number of bytes to be stored.
 226          */
 227         lines_used += (remaining_size / cache_line_size);
 228
 229         /* 3. Check if we need an extra line due to the remaining size not being
 230          * a multiple of CACHE_LINE_SIZE.
 231          */
 232         if (remaining_size % cache_line_size > 0)
 233                 lines_used++;
 234
 235         return lines_used;
 236 }
 237
 238 /* This function loops through every surface that needs to be cached in CAB for SS,
 239  * and calculates the total number of ways required to store all surfaces (primary,
 240  * meta, cursor).
 241  */
 242 static uint32_t dcn32_calculate_cab_allocation(struct dc *dc, struct dc_state *ctx)
 243 {
 244         uint8_t i, j;
 245         struct dc_stream_state *stream = NULL;
 246         struct dc_plane_state *plane = NULL;
 247         uint32_t surface_size = 0;
 248         uint32_t cursor_size = 0;
 249         uint32_t cache_lines_used = 0;
 250         uint32_t total_lines = 0;
 251         uint32_t lines_per_way = 0;
 252         uint32_t num_ways = 0;
 253         uint32_t prev_addr_low = 0;
 254
 255         for (i = 0; i < ctx->stream_count; i++) {
 256                 stream = ctx->streams[i];
 257
 258                 // Don't include PSR surface in the total surface size for CAB allocation
 259                 if (stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED)
 260                         continue;
 261
 262                 if (ctx->stream_status[i].plane_count == 0)
 263                         continue;
 264
 265                 // For each stream, loop through each plane to calculate the number of cache
 266                 // lines required to store the surface in CAB
 267                 for (j = 0; j < ctx->stream_status[i].plane_count; j++) {
 268                         plane = ctx->stream_status[i].plane_states[j];
 269
 270                         // Calculate total surface size
 271                         if (prev_addr_low != plane->address.grph.addr.u.low_part) {
 272                                 /* if plane address are different from prev FB, then userspace allocated separate FBs*/
 273                                 surface_size += plane->plane_size.surface_pitch *
 274                                         plane->plane_size.surface_size.height *
 275                                         (plane->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ? 8 : 4);
 276
 277                                 prev_addr_low = plane->address.grph.addr.u.low_part;
 278                         } else {
 279                                 /* We have the same fb for all the planes.
 280                                  * Xorg always creates one giant fb that holds all surfaces,
 281                                  * so allocating it once is sufficient.
 282                                  * */
 283                                 continue;
 284                         }
 285                         // Convert surface size + starting address to number of cache lines required
 286                         // (alignment accounted for)
 287                         cache_lines_used += dcn32_cache_lines_for_surface(dc, surface_size,
 288                                         plane->address.grph.addr.quad_part);
 289
 290                         if (plane->address.grph.meta_addr.quad_part) {
 291                                 // Meta surface
 292                                 cache_lines_used += dcn32_cache_lines_for_surface(dc, surface_size,
 293                                                 plane->address.grph.meta_addr.quad_part);
 294                         }
 295                 }
 296
 297                 // Include cursor size for CAB allocation
 298                 if (stream->cursor_position.enable && plane->address.grph.cursor_cache_addr.quad_part) {
 299                         cursor_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size;
 300                         switch (stream->cursor_attributes.color_format) {
 301                         case CURSOR_MODE_MONO:
 302                                 cursor_size /= 2;
 303                                 break;
 304                         case CURSOR_MODE_COLOR_1BIT_AND:
 305                         case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:
 306                         case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:
 307                                 cursor_size *= 4;
 308                                 break;
 309
 310                         case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED:
 311                         case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED:
 312                                 cursor_size *= 8;
 313                                 break;
 314                         }
 315                         cache_lines_used += dcn32_cache_lines_for_surface(dc, cursor_size,
 316                                         plane->address.grph.cursor_cache_addr.quad_part);
 317                 }
 318         }
 319
 320         // Convert number of cache lines required to number of ways
 321         total_lines = dc->caps.max_cab_allocation_bytes / dc->caps.cache_line_size;
 322         lines_per_way = total_lines / dc->caps.cache_num_ways;
 323         num_ways = cache_lines_used / lines_per_way;
 324
 325         if (cache_lines_used % lines_per_way > 0)
 326                 num_ways++;
 327
 328         return num_ways;
 329 }
 330
 331 bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable)
 332 {
 333         union dmub_rb_cmd cmd;
 334         uint8_t ways, i;
 335         int j;
 336         bool stereo_in_use = false;
 337         struct dc_plane_state *plane = NULL;
 338
 339         if (!dc->ctx->dmub_srv)
 340                 return false;
 341
 342         if (enable) {
 343                 if (dc->current_state) {
 344
 345                         /* 1. Check no memory request case for CAB.
 346                          * If no memory request case, send CAB_ACTION NO_DF_REQ DMUB message
 347                          */
 348                         if (dcn32_check_no_memory_request_for_cab(dc)) {
 349                                 /* Enable no-memory-requests case */
 350                                 memset(&cmd, 0, sizeof(cmd));
 351                                 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS;
 352                                 cmd.cab.header.sub_type = DMUB_CMD__CAB_NO_DCN_REQ;
 353                                 cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header);
 354
 355                                 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
 356                                 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
 357
 358                                 return true;
 359                         }
 360
 361                         /* 2. Check if all surfaces can fit in CAB.
 362                          * If surfaces can fit into CAB, send CAB_ACTION_ALLOW DMUB message
 363                          * and configure HUBP's to fetch from MALL
 364                          */
 365                         ways = dcn32_calculate_cab_allocation(dc, dc->current_state);
 366
 367                         /* MALL not supported with Stereo3D. If any plane is using stereo,
 368                          * don't try to enter MALL.
 369                          */
 370                         for (i = 0; i < dc->current_state->stream_count; i++) {
 371                                 for (j = 0; j < dc->current_state->stream_status[i].plane_count; j++) {
 372                                         plane = dc->current_state->stream_status[i].plane_states[j];
 373
 374                                         if (plane->address.type == PLN_ADDR_TYPE_GRPH_STEREO) {
 375                                                 stereo_in_use = true;
 376                                                 break;
 377                                         }
 378                                 }
 379                                 if (stereo_in_use)
 380                                         break;
 381                         }
 382                         if (ways <= dc->caps.cache_num_ways && !stereo_in_use) {
 383                                 memset(&cmd, 0, sizeof(cmd));
 384                                 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS;
 385                                 cmd.cab.header.sub_type = DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB;
 386                                 cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header);
 387                                 cmd.cab.cab_alloc_ways = ways;
 388
 389                                 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
 390                                 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
 391
 392                                 return true;
 393                         }
 394
 395                 }
 396                 return false;
 397         }
 398
 399         /* Disable CAB */
 400         memset(&cmd, 0, sizeof(cmd));
 401         cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS;
 402         cmd.cab.header.sub_type = DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION;
 403         cmd.cab.header.payload_bytes =
 404                         sizeof(cmd.cab) - sizeof(cmd.cab.header);
 405
 406         dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
 407         dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
 408         dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);
 409
 410         return true;
 411 }
 412
 413 /* Send DMCUB message with SubVP pipe info
 414  * - For each pipe in context, populate payload with required SubVP information
 415  *   if the pipe is using SubVP for MCLK switch
 416  * - This function must be called while the DMUB HW lock is acquired by driver
 417  */
 418 void dcn32_commit_subvp_config(struct dc *dc, struct dc_state *context)
 419 {
 420 /*
 421         int i;
 422         bool enable_subvp = false;
 423
 424         if (!dc->ctx || !dc->ctx->dmub_srv)
 425                 return;
 426
 427         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 428                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
 429
 430                 if (pipe_ctx->stream && pipe_ctx->stream->mall_stream_config.paired_stream &&
 431                                 pipe_ctx->stream->mall_stream_config.type == SUBVP_MAIN) {
 432                         // There is at least 1 SubVP pipe, so enable SubVP
 433                         enable_subvp = true;
 434                         break;
 435                 }
 436         }
 437         dc_dmub_setup_subvp_dmub_command(dc, context, enable_subvp);
 438 */
 439 }
 440
 441 /* Sub-Viewport DMUB lock needs to be acquired by driver whenever SubVP is active and:
 442  * 1. Any full update for any SubVP main pipe
 443  * 2. Any immediate flip for any SubVP pipe
 444  * 3. Any flip for DRR pipe
 445  * 4. If SubVP was previously in use (i.e. in old context)
 446  */
 447 void dcn32_subvp_pipe_control_lock(struct dc *dc,
 448                 struct dc_state *context,
 449                 bool lock,
 450                 bool should_lock_all_pipes,
 451                 struct pipe_ctx *top_pipe_to_program,
 452                 bool subvp_prev_use)
 453 {
 454         unsigned int i = 0;
 455         bool subvp_immediate_flip = false;
 456         bool subvp_in_use = false;
 457         struct pipe_ctx *pipe;
 458
 459         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 460                 pipe = &context->res_ctx.pipe_ctx[i];
 461
 462                 if (pipe->stream && pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
 463                         subvp_in_use = true;
 464                         break;
 465                 }
 466         }
 467
 468         if (top_pipe_to_program && top_pipe_to_program->stream && top_pipe_to_program->plane_state) {
 469                 if (top_pipe_to_program->stream->mall_stream_config.type == SUBVP_MAIN &&
 470                                 top_pipe_to_program->plane_state->flip_immediate)
 471                         subvp_immediate_flip = true;
 472         }
 473
 474         // Don't need to lock for DRR VSYNC flips -- FW will wait for DRR pending update cleared.
 475         if ((subvp_in_use && (should_lock_all_pipes || subvp_immediate_flip)) || (!subvp_in_use && subvp_prev_use)) {
 476                 union dmub_inbox0_cmd_lock_hw hw_lock_cmd = { 0 };
 477
 478                 if (!lock) {
 479                         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 480                                 pipe = &context->res_ctx.pipe_ctx[i];
 481                                 if (pipe->stream && pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_MAIN &&
 482                                                 should_lock_all_pipes)
 483                                         pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VBLANK);
 484                         }
 485                 }
 486
 487                 hw_lock_cmd.bits.command_code = DMUB_INBOX0_CMD__HW_LOCK;
 488                 hw_lock_cmd.bits.hw_lock_client = HW_LOCK_CLIENT_DRIVER;
 489                 hw_lock_cmd.bits.lock = lock;
 490                 hw_lock_cmd.bits.should_release = !lock;
 491                 dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd);
 492         }
 493 }
 494
 495
 496 static bool dcn32_set_mpc_shaper_3dlut(
 497         struct pipe_ctx *pipe_ctx, const struct dc_stream_state *stream)
 498 {
 499         struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
 500         int mpcc_id = pipe_ctx->plane_res.hubp->inst;
 501         struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
 502         bool result = false;
 503
 504         const struct pwl_params *shaper_lut = NULL;
 505         //get the shaper lut params
 506         if (stream->func_shaper) {
 507                 if (stream->func_shaper->type == TF_TYPE_HWPWL)
 508                         shaper_lut = &stream->func_shaper->pwl;
 509                 else if (stream->func_shaper->type == TF_TYPE_DISTRIBUTED_POINTS) {
 510                         cm_helper_translate_curve_to_hw_format(
 511                                         stream->func_shaper,
 512                                         &dpp_base->shaper_params, true);
 513                         shaper_lut = &dpp_base->shaper_params;
 514                 }
 515         }
 516
 517         if (stream->lut3d_func &&
 518                 stream->lut3d_func->state.bits.initialized == 1) {
 519
 520                 result = mpc->funcs->program_3dlut(mpc,
 521                                                                 &stream->lut3d_func->lut_3d,
 522                                                                 mpcc_id);
 523
 524                 result = mpc->funcs->program_shaper(mpc,
 525                                                                 shaper_lut,
 526                                                                 mpcc_id);
 527         }
 528
 529         return result;
 530 }
 531
 532 bool dcn32_set_mcm_luts(
 533         struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
 534 {
 535         struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
 536         int mpcc_id = pipe_ctx->plane_res.hubp->inst;
 537         struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
 538         bool result = true;
 539         struct pwl_params *lut_params = NULL;
 540
 541         // 1D LUT
 542         if (plane_state->blend_tf) {
 543                 if (plane_state->blend_tf->type == TF_TYPE_HWPWL)
 544                         lut_params = &plane_state->blend_tf->pwl;
 545                 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) {
 546                         cm_helper_translate_curve_to_hw_format(
 547                                         plane_state->blend_tf,
 548                                         &dpp_base->regamma_params, false);
 549                         lut_params = &dpp_base->regamma_params;
 550                 }
 551         }
 552         result = mpc->funcs->program_1dlut(mpc, lut_params, mpcc_id);
 553
 554         // Shaper
 555         if (plane_state->in_shaper_func) {
 556                 if (plane_state->in_shaper_func->type == TF_TYPE_HWPWL)
 557                         lut_params = &plane_state->in_shaper_func->pwl;
 558                 else if (plane_state->in_shaper_func->type == TF_TYPE_DISTRIBUTED_POINTS) {
 559                         // TODO: dpp_base replace
 560                         ASSERT(false);
 561                         cm_helper_translate_curve_to_hw_format(
 562                                         plane_state->in_shaper_func,
 563                                         &dpp_base->shaper_params, true);
 564                         lut_params = &dpp_base->shaper_params;
 565                 }
 566         }
 567
 568         result = mpc->funcs->program_shaper(mpc, lut_params, mpcc_id);
 569
 570         // 3D
 571         if (plane_state->lut3d_func && plane_state->lut3d_func->state.bits.initialized == 1)
 572                 result = mpc->funcs->program_3dlut(mpc, &plane_state->lut3d_func->lut_3d, mpcc_id);
 573         else
 574                 result = mpc->funcs->program_3dlut(mpc, NULL, mpcc_id);
 575
 576         return result;
 577 }
 578
 579 bool dcn32_set_input_transfer_func(struct dc *dc,
 580                                 struct pipe_ctx *pipe_ctx,
 581                                 const struct dc_plane_state *plane_state)
 582 {
 583         struct dce_hwseq *hws = dc->hwseq;
 584         struct mpc *mpc = dc->res_pool->mpc;
 585         struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
 586
 587         enum dc_transfer_func_predefined tf;
 588         bool result = true;
 589         struct pwl_params *params = NULL;
 590
 591         if (mpc == NULL || plane_state == NULL)
 592                 return false;
 593
 594         tf = TRANSFER_FUNCTION_UNITY;
 595
 596         if (plane_state->in_transfer_func &&
 597                 plane_state->in_transfer_func->type == TF_TYPE_PREDEFINED)
 598                 tf = plane_state->in_transfer_func->tf;
 599
 600         dpp_base->funcs->dpp_set_pre_degam(dpp_base, tf);
 601
 602         if (plane_state->in_transfer_func) {
 603                 if (plane_state->in_transfer_func->type == TF_TYPE_HWPWL)
 604                         params = &plane_state->in_transfer_func->pwl;
 605                 else if (plane_state->in_transfer_func->type == TF_TYPE_DISTRIBUTED_POINTS &&
 606                         cm3_helper_translate_curve_to_hw_format(plane_state->in_transfer_func,
 607                                         &dpp_base->degamma_params, false))
 608                         params = &dpp_base->degamma_params;
 609         }
 610
 611         result = dpp_base->funcs->dpp_program_gamcor_lut(dpp_base, params);
 612
 613         if (result &&
 614                         pipe_ctx->stream_res.opp &&
 615                         pipe_ctx->stream_res.opp->ctx &&
 616                         hws->funcs.set_mcm_luts)
 617                 result = hws->funcs.set_mcm_luts(pipe_ctx, plane_state);
 618
 619         return result;
 620 }
 621
 622 bool dcn32_set_output_transfer_func(struct dc *dc,
 623                                 struct pipe_ctx *pipe_ctx,
 624                                 const struct dc_stream_state *stream)
 625 {
 626         int mpcc_id = pipe_ctx->plane_res.hubp->inst;
 627         struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
 628         struct pwl_params *params = NULL;
 629         bool ret = false;
 630
 631         /* program OGAM or 3DLUT only for the top pipe*/
 632         if (pipe_ctx->top_pipe == NULL) {
 633                 /*program shaper and 3dlut in MPC*/
 634                 ret = dcn32_set_mpc_shaper_3dlut(pipe_ctx, stream);
 635                 if (ret == false && mpc->funcs->set_output_gamma && stream->out_transfer_func) {
 636                         if (stream->out_transfer_func->type == TF_TYPE_HWPWL)
 637                                 params = &stream->out_transfer_func->pwl;
 638                         else if (pipe_ctx->stream->out_transfer_func->type ==
 639                                         TF_TYPE_DISTRIBUTED_POINTS &&
 640                                         cm3_helper_translate_curve_to_hw_format(
 641                                         stream->out_transfer_func,
 642                                         &mpc->blender_params, false))
 643                                 params = &mpc->blender_params;
 644                  /* there are no ROM LUTs in OUTGAM */
 645                 if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED)
 646                         BREAK_TO_DEBUGGER();
 647                 }
 648         }
 649
 650         mpc->funcs->set_output_gamma(mpc, mpcc_id, params);
 651         return ret;
 652 }
 653
 654 /* Program P-State force value according to if pipe is using SubVP or not:
 655  * 1. Reset P-State force on all pipes first
 656  * 2. For each main pipe, force P-State disallow (P-State allow moderated by DMUB)
 657  */
 658 void dcn32_subvp_update_force_pstate(struct dc *dc, struct dc_state *context)
 659 {
 660         int i;
 661         int num_subvp = 0;
 662         /* Unforce p-state for each pipe
 663          */
 664         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 665                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 666                 struct hubp *hubp = pipe->plane_res.hubp;
 667
 668                 if (hubp && hubp->funcs->hubp_update_force_pstate_disallow)
 669                         hubp->funcs->hubp_update_force_pstate_disallow(hubp, false);
 670                 if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_MAIN)
 671                         num_subvp++;
 672         }
 673
 674         if (num_subvp == 0)
 675                 return;
 676
 677         /* Loop through each pipe -- for each subvp main pipe force p-state allow equal to false.
 678          */
 679         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 680                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 681
 682                 // For SubVP + DRR, also force disallow on the DRR pipe
 683                 // (We will force allow in the DMUB sequence -- some DRR timings by default won't allow P-State so we have
 684                 // to force once the vblank is stretched).
 685                 if (pipe->stream && pipe->plane_state && (pipe->stream->mall_stream_config.type == SUBVP_MAIN ||
 686                                 (pipe->stream->mall_stream_config.type == SUBVP_NONE && pipe->stream->ignore_msa_timing_param))) {
 687                         struct hubp *hubp = pipe->plane_res.hubp;
 688
 689                         if (hubp && hubp->funcs->hubp_update_force_pstate_disallow)
 690                                 hubp->funcs->hubp_update_force_pstate_disallow(hubp, true);
 691                 }
 692         }
 693 }
 694
 695 /* Update MALL_SEL register based on if pipe / plane
 696  * is a phantom pipe, main pipe, and if using MALL
 697  * for SS.
 698  */
 699 void dcn32_update_mall_sel(struct dc *dc, struct dc_state *context)
 700 {
 701         int i;
 702         unsigned int num_ways = dcn32_calculate_cab_allocation(dc, context);
 703         bool cache_cursor = false;
 704
 705         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 706                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 707                 struct hubp *hubp = pipe->plane_res.hubp;
 708
 709                 if (pipe->stream && pipe->plane_state && hubp && hubp->funcs->hubp_update_mall_sel) {
 710                         if (hubp->curs_attr.width * hubp->curs_attr.height * 4 > 16384)
 711                                 cache_cursor = true;
 712
 713                         if (pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) {
 714                                         hubp->funcs->hubp_update_mall_sel(hubp, 1, false);
 715                         } else {
 716                                 // MALL not supported with Stereo3D
 717                                 hubp->funcs->hubp_update_mall_sel(hubp,
 718                                         num_ways <= dc->caps.cache_num_ways &&
 719                                         pipe->stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED &&
 720                                         pipe->plane_state->address.type !=  PLN_ADDR_TYPE_GRPH_STEREO ? 2 : 0,
 721                                                         cache_cursor);
 722                         }
 723                 }
 724         }
 725 }
 726
 727 /* Program the sub-viewport pipe configuration after the main / phantom pipes
 728  * have been programmed in hardware.
 729  * 1. Update force P-State for all the main pipes (disallow P-state)
 730  * 2. Update MALL_SEL register
 731  * 3. Program FORCE_ONE_ROW_FOR_FRAME for main subvp pipes
 732  */
 733 void dcn32_program_mall_pipe_config(struct dc *dc, struct dc_state *context)
 734 {
 735         int i;
 736         struct dce_hwseq *hws = dc->hwseq;
 737
 738         // Don't force p-state disallow -- can't block dummy p-state
 739
 740         // Update MALL_SEL register for each pipe
 741         if (hws && hws->funcs.update_mall_sel)
 742                 hws->funcs.update_mall_sel(dc, context);
 743
 744         // Program FORCE_ONE_ROW_FOR_FRAME and CURSOR_REQ_MODE for main subvp pipes
 745         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 746                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 747                 struct hubp *hubp = pipe->plane_res.hubp;
 748
 749                 if (pipe->stream && hubp && hubp->funcs->hubp_prepare_subvp_buffering) {
 750                         /* TODO - remove setting CURSOR_REQ_MODE to 0 for legacy cases
 751                          *      - need to investigate single pipe MPO + SubVP case to
 752                          *        see if CURSOR_REQ_MODE will be back to 1 for SubVP
 753                          *        when it should be 0 for MPO
 754                          */
 755                         if (pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
 756                                 hubp->funcs->hubp_prepare_subvp_buffering(hubp, true);
 757                         }
 758                 }
 759         }
 760 }
 761
 762 void dcn32_init_hw(struct dc *dc)
 763 {
 764         struct abm **abms = dc->res_pool->multiple_abms;
 765         struct dce_hwseq *hws = dc->hwseq;
 766         struct dc_bios *dcb = dc->ctx->dc_bios;
 767         struct resource_pool *res_pool = dc->res_pool;
 768         int i;
 769         int edp_num;
 770         uint32_t backlight = MAX_BACKLIGHT_LEVEL;
 771
 772         if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
 773                 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
 774
 775         // Initialize the dccg
 776         if (res_pool->dccg->funcs->dccg_init)
 777                 res_pool->dccg->funcs->dccg_init(res_pool->dccg);
 778
 779         if (!dcb->funcs->is_accelerated_mode(dcb)) {
 780                 hws->funcs.bios_golden_init(dc);
 781                 hws->funcs.disable_vga(dc->hwseq);
 782         }
 783
 784         // Set default OPTC memory power states
 785         if (dc->debug.enable_mem_low_power.bits.optc) {
 786                 // Shutdown when unassigned and light sleep in VBLANK
 787                 REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1);
 788         }
 789
 790         if (dc->debug.enable_mem_low_power.bits.vga) {
 791                 // Power down VGA memory
 792                 REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1);
 793         }
 794
 795         if (dc->ctx->dc_bios->fw_info_valid) {
 796                 res_pool->ref_clocks.xtalin_clock_inKhz =
 797                                 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
 798
 799                 if (res_pool->dccg && res_pool->hubbub) {
 800                         (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
 801                                         dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
 802                                         &res_pool->ref_clocks.dccg_ref_clock_inKhz);
 803
 804                         (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
 805                                         res_pool->ref_clocks.dccg_ref_clock_inKhz,
 806                                         &res_pool->ref_clocks.dchub_ref_clock_inKhz);
 807                 } else {
 808                         // Not all ASICs have DCCG sw component
 809                         res_pool->ref_clocks.dccg_ref_clock_inKhz =
 810                                         res_pool->ref_clocks.xtalin_clock_inKhz;
 811                         res_pool->ref_clocks.dchub_ref_clock_inKhz =
 812                                         res_pool->ref_clocks.xtalin_clock_inKhz;
 813                 }
 814         } else
 815                 ASSERT_CRITICAL(false);
 816
 817         for (i = 0; i < dc->link_count; i++) {
 818                 /* Power up AND update implementation according to the
 819                  * required signal (which may be different from the
 820                  * default signal on connector).
 821                  */
 822                 struct dc_link *link = dc->links[i];
 823
 824                 link->link_enc->funcs->hw_init(link->link_enc);
 825
 826                 /* Check for enabled DIG to identify enabled display */
 827                 if (link->link_enc->funcs->is_dig_enabled &&
 828                         link->link_enc->funcs->is_dig_enabled(link->link_enc)) {
 829                         link->link_status.link_active = true;
 830                         if (link->link_enc->funcs->fec_is_active &&
 831                                         link->link_enc->funcs->fec_is_active(link->link_enc))
 832                                 link->fec_state = dc_link_fec_enabled;
 833                 }
 834         }
 835
 836         /* Power gate DSCs */
 837         for (i = 0; i < res_pool->res_cap->num_dsc; i++)
 838                 if (hws->funcs.dsc_pg_control != NULL)
 839                         hws->funcs.dsc_pg_control(hws, res_pool->dscs[i]->inst, false);
 840
 841         /* we want to turn off all dp displays before doing detection */
 842         dc_link_blank_all_dp_displays(dc);
 843
 844         /* If taking control over from VBIOS, we may want to optimize our first
 845          * mode set, so we need to skip powering down pipes until we know which
 846          * pipes we want to use.
 847          * Otherwise, if taking control is not possible, we need to power
 848          * everything down.
 849          */
 850         if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) {
 851                 hws->funcs.init_pipes(dc, dc->current_state);
 852                 if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)
 853                         dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,
 854                                         !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);
 855         }
 856
 857         /* In headless boot cases, DIG may be turned
 858          * on which causes HW/SW discrepancies.
 859          * To avoid this, power down hardware on boot
 860          * if DIG is turned on and seamless boot not enabled
 861          */
 862         if (!dc->config.seamless_boot_edp_requested) {
 863                 struct dc_link *edp_links[MAX_NUM_EDP];
 864                 struct dc_link *edp_link;
 865
 866                 get_edp_links(dc, edp_links, &edp_num);
 867                 if (edp_num) {
 868                         for (i = 0; i < edp_num; i++) {
 869                                 edp_link = edp_links[i];
 870                                 if (edp_link->link_enc->funcs->is_dig_enabled &&
 871                                                 edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) &&
 872                                                 dc->hwss.edp_backlight_control &&
 873                                                 dc->hwss.power_down &&
 874                                                 dc->hwss.edp_power_control) {
 875                                         dc->hwss.edp_backlight_control(edp_link, false);
 876                                         dc->hwss.power_down(dc);
 877                                         dc->hwss.edp_power_control(edp_link, false);
 878                                 }
 879                         }
 880                 } else {
 881                         for (i = 0; i < dc->link_count; i++) {
 882                                 struct dc_link *link = dc->links[i];
 883
 884                                 if (link->link_enc->funcs->is_dig_enabled &&
 885                                                 link->link_enc->funcs->is_dig_enabled(link->link_enc) &&
 886                                                 dc->hwss.power_down) {
 887                                         dc->hwss.power_down(dc);
 888                                         break;
 889                                 }
 890
 891                         }
 892                 }
 893         }
 894
 895         for (i = 0; i < res_pool->audio_count; i++) {
 896                 struct audio *audio = res_pool->audios[i];
 897
 898                 audio->funcs->hw_init(audio);
 899         }
 900
 901         for (i = 0; i < dc->link_count; i++) {
 902                 struct dc_link *link = dc->links[i];
 903
 904                 if (link->panel_cntl)
 905                         backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl);
 906         }
 907
 908         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 909                 if (abms[i] != NULL && abms[i]->funcs != NULL)
 910                         abms[i]->funcs->abm_init(abms[i], backlight);
 911         }
 912
 913         /* power AFMT HDMI memory TODO: may move to dis/en output save power*/
 914         REG_WRITE(DIO_MEM_PWR_CTRL, 0);
 915
 916         if (!dc->debug.disable_clock_gate) {
 917                 /* enable all DCN clock gating */
 918                 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
 919
 920                 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
 921
 922                 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
 923         }
 924         if (hws->funcs.enable_power_gating_plane)
 925                 hws->funcs.enable_power_gating_plane(dc->hwseq, true);
 926
 927         if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks)
 928                 dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);
 929
 930         if (dc->clk_mgr->funcs->notify_wm_ranges)
 931                 dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);
 932
 933         if (dc->clk_mgr->funcs->set_hard_max_memclk)
 934                 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
 935
 936         if (dc->res_pool->hubbub->funcs->force_pstate_change_control)
 937                 dc->res_pool->hubbub->funcs->force_pstate_change_control(
 938                                 dc->res_pool->hubbub, false, false);
 939
 940         if (dc->res_pool->hubbub->funcs->init_crb)
 941                 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);
 942
 943         // Get DMCUB capabilities
 944         if (dc->ctx->dmub_srv) {
 945                 dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv->dmub);
 946                 dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;
 947         }
 948 }
 949
 950 static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream,
 951                 int opp_cnt)
 952 {
 953         bool hblank_halved = optc2_is_two_pixels_per_containter(&stream->timing);
 954         int flow_ctrl_cnt;
 955
 956         if (opp_cnt >= 2)
 957                 hblank_halved = true;
 958
 959         flow_ctrl_cnt = stream->timing.h_total - stream->timing.h_addressable -
 960                         stream->timing.h_border_left -
 961                         stream->timing.h_border_right;
 962
 963         if (hblank_halved)
 964                 flow_ctrl_cnt /= 2;
 965
 966         /* ODM combine 4:1 case */
 967         if (opp_cnt == 4)
 968                 flow_ctrl_cnt /= 2;
 969
 970         return flow_ctrl_cnt;
 971 }
 972
 973 static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
 974 {
 975         struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;
 976         struct dc_stream_state *stream = pipe_ctx->stream;
 977         struct pipe_ctx *odm_pipe;
 978         int opp_cnt = 1;
 979
 980         ASSERT(dsc);
 981         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
 982                 opp_cnt++;
 983
 984         if (enable) {
 985                 struct dsc_config dsc_cfg;
 986                 struct dsc_optc_config dsc_optc_cfg;
 987                 enum optc_dsc_mode optc_dsc_mode;
 988
 989                 /* Enable DSC hw block */
 990                 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt;
 991                 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;
 992                 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
 993                 dsc_cfg.color_depth = stream->timing.display_color_depth;
 994                 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;
 995                 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
 996                 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0);
 997                 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
 998
 999                 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg);
1000                 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);
1001                 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
1002                         struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc;
1003
1004                         ASSERT(odm_dsc);
1005                         odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg);
1006                         odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst);
1007                 }
1008                 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt;
1009                 dsc_cfg.pic_width *= opp_cnt;
1010
1011                 optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED;
1012
1013                 /* Enable DSC in OPTC */
1014                 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst);
1015                 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg,
1016                                                         optc_dsc_mode,
1017                                                         dsc_optc_cfg.bytes_per_pixel,
1018                                                         dsc_optc_cfg.slice_width);
1019         } else {
1020                 /* disable DSC in OPTC */
1021                 pipe_ctx->stream_res.tg->funcs->set_dsc_config(
1022                                 pipe_ctx->stream_res.tg,
1023                                 OPTC_DSC_DISABLED, 0, 0);
1024
1025                 /* disable DSC block */
1026                 dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc);
1027                 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
1028                         ASSERT(odm_pipe->stream_res.dsc);
1029                         odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc);
1030                 }
1031         }
1032 }
1033
1034 /*
1035 * Given any pipe_ctx, return the total ODM combine factor, and optionally return
1036 * the OPPids which are used
1037 * */
1038 static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, unsigned int *opp_instances)
1039 {
1040         unsigned int opp_count = 1;
1041         struct pipe_ctx *odm_pipe;
1042
1043         /* First get to the top pipe */
1044         for (odm_pipe = pipe_ctx; odm_pipe->prev_odm_pipe; odm_pipe = odm_pipe->prev_odm_pipe)
1045                 ;
1046
1047         /* First pipe is always used */
1048         if (opp_instances)
1049                 opp_instances[0] = odm_pipe->stream_res.opp->inst;
1050
1051         /* Find and count odm pipes, if any */
1052         for (odm_pipe = odm_pipe->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
1053                 if (opp_instances)
1054                         opp_instances[opp_count] = odm_pipe->stream_res.opp->inst;
1055                 opp_count++;
1056         }
1057
1058         return opp_count;
1059 }
1060
1061 void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)
1062 {
1063         struct pipe_ctx *odm_pipe;
1064         int opp_cnt = 0;
1065         int opp_inst[MAX_PIPES] = {0};
1066         bool rate_control_2x_pclk = (pipe_ctx->stream->timing.flags.INTERLACE || optc2_is_two_pixels_per_containter(&pipe_ctx->stream->timing));
1067         struct mpc_dwb_flow_control flow_control;
1068         struct mpc *mpc = dc->res_pool->mpc;
1069         int i;
1070
1071         opp_cnt = get_odm_config(pipe_ctx, opp_inst);
1072
1073         if (opp_cnt > 1)
1074                 pipe_ctx->stream_res.tg->funcs->set_odm_combine(
1075                                 pipe_ctx->stream_res.tg,
1076                                 opp_inst, opp_cnt,
1077                                 &pipe_ctx->stream->timing);
1078         else
1079                 pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
1080                                 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
1081
1082         rate_control_2x_pclk = rate_control_2x_pclk || opp_cnt > 1;
1083         flow_control.flow_ctrl_mode = 0;
1084         flow_control.flow_ctrl_cnt0 = 0x80;
1085         flow_control.flow_ctrl_cnt1 = calc_mpc_flow_ctrl_cnt(pipe_ctx->stream, opp_cnt);
1086         if (mpc->funcs->set_out_rate_control) {
1087                 for (i = 0; i < opp_cnt; ++i) {
1088                         mpc->funcs->set_out_rate_control(
1089                                         mpc, opp_inst[i],
1090                                         true,
1091                                         rate_control_2x_pclk,
1092                                         &flow_control);
1093                 }
1094         }
1095
1096         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
1097                 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control(
1098                                 odm_pipe->stream_res.opp,
1099                                 true);
1100         }
1101
1102         // Don't program pixel clock after link is already enabled
1103 /*      if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
1104                         pipe_ctx->clock_source,
1105                         &pipe_ctx->stream_res.pix_clk_params,
1106                         &pipe_ctx->pll_settings)) {
1107                 BREAK_TO_DEBUGGER();
1108         }*/
1109
1110         if (pipe_ctx->stream_res.dsc)
1111                 update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC);
1112 }
1113
1114 unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div)
1115 {
1116         struct dc_stream_state *stream = pipe_ctx->stream;
1117         unsigned int odm_combine_factor = 0;
1118         struct dc *dc = pipe_ctx->stream->ctx->dc;
1119         bool two_pix_per_container = false;
1120
1121         // For phantom pipes, use the same programming as the main pipes
1122         if (pipe_ctx->stream->mall_stream_config.type == SUBVP_PHANTOM) {
1123                 stream = pipe_ctx->stream->mall_stream_config.paired_stream;
1124         }
1125         two_pix_per_container = optc2_is_two_pixels_per_containter(&stream->timing);
1126         odm_combine_factor = get_odm_config(pipe_ctx, NULL);
1127
1128         if (is_dp_128b_132b_signal(pipe_ctx)) {
1129                 *k2_div = PIXEL_RATE_DIV_BY_1;
1130         } else if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) || dc_is_dvi_signal(pipe_ctx->stream->signal)) {
1131                 *k1_div = PIXEL_RATE_DIV_BY_1;
1132                 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
1133                         *k2_div = PIXEL_RATE_DIV_BY_2;
1134                 else
1135                         *k2_div = PIXEL_RATE_DIV_BY_4;
1136         } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
1137                 if (two_pix_per_container) {
1138                         *k1_div = PIXEL_RATE_DIV_BY_1;
1139                         *k2_div = PIXEL_RATE_DIV_BY_2;
1140                 } else {
1141                         *k1_div = PIXEL_RATE_DIV_BY_1;
1142                         *k2_div = PIXEL_RATE_DIV_BY_4;
1143                         if ((odm_combine_factor == 2) || dc->debug.enable_dp_dig_pixel_rate_div_policy)
1144                                 *k2_div = PIXEL_RATE_DIV_BY_2;
1145                 }
1146         }
1147
1148         if ((*k1_div == PIXEL_RATE_DIV_NA) && (*k2_div == PIXEL_RATE_DIV_NA))
1149                 ASSERT(false);
1150
1151         return odm_combine_factor;
1152 }
1153
1154 void dcn32_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx)
1155 {
1156         uint32_t pix_per_cycle = 1;
1157         uint32_t odm_combine_factor = 1;
1158
1159         if (!pipe_ctx || !pipe_ctx->stream || !pipe_ctx->stream_res.stream_enc)
1160                 return;
1161
1162         odm_combine_factor = get_odm_config(pipe_ctx, NULL);
1163         if (optc2_is_two_pixels_per_containter(&pipe_ctx->stream->timing) || odm_combine_factor > 1
1164                 || dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx))
1165                 pix_per_cycle = 2;
1166
1167         if (pipe_ctx->stream_res.stream_enc->funcs->set_input_mode)
1168                 pipe_ctx->stream_res.stream_enc->funcs->set_input_mode(pipe_ctx->stream_res.stream_enc,
1169                                 pix_per_cycle);
1170 }
1171
1172 void dcn32_unblank_stream(struct pipe_ctx *pipe_ctx,
1173                 struct dc_link_settings *link_settings)
1174 {
1175         struct encoder_unblank_param params = {0};
1176         struct dc_stream_state *stream = pipe_ctx->stream;
1177         struct dc_link *link = stream->link;
1178         struct dce_hwseq *hws = link->dc->hwseq;
1179         struct pipe_ctx *odm_pipe;
1180         struct dc *dc = pipe_ctx->stream->ctx->dc;
1181         uint32_t pix_per_cycle = 1;
1182
1183         params.opp_cnt = 1;
1184         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
1185                 params.opp_cnt++;
1186
1187         /* only 3 items below are used by unblank */
1188         params.timing = pipe_ctx->stream->timing;
1189
1190         params.link_settings.link_rate = link_settings->link_rate;
1191
1192         if (is_dp_128b_132b_signal(pipe_ctx)) {
1193                 /* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */
1194                 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_unblank(
1195                                 pipe_ctx->stream_res.hpo_dp_stream_enc,
1196                                 pipe_ctx->stream_res.tg->inst);
1197         } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
1198                 if (optc2_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt > 1
1199                         || dc->debug.enable_dp_dig_pixel_rate_div_policy) {
1200                         params.timing.pix_clk_100hz /= 2;
1201                         pix_per_cycle = 2;
1202                 }
1203                 pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine(
1204                                 pipe_ctx->stream_res.stream_enc, pix_per_cycle > 1);
1205                 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, &params);
1206         }
1207
1208         if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP)
1209                 hws->funcs.edp_backlight_control(link, true);
1210 }
1211
1212 bool dcn32_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx)
1213 {
1214         struct dc *dc = pipe_ctx->stream->ctx->dc;
1215
1216         if (dc_is_dp_signal(pipe_ctx->stream->signal) && !is_dp_128b_132b_signal(pipe_ctx) &&
1217                 dc->debug.enable_dp_dig_pixel_rate_div_policy)
1218                 return true;
1219         return false;
1220 }