drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c

   1 /*
   2  * Copyright 2021 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26
  27 #include "dm_services.h"
  28 #include "dc.h"
  29
  30 #include "dcn31/dcn31_init.h"
  31
  32 #include "resource.h"
  33 #include "include/irq_service_interface.h"
  34 #include "dcn316_resource.h"
  35
  36 #include "dcn20/dcn20_resource.h"
  37 #include "dcn30/dcn30_resource.h"
  38 #include "dcn31/dcn31_resource.h"
  39
  40 #include "dcn10/dcn10_ipp.h"
  41 #include "dcn30/dcn30_hubbub.h"
  42 #include "dcn31/dcn31_hubbub.h"
  43 #include "dcn30/dcn30_mpc.h"
  44 #include "dcn31/dcn31_hubp.h"
  45 #include "irq/dcn31/irq_service_dcn31.h"
  46 #include "dcn30/dcn30_dpp.h"
  47 #include "dcn31/dcn31_optc.h"
  48 #include "dcn20/dcn20_hwseq.h"
  49 #include "dcn30/dcn30_hwseq.h"
  50 #include "dce110/dce110_hw_sequencer.h"
  51 #include "dcn30/dcn30_opp.h"
  52 #include "dcn20/dcn20_dsc.h"
  53 #include "dcn30/dcn30_vpg.h"
  54 #include "dcn30/dcn30_afmt.h"
  55 #include "dcn30/dcn30_dio_stream_encoder.h"
  56 #include "dcn31/dcn31_hpo_dp_stream_encoder.h"
  57 #include "dcn31/dcn31_hpo_dp_link_encoder.h"
  58 #include "dcn31/dcn31_apg.h"
  59 #include "dcn31/dcn31_dio_link_encoder.h"
  60 #include "dcn31/dcn31_vpg.h"
  61 #include "dcn31/dcn31_afmt.h"
  62 #include "dce/dce_clock_source.h"
  63 #include "dce/dce_audio.h"
  64 #include "dce/dce_hwseq.h"
  65 #include "clk_mgr.h"
  66 #include "virtual/virtual_stream_encoder.h"
  67 #include "dce110/dce110_resource.h"
  68 #include "dml/display_mode_vba.h"
  69 #include "dml/dcn31/dcn31_fpu.h"
  70 #include "dcn31/dcn31_dccg.h"
  71 #include "dcn10/dcn10_resource.h"
  72 #include "dcn31/dcn31_panel_cntl.h"
  73
  74 #include "dcn30/dcn30_dwb.h"
  75 #include "dcn30/dcn30_mmhubbub.h"
  76
  77 #include "dcn/dcn_3_1_6_offset.h"
  78 #include "dcn/dcn_3_1_6_sh_mask.h"
  79 #include "dpcs/dpcs_4_2_3_offset.h"
  80 #include "dpcs/dpcs_4_2_3_sh_mask.h"
  81
  82 #define regBIF_BX1_BIOS_SCRATCH_2                                                                       0x003a
  83 #define regBIF_BX1_BIOS_SCRATCH_2_BASE_IDX                                                              1
  84 #define regBIF_BX1_BIOS_SCRATCH_3                                                                       0x003b
  85 #define regBIF_BX1_BIOS_SCRATCH_3_BASE_IDX                                                              1
  86 #define regBIF_BX1_BIOS_SCRATCH_6                                                                       0x003e
  87 #define regBIF_BX1_BIOS_SCRATCH_6_BASE_IDX                                                              1
  88
  89 #define regDCHUBBUB_DEBUG_CTRL_0                                              0x04d6
  90 #define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX                                     2
  91 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT                               0x10
  92 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK                                 0x01FF0000L
  93
  94 #define DCN_BASE__INST0_SEG0                       0x00000012
  95 #define DCN_BASE__INST0_SEG1                       0x000000C0
  96 #define DCN_BASE__INST0_SEG2                       0x000034C0
  97 #define DCN_BASE__INST0_SEG3                       0x00009000
  98 #define DCN_BASE__INST0_SEG4                       0x02403C00
  99 #define DCN_BASE__INST0_SEG5                       0
 100
 101 #define DPCS_BASE__INST0_SEG0                      0x00000012
 102 #define DPCS_BASE__INST0_SEG1                      0x000000C0
 103 #define DPCS_BASE__INST0_SEG2                      0x000034C0
 104 #define DPCS_BASE__INST0_SEG3                      0x00009000
 105 #define DPCS_BASE__INST0_SEG4                      0x02403C00
 106 #define DPCS_BASE__INST0_SEG5                      0
 107
 108 #define NBIO_BASE__INST0_SEG0                      0x00000000
 109 #define NBIO_BASE__INST0_SEG1                      0x00000014
 110 #define NBIO_BASE__INST0_SEG2                      0x00000D20
 111 #define NBIO_BASE__INST0_SEG3                      0x00010400
 112 #define NBIO_BASE__INST0_SEG4                      0x0241B000
 113 #define NBIO_BASE__INST0_SEG5                      0x04040000
 114
 115 #include "reg_helper.h"
 116 #include "dce/dmub_abm.h"
 117 #include "dce/dmub_psr.h"
 118 #include "dce/dce_aux.h"
 119 #include "dce/dce_i2c.h"
 120
 121 #include "dml/dcn30/display_mode_vba_30.h"
 122 #include "vm_helper.h"
 123 #include "dcn20/dcn20_vmid.h"
 124
 125 #include "link_enc_cfg.h"
 126
 127 #define DCN3_16_MAX_DET_SIZE 384
 128 #define DCN3_16_MIN_COMPBUF_SIZE_KB 128
 129 #define DCN3_16_CRB_SEGMENT_SIZE_KB 64
 130
 131 enum dcn31_clk_src_array_id {
 132         DCN31_CLK_SRC_PLL0,
 133         DCN31_CLK_SRC_PLL1,
 134         DCN31_CLK_SRC_PLL2,
 135         DCN31_CLK_SRC_PLL3,
 136         DCN31_CLK_SRC_PLL4,
 137         DCN30_CLK_SRC_TOTAL
 138 };
 139
 140 /* begin *********************
 141  * macros to expend register list macro defined in HW object header file
 142  */
 143
 144 /* DCN */
 145 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
 146
 147 #define BASE(seg) BASE_INNER(seg)
 148
 149 #define SR(reg_name)\
 150                 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) +  \
 151                                         reg ## reg_name
 152
 153 #define SRI(reg_name, block, id)\
 154         .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 155                                         reg ## block ## id ## _ ## reg_name
 156
 157 #define SRI2(reg_name, block, id)\
 158         .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
 159                                         reg ## reg_name
 160
 161 #define SRIR(var_name, reg_name, block, id)\
 162         .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 163                                         reg ## block ## id ## _ ## reg_name
 164
 165 #define SRII(reg_name, block, id)\
 166         .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 167                                         reg ## block ## id ## _ ## reg_name
 168
 169 #define SRII_MPC_RMU(reg_name, block, id)\
 170         .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 171                                         reg ## block ## id ## _ ## reg_name
 172
 173 #define SRII_DWB(reg_name, temp_name, block, id)\
 174         .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
 175                                         reg ## block ## id ## _ ## temp_name
 176
 177 #define SF_DWB2(reg_name, block, id, field_name, post_fix)      \
 178         .field_name = reg_name ## __ ## field_name ## post_fix
 179
 180 #define DCCG_SRII(reg_name, block, id)\
 181         .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 182                                         reg ## block ## id ## _ ## reg_name
 183
 184 #define VUPDATE_SRII(reg_name, block, id)\
 185         .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
 186                                         reg ## reg_name ## _ ## block ## id
 187
 188 /* NBIO */
 189 #define NBIO_BASE_INNER(seg) \
 190         NBIO_BASE__INST0_SEG ## seg
 191
 192 #define NBIO_BASE(seg) \
 193         NBIO_BASE_INNER(seg)
 194
 195 #define NBIO_SR(reg_name)\
 196                 .reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \
 197                                         regBIF_BX1_ ## reg_name
 198
 199 static const struct bios_registers bios_regs = {
 200                 NBIO_SR(BIOS_SCRATCH_3),
 201                 NBIO_SR(BIOS_SCRATCH_6)
 202 };
 203
 204 #define clk_src_regs(index, pllid)\
 205 [index] = {\
 206         CS_COMMON_REG_LIST_DCN3_0(index, pllid),\
 207 }
 208
 209 static const struct dce110_clk_src_regs clk_src_regs[] = {
 210         clk_src_regs(0, A),
 211         clk_src_regs(1, B),
 212         clk_src_regs(2, C),
 213         clk_src_regs(3, D),
 214         clk_src_regs(4, E)
 215 };
 216
 217 static const struct dce110_clk_src_shift cs_shift = {
 218                 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
 219 };
 220
 221 static const struct dce110_clk_src_mask cs_mask = {
 222                 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
 223 };
 224
 225 #define abm_regs(id)\
 226 [id] = {\
 227                 ABM_DCN302_REG_LIST(id)\
 228 }
 229
 230 static const struct dce_abm_registers abm_regs[] = {
 231                 abm_regs(0),
 232                 abm_regs(1),
 233                 abm_regs(2),
 234                 abm_regs(3),
 235 };
 236
 237 static const struct dce_abm_shift abm_shift = {
 238                 ABM_MASK_SH_LIST_DCN30(__SHIFT)
 239 };
 240
 241 static const struct dce_abm_mask abm_mask = {
 242                 ABM_MASK_SH_LIST_DCN30(_MASK)
 243 };
 244
 245 #define audio_regs(id)\
 246 [id] = {\
 247                 AUD_COMMON_REG_LIST(id)\
 248 }
 249
 250 static const struct dce_audio_registers audio_regs[] = {
 251         audio_regs(0),
 252         audio_regs(1),
 253         audio_regs(2),
 254         audio_regs(3),
 255         audio_regs(4),
 256         audio_regs(5),
 257         audio_regs(6)
 258 };
 259
 260 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
 261                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
 262                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
 263                 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
 264
 265 static const struct dce_audio_shift audio_shift = {
 266                 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
 267 };
 268
 269 static const struct dce_audio_mask audio_mask = {
 270                 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
 271 };
 272
 273 #define vpg_regs(id)\
 274 [id] = {\
 275         VPG_DCN31_REG_LIST(id)\
 276 }
 277
 278 static const struct dcn31_vpg_registers vpg_regs[] = {
 279         vpg_regs(0),
 280         vpg_regs(1),
 281         vpg_regs(2),
 282         vpg_regs(3),
 283         vpg_regs(4),
 284         vpg_regs(5),
 285         vpg_regs(6),
 286         vpg_regs(7),
 287         vpg_regs(8),
 288         vpg_regs(9),
 289 };
 290
 291 static const struct dcn31_vpg_shift vpg_shift = {
 292         DCN31_VPG_MASK_SH_LIST(__SHIFT)
 293 };
 294
 295 static const struct dcn31_vpg_mask vpg_mask = {
 296         DCN31_VPG_MASK_SH_LIST(_MASK)
 297 };
 298
 299 #define afmt_regs(id)\
 300 [id] = {\
 301         AFMT_DCN31_REG_LIST(id)\
 302 }
 303
 304 static const struct dcn31_afmt_registers afmt_regs[] = {
 305         afmt_regs(0),
 306         afmt_regs(1),
 307         afmt_regs(2),
 308         afmt_regs(3),
 309         afmt_regs(4),
 310         afmt_regs(5)
 311 };
 312
 313 static const struct dcn31_afmt_shift afmt_shift = {
 314         DCN31_AFMT_MASK_SH_LIST(__SHIFT)
 315 };
 316
 317 static const struct dcn31_afmt_mask afmt_mask = {
 318         DCN31_AFMT_MASK_SH_LIST(_MASK)
 319 };
 320
 321
 322 #define apg_regs(id)\
 323 [id] = {\
 324         APG_DCN31_REG_LIST(id)\
 325 }
 326
 327 static const struct dcn31_apg_registers apg_regs[] = {
 328         apg_regs(0),
 329         apg_regs(1),
 330         apg_regs(2),
 331         apg_regs(3)
 332 };
 333
 334 static const struct dcn31_apg_shift apg_shift = {
 335         DCN31_APG_MASK_SH_LIST(__SHIFT)
 336 };
 337
 338 static const struct dcn31_apg_mask apg_mask = {
 339                 DCN31_APG_MASK_SH_LIST(_MASK)
 340 };
 341
 342
 343 #define stream_enc_regs(id)\
 344 [id] = {\
 345         SE_DCN3_REG_LIST(id)\
 346 }
 347
 348 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
 349         stream_enc_regs(0),
 350         stream_enc_regs(1),
 351         stream_enc_regs(2),
 352         stream_enc_regs(3),
 353         stream_enc_regs(4)
 354 };
 355
 356 static const struct dcn10_stream_encoder_shift se_shift = {
 357                 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 358 };
 359
 360 static const struct dcn10_stream_encoder_mask se_mask = {
 361                 SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
 362 };
 363
 364
 365 #define aux_regs(id)\
 366 [id] = {\
 367         DCN2_AUX_REG_LIST(id)\
 368 }
 369
 370 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
 371                 aux_regs(0),
 372                 aux_regs(1),
 373                 aux_regs(2),
 374                 aux_regs(3),
 375                 aux_regs(4)
 376 };
 377
 378 #define hpd_regs(id)\
 379 [id] = {\
 380         HPD_REG_LIST(id)\
 381 }
 382
 383 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
 384                 hpd_regs(0),
 385                 hpd_regs(1),
 386                 hpd_regs(2),
 387                 hpd_regs(3),
 388                 hpd_regs(4)
 389 };
 390
 391 #define link_regs(id, phyid)\
 392 [id] = {\
 393         LE_DCN31_REG_LIST(id), \
 394         UNIPHY_DCN2_REG_LIST(phyid), \
 395         DPCS_DCN31_REG_LIST(id), \
 396 }
 397
 398 static const struct dce110_aux_registers_shift aux_shift = {
 399         DCN_AUX_MASK_SH_LIST(__SHIFT)
 400 };
 401
 402 static const struct dce110_aux_registers_mask aux_mask = {
 403         DCN_AUX_MASK_SH_LIST(_MASK)
 404 };
 405
 406 static const struct dcn10_link_enc_registers link_enc_regs[] = {
 407         link_regs(0, A),
 408         link_regs(1, B),
 409         link_regs(2, C),
 410         link_regs(3, D),
 411         link_regs(4, E)
 412 };
 413
 414 static const struct dcn10_link_enc_shift le_shift = {
 415         LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \
 416         DPCS_DCN31_MASK_SH_LIST(__SHIFT)
 417 };
 418
 419 static const struct dcn10_link_enc_mask le_mask = {
 420         LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \
 421         DPCS_DCN31_MASK_SH_LIST(_MASK)
 422 };
 423
 424
 425
 426 #define hpo_dp_stream_encoder_reg_list(id)\
 427 [id] = {\
 428         DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\
 429 }
 430
 431 static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = {
 432         hpo_dp_stream_encoder_reg_list(0),
 433         hpo_dp_stream_encoder_reg_list(1),
 434         hpo_dp_stream_encoder_reg_list(2),
 435         hpo_dp_stream_encoder_reg_list(3),
 436 };
 437
 438 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
 439         DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
 440 };
 441
 442 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
 443         DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
 444 };
 445
 446
 447 #define hpo_dp_link_encoder_reg_list(id)\
 448 [id] = {\
 449         DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\
 450         DCN3_1_RDPCSTX_REG_LIST(0),\
 451         DCN3_1_RDPCSTX_REG_LIST(1),\
 452         DCN3_1_RDPCSTX_REG_LIST(2),\
 453         DCN3_1_RDPCSTX_REG_LIST(3),\
 454         DCN3_1_RDPCSTX_REG_LIST(4)\
 455 }
 456
 457 static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = {
 458         hpo_dp_link_encoder_reg_list(0),
 459         hpo_dp_link_encoder_reg_list(1),
 460 };
 461
 462 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
 463         DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)
 464 };
 465
 466 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
 467         DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)
 468 };
 469
 470
 471 #define dpp_regs(id)\
 472 [id] = {\
 473         DPP_REG_LIST_DCN30(id),\
 474 }
 475
 476 static const struct dcn3_dpp_registers dpp_regs[] = {
 477         dpp_regs(0),
 478         dpp_regs(1),
 479         dpp_regs(2),
 480         dpp_regs(3)
 481 };
 482
 483 static const struct dcn3_dpp_shift tf_shift = {
 484                 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
 485 };
 486
 487 static const struct dcn3_dpp_mask tf_mask = {
 488                 DPP_REG_LIST_SH_MASK_DCN30(_MASK)
 489 };
 490
 491 #define opp_regs(id)\
 492 [id] = {\
 493         OPP_REG_LIST_DCN30(id),\
 494 }
 495
 496 static const struct dcn20_opp_registers opp_regs[] = {
 497         opp_regs(0),
 498         opp_regs(1),
 499         opp_regs(2),
 500         opp_regs(3)
 501 };
 502
 503 static const struct dcn20_opp_shift opp_shift = {
 504         OPP_MASK_SH_LIST_DCN20(__SHIFT)
 505 };
 506
 507 static const struct dcn20_opp_mask opp_mask = {
 508         OPP_MASK_SH_LIST_DCN20(_MASK)
 509 };
 510
 511 #define aux_engine_regs(id)\
 512 [id] = {\
 513         AUX_COMMON_REG_LIST0(id), \
 514         .AUXN_IMPCAL = 0, \
 515         .AUXP_IMPCAL = 0, \
 516         .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
 517 }
 518
 519 static const struct dce110_aux_registers aux_engine_regs[] = {
 520                 aux_engine_regs(0),
 521                 aux_engine_regs(1),
 522                 aux_engine_regs(2),
 523                 aux_engine_regs(3),
 524                 aux_engine_regs(4)
 525 };
 526
 527 #define dwbc_regs_dcn3(id)\
 528 [id] = {\
 529         DWBC_COMMON_REG_LIST_DCN30(id),\
 530 }
 531
 532 static const struct dcn30_dwbc_registers dwbc30_regs[] = {
 533         dwbc_regs_dcn3(0),
 534 };
 535
 536 static const struct dcn30_dwbc_shift dwbc30_shift = {
 537         DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 538 };
 539
 540 static const struct dcn30_dwbc_mask dwbc30_mask = {
 541         DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
 542 };
 543
 544 #define mcif_wb_regs_dcn3(id)\
 545 [id] = {\
 546         MCIF_WB_COMMON_REG_LIST_DCN30(id),\
 547 }
 548
 549 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
 550         mcif_wb_regs_dcn3(0)
 551 };
 552
 553 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
 554         MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 555 };
 556
 557 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
 558         MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
 559 };
 560
 561 #define dsc_regsDCN20(id)\
 562 [id] = {\
 563         DSC_REG_LIST_DCN20(id)\
 564 }
 565
 566 static const struct dcn20_dsc_registers dsc_regs[] = {
 567         dsc_regsDCN20(0),
 568         dsc_regsDCN20(1),
 569         dsc_regsDCN20(2)
 570 };
 571
 572 static const struct dcn20_dsc_shift dsc_shift = {
 573         DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
 574 };
 575
 576 static const struct dcn20_dsc_mask dsc_mask = {
 577         DSC_REG_LIST_SH_MASK_DCN20(_MASK)
 578 };
 579
 580 static const struct dcn30_mpc_registers mpc_regs = {
 581                 MPC_REG_LIST_DCN3_0(0),
 582                 MPC_REG_LIST_DCN3_0(1),
 583                 MPC_REG_LIST_DCN3_0(2),
 584                 MPC_REG_LIST_DCN3_0(3),
 585                 MPC_OUT_MUX_REG_LIST_DCN3_0(0),
 586                 MPC_OUT_MUX_REG_LIST_DCN3_0(1),
 587                 MPC_OUT_MUX_REG_LIST_DCN3_0(2),
 588                 MPC_OUT_MUX_REG_LIST_DCN3_0(3),
 589                 MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
 590                 MPC_RMU_REG_LIST_DCN3AG(0),
 591                 MPC_RMU_REG_LIST_DCN3AG(1),
 592                 //MPC_RMU_REG_LIST_DCN3AG(2),
 593                 MPC_DWB_MUX_REG_LIST_DCN3_0(0),
 594 };
 595
 596 static const struct dcn30_mpc_shift mpc_shift = {
 597         MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 598 };
 599
 600 static const struct dcn30_mpc_mask mpc_mask = {
 601         MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
 602 };
 603
 604 #define optc_regs(id)\
 605 [id] = {OPTC_COMMON_REG_LIST_DCN3_1(id)}
 606
 607 static const struct dcn_optc_registers optc_regs[] = {
 608         optc_regs(0),
 609         optc_regs(1),
 610         optc_regs(2),
 611         optc_regs(3)
 612 };
 613
 614 static const struct dcn_optc_shift optc_shift = {
 615         OPTC_COMMON_MASK_SH_LIST_DCN3_1(__SHIFT)
 616 };
 617
 618 static const struct dcn_optc_mask optc_mask = {
 619         OPTC_COMMON_MASK_SH_LIST_DCN3_1(_MASK)
 620 };
 621
 622 #define hubp_regs(id)\
 623 [id] = {\
 624         HUBP_REG_LIST_DCN30(id)\
 625 }
 626
 627 static const struct dcn_hubp2_registers hubp_regs[] = {
 628                 hubp_regs(0),
 629                 hubp_regs(1),
 630                 hubp_regs(2),
 631                 hubp_regs(3)
 632 };
 633
 634
 635 static const struct dcn_hubp2_shift hubp_shift = {
 636                 HUBP_MASK_SH_LIST_DCN31(__SHIFT)
 637 };
 638
 639 static const struct dcn_hubp2_mask hubp_mask = {
 640                 HUBP_MASK_SH_LIST_DCN31(_MASK)
 641 };
 642 static const struct dcn_hubbub_registers hubbub_reg = {
 643                 HUBBUB_REG_LIST_DCN31(0)
 644 };
 645
 646 static const struct dcn_hubbub_shift hubbub_shift = {
 647                 HUBBUB_MASK_SH_LIST_DCN31(__SHIFT)
 648 };
 649
 650 static const struct dcn_hubbub_mask hubbub_mask = {
 651                 HUBBUB_MASK_SH_LIST_DCN31(_MASK)
 652 };
 653
 654 static const struct dccg_registers dccg_regs = {
 655                 DCCG_REG_LIST_DCN31()
 656 };
 657
 658 static const struct dccg_shift dccg_shift = {
 659                 DCCG_MASK_SH_LIST_DCN31(__SHIFT)
 660 };
 661
 662 static const struct dccg_mask dccg_mask = {
 663                 DCCG_MASK_SH_LIST_DCN31(_MASK)
 664 };
 665
 666
 667 #define SRII2(reg_name_pre, reg_name_post, id)\
 668         .reg_name_pre ## _ ##  reg_name_post[id] = BASE(reg ## reg_name_pre \
 669                         ## id ## _ ## reg_name_post ## _BASE_IDX) + \
 670                         reg ## reg_name_pre ## id ## _ ## reg_name_post
 671
 672
 673 #define HWSEQ_DCN31_REG_LIST()\
 674         SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
 675         SR(DCHUBBUB_ARB_HOSTVM_CNTL), \
 676         SR(DIO_MEM_PWR_CTRL), \
 677         SR(ODM_MEM_PWR_CTRL3), \
 678         SR(DMU_MEM_PWR_CNTL), \
 679         SR(MMHUBBUB_MEM_PWR_CNTL), \
 680         SR(DCCG_GATE_DISABLE_CNTL), \
 681         SR(DCCG_GATE_DISABLE_CNTL2), \
 682         SR(DCFCLK_CNTL),\
 683         SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
 684         SRII(PIXEL_RATE_CNTL, OTG, 0), \
 685         SRII(PIXEL_RATE_CNTL, OTG, 1),\
 686         SRII(PIXEL_RATE_CNTL, OTG, 2),\
 687         SRII(PIXEL_RATE_CNTL, OTG, 3),\
 688         SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
 689         SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
 690         SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
 691         SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
 692         SR(MICROSECOND_TIME_BASE_DIV), \
 693         SR(MILLISECOND_TIME_BASE_DIV), \
 694         SR(DISPCLK_FREQ_CHANGE_CNTL), \
 695         SR(RBBMIF_TIMEOUT_DIS), \
 696         SR(RBBMIF_TIMEOUT_DIS_2), \
 697         SR(DCHUBBUB_CRC_CTRL), \
 698         SR(DPP_TOP0_DPP_CRC_CTRL), \
 699         SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
 700         SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
 701         SR(MPC_CRC_CTRL), \
 702         SR(MPC_CRC_RESULT_GB), \
 703         SR(MPC_CRC_RESULT_C), \
 704         SR(MPC_CRC_RESULT_AR), \
 705         SR(DOMAIN0_PG_CONFIG), \
 706         SR(DOMAIN1_PG_CONFIG), \
 707         SR(DOMAIN2_PG_CONFIG), \
 708         SR(DOMAIN3_PG_CONFIG), \
 709         SR(DOMAIN16_PG_CONFIG), \
 710         SR(DOMAIN17_PG_CONFIG), \
 711         SR(DOMAIN18_PG_CONFIG), \
 712         SR(DOMAIN0_PG_STATUS), \
 713         SR(DOMAIN1_PG_STATUS), \
 714         SR(DOMAIN2_PG_STATUS), \
 715         SR(DOMAIN3_PG_STATUS), \
 716         SR(DOMAIN16_PG_STATUS), \
 717         SR(DOMAIN17_PG_STATUS), \
 718         SR(DOMAIN18_PG_STATUS), \
 719         SR(D1VGA_CONTROL), \
 720         SR(D2VGA_CONTROL), \
 721         SR(D3VGA_CONTROL), \
 722         SR(D4VGA_CONTROL), \
 723         SR(D5VGA_CONTROL), \
 724         SR(D6VGA_CONTROL), \
 725         SR(DC_IP_REQUEST_CNTL), \
 726         SR(AZALIA_AUDIO_DTO), \
 727         SR(AZALIA_CONTROLLER_CLOCK_GATING), \
 728         SR(HPO_TOP_HW_CONTROL)
 729
 730 static const struct dce_hwseq_registers hwseq_reg = {
 731                 HWSEQ_DCN31_REG_LIST()
 732 };
 733
 734 #define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\
 735         HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
 736         HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
 737         HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \
 738         HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 739         HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 740         HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 741         HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 742         HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 743         HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 744         HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 745         HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 746         HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 747         HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 748         HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 749         HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 750         HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 751         HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 752         HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 753         HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 754         HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 755         HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 756         HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 757         HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 758         HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 759         HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
 760         HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
 761         HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
 762         HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \
 763         HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
 764         HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
 765         HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh), \
 766         HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \
 767         HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh)
 768
 769 static const struct dce_hwseq_shift hwseq_shift = {
 770                 HWSEQ_DCN31_MASK_SH_LIST(__SHIFT)
 771 };
 772
 773 static const struct dce_hwseq_mask hwseq_mask = {
 774                 HWSEQ_DCN31_MASK_SH_LIST(_MASK)
 775 };
 776 #define vmid_regs(id)\
 777 [id] = {\
 778                 DCN20_VMID_REG_LIST(id)\
 779 }
 780
 781 static const struct dcn_vmid_registers vmid_regs[] = {
 782         vmid_regs(0),
 783         vmid_regs(1),
 784         vmid_regs(2),
 785         vmid_regs(3),
 786         vmid_regs(4),
 787         vmid_regs(5),
 788         vmid_regs(6),
 789         vmid_regs(7),
 790         vmid_regs(8),
 791         vmid_regs(9),
 792         vmid_regs(10),
 793         vmid_regs(11),
 794         vmid_regs(12),
 795         vmid_regs(13),
 796         vmid_regs(14),
 797         vmid_regs(15)
 798 };
 799
 800 static const struct dcn20_vmid_shift vmid_shifts = {
 801                 DCN20_VMID_MASK_SH_LIST(__SHIFT)
 802 };
 803
 804 static const struct dcn20_vmid_mask vmid_masks = {
 805                 DCN20_VMID_MASK_SH_LIST(_MASK)
 806 };
 807
 808 static const struct resource_caps res_cap_dcn31 = {
 809         .num_timing_generator = 4,
 810         .num_opp = 4,
 811         .num_video_plane = 4,
 812         .num_audio = 5,
 813         .num_stream_encoder = 5,
 814         .num_dig_link_enc = 5,
 815         .num_hpo_dp_stream_encoder = 4,
 816         .num_hpo_dp_link_encoder = 2,
 817         .num_pll = 5,
 818         .num_dwb = 1,
 819         .num_ddc = 5,
 820         .num_vmid = 16,
 821         .num_mpc_3dlut = 2,
 822         .num_dsc = 3,
 823 };
 824
 825 static const struct dc_plane_cap plane_cap = {
 826         .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
 827         .per_pixel_alpha = true,
 828
 829         .pixel_format_support = {
 830                         .argb8888 = true,
 831                         .nv12 = true,
 832                         .fp16 = true,
 833                         .p010 = true,
 834                         .ayuv = false,
 835         },
 836
 837         .max_upscale_factor = {
 838                         .argb8888 = 16000,
 839                         .nv12 = 16000,
 840                         .fp16 = 16000
 841         },
 842
 843         // 6:1 downscaling ratio: 1000/6 = 166.666
 844         .max_downscale_factor = {
 845                         .argb8888 = 167,
 846                         .nv12 = 167,
 847                         .fp16 = 167
 848         },
 849         64,
 850         64
 851 };
 852
 853 static const struct dc_debug_options debug_defaults_drv = {
 854         .disable_z10 = true, /*hw not support it*/
 855         .disable_dmcu = true,
 856         .force_abm_enable = false,
 857         .timing_trace = false,
 858         .clock_trace = true,
 859         .disable_pplib_clock_request = false,
 860         .pipe_split_policy = MPC_SPLIT_DYNAMIC,
 861         .force_single_disp_pipe_split = false,
 862         .disable_dcc = DCC_ENABLE,
 863         .vsr_support = true,
 864         .performance_trace = false,
 865         .max_downscale_src_width = 4096,/*upto true 4k*/
 866         .disable_pplib_wm_range = false,
 867         .scl_reset_length10 = true,
 868         .sanity_checks = false,
 869         .underflow_assert_delay_us = 0xFFFFFFFF,
 870         .dwb_fi_phase = -1, // -1 = disable,
 871         .dmub_command_table = true,
 872         .pstate_enabled = true,
 873         .use_max_lb = true,
 874         .enable_mem_low_power = {
 875                 .bits = {
 876                         .vga = true,
 877                         .i2c = true,
 878                         .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
 879                         .dscl = true,
 880                         .cm = true,
 881                         .mpc = true,
 882                         .optc = true,
 883                         .vpg = true,
 884                         .afmt = true,
 885                 }
 886         },
 887 };
 888
 889 static const struct dc_panel_config panel_config_defaults = {
 890         .psr = {
 891                 .disable_psr = false,
 892                 .disallow_psrsu = false,
 893         },
 894         .ilr = {
 895                 .optimize_edp_link_rate = true,
 896         },
 897 };
 898
 899 static void dcn31_dpp_destroy(struct dpp **dpp)
 900 {
 901         kfree(TO_DCN20_DPP(*dpp));
 902         *dpp = NULL;
 903 }
 904
 905 static struct dpp *dcn31_dpp_create(
 906         struct dc_context *ctx,
 907         uint32_t inst)
 908 {
 909         struct dcn3_dpp *dpp =
 910                 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
 911
 912         if (!dpp)
 913                 return NULL;
 914
 915         if (dpp3_construct(dpp, ctx, inst,
 916                         &dpp_regs[inst], &tf_shift, &tf_mask))
 917                 return &dpp->base;
 918
 919         BREAK_TO_DEBUGGER();
 920         kfree(dpp);
 921         return NULL;
 922 }
 923
 924 static struct output_pixel_processor *dcn31_opp_create(
 925         struct dc_context *ctx, uint32_t inst)
 926 {
 927         struct dcn20_opp *opp =
 928                 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
 929
 930         if (!opp) {
 931                 BREAK_TO_DEBUGGER();
 932                 return NULL;
 933         }
 934
 935         dcn20_opp_construct(opp, ctx, inst,
 936                         &opp_regs[inst], &opp_shift, &opp_mask);
 937         return &opp->base;
 938 }
 939
 940 static struct dce_aux *dcn31_aux_engine_create(
 941         struct dc_context *ctx,
 942         uint32_t inst)
 943 {
 944         struct aux_engine_dce110 *aux_engine =
 945                 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
 946
 947         if (!aux_engine)
 948                 return NULL;
 949
 950         dce110_aux_engine_construct(aux_engine, ctx, inst,
 951                                     SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
 952                                     &aux_engine_regs[inst],
 953                                         &aux_mask,
 954                                         &aux_shift,
 955                                         ctx->dc->caps.extended_aux_timeout_support);
 956
 957         return &aux_engine->base;
 958 }
 959 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }
 960
 961 static const struct dce_i2c_registers i2c_hw_regs[] = {
 962                 i2c_inst_regs(1),
 963                 i2c_inst_regs(2),
 964                 i2c_inst_regs(3),
 965                 i2c_inst_regs(4),
 966                 i2c_inst_regs(5),
 967 };
 968
 969 static const struct dce_i2c_shift i2c_shifts = {
 970                 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 971 };
 972
 973 static const struct dce_i2c_mask i2c_masks = {
 974                 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
 975 };
 976
 977 static struct dce_i2c_hw *dcn31_i2c_hw_create(
 978         struct dc_context *ctx,
 979         uint32_t inst)
 980 {
 981         struct dce_i2c_hw *dce_i2c_hw =
 982                 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
 983
 984         if (!dce_i2c_hw)
 985                 return NULL;
 986
 987         dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
 988                                     &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
 989
 990         return dce_i2c_hw;
 991 }
 992 static struct mpc *dcn31_mpc_create(
 993                 struct dc_context *ctx,
 994                 int num_mpcc,
 995                 int num_rmu)
 996 {
 997         struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
 998                                           GFP_KERNEL);
 999
1000         if (!mpc30)
1001                 return NULL;
1002
1003         dcn30_mpc_construct(mpc30, ctx,
1004                         &mpc_regs,
1005                         &mpc_shift,
1006                         &mpc_mask,
1007                         num_mpcc,
1008                         num_rmu);
1009
1010         return &mpc30->base;
1011 }
1012
1013 static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx)
1014 {
1015         int i;
1016
1017         struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),
1018                                           GFP_KERNEL);
1019
1020         if (!hubbub3)
1021                 return NULL;
1022
1023         hubbub31_construct(hubbub3, ctx,
1024                         &hubbub_reg,
1025                         &hubbub_shift,
1026                         &hubbub_mask,
1027                         dcn3_16_ip.det_buffer_size_kbytes,
1028                         dcn3_16_ip.pixel_chunk_size_kbytes,
1029                         dcn3_16_ip.config_return_buffer_size_in_kbytes);
1030
1031
1032         for (i = 0; i < res_cap_dcn31.num_vmid; i++) {
1033                 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
1034
1035                 vmid->ctx = ctx;
1036
1037                 vmid->regs = &vmid_regs[i];
1038                 vmid->shifts = &vmid_shifts;
1039                 vmid->masks = &vmid_masks;
1040         }
1041
1042         return &hubbub3->base;
1043 }
1044
1045 static struct timing_generator *dcn31_timing_generator_create(
1046                 struct dc_context *ctx,
1047                 uint32_t instance)
1048 {
1049         struct optc *tgn10 =
1050                 kzalloc(sizeof(struct optc), GFP_KERNEL);
1051
1052         if (!tgn10)
1053                 return NULL;
1054
1055         tgn10->base.inst = instance;
1056         tgn10->base.ctx = ctx;
1057
1058         tgn10->tg_regs = &optc_regs[instance];
1059         tgn10->tg_shift = &optc_shift;
1060         tgn10->tg_mask = &optc_mask;
1061
1062         dcn31_timing_generator_init(tgn10);
1063
1064         return &tgn10->base;
1065 }
1066
1067 static const struct encoder_feature_support link_enc_feature = {
1068                 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1069                 .max_hdmi_pixel_clock = 600000,
1070                 .hdmi_ycbcr420_supported = true,
1071                 .dp_ycbcr420_supported = true,
1072                 .fec_supported = true,
1073                 .flags.bits.IS_HBR2_CAPABLE = true,
1074                 .flags.bits.IS_HBR3_CAPABLE = true,
1075                 .flags.bits.IS_TPS3_CAPABLE = true,
1076                 .flags.bits.IS_TPS4_CAPABLE = true
1077 };
1078
1079 static struct link_encoder *dcn31_link_encoder_create(
1080         struct dc_context *ctx,
1081         const struct encoder_init_data *enc_init_data)
1082 {
1083         struct dcn20_link_encoder *enc20 =
1084                 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1085
1086         if (!enc20)
1087                 return NULL;
1088
1089         dcn31_link_encoder_construct(enc20,
1090                         enc_init_data,
1091                         &link_enc_feature,
1092                         &link_enc_regs[enc_init_data->transmitter],
1093                         &link_enc_aux_regs[enc_init_data->channel - 1],
1094                         &link_enc_hpd_regs[enc_init_data->hpd_source],
1095                         &le_shift,
1096                         &le_mask);
1097
1098         return &enc20->enc10.base;
1099 }
1100
1101 /* Create a minimal link encoder object not associated with a particular
1102  * physical connector.
1103  * resource_funcs.link_enc_create_minimal
1104  */
1105 static struct link_encoder *dcn31_link_enc_create_minimal(
1106                 struct dc_context *ctx, enum engine_id eng_id)
1107 {
1108         struct dcn20_link_encoder *enc20;
1109
1110         if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
1111                 return NULL;
1112
1113         enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1114         if (!enc20)
1115                 return NULL;
1116
1117         dcn31_link_encoder_construct_minimal(
1118                         enc20,
1119                         ctx,
1120                         &link_enc_feature,
1121                         &link_enc_regs[eng_id - ENGINE_ID_DIGA],
1122                         eng_id);
1123
1124         return &enc20->enc10.base;
1125 }
1126
1127 static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1128 {
1129         struct dcn31_panel_cntl *panel_cntl =
1130                 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL);
1131
1132         if (!panel_cntl)
1133                 return NULL;
1134
1135         dcn31_panel_cntl_construct(panel_cntl, init_data);
1136
1137         return &panel_cntl->base;
1138 }
1139
1140 static void read_dce_straps(
1141         struct dc_context *ctx,
1142         struct resource_straps *straps)
1143 {
1144         generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),
1145                 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1146
1147 }
1148
1149 static struct audio *dcn31_create_audio(
1150                 struct dc_context *ctx, unsigned int inst)
1151 {
1152         return dce_audio_create(ctx, inst,
1153                         &audio_regs[inst], &audio_shift, &audio_mask);
1154 }
1155
1156 static struct vpg *dcn31_vpg_create(
1157         struct dc_context *ctx,
1158         uint32_t inst)
1159 {
1160         struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL);
1161
1162         if (!vpg31)
1163                 return NULL;
1164
1165         vpg31_construct(vpg31, ctx, inst,
1166                         &vpg_regs[inst],
1167                         &vpg_shift,
1168                         &vpg_mask);
1169
1170         return &vpg31->base;
1171 }
1172
1173 static struct afmt *dcn31_afmt_create(
1174         struct dc_context *ctx,
1175         uint32_t inst)
1176 {
1177         struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL);
1178
1179         if (!afmt31)
1180                 return NULL;
1181
1182         afmt31_construct(afmt31, ctx, inst,
1183                         &afmt_regs[inst],
1184                         &afmt_shift,
1185                         &afmt_mask);
1186
1187         // Light sleep by default, no need to power down here
1188
1189         return &afmt31->base;
1190 }
1191
1192
1193 static struct apg *dcn31_apg_create(
1194         struct dc_context *ctx,
1195         uint32_t inst)
1196 {
1197         struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL);
1198
1199         if (!apg31)
1200                 return NULL;
1201
1202         apg31_construct(apg31, ctx, inst,
1203                         &apg_regs[inst],
1204                         &apg_shift,
1205                         &apg_mask);
1206
1207         return &apg31->base;
1208 }
1209
1210
1211 static struct stream_encoder *dcn316_stream_encoder_create(
1212         enum engine_id eng_id,
1213         struct dc_context *ctx)
1214 {
1215         struct dcn10_stream_encoder *enc1;
1216         struct vpg *vpg;
1217         struct afmt *afmt;
1218         int vpg_inst;
1219         int afmt_inst;
1220
1221         /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1222         if (eng_id <= ENGINE_ID_DIGF) {
1223                 vpg_inst = eng_id;
1224                 afmt_inst = eng_id;
1225         } else
1226                 return NULL;
1227
1228         enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1229         vpg = dcn31_vpg_create(ctx, vpg_inst);
1230         afmt = dcn31_afmt_create(ctx, afmt_inst);
1231
1232         if (!enc1 || !vpg || !afmt) {
1233                 kfree(enc1);
1234                 kfree(vpg);
1235                 kfree(afmt);
1236                 return NULL;
1237         }
1238
1239         dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1240                                         eng_id, vpg, afmt,
1241                                         &stream_enc_regs[eng_id],
1242                                         &se_shift, &se_mask);
1243
1244         return &enc1->base;
1245 }
1246
1247
1248 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create(
1249         enum engine_id eng_id,
1250         struct dc_context *ctx)
1251 {
1252         struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1253         struct vpg *vpg;
1254         struct apg *apg;
1255         uint32_t hpo_dp_inst;
1256         uint32_t vpg_inst;
1257         uint32_t apg_inst;
1258
1259         ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1260         hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1261
1262         /* Mapping of VPG register blocks to HPO DP block instance:
1263          * VPG[6] -> HPO_DP[0]
1264          * VPG[7] -> HPO_DP[1]
1265          * VPG[8] -> HPO_DP[2]
1266          * VPG[9] -> HPO_DP[3]
1267          */
1268         vpg_inst = hpo_dp_inst + 6;
1269
1270         /* Mapping of APG register blocks to HPO DP block instance:
1271          * APG[0] -> HPO_DP[0]
1272          * APG[1] -> HPO_DP[1]
1273          * APG[2] -> HPO_DP[2]
1274          * APG[3] -> HPO_DP[3]
1275          */
1276         apg_inst = hpo_dp_inst;
1277
1278         /* allocate HPO stream encoder and create VPG sub-block */
1279         hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL);
1280         vpg = dcn31_vpg_create(ctx, vpg_inst);
1281         apg = dcn31_apg_create(ctx, apg_inst);
1282
1283         if (!hpo_dp_enc31 || !vpg || !apg) {
1284                 kfree(hpo_dp_enc31);
1285                 kfree(vpg);
1286                 kfree(apg);
1287                 return NULL;
1288         }
1289
1290         dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1291                                         hpo_dp_inst, eng_id, vpg, apg,
1292                                         &hpo_dp_stream_enc_regs[hpo_dp_inst],
1293                                         &hpo_dp_se_shift, &hpo_dp_se_mask);
1294
1295         return &hpo_dp_enc31->base;
1296 }
1297
1298 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create(
1299         uint8_t inst,
1300         struct dc_context *ctx)
1301 {
1302         struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1303
1304         /* allocate HPO link encoder */
1305         hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);
1306
1307         hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,
1308                                         &hpo_dp_link_enc_regs[inst],
1309                                         &hpo_dp_le_shift, &hpo_dp_le_mask);
1310
1311         return &hpo_dp_enc31->base;
1312 }
1313
1314
1315 static struct dce_hwseq *dcn31_hwseq_create(
1316         struct dc_context *ctx)
1317 {
1318         struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1319
1320         if (hws) {
1321                 hws->ctx = ctx;
1322                 hws->regs = &hwseq_reg;
1323                 hws->shifts = &hwseq_shift;
1324                 hws->masks = &hwseq_mask;
1325         }
1326         return hws;
1327 }
1328 static const struct resource_create_funcs res_create_funcs = {
1329         .read_dce_straps = read_dce_straps,
1330         .create_audio = dcn31_create_audio,
1331         .create_stream_encoder = dcn316_stream_encoder_create,
1332         .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,
1333         .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,
1334         .create_hwseq = dcn31_hwseq_create,
1335 };
1336
1337 static void dcn316_resource_destruct(struct dcn316_resource_pool *pool)
1338 {
1339         unsigned int i;
1340
1341         for (i = 0; i < pool->base.stream_enc_count; i++) {
1342                 if (pool->base.stream_enc[i] != NULL) {
1343                         if (pool->base.stream_enc[i]->vpg != NULL) {
1344                                 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1345                                 pool->base.stream_enc[i]->vpg = NULL;
1346                         }
1347                         if (pool->base.stream_enc[i]->afmt != NULL) {
1348                                 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1349                                 pool->base.stream_enc[i]->afmt = NULL;
1350                         }
1351                         kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1352                         pool->base.stream_enc[i] = NULL;
1353                 }
1354         }
1355
1356         for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1357                 if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1358                         if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1359                                 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1360                                 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1361                         }
1362                         if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1363                                 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1364                                 pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1365                         }
1366                         kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1367                         pool->base.hpo_dp_stream_enc[i] = NULL;
1368                 }
1369         }
1370
1371         for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1372                 if (pool->base.hpo_dp_link_enc[i] != NULL) {
1373                         kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1374                         pool->base.hpo_dp_link_enc[i] = NULL;
1375                 }
1376         }
1377
1378         for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1379                 if (pool->base.dscs[i] != NULL)
1380                         dcn20_dsc_destroy(&pool->base.dscs[i]);
1381         }
1382
1383         if (pool->base.mpc != NULL) {
1384                 kfree(TO_DCN20_MPC(pool->base.mpc));
1385                 pool->base.mpc = NULL;
1386         }
1387         if (pool->base.hubbub != NULL) {
1388                 kfree(pool->base.hubbub);
1389                 pool->base.hubbub = NULL;
1390         }
1391         for (i = 0; i < pool->base.pipe_count; i++) {
1392                 if (pool->base.dpps[i] != NULL)
1393                         dcn31_dpp_destroy(&pool->base.dpps[i]);
1394
1395                 if (pool->base.ipps[i] != NULL)
1396                         pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1397
1398                 if (pool->base.hubps[i] != NULL) {
1399                         kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1400                         pool->base.hubps[i] = NULL;
1401                 }
1402
1403                 if (pool->base.irqs != NULL) {
1404                         dal_irq_service_destroy(&pool->base.irqs);
1405                 }
1406         }
1407
1408         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1409                 if (pool->base.engines[i] != NULL)
1410                         dce110_engine_destroy(&pool->base.engines[i]);
1411                 if (pool->base.hw_i2cs[i] != NULL) {
1412                         kfree(pool->base.hw_i2cs[i]);
1413                         pool->base.hw_i2cs[i] = NULL;
1414                 }
1415                 if (pool->base.sw_i2cs[i] != NULL) {
1416                         kfree(pool->base.sw_i2cs[i]);
1417                         pool->base.sw_i2cs[i] = NULL;
1418                 }
1419         }
1420
1421         for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1422                 if (pool->base.opps[i] != NULL)
1423                         pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1424         }
1425
1426         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1427                 if (pool->base.timing_generators[i] != NULL)    {
1428                         kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1429                         pool->base.timing_generators[i] = NULL;
1430                 }
1431         }
1432
1433         for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1434                 if (pool->base.dwbc[i] != NULL) {
1435                         kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1436                         pool->base.dwbc[i] = NULL;
1437                 }
1438                 if (pool->base.mcif_wb[i] != NULL) {
1439                         kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1440                         pool->base.mcif_wb[i] = NULL;
1441                 }
1442         }
1443
1444         for (i = 0; i < pool->base.audio_count; i++) {
1445                 if (pool->base.audios[i])
1446                         dce_aud_destroy(&pool->base.audios[i]);
1447         }
1448
1449         for (i = 0; i < pool->base.clk_src_count; i++) {
1450                 if (pool->base.clock_sources[i] != NULL) {
1451                         dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1452                         pool->base.clock_sources[i] = NULL;
1453                 }
1454         }
1455
1456         for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1457                 if (pool->base.mpc_lut[i] != NULL) {
1458                         dc_3dlut_func_release(pool->base.mpc_lut[i]);
1459                         pool->base.mpc_lut[i] = NULL;
1460                 }
1461                 if (pool->base.mpc_shaper[i] != NULL) {
1462                         dc_transfer_func_release(pool->base.mpc_shaper[i]);
1463                         pool->base.mpc_shaper[i] = NULL;
1464                 }
1465         }
1466
1467         if (pool->base.dp_clock_source != NULL) {
1468                 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1469                 pool->base.dp_clock_source = NULL;
1470         }
1471
1472         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1473                 if (pool->base.multiple_abms[i] != NULL)
1474                         dce_abm_destroy(&pool->base.multiple_abms[i]);
1475         }
1476
1477         if (pool->base.psr != NULL)
1478                 dmub_psr_destroy(&pool->base.psr);
1479
1480         if (pool->base.dccg != NULL)
1481                 dcn_dccg_destroy(&pool->base.dccg);
1482 }
1483
1484 static struct hubp *dcn31_hubp_create(
1485         struct dc_context *ctx,
1486         uint32_t inst)
1487 {
1488         struct dcn20_hubp *hubp2 =
1489                 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1490
1491         if (!hubp2)
1492                 return NULL;
1493
1494         if (hubp31_construct(hubp2, ctx, inst,
1495                         &hubp_regs[inst], &hubp_shift, &hubp_mask))
1496                 return &hubp2->base;
1497
1498         BREAK_TO_DEBUGGER();
1499         kfree(hubp2);
1500         return NULL;
1501 }
1502
1503 static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1504 {
1505         int i;
1506         uint32_t pipe_count = pool->res_cap->num_dwb;
1507
1508         for (i = 0; i < pipe_count; i++) {
1509                 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1510                                                     GFP_KERNEL);
1511
1512                 if (!dwbc30) {
1513                         dm_error("DC: failed to create dwbc30!\n");
1514                         return false;
1515                 }
1516
1517                 dcn30_dwbc_construct(dwbc30, ctx,
1518                                 &dwbc30_regs[i],
1519                                 &dwbc30_shift,
1520                                 &dwbc30_mask,
1521                                 i);
1522
1523                 pool->dwbc[i] = &dwbc30->base;
1524         }
1525         return true;
1526 }
1527
1528 static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1529 {
1530         int i;
1531         uint32_t pipe_count = pool->res_cap->num_dwb;
1532
1533         for (i = 0; i < pipe_count; i++) {
1534                 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1535                                                     GFP_KERNEL);
1536
1537                 if (!mcif_wb30) {
1538                         dm_error("DC: failed to create mcif_wb30!\n");
1539                         return false;
1540                 }
1541
1542                 dcn30_mmhubbub_construct(mcif_wb30, ctx,
1543                                 &mcif_wb30_regs[i],
1544                                 &mcif_wb30_shift,
1545                                 &mcif_wb30_mask,
1546                                 i);
1547
1548                 pool->mcif_wb[i] = &mcif_wb30->base;
1549         }
1550         return true;
1551 }
1552
1553 static struct display_stream_compressor *dcn31_dsc_create(
1554         struct dc_context *ctx, uint32_t inst)
1555 {
1556         struct dcn20_dsc *dsc =
1557                 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1558
1559         if (!dsc) {
1560                 BREAK_TO_DEBUGGER();
1561                 return NULL;
1562         }
1563
1564         dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1565         return &dsc->base;
1566 }
1567
1568 static void dcn316_destroy_resource_pool(struct resource_pool **pool)
1569 {
1570         struct dcn316_resource_pool *dcn31_pool = TO_DCN316_RES_POOL(*pool);
1571
1572         dcn316_resource_destruct(dcn31_pool);
1573         kfree(dcn31_pool);
1574         *pool = NULL;
1575 }
1576
1577 static struct clock_source *dcn31_clock_source_create(
1578                 struct dc_context *ctx,
1579                 struct dc_bios *bios,
1580                 enum clock_source_id id,
1581                 const struct dce110_clk_src_regs *regs,
1582                 bool dp_clk_src)
1583 {
1584         struct dce110_clk_src *clk_src =
1585                 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1586
1587         if (!clk_src)
1588                 return NULL;
1589
1590         if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
1591                         regs, &cs_shift, &cs_mask)) {
1592                 clk_src->base.dp_clk_src = dp_clk_src;
1593                 return &clk_src->base;
1594         }
1595
1596         kfree(clk_src);
1597
1598         BREAK_TO_DEBUGGER();
1599         return NULL;
1600 }
1601
1602 static bool is_dual_plane(enum surface_pixel_format format)
1603 {
1604         return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA;
1605 }
1606
1607 static int dcn316_populate_dml_pipes_from_context(
1608         struct dc *dc, struct dc_state *context,
1609         display_e2e_pipe_params_st *pipes,
1610         bool fast_validate)
1611 {
1612         int i, pipe_cnt;
1613         struct resource_context *res_ctx = &context->res_ctx;
1614         struct pipe_ctx *pipe;
1615         const int max_usable_det = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes - DCN3_16_MIN_COMPBUF_SIZE_KB;
1616
1617         DC_FP_START();
1618         dcn31x_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
1619         DC_FP_END();
1620
1621         for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1622                 struct dc_crtc_timing *timing;
1623
1624                 if (!res_ctx->pipe_ctx[i].stream)
1625                         continue;
1626                 pipe = &res_ctx->pipe_ctx[i];
1627                 timing = &pipe->stream->timing;
1628
1629                 /*
1630                  * Immediate flip can be set dynamically after enabling the plane.
1631                  * We need to require support for immediate flip or underflow can be
1632                  * intermittently experienced depending on peak b/w requirements.
1633                  */
1634                 pipes[pipe_cnt].pipe.src.immediate_flip = true;
1635
1636                 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
1637                 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;
1638                 pipes[pipe_cnt].pipe.src.dcc_rate = 3;
1639                 pipes[pipe_cnt].dout.dsc_input_bpc = 0;
1640                 DC_FP_START();
1641                 dcn31_zero_pipe_dcc_fraction(pipes, pipe_cnt);
1642                 DC_FP_END();
1643
1644                 if (pipes[pipe_cnt].dout.dsc_enable) {
1645                         switch (timing->display_color_depth) {
1646                         case COLOR_DEPTH_888:
1647                                 pipes[pipe_cnt].dout.dsc_input_bpc = 8;
1648                                 break;
1649                         case COLOR_DEPTH_101010:
1650                                 pipes[pipe_cnt].dout.dsc_input_bpc = 10;
1651                                 break;
1652                         case COLOR_DEPTH_121212:
1653                                 pipes[pipe_cnt].dout.dsc_input_bpc = 12;
1654                                 break;
1655                         default:
1656                                 ASSERT(0);
1657                                 break;
1658                         }
1659                 }
1660
1661                 pipe_cnt++;
1662         }
1663
1664         if (pipe_cnt)
1665                 context->bw_ctx.dml.ip.det_buffer_size_kbytes =
1666                                 (max_usable_det / DCN3_16_CRB_SEGMENT_SIZE_KB / pipe_cnt) * DCN3_16_CRB_SEGMENT_SIZE_KB;
1667         if (context->bw_ctx.dml.ip.det_buffer_size_kbytes > DCN3_16_MAX_DET_SIZE)
1668                 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_16_MAX_DET_SIZE;
1669         ASSERT(context->bw_ctx.dml.ip.det_buffer_size_kbytes >= DCN3_16_DEFAULT_DET_SIZE);
1670         dc->config.enable_4to1MPC = false;
1671         if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) {
1672                 if (is_dual_plane(pipe->plane_state->format)
1673                                 && pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) {
1674                         dc->config.enable_4to1MPC = true;
1675                         context->bw_ctx.dml.ip.det_buffer_size_kbytes =
1676                                         (max_usable_det / DCN3_16_CRB_SEGMENT_SIZE_KB / 4) * DCN3_16_CRB_SEGMENT_SIZE_KB;
1677                 } else if (!is_dual_plane(pipe->plane_state->format)) {
1678                         context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;
1679                         pipes[0].pipe.src.unbounded_req_mode = true;
1680                 }
1681         }
1682
1683         return pipe_cnt;
1684 }
1685
1686 static void dcn316_get_panel_config_defaults(struct dc_panel_config *panel_config)
1687 {
1688         *panel_config = panel_config_defaults;
1689 }
1690
1691 static struct dc_cap_funcs cap_funcs = {
1692         .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1693 };
1694
1695 static struct resource_funcs dcn316_res_pool_funcs = {
1696         .destroy = dcn316_destroy_resource_pool,
1697         .link_enc_create = dcn31_link_encoder_create,
1698         .link_enc_create_minimal = dcn31_link_enc_create_minimal,
1699         .link_encs_assign = link_enc_cfg_link_encs_assign,
1700         .link_enc_unassign = link_enc_cfg_link_enc_unassign,
1701         .panel_cntl_create = dcn31_panel_cntl_create,
1702         .validate_bandwidth = dcn31_validate_bandwidth,
1703         .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg,
1704         .update_soc_for_wm_a = dcn31_update_soc_for_wm_a,
1705         .populate_dml_pipes = dcn316_populate_dml_pipes_from_context,
1706         .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
1707         .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1708         .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1709         .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1710         .populate_dml_writeback_from_context = dcn31_populate_dml_writeback_from_context,
1711         .set_mcif_arb_params = dcn31_set_mcif_arb_params,
1712         .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1713         .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1714         .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1715         .update_bw_bounding_box = dcn316_update_bw_bounding_box,
1716         .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1717         .get_panel_config_defaults = dcn316_get_panel_config_defaults,
1718 };
1719
1720 static bool dcn316_resource_construct(
1721         uint8_t num_virtual_links,
1722         struct dc *dc,
1723         struct dcn316_resource_pool *pool)
1724 {
1725         int i;
1726         struct dc_context *ctx = dc->ctx;
1727         struct irq_service_init_data init_data;
1728
1729         ctx->dc_bios->regs = &bios_regs;
1730
1731         pool->base.res_cap = &res_cap_dcn31;
1732
1733         pool->base.funcs = &dcn316_res_pool_funcs;
1734
1735         /*************************************************
1736          *  Resource + asic cap harcoding                *
1737          *************************************************/
1738         pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1739         pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1740         pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
1741         dc->caps.max_downscale_ratio = 600;
1742         dc->caps.i2c_speed_in_khz = 100;
1743         dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.5 w/a applied by default*/
1744         dc->caps.max_cursor_size = 256;
1745         dc->caps.min_horizontal_blanking_period = 80;
1746         dc->caps.dmdata_alloc_size = 2048;
1747         dc->caps.max_slave_planes = 2;
1748         dc->caps.max_slave_yuv_planes = 2;
1749         dc->caps.max_slave_rgb_planes = 2;
1750         dc->caps.post_blend_color_processing = true;
1751         dc->caps.force_dp_tps4_for_cp2520 = true;
1752         if (dc->config.forceHBR2CP2520)
1753                 dc->caps.force_dp_tps4_for_cp2520 = false;
1754         dc->caps.dp_hpo = true;
1755         dc->caps.dp_hdmi21_pcon_support = true;
1756         dc->caps.edp_dsc_support = true;
1757         dc->caps.extended_aux_timeout_support = true;
1758         dc->caps.dmcub_support = true;
1759         dc->caps.is_apu = true;
1760
1761         /* Color pipeline capabilities */
1762         dc->caps.color.dpp.dcn_arch = 1;
1763         dc->caps.color.dpp.input_lut_shared = 0;
1764         dc->caps.color.dpp.icsc = 1;
1765         dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1766         dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1767         dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1768         dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1769         dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1770         dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1771         dc->caps.color.dpp.post_csc = 1;
1772         dc->caps.color.dpp.gamma_corr = 1;
1773         dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1774
1775         dc->caps.color.dpp.hw_3d_lut = 1;
1776         dc->caps.color.dpp.ogam_ram = 1;
1777         // no OGAM ROM on DCN301
1778         dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1779         dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1780         dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1781         dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1782         dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1783         dc->caps.color.dpp.ocsc = 0;
1784
1785         dc->caps.color.mpc.gamut_remap = 1;
1786         dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
1787         dc->caps.color.mpc.ogam_ram = 1;
1788         dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1789         dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1790         dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1791         dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1792         dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1793         dc->caps.color.mpc.ocsc = 1;
1794
1795         /* read VBIOS LTTPR caps */
1796         {
1797                 if (ctx->dc_bios->funcs->get_lttpr_caps) {
1798                         enum bp_result bp_query_result;
1799                         uint8_t is_vbios_lttpr_enable = 0;
1800
1801                         bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1802                         dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1803                 }
1804
1805                 /* interop bit is implicit */
1806                 {
1807                         dc->caps.vbios_lttpr_aware = true;
1808                 }
1809         }
1810
1811         if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1812                 dc->debug = debug_defaults_drv;
1813
1814         // Init the vm_helper
1815         if (dc->vm_helper)
1816                 vm_helper_init(dc->vm_helper, 16);
1817
1818         /*************************************************
1819          *  Create resources                             *
1820          *************************************************/
1821
1822         /* Clock Sources for Pixel Clock*/
1823         pool->base.clock_sources[DCN31_CLK_SRC_PLL0] =
1824                         dcn31_clock_source_create(ctx, ctx->dc_bios,
1825                                 CLOCK_SOURCE_COMBO_PHY_PLL0,
1826                                 &clk_src_regs[0], false);
1827         pool->base.clock_sources[DCN31_CLK_SRC_PLL1] =
1828                         dcn31_clock_source_create(ctx, ctx->dc_bios,
1829                                 CLOCK_SOURCE_COMBO_PHY_PLL1,
1830                                 &clk_src_regs[1], false);
1831         pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =
1832                         dcn31_clock_source_create(ctx, ctx->dc_bios,
1833                                 CLOCK_SOURCE_COMBO_PHY_PLL2,
1834                                 &clk_src_regs[2], false);
1835         pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =
1836                         dcn31_clock_source_create(ctx, ctx->dc_bios,
1837                                 CLOCK_SOURCE_COMBO_PHY_PLL3,
1838                                 &clk_src_regs[3], false);
1839         pool->base.clock_sources[DCN31_CLK_SRC_PLL4] =
1840                         dcn31_clock_source_create(ctx, ctx->dc_bios,
1841                                 CLOCK_SOURCE_COMBO_PHY_PLL4,
1842                                 &clk_src_regs[4], false);
1843
1844         pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL;
1845
1846         /* todo: not reuse phy_pll registers */
1847         pool->base.dp_clock_source =
1848                         dcn31_clock_source_create(ctx, ctx->dc_bios,
1849                                 CLOCK_SOURCE_ID_DP_DTO,
1850                                 &clk_src_regs[0], true);
1851
1852         for (i = 0; i < pool->base.clk_src_count; i++) {
1853                 if (pool->base.clock_sources[i] == NULL) {
1854                         dm_error("DC: failed to create clock sources!\n");
1855                         BREAK_TO_DEBUGGER();
1856                         goto create_fail;
1857                 }
1858         }
1859
1860         /* TODO: DCCG */
1861         pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1862         if (pool->base.dccg == NULL) {
1863                 dm_error("DC: failed to create dccg!\n");
1864                 BREAK_TO_DEBUGGER();
1865                 goto create_fail;
1866         }
1867
1868         /* TODO: IRQ */
1869         init_data.ctx = dc->ctx;
1870         pool->base.irqs = dal_irq_service_dcn31_create(&init_data);
1871         if (!pool->base.irqs)
1872                 goto create_fail;
1873
1874         /* HUBBUB */
1875         pool->base.hubbub = dcn31_hubbub_create(ctx);
1876         if (pool->base.hubbub == NULL) {
1877                 BREAK_TO_DEBUGGER();
1878                 dm_error("DC: failed to create hubbub!\n");
1879                 goto create_fail;
1880         }
1881
1882         /* HUBPs, DPPs, OPPs and TGs */
1883         for (i = 0; i < pool->base.pipe_count; i++) {
1884                 pool->base.hubps[i] = dcn31_hubp_create(ctx, i);
1885                 if (pool->base.hubps[i] == NULL) {
1886                         BREAK_TO_DEBUGGER();
1887                         dm_error(
1888                                 "DC: failed to create hubps!\n");
1889                         goto create_fail;
1890                 }
1891
1892                 pool->base.dpps[i] = dcn31_dpp_create(ctx, i);
1893                 if (pool->base.dpps[i] == NULL) {
1894                         BREAK_TO_DEBUGGER();
1895                         dm_error(
1896                                 "DC: failed to create dpps!\n");
1897                         goto create_fail;
1898                 }
1899         }
1900
1901         for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1902                 pool->base.opps[i] = dcn31_opp_create(ctx, i);
1903                 if (pool->base.opps[i] == NULL) {
1904                         BREAK_TO_DEBUGGER();
1905                         dm_error(
1906                                 "DC: failed to create output pixel processor!\n");
1907                         goto create_fail;
1908                 }
1909         }
1910
1911         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1912                 pool->base.timing_generators[i] = dcn31_timing_generator_create(
1913                                 ctx, i);
1914                 if (pool->base.timing_generators[i] == NULL) {
1915                         BREAK_TO_DEBUGGER();
1916                         dm_error("DC: failed to create tg!\n");
1917                         goto create_fail;
1918                 }
1919         }
1920         pool->base.timing_generator_count = i;
1921
1922         /* PSR */
1923         pool->base.psr = dmub_psr_create(ctx);
1924         if (pool->base.psr == NULL) {
1925                 dm_error("DC: failed to create psr obj!\n");
1926                 BREAK_TO_DEBUGGER();
1927                 goto create_fail;
1928         }
1929
1930         /* ABM */
1931         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1932                 pool->base.multiple_abms[i] = dmub_abm_create(ctx,
1933                                 &abm_regs[i],
1934                                 &abm_shift,
1935                                 &abm_mask);
1936                 if (pool->base.multiple_abms[i] == NULL) {
1937                         dm_error("DC: failed to create abm for pipe %d!\n", i);
1938                         BREAK_TO_DEBUGGER();
1939                         goto create_fail;
1940                 }
1941         }
1942
1943         /* MPC and DSC */
1944         pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
1945         if (pool->base.mpc == NULL) {
1946                 BREAK_TO_DEBUGGER();
1947                 dm_error("DC: failed to create mpc!\n");
1948                 goto create_fail;
1949         }
1950
1951         for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1952                 pool->base.dscs[i] = dcn31_dsc_create(ctx, i);
1953                 if (pool->base.dscs[i] == NULL) {
1954                         BREAK_TO_DEBUGGER();
1955                         dm_error("DC: failed to create display stream compressor %d!\n", i);
1956                         goto create_fail;
1957                 }
1958         }
1959
1960         /* DWB and MMHUBBUB */
1961         if (!dcn31_dwbc_create(ctx, &pool->base)) {
1962                 BREAK_TO_DEBUGGER();
1963                 dm_error("DC: failed to create dwbc!\n");
1964                 goto create_fail;
1965         }
1966
1967         if (!dcn31_mmhubbub_create(ctx, &pool->base)) {
1968                 BREAK_TO_DEBUGGER();
1969                 dm_error("DC: failed to create mcif_wb!\n");
1970                 goto create_fail;
1971         }
1972
1973         /* AUX and I2C */
1974         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1975                 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i);
1976                 if (pool->base.engines[i] == NULL) {
1977                         BREAK_TO_DEBUGGER();
1978                         dm_error(
1979                                 "DC:failed to create aux engine!!\n");
1980                         goto create_fail;
1981                 }
1982                 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);
1983                 if (pool->base.hw_i2cs[i] == NULL) {
1984                         BREAK_TO_DEBUGGER();
1985                         dm_error(
1986                                 "DC:failed to create hw i2c!!\n");
1987                         goto create_fail;
1988                 }
1989                 pool->base.sw_i2cs[i] = NULL;
1990         }
1991
1992         /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
1993         if (!resource_construct(num_virtual_links, dc, &pool->base,
1994                         &res_create_funcs))
1995                 goto create_fail;
1996
1997         /* HW Sequencer and Plane caps */
1998         dcn31_hw_sequencer_construct(dc);
1999
2000         dc->caps.max_planes =  pool->base.pipe_count;
2001
2002         for (i = 0; i < dc->caps.max_planes; ++i)
2003                 dc->caps.planes[i] = plane_cap;
2004
2005         dc->cap_funcs = cap_funcs;
2006
2007         dc->dcn_ip->max_num_dpp = dcn3_16_ip.max_num_dpp;
2008
2009         return true;
2010
2011 create_fail:
2012
2013         dcn316_resource_destruct(pool);
2014
2015         return false;
2016 }
2017
2018 struct resource_pool *dcn316_create_resource_pool(
2019                 const struct dc_init_data *init_data,
2020                 struct dc *dc)
2021 {
2022         struct dcn316_resource_pool *pool =
2023                 kzalloc(sizeof(struct dcn316_resource_pool), GFP_KERNEL);
2024
2025         if (!pool)
2026                 return NULL;
2027
2028         if (dcn316_resource_construct(init_data->num_virtual_links, dc, pool))
2029                 return &pool->base;
2030
2031         BREAK_TO_DEBUGGER();
2032         kfree(pool);
2033         return NULL;
2034 }